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1f22fda7c55d3cee4e4439c3a129b64702b3d06b
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 #include "addrlib/gfx9/chip/gfx9_enum.h"
41
42 enum {
43 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
44 RADV_PREFETCH_VS = (1 << 1),
45 RADV_PREFETCH_TCS = (1 << 2),
46 RADV_PREFETCH_TES = (1 << 3),
47 RADV_PREFETCH_GS = (1 << 4),
48 RADV_PREFETCH_PS = (1 << 5),
49 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
50 RADV_PREFETCH_TCS |
51 RADV_PREFETCH_TES |
52 RADV_PREFETCH_GS |
53 RADV_PREFETCH_PS)
54 };
55
56 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
57 struct radv_image *image,
58 VkImageLayout src_layout,
59 VkImageLayout dst_layout,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 VkImageAspectFlags pending_clears);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111
112 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
113 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
114 src->viewport.count * sizeof(VkViewport))) {
115 typed_memcpy(dest->viewport.viewports,
116 src->viewport.viewports,
117 src->viewport.count);
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
123 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
124 src->scissor.count * sizeof(VkRect2D))) {
125 typed_memcpy(dest->scissor.scissors,
126 src->scissor.scissors, src->scissor.count);
127 dest_mask |= RADV_DYNAMIC_SCISSOR;
128 }
129 }
130
131 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
132 if (dest->line_width != src->line_width) {
133 dest->line_width = src->line_width;
134 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
135 }
136 }
137
138 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
139 if (memcmp(&dest->depth_bias, &src->depth_bias,
140 sizeof(src->depth_bias))) {
141 dest->depth_bias = src->depth_bias;
142 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
143 }
144 }
145
146 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
147 if (memcmp(&dest->blend_constants, &src->blend_constants,
148 sizeof(src->blend_constants))) {
149 typed_memcpy(dest->blend_constants,
150 src->blend_constants, 4);
151 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
152 }
153 }
154
155 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
156 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
157 sizeof(src->depth_bounds))) {
158 dest->depth_bounds = src->depth_bounds;
159 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
160 }
161 }
162
163 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
164 if (memcmp(&dest->stencil_compare_mask,
165 &src->stencil_compare_mask,
166 sizeof(src->stencil_compare_mask))) {
167 dest->stencil_compare_mask = src->stencil_compare_mask;
168 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
173 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
174 sizeof(src->stencil_write_mask))) {
175 dest->stencil_write_mask = src->stencil_write_mask;
176 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
177 }
178 }
179
180 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
181 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
182 sizeof(src->stencil_reference))) {
183 dest->stencil_reference = src->stencil_reference;
184 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
185 }
186 }
187
188 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
189 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
190 src->discard_rectangle.count * sizeof(VkRect2D))) {
191 typed_memcpy(dest->discard_rectangle.rectangles,
192 src->discard_rectangle.rectangles,
193 src->discard_rectangle.count);
194 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
195 }
196 }
197
198 cmd_buffer->state.dirty |= dest_mask;
199 }
200
201 static void
202 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
203 struct radv_pipeline *pipeline)
204 {
205 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
206 struct radv_shader_info *info;
207
208 if (!pipeline->streamout_shader)
209 return;
210
211 info = &pipeline->streamout_shader->info.info;
212 for (int i = 0; i < MAX_SO_BUFFERS; i++)
213 so->stride_in_dw[i] = info->so.strides[i];
214
215 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
216 }
217
218 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
219 {
220 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
221 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
222 }
223
224 enum ring_type radv_queue_family_to_ring(int f) {
225 switch (f) {
226 case RADV_QUEUE_GENERAL:
227 return RING_GFX;
228 case RADV_QUEUE_COMPUTE:
229 return RING_COMPUTE;
230 case RADV_QUEUE_TRANSFER:
231 return RING_DMA;
232 default:
233 unreachable("Unknown queue family");
234 }
235 }
236
237 static VkResult radv_create_cmd_buffer(
238 struct radv_device * device,
239 struct radv_cmd_pool * pool,
240 VkCommandBufferLevel level,
241 VkCommandBuffer* pCommandBuffer)
242 {
243 struct radv_cmd_buffer *cmd_buffer;
244 unsigned ring;
245 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
246 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
247 if (cmd_buffer == NULL)
248 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
249
250 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251 cmd_buffer->device = device;
252 cmd_buffer->pool = pool;
253 cmd_buffer->level = level;
254
255 if (pool) {
256 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
257 cmd_buffer->queue_family_index = pool->queue_family_index;
258
259 } else {
260 /* Init the pool_link so we can safely call list_del when we destroy
261 * the command buffer
262 */
263 list_inithead(&cmd_buffer->pool_link);
264 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
265 }
266
267 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
268
269 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
270 if (!cmd_buffer->cs) {
271 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
273 }
274
275 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
276
277 list_inithead(&cmd_buffer->upload.list);
278
279 return VK_SUCCESS;
280 }
281
282 static void
283 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
284 {
285 list_del(&cmd_buffer->pool_link);
286
287 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
288 &cmd_buffer->upload.list, list) {
289 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
290 list_del(&up->list);
291 free(up);
292 }
293
294 if (cmd_buffer->upload.upload_bo)
295 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
296 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
297
298 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
299 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
300
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 }
303
304 static VkResult
305 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
306 {
307
308 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 cmd_buffer->push_constant_stages = 0;
318 cmd_buffer->scratch_size_needed = 0;
319 cmd_buffer->compute_scratch_size_needed = 0;
320 cmd_buffer->esgs_ring_size_needed = 0;
321 cmd_buffer->gsvs_ring_size_needed = 0;
322 cmd_buffer->tess_rings_needed = false;
323 cmd_buffer->sample_positions_needed = false;
324
325 if (cmd_buffer->upload.upload_bo)
326 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
327 cmd_buffer->upload.upload_bo);
328 cmd_buffer->upload.offset = 0;
329
330 cmd_buffer->record_result = VK_SUCCESS;
331
332 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
333 cmd_buffer->descriptors[i].dirty = 0;
334 cmd_buffer->descriptors[i].valid = 0;
335 cmd_buffer->descriptors[i].push_dirty = false;
336 }
337
338 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
339 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
340 unsigned eop_bug_offset;
341 void *fence_ptr;
342
343 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
344 &cmd_buffer->gfx9_fence_offset,
345 &fence_ptr);
346 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT);
379
380 if (!bo) {
381 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
382 return false;
383 }
384
385 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
386 if (cmd_buffer->upload.upload_bo) {
387 upload = malloc(sizeof(*upload));
388
389 if (!upload) {
390 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
391 device->ws->buffer_destroy(bo);
392 return false;
393 }
394
395 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
396 list_add(&upload->list, &cmd_buffer->upload.list);
397 }
398
399 cmd_buffer->upload.upload_bo = bo;
400 cmd_buffer->upload.size = new_size;
401 cmd_buffer->upload.offset = 0;
402 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
403
404 if (!cmd_buffer->upload.map) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 return true;
410 }
411
412 bool
413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
414 unsigned size,
415 unsigned alignment,
416 unsigned *out_offset,
417 void **ptr)
418 {
419 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
420 if (offset + size > cmd_buffer->upload.size) {
421 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
422 return false;
423 offset = 0;
424 }
425
426 *out_offset = offset;
427 *ptr = cmd_buffer->upload.map + offset;
428
429 cmd_buffer->upload.offset = offset + size;
430 return true;
431 }
432
433 bool
434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
435 unsigned size, unsigned alignment,
436 const void *data, unsigned *out_offset)
437 {
438 uint8_t *ptr;
439
440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
441 out_offset, (void **)&ptr))
442 return false;
443
444 if (ptr)
445 memcpy(ptr, data, size);
446
447 return true;
448 }
449
450 static void
451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
452 unsigned count, const uint32_t *data)
453 {
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455
456 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
457
458 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
459 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
460 S_370_WR_CONFIRM(1) |
461 S_370_ENGINE_SEL(V_370_ME));
462 radeon_emit(cs, va);
463 radeon_emit(cs, va >> 32);
464 radeon_emit_array(cs, data, count);
465 }
466
467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
468 {
469 struct radv_device *device = cmd_buffer->device;
470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
471 uint64_t va;
472
473 va = radv_buffer_get_va(device->trace_bo);
474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
475 va += 4;
476
477 ++cmd_buffer->state.trace_id;
478 radv_emit_write_data_packet(cmd_buffer, va, 1,
479 &cmd_buffer->state.trace_id);
480
481 radeon_check_space(cmd_buffer->device->ws, cs, 2);
482
483 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
484 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
485 }
486
487 static void
488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
489 enum radv_cmd_flush_bits flags)
490 {
491 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
492 uint32_t *ptr = NULL;
493 uint64_t va = 0;
494
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
499 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
500 cmd_buffer->gfx9_fence_offset;
501 ptr = &cmd_buffer->gfx9_fence_idx;
502 }
503
504 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
505
506 /* Force wait for graphics or compute engines to be idle. */
507 si_cs_emit_cache_flush(cmd_buffer->cs,
508 cmd_buffer->device->physical_device->rad_info.chip_class,
509 ptr, va,
510 radv_cmd_buffer_uses_mec(cmd_buffer),
511 flags, cmd_buffer->gfx9_eop_bug_va);
512 }
513
514 if (unlikely(cmd_buffer->device->trace_bo))
515 radv_cmd_buffer_trace_emit(cmd_buffer);
516 }
517
518 static void
519 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
520 struct radv_pipeline *pipeline, enum ring_type ring)
521 {
522 struct radv_device *device = cmd_buffer->device;
523 uint32_t data[2];
524 uint64_t va;
525
526 va = radv_buffer_get_va(device->trace_bo);
527
528 switch (ring) {
529 case RING_GFX:
530 va += 8;
531 break;
532 case RING_COMPUTE:
533 va += 16;
534 break;
535 default:
536 assert(!"invalid ring type");
537 }
538
539 data[0] = (uintptr_t)pipeline;
540 data[1] = (uintptr_t)pipeline >> 32;
541
542 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
543 }
544
545 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
546 VkPipelineBindPoint bind_point,
547 struct radv_descriptor_set *set,
548 unsigned idx)
549 {
550 struct radv_descriptor_state *descriptors_state =
551 radv_get_descriptors_state(cmd_buffer, bind_point);
552
553 descriptors_state->sets[idx] = set;
554
555 descriptors_state->valid |= (1u << idx); /* active descriptors */
556 descriptors_state->dirty |= (1u << idx);
557 }
558
559 static void
560 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
561 VkPipelineBindPoint bind_point)
562 {
563 struct radv_descriptor_state *descriptors_state =
564 radv_get_descriptors_state(cmd_buffer, bind_point);
565 struct radv_device *device = cmd_buffer->device;
566 uint32_t data[MAX_SETS * 2] = {};
567 uint64_t va;
568 unsigned i;
569 va = radv_buffer_get_va(device->trace_bo) + 24;
570
571 for_each_bit(i, descriptors_state->valid) {
572 struct radv_descriptor_set *set = descriptors_state->sets[i];
573 data[i * 2] = (uintptr_t)set;
574 data[i * 2 + 1] = (uintptr_t)set >> 32;
575 }
576
577 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
578 }
579
580 struct radv_userdata_info *
581 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
582 gl_shader_stage stage,
583 int idx)
584 {
585 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
586 return &shader->info.user_sgprs_locs.shader_data[idx];
587 }
588
589 static void
590 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline,
592 gl_shader_stage stage,
593 int idx, uint64_t va)
594 {
595 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
596 uint32_t base_reg = pipeline->user_data_0[stage];
597 if (loc->sgpr_idx == -1)
598 return;
599
600 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
601 assert(!loc->indirect);
602
603 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
604 base_reg + loc->sgpr_idx * 4, va, false);
605 }
606
607 static void
608 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
609 struct radv_pipeline *pipeline,
610 struct radv_descriptor_state *descriptors_state,
611 gl_shader_stage stage)
612 {
613 struct radv_device *device = cmd_buffer->device;
614 struct radeon_cmdbuf *cs = cmd_buffer->cs;
615 uint32_t sh_base = pipeline->user_data_0[stage];
616 struct radv_userdata_locations *locs =
617 &pipeline->shaders[stage]->info.user_sgprs_locs;
618 unsigned mask = locs->descriptor_sets_enabled;
619
620 mask &= descriptors_state->dirty & descriptors_state->valid;
621
622 while (mask) {
623 int start, count;
624
625 u_bit_scan_consecutive_range(&mask, &start, &count);
626
627 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
628 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
629
630 radv_emit_shader_pointer_head(cs, sh_offset, count,
631 HAVE_32BIT_POINTERS);
632 for (int i = 0; i < count; i++) {
633 struct radv_descriptor_set *set =
634 descriptors_state->sets[start + i];
635
636 radv_emit_shader_pointer_body(device, cs, set->va,
637 HAVE_32BIT_POINTERS);
638 }
639 }
640 }
641
642 static void
643 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 int num_samples = pipeline->graphics.ms.num_samples;
647 struct radv_multisample_state *ms = &pipeline->graphics.ms;
648 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
649
650 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
651 cmd_buffer->sample_positions_needed = true;
652
653 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
654 return;
655
656 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
657 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
658 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
659
660 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
661
662 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
663
664 /* GFX9: Flush DFSM when the AA mode changes. */
665 if (cmd_buffer->device->dfsm_allowed) {
666 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
667 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
668 }
669 }
670
671 static void
672 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 uint64_t va;
676
677 if (!shader)
678 return;
679
680 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
681
682 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
683 }
684
685 static void
686 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
687 struct radv_pipeline *pipeline,
688 bool vertex_stage_only)
689 {
690 struct radv_cmd_state *state = &cmd_buffer->state;
691 uint32_t mask = state->prefetch_L2_mask;
692
693 if (vertex_stage_only) {
694 /* Fast prefetch path for starting draws as soon as possible.
695 */
696 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
697 RADV_PREFETCH_VBO_DESCRIPTORS);
698 }
699
700 if (mask & RADV_PREFETCH_VS)
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_VERTEX]);
703
704 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
705 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
706
707 if (mask & RADV_PREFETCH_TCS)
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
710
711 if (mask & RADV_PREFETCH_TES)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
714
715 if (mask & RADV_PREFETCH_GS) {
716 radv_emit_shader_prefetch(cmd_buffer,
717 pipeline->shaders[MESA_SHADER_GEOMETRY]);
718 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
719 }
720
721 if (mask & RADV_PREFETCH_PS)
722 radv_emit_shader_prefetch(cmd_buffer,
723 pipeline->shaders[MESA_SHADER_FRAGMENT]);
724
725 state->prefetch_L2_mask &= ~mask;
726 }
727
728 static void
729 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
730 {
731 if (!cmd_buffer->device->physical_device->rbplus_allowed)
732 return;
733
734 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
735 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
736 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
737
738 unsigned sx_ps_downconvert = 0;
739 unsigned sx_blend_opt_epsilon = 0;
740 unsigned sx_blend_opt_control = 0;
741
742 for (unsigned i = 0; i < subpass->color_count; ++i) {
743 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
744 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
745 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
746 continue;
747 }
748
749 int idx = subpass->color_attachments[i].attachment;
750 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
751
752 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
753 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
754 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
755 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
756
757 bool has_alpha, has_rgb;
758
759 /* Set if RGB and A are present. */
760 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
761
762 if (format == V_028C70_COLOR_8 ||
763 format == V_028C70_COLOR_16 ||
764 format == V_028C70_COLOR_32)
765 has_rgb = !has_alpha;
766 else
767 has_rgb = true;
768
769 /* Check the colormask and export format. */
770 if (!(colormask & 0x7))
771 has_rgb = false;
772 if (!(colormask & 0x8))
773 has_alpha = false;
774
775 if (spi_format == V_028714_SPI_SHADER_ZERO) {
776 has_rgb = false;
777 has_alpha = false;
778 }
779
780 /* Disable value checking for disabled channels. */
781 if (!has_rgb)
782 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
783 if (!has_alpha)
784 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
785
786 /* Enable down-conversion for 32bpp and smaller formats. */
787 switch (format) {
788 case V_028C70_COLOR_8:
789 case V_028C70_COLOR_8_8:
790 case V_028C70_COLOR_8_8_8_8:
791 /* For 1 and 2-channel formats, use the superset thereof. */
792 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
793 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
794 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
795 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
796 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
797 }
798 break;
799
800 case V_028C70_COLOR_5_6_5:
801 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
802 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
803 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
804 }
805 break;
806
807 case V_028C70_COLOR_1_5_5_5:
808 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
810 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
811 }
812 break;
813
814 case V_028C70_COLOR_4_4_4_4:
815 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
816 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
817 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
818 }
819 break;
820
821 case V_028C70_COLOR_32:
822 if (swap == V_028C70_SWAP_STD &&
823 spi_format == V_028714_SPI_SHADER_32_R)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
825 else if (swap == V_028C70_SWAP_ALT_REV &&
826 spi_format == V_028714_SPI_SHADER_32_AR)
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
828 break;
829
830 case V_028C70_COLOR_16:
831 case V_028C70_COLOR_16_16:
832 /* For 1-channel formats, use the superset thereof. */
833 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
834 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
835 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
836 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
837 if (swap == V_028C70_SWAP_STD ||
838 swap == V_028C70_SWAP_STD_REV)
839 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
840 else
841 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
842 }
843 break;
844
845 case V_028C70_COLOR_10_11_11:
846 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
847 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
848 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
849 }
850 break;
851
852 case V_028C70_COLOR_2_10_10_10:
853 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
854 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
855 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
856 }
857 break;
858 }
859 }
860
861 for (unsigned i = subpass->color_count; i < 8; ++i) {
862 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
863 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
864 }
865 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
866 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
867 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
868 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
869 }
870
871 static void
872 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
873 {
874 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
875
876 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
877 return;
878
879 radv_update_multisample_state(cmd_buffer, pipeline);
880
881 cmd_buffer->scratch_size_needed =
882 MAX2(cmd_buffer->scratch_size_needed,
883 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
884
885 if (!cmd_buffer->state.emitted_pipeline ||
886 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
887 pipeline->graphics.can_use_guardband)
888 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
889
890 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
891
892 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
893 if (!pipeline->shaders[i])
894 continue;
895
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->shaders[i]->bo);
898 }
899
900 if (radv_pipeline_has_gs(pipeline))
901 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
902 pipeline->gs_copy_shader->bo);
903
904 if (unlikely(cmd_buffer->device->trace_bo))
905 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
906
907 cmd_buffer->state.emitted_pipeline = pipeline;
908
909 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
910 }
911
912 static void
913 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
914 {
915 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
916 cmd_buffer->state.dynamic.viewport.viewports);
917 }
918
919 static void
920 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
921 {
922 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
923
924 si_write_scissors(cmd_buffer->cs, 0, count,
925 cmd_buffer->state.dynamic.scissor.scissors,
926 cmd_buffer->state.dynamic.viewport.viewports,
927 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
928 }
929
930 static void
931 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
932 {
933 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
934 return;
935
936 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
937 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
938 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
939 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
940 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
941 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
942 S_028214_BR_Y(rect.offset.y + rect.extent.height));
943 }
944 }
945
946 static void
947 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
948 {
949 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
952 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
953 }
954
955 static void
956 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
957 {
958 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
959
960 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
961 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
962 }
963
964 static void
965 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg_seq(cmd_buffer->cs,
970 R_028430_DB_STENCILREFMASK, 2);
971 radeon_emit(cmd_buffer->cs,
972 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
973 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
974 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
975 S_028430_STENCILOPVAL(1));
976 radeon_emit(cmd_buffer->cs,
977 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
978 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
979 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
980 S_028434_STENCILOPVAL_BF(1));
981 }
982
983 static void
984 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
985 {
986 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
989 fui(d->depth_bounds.min));
990 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
991 fui(d->depth_bounds.max));
992 }
993
994 static void
995 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
996 {
997 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
998 unsigned slope = fui(d->depth_bias.slope * 16.0f);
999 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1000
1001
1002 radeon_set_context_reg_seq(cmd_buffer->cs,
1003 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1004 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1005 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1006 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1007 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1008 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1009 }
1010
1011 static void
1012 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1013 int index,
1014 struct radv_attachment_info *att,
1015 struct radv_image *image,
1016 VkImageLayout layout)
1017 {
1018 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1019 struct radv_color_buffer_info *cb = &att->cb;
1020 uint32_t cb_color_info = cb->cb_color_info;
1021
1022 if (!radv_layout_dcc_compressed(image, layout,
1023 radv_image_queue_family_mask(image,
1024 cmd_buffer->queue_family_index,
1025 cmd_buffer->queue_family_index))) {
1026 cb_color_info &= C_028C70_DCC_ENABLE;
1027 }
1028
1029 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1030 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1032 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1035 radeon_emit(cmd_buffer->cs, cb_color_info);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1037 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1039 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1041 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1042
1043 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1044 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1045 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1046
1047 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1048 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1049 } else {
1050 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1052 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1055 radeon_emit(cmd_buffer->cs, cb_color_info);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1057 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1060 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1062
1063 if (is_vi) { /* DCC BASE */
1064 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1065 }
1066 }
1067 }
1068
1069 static void
1070 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_ds_buffer_info *ds,
1072 struct radv_image *image, VkImageLayout layout,
1073 bool requires_cond_write)
1074 {
1075 uint32_t db_z_info = ds->db_z_info;
1076 uint32_t db_z_info_reg;
1077
1078 if (!radv_image_is_tc_compat_htile(image))
1079 return;
1080
1081 if (!radv_layout_has_htile(image, layout,
1082 radv_image_queue_family_mask(image,
1083 cmd_buffer->queue_family_index,
1084 cmd_buffer->queue_family_index))) {
1085 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1086 }
1087
1088 db_z_info &= C_028040_ZRANGE_PRECISION;
1089
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 db_z_info_reg = R_028038_DB_Z_INFO;
1092 } else {
1093 db_z_info_reg = R_028040_DB_Z_INFO;
1094 }
1095
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet, otherwise we can update DB_Z_INFO directly.
1098 */
1099 if (requires_cond_write) {
1100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1101
1102 const uint32_t write_space = 0 << 8; /* register */
1103 const uint32_t poll_space = 1 << 4; /* memory */
1104 const uint32_t function = 3 << 0; /* equal to the reference */
1105 const uint32_t options = write_space | poll_space | function;
1106 radeon_emit(cmd_buffer->cs, options);
1107
1108 /* poll address - location of the depth clear value */
1109 uint64_t va = radv_buffer_get_va(image->bo);
1110 va += image->offset + image->clear_value_offset;
1111
1112 /* In presence of stencil format, we have to adjust the base
1113 * address because the first value is the stencil clear value.
1114 */
1115 if (vk_format_is_stencil(image->vk_format))
1116 va += 4;
1117
1118 radeon_emit(cmd_buffer->cs, va);
1119 radeon_emit(cmd_buffer->cs, va >> 32);
1120
1121 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1122 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1123 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1124 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1125 radeon_emit(cmd_buffer->cs, db_z_info);
1126 } else {
1127 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1128 }
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1190 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1191
1192 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1193 ds->pa_su_poly_offset_db_fmt_cntl);
1194 }
1195
1196 /**
1197 * Update the fast clear depth/stencil values if the image is bound as a
1198 * depth/stencil buffer.
1199 */
1200 static void
1201 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1202 struct radv_image *image,
1203 VkClearDepthStencilValue ds_clear_value,
1204 VkImageAspectFlags aspects)
1205 {
1206 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1207 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1208 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1209 struct radv_attachment_info *att;
1210 uint32_t att_idx;
1211
1212 if (!framebuffer || !subpass)
1213 return;
1214
1215 att_idx = subpass->depth_stencil_attachment.attachment;
1216 if (att_idx == VK_ATTACHMENT_UNUSED)
1217 return;
1218
1219 att = &framebuffer->attachments[att_idx];
1220 if (att->attachment->image != image)
1221 return;
1222
1223 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1224 radeon_emit(cs, ds_clear_value.stencil);
1225 radeon_emit(cs, fui(ds_clear_value.depth));
1226
1227 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1228 * only needed when clearing Z to 0.0.
1229 */
1230 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1231 ds_clear_value.depth == 0.0) {
1232 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1233
1234 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1235 layout, false);
1236 }
1237 }
1238
1239 /**
1240 * Set the clear depth/stencil values to the image's metadata.
1241 */
1242 static void
1243 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1244 struct radv_image *image,
1245 VkClearDepthStencilValue ds_clear_value,
1246 VkImageAspectFlags aspects)
1247 {
1248 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1249 uint64_t va = radv_buffer_get_va(image->bo);
1250 unsigned reg_offset = 0, reg_count = 0;
1251
1252 va += image->offset + image->clear_value_offset;
1253
1254 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1255 ++reg_count;
1256 } else {
1257 ++reg_offset;
1258 va += 4;
1259 }
1260 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1261 ++reg_count;
1262
1263 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1264 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1265 S_370_WR_CONFIRM(1) |
1266 S_370_ENGINE_SEL(V_370_PFP));
1267 radeon_emit(cs, va);
1268 radeon_emit(cs, va >> 32);
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1270 radeon_emit(cs, ds_clear_value.stencil);
1271 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1272 radeon_emit(cs, fui(ds_clear_value.depth));
1273 }
1274
1275 /**
1276 * Update the clear depth/stencil values for this image.
1277 */
1278 void
1279 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1280 struct radv_image *image,
1281 VkClearDepthStencilValue ds_clear_value,
1282 VkImageAspectFlags aspects)
1283 {
1284 assert(radv_image_has_htile(image));
1285
1286 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1287
1288 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1289 aspects);
1290 }
1291
1292 /**
1293 * Load the clear depth/stencil values from the image's metadata.
1294 */
1295 static void
1296 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_image *image)
1298 {
1299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1300 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1301 uint64_t va = radv_buffer_get_va(image->bo);
1302 unsigned reg_offset = 0, reg_count = 0;
1303
1304 va += image->offset + image->clear_value_offset;
1305
1306 if (!radv_image_has_htile(image))
1307 return;
1308
1309 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1310 ++reg_count;
1311 } else {
1312 ++reg_offset;
1313 va += 4;
1314 }
1315 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1316 ++reg_count;
1317
1318 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1319
1320 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1321 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1322 radeon_emit(cs, va);
1323 radeon_emit(cs, va >> 32);
1324 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1325 radeon_emit(cs, reg_count);
1326 } else {
1327 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1328 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1329 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1330 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1331 radeon_emit(cs, va);
1332 radeon_emit(cs, va >> 32);
1333 radeon_emit(cs, reg >> 2);
1334 radeon_emit(cs, 0);
1335
1336 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1337 radeon_emit(cs, 0);
1338 }
1339 }
1340
1341 /*
1342 * With DCC some colors don't require CMASK elimination before being
1343 * used as a texture. This sets a predicate value to determine if the
1344 * cmask eliminate is required.
1345 */
1346 void
1347 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1348 struct radv_image *image,
1349 bool value)
1350 {
1351 uint64_t pred_val = value;
1352 uint64_t va = radv_buffer_get_va(image->bo);
1353 va += image->offset + image->dcc_pred_offset;
1354
1355 assert(radv_image_has_dcc(image));
1356
1357 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1358 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1359 S_370_WR_CONFIRM(1) |
1360 S_370_ENGINE_SEL(V_370_PFP));
1361 radeon_emit(cmd_buffer->cs, va);
1362 radeon_emit(cmd_buffer->cs, va >> 32);
1363 radeon_emit(cmd_buffer->cs, pred_val);
1364 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1365 }
1366
1367 /**
1368 * Update the fast clear color values if the image is bound as a color buffer.
1369 */
1370 static void
1371 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1372 struct radv_image *image,
1373 int cb_idx,
1374 uint32_t color_values[2])
1375 {
1376 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1377 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1378 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1379 struct radv_attachment_info *att;
1380 uint32_t att_idx;
1381
1382 if (!framebuffer || !subpass)
1383 return;
1384
1385 att_idx = subpass->color_attachments[cb_idx].attachment;
1386 if (att_idx == VK_ATTACHMENT_UNUSED)
1387 return;
1388
1389 att = &framebuffer->attachments[att_idx];
1390 if (att->attachment->image != image)
1391 return;
1392
1393 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1394 radeon_emit(cs, color_values[0]);
1395 radeon_emit(cs, color_values[1]);
1396 }
1397
1398 /**
1399 * Set the clear color values to the image's metadata.
1400 */
1401 static void
1402 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1403 struct radv_image *image,
1404 uint32_t color_values[2])
1405 {
1406 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1407 uint64_t va = radv_buffer_get_va(image->bo);
1408
1409 va += image->offset + image->clear_value_offset;
1410
1411 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1412
1413 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1414 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1415 S_370_WR_CONFIRM(1) |
1416 S_370_ENGINE_SEL(V_370_PFP));
1417 radeon_emit(cs, va);
1418 radeon_emit(cs, va >> 32);
1419 radeon_emit(cs, color_values[0]);
1420 radeon_emit(cs, color_values[1]);
1421 }
1422
1423 /**
1424 * Update the clear color values for this image.
1425 */
1426 void
1427 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1428 struct radv_image *image,
1429 int cb_idx,
1430 uint32_t color_values[2])
1431 {
1432 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1433
1434 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1435
1436 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1437 color_values);
1438 }
1439
1440 /**
1441 * Load the clear color values from the image's metadata.
1442 */
1443 static void
1444 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1445 struct radv_image *image,
1446 int cb_idx)
1447 {
1448 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1449 uint64_t va = radv_buffer_get_va(image->bo);
1450
1451 va += image->offset + image->clear_value_offset;
1452
1453 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1454 return;
1455
1456 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1457
1458 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1459 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1460 radeon_emit(cs, va);
1461 radeon_emit(cs, va >> 32);
1462 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1463 radeon_emit(cs, 2);
1464 } else {
1465 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1466 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1467 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1468 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1469 COPY_DATA_COUNT_SEL);
1470 radeon_emit(cs, va);
1471 radeon_emit(cs, va >> 32);
1472 radeon_emit(cs, reg >> 2);
1473 radeon_emit(cs, 0);
1474
1475 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1476 radeon_emit(cs, 0);
1477 }
1478 }
1479
1480 static void
1481 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1482 {
1483 int i;
1484 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1485 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1486
1487 /* this may happen for inherited secondary recording */
1488 if (!framebuffer)
1489 return;
1490
1491 for (i = 0; i < 8; ++i) {
1492 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1493 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1494 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1495 continue;
1496 }
1497
1498 int idx = subpass->color_attachments[i].attachment;
1499 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1500 struct radv_image *image = att->attachment->image;
1501 VkImageLayout layout = subpass->color_attachments[i].layout;
1502
1503 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1504
1505 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1506 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1507
1508 radv_load_color_clear_metadata(cmd_buffer, image, i);
1509 }
1510
1511 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1512 int idx = subpass->depth_stencil_attachment.attachment;
1513 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1514 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1515 struct radv_image *image = att->attachment->image;
1516 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1517 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1518 cmd_buffer->queue_family_index,
1519 cmd_buffer->queue_family_index);
1520 /* We currently don't support writing decompressed HTILE */
1521 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1522 radv_layout_is_htile_compressed(image, layout, queue_mask));
1523
1524 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1525
1526 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1527 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1528 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1529 }
1530 radv_load_ds_clear_metadata(cmd_buffer, image);
1531 } else {
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1533 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1534 else
1535 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1536
1537 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1538 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1539 }
1540 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1541 S_028208_BR_X(framebuffer->width) |
1542 S_028208_BR_Y(framebuffer->height));
1543
1544 if (cmd_buffer->device->dfsm_allowed) {
1545 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1546 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1547 }
1548
1549 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1550 }
1551
1552 static void
1553 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1554 {
1555 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1556 struct radv_cmd_state *state = &cmd_buffer->state;
1557
1558 if (state->index_type != state->last_index_type) {
1559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1560 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1561 2, state->index_type);
1562 } else {
1563 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1564 radeon_emit(cs, state->index_type);
1565 }
1566
1567 state->last_index_type = state->index_type;
1568 }
1569
1570 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1571 radeon_emit(cs, state->index_va);
1572 radeon_emit(cs, state->index_va >> 32);
1573
1574 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1575 radeon_emit(cs, state->max_index_count);
1576
1577 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1578 }
1579
1580 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1581 {
1582 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1583 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1584 uint32_t pa_sc_mode_cntl_1 =
1585 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1586 uint32_t db_count_control;
1587
1588 if(!cmd_buffer->state.active_occlusion_queries) {
1589 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1590 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1591 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1592 has_perfect_queries) {
1593 /* Re-enable out-of-order rasterization if the
1594 * bound pipeline supports it and if it's has
1595 * been disabled before starting any perfect
1596 * occlusion queries.
1597 */
1598 radeon_set_context_reg(cmd_buffer->cs,
1599 R_028A4C_PA_SC_MODE_CNTL_1,
1600 pa_sc_mode_cntl_1);
1601 }
1602 }
1603 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1604 } else {
1605 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1606 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1607
1608 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1609 db_count_control =
1610 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1611 S_028004_SAMPLE_RATE(sample_rate) |
1612 S_028004_ZPASS_ENABLE(1) |
1613 S_028004_SLICE_EVEN_ENABLE(1) |
1614 S_028004_SLICE_ODD_ENABLE(1);
1615
1616 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1617 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1618 has_perfect_queries) {
1619 /* If the bound pipeline has enabled
1620 * out-of-order rasterization, we should
1621 * disable it before starting any perfect
1622 * occlusion queries.
1623 */
1624 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1625
1626 radeon_set_context_reg(cmd_buffer->cs,
1627 R_028A4C_PA_SC_MODE_CNTL_1,
1628 pa_sc_mode_cntl_1);
1629 }
1630 } else {
1631 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1632 S_028004_SAMPLE_RATE(sample_rate);
1633 }
1634 }
1635
1636 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1637 }
1638
1639 static void
1640 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1641 {
1642 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1643
1644 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1645 radv_emit_viewport(cmd_buffer);
1646
1647 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1648 !cmd_buffer->device->physical_device->has_scissor_bug)
1649 radv_emit_scissor(cmd_buffer);
1650
1651 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1652 radv_emit_line_width(cmd_buffer);
1653
1654 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1655 radv_emit_blend_constants(cmd_buffer);
1656
1657 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1658 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1659 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1660 radv_emit_stencil(cmd_buffer);
1661
1662 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1663 radv_emit_depth_bounds(cmd_buffer);
1664
1665 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1666 radv_emit_depth_bias(cmd_buffer);
1667
1668 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1669 radv_emit_discard_rectangle(cmd_buffer);
1670
1671 cmd_buffer->state.dirty &= ~states;
1672 }
1673
1674 static void
1675 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1676 VkPipelineBindPoint bind_point)
1677 {
1678 struct radv_descriptor_state *descriptors_state =
1679 radv_get_descriptors_state(cmd_buffer, bind_point);
1680 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1681 unsigned bo_offset;
1682
1683 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1684 set->mapped_ptr,
1685 &bo_offset))
1686 return;
1687
1688 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1689 set->va += bo_offset;
1690 }
1691
1692 static void
1693 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1694 VkPipelineBindPoint bind_point)
1695 {
1696 struct radv_descriptor_state *descriptors_state =
1697 radv_get_descriptors_state(cmd_buffer, bind_point);
1698 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1699 uint32_t size = MAX_SETS * 4 * ptr_size;
1700 uint32_t offset;
1701 void *ptr;
1702
1703 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1704 256, &offset, &ptr))
1705 return;
1706
1707 for (unsigned i = 0; i < MAX_SETS; i++) {
1708 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1709 uint64_t set_va = 0;
1710 struct radv_descriptor_set *set = descriptors_state->sets[i];
1711 if (descriptors_state->valid & (1u << i))
1712 set_va = set->va;
1713 uptr[0] = set_va & 0xffffffff;
1714 if (ptr_size == 2)
1715 uptr[1] = set_va >> 32;
1716 }
1717
1718 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1719 va += offset;
1720
1721 if (cmd_buffer->state.pipeline) {
1722 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1723 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1724 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1725
1726 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1727 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1728 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1729
1730 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1731 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1732 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1733
1734 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1735 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1736 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1737
1738 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1739 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1740 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1741 }
1742
1743 if (cmd_buffer->state.compute_pipeline)
1744 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1745 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1746 }
1747
1748 static void
1749 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1750 VkShaderStageFlags stages)
1751 {
1752 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1753 VK_PIPELINE_BIND_POINT_COMPUTE :
1754 VK_PIPELINE_BIND_POINT_GRAPHICS;
1755 struct radv_descriptor_state *descriptors_state =
1756 radv_get_descriptors_state(cmd_buffer, bind_point);
1757 struct radv_cmd_state *state = &cmd_buffer->state;
1758 bool flush_indirect_descriptors;
1759
1760 if (!descriptors_state->dirty)
1761 return;
1762
1763 if (descriptors_state->push_dirty)
1764 radv_flush_push_descriptors(cmd_buffer, bind_point);
1765
1766 flush_indirect_descriptors =
1767 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1768 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1769 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1770 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1771
1772 if (flush_indirect_descriptors)
1773 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1774
1775 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1776 cmd_buffer->cs,
1777 MAX_SETS * MESA_SHADER_STAGES * 4);
1778
1779 if (cmd_buffer->state.pipeline) {
1780 radv_foreach_stage(stage, stages) {
1781 if (!cmd_buffer->state.pipeline->shaders[stage])
1782 continue;
1783
1784 radv_emit_descriptor_pointers(cmd_buffer,
1785 cmd_buffer->state.pipeline,
1786 descriptors_state, stage);
1787 }
1788 }
1789
1790 if (cmd_buffer->state.compute_pipeline &&
1791 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1792 radv_emit_descriptor_pointers(cmd_buffer,
1793 cmd_buffer->state.compute_pipeline,
1794 descriptors_state,
1795 MESA_SHADER_COMPUTE);
1796 }
1797
1798 descriptors_state->dirty = 0;
1799 descriptors_state->push_dirty = false;
1800
1801 assert(cmd_buffer->cs->cdw <= cdw_max);
1802
1803 if (unlikely(cmd_buffer->device->trace_bo))
1804 radv_save_descriptors(cmd_buffer, bind_point);
1805 }
1806
1807 static void
1808 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1809 VkShaderStageFlags stages)
1810 {
1811 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1812 ? cmd_buffer->state.compute_pipeline
1813 : cmd_buffer->state.pipeline;
1814 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1815 VK_PIPELINE_BIND_POINT_COMPUTE :
1816 VK_PIPELINE_BIND_POINT_GRAPHICS;
1817 struct radv_descriptor_state *descriptors_state =
1818 radv_get_descriptors_state(cmd_buffer, bind_point);
1819 struct radv_pipeline_layout *layout = pipeline->layout;
1820 struct radv_shader_variant *shader, *prev_shader;
1821 unsigned offset;
1822 void *ptr;
1823 uint64_t va;
1824
1825 stages &= cmd_buffer->push_constant_stages;
1826 if (!stages ||
1827 (!layout->push_constant_size && !layout->dynamic_offset_count))
1828 return;
1829
1830 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1831 16 * layout->dynamic_offset_count,
1832 256, &offset, &ptr))
1833 return;
1834
1835 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1836 memcpy((char*)ptr + layout->push_constant_size,
1837 descriptors_state->dynamic_buffers,
1838 16 * layout->dynamic_offset_count);
1839
1840 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1841 va += offset;
1842
1843 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1844 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1845
1846 prev_shader = NULL;
1847 radv_foreach_stage(stage, stages) {
1848 shader = radv_get_shader(pipeline, stage);
1849
1850 /* Avoid redundantly emitting the address for merged stages. */
1851 if (shader && shader != prev_shader) {
1852 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1853 AC_UD_PUSH_CONSTANTS, va);
1854
1855 prev_shader = shader;
1856 }
1857 }
1858
1859 cmd_buffer->push_constant_stages &= ~stages;
1860 assert(cmd_buffer->cs->cdw <= cdw_max);
1861 }
1862
1863 static void
1864 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1865 bool pipeline_is_dirty)
1866 {
1867 if ((pipeline_is_dirty ||
1868 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1869 cmd_buffer->state.pipeline->vertex_elements.count &&
1870 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1871 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1872 unsigned vb_offset;
1873 void *vb_ptr;
1874 uint32_t i = 0;
1875 uint32_t count = velems->count;
1876 uint64_t va;
1877
1878 /* allocate some descriptor state for vertex buffers */
1879 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1880 &vb_offset, &vb_ptr))
1881 return;
1882
1883 for (i = 0; i < count; i++) {
1884 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1885 uint32_t offset;
1886 int vb = velems->binding[i];
1887 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1888 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1889
1890 va = radv_buffer_get_va(buffer->bo);
1891
1892 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1893 va += offset + buffer->offset;
1894 desc[0] = va;
1895 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1896 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1897 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1898 else
1899 desc[2] = buffer->size - offset;
1900 desc[3] = velems->rsrc_word3[i];
1901 }
1902
1903 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1904 va += vb_offset;
1905
1906 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1907 AC_UD_VS_VERTEX_BUFFERS, va);
1908
1909 cmd_buffer->state.vb_va = va;
1910 cmd_buffer->state.vb_size = count * 16;
1911 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1912 }
1913 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1914 }
1915
1916 static void
1917 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1918 {
1919 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1920 struct radv_userdata_info *loc;
1921 uint32_t base_reg;
1922
1923 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1924 if (!radv_get_shader(pipeline, stage))
1925 continue;
1926
1927 loc = radv_lookup_user_sgpr(pipeline, stage,
1928 AC_UD_STREAMOUT_BUFFERS);
1929 if (loc->sgpr_idx == -1)
1930 continue;
1931
1932 base_reg = pipeline->user_data_0[stage];
1933
1934 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1935 base_reg + loc->sgpr_idx * 4, va, false);
1936 }
1937
1938 if (pipeline->gs_copy_shader) {
1939 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1940 if (loc->sgpr_idx != -1) {
1941 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1942
1943 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1944 base_reg + loc->sgpr_idx * 4, va, false);
1945 }
1946 }
1947 }
1948
1949 static void
1950 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1951 {
1952 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1953 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1954 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1955 unsigned so_offset;
1956 void *so_ptr;
1957 uint64_t va;
1958
1959 /* Allocate some descriptor state for streamout buffers. */
1960 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1961 MAX_SO_BUFFERS * 16, 256,
1962 &so_offset, &so_ptr))
1963 return;
1964
1965 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1966 struct radv_buffer *buffer = sb[i].buffer;
1967 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1968
1969 if (!(so->enabled_mask & (1 << i)))
1970 continue;
1971
1972 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1973
1974 va += sb[i].offset;
1975
1976 /* Set the descriptor.
1977 *
1978 * On VI, the format must be non-INVALID, otherwise
1979 * the buffer will be considered not bound and store
1980 * instructions will be no-ops.
1981 */
1982 desc[0] = va;
1983 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1984 desc[2] = 0xffffffff;
1985 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1986 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1987 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1988 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1989 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1990 }
1991
1992 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1993 va += so_offset;
1994
1995 radv_emit_streamout_buffers(cmd_buffer, va);
1996 }
1997
1998 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
1999 }
2000
2001 static void
2002 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2003 {
2004 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2005 radv_flush_streamout_descriptors(cmd_buffer);
2006 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2007 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2008 }
2009
2010 static void
2011 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2012 bool instanced_draw, bool indirect_draw,
2013 uint32_t draw_vertex_count)
2014 {
2015 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2016 struct radv_cmd_state *state = &cmd_buffer->state;
2017 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2018 uint32_t ia_multi_vgt_param;
2019 int32_t primitive_reset_en;
2020
2021 /* Draw state. */
2022 ia_multi_vgt_param =
2023 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2024 indirect_draw, draw_vertex_count);
2025
2026 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2027 if (info->chip_class >= GFX9) {
2028 radeon_set_uconfig_reg_idx(cs,
2029 R_030960_IA_MULTI_VGT_PARAM,
2030 4, ia_multi_vgt_param);
2031 } else if (info->chip_class >= CIK) {
2032 radeon_set_context_reg_idx(cs,
2033 R_028AA8_IA_MULTI_VGT_PARAM,
2034 1, ia_multi_vgt_param);
2035 } else {
2036 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2037 ia_multi_vgt_param);
2038 }
2039 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2040 }
2041
2042 /* Primitive restart. */
2043 primitive_reset_en =
2044 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2045
2046 if (primitive_reset_en != state->last_primitive_reset_en) {
2047 state->last_primitive_reset_en = primitive_reset_en;
2048 if (info->chip_class >= GFX9) {
2049 radeon_set_uconfig_reg(cs,
2050 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2051 primitive_reset_en);
2052 } else {
2053 radeon_set_context_reg(cs,
2054 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2055 primitive_reset_en);
2056 }
2057 }
2058
2059 if (primitive_reset_en) {
2060 uint32_t primitive_reset_index =
2061 state->index_type ? 0xffffffffu : 0xffffu;
2062
2063 if (primitive_reset_index != state->last_primitive_reset_index) {
2064 radeon_set_context_reg(cs,
2065 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2066 primitive_reset_index);
2067 state->last_primitive_reset_index = primitive_reset_index;
2068 }
2069 }
2070 }
2071
2072 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2073 VkPipelineStageFlags src_stage_mask)
2074 {
2075 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2076 VK_PIPELINE_STAGE_TRANSFER_BIT |
2077 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2078 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2079 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2080 }
2081
2082 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2083 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2084 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2085 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2086 VK_PIPELINE_STAGE_TRANSFER_BIT |
2087 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2088 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2089 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2090 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2091 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2092 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2093 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2094 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2095 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2096 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2097 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2098 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2099 }
2100 }
2101
2102 static enum radv_cmd_flush_bits
2103 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2104 VkAccessFlags src_flags,
2105 struct radv_image *image)
2106 {
2107 bool flush_CB_meta = true, flush_DB_meta = true;
2108 enum radv_cmd_flush_bits flush_bits = 0;
2109 uint32_t b;
2110
2111 if (image) {
2112 if (!radv_image_has_CB_metadata(image))
2113 flush_CB_meta = false;
2114 if (!radv_image_has_htile(image))
2115 flush_DB_meta = false;
2116 }
2117
2118 for_each_bit(b, src_flags) {
2119 switch ((VkAccessFlagBits)(1 << b)) {
2120 case VK_ACCESS_SHADER_WRITE_BIT:
2121 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2122 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2123 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2124 break;
2125 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2126 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2127 if (flush_CB_meta)
2128 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2129 break;
2130 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2131 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2132 if (flush_DB_meta)
2133 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2134 break;
2135 case VK_ACCESS_TRANSFER_WRITE_BIT:
2136 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2137 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2138 RADV_CMD_FLAG_INV_GLOBAL_L2;
2139
2140 if (flush_CB_meta)
2141 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2142 if (flush_DB_meta)
2143 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2144 break;
2145 default:
2146 break;
2147 }
2148 }
2149 return flush_bits;
2150 }
2151
2152 static enum radv_cmd_flush_bits
2153 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2154 VkAccessFlags dst_flags,
2155 struct radv_image *image)
2156 {
2157 bool flush_CB_meta = true, flush_DB_meta = true;
2158 enum radv_cmd_flush_bits flush_bits = 0;
2159 bool flush_CB = true, flush_DB = true;
2160 bool image_is_coherent = false;
2161 uint32_t b;
2162
2163 if (image) {
2164 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2165 flush_CB = false;
2166 flush_DB = false;
2167 }
2168
2169 if (!radv_image_has_CB_metadata(image))
2170 flush_CB_meta = false;
2171 if (!radv_image_has_htile(image))
2172 flush_DB_meta = false;
2173
2174 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2175 if (image->info.samples == 1 &&
2176 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2177 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2178 !vk_format_is_stencil(image->vk_format)) {
2179 /* Single-sample color and single-sample depth
2180 * (not stencil) are coherent with shaders on
2181 * GFX9.
2182 */
2183 image_is_coherent = true;
2184 }
2185 }
2186 }
2187
2188 for_each_bit(b, dst_flags) {
2189 switch ((VkAccessFlagBits)(1 << b)) {
2190 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2191 case VK_ACCESS_INDEX_READ_BIT:
2192 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2193 break;
2194 case VK_ACCESS_UNIFORM_READ_BIT:
2195 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2196 break;
2197 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2198 case VK_ACCESS_TRANSFER_READ_BIT:
2199 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2200 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2201 RADV_CMD_FLAG_INV_GLOBAL_L2;
2202 break;
2203 case VK_ACCESS_SHADER_READ_BIT:
2204 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2205
2206 if (!image_is_coherent)
2207 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2208 break;
2209 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2210 if (flush_CB)
2211 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2212 if (flush_CB_meta)
2213 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2214 break;
2215 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2216 if (flush_DB)
2217 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2218 if (flush_DB_meta)
2219 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2220 break;
2221 default:
2222 break;
2223 }
2224 }
2225 return flush_bits;
2226 }
2227
2228 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2229 const struct radv_subpass_barrier *barrier)
2230 {
2231 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2232 NULL);
2233 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2234 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2235 NULL);
2236 }
2237
2238 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2239 struct radv_subpass_attachment att)
2240 {
2241 unsigned idx = att.attachment;
2242 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2243 VkImageSubresourceRange range;
2244 range.aspectMask = 0;
2245 range.baseMipLevel = view->base_mip;
2246 range.levelCount = 1;
2247 range.baseArrayLayer = view->base_layer;
2248 range.layerCount = cmd_buffer->state.framebuffer->layers;
2249
2250 radv_handle_image_transition(cmd_buffer,
2251 view->image,
2252 cmd_buffer->state.attachments[idx].current_layout,
2253 att.layout, 0, 0, &range,
2254 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2255
2256 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2257
2258
2259 }
2260
2261 void
2262 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2263 const struct radv_subpass *subpass, bool transitions)
2264 {
2265 if (transitions) {
2266 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2267
2268 for (unsigned i = 0; i < subpass->color_count; ++i) {
2269 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2270 radv_handle_subpass_image_transition(cmd_buffer,
2271 subpass->color_attachments[i]);
2272 }
2273
2274 for (unsigned i = 0; i < subpass->input_count; ++i) {
2275 radv_handle_subpass_image_transition(cmd_buffer,
2276 subpass->input_attachments[i]);
2277 }
2278
2279 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2280 radv_handle_subpass_image_transition(cmd_buffer,
2281 subpass->depth_stencil_attachment);
2282 }
2283 }
2284
2285 cmd_buffer->state.subpass = subpass;
2286
2287 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2288 }
2289
2290 static VkResult
2291 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2292 struct radv_render_pass *pass,
2293 const VkRenderPassBeginInfo *info)
2294 {
2295 struct radv_cmd_state *state = &cmd_buffer->state;
2296
2297 if (pass->attachment_count == 0) {
2298 state->attachments = NULL;
2299 return VK_SUCCESS;
2300 }
2301
2302 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2303 pass->attachment_count *
2304 sizeof(state->attachments[0]),
2305 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2306 if (state->attachments == NULL) {
2307 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2308 return cmd_buffer->record_result;
2309 }
2310
2311 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2312 struct radv_render_pass_attachment *att = &pass->attachments[i];
2313 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2314 VkImageAspectFlags clear_aspects = 0;
2315
2316 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2317 /* color attachment */
2318 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2319 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2320 }
2321 } else {
2322 /* depthstencil attachment */
2323 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2324 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2325 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2326 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2327 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2328 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2329 }
2330 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2331 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2332 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2333 }
2334 }
2335
2336 state->attachments[i].pending_clear_aspects = clear_aspects;
2337 state->attachments[i].cleared_views = 0;
2338 if (clear_aspects && info) {
2339 assert(info->clearValueCount > i);
2340 state->attachments[i].clear_value = info->pClearValues[i];
2341 }
2342
2343 state->attachments[i].current_layout = att->initial_layout;
2344 }
2345
2346 return VK_SUCCESS;
2347 }
2348
2349 VkResult radv_AllocateCommandBuffers(
2350 VkDevice _device,
2351 const VkCommandBufferAllocateInfo *pAllocateInfo,
2352 VkCommandBuffer *pCommandBuffers)
2353 {
2354 RADV_FROM_HANDLE(radv_device, device, _device);
2355 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2356
2357 VkResult result = VK_SUCCESS;
2358 uint32_t i;
2359
2360 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2361
2362 if (!list_empty(&pool->free_cmd_buffers)) {
2363 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2364
2365 list_del(&cmd_buffer->pool_link);
2366 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2367
2368 result = radv_reset_cmd_buffer(cmd_buffer);
2369 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2370 cmd_buffer->level = pAllocateInfo->level;
2371
2372 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2373 } else {
2374 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2375 &pCommandBuffers[i]);
2376 }
2377 if (result != VK_SUCCESS)
2378 break;
2379 }
2380
2381 if (result != VK_SUCCESS) {
2382 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2383 i, pCommandBuffers);
2384
2385 /* From the Vulkan 1.0.66 spec:
2386 *
2387 * "vkAllocateCommandBuffers can be used to create multiple
2388 * command buffers. If the creation of any of those command
2389 * buffers fails, the implementation must destroy all
2390 * successfully created command buffer objects from this
2391 * command, set all entries of the pCommandBuffers array to
2392 * NULL and return the error."
2393 */
2394 memset(pCommandBuffers, 0,
2395 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2396 }
2397
2398 return result;
2399 }
2400
2401 void radv_FreeCommandBuffers(
2402 VkDevice device,
2403 VkCommandPool commandPool,
2404 uint32_t commandBufferCount,
2405 const VkCommandBuffer *pCommandBuffers)
2406 {
2407 for (uint32_t i = 0; i < commandBufferCount; i++) {
2408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2409
2410 if (cmd_buffer) {
2411 if (cmd_buffer->pool) {
2412 list_del(&cmd_buffer->pool_link);
2413 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2414 } else
2415 radv_cmd_buffer_destroy(cmd_buffer);
2416
2417 }
2418 }
2419 }
2420
2421 VkResult radv_ResetCommandBuffer(
2422 VkCommandBuffer commandBuffer,
2423 VkCommandBufferResetFlags flags)
2424 {
2425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2426 return radv_reset_cmd_buffer(cmd_buffer);
2427 }
2428
2429 VkResult radv_BeginCommandBuffer(
2430 VkCommandBuffer commandBuffer,
2431 const VkCommandBufferBeginInfo *pBeginInfo)
2432 {
2433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2434 VkResult result = VK_SUCCESS;
2435
2436 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2437 /* If the command buffer has already been resetted with
2438 * vkResetCommandBuffer, no need to do it again.
2439 */
2440 result = radv_reset_cmd_buffer(cmd_buffer);
2441 if (result != VK_SUCCESS)
2442 return result;
2443 }
2444
2445 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2446 cmd_buffer->state.last_primitive_reset_en = -1;
2447 cmd_buffer->state.last_index_type = -1;
2448 cmd_buffer->state.last_num_instances = -1;
2449 cmd_buffer->state.last_vertex_offset = -1;
2450 cmd_buffer->state.last_first_instance = -1;
2451 cmd_buffer->state.predication_type = -1;
2452 cmd_buffer->usage_flags = pBeginInfo->flags;
2453
2454 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2455 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2456 assert(pBeginInfo->pInheritanceInfo);
2457 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2458 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2459
2460 struct radv_subpass *subpass =
2461 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2462
2463 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2464 if (result != VK_SUCCESS)
2465 return result;
2466
2467 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2468 }
2469
2470 if (unlikely(cmd_buffer->device->trace_bo)) {
2471 struct radv_device *device = cmd_buffer->device;
2472
2473 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2474 device->trace_bo);
2475
2476 radv_cmd_buffer_trace_emit(cmd_buffer);
2477 }
2478
2479 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2480
2481 return result;
2482 }
2483
2484 void radv_CmdBindVertexBuffers(
2485 VkCommandBuffer commandBuffer,
2486 uint32_t firstBinding,
2487 uint32_t bindingCount,
2488 const VkBuffer* pBuffers,
2489 const VkDeviceSize* pOffsets)
2490 {
2491 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2492 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2493 bool changed = false;
2494
2495 /* We have to defer setting up vertex buffer since we need the buffer
2496 * stride from the pipeline. */
2497
2498 assert(firstBinding + bindingCount <= MAX_VBS);
2499 for (uint32_t i = 0; i < bindingCount; i++) {
2500 uint32_t idx = firstBinding + i;
2501
2502 if (!changed &&
2503 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2504 vb[idx].offset != pOffsets[i])) {
2505 changed = true;
2506 }
2507
2508 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2509 vb[idx].offset = pOffsets[i];
2510
2511 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2512 vb[idx].buffer->bo);
2513 }
2514
2515 if (!changed) {
2516 /* No state changes. */
2517 return;
2518 }
2519
2520 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2521 }
2522
2523 void radv_CmdBindIndexBuffer(
2524 VkCommandBuffer commandBuffer,
2525 VkBuffer buffer,
2526 VkDeviceSize offset,
2527 VkIndexType indexType)
2528 {
2529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2530 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2531
2532 if (cmd_buffer->state.index_buffer == index_buffer &&
2533 cmd_buffer->state.index_offset == offset &&
2534 cmd_buffer->state.index_type == indexType) {
2535 /* No state changes. */
2536 return;
2537 }
2538
2539 cmd_buffer->state.index_buffer = index_buffer;
2540 cmd_buffer->state.index_offset = offset;
2541 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2542 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2543 cmd_buffer->state.index_va += index_buffer->offset + offset;
2544
2545 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2546 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2547 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2548 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2549 }
2550
2551
2552 static void
2553 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2554 VkPipelineBindPoint bind_point,
2555 struct radv_descriptor_set *set, unsigned idx)
2556 {
2557 struct radeon_winsys *ws = cmd_buffer->device->ws;
2558
2559 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2560
2561 assert(set);
2562 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2563
2564 if (!cmd_buffer->device->use_global_bo_list) {
2565 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2566 if (set->descriptors[j])
2567 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2568 }
2569
2570 if(set->bo)
2571 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2572 }
2573
2574 void radv_CmdBindDescriptorSets(
2575 VkCommandBuffer commandBuffer,
2576 VkPipelineBindPoint pipelineBindPoint,
2577 VkPipelineLayout _layout,
2578 uint32_t firstSet,
2579 uint32_t descriptorSetCount,
2580 const VkDescriptorSet* pDescriptorSets,
2581 uint32_t dynamicOffsetCount,
2582 const uint32_t* pDynamicOffsets)
2583 {
2584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2585 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2586 unsigned dyn_idx = 0;
2587
2588 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2589 struct radv_descriptor_state *descriptors_state =
2590 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2591
2592 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2593 unsigned idx = i + firstSet;
2594 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2595 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2596
2597 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2598 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2599 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2600 assert(dyn_idx < dynamicOffsetCount);
2601
2602 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2603 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2604 dst[0] = va;
2605 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2606 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2607 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2608 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2609 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2610 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2611 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2612 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2613 cmd_buffer->push_constant_stages |=
2614 set->layout->dynamic_shader_stages;
2615 }
2616 }
2617 }
2618
2619 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2620 struct radv_descriptor_set *set,
2621 struct radv_descriptor_set_layout *layout,
2622 VkPipelineBindPoint bind_point)
2623 {
2624 struct radv_descriptor_state *descriptors_state =
2625 radv_get_descriptors_state(cmd_buffer, bind_point);
2626 set->size = layout->size;
2627 set->layout = layout;
2628
2629 if (descriptors_state->push_set.capacity < set->size) {
2630 size_t new_size = MAX2(set->size, 1024);
2631 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2632 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2633
2634 free(set->mapped_ptr);
2635 set->mapped_ptr = malloc(new_size);
2636
2637 if (!set->mapped_ptr) {
2638 descriptors_state->push_set.capacity = 0;
2639 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2640 return false;
2641 }
2642
2643 descriptors_state->push_set.capacity = new_size;
2644 }
2645
2646 return true;
2647 }
2648
2649 void radv_meta_push_descriptor_set(
2650 struct radv_cmd_buffer* cmd_buffer,
2651 VkPipelineBindPoint pipelineBindPoint,
2652 VkPipelineLayout _layout,
2653 uint32_t set,
2654 uint32_t descriptorWriteCount,
2655 const VkWriteDescriptorSet* pDescriptorWrites)
2656 {
2657 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2658 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2659 unsigned bo_offset;
2660
2661 assert(set == 0);
2662 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2663
2664 push_set->size = layout->set[set].layout->size;
2665 push_set->layout = layout->set[set].layout;
2666
2667 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2668 &bo_offset,
2669 (void**) &push_set->mapped_ptr))
2670 return;
2671
2672 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2673 push_set->va += bo_offset;
2674
2675 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2676 radv_descriptor_set_to_handle(push_set),
2677 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2678
2679 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2680 }
2681
2682 void radv_CmdPushDescriptorSetKHR(
2683 VkCommandBuffer commandBuffer,
2684 VkPipelineBindPoint pipelineBindPoint,
2685 VkPipelineLayout _layout,
2686 uint32_t set,
2687 uint32_t descriptorWriteCount,
2688 const VkWriteDescriptorSet* pDescriptorWrites)
2689 {
2690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2691 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2692 struct radv_descriptor_state *descriptors_state =
2693 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2694 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2695
2696 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2697
2698 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2699 layout->set[set].layout,
2700 pipelineBindPoint))
2701 return;
2702
2703 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2704 radv_descriptor_set_to_handle(push_set),
2705 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2706
2707 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2708 descriptors_state->push_dirty = true;
2709 }
2710
2711 void radv_CmdPushDescriptorSetWithTemplateKHR(
2712 VkCommandBuffer commandBuffer,
2713 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2714 VkPipelineLayout _layout,
2715 uint32_t set,
2716 const void* pData)
2717 {
2718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2719 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2720 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2721 struct radv_descriptor_state *descriptors_state =
2722 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2723 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2724
2725 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2726
2727 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2728 layout->set[set].layout,
2729 templ->bind_point))
2730 return;
2731
2732 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2733 descriptorUpdateTemplate, pData);
2734
2735 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2736 descriptors_state->push_dirty = true;
2737 }
2738
2739 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2740 VkPipelineLayout layout,
2741 VkShaderStageFlags stageFlags,
2742 uint32_t offset,
2743 uint32_t size,
2744 const void* pValues)
2745 {
2746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2747 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2748 cmd_buffer->push_constant_stages |= stageFlags;
2749 }
2750
2751 VkResult radv_EndCommandBuffer(
2752 VkCommandBuffer commandBuffer)
2753 {
2754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2755
2756 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2757 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2758 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2759 si_emit_cache_flush(cmd_buffer);
2760 }
2761
2762 /* Make sure CP DMA is idle at the end of IBs because the kernel
2763 * doesn't wait for it.
2764 */
2765 si_cp_dma_wait_for_idle(cmd_buffer);
2766
2767 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2768
2769 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2770 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2771
2772 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2773
2774 return cmd_buffer->record_result;
2775 }
2776
2777 static void
2778 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2779 {
2780 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2781
2782 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2783 return;
2784
2785 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2786
2787 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2788 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2789
2790 cmd_buffer->compute_scratch_size_needed =
2791 MAX2(cmd_buffer->compute_scratch_size_needed,
2792 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2793
2794 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2795 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2796
2797 if (unlikely(cmd_buffer->device->trace_bo))
2798 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2799 }
2800
2801 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2802 VkPipelineBindPoint bind_point)
2803 {
2804 struct radv_descriptor_state *descriptors_state =
2805 radv_get_descriptors_state(cmd_buffer, bind_point);
2806
2807 descriptors_state->dirty |= descriptors_state->valid;
2808 }
2809
2810 void radv_CmdBindPipeline(
2811 VkCommandBuffer commandBuffer,
2812 VkPipelineBindPoint pipelineBindPoint,
2813 VkPipeline _pipeline)
2814 {
2815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2816 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2817
2818 switch (pipelineBindPoint) {
2819 case VK_PIPELINE_BIND_POINT_COMPUTE:
2820 if (cmd_buffer->state.compute_pipeline == pipeline)
2821 return;
2822 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2823
2824 cmd_buffer->state.compute_pipeline = pipeline;
2825 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2826 break;
2827 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2828 if (cmd_buffer->state.pipeline == pipeline)
2829 return;
2830 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2831
2832 cmd_buffer->state.pipeline = pipeline;
2833 if (!pipeline)
2834 break;
2835
2836 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2837 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2838
2839 /* the new vertex shader might not have the same user regs */
2840 cmd_buffer->state.last_first_instance = -1;
2841 cmd_buffer->state.last_vertex_offset = -1;
2842
2843 /* Prefetch all pipeline shaders at first draw time. */
2844 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2845
2846 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2847 radv_bind_streamout_state(cmd_buffer, pipeline);
2848
2849 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2850 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2851 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2852 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2853
2854 if (radv_pipeline_has_tess(pipeline))
2855 cmd_buffer->tess_rings_needed = true;
2856 break;
2857 default:
2858 assert(!"invalid bind point");
2859 break;
2860 }
2861 }
2862
2863 void radv_CmdSetViewport(
2864 VkCommandBuffer commandBuffer,
2865 uint32_t firstViewport,
2866 uint32_t viewportCount,
2867 const VkViewport* pViewports)
2868 {
2869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2870 struct radv_cmd_state *state = &cmd_buffer->state;
2871 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2872
2873 assert(firstViewport < MAX_VIEWPORTS);
2874 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2875
2876 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2877 viewportCount * sizeof(*pViewports));
2878
2879 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2880 }
2881
2882 void radv_CmdSetScissor(
2883 VkCommandBuffer commandBuffer,
2884 uint32_t firstScissor,
2885 uint32_t scissorCount,
2886 const VkRect2D* pScissors)
2887 {
2888 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2889 struct radv_cmd_state *state = &cmd_buffer->state;
2890 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2891
2892 assert(firstScissor < MAX_SCISSORS);
2893 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2894
2895 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2896 scissorCount * sizeof(*pScissors));
2897
2898 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2899 }
2900
2901 void radv_CmdSetLineWidth(
2902 VkCommandBuffer commandBuffer,
2903 float lineWidth)
2904 {
2905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2906 cmd_buffer->state.dynamic.line_width = lineWidth;
2907 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2908 }
2909
2910 void radv_CmdSetDepthBias(
2911 VkCommandBuffer commandBuffer,
2912 float depthBiasConstantFactor,
2913 float depthBiasClamp,
2914 float depthBiasSlopeFactor)
2915 {
2916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2917
2918 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2919 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2920 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2921
2922 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2923 }
2924
2925 void radv_CmdSetBlendConstants(
2926 VkCommandBuffer commandBuffer,
2927 const float blendConstants[4])
2928 {
2929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2930
2931 memcpy(cmd_buffer->state.dynamic.blend_constants,
2932 blendConstants, sizeof(float) * 4);
2933
2934 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2935 }
2936
2937 void radv_CmdSetDepthBounds(
2938 VkCommandBuffer commandBuffer,
2939 float minDepthBounds,
2940 float maxDepthBounds)
2941 {
2942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2943
2944 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2945 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2946
2947 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2948 }
2949
2950 void radv_CmdSetStencilCompareMask(
2951 VkCommandBuffer commandBuffer,
2952 VkStencilFaceFlags faceMask,
2953 uint32_t compareMask)
2954 {
2955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2956
2957 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2958 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2959 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2960 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2961
2962 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2963 }
2964
2965 void radv_CmdSetStencilWriteMask(
2966 VkCommandBuffer commandBuffer,
2967 VkStencilFaceFlags faceMask,
2968 uint32_t writeMask)
2969 {
2970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2971
2972 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2973 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2974 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2975 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2976
2977 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2978 }
2979
2980 void radv_CmdSetStencilReference(
2981 VkCommandBuffer commandBuffer,
2982 VkStencilFaceFlags faceMask,
2983 uint32_t reference)
2984 {
2985 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2986
2987 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2988 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2989 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2990 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2991
2992 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2993 }
2994
2995 void radv_CmdSetDiscardRectangleEXT(
2996 VkCommandBuffer commandBuffer,
2997 uint32_t firstDiscardRectangle,
2998 uint32_t discardRectangleCount,
2999 const VkRect2D* pDiscardRectangles)
3000 {
3001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3002 struct radv_cmd_state *state = &cmd_buffer->state;
3003 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3004
3005 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3006 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3007
3008 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3009 pDiscardRectangles, discardRectangleCount);
3010
3011 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3012 }
3013
3014 void radv_CmdExecuteCommands(
3015 VkCommandBuffer commandBuffer,
3016 uint32_t commandBufferCount,
3017 const VkCommandBuffer* pCmdBuffers)
3018 {
3019 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3020
3021 assert(commandBufferCount > 0);
3022
3023 /* Emit pending flushes on primary prior to executing secondary */
3024 si_emit_cache_flush(primary);
3025
3026 for (uint32_t i = 0; i < commandBufferCount; i++) {
3027 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3028
3029 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3030 secondary->scratch_size_needed);
3031 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3032 secondary->compute_scratch_size_needed);
3033
3034 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3035 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3036 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3037 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3038 if (secondary->tess_rings_needed)
3039 primary->tess_rings_needed = true;
3040 if (secondary->sample_positions_needed)
3041 primary->sample_positions_needed = true;
3042
3043 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3044
3045
3046 /* When the secondary command buffer is compute only we don't
3047 * need to re-emit the current graphics pipeline.
3048 */
3049 if (secondary->state.emitted_pipeline) {
3050 primary->state.emitted_pipeline =
3051 secondary->state.emitted_pipeline;
3052 }
3053
3054 /* When the secondary command buffer is graphics only we don't
3055 * need to re-emit the current compute pipeline.
3056 */
3057 if (secondary->state.emitted_compute_pipeline) {
3058 primary->state.emitted_compute_pipeline =
3059 secondary->state.emitted_compute_pipeline;
3060 }
3061
3062 /* Only re-emit the draw packets when needed. */
3063 if (secondary->state.last_primitive_reset_en != -1) {
3064 primary->state.last_primitive_reset_en =
3065 secondary->state.last_primitive_reset_en;
3066 }
3067
3068 if (secondary->state.last_primitive_reset_index) {
3069 primary->state.last_primitive_reset_index =
3070 secondary->state.last_primitive_reset_index;
3071 }
3072
3073 if (secondary->state.last_ia_multi_vgt_param) {
3074 primary->state.last_ia_multi_vgt_param =
3075 secondary->state.last_ia_multi_vgt_param;
3076 }
3077
3078 primary->state.last_first_instance = secondary->state.last_first_instance;
3079 primary->state.last_num_instances = secondary->state.last_num_instances;
3080 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3081
3082 if (secondary->state.last_index_type != -1) {
3083 primary->state.last_index_type =
3084 secondary->state.last_index_type;
3085 }
3086 }
3087
3088 /* After executing commands from secondary buffers we have to dirty
3089 * some states.
3090 */
3091 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3092 RADV_CMD_DIRTY_INDEX_BUFFER |
3093 RADV_CMD_DIRTY_DYNAMIC_ALL;
3094 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3095 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3096 }
3097
3098 VkResult radv_CreateCommandPool(
3099 VkDevice _device,
3100 const VkCommandPoolCreateInfo* pCreateInfo,
3101 const VkAllocationCallbacks* pAllocator,
3102 VkCommandPool* pCmdPool)
3103 {
3104 RADV_FROM_HANDLE(radv_device, device, _device);
3105 struct radv_cmd_pool *pool;
3106
3107 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3108 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3109 if (pool == NULL)
3110 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3111
3112 if (pAllocator)
3113 pool->alloc = *pAllocator;
3114 else
3115 pool->alloc = device->alloc;
3116
3117 list_inithead(&pool->cmd_buffers);
3118 list_inithead(&pool->free_cmd_buffers);
3119
3120 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3121
3122 *pCmdPool = radv_cmd_pool_to_handle(pool);
3123
3124 return VK_SUCCESS;
3125
3126 }
3127
3128 void radv_DestroyCommandPool(
3129 VkDevice _device,
3130 VkCommandPool commandPool,
3131 const VkAllocationCallbacks* pAllocator)
3132 {
3133 RADV_FROM_HANDLE(radv_device, device, _device);
3134 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3135
3136 if (!pool)
3137 return;
3138
3139 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3140 &pool->cmd_buffers, pool_link) {
3141 radv_cmd_buffer_destroy(cmd_buffer);
3142 }
3143
3144 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3145 &pool->free_cmd_buffers, pool_link) {
3146 radv_cmd_buffer_destroy(cmd_buffer);
3147 }
3148
3149 vk_free2(&device->alloc, pAllocator, pool);
3150 }
3151
3152 VkResult radv_ResetCommandPool(
3153 VkDevice device,
3154 VkCommandPool commandPool,
3155 VkCommandPoolResetFlags flags)
3156 {
3157 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3158 VkResult result;
3159
3160 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3161 &pool->cmd_buffers, pool_link) {
3162 result = radv_reset_cmd_buffer(cmd_buffer);
3163 if (result != VK_SUCCESS)
3164 return result;
3165 }
3166
3167 return VK_SUCCESS;
3168 }
3169
3170 void radv_TrimCommandPool(
3171 VkDevice device,
3172 VkCommandPool commandPool,
3173 VkCommandPoolTrimFlagsKHR flags)
3174 {
3175 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3176
3177 if (!pool)
3178 return;
3179
3180 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3181 &pool->free_cmd_buffers, pool_link) {
3182 radv_cmd_buffer_destroy(cmd_buffer);
3183 }
3184 }
3185
3186 void radv_CmdBeginRenderPass(
3187 VkCommandBuffer commandBuffer,
3188 const VkRenderPassBeginInfo* pRenderPassBegin,
3189 VkSubpassContents contents)
3190 {
3191 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3192 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3193 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3194
3195 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3196 cmd_buffer->cs, 2048);
3197 MAYBE_UNUSED VkResult result;
3198
3199 cmd_buffer->state.framebuffer = framebuffer;
3200 cmd_buffer->state.pass = pass;
3201 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3202
3203 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3204 if (result != VK_SUCCESS)
3205 return;
3206
3207 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3208 assert(cmd_buffer->cs->cdw <= cdw_max);
3209
3210 radv_cmd_buffer_clear_subpass(cmd_buffer);
3211 }
3212
3213 void radv_CmdBeginRenderPass2KHR(
3214 VkCommandBuffer commandBuffer,
3215 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3216 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3217 {
3218 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3219 pSubpassBeginInfo->contents);
3220 }
3221
3222 void radv_CmdNextSubpass(
3223 VkCommandBuffer commandBuffer,
3224 VkSubpassContents contents)
3225 {
3226 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3227
3228 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3229
3230 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3231 2048);
3232
3233 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3234 radv_cmd_buffer_clear_subpass(cmd_buffer);
3235 }
3236
3237 void radv_CmdNextSubpass2KHR(
3238 VkCommandBuffer commandBuffer,
3239 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3240 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3241 {
3242 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3243 }
3244
3245 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3246 {
3247 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3248 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3249 if (!radv_get_shader(pipeline, stage))
3250 continue;
3251
3252 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3253 if (loc->sgpr_idx == -1)
3254 continue;
3255 uint32_t base_reg = pipeline->user_data_0[stage];
3256 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3257
3258 }
3259 if (pipeline->gs_copy_shader) {
3260 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3261 if (loc->sgpr_idx != -1) {
3262 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3263 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3264 }
3265 }
3266 }
3267
3268 static void
3269 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3270 uint32_t vertex_count,
3271 bool use_opaque)
3272 {
3273 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3274 radeon_emit(cmd_buffer->cs, vertex_count);
3275 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3276 S_0287F0_USE_OPAQUE(use_opaque));
3277 }
3278
3279 static void
3280 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3281 uint64_t index_va,
3282 uint32_t index_count)
3283 {
3284 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3285 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3286 radeon_emit(cmd_buffer->cs, index_va);
3287 radeon_emit(cmd_buffer->cs, index_va >> 32);
3288 radeon_emit(cmd_buffer->cs, index_count);
3289 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3290 }
3291
3292 static void
3293 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3294 bool indexed,
3295 uint32_t draw_count,
3296 uint64_t count_va,
3297 uint32_t stride)
3298 {
3299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3300 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3301 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3302 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3303 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3304 bool predicating = cmd_buffer->state.predicating;
3305 assert(base_reg);
3306
3307 /* just reset draw state for vertex data */
3308 cmd_buffer->state.last_first_instance = -1;
3309 cmd_buffer->state.last_num_instances = -1;
3310 cmd_buffer->state.last_vertex_offset = -1;
3311
3312 if (draw_count == 1 && !count_va && !draw_id_enable) {
3313 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3314 PKT3_DRAW_INDIRECT, 3, predicating));
3315 radeon_emit(cs, 0);
3316 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3317 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3318 radeon_emit(cs, di_src_sel);
3319 } else {
3320 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3321 PKT3_DRAW_INDIRECT_MULTI,
3322 8, predicating));
3323 radeon_emit(cs, 0);
3324 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3325 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3326 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3327 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3328 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3329 radeon_emit(cs, draw_count); /* count */
3330 radeon_emit(cs, count_va); /* count_addr */
3331 radeon_emit(cs, count_va >> 32);
3332 radeon_emit(cs, stride); /* stride */
3333 radeon_emit(cs, di_src_sel);
3334 }
3335 }
3336
3337 struct radv_draw_info {
3338 /**
3339 * Number of vertices.
3340 */
3341 uint32_t count;
3342
3343 /**
3344 * Index of the first vertex.
3345 */
3346 int32_t vertex_offset;
3347
3348 /**
3349 * First instance id.
3350 */
3351 uint32_t first_instance;
3352
3353 /**
3354 * Number of instances.
3355 */
3356 uint32_t instance_count;
3357
3358 /**
3359 * First index (indexed draws only).
3360 */
3361 uint32_t first_index;
3362
3363 /**
3364 * Whether it's an indexed draw.
3365 */
3366 bool indexed;
3367
3368 /**
3369 * Indirect draw parameters resource.
3370 */
3371 struct radv_buffer *indirect;
3372 uint64_t indirect_offset;
3373 uint32_t stride;
3374
3375 /**
3376 * Draw count parameters resource.
3377 */
3378 struct radv_buffer *count_buffer;
3379 uint64_t count_buffer_offset;
3380
3381 /**
3382 * Stream output parameters resource.
3383 */
3384 struct radv_buffer *strmout_buffer;
3385 uint64_t strmout_buffer_offset;
3386 };
3387
3388 static void
3389 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3390 const struct radv_draw_info *info)
3391 {
3392 struct radv_cmd_state *state = &cmd_buffer->state;
3393 struct radeon_winsys *ws = cmd_buffer->device->ws;
3394 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3395
3396 if (info->strmout_buffer) {
3397 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3398
3399 va += info->strmout_buffer->offset +
3400 info->strmout_buffer_offset;
3401
3402 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3403 info->stride);
3404
3405 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3406 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3407 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3408 COPY_DATA_WR_CONFIRM);
3409 radeon_emit(cs, va);
3410 radeon_emit(cs, va >> 32);
3411 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3412 radeon_emit(cs, 0); /* unused */
3413
3414 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3415 }
3416
3417 if (info->indirect) {
3418 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3419 uint64_t count_va = 0;
3420
3421 va += info->indirect->offset + info->indirect_offset;
3422
3423 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3424
3425 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3426 radeon_emit(cs, 1);
3427 radeon_emit(cs, va);
3428 radeon_emit(cs, va >> 32);
3429
3430 if (info->count_buffer) {
3431 count_va = radv_buffer_get_va(info->count_buffer->bo);
3432 count_va += info->count_buffer->offset +
3433 info->count_buffer_offset;
3434
3435 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3436 }
3437
3438 if (!state->subpass->view_mask) {
3439 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3440 info->indexed,
3441 info->count,
3442 count_va,
3443 info->stride);
3444 } else {
3445 unsigned i;
3446 for_each_bit(i, state->subpass->view_mask) {
3447 radv_emit_view_index(cmd_buffer, i);
3448
3449 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3450 info->indexed,
3451 info->count,
3452 count_va,
3453 info->stride);
3454 }
3455 }
3456 } else {
3457 assert(state->pipeline->graphics.vtx_base_sgpr);
3458
3459 if (info->vertex_offset != state->last_vertex_offset ||
3460 info->first_instance != state->last_first_instance) {
3461 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3462 state->pipeline->graphics.vtx_emit_num);
3463
3464 radeon_emit(cs, info->vertex_offset);
3465 radeon_emit(cs, info->first_instance);
3466 if (state->pipeline->graphics.vtx_emit_num == 3)
3467 radeon_emit(cs, 0);
3468 state->last_first_instance = info->first_instance;
3469 state->last_vertex_offset = info->vertex_offset;
3470 }
3471
3472 if (state->last_num_instances != info->instance_count) {
3473 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3474 radeon_emit(cs, info->instance_count);
3475 state->last_num_instances = info->instance_count;
3476 }
3477
3478 if (info->indexed) {
3479 int index_size = state->index_type ? 4 : 2;
3480 uint64_t index_va;
3481
3482 index_va = state->index_va;
3483 index_va += info->first_index * index_size;
3484
3485 if (!state->subpass->view_mask) {
3486 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3487 index_va,
3488 info->count);
3489 } else {
3490 unsigned i;
3491 for_each_bit(i, state->subpass->view_mask) {
3492 radv_emit_view_index(cmd_buffer, i);
3493
3494 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3495 index_va,
3496 info->count);
3497 }
3498 }
3499 } else {
3500 if (!state->subpass->view_mask) {
3501 radv_cs_emit_draw_packet(cmd_buffer,
3502 info->count,
3503 !!info->strmout_buffer);
3504 } else {
3505 unsigned i;
3506 for_each_bit(i, state->subpass->view_mask) {
3507 radv_emit_view_index(cmd_buffer, i);
3508
3509 radv_cs_emit_draw_packet(cmd_buffer,
3510 info->count,
3511 !!info->strmout_buffer);
3512 }
3513 }
3514 }
3515 }
3516 }
3517
3518 /*
3519 * Vega and raven have a bug which triggers if there are multiple context
3520 * register contexts active at the same time with different scissor values.
3521 *
3522 * There are two possible workarounds:
3523 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3524 * there is only ever 1 active set of scissor values at the same time.
3525 *
3526 * 2) Whenever the hardware switches contexts we have to set the scissor
3527 * registers again even if it is a noop. That way the new context gets
3528 * the correct scissor values.
3529 *
3530 * This implements option 2. radv_need_late_scissor_emission needs to
3531 * return true on affected HW if radv_emit_all_graphics_states sets
3532 * any context registers.
3533 */
3534 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3535 bool indexed_draw)
3536 {
3537 struct radv_cmd_state *state = &cmd_buffer->state;
3538
3539 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3540 return false;
3541
3542 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3543
3544 /* Index, vertex and streamout buffers don't change context regs, and
3545 * pipeline is handled later.
3546 */
3547 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3548 RADV_CMD_DIRTY_VERTEX_BUFFER |
3549 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3550 RADV_CMD_DIRTY_PIPELINE);
3551
3552 /* Assume all state changes except these two can imply context rolls. */
3553 if (cmd_buffer->state.dirty & used_states)
3554 return true;
3555
3556 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3557 return true;
3558
3559 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3560 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3561 return true;
3562
3563 return false;
3564 }
3565
3566 static void
3567 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3568 const struct radv_draw_info *info)
3569 {
3570 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3571
3572 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3573 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3574 radv_emit_rbplus_state(cmd_buffer);
3575
3576 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3577 radv_emit_graphics_pipeline(cmd_buffer);
3578
3579 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3580 radv_emit_framebuffer_state(cmd_buffer);
3581
3582 if (info->indexed) {
3583 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3584 radv_emit_index_buffer(cmd_buffer);
3585 } else {
3586 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3587 * so the state must be re-emitted before the next indexed
3588 * draw.
3589 */
3590 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3591 cmd_buffer->state.last_index_type = -1;
3592 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3593 }
3594 }
3595
3596 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3597
3598 radv_emit_draw_registers(cmd_buffer, info->indexed,
3599 info->instance_count > 1, info->indirect,
3600 info->indirect ? 0 : info->count);
3601
3602 if (late_scissor_emission)
3603 radv_emit_scissor(cmd_buffer);
3604 }
3605
3606 static void
3607 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3608 const struct radv_draw_info *info)
3609 {
3610 struct radeon_info *rad_info =
3611 &cmd_buffer->device->physical_device->rad_info;
3612 bool has_prefetch =
3613 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3614 bool pipeline_is_dirty =
3615 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3616 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3617
3618 MAYBE_UNUSED unsigned cdw_max =
3619 radeon_check_space(cmd_buffer->device->ws,
3620 cmd_buffer->cs, 4096);
3621
3622 /* Use optimal packet order based on whether we need to sync the
3623 * pipeline.
3624 */
3625 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3626 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3627 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3628 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3629 /* If we have to wait for idle, set all states first, so that
3630 * all SET packets are processed in parallel with previous draw
3631 * calls. Then upload descriptors, set shader pointers, and
3632 * draw, and prefetch at the end. This ensures that the time
3633 * the CUs are idle is very short. (there are only SET_SH
3634 * packets between the wait and the draw)
3635 */
3636 radv_emit_all_graphics_states(cmd_buffer, info);
3637 si_emit_cache_flush(cmd_buffer);
3638 /* <-- CUs are idle here --> */
3639
3640 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3641
3642 radv_emit_draw_packets(cmd_buffer, info);
3643 /* <-- CUs are busy here --> */
3644
3645 /* Start prefetches after the draw has been started. Both will
3646 * run in parallel, but starting the draw first is more
3647 * important.
3648 */
3649 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3650 radv_emit_prefetch_L2(cmd_buffer,
3651 cmd_buffer->state.pipeline, false);
3652 }
3653 } else {
3654 /* If we don't wait for idle, start prefetches first, then set
3655 * states, and draw at the end.
3656 */
3657 si_emit_cache_flush(cmd_buffer);
3658
3659 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3660 /* Only prefetch the vertex shader and VBO descriptors
3661 * in order to start the draw as soon as possible.
3662 */
3663 radv_emit_prefetch_L2(cmd_buffer,
3664 cmd_buffer->state.pipeline, true);
3665 }
3666
3667 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3668
3669 radv_emit_all_graphics_states(cmd_buffer, info);
3670 radv_emit_draw_packets(cmd_buffer, info);
3671
3672 /* Prefetch the remaining shaders after the draw has been
3673 * started.
3674 */
3675 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3676 radv_emit_prefetch_L2(cmd_buffer,
3677 cmd_buffer->state.pipeline, false);
3678 }
3679 }
3680
3681 /* Workaround for a VGT hang when streamout is enabled.
3682 * It must be done after drawing.
3683 */
3684 if (cmd_buffer->state.streamout.streamout_enabled &&
3685 (rad_info->family == CHIP_HAWAII ||
3686 rad_info->family == CHIP_TONGA ||
3687 rad_info->family == CHIP_FIJI)) {
3688 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3689 }
3690
3691 assert(cmd_buffer->cs->cdw <= cdw_max);
3692 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3693 }
3694
3695 void radv_CmdDraw(
3696 VkCommandBuffer commandBuffer,
3697 uint32_t vertexCount,
3698 uint32_t instanceCount,
3699 uint32_t firstVertex,
3700 uint32_t firstInstance)
3701 {
3702 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3703 struct radv_draw_info info = {};
3704
3705 info.count = vertexCount;
3706 info.instance_count = instanceCount;
3707 info.first_instance = firstInstance;
3708 info.vertex_offset = firstVertex;
3709
3710 radv_draw(cmd_buffer, &info);
3711 }
3712
3713 void radv_CmdDrawIndexed(
3714 VkCommandBuffer commandBuffer,
3715 uint32_t indexCount,
3716 uint32_t instanceCount,
3717 uint32_t firstIndex,
3718 int32_t vertexOffset,
3719 uint32_t firstInstance)
3720 {
3721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3722 struct radv_draw_info info = {};
3723
3724 info.indexed = true;
3725 info.count = indexCount;
3726 info.instance_count = instanceCount;
3727 info.first_index = firstIndex;
3728 info.vertex_offset = vertexOffset;
3729 info.first_instance = firstInstance;
3730
3731 radv_draw(cmd_buffer, &info);
3732 }
3733
3734 void radv_CmdDrawIndirect(
3735 VkCommandBuffer commandBuffer,
3736 VkBuffer _buffer,
3737 VkDeviceSize offset,
3738 uint32_t drawCount,
3739 uint32_t stride)
3740 {
3741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3742 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3743 struct radv_draw_info info = {};
3744
3745 info.count = drawCount;
3746 info.indirect = buffer;
3747 info.indirect_offset = offset;
3748 info.stride = stride;
3749
3750 radv_draw(cmd_buffer, &info);
3751 }
3752
3753 void radv_CmdDrawIndexedIndirect(
3754 VkCommandBuffer commandBuffer,
3755 VkBuffer _buffer,
3756 VkDeviceSize offset,
3757 uint32_t drawCount,
3758 uint32_t stride)
3759 {
3760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3761 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3762 struct radv_draw_info info = {};
3763
3764 info.indexed = true;
3765 info.count = drawCount;
3766 info.indirect = buffer;
3767 info.indirect_offset = offset;
3768 info.stride = stride;
3769
3770 radv_draw(cmd_buffer, &info);
3771 }
3772
3773 void radv_CmdDrawIndirectCountAMD(
3774 VkCommandBuffer commandBuffer,
3775 VkBuffer _buffer,
3776 VkDeviceSize offset,
3777 VkBuffer _countBuffer,
3778 VkDeviceSize countBufferOffset,
3779 uint32_t maxDrawCount,
3780 uint32_t stride)
3781 {
3782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3783 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3784 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3785 struct radv_draw_info info = {};
3786
3787 info.count = maxDrawCount;
3788 info.indirect = buffer;
3789 info.indirect_offset = offset;
3790 info.count_buffer = count_buffer;
3791 info.count_buffer_offset = countBufferOffset;
3792 info.stride = stride;
3793
3794 radv_draw(cmd_buffer, &info);
3795 }
3796
3797 void radv_CmdDrawIndexedIndirectCountAMD(
3798 VkCommandBuffer commandBuffer,
3799 VkBuffer _buffer,
3800 VkDeviceSize offset,
3801 VkBuffer _countBuffer,
3802 VkDeviceSize countBufferOffset,
3803 uint32_t maxDrawCount,
3804 uint32_t stride)
3805 {
3806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3807 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3808 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3809 struct radv_draw_info info = {};
3810
3811 info.indexed = true;
3812 info.count = maxDrawCount;
3813 info.indirect = buffer;
3814 info.indirect_offset = offset;
3815 info.count_buffer = count_buffer;
3816 info.count_buffer_offset = countBufferOffset;
3817 info.stride = stride;
3818
3819 radv_draw(cmd_buffer, &info);
3820 }
3821
3822 void radv_CmdDrawIndirectCountKHR(
3823 VkCommandBuffer commandBuffer,
3824 VkBuffer _buffer,
3825 VkDeviceSize offset,
3826 VkBuffer _countBuffer,
3827 VkDeviceSize countBufferOffset,
3828 uint32_t maxDrawCount,
3829 uint32_t stride)
3830 {
3831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3832 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3833 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3834 struct radv_draw_info info = {};
3835
3836 info.count = maxDrawCount;
3837 info.indirect = buffer;
3838 info.indirect_offset = offset;
3839 info.count_buffer = count_buffer;
3840 info.count_buffer_offset = countBufferOffset;
3841 info.stride = stride;
3842
3843 radv_draw(cmd_buffer, &info);
3844 }
3845
3846 void radv_CmdDrawIndexedIndirectCountKHR(
3847 VkCommandBuffer commandBuffer,
3848 VkBuffer _buffer,
3849 VkDeviceSize offset,
3850 VkBuffer _countBuffer,
3851 VkDeviceSize countBufferOffset,
3852 uint32_t maxDrawCount,
3853 uint32_t stride)
3854 {
3855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3856 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3857 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3858 struct radv_draw_info info = {};
3859
3860 info.indexed = true;
3861 info.count = maxDrawCount;
3862 info.indirect = buffer;
3863 info.indirect_offset = offset;
3864 info.count_buffer = count_buffer;
3865 info.count_buffer_offset = countBufferOffset;
3866 info.stride = stride;
3867
3868 radv_draw(cmd_buffer, &info);
3869 }
3870
3871 struct radv_dispatch_info {
3872 /**
3873 * Determine the layout of the grid (in block units) to be used.
3874 */
3875 uint32_t blocks[3];
3876
3877 /**
3878 * A starting offset for the grid. If unaligned is set, the offset
3879 * must still be aligned.
3880 */
3881 uint32_t offsets[3];
3882 /**
3883 * Whether it's an unaligned compute dispatch.
3884 */
3885 bool unaligned;
3886
3887 /**
3888 * Indirect compute parameters resource.
3889 */
3890 struct radv_buffer *indirect;
3891 uint64_t indirect_offset;
3892 };
3893
3894 static void
3895 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3896 const struct radv_dispatch_info *info)
3897 {
3898 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3899 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3900 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3901 struct radeon_winsys *ws = cmd_buffer->device->ws;
3902 bool predicating = cmd_buffer->state.predicating;
3903 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3904 struct radv_userdata_info *loc;
3905
3906 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3907 AC_UD_CS_GRID_SIZE);
3908
3909 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3910
3911 if (info->indirect) {
3912 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3913
3914 va += info->indirect->offset + info->indirect_offset;
3915
3916 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3917
3918 if (loc->sgpr_idx != -1) {
3919 for (unsigned i = 0; i < 3; ++i) {
3920 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3921 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3922 COPY_DATA_DST_SEL(COPY_DATA_REG));
3923 radeon_emit(cs, (va + 4 * i));
3924 radeon_emit(cs, (va + 4 * i) >> 32);
3925 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3926 + loc->sgpr_idx * 4) >> 2) + i);
3927 radeon_emit(cs, 0);
3928 }
3929 }
3930
3931 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3932 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3933 PKT3_SHADER_TYPE_S(1));
3934 radeon_emit(cs, va);
3935 radeon_emit(cs, va >> 32);
3936 radeon_emit(cs, dispatch_initiator);
3937 } else {
3938 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3939 PKT3_SHADER_TYPE_S(1));
3940 radeon_emit(cs, 1);
3941 radeon_emit(cs, va);
3942 radeon_emit(cs, va >> 32);
3943
3944 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3945 PKT3_SHADER_TYPE_S(1));
3946 radeon_emit(cs, 0);
3947 radeon_emit(cs, dispatch_initiator);
3948 }
3949 } else {
3950 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3951 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3952
3953 if (info->unaligned) {
3954 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3955 unsigned remainder[3];
3956
3957 /* If aligned, these should be an entire block size,
3958 * not 0.
3959 */
3960 remainder[0] = blocks[0] + cs_block_size[0] -
3961 align_u32_npot(blocks[0], cs_block_size[0]);
3962 remainder[1] = blocks[1] + cs_block_size[1] -
3963 align_u32_npot(blocks[1], cs_block_size[1]);
3964 remainder[2] = blocks[2] + cs_block_size[2] -
3965 align_u32_npot(blocks[2], cs_block_size[2]);
3966
3967 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3968 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3969 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3970
3971 for(unsigned i = 0; i < 3; ++i) {
3972 assert(offsets[i] % cs_block_size[i] == 0);
3973 offsets[i] /= cs_block_size[i];
3974 }
3975
3976 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3977 radeon_emit(cs,
3978 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3979 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3980 radeon_emit(cs,
3981 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3982 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3983 radeon_emit(cs,
3984 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3985 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3986
3987 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3988 }
3989
3990 if (loc->sgpr_idx != -1) {
3991 assert(!loc->indirect);
3992 assert(loc->num_sgprs == 3);
3993
3994 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3995 loc->sgpr_idx * 4, 3);
3996 radeon_emit(cs, blocks[0]);
3997 radeon_emit(cs, blocks[1]);
3998 radeon_emit(cs, blocks[2]);
3999 }
4000
4001 if (offsets[0] || offsets[1] || offsets[2]) {
4002 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4003 radeon_emit(cs, offsets[0]);
4004 radeon_emit(cs, offsets[1]);
4005 radeon_emit(cs, offsets[2]);
4006
4007 /* The blocks in the packet are not counts but end values. */
4008 for (unsigned i = 0; i < 3; ++i)
4009 blocks[i] += offsets[i];
4010 } else {
4011 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4012 }
4013
4014 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4015 PKT3_SHADER_TYPE_S(1));
4016 radeon_emit(cs, blocks[0]);
4017 radeon_emit(cs, blocks[1]);
4018 radeon_emit(cs, blocks[2]);
4019 radeon_emit(cs, dispatch_initiator);
4020 }
4021
4022 assert(cmd_buffer->cs->cdw <= cdw_max);
4023 }
4024
4025 static void
4026 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4027 {
4028 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4029 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4030 }
4031
4032 static void
4033 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4034 const struct radv_dispatch_info *info)
4035 {
4036 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4037 bool has_prefetch =
4038 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4039 bool pipeline_is_dirty = pipeline &&
4040 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4041
4042 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4043 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4044 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4045 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4046 /* If we have to wait for idle, set all states first, so that
4047 * all SET packets are processed in parallel with previous draw
4048 * calls. Then upload descriptors, set shader pointers, and
4049 * dispatch, and prefetch at the end. This ensures that the
4050 * time the CUs are idle is very short. (there are only SET_SH
4051 * packets between the wait and the draw)
4052 */
4053 radv_emit_compute_pipeline(cmd_buffer);
4054 si_emit_cache_flush(cmd_buffer);
4055 /* <-- CUs are idle here --> */
4056
4057 radv_upload_compute_shader_descriptors(cmd_buffer);
4058
4059 radv_emit_dispatch_packets(cmd_buffer, info);
4060 /* <-- CUs are busy here --> */
4061
4062 /* Start prefetches after the dispatch has been started. Both
4063 * will run in parallel, but starting the dispatch first is
4064 * more important.
4065 */
4066 if (has_prefetch && pipeline_is_dirty) {
4067 radv_emit_shader_prefetch(cmd_buffer,
4068 pipeline->shaders[MESA_SHADER_COMPUTE]);
4069 }
4070 } else {
4071 /* If we don't wait for idle, start prefetches first, then set
4072 * states, and dispatch at the end.
4073 */
4074 si_emit_cache_flush(cmd_buffer);
4075
4076 if (has_prefetch && pipeline_is_dirty) {
4077 radv_emit_shader_prefetch(cmd_buffer,
4078 pipeline->shaders[MESA_SHADER_COMPUTE]);
4079 }
4080
4081 radv_upload_compute_shader_descriptors(cmd_buffer);
4082
4083 radv_emit_compute_pipeline(cmd_buffer);
4084 radv_emit_dispatch_packets(cmd_buffer, info);
4085 }
4086
4087 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4088 }
4089
4090 void radv_CmdDispatchBase(
4091 VkCommandBuffer commandBuffer,
4092 uint32_t base_x,
4093 uint32_t base_y,
4094 uint32_t base_z,
4095 uint32_t x,
4096 uint32_t y,
4097 uint32_t z)
4098 {
4099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4100 struct radv_dispatch_info info = {};
4101
4102 info.blocks[0] = x;
4103 info.blocks[1] = y;
4104 info.blocks[2] = z;
4105
4106 info.offsets[0] = base_x;
4107 info.offsets[1] = base_y;
4108 info.offsets[2] = base_z;
4109 radv_dispatch(cmd_buffer, &info);
4110 }
4111
4112 void radv_CmdDispatch(
4113 VkCommandBuffer commandBuffer,
4114 uint32_t x,
4115 uint32_t y,
4116 uint32_t z)
4117 {
4118 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4119 }
4120
4121 void radv_CmdDispatchIndirect(
4122 VkCommandBuffer commandBuffer,
4123 VkBuffer _buffer,
4124 VkDeviceSize offset)
4125 {
4126 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4127 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4128 struct radv_dispatch_info info = {};
4129
4130 info.indirect = buffer;
4131 info.indirect_offset = offset;
4132
4133 radv_dispatch(cmd_buffer, &info);
4134 }
4135
4136 void radv_unaligned_dispatch(
4137 struct radv_cmd_buffer *cmd_buffer,
4138 uint32_t x,
4139 uint32_t y,
4140 uint32_t z)
4141 {
4142 struct radv_dispatch_info info = {};
4143
4144 info.blocks[0] = x;
4145 info.blocks[1] = y;
4146 info.blocks[2] = z;
4147 info.unaligned = 1;
4148
4149 radv_dispatch(cmd_buffer, &info);
4150 }
4151
4152 void radv_CmdEndRenderPass(
4153 VkCommandBuffer commandBuffer)
4154 {
4155 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4156
4157 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4158
4159 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4160
4161 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4162 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4163 radv_handle_subpass_image_transition(cmd_buffer,
4164 (struct radv_subpass_attachment){i, layout});
4165 }
4166
4167 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4168
4169 cmd_buffer->state.pass = NULL;
4170 cmd_buffer->state.subpass = NULL;
4171 cmd_buffer->state.attachments = NULL;
4172 cmd_buffer->state.framebuffer = NULL;
4173 }
4174
4175 void radv_CmdEndRenderPass2KHR(
4176 VkCommandBuffer commandBuffer,
4177 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4178 {
4179 radv_CmdEndRenderPass(commandBuffer);
4180 }
4181
4182 /*
4183 * For HTILE we have the following interesting clear words:
4184 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4185 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4186 * 0xfffffff0: Clear depth to 1.0
4187 * 0x00000000: Clear depth to 0.0
4188 */
4189 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4190 struct radv_image *image,
4191 const VkImageSubresourceRange *range,
4192 uint32_t clear_word)
4193 {
4194 assert(range->baseMipLevel == 0);
4195 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4196 unsigned layer_count = radv_get_layerCount(image, range);
4197 uint64_t size = image->surface.htile_slice_size * layer_count;
4198 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4199 uint64_t offset = image->offset + image->htile_offset +
4200 image->surface.htile_slice_size * range->baseArrayLayer;
4201 struct radv_cmd_state *state = &cmd_buffer->state;
4202 VkClearDepthStencilValue value = {};
4203
4204 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4205 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4206
4207 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4208 size, clear_word);
4209
4210 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4211
4212 if (vk_format_is_stencil(image->vk_format))
4213 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4214
4215 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4216 }
4217
4218 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4219 struct radv_image *image,
4220 VkImageLayout src_layout,
4221 VkImageLayout dst_layout,
4222 unsigned src_queue_mask,
4223 unsigned dst_queue_mask,
4224 const VkImageSubresourceRange *range,
4225 VkImageAspectFlags pending_clears)
4226 {
4227 if (!radv_image_has_htile(image))
4228 return;
4229
4230 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4231 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4232 /* TODO: merge with the clear if applicable */
4233 radv_initialize_htile(cmd_buffer, image, range, 0);
4234 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4235 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4236 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4237 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4238 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4239 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4240 VkImageSubresourceRange local_range = *range;
4241 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4242 local_range.baseMipLevel = 0;
4243 local_range.levelCount = 1;
4244
4245 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4246 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4247
4248 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4249
4250 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4251 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4252 }
4253 }
4254
4255 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4256 struct radv_image *image, uint32_t value)
4257 {
4258 struct radv_cmd_state *state = &cmd_buffer->state;
4259
4260 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4261 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4262
4263 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4264
4265 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4266 }
4267
4268 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4269 struct radv_image *image, uint32_t value)
4270 {
4271 struct radv_cmd_state *state = &cmd_buffer->state;
4272
4273 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4274 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4275
4276 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4277
4278 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4279 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4280 }
4281
4282 /**
4283 * Initialize DCC/FMASK/CMASK metadata for a color image.
4284 */
4285 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4286 struct radv_image *image,
4287 VkImageLayout src_layout,
4288 VkImageLayout dst_layout,
4289 unsigned src_queue_mask,
4290 unsigned dst_queue_mask)
4291 {
4292 if (radv_image_has_cmask(image)) {
4293 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4294
4295 /* TODO: clarify this. */
4296 if (radv_image_has_fmask(image)) {
4297 value = 0xccccccccu;
4298 }
4299
4300 radv_initialise_cmask(cmd_buffer, image, value);
4301 }
4302
4303 if (radv_image_has_dcc(image)) {
4304 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4305 bool need_decompress_pass = false;
4306
4307 if (radv_layout_dcc_compressed(image, dst_layout,
4308 dst_queue_mask)) {
4309 value = 0x20202020u;
4310 need_decompress_pass = true;
4311 }
4312
4313 radv_initialize_dcc(cmd_buffer, image, value);
4314
4315 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4316 need_decompress_pass);
4317 }
4318
4319 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4320 uint32_t color_values[2] = {};
4321 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4322 }
4323 }
4324
4325 /**
4326 * Handle color image transitions for DCC/FMASK/CMASK.
4327 */
4328 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4329 struct radv_image *image,
4330 VkImageLayout src_layout,
4331 VkImageLayout dst_layout,
4332 unsigned src_queue_mask,
4333 unsigned dst_queue_mask,
4334 const VkImageSubresourceRange *range)
4335 {
4336 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4337 radv_init_color_image_metadata(cmd_buffer, image,
4338 src_layout, dst_layout,
4339 src_queue_mask, dst_queue_mask);
4340 return;
4341 }
4342
4343 if (radv_image_has_dcc(image)) {
4344 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4345 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4346 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4347 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4348 radv_decompress_dcc(cmd_buffer, image, range);
4349 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4350 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4351 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4352 }
4353 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4354 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4355 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4356 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4357 }
4358 }
4359 }
4360
4361 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4362 struct radv_image *image,
4363 VkImageLayout src_layout,
4364 VkImageLayout dst_layout,
4365 uint32_t src_family,
4366 uint32_t dst_family,
4367 const VkImageSubresourceRange *range,
4368 VkImageAspectFlags pending_clears)
4369 {
4370 if (image->exclusive && src_family != dst_family) {
4371 /* This is an acquire or a release operation and there will be
4372 * a corresponding release/acquire. Do the transition in the
4373 * most flexible queue. */
4374
4375 assert(src_family == cmd_buffer->queue_family_index ||
4376 dst_family == cmd_buffer->queue_family_index);
4377
4378 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4379 return;
4380
4381 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4382 (src_family == RADV_QUEUE_GENERAL ||
4383 dst_family == RADV_QUEUE_GENERAL))
4384 return;
4385 }
4386
4387 unsigned src_queue_mask =
4388 radv_image_queue_family_mask(image, src_family,
4389 cmd_buffer->queue_family_index);
4390 unsigned dst_queue_mask =
4391 radv_image_queue_family_mask(image, dst_family,
4392 cmd_buffer->queue_family_index);
4393
4394 if (vk_format_is_depth(image->vk_format)) {
4395 radv_handle_depth_image_transition(cmd_buffer, image,
4396 src_layout, dst_layout,
4397 src_queue_mask, dst_queue_mask,
4398 range, pending_clears);
4399 } else {
4400 radv_handle_color_image_transition(cmd_buffer, image,
4401 src_layout, dst_layout,
4402 src_queue_mask, dst_queue_mask,
4403 range);
4404 }
4405 }
4406
4407 struct radv_barrier_info {
4408 uint32_t eventCount;
4409 const VkEvent *pEvents;
4410 VkPipelineStageFlags srcStageMask;
4411 };
4412
4413 static void
4414 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4415 uint32_t memoryBarrierCount,
4416 const VkMemoryBarrier *pMemoryBarriers,
4417 uint32_t bufferMemoryBarrierCount,
4418 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4419 uint32_t imageMemoryBarrierCount,
4420 const VkImageMemoryBarrier *pImageMemoryBarriers,
4421 const struct radv_barrier_info *info)
4422 {
4423 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4424 enum radv_cmd_flush_bits src_flush_bits = 0;
4425 enum radv_cmd_flush_bits dst_flush_bits = 0;
4426
4427 for (unsigned i = 0; i < info->eventCount; ++i) {
4428 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4429 uint64_t va = radv_buffer_get_va(event->bo);
4430
4431 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4432
4433 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4434
4435 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4436 assert(cmd_buffer->cs->cdw <= cdw_max);
4437 }
4438
4439 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4440 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4441 NULL);
4442 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4443 NULL);
4444 }
4445
4446 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4447 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4448 NULL);
4449 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4450 NULL);
4451 }
4452
4453 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4454 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4455
4456 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4457 image);
4458 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4459 image);
4460 }
4461
4462 radv_stage_flush(cmd_buffer, info->srcStageMask);
4463 cmd_buffer->state.flush_bits |= src_flush_bits;
4464
4465 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4466 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4467 radv_handle_image_transition(cmd_buffer, image,
4468 pImageMemoryBarriers[i].oldLayout,
4469 pImageMemoryBarriers[i].newLayout,
4470 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4471 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4472 &pImageMemoryBarriers[i].subresourceRange,
4473 0);
4474 }
4475
4476 /* Make sure CP DMA is idle because the driver might have performed a
4477 * DMA operation for copying or filling buffers/images.
4478 */
4479 si_cp_dma_wait_for_idle(cmd_buffer);
4480
4481 cmd_buffer->state.flush_bits |= dst_flush_bits;
4482 }
4483
4484 void radv_CmdPipelineBarrier(
4485 VkCommandBuffer commandBuffer,
4486 VkPipelineStageFlags srcStageMask,
4487 VkPipelineStageFlags destStageMask,
4488 VkBool32 byRegion,
4489 uint32_t memoryBarrierCount,
4490 const VkMemoryBarrier* pMemoryBarriers,
4491 uint32_t bufferMemoryBarrierCount,
4492 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4493 uint32_t imageMemoryBarrierCount,
4494 const VkImageMemoryBarrier* pImageMemoryBarriers)
4495 {
4496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4497 struct radv_barrier_info info;
4498
4499 info.eventCount = 0;
4500 info.pEvents = NULL;
4501 info.srcStageMask = srcStageMask;
4502
4503 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4504 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4505 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4506 }
4507
4508
4509 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4510 struct radv_event *event,
4511 VkPipelineStageFlags stageMask,
4512 unsigned value)
4513 {
4514 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4515 uint64_t va = radv_buffer_get_va(event->bo);
4516
4517 si_emit_cache_flush(cmd_buffer);
4518
4519 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4520
4521 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4522
4523 /* Flags that only require a top-of-pipe event. */
4524 VkPipelineStageFlags top_of_pipe_flags =
4525 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4526
4527 /* Flags that only require a post-index-fetch event. */
4528 VkPipelineStageFlags post_index_fetch_flags =
4529 top_of_pipe_flags |
4530 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4531 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4532
4533 /* Make sure CP DMA is idle because the driver might have performed a
4534 * DMA operation for copying or filling buffers/images.
4535 */
4536 si_cp_dma_wait_for_idle(cmd_buffer);
4537
4538 /* TODO: Emit EOS events for syncing PS/CS stages. */
4539
4540 if (!(stageMask & ~top_of_pipe_flags)) {
4541 /* Just need to sync the PFP engine. */
4542 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4543 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4544 S_370_WR_CONFIRM(1) |
4545 S_370_ENGINE_SEL(V_370_PFP));
4546 radeon_emit(cs, va);
4547 radeon_emit(cs, va >> 32);
4548 radeon_emit(cs, value);
4549 } else if (!(stageMask & ~post_index_fetch_flags)) {
4550 /* Sync ME because PFP reads index and indirect buffers. */
4551 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4552 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4553 S_370_WR_CONFIRM(1) |
4554 S_370_ENGINE_SEL(V_370_ME));
4555 radeon_emit(cs, va);
4556 radeon_emit(cs, va >> 32);
4557 radeon_emit(cs, value);
4558 } else {
4559 /* Otherwise, sync all prior GPU work using an EOP event. */
4560 si_cs_emit_write_event_eop(cs,
4561 cmd_buffer->device->physical_device->rad_info.chip_class,
4562 radv_cmd_buffer_uses_mec(cmd_buffer),
4563 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4564 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4565 cmd_buffer->gfx9_eop_bug_va);
4566 }
4567
4568 assert(cmd_buffer->cs->cdw <= cdw_max);
4569 }
4570
4571 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4572 VkEvent _event,
4573 VkPipelineStageFlags stageMask)
4574 {
4575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4576 RADV_FROM_HANDLE(radv_event, event, _event);
4577
4578 write_event(cmd_buffer, event, stageMask, 1);
4579 }
4580
4581 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4582 VkEvent _event,
4583 VkPipelineStageFlags stageMask)
4584 {
4585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4586 RADV_FROM_HANDLE(radv_event, event, _event);
4587
4588 write_event(cmd_buffer, event, stageMask, 0);
4589 }
4590
4591 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4592 uint32_t eventCount,
4593 const VkEvent* pEvents,
4594 VkPipelineStageFlags srcStageMask,
4595 VkPipelineStageFlags dstStageMask,
4596 uint32_t memoryBarrierCount,
4597 const VkMemoryBarrier* pMemoryBarriers,
4598 uint32_t bufferMemoryBarrierCount,
4599 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4600 uint32_t imageMemoryBarrierCount,
4601 const VkImageMemoryBarrier* pImageMemoryBarriers)
4602 {
4603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4604 struct radv_barrier_info info;
4605
4606 info.eventCount = eventCount;
4607 info.pEvents = pEvents;
4608 info.srcStageMask = 0;
4609
4610 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4611 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4612 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4613 }
4614
4615
4616 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4617 uint32_t deviceMask)
4618 {
4619 /* No-op */
4620 }
4621
4622 /* VK_EXT_conditional_rendering */
4623 void radv_CmdBeginConditionalRenderingEXT(
4624 VkCommandBuffer commandBuffer,
4625 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4626 {
4627 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4628 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4629 bool draw_visible = true;
4630 uint64_t va;
4631
4632 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4633
4634 /* By default, if the 32-bit value at offset in buffer memory is zero,
4635 * then the rendering commands are discarded, otherwise they are
4636 * executed as normal. If the inverted flag is set, all commands are
4637 * discarded if the value is non zero.
4638 */
4639 if (pConditionalRenderingBegin->flags &
4640 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4641 draw_visible = false;
4642 }
4643
4644 /* Enable predication for this command buffer. */
4645 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4646 cmd_buffer->state.predicating = true;
4647
4648 /* Store conditional rendering user info. */
4649 cmd_buffer->state.predication_type = draw_visible;
4650 cmd_buffer->state.predication_va = va;
4651 }
4652
4653 void radv_CmdEndConditionalRenderingEXT(
4654 VkCommandBuffer commandBuffer)
4655 {
4656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4657
4658 /* Disable predication for this command buffer. */
4659 si_emit_set_predication_state(cmd_buffer, false, 0);
4660 cmd_buffer->state.predicating = false;
4661
4662 /* Reset conditional rendering user info. */
4663 cmd_buffer->state.predication_type = -1;
4664 cmd_buffer->state.predication_va = 0;
4665 }
4666
4667 /* VK_EXT_transform_feedback */
4668 void radv_CmdBindTransformFeedbackBuffersEXT(
4669 VkCommandBuffer commandBuffer,
4670 uint32_t firstBinding,
4671 uint32_t bindingCount,
4672 const VkBuffer* pBuffers,
4673 const VkDeviceSize* pOffsets,
4674 const VkDeviceSize* pSizes)
4675 {
4676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4677 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4678 uint8_t enabled_mask = 0;
4679
4680 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4681 for (uint32_t i = 0; i < bindingCount; i++) {
4682 uint32_t idx = firstBinding + i;
4683
4684 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4685 sb[idx].offset = pOffsets[i];
4686 sb[idx].size = pSizes[i];
4687
4688 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4689 sb[idx].buffer->bo);
4690
4691 enabled_mask |= 1 << idx;
4692 }
4693
4694 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4695
4696 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4697 }
4698
4699 static void
4700 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4701 {
4702 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4703 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4704
4705 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4706 radeon_emit(cs,
4707 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4708 S_028B94_RAST_STREAM(0) |
4709 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4710 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4711 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4712 radeon_emit(cs, so->hw_enabled_mask &
4713 so->enabled_stream_buffers_mask);
4714 }
4715
4716 static void
4717 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4718 {
4719 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4720 bool old_streamout_enabled = so->streamout_enabled;
4721 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4722
4723 so->streamout_enabled = enable;
4724
4725 so->hw_enabled_mask = so->enabled_mask |
4726 (so->enabled_mask << 4) |
4727 (so->enabled_mask << 8) |
4728 (so->enabled_mask << 12);
4729
4730 if ((old_streamout_enabled != so->streamout_enabled) ||
4731 (old_hw_enabled_mask != so->hw_enabled_mask))
4732 radv_emit_streamout_enable(cmd_buffer);
4733 }
4734
4735 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4736 {
4737 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4738 unsigned reg_strmout_cntl;
4739
4740 /* The register is at different places on different ASICs. */
4741 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4742 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4743 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4744 } else {
4745 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4746 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4747 }
4748
4749 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4750 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4751
4752 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4753 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4754 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4755 radeon_emit(cs, 0);
4756 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4757 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4758 radeon_emit(cs, 4); /* poll interval */
4759 }
4760
4761 void radv_CmdBeginTransformFeedbackEXT(
4762 VkCommandBuffer commandBuffer,
4763 uint32_t firstCounterBuffer,
4764 uint32_t counterBufferCount,
4765 const VkBuffer* pCounterBuffers,
4766 const VkDeviceSize* pCounterBufferOffsets)
4767 {
4768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4769 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4770 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4771 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4772 uint32_t i;
4773
4774 radv_flush_vgt_streamout(cmd_buffer);
4775
4776 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4777 for_each_bit(i, so->enabled_mask) {
4778 int32_t counter_buffer_idx = i - firstCounterBuffer;
4779 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4780 counter_buffer_idx = -1;
4781
4782 /* SI binds streamout buffers as shader resources.
4783 * VGT only counts primitives and tells the shader through
4784 * SGPRs what to do.
4785 */
4786 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4787 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4788 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4789
4790 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4791 /* The array of counter buffers is optional. */
4792 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4793 uint64_t va = radv_buffer_get_va(buffer->bo);
4794
4795 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4796
4797 /* Append */
4798 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4799 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4800 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4801 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4802 radeon_emit(cs, 0); /* unused */
4803 radeon_emit(cs, 0); /* unused */
4804 radeon_emit(cs, va); /* src address lo */
4805 radeon_emit(cs, va >> 32); /* src address hi */
4806
4807 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4808 } else {
4809 /* Start from the beginning. */
4810 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4811 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4812 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4813 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4814 radeon_emit(cs, 0); /* unused */
4815 radeon_emit(cs, 0); /* unused */
4816 radeon_emit(cs, 0); /* unused */
4817 radeon_emit(cs, 0); /* unused */
4818 }
4819 }
4820
4821 radv_set_streamout_enable(cmd_buffer, true);
4822 }
4823
4824 void radv_CmdEndTransformFeedbackEXT(
4825 VkCommandBuffer commandBuffer,
4826 uint32_t firstCounterBuffer,
4827 uint32_t counterBufferCount,
4828 const VkBuffer* pCounterBuffers,
4829 const VkDeviceSize* pCounterBufferOffsets)
4830 {
4831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4832 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4833 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4834 uint32_t i;
4835
4836 radv_flush_vgt_streamout(cmd_buffer);
4837
4838 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4839 for_each_bit(i, so->enabled_mask) {
4840 int32_t counter_buffer_idx = i - firstCounterBuffer;
4841 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4842 counter_buffer_idx = -1;
4843
4844 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4845 /* The array of counters buffer is optional. */
4846 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4847 uint64_t va = radv_buffer_get_va(buffer->bo);
4848
4849 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4850
4851 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4852 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4853 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4854 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4855 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4856 radeon_emit(cs, va); /* dst address lo */
4857 radeon_emit(cs, va >> 32); /* dst address hi */
4858 radeon_emit(cs, 0); /* unused */
4859 radeon_emit(cs, 0); /* unused */
4860
4861 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4862 }
4863
4864 /* Deactivate transform feedback by zeroing the buffer size.
4865 * The counters (primitives generated, primitives emitted) may
4866 * be enabled even if there is not buffer bound. This ensures
4867 * that the primitives-emitted query won't increment.
4868 */
4869 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4870 }
4871
4872 radv_set_streamout_enable(cmd_buffer, false);
4873 }
4874
4875 void radv_CmdDrawIndirectByteCountEXT(
4876 VkCommandBuffer commandBuffer,
4877 uint32_t instanceCount,
4878 uint32_t firstInstance,
4879 VkBuffer _counterBuffer,
4880 VkDeviceSize counterBufferOffset,
4881 uint32_t counterOffset,
4882 uint32_t vertexStride)
4883 {
4884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4885 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4886 struct radv_draw_info info = {};
4887
4888 info.instance_count = instanceCount;
4889 info.first_instance = firstInstance;
4890 info.strmout_buffer = counterBuffer;
4891 info.strmout_buffer_offset = counterBufferOffset;
4892 info.stride = vertexStride;
4893
4894 radv_draw(cmd_buffer, &info);
4895 }