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1f34d07476701a0d5650bc3b0f40c9081d27c66e
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 return cmd_buffer->record_result;
296 }
297
298 static bool
299 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
300 uint64_t min_needed)
301 {
302 uint64_t new_size;
303 struct radeon_winsys_bo *bo;
304 struct radv_cmd_buffer_upload *upload;
305 struct radv_device *device = cmd_buffer->device;
306
307 new_size = MAX2(min_needed, 16 * 1024);
308 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
309
310 bo = device->ws->buffer_create(device->ws,
311 new_size, 4096,
312 RADEON_DOMAIN_GTT,
313 RADEON_FLAG_CPU_ACCESS|
314 RADEON_FLAG_NO_INTERPROCESS_SHARING);
315
316 if (!bo) {
317 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
318 return false;
319 }
320
321 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
322 if (cmd_buffer->upload.upload_bo) {
323 upload = malloc(sizeof(*upload));
324
325 if (!upload) {
326 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
327 device->ws->buffer_destroy(bo);
328 return false;
329 }
330
331 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
332 list_add(&upload->list, &cmd_buffer->upload.list);
333 }
334
335 cmd_buffer->upload.upload_bo = bo;
336 cmd_buffer->upload.size = new_size;
337 cmd_buffer->upload.offset = 0;
338 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
339
340 if (!cmd_buffer->upload.map) {
341 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
342 return false;
343 }
344
345 return true;
346 }
347
348 bool
349 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
350 unsigned size,
351 unsigned alignment,
352 unsigned *out_offset,
353 void **ptr)
354 {
355 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
356 if (offset + size > cmd_buffer->upload.size) {
357 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
358 return false;
359 offset = 0;
360 }
361
362 *out_offset = offset;
363 *ptr = cmd_buffer->upload.map + offset;
364
365 cmd_buffer->upload.offset = offset + size;
366 return true;
367 }
368
369 bool
370 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
371 unsigned size, unsigned alignment,
372 const void *data, unsigned *out_offset)
373 {
374 uint8_t *ptr;
375
376 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
377 out_offset, (void **)&ptr))
378 return false;
379
380 if (ptr)
381 memcpy(ptr, data, size);
382
383 return true;
384 }
385
386 static void
387 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
388 unsigned count, const uint32_t *data)
389 {
390 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
391 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
392 S_370_WR_CONFIRM(1) |
393 S_370_ENGINE_SEL(V_370_ME));
394 radeon_emit(cs, va);
395 radeon_emit(cs, va >> 32);
396 radeon_emit_array(cs, data, count);
397 }
398
399 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
400 {
401 struct radv_device *device = cmd_buffer->device;
402 struct radeon_winsys_cs *cs = cmd_buffer->cs;
403 uint64_t va;
404
405 va = radv_buffer_get_va(device->trace_bo);
406 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
407 va += 4;
408
409 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
410
411 ++cmd_buffer->state.trace_id;
412 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
413 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
414 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
415 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
416 }
417
418 static void
419 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
420 {
421 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
422 enum radv_cmd_flush_bits flags;
423
424 /* Force wait for graphics/compute engines to be idle. */
425 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
426 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
427
428 si_cs_emit_cache_flush(cmd_buffer->cs, false,
429 cmd_buffer->device->physical_device->rad_info.chip_class,
430 NULL, 0,
431 radv_cmd_buffer_uses_mec(cmd_buffer),
432 flags);
433 }
434
435 if (unlikely(cmd_buffer->device->trace_bo))
436 radv_cmd_buffer_trace_emit(cmd_buffer);
437 }
438
439 static void
440 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
441 struct radv_pipeline *pipeline, enum ring_type ring)
442 {
443 struct radv_device *device = cmd_buffer->device;
444 struct radeon_winsys_cs *cs = cmd_buffer->cs;
445 uint32_t data[2];
446 uint64_t va;
447
448 va = radv_buffer_get_va(device->trace_bo);
449
450 switch (ring) {
451 case RING_GFX:
452 va += 8;
453 break;
454 case RING_COMPUTE:
455 va += 16;
456 break;
457 default:
458 assert(!"invalid ring type");
459 }
460
461 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
462 cmd_buffer->cs, 6);
463
464 data[0] = (uintptr_t)pipeline;
465 data[1] = (uintptr_t)pipeline >> 32;
466
467 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
468 radv_emit_write_data_packet(cs, va, 2, data);
469 }
470
471 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
472 struct radv_descriptor_set *set,
473 unsigned idx)
474 {
475 cmd_buffer->descriptors[idx] = set;
476 if (set)
477 cmd_buffer->state.valid_descriptors |= (1u << idx);
478 else
479 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
480 cmd_buffer->state.descriptors_dirty |= (1u << idx);
481
482 }
483
484 static void
485 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[MAX_SETS * 2] = {};
490 uint64_t va;
491 unsigned i;
492 va = radv_buffer_get_va(device->trace_bo) + 24;
493
494 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
495 cmd_buffer->cs, 4 + MAX_SETS * 2);
496
497 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
498 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
499 data[i * 2] = (uintptr_t)set;
500 data[i * 2 + 1] = (uintptr_t)set >> 32;
501 }
502
503 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
504 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
505 }
506
507 static void
508 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
509 struct radv_pipeline *pipeline)
510 {
511 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
512 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
513 8);
514 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
515 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
516
517 if (cmd_buffer->device->physical_device->has_rbplus) {
518
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
521
522 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
523 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
524 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
525 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
526 }
527 }
528
529 static void
530 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
534 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
535 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
536
537 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
538 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
539 }
540
541 struct ac_userdata_info *
542 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
543 gl_shader_stage stage,
544 int idx)
545 {
546 if (stage == MESA_SHADER_VERTEX) {
547 if (pipeline->shaders[MESA_SHADER_VERTEX])
548 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
549 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
550 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
552 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
553 } else if (stage == MESA_SHADER_TESS_EVAL) {
554 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
555 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
556 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
557 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
558 }
559 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
560 }
561
562 static void
563 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_pipeline *pipeline,
565 gl_shader_stage stage,
566 int idx, uint64_t va)
567 {
568 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
569 uint32_t base_reg = pipeline->user_data_0[stage];
570 if (loc->sgpr_idx == -1)
571 return;
572 assert(loc->num_sgprs == 2);
573 assert(!loc->indirect);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
575 radeon_emit(cmd_buffer->cs, va);
576 radeon_emit(cmd_buffer->cs, va >> 32);
577 }
578
579 static void
580 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
581 struct radv_pipeline *pipeline)
582 {
583 int num_samples = pipeline->graphics.ms.num_samples;
584 struct radv_multisample_state *ms = &pipeline->graphics.ms;
585 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
586
587 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
588 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
589 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
590
591 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
592 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
593
594 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
595 return;
596
597 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
598 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
599 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
600
601 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
602
603 /* GFX9: Flush DFSM when the AA mode changes. */
604 if (cmd_buffer->device->dfsm_allowed) {
605 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
606 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
607 }
608 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
609 uint32_t offset;
610 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
611 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
612 if (loc->sgpr_idx == -1)
613 return;
614 assert(loc->num_sgprs == 1);
615 assert(!loc->indirect);
616 switch (num_samples) {
617 default:
618 offset = 0;
619 break;
620 case 2:
621 offset = 1;
622 break;
623 case 4:
624 offset = 3;
625 break;
626 case 8:
627 offset = 7;
628 break;
629 case 16:
630 offset = 15;
631 break;
632 }
633
634 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
635 cmd_buffer->sample_positions_needed = true;
636 }
637 }
638
639 static void
640 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
641 struct radv_pipeline *pipeline)
642 {
643 struct radv_raster_state *raster = &pipeline->graphics.raster;
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
646 raster->pa_cl_clip_cntl);
647 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
648 raster->spi_interp_control);
649 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
650 raster->pa_su_vtx_cntl);
651 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
652 raster->pa_su_sc_mode_cntl);
653 }
654
655 static inline void
656 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
657 unsigned size)
658 {
659 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
660 si_cp_dma_prefetch(cmd_buffer, va, size);
661 }
662
663 static void
664 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
665 {
666 if (cmd_buffer->state.vb_prefetch_dirty) {
667 radv_emit_prefetch_TC_L2_async(cmd_buffer,
668 cmd_buffer->state.vb_va,
669 cmd_buffer->state.vb_size);
670 cmd_buffer->state.vb_prefetch_dirty = false;
671 }
672 }
673
674 static void
675 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
676 struct radv_shader_variant *shader)
677 {
678 struct radeon_winsys *ws = cmd_buffer->device->ws;
679 struct radeon_winsys_cs *cs = cmd_buffer->cs;
680 uint64_t va;
681
682 if (!shader)
683 return;
684
685 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
686
687 radv_cs_add_buffer(ws, cs, shader->bo, 8);
688 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
689 }
690
691 static void
692 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
693 struct radv_pipeline *pipeline)
694 {
695 radv_emit_shader_prefetch(cmd_buffer,
696 pipeline->shaders[MESA_SHADER_VERTEX]);
697 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_GEOMETRY]);
704 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_FRAGMENT]);
707 }
708
709 static void
710 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
711 struct radv_pipeline *pipeline,
712 struct radv_shader_variant *shader)
713 {
714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
715
716 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
717 pipeline->graphics.vs.spi_vs_out_config);
718
719 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
720 pipeline->graphics.vs.spi_shader_pos_format);
721
722 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
723 radeon_emit(cmd_buffer->cs, va >> 8);
724 radeon_emit(cmd_buffer->cs, va >> 40);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2);
727
728 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
729 S_028818_VTX_W0_FMT(1) |
730 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
731 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
732 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
733
734
735 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
736 pipeline->graphics.vs.pa_cl_vs_out_cntl);
737
738 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
739 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
740 pipeline->graphics.vs.vgt_reuse_off);
741 }
742
743 static void
744 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_pipeline *pipeline,
746 struct radv_shader_variant *shader)
747 {
748 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
749
750 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
751 radeon_emit(cmd_buffer->cs, va >> 8);
752 radeon_emit(cmd_buffer->cs, va >> 40);
753 radeon_emit(cmd_buffer->cs, shader->rsrc1);
754 radeon_emit(cmd_buffer->cs, shader->rsrc2);
755 }
756
757 static void
758 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
759 struct radv_shader_variant *shader)
760 {
761 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
762 uint32_t rsrc2 = shader->rsrc2;
763
764 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
765 radeon_emit(cmd_buffer->cs, va >> 8);
766 radeon_emit(cmd_buffer->cs, va >> 40);
767
768 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
769 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
770 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
771 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
772
773 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
774 radeon_emit(cmd_buffer->cs, shader->rsrc1);
775 radeon_emit(cmd_buffer->cs, rsrc2);
776 }
777
778 static void
779 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
780 struct radv_shader_variant *shader)
781 {
782 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
783
784 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
785 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
786 radeon_emit(cmd_buffer->cs, va >> 8);
787 radeon_emit(cmd_buffer->cs, va >> 40);
788
789 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
790 radeon_emit(cmd_buffer->cs, shader->rsrc1);
791 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
792 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
793 } else {
794 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
795 radeon_emit(cmd_buffer->cs, va >> 8);
796 radeon_emit(cmd_buffer->cs, va >> 40);
797 radeon_emit(cmd_buffer->cs, shader->rsrc1);
798 radeon_emit(cmd_buffer->cs, shader->rsrc2);
799 }
800 }
801
802 static void
803 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_pipeline *pipeline)
805 {
806 struct radv_shader_variant *vs;
807
808 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
809
810 /* Skip shaders merged into HS/GS */
811 vs = pipeline->shaders[MESA_SHADER_VERTEX];
812 if (!vs)
813 return;
814
815 if (vs->info.vs.as_ls)
816 radv_emit_hw_ls(cmd_buffer, vs);
817 else if (vs->info.vs.as_es)
818 radv_emit_hw_es(cmd_buffer, pipeline, vs);
819 else
820 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
821 }
822
823
824 static void
825 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
826 struct radv_pipeline *pipeline)
827 {
828 if (!radv_pipeline_has_tess(pipeline))
829 return;
830
831 struct radv_shader_variant *tes, *tcs;
832
833 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
834 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
835
836 if (tes) {
837 if (tes->info.tes.as_es)
838 radv_emit_hw_es(cmd_buffer, pipeline, tes);
839 else
840 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
841 }
842
843 radv_emit_hw_hs(cmd_buffer, tcs);
844
845 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
846 pipeline->graphics.tess.tf_param);
847
848 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
849 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
850 pipeline->graphics.tess.ls_hs_config);
851 else
852 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
853 pipeline->graphics.tess.ls_hs_config);
854
855 struct ac_userdata_info *loc;
856
857 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
858 if (loc->sgpr_idx != -1) {
859 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
860 assert(loc->num_sgprs == 4);
861 assert(!loc->indirect);
862 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
866 pipeline->graphics.tess.num_tcs_input_cp << 26);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
868 }
869
870 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
871 if (loc->sgpr_idx != -1) {
872 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
873 assert(loc->num_sgprs == 1);
874 assert(!loc->indirect);
875
876 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
877 pipeline->graphics.tess.offchip_layout);
878 }
879
880 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
881 if (loc->sgpr_idx != -1) {
882 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
883 assert(loc->num_sgprs == 1);
884 assert(!loc->indirect);
885
886 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
887 pipeline->graphics.tess.tcs_in_layout);
888 }
889 }
890
891 static void
892 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
893 struct radv_pipeline *pipeline)
894 {
895 struct radv_shader_variant *gs;
896 uint64_t va;
897
898 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
899
900 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
901 if (!gs)
902 return;
903
904 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
905
906 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
907 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
908 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910
911 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
914
915 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
916 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
917 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
918 radeon_emit(cmd_buffer->cs, 0);
919 radeon_emit(cmd_buffer->cs, 0);
920 radeon_emit(cmd_buffer->cs, 0);
921
922 uint32_t gs_num_invocations = gs->info.gs.invocations;
923 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
924 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
925 S_028B90_ENABLE(gs_num_invocations > 0));
926
927 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
928 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
929
930 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
931
932 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
933 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
934 radeon_emit(cmd_buffer->cs, va >> 8);
935 radeon_emit(cmd_buffer->cs, va >> 40);
936
937 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
938 radeon_emit(cmd_buffer->cs, gs->rsrc1);
939 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
940 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
941
942 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
943 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
944 } else {
945 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
946 radeon_emit(cmd_buffer->cs, va >> 8);
947 radeon_emit(cmd_buffer->cs, va >> 40);
948 radeon_emit(cmd_buffer->cs, gs->rsrc1);
949 radeon_emit(cmd_buffer->cs, gs->rsrc2);
950 }
951
952 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
953
954 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
955 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
956 if (loc->sgpr_idx != -1) {
957 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
958 uint32_t num_entries = 64;
959 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
960
961 if (is_vi)
962 num_entries *= stride;
963
964 stride = S_008F04_STRIDE(stride);
965 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
966 radeon_emit(cmd_buffer->cs, stride);
967 radeon_emit(cmd_buffer->cs, num_entries);
968 }
969 }
970
971 static void
972 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
973 struct radv_pipeline *pipeline)
974 {
975 struct radv_shader_variant *ps;
976 uint64_t va;
977 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
978 struct radv_blend_state *blend = &pipeline->graphics.blend;
979 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
980
981 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
982 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
983
984 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
985 radeon_emit(cmd_buffer->cs, va >> 8);
986 radeon_emit(cmd_buffer->cs, va >> 40);
987 radeon_emit(cmd_buffer->cs, ps->rsrc1);
988 radeon_emit(cmd_buffer->cs, ps->rsrc2);
989
990 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
991 pipeline->graphics.db_shader_control);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
994 ps->config.spi_ps_input_ena);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
997 ps->config.spi_ps_input_addr);
998
999 if (ps->info.info.ps.force_persample)
1000 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1001
1002 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1003 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1008 pipeline->graphics.shader_z_format);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1013 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1014
1015 if (cmd_buffer->device->dfsm_allowed) {
1016 /* optimise this? */
1017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1018 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1019 }
1020
1021 if (pipeline->graphics.ps_input_cntl_num) {
1022 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1023 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1024 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1025 }
1026 }
1027 }
1028
1029 static void
1030 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1031 struct radv_pipeline *pipeline)
1032 {
1033 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1034
1035 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1036 return;
1037
1038 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1039 pipeline->graphics.vtx_reuse_depth);
1040 }
1041
1042 static void
1043 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1044 {
1045 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1046
1047 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1048 return;
1049
1050 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1051 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1052 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1053 radv_update_multisample_state(cmd_buffer, pipeline);
1054 radv_emit_vertex_shader(cmd_buffer, pipeline);
1055 radv_emit_tess_shaders(cmd_buffer, pipeline);
1056 radv_emit_geometry_shader(cmd_buffer, pipeline);
1057 radv_emit_fragment_shader(cmd_buffer, pipeline);
1058 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1059
1060 cmd_buffer->scratch_size_needed =
1061 MAX2(cmd_buffer->scratch_size_needed,
1062 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1063
1064 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1065 S_0286E8_WAVES(pipeline->max_waves) |
1066 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1067
1068 if (!cmd_buffer->state.emitted_pipeline ||
1069 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1070 pipeline->graphics.can_use_guardband)
1071 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1072
1073 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1074
1075 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1076 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1077 } else {
1078 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1079 }
1080 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1081
1082 if (unlikely(cmd_buffer->device->trace_bo))
1083 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1084
1085 cmd_buffer->state.emitted_pipeline = pipeline;
1086
1087 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1088 }
1089
1090 static void
1091 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1092 {
1093 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1094 cmd_buffer->state.dynamic.viewport.viewports);
1095 }
1096
1097 static void
1098 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1099 {
1100 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1101
1102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1103 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1104 si_emit_cache_flush(cmd_buffer);
1105 }
1106 si_write_scissors(cmd_buffer->cs, 0, count,
1107 cmd_buffer->state.dynamic.scissor.scissors,
1108 cmd_buffer->state.dynamic.viewport.viewports,
1109 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1110 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1111 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1112 }
1113
1114 static void
1115 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1116 {
1117 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1118
1119 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1120 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1121 }
1122
1123 static void
1124 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1125 {
1126 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1127
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1129 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1130 }
1131
1132 static void
1133 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1136
1137 radeon_set_context_reg_seq(cmd_buffer->cs,
1138 R_028430_DB_STENCILREFMASK, 2);
1139 radeon_emit(cmd_buffer->cs,
1140 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1141 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1142 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1143 S_028430_STENCILOPVAL(1));
1144 radeon_emit(cmd_buffer->cs,
1145 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1146 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1147 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1148 S_028434_STENCILOPVAL_BF(1));
1149 }
1150
1151 static void
1152 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1153 {
1154 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1155
1156 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1157 fui(d->depth_bounds.min));
1158 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1159 fui(d->depth_bounds.max));
1160 }
1161
1162 static void
1163 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1164 {
1165 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1166 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1167 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1168 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1169
1170 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1171 radeon_set_context_reg_seq(cmd_buffer->cs,
1172 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1173 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1174 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1175 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1176 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1178 }
1179 }
1180
1181 static void
1182 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1183 int index,
1184 struct radv_color_buffer_info *cb)
1185 {
1186 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1187
1188 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1190 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1191 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1192 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1196 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1201
1202 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1203 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1204 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1205
1206 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1207 cb->gfx9_epitch);
1208 } else {
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1210 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1211 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1212 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1216 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1219 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1221
1222 if (is_vi) { /* DCC BASE */
1223 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1224 }
1225 }
1226 }
1227
1228 static void
1229 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1230 struct radv_ds_buffer_info *ds,
1231 struct radv_image *image,
1232 VkImageLayout layout)
1233 {
1234 uint32_t db_z_info = ds->db_z_info;
1235 uint32_t db_stencil_info = ds->db_stencil_info;
1236
1237 if (!radv_layout_has_htile(image, layout,
1238 radv_image_queue_family_mask(image,
1239 cmd_buffer->queue_family_index,
1240 cmd_buffer->queue_family_index))) {
1241 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1242 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1243 }
1244
1245 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1246 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1247
1248
1249 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1250 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1251 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1252 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1253 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1254
1255 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1256 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1257 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1258 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1259 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1260 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1261 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1263 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1265 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1266
1267 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1268 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1269 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1270 } else {
1271 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1272
1273 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1274 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1275 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1276 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1277 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1278 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1279 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1280 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1282 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1283
1284 }
1285
1286 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1287 ds->pa_su_poly_offset_db_fmt_cntl);
1288 }
1289
1290 void
1291 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_image *image,
1293 VkClearDepthStencilValue ds_clear_value,
1294 VkImageAspectFlags aspects)
1295 {
1296 uint64_t va = radv_buffer_get_va(image->bo);
1297 va += image->offset + image->clear_value_offset;
1298 unsigned reg_offset = 0, reg_count = 0;
1299
1300 if (!image->surface.htile_size || !aspects)
1301 return;
1302
1303 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1304 ++reg_count;
1305 } else {
1306 ++reg_offset;
1307 va += 4;
1308 }
1309 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1310 ++reg_count;
1311
1312 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1313
1314 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1315 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP));
1318 radeon_emit(cmd_buffer->cs, va);
1319 radeon_emit(cmd_buffer->cs, va >> 32);
1320 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1321 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1322 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1323 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1324
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1326 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1327 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1328 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1329 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1330 }
1331
1332 static void
1333 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1334 struct radv_image *image)
1335 {
1336 uint64_t va = radv_buffer_get_va(image->bo);
1337 va += image->offset + image->clear_value_offset;
1338
1339 if (!image->surface.htile_size)
1340 return;
1341
1342
1343 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1344 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1345 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1346 COPY_DATA_COUNT_SEL);
1347 radeon_emit(cmd_buffer->cs, va);
1348 radeon_emit(cmd_buffer->cs, va >> 32);
1349 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1350 radeon_emit(cmd_buffer->cs, 0);
1351
1352 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1353 radeon_emit(cmd_buffer->cs, 0);
1354 }
1355
1356 /*
1357 *with DCC some colors don't require CMASK elimiation before being
1358 * used as a texture. This sets a predicate value to determine if the
1359 * cmask eliminate is required.
1360 */
1361 void
1362 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1363 struct radv_image *image,
1364 bool value)
1365 {
1366 uint64_t pred_val = value;
1367 uint64_t va = radv_buffer_get_va(image->bo);
1368 va += image->offset + image->dcc_pred_offset;
1369
1370 if (!image->surface.dcc_size)
1371 return;
1372
1373 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1374
1375 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1376 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1377 S_370_WR_CONFIRM(1) |
1378 S_370_ENGINE_SEL(V_370_PFP));
1379 radeon_emit(cmd_buffer->cs, va);
1380 radeon_emit(cmd_buffer->cs, va >> 32);
1381 radeon_emit(cmd_buffer->cs, pred_val);
1382 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1383 }
1384
1385 void
1386 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1387 struct radv_image *image,
1388 int idx,
1389 uint32_t color_values[2])
1390 {
1391 uint64_t va = radv_buffer_get_va(image->bo);
1392 va += image->offset + image->clear_value_offset;
1393
1394 if (!image->cmask.size && !image->surface.dcc_size)
1395 return;
1396
1397 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1398
1399 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1400 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1401 S_370_WR_CONFIRM(1) |
1402 S_370_ENGINE_SEL(V_370_PFP));
1403 radeon_emit(cmd_buffer->cs, va);
1404 radeon_emit(cmd_buffer->cs, va >> 32);
1405 radeon_emit(cmd_buffer->cs, color_values[0]);
1406 radeon_emit(cmd_buffer->cs, color_values[1]);
1407
1408 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1409 radeon_emit(cmd_buffer->cs, color_values[0]);
1410 radeon_emit(cmd_buffer->cs, color_values[1]);
1411 }
1412
1413 static void
1414 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1415 struct radv_image *image,
1416 int idx)
1417 {
1418 uint64_t va = radv_buffer_get_va(image->bo);
1419 va += image->offset + image->clear_value_offset;
1420
1421 if (!image->cmask.size && !image->surface.dcc_size)
1422 return;
1423
1424 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1425
1426 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1427 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1428 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1429 COPY_DATA_COUNT_SEL);
1430 radeon_emit(cmd_buffer->cs, va);
1431 radeon_emit(cmd_buffer->cs, va >> 32);
1432 radeon_emit(cmd_buffer->cs, reg >> 2);
1433 radeon_emit(cmd_buffer->cs, 0);
1434
1435 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1436 radeon_emit(cmd_buffer->cs, 0);
1437 }
1438
1439 static void
1440 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1441 {
1442 int i;
1443 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1444 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1445
1446 /* this may happen for inherited secondary recording */
1447 if (!framebuffer)
1448 return;
1449
1450 for (i = 0; i < 8; ++i) {
1451 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1452 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1453 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1454 continue;
1455 }
1456
1457 int idx = subpass->color_attachments[i].attachment;
1458 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1459
1460 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1461
1462 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1463 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1464
1465 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1466 }
1467
1468 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1469 int idx = subpass->depth_stencil_attachment.attachment;
1470 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1471 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1472 struct radv_image *image = att->attachment->image;
1473 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1474 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1475 cmd_buffer->queue_family_index,
1476 cmd_buffer->queue_family_index);
1477 /* We currently don't support writing decompressed HTILE */
1478 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1479 radv_layout_is_htile_compressed(image, layout, queue_mask));
1480
1481 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1482
1483 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1484 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1485 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1486 }
1487 radv_load_depth_clear_regs(cmd_buffer, image);
1488 } else {
1489 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1491 else
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1493
1494 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1495 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1496 }
1497 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1498 S_028208_BR_X(framebuffer->width) |
1499 S_028208_BR_Y(framebuffer->height));
1500
1501 if (cmd_buffer->device->dfsm_allowed) {
1502 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1503 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1504 }
1505
1506 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1507 }
1508
1509 static void
1510 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1511 {
1512 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1513
1514 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1515 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1516 2, cmd_buffer->state.index_type);
1517 } else {
1518 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1519 radeon_emit(cs, cmd_buffer->state.index_type);
1520 }
1521
1522 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1523 radeon_emit(cs, cmd_buffer->state.index_va);
1524 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1525
1526 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1527 radeon_emit(cs, cmd_buffer->state.max_index_count);
1528
1529 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1530 }
1531
1532 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1533 {
1534 uint32_t db_count_control;
1535
1536 if(!cmd_buffer->state.active_occlusion_queries) {
1537 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1538 db_count_control = 0;
1539 } else {
1540 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1541 }
1542 } else {
1543 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1544 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1545 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1546 S_028004_ZPASS_ENABLE(1) |
1547 S_028004_SLICE_EVEN_ENABLE(1) |
1548 S_028004_SLICE_ODD_ENABLE(1);
1549 } else {
1550 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1551 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1552 }
1553 }
1554
1555 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1556 }
1557
1558 static void
1559 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1560 {
1561 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1562 return;
1563
1564 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1565 radv_emit_viewport(cmd_buffer);
1566
1567 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1568 radv_emit_scissor(cmd_buffer);
1569
1570 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1571 radv_emit_line_width(cmd_buffer);
1572
1573 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1574 radv_emit_blend_constants(cmd_buffer);
1575
1576 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1577 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1578 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1579 radv_emit_stencil(cmd_buffer);
1580
1581 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1582 radv_emit_depth_bounds(cmd_buffer);
1583
1584 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1585 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1586 radv_emit_depth_biais(cmd_buffer);
1587
1588 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1589 }
1590
1591 static void
1592 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1593 struct radv_pipeline *pipeline,
1594 int idx,
1595 uint64_t va,
1596 gl_shader_stage stage)
1597 {
1598 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1599 uint32_t base_reg = pipeline->user_data_0[stage];
1600
1601 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1602 return;
1603
1604 assert(!desc_set_loc->indirect);
1605 assert(desc_set_loc->num_sgprs == 2);
1606 radeon_set_sh_reg_seq(cmd_buffer->cs,
1607 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1608 radeon_emit(cmd_buffer->cs, va);
1609 radeon_emit(cmd_buffer->cs, va >> 32);
1610 }
1611
1612 static void
1613 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1614 VkShaderStageFlags stages,
1615 struct radv_descriptor_set *set,
1616 unsigned idx)
1617 {
1618 if (cmd_buffer->state.pipeline) {
1619 radv_foreach_stage(stage, stages) {
1620 if (cmd_buffer->state.pipeline->shaders[stage])
1621 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1622 idx, set->va,
1623 stage);
1624 }
1625 }
1626
1627 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1628 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1629 idx, set->va,
1630 MESA_SHADER_COMPUTE);
1631 }
1632
1633 static void
1634 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1635 {
1636 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1637 unsigned bo_offset;
1638
1639 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1640 set->mapped_ptr,
1641 &bo_offset))
1642 return;
1643
1644 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1645 set->va += bo_offset;
1646 }
1647
1648 static void
1649 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1650 {
1651 uint32_t size = MAX_SETS * 2 * 4;
1652 uint32_t offset;
1653 void *ptr;
1654
1655 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1656 256, &offset, &ptr))
1657 return;
1658
1659 for (unsigned i = 0; i < MAX_SETS; i++) {
1660 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1661 uint64_t set_va = 0;
1662 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1663 if (cmd_buffer->state.valid_descriptors & (1u << i))
1664 set_va = set->va;
1665 uptr[0] = set_va & 0xffffffff;
1666 uptr[1] = set_va >> 32;
1667 }
1668
1669 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1670 va += offset;
1671
1672 if (cmd_buffer->state.pipeline) {
1673 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1674 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1675 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1676
1677 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680
1681 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692 }
1693
1694 if (cmd_buffer->state.compute_pipeline)
1695 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1697 }
1698
1699 static void
1700 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1701 VkShaderStageFlags stages)
1702 {
1703 unsigned i;
1704
1705 if (!cmd_buffer->state.descriptors_dirty)
1706 return;
1707
1708 if (cmd_buffer->state.push_descriptors_dirty)
1709 radv_flush_push_descriptors(cmd_buffer);
1710
1711 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1712 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1713 radv_flush_indirect_descriptor_sets(cmd_buffer);
1714 }
1715
1716 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1717 cmd_buffer->cs,
1718 MAX_SETS * MESA_SHADER_STAGES * 4);
1719
1720 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1721 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1722 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1723 continue;
1724
1725 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1726 }
1727 cmd_buffer->state.descriptors_dirty = 0;
1728 cmd_buffer->state.push_descriptors_dirty = false;
1729
1730 if (unlikely(cmd_buffer->device->trace_bo))
1731 radv_save_descriptors(cmd_buffer);
1732
1733 assert(cmd_buffer->cs->cdw <= cdw_max);
1734 }
1735
1736 static void
1737 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1738 struct radv_pipeline *pipeline,
1739 VkShaderStageFlags stages)
1740 {
1741 struct radv_pipeline_layout *layout = pipeline->layout;
1742 unsigned offset;
1743 void *ptr;
1744 uint64_t va;
1745
1746 stages &= cmd_buffer->push_constant_stages;
1747 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1748 return;
1749
1750 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1751 16 * layout->dynamic_offset_count,
1752 256, &offset, &ptr))
1753 return;
1754
1755 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1756 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1757 16 * layout->dynamic_offset_count);
1758
1759 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1760 va += offset;
1761
1762 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1763 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1764
1765 radv_foreach_stage(stage, stages) {
1766 if (pipeline->shaders[stage]) {
1767 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1768 AC_UD_PUSH_CONSTANTS, va);
1769 }
1770 }
1771
1772 cmd_buffer->push_constant_stages &= ~stages;
1773 assert(cmd_buffer->cs->cdw <= cdw_max);
1774 }
1775
1776 static bool
1777 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1778 {
1779 struct radv_device *device = cmd_buffer->device;
1780
1781 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1782 cmd_buffer->state.pipeline->vertex_elements.count &&
1783 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1784 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1785 unsigned vb_offset;
1786 void *vb_ptr;
1787 uint32_t i = 0;
1788 uint32_t count = velems->count;
1789 uint64_t va;
1790
1791 /* allocate some descriptor state for vertex buffers */
1792 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1793 &vb_offset, &vb_ptr))
1794 return false;
1795
1796 for (i = 0; i < count; i++) {
1797 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1798 uint32_t offset;
1799 int vb = velems->binding[i];
1800 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1801 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1802
1803 radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 8);
1804 va = radv_buffer_get_va(buffer->bo);
1805
1806 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1807 va += offset + buffer->offset;
1808 desc[0] = va;
1809 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1810 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1811 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1812 else
1813 desc[2] = buffer->size - offset;
1814 desc[3] = velems->rsrc_word3[i];
1815 }
1816
1817 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1818 va += vb_offset;
1819
1820 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1821 AC_UD_VS_VERTEX_BUFFERS, va);
1822
1823 cmd_buffer->state.vb_va = va;
1824 cmd_buffer->state.vb_size = count * 16;
1825 cmd_buffer->state.vb_prefetch_dirty = true;
1826 }
1827 cmd_buffer->state.vb_dirty = false;
1828
1829 return true;
1830 }
1831
1832 static bool
1833 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1834 {
1835 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1836 return false;
1837
1838 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1839 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1840 VK_SHADER_STAGE_ALL_GRAPHICS);
1841
1842 return true;
1843 }
1844
1845 static void
1846 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1847 bool instanced_draw, bool indirect_draw,
1848 uint32_t draw_vertex_count)
1849 {
1850 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1851 struct radv_cmd_state *state = &cmd_buffer->state;
1852 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1853 uint32_t ia_multi_vgt_param;
1854 int32_t primitive_reset_en;
1855
1856 /* Draw state. */
1857 ia_multi_vgt_param =
1858 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1859 indirect_draw, draw_vertex_count);
1860
1861 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1862 if (info->chip_class >= GFX9) {
1863 radeon_set_uconfig_reg_idx(cs,
1864 R_030960_IA_MULTI_VGT_PARAM,
1865 4, ia_multi_vgt_param);
1866 } else if (info->chip_class >= CIK) {
1867 radeon_set_context_reg_idx(cs,
1868 R_028AA8_IA_MULTI_VGT_PARAM,
1869 1, ia_multi_vgt_param);
1870 } else {
1871 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1872 ia_multi_vgt_param);
1873 }
1874 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1875 }
1876
1877 /* Primitive restart. */
1878 primitive_reset_en =
1879 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1880
1881 if (primitive_reset_en != state->last_primitive_reset_en) {
1882 state->last_primitive_reset_en = primitive_reset_en;
1883 if (info->chip_class >= GFX9) {
1884 radeon_set_uconfig_reg(cs,
1885 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1886 primitive_reset_en);
1887 } else {
1888 radeon_set_context_reg(cs,
1889 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1890 primitive_reset_en);
1891 }
1892 }
1893
1894 if (primitive_reset_en) {
1895 uint32_t primitive_reset_index =
1896 state->index_type ? 0xffffffffu : 0xffffu;
1897
1898 if (primitive_reset_index != state->last_primitive_reset_index) {
1899 radeon_set_context_reg(cs,
1900 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1901 primitive_reset_index);
1902 state->last_primitive_reset_index = primitive_reset_index;
1903 }
1904 }
1905 }
1906
1907 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1908 VkPipelineStageFlags src_stage_mask)
1909 {
1910 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1911 VK_PIPELINE_STAGE_TRANSFER_BIT |
1912 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1913 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1914 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1915 }
1916
1917 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1918 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1919 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1920 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1921 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1922 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1923 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1924 VK_PIPELINE_STAGE_TRANSFER_BIT |
1925 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1926 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1927 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1928 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1929 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1930 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1931 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1932 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1933 }
1934 }
1935
1936 static enum radv_cmd_flush_bits
1937 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1938 VkAccessFlags src_flags)
1939 {
1940 enum radv_cmd_flush_bits flush_bits = 0;
1941 uint32_t b;
1942 for_each_bit(b, src_flags) {
1943 switch ((VkAccessFlagBits)(1 << b)) {
1944 case VK_ACCESS_SHADER_WRITE_BIT:
1945 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1946 break;
1947 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1948 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1949 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1950 break;
1951 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1952 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1953 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1954 break;
1955 case VK_ACCESS_TRANSFER_WRITE_BIT:
1956 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1957 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1958 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1959 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1960 RADV_CMD_FLAG_INV_GLOBAL_L2;
1961 break;
1962 default:
1963 break;
1964 }
1965 }
1966 return flush_bits;
1967 }
1968
1969 static enum radv_cmd_flush_bits
1970 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1971 VkAccessFlags dst_flags,
1972 struct radv_image *image)
1973 {
1974 enum radv_cmd_flush_bits flush_bits = 0;
1975 uint32_t b;
1976 for_each_bit(b, dst_flags) {
1977 switch ((VkAccessFlagBits)(1 << b)) {
1978 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1979 case VK_ACCESS_INDEX_READ_BIT:
1980 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1981 break;
1982 case VK_ACCESS_UNIFORM_READ_BIT:
1983 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1984 break;
1985 case VK_ACCESS_SHADER_READ_BIT:
1986 case VK_ACCESS_TRANSFER_READ_BIT:
1987 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1988 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1989 RADV_CMD_FLAG_INV_GLOBAL_L2;
1990 break;
1991 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1992 /* TODO: change to image && when the image gets passed
1993 * through from the subpass. */
1994 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1995 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1996 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1997 break;
1998 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1999 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2000 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2001 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2002 break;
2003 default:
2004 break;
2005 }
2006 }
2007 return flush_bits;
2008 }
2009
2010 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2011 {
2012 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2013 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2014 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2015 NULL);
2016 }
2017
2018 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2019 VkAttachmentReference att)
2020 {
2021 unsigned idx = att.attachment;
2022 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2023 VkImageSubresourceRange range;
2024 range.aspectMask = 0;
2025 range.baseMipLevel = view->base_mip;
2026 range.levelCount = 1;
2027 range.baseArrayLayer = view->base_layer;
2028 range.layerCount = cmd_buffer->state.framebuffer->layers;
2029
2030 radv_handle_image_transition(cmd_buffer,
2031 view->image,
2032 cmd_buffer->state.attachments[idx].current_layout,
2033 att.layout, 0, 0, &range,
2034 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2035
2036 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2037
2038
2039 }
2040
2041 void
2042 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2043 const struct radv_subpass *subpass, bool transitions)
2044 {
2045 if (transitions) {
2046 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2047
2048 for (unsigned i = 0; i < subpass->color_count; ++i) {
2049 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2050 radv_handle_subpass_image_transition(cmd_buffer,
2051 subpass->color_attachments[i]);
2052 }
2053
2054 for (unsigned i = 0; i < subpass->input_count; ++i) {
2055 radv_handle_subpass_image_transition(cmd_buffer,
2056 subpass->input_attachments[i]);
2057 }
2058
2059 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2060 radv_handle_subpass_image_transition(cmd_buffer,
2061 subpass->depth_stencil_attachment);
2062 }
2063 }
2064
2065 cmd_buffer->state.subpass = subpass;
2066
2067 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2068 }
2069
2070 static VkResult
2071 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2072 struct radv_render_pass *pass,
2073 const VkRenderPassBeginInfo *info)
2074 {
2075 struct radv_cmd_state *state = &cmd_buffer->state;
2076
2077 if (pass->attachment_count == 0) {
2078 state->attachments = NULL;
2079 return VK_SUCCESS;
2080 }
2081
2082 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2083 pass->attachment_count *
2084 sizeof(state->attachments[0]),
2085 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2086 if (state->attachments == NULL) {
2087 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2088 return cmd_buffer->record_result;
2089 }
2090
2091 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2092 struct radv_render_pass_attachment *att = &pass->attachments[i];
2093 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2094 VkImageAspectFlags clear_aspects = 0;
2095
2096 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2097 /* color attachment */
2098 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2099 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2100 }
2101 } else {
2102 /* depthstencil attachment */
2103 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2104 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2105 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2106 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2107 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2108 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2109 }
2110 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2111 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2112 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2113 }
2114 }
2115
2116 state->attachments[i].pending_clear_aspects = clear_aspects;
2117 state->attachments[i].cleared_views = 0;
2118 if (clear_aspects && info) {
2119 assert(info->clearValueCount > i);
2120 state->attachments[i].clear_value = info->pClearValues[i];
2121 }
2122
2123 state->attachments[i].current_layout = att->initial_layout;
2124 }
2125
2126 return VK_SUCCESS;
2127 }
2128
2129 VkResult radv_AllocateCommandBuffers(
2130 VkDevice _device,
2131 const VkCommandBufferAllocateInfo *pAllocateInfo,
2132 VkCommandBuffer *pCommandBuffers)
2133 {
2134 RADV_FROM_HANDLE(radv_device, device, _device);
2135 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2136
2137 VkResult result = VK_SUCCESS;
2138 uint32_t i;
2139
2140 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2141
2142 if (!list_empty(&pool->free_cmd_buffers)) {
2143 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2144
2145 list_del(&cmd_buffer->pool_link);
2146 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2147
2148 result = radv_reset_cmd_buffer(cmd_buffer);
2149 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2150 cmd_buffer->level = pAllocateInfo->level;
2151
2152 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2153 } else {
2154 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2155 &pCommandBuffers[i]);
2156 }
2157 if (result != VK_SUCCESS)
2158 break;
2159 }
2160
2161 if (result != VK_SUCCESS)
2162 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2163 i, pCommandBuffers);
2164
2165 return result;
2166 }
2167
2168 void radv_FreeCommandBuffers(
2169 VkDevice device,
2170 VkCommandPool commandPool,
2171 uint32_t commandBufferCount,
2172 const VkCommandBuffer *pCommandBuffers)
2173 {
2174 for (uint32_t i = 0; i < commandBufferCount; i++) {
2175 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2176
2177 if (cmd_buffer) {
2178 if (cmd_buffer->pool) {
2179 list_del(&cmd_buffer->pool_link);
2180 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2181 } else
2182 radv_cmd_buffer_destroy(cmd_buffer);
2183
2184 }
2185 }
2186 }
2187
2188 VkResult radv_ResetCommandBuffer(
2189 VkCommandBuffer commandBuffer,
2190 VkCommandBufferResetFlags flags)
2191 {
2192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2193 return radv_reset_cmd_buffer(cmd_buffer);
2194 }
2195
2196 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2197 {
2198 struct radv_device *device = cmd_buffer->device;
2199 if (device->gfx_init) {
2200 uint64_t va = radv_buffer_get_va(device->gfx_init);
2201 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2202 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2203 radeon_emit(cmd_buffer->cs, va);
2204 radeon_emit(cmd_buffer->cs, va >> 32);
2205 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2206 } else
2207 si_init_config(cmd_buffer);
2208 }
2209
2210 VkResult radv_BeginCommandBuffer(
2211 VkCommandBuffer commandBuffer,
2212 const VkCommandBufferBeginInfo *pBeginInfo)
2213 {
2214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2215 VkResult result;
2216
2217 result = radv_reset_cmd_buffer(cmd_buffer);
2218 if (result != VK_SUCCESS)
2219 return result;
2220
2221 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2222 cmd_buffer->state.last_primitive_reset_en = -1;
2223 cmd_buffer->usage_flags = pBeginInfo->flags;
2224
2225 /* setup initial configuration into command buffer */
2226 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2227 switch (cmd_buffer->queue_family_index) {
2228 case RADV_QUEUE_GENERAL:
2229 emit_gfx_buffer_state(cmd_buffer);
2230 break;
2231 case RADV_QUEUE_COMPUTE:
2232 si_init_compute(cmd_buffer);
2233 break;
2234 case RADV_QUEUE_TRANSFER:
2235 default:
2236 break;
2237 }
2238 }
2239
2240 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2241 assert(pBeginInfo->pInheritanceInfo);
2242 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2243 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2244
2245 struct radv_subpass *subpass =
2246 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2247
2248 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2249 if (result != VK_SUCCESS)
2250 return result;
2251
2252 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2253 }
2254
2255 if (unlikely(cmd_buffer->device->trace_bo))
2256 radv_cmd_buffer_trace_emit(cmd_buffer);
2257
2258 return result;
2259 }
2260
2261 void radv_CmdBindVertexBuffers(
2262 VkCommandBuffer commandBuffer,
2263 uint32_t firstBinding,
2264 uint32_t bindingCount,
2265 const VkBuffer* pBuffers,
2266 const VkDeviceSize* pOffsets)
2267 {
2268 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2269 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2270 bool changed = false;
2271
2272 /* We have to defer setting up vertex buffer since we need the buffer
2273 * stride from the pipeline. */
2274
2275 assert(firstBinding + bindingCount <= MAX_VBS);
2276 for (uint32_t i = 0; i < bindingCount; i++) {
2277 uint32_t idx = firstBinding + i;
2278
2279 if (!changed &&
2280 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2281 vb[idx].offset != pOffsets[i])) {
2282 changed = true;
2283 }
2284
2285 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2286 vb[idx].offset = pOffsets[i];
2287 }
2288
2289 if (!changed) {
2290 /* No state changes. */
2291 return;
2292 }
2293
2294 cmd_buffer->state.vb_dirty = true;
2295 }
2296
2297 void radv_CmdBindIndexBuffer(
2298 VkCommandBuffer commandBuffer,
2299 VkBuffer buffer,
2300 VkDeviceSize offset,
2301 VkIndexType indexType)
2302 {
2303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2304 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2305
2306 if (cmd_buffer->state.index_buffer == index_buffer &&
2307 cmd_buffer->state.index_offset == offset &&
2308 cmd_buffer->state.index_type == indexType) {
2309 /* No state changes. */
2310 return;
2311 }
2312
2313 cmd_buffer->state.index_buffer = index_buffer;
2314 cmd_buffer->state.index_offset = offset;
2315 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2316 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2317 cmd_buffer->state.index_va += index_buffer->offset + offset;
2318
2319 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2320 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2321 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2322 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2323 }
2324
2325
2326 static void
2327 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2328 struct radv_descriptor_set *set, unsigned idx)
2329 {
2330 struct radeon_winsys *ws = cmd_buffer->device->ws;
2331
2332 radv_set_descriptor_set(cmd_buffer, set, idx);
2333 if (!set)
2334 return;
2335
2336 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2337
2338 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2339 if (set->descriptors[j])
2340 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2341
2342 if(set->bo)
2343 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2344 }
2345
2346 void radv_CmdBindDescriptorSets(
2347 VkCommandBuffer commandBuffer,
2348 VkPipelineBindPoint pipelineBindPoint,
2349 VkPipelineLayout _layout,
2350 uint32_t firstSet,
2351 uint32_t descriptorSetCount,
2352 const VkDescriptorSet* pDescriptorSets,
2353 uint32_t dynamicOffsetCount,
2354 const uint32_t* pDynamicOffsets)
2355 {
2356 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2357 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2358 unsigned dyn_idx = 0;
2359
2360 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2361 unsigned idx = i + firstSet;
2362 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2363 radv_bind_descriptor_set(cmd_buffer, set, idx);
2364
2365 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2366 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2367 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2368 assert(dyn_idx < dynamicOffsetCount);
2369
2370 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2371 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2372 dst[0] = va;
2373 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2374 dst[2] = range->size;
2375 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2376 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2377 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2378 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2379 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2380 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2381 cmd_buffer->push_constant_stages |=
2382 set->layout->dynamic_shader_stages;
2383 }
2384 }
2385 }
2386
2387 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2388 struct radv_descriptor_set *set,
2389 struct radv_descriptor_set_layout *layout)
2390 {
2391 set->size = layout->size;
2392 set->layout = layout;
2393
2394 if (cmd_buffer->push_descriptors.capacity < set->size) {
2395 size_t new_size = MAX2(set->size, 1024);
2396 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2397 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2398
2399 free(set->mapped_ptr);
2400 set->mapped_ptr = malloc(new_size);
2401
2402 if (!set->mapped_ptr) {
2403 cmd_buffer->push_descriptors.capacity = 0;
2404 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2405 return false;
2406 }
2407
2408 cmd_buffer->push_descriptors.capacity = new_size;
2409 }
2410
2411 return true;
2412 }
2413
2414 void radv_meta_push_descriptor_set(
2415 struct radv_cmd_buffer* cmd_buffer,
2416 VkPipelineBindPoint pipelineBindPoint,
2417 VkPipelineLayout _layout,
2418 uint32_t set,
2419 uint32_t descriptorWriteCount,
2420 const VkWriteDescriptorSet* pDescriptorWrites)
2421 {
2422 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2423 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2424 unsigned bo_offset;
2425
2426 assert(set == 0);
2427 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2428
2429 push_set->size = layout->set[set].layout->size;
2430 push_set->layout = layout->set[set].layout;
2431
2432 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2433 &bo_offset,
2434 (void**) &push_set->mapped_ptr))
2435 return;
2436
2437 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2438 push_set->va += bo_offset;
2439
2440 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2441 radv_descriptor_set_to_handle(push_set),
2442 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2443
2444 radv_set_descriptor_set(cmd_buffer, push_set, set);
2445 }
2446
2447 void radv_CmdPushDescriptorSetKHR(
2448 VkCommandBuffer commandBuffer,
2449 VkPipelineBindPoint pipelineBindPoint,
2450 VkPipelineLayout _layout,
2451 uint32_t set,
2452 uint32_t descriptorWriteCount,
2453 const VkWriteDescriptorSet* pDescriptorWrites)
2454 {
2455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2456 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2457 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2458
2459 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2460
2461 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2462 return;
2463
2464 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2465 radv_descriptor_set_to_handle(push_set),
2466 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2467
2468 radv_set_descriptor_set(cmd_buffer, push_set, set);
2469 cmd_buffer->state.push_descriptors_dirty = true;
2470 }
2471
2472 void radv_CmdPushDescriptorSetWithTemplateKHR(
2473 VkCommandBuffer commandBuffer,
2474 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2475 VkPipelineLayout _layout,
2476 uint32_t set,
2477 const void* pData)
2478 {
2479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2480 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2481 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2482
2483 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2484
2485 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2486 return;
2487
2488 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2489 descriptorUpdateTemplate, pData);
2490
2491 radv_set_descriptor_set(cmd_buffer, push_set, set);
2492 cmd_buffer->state.push_descriptors_dirty = true;
2493 }
2494
2495 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2496 VkPipelineLayout layout,
2497 VkShaderStageFlags stageFlags,
2498 uint32_t offset,
2499 uint32_t size,
2500 const void* pValues)
2501 {
2502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2503 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2504 cmd_buffer->push_constant_stages |= stageFlags;
2505 }
2506
2507 VkResult radv_EndCommandBuffer(
2508 VkCommandBuffer commandBuffer)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2511
2512 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2513 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2514 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2515 si_emit_cache_flush(cmd_buffer);
2516 }
2517
2518 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2519
2520 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2521 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2522
2523 return cmd_buffer->record_result;
2524 }
2525
2526 static void
2527 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2528 {
2529 struct radv_shader_variant *compute_shader;
2530 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2531 uint64_t va;
2532
2533 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2534 return;
2535
2536 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2537
2538 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2539 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2540
2541 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2542 cmd_buffer->cs, 16);
2543
2544 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2545 radeon_emit(cmd_buffer->cs, va >> 8);
2546 radeon_emit(cmd_buffer->cs, va >> 40);
2547
2548 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2549 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2550 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2551
2552
2553 cmd_buffer->compute_scratch_size_needed =
2554 MAX2(cmd_buffer->compute_scratch_size_needed,
2555 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2556
2557 /* change these once we have scratch support */
2558 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2559 S_00B860_WAVES(pipeline->max_waves) |
2560 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2561
2562 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2563 radeon_emit(cmd_buffer->cs,
2564 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2565 radeon_emit(cmd_buffer->cs,
2566 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2567 radeon_emit(cmd_buffer->cs,
2568 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2569
2570 assert(cmd_buffer->cs->cdw <= cdw_max);
2571
2572 if (unlikely(cmd_buffer->device->trace_bo))
2573 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2574 }
2575
2576 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2577 {
2578 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2579 }
2580
2581 void radv_CmdBindPipeline(
2582 VkCommandBuffer commandBuffer,
2583 VkPipelineBindPoint pipelineBindPoint,
2584 VkPipeline _pipeline)
2585 {
2586 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2587 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2588
2589 switch (pipelineBindPoint) {
2590 case VK_PIPELINE_BIND_POINT_COMPUTE:
2591 if (cmd_buffer->state.compute_pipeline == pipeline)
2592 return;
2593 radv_mark_descriptor_sets_dirty(cmd_buffer);
2594
2595 cmd_buffer->state.compute_pipeline = pipeline;
2596 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2597 break;
2598 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2599 if (cmd_buffer->state.pipeline == pipeline)
2600 return;
2601 radv_mark_descriptor_sets_dirty(cmd_buffer);
2602
2603 cmd_buffer->state.pipeline = pipeline;
2604 if (!pipeline)
2605 break;
2606
2607 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2608 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2609
2610 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2611
2612 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2613 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2614 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2615 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2616
2617 if (radv_pipeline_has_tess(pipeline))
2618 cmd_buffer->tess_rings_needed = true;
2619
2620 if (radv_pipeline_has_gs(pipeline)) {
2621 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2622 AC_UD_SCRATCH_RING_OFFSETS);
2623 if (cmd_buffer->ring_offsets_idx == -1)
2624 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2625 else if (loc->sgpr_idx != -1)
2626 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2627 }
2628 break;
2629 default:
2630 assert(!"invalid bind point");
2631 break;
2632 }
2633 }
2634
2635 void radv_CmdSetViewport(
2636 VkCommandBuffer commandBuffer,
2637 uint32_t firstViewport,
2638 uint32_t viewportCount,
2639 const VkViewport* pViewports)
2640 {
2641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2642 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2643
2644 assert(firstViewport < MAX_VIEWPORTS);
2645 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2646
2647 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2648 pViewports, viewportCount * sizeof(*pViewports));
2649
2650 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2651 }
2652
2653 void radv_CmdSetScissor(
2654 VkCommandBuffer commandBuffer,
2655 uint32_t firstScissor,
2656 uint32_t scissorCount,
2657 const VkRect2D* pScissors)
2658 {
2659 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2660 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2661
2662 assert(firstScissor < MAX_SCISSORS);
2663 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2664
2665 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2666 pScissors, scissorCount * sizeof(*pScissors));
2667 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2668 }
2669
2670 void radv_CmdSetLineWidth(
2671 VkCommandBuffer commandBuffer,
2672 float lineWidth)
2673 {
2674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2675 cmd_buffer->state.dynamic.line_width = lineWidth;
2676 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2677 }
2678
2679 void radv_CmdSetDepthBias(
2680 VkCommandBuffer commandBuffer,
2681 float depthBiasConstantFactor,
2682 float depthBiasClamp,
2683 float depthBiasSlopeFactor)
2684 {
2685 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2686
2687 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2688 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2689 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2690
2691 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2692 }
2693
2694 void radv_CmdSetBlendConstants(
2695 VkCommandBuffer commandBuffer,
2696 const float blendConstants[4])
2697 {
2698 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2699
2700 memcpy(cmd_buffer->state.dynamic.blend_constants,
2701 blendConstants, sizeof(float) * 4);
2702
2703 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2704 }
2705
2706 void radv_CmdSetDepthBounds(
2707 VkCommandBuffer commandBuffer,
2708 float minDepthBounds,
2709 float maxDepthBounds)
2710 {
2711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2712
2713 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2714 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2715
2716 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2717 }
2718
2719 void radv_CmdSetStencilCompareMask(
2720 VkCommandBuffer commandBuffer,
2721 VkStencilFaceFlags faceMask,
2722 uint32_t compareMask)
2723 {
2724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2725
2726 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2727 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2728 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2729 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2730
2731 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2732 }
2733
2734 void radv_CmdSetStencilWriteMask(
2735 VkCommandBuffer commandBuffer,
2736 VkStencilFaceFlags faceMask,
2737 uint32_t writeMask)
2738 {
2739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2740
2741 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2742 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2743 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2744 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2745
2746 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2747 }
2748
2749 void radv_CmdSetStencilReference(
2750 VkCommandBuffer commandBuffer,
2751 VkStencilFaceFlags faceMask,
2752 uint32_t reference)
2753 {
2754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2755
2756 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2757 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2758 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2759 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2760
2761 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2762 }
2763
2764 void radv_CmdExecuteCommands(
2765 VkCommandBuffer commandBuffer,
2766 uint32_t commandBufferCount,
2767 const VkCommandBuffer* pCmdBuffers)
2768 {
2769 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2770
2771 assert(commandBufferCount > 0);
2772
2773 /* Emit pending flushes on primary prior to executing secondary */
2774 si_emit_cache_flush(primary);
2775
2776 for (uint32_t i = 0; i < commandBufferCount; i++) {
2777 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2778
2779 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2780 secondary->scratch_size_needed);
2781 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2782 secondary->compute_scratch_size_needed);
2783
2784 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2785 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2786 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2787 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2788 if (secondary->tess_rings_needed)
2789 primary->tess_rings_needed = true;
2790 if (secondary->sample_positions_needed)
2791 primary->sample_positions_needed = true;
2792
2793 if (secondary->ring_offsets_idx != -1) {
2794 if (primary->ring_offsets_idx == -1)
2795 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2796 else
2797 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2798 }
2799 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2800
2801
2802 /* When the secondary command buffer is compute only we don't
2803 * need to re-emit the current graphics pipeline.
2804 */
2805 if (secondary->state.emitted_pipeline) {
2806 primary->state.emitted_pipeline =
2807 secondary->state.emitted_pipeline;
2808 }
2809
2810 /* When the secondary command buffer is graphics only we don't
2811 * need to re-emit the current compute pipeline.
2812 */
2813 if (secondary->state.emitted_compute_pipeline) {
2814 primary->state.emitted_compute_pipeline =
2815 secondary->state.emitted_compute_pipeline;
2816 }
2817
2818 /* Only re-emit the draw packets when needed. */
2819 if (secondary->state.last_primitive_reset_en != -1) {
2820 primary->state.last_primitive_reset_en =
2821 secondary->state.last_primitive_reset_en;
2822 }
2823
2824 if (secondary->state.last_primitive_reset_index) {
2825 primary->state.last_primitive_reset_index =
2826 secondary->state.last_primitive_reset_index;
2827 }
2828
2829 if (secondary->state.last_ia_multi_vgt_param) {
2830 primary->state.last_ia_multi_vgt_param =
2831 secondary->state.last_ia_multi_vgt_param;
2832 }
2833 }
2834
2835 /* After executing commands from secondary buffers we have to dirty
2836 * some states.
2837 */
2838 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2839 RADV_CMD_DIRTY_INDEX_BUFFER |
2840 RADV_CMD_DIRTY_DYNAMIC_ALL;
2841 radv_mark_descriptor_sets_dirty(primary);
2842 }
2843
2844 VkResult radv_CreateCommandPool(
2845 VkDevice _device,
2846 const VkCommandPoolCreateInfo* pCreateInfo,
2847 const VkAllocationCallbacks* pAllocator,
2848 VkCommandPool* pCmdPool)
2849 {
2850 RADV_FROM_HANDLE(radv_device, device, _device);
2851 struct radv_cmd_pool *pool;
2852
2853 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2854 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2855 if (pool == NULL)
2856 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2857
2858 if (pAllocator)
2859 pool->alloc = *pAllocator;
2860 else
2861 pool->alloc = device->alloc;
2862
2863 list_inithead(&pool->cmd_buffers);
2864 list_inithead(&pool->free_cmd_buffers);
2865
2866 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2867
2868 *pCmdPool = radv_cmd_pool_to_handle(pool);
2869
2870 return VK_SUCCESS;
2871
2872 }
2873
2874 void radv_DestroyCommandPool(
2875 VkDevice _device,
2876 VkCommandPool commandPool,
2877 const VkAllocationCallbacks* pAllocator)
2878 {
2879 RADV_FROM_HANDLE(radv_device, device, _device);
2880 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2881
2882 if (!pool)
2883 return;
2884
2885 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2886 &pool->cmd_buffers, pool_link) {
2887 radv_cmd_buffer_destroy(cmd_buffer);
2888 }
2889
2890 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2891 &pool->free_cmd_buffers, pool_link) {
2892 radv_cmd_buffer_destroy(cmd_buffer);
2893 }
2894
2895 vk_free2(&device->alloc, pAllocator, pool);
2896 }
2897
2898 VkResult radv_ResetCommandPool(
2899 VkDevice device,
2900 VkCommandPool commandPool,
2901 VkCommandPoolResetFlags flags)
2902 {
2903 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2904 VkResult result;
2905
2906 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2907 &pool->cmd_buffers, pool_link) {
2908 result = radv_reset_cmd_buffer(cmd_buffer);
2909 if (result != VK_SUCCESS)
2910 return result;
2911 }
2912
2913 return VK_SUCCESS;
2914 }
2915
2916 void radv_TrimCommandPoolKHR(
2917 VkDevice device,
2918 VkCommandPool commandPool,
2919 VkCommandPoolTrimFlagsKHR flags)
2920 {
2921 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2922
2923 if (!pool)
2924 return;
2925
2926 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2927 &pool->free_cmd_buffers, pool_link) {
2928 radv_cmd_buffer_destroy(cmd_buffer);
2929 }
2930 }
2931
2932 void radv_CmdBeginRenderPass(
2933 VkCommandBuffer commandBuffer,
2934 const VkRenderPassBeginInfo* pRenderPassBegin,
2935 VkSubpassContents contents)
2936 {
2937 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2938 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2939 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2940
2941 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2942 cmd_buffer->cs, 2048);
2943 MAYBE_UNUSED VkResult result;
2944
2945 cmd_buffer->state.framebuffer = framebuffer;
2946 cmd_buffer->state.pass = pass;
2947 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2948
2949 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2950 if (result != VK_SUCCESS)
2951 return;
2952
2953 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2954 assert(cmd_buffer->cs->cdw <= cdw_max);
2955
2956 radv_cmd_buffer_clear_subpass(cmd_buffer);
2957 }
2958
2959 void radv_CmdNextSubpass(
2960 VkCommandBuffer commandBuffer,
2961 VkSubpassContents contents)
2962 {
2963 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2964
2965 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2966
2967 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2968 2048);
2969
2970 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2971 radv_cmd_buffer_clear_subpass(cmd_buffer);
2972 }
2973
2974 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2975 {
2976 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2977 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2978 if (!pipeline->shaders[stage])
2979 continue;
2980 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2981 if (loc->sgpr_idx == -1)
2982 continue;
2983 uint32_t base_reg = pipeline->user_data_0[stage];
2984 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2985
2986 }
2987 if (pipeline->gs_copy_shader) {
2988 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2989 if (loc->sgpr_idx != -1) {
2990 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2991 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2992 }
2993 }
2994 }
2995
2996 static void
2997 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2998 uint32_t vertex_count)
2999 {
3000 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3001 radeon_emit(cmd_buffer->cs, vertex_count);
3002 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3003 S_0287F0_USE_OPAQUE(0));
3004 }
3005
3006 static void
3007 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3008 uint64_t index_va,
3009 uint32_t index_count)
3010 {
3011 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3012 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3013 radeon_emit(cmd_buffer->cs, index_va);
3014 radeon_emit(cmd_buffer->cs, index_va >> 32);
3015 radeon_emit(cmd_buffer->cs, index_count);
3016 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3017 }
3018
3019 static void
3020 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3021 bool indexed,
3022 uint32_t draw_count,
3023 uint64_t count_va,
3024 uint32_t stride)
3025 {
3026 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3027 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3028 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3029 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3030 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3031 assert(base_reg);
3032
3033 if (draw_count == 1 && !count_va && !draw_id_enable) {
3034 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3035 PKT3_DRAW_INDIRECT, 3, false));
3036 radeon_emit(cs, 0);
3037 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3038 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3039 radeon_emit(cs, di_src_sel);
3040 } else {
3041 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3042 PKT3_DRAW_INDIRECT_MULTI,
3043 8, false));
3044 radeon_emit(cs, 0);
3045 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3046 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3047 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3048 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3049 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3050 radeon_emit(cs, draw_count); /* count */
3051 radeon_emit(cs, count_va); /* count_addr */
3052 radeon_emit(cs, count_va >> 32);
3053 radeon_emit(cs, stride); /* stride */
3054 radeon_emit(cs, di_src_sel);
3055 }
3056 }
3057
3058 struct radv_draw_info {
3059 /**
3060 * Number of vertices.
3061 */
3062 uint32_t count;
3063
3064 /**
3065 * Index of the first vertex.
3066 */
3067 int32_t vertex_offset;
3068
3069 /**
3070 * First instance id.
3071 */
3072 uint32_t first_instance;
3073
3074 /**
3075 * Number of instances.
3076 */
3077 uint32_t instance_count;
3078
3079 /**
3080 * First index (indexed draws only).
3081 */
3082 uint32_t first_index;
3083
3084 /**
3085 * Whether it's an indexed draw.
3086 */
3087 bool indexed;
3088
3089 /**
3090 * Indirect draw parameters resource.
3091 */
3092 struct radv_buffer *indirect;
3093 uint64_t indirect_offset;
3094 uint32_t stride;
3095
3096 /**
3097 * Draw count parameters resource.
3098 */
3099 struct radv_buffer *count_buffer;
3100 uint64_t count_buffer_offset;
3101 };
3102
3103 static void
3104 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3105 const struct radv_draw_info *info)
3106 {
3107 struct radv_cmd_state *state = &cmd_buffer->state;
3108 struct radeon_winsys *ws = cmd_buffer->device->ws;
3109 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3110
3111 if (info->indirect) {
3112 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3113 uint64_t count_va = 0;
3114
3115 va += info->indirect->offset + info->indirect_offset;
3116
3117 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3118
3119 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3120 radeon_emit(cs, 1);
3121 radeon_emit(cs, va);
3122 radeon_emit(cs, va >> 32);
3123
3124 if (info->count_buffer) {
3125 count_va = radv_buffer_get_va(info->count_buffer->bo);
3126 count_va += info->count_buffer->offset +
3127 info->count_buffer_offset;
3128
3129 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3130 }
3131
3132 if (!state->subpass->view_mask) {
3133 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3134 info->indexed,
3135 info->count,
3136 count_va,
3137 info->stride);
3138 } else {
3139 unsigned i;
3140 for_each_bit(i, state->subpass->view_mask) {
3141 radv_emit_view_index(cmd_buffer, i);
3142
3143 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3144 info->indexed,
3145 info->count,
3146 count_va,
3147 info->stride);
3148 }
3149 }
3150 } else {
3151 assert(state->pipeline->graphics.vtx_base_sgpr);
3152 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3153 state->pipeline->graphics.vtx_emit_num);
3154 radeon_emit(cs, info->vertex_offset);
3155 radeon_emit(cs, info->first_instance);
3156 if (state->pipeline->graphics.vtx_emit_num == 3)
3157 radeon_emit(cs, 0);
3158
3159 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3160 radeon_emit(cs, info->instance_count);
3161
3162 if (info->indexed) {
3163 int index_size = state->index_type ? 4 : 2;
3164 uint64_t index_va;
3165
3166 index_va = state->index_va;
3167 index_va += info->first_index * index_size;
3168
3169 if (!state->subpass->view_mask) {
3170 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3171 index_va,
3172 info->count);
3173 } else {
3174 unsigned i;
3175 for_each_bit(i, state->subpass->view_mask) {
3176 radv_emit_view_index(cmd_buffer, i);
3177
3178 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3179 index_va,
3180 info->count);
3181 }
3182 }
3183 } else {
3184 if (!state->subpass->view_mask) {
3185 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3186 } else {
3187 unsigned i;
3188 for_each_bit(i, state->subpass->view_mask) {
3189 radv_emit_view_index(cmd_buffer, i);
3190
3191 radv_cs_emit_draw_packet(cmd_buffer,
3192 info->count);
3193 }
3194 }
3195 }
3196 }
3197 }
3198
3199 static void
3200 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3201 const struct radv_draw_info *info)
3202 {
3203 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3204 radv_emit_graphics_pipeline(cmd_buffer);
3205
3206 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3207 radv_emit_framebuffer_state(cmd_buffer);
3208
3209 if (info->indexed) {
3210 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3211 radv_emit_index_buffer(cmd_buffer);
3212 } else {
3213 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3214 * so the state must be re-emitted before the next indexed
3215 * draw.
3216 */
3217 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3218 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3219 }
3220
3221 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3222
3223 radv_emit_draw_registers(cmd_buffer, info->indexed,
3224 info->instance_count > 1, info->indirect,
3225 info->indirect ? 0 : info->count);
3226 }
3227
3228 static void
3229 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3230 const struct radv_draw_info *info)
3231 {
3232 bool pipeline_is_dirty =
3233 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3234 cmd_buffer->state.pipeline &&
3235 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3236
3237 MAYBE_UNUSED unsigned cdw_max =
3238 radeon_check_space(cmd_buffer->device->ws,
3239 cmd_buffer->cs, 4096);
3240
3241 /* Use optimal packet order based on whether we need to sync the
3242 * pipeline.
3243 */
3244 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3245 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3246 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3247 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3248 /* If we have to wait for idle, set all states first, so that
3249 * all SET packets are processed in parallel with previous draw
3250 * calls. Then upload descriptors, set shader pointers, and
3251 * draw, and prefetch at the end. This ensures that the time
3252 * the CUs are idle is very short. (there are only SET_SH
3253 * packets between the wait and the draw)
3254 */
3255 radv_emit_all_graphics_states(cmd_buffer, info);
3256 si_emit_cache_flush(cmd_buffer);
3257 /* <-- CUs are idle here --> */
3258
3259 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3260 return;
3261
3262 radv_emit_draw_packets(cmd_buffer, info);
3263 /* <-- CUs are busy here --> */
3264
3265 /* Start prefetches after the draw has been started. Both will
3266 * run in parallel, but starting the draw first is more
3267 * important.
3268 */
3269 if (pipeline_is_dirty) {
3270 radv_emit_prefetch(cmd_buffer,
3271 cmd_buffer->state.pipeline);
3272 }
3273 } else {
3274 /* If we don't wait for idle, start prefetches first, then set
3275 * states, and draw at the end.
3276 */
3277 si_emit_cache_flush(cmd_buffer);
3278
3279 if (pipeline_is_dirty) {
3280 radv_emit_prefetch(cmd_buffer,
3281 cmd_buffer->state.pipeline);
3282 }
3283
3284 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3285 return;
3286
3287 radv_emit_all_graphics_states(cmd_buffer, info);
3288 radv_emit_draw_packets(cmd_buffer, info);
3289 }
3290
3291 assert(cmd_buffer->cs->cdw <= cdw_max);
3292 radv_cmd_buffer_after_draw(cmd_buffer);
3293 }
3294
3295 void radv_CmdDraw(
3296 VkCommandBuffer commandBuffer,
3297 uint32_t vertexCount,
3298 uint32_t instanceCount,
3299 uint32_t firstVertex,
3300 uint32_t firstInstance)
3301 {
3302 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3303 struct radv_draw_info info = {};
3304
3305 info.count = vertexCount;
3306 info.instance_count = instanceCount;
3307 info.first_instance = firstInstance;
3308 info.vertex_offset = firstVertex;
3309
3310 radv_draw(cmd_buffer, &info);
3311 }
3312
3313 void radv_CmdDrawIndexed(
3314 VkCommandBuffer commandBuffer,
3315 uint32_t indexCount,
3316 uint32_t instanceCount,
3317 uint32_t firstIndex,
3318 int32_t vertexOffset,
3319 uint32_t firstInstance)
3320 {
3321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3322 struct radv_draw_info info = {};
3323
3324 info.indexed = true;
3325 info.count = indexCount;
3326 info.instance_count = instanceCount;
3327 info.first_index = firstIndex;
3328 info.vertex_offset = vertexOffset;
3329 info.first_instance = firstInstance;
3330
3331 radv_draw(cmd_buffer, &info);
3332 }
3333
3334 void radv_CmdDrawIndirect(
3335 VkCommandBuffer commandBuffer,
3336 VkBuffer _buffer,
3337 VkDeviceSize offset,
3338 uint32_t drawCount,
3339 uint32_t stride)
3340 {
3341 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3342 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3343 struct radv_draw_info info = {};
3344
3345 info.count = drawCount;
3346 info.indirect = buffer;
3347 info.indirect_offset = offset;
3348 info.stride = stride;
3349
3350 radv_draw(cmd_buffer, &info);
3351 }
3352
3353 void radv_CmdDrawIndexedIndirect(
3354 VkCommandBuffer commandBuffer,
3355 VkBuffer _buffer,
3356 VkDeviceSize offset,
3357 uint32_t drawCount,
3358 uint32_t stride)
3359 {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3361 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3362 struct radv_draw_info info = {};
3363
3364 info.indexed = true;
3365 info.count = drawCount;
3366 info.indirect = buffer;
3367 info.indirect_offset = offset;
3368 info.stride = stride;
3369
3370 radv_draw(cmd_buffer, &info);
3371 }
3372
3373 void radv_CmdDrawIndirectCountAMD(
3374 VkCommandBuffer commandBuffer,
3375 VkBuffer _buffer,
3376 VkDeviceSize offset,
3377 VkBuffer _countBuffer,
3378 VkDeviceSize countBufferOffset,
3379 uint32_t maxDrawCount,
3380 uint32_t stride)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3383 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3384 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3385 struct radv_draw_info info = {};
3386
3387 info.count = maxDrawCount;
3388 info.indirect = buffer;
3389 info.indirect_offset = offset;
3390 info.count_buffer = count_buffer;
3391 info.count_buffer_offset = countBufferOffset;
3392 info.stride = stride;
3393
3394 radv_draw(cmd_buffer, &info);
3395 }
3396
3397 void radv_CmdDrawIndexedIndirectCountAMD(
3398 VkCommandBuffer commandBuffer,
3399 VkBuffer _buffer,
3400 VkDeviceSize offset,
3401 VkBuffer _countBuffer,
3402 VkDeviceSize countBufferOffset,
3403 uint32_t maxDrawCount,
3404 uint32_t stride)
3405 {
3406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3407 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3408 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3409 struct radv_draw_info info = {};
3410
3411 info.indexed = true;
3412 info.count = maxDrawCount;
3413 info.indirect = buffer;
3414 info.indirect_offset = offset;
3415 info.count_buffer = count_buffer;
3416 info.count_buffer_offset = countBufferOffset;
3417 info.stride = stride;
3418
3419 radv_draw(cmd_buffer, &info);
3420 }
3421
3422 struct radv_dispatch_info {
3423 /**
3424 * Determine the layout of the grid (in block units) to be used.
3425 */
3426 uint32_t blocks[3];
3427
3428 /**
3429 * Whether it's an unaligned compute dispatch.
3430 */
3431 bool unaligned;
3432
3433 /**
3434 * Indirect compute parameters resource.
3435 */
3436 struct radv_buffer *indirect;
3437 uint64_t indirect_offset;
3438 };
3439
3440 static void
3441 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3442 const struct radv_dispatch_info *info)
3443 {
3444 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3445 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3446 struct radeon_winsys *ws = cmd_buffer->device->ws;
3447 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3448 struct ac_userdata_info *loc;
3449 unsigned dispatch_initiator;
3450 uint8_t grid_used;
3451
3452 grid_used = compute_shader->info.info.cs.grid_components_used;
3453
3454 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3455 AC_UD_CS_GRID_SIZE);
3456
3457 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3458
3459 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3460 S_00B800_FORCE_START_AT_000(1);
3461
3462 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3463 /* If the KMD allows it (there is a KMD hw register for it),
3464 * allow launching waves out-of-order.
3465 */
3466 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3467 }
3468
3469 if (info->indirect) {
3470 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3471
3472 va += info->indirect->offset + info->indirect_offset;
3473
3474 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3475
3476 if (loc->sgpr_idx != -1) {
3477 for (unsigned i = 0; i < grid_used; ++i) {
3478 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3479 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3480 COPY_DATA_DST_SEL(COPY_DATA_REG));
3481 radeon_emit(cs, (va + 4 * i));
3482 radeon_emit(cs, (va + 4 * i) >> 32);
3483 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3484 + loc->sgpr_idx * 4) >> 2) + i);
3485 radeon_emit(cs, 0);
3486 }
3487 }
3488
3489 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3490 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3491 PKT3_SHADER_TYPE_S(1));
3492 radeon_emit(cs, va);
3493 radeon_emit(cs, va >> 32);
3494 radeon_emit(cs, dispatch_initiator);
3495 } else {
3496 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3497 PKT3_SHADER_TYPE_S(1));
3498 radeon_emit(cs, 1);
3499 radeon_emit(cs, va);
3500 radeon_emit(cs, va >> 32);
3501
3502 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3503 PKT3_SHADER_TYPE_S(1));
3504 radeon_emit(cs, 0);
3505 radeon_emit(cs, dispatch_initiator);
3506 }
3507 } else {
3508 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3509
3510 if (info->unaligned) {
3511 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3512 unsigned remainder[3];
3513
3514 /* If aligned, these should be an entire block size,
3515 * not 0.
3516 */
3517 remainder[0] = blocks[0] + cs_block_size[0] -
3518 align_u32_npot(blocks[0], cs_block_size[0]);
3519 remainder[1] = blocks[1] + cs_block_size[1] -
3520 align_u32_npot(blocks[1], cs_block_size[1]);
3521 remainder[2] = blocks[2] + cs_block_size[2] -
3522 align_u32_npot(blocks[2], cs_block_size[2]);
3523
3524 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3525 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3526 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3527
3528 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3529 radeon_emit(cs,
3530 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3531 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3532 radeon_emit(cs,
3533 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3534 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3535 radeon_emit(cs,
3536 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3537 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3538
3539 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3540 }
3541
3542 if (loc->sgpr_idx != -1) {
3543 assert(!loc->indirect);
3544 assert(loc->num_sgprs == grid_used);
3545
3546 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3547 loc->sgpr_idx * 4, grid_used);
3548 radeon_emit(cs, blocks[0]);
3549 if (grid_used > 1)
3550 radeon_emit(cs, blocks[1]);
3551 if (grid_used > 2)
3552 radeon_emit(cs, blocks[2]);
3553 }
3554
3555 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3556 PKT3_SHADER_TYPE_S(1));
3557 radeon_emit(cs, blocks[0]);
3558 radeon_emit(cs, blocks[1]);
3559 radeon_emit(cs, blocks[2]);
3560 radeon_emit(cs, dispatch_initiator);
3561 }
3562
3563 assert(cmd_buffer->cs->cdw <= cdw_max);
3564 }
3565
3566 static void
3567 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3568 {
3569 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3570 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3571 VK_SHADER_STAGE_COMPUTE_BIT);
3572 }
3573
3574 static void
3575 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3576 const struct radv_dispatch_info *info)
3577 {
3578 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3579 bool pipeline_is_dirty = pipeline &&
3580 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3581
3582 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3583 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3584 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3585 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3586 /* If we have to wait for idle, set all states first, so that
3587 * all SET packets are processed in parallel with previous draw
3588 * calls. Then upload descriptors, set shader pointers, and
3589 * dispatch, and prefetch at the end. This ensures that the
3590 * time the CUs are idle is very short. (there are only SET_SH
3591 * packets between the wait and the draw)
3592 */
3593 radv_emit_compute_pipeline(cmd_buffer);
3594 si_emit_cache_flush(cmd_buffer);
3595 /* <-- CUs are idle here --> */
3596
3597 radv_upload_compute_shader_descriptors(cmd_buffer);
3598
3599 radv_emit_dispatch_packets(cmd_buffer, info);
3600 /* <-- CUs are busy here --> */
3601
3602 /* Start prefetches after the dispatch has been started. Both
3603 * will run in parallel, but starting the dispatch first is
3604 * more important.
3605 */
3606 if (pipeline_is_dirty) {
3607 radv_emit_shader_prefetch(cmd_buffer,
3608 pipeline->shaders[MESA_SHADER_COMPUTE]);
3609 }
3610 } else {
3611 /* If we don't wait for idle, start prefetches first, then set
3612 * states, and dispatch at the end.
3613 */
3614 si_emit_cache_flush(cmd_buffer);
3615
3616 if (pipeline_is_dirty) {
3617 radv_emit_shader_prefetch(cmd_buffer,
3618 pipeline->shaders[MESA_SHADER_COMPUTE]);
3619 }
3620
3621 radv_upload_compute_shader_descriptors(cmd_buffer);
3622
3623 radv_emit_compute_pipeline(cmd_buffer);
3624 radv_emit_dispatch_packets(cmd_buffer, info);
3625 }
3626
3627 radv_cmd_buffer_after_draw(cmd_buffer);
3628 }
3629
3630 void radv_CmdDispatch(
3631 VkCommandBuffer commandBuffer,
3632 uint32_t x,
3633 uint32_t y,
3634 uint32_t z)
3635 {
3636 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3637 struct radv_dispatch_info info = {};
3638
3639 info.blocks[0] = x;
3640 info.blocks[1] = y;
3641 info.blocks[2] = z;
3642
3643 radv_dispatch(cmd_buffer, &info);
3644 }
3645
3646 void radv_CmdDispatchIndirect(
3647 VkCommandBuffer commandBuffer,
3648 VkBuffer _buffer,
3649 VkDeviceSize offset)
3650 {
3651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3652 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3653 struct radv_dispatch_info info = {};
3654
3655 info.indirect = buffer;
3656 info.indirect_offset = offset;
3657
3658 radv_dispatch(cmd_buffer, &info);
3659 }
3660
3661 void radv_unaligned_dispatch(
3662 struct radv_cmd_buffer *cmd_buffer,
3663 uint32_t x,
3664 uint32_t y,
3665 uint32_t z)
3666 {
3667 struct radv_dispatch_info info = {};
3668
3669 info.blocks[0] = x;
3670 info.blocks[1] = y;
3671 info.blocks[2] = z;
3672 info.unaligned = 1;
3673
3674 radv_dispatch(cmd_buffer, &info);
3675 }
3676
3677 void radv_CmdEndRenderPass(
3678 VkCommandBuffer commandBuffer)
3679 {
3680 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3681
3682 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3683
3684 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3685
3686 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3687 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3688 radv_handle_subpass_image_transition(cmd_buffer,
3689 (VkAttachmentReference){i, layout});
3690 }
3691
3692 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3693
3694 cmd_buffer->state.pass = NULL;
3695 cmd_buffer->state.subpass = NULL;
3696 cmd_buffer->state.attachments = NULL;
3697 cmd_buffer->state.framebuffer = NULL;
3698 }
3699
3700 /*
3701 * For HTILE we have the following interesting clear words:
3702 * 0x0000030f: Uncompressed.
3703 * 0xfffffff0: Clear depth to 1.0
3704 * 0x00000000: Clear depth to 0.0
3705 */
3706 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3707 struct radv_image *image,
3708 const VkImageSubresourceRange *range,
3709 uint32_t clear_word)
3710 {
3711 assert(range->baseMipLevel == 0);
3712 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3713 unsigned layer_count = radv_get_layerCount(image, range);
3714 uint64_t size = image->surface.htile_slice_size * layer_count;
3715 uint64_t offset = image->offset + image->htile_offset +
3716 image->surface.htile_slice_size * range->baseArrayLayer;
3717 struct radv_cmd_state *state = &cmd_buffer->state;
3718
3719 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3720 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3721
3722 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3723 size, clear_word);
3724
3725 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3726 }
3727
3728 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3729 struct radv_image *image,
3730 VkImageLayout src_layout,
3731 VkImageLayout dst_layout,
3732 unsigned src_queue_mask,
3733 unsigned dst_queue_mask,
3734 const VkImageSubresourceRange *range,
3735 VkImageAspectFlags pending_clears)
3736 {
3737 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3738 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3739 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3740 cmd_buffer->state.render_area.extent.width == image->info.width &&
3741 cmd_buffer->state.render_area.extent.height == image->info.height) {
3742 /* The clear will initialize htile. */
3743 return;
3744 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3745 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3746 /* TODO: merge with the clear if applicable */
3747 radv_initialize_htile(cmd_buffer, image, range, 0);
3748 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3749 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3750 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3751 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3752 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3753 VkImageSubresourceRange local_range = *range;
3754 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3755 local_range.baseMipLevel = 0;
3756 local_range.levelCount = 1;
3757
3758 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3759 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3760
3761 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3762
3763 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3764 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3765 }
3766 }
3767
3768 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3769 struct radv_image *image, uint32_t value)
3770 {
3771 struct radv_cmd_state *state = &cmd_buffer->state;
3772
3773 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3774 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3775
3776 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3777 image->offset + image->cmask.offset,
3778 image->cmask.size, value);
3779
3780 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3781 }
3782
3783 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3784 struct radv_image *image,
3785 VkImageLayout src_layout,
3786 VkImageLayout dst_layout,
3787 unsigned src_queue_mask,
3788 unsigned dst_queue_mask,
3789 const VkImageSubresourceRange *range)
3790 {
3791 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3792 if (image->fmask.size)
3793 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3794 else
3795 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3796 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3797 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3798 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3799 }
3800 }
3801
3802 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3803 struct radv_image *image, uint32_t value)
3804 {
3805 struct radv_cmd_state *state = &cmd_buffer->state;
3806
3807 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3808 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3809
3810 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3811 image->offset + image->dcc_offset,
3812 image->surface.dcc_size, value);
3813
3814 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3815 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3816 }
3817
3818 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3819 struct radv_image *image,
3820 VkImageLayout src_layout,
3821 VkImageLayout dst_layout,
3822 unsigned src_queue_mask,
3823 unsigned dst_queue_mask,
3824 const VkImageSubresourceRange *range)
3825 {
3826 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3827 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3828 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3829 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3830 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3831 }
3832 }
3833
3834 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3835 struct radv_image *image,
3836 VkImageLayout src_layout,
3837 VkImageLayout dst_layout,
3838 uint32_t src_family,
3839 uint32_t dst_family,
3840 const VkImageSubresourceRange *range,
3841 VkImageAspectFlags pending_clears)
3842 {
3843 if (image->exclusive && src_family != dst_family) {
3844 /* This is an acquire or a release operation and there will be
3845 * a corresponding release/acquire. Do the transition in the
3846 * most flexible queue. */
3847
3848 assert(src_family == cmd_buffer->queue_family_index ||
3849 dst_family == cmd_buffer->queue_family_index);
3850
3851 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3852 return;
3853
3854 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3855 (src_family == RADV_QUEUE_GENERAL ||
3856 dst_family == RADV_QUEUE_GENERAL))
3857 return;
3858 }
3859
3860 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3861 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3862
3863 if (image->surface.htile_size)
3864 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3865 dst_layout, src_queue_mask,
3866 dst_queue_mask, range,
3867 pending_clears);
3868
3869 if (image->cmask.size || image->fmask.size)
3870 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3871 dst_layout, src_queue_mask,
3872 dst_queue_mask, range);
3873
3874 if (image->surface.dcc_size)
3875 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3876 dst_layout, src_queue_mask,
3877 dst_queue_mask, range);
3878 }
3879
3880 void radv_CmdPipelineBarrier(
3881 VkCommandBuffer commandBuffer,
3882 VkPipelineStageFlags srcStageMask,
3883 VkPipelineStageFlags destStageMask,
3884 VkBool32 byRegion,
3885 uint32_t memoryBarrierCount,
3886 const VkMemoryBarrier* pMemoryBarriers,
3887 uint32_t bufferMemoryBarrierCount,
3888 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3889 uint32_t imageMemoryBarrierCount,
3890 const VkImageMemoryBarrier* pImageMemoryBarriers)
3891 {
3892 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3893 enum radv_cmd_flush_bits src_flush_bits = 0;
3894 enum radv_cmd_flush_bits dst_flush_bits = 0;
3895
3896 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3897 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3898 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3899 NULL);
3900 }
3901
3902 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3903 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3904 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3905 NULL);
3906 }
3907
3908 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3909 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3910 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3911 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3912 image);
3913 }
3914
3915 radv_stage_flush(cmd_buffer, srcStageMask);
3916 cmd_buffer->state.flush_bits |= src_flush_bits;
3917
3918 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3919 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3920 radv_handle_image_transition(cmd_buffer, image,
3921 pImageMemoryBarriers[i].oldLayout,
3922 pImageMemoryBarriers[i].newLayout,
3923 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3924 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3925 &pImageMemoryBarriers[i].subresourceRange,
3926 0);
3927 }
3928
3929 cmd_buffer->state.flush_bits |= dst_flush_bits;
3930 }
3931
3932
3933 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3934 struct radv_event *event,
3935 VkPipelineStageFlags stageMask,
3936 unsigned value)
3937 {
3938 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3939 uint64_t va = radv_buffer_get_va(event->bo);
3940
3941 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3942
3943 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3944
3945 /* TODO: this is overkill. Probably should figure something out from
3946 * the stage mask. */
3947
3948 si_cs_emit_write_event_eop(cs,
3949 cmd_buffer->state.predicating,
3950 cmd_buffer->device->physical_device->rad_info.chip_class,
3951 false,
3952 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3953 1, va, 2, value);
3954
3955 assert(cmd_buffer->cs->cdw <= cdw_max);
3956 }
3957
3958 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3959 VkEvent _event,
3960 VkPipelineStageFlags stageMask)
3961 {
3962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3963 RADV_FROM_HANDLE(radv_event, event, _event);
3964
3965 write_event(cmd_buffer, event, stageMask, 1);
3966 }
3967
3968 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3969 VkEvent _event,
3970 VkPipelineStageFlags stageMask)
3971 {
3972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3973 RADV_FROM_HANDLE(radv_event, event, _event);
3974
3975 write_event(cmd_buffer, event, stageMask, 0);
3976 }
3977
3978 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3979 uint32_t eventCount,
3980 const VkEvent* pEvents,
3981 VkPipelineStageFlags srcStageMask,
3982 VkPipelineStageFlags dstStageMask,
3983 uint32_t memoryBarrierCount,
3984 const VkMemoryBarrier* pMemoryBarriers,
3985 uint32_t bufferMemoryBarrierCount,
3986 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3987 uint32_t imageMemoryBarrierCount,
3988 const VkImageMemoryBarrier* pImageMemoryBarriers)
3989 {
3990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3991 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3992
3993 for (unsigned i = 0; i < eventCount; ++i) {
3994 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3995 uint64_t va = radv_buffer_get_va(event->bo);
3996
3997 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3998
3999 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4000
4001 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4002 assert(cmd_buffer->cs->cdw <= cdw_max);
4003 }
4004
4005
4006 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4007 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4008
4009 radv_handle_image_transition(cmd_buffer, image,
4010 pImageMemoryBarriers[i].oldLayout,
4011 pImageMemoryBarriers[i].newLayout,
4012 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4013 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4014 &pImageMemoryBarriers[i].subresourceRange,
4015 0);
4016 }
4017
4018 /* TODO: figure out how to do memory barriers without waiting */
4019 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4020 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4021 RADV_CMD_FLAG_INV_VMEM_L1 |
4022 RADV_CMD_FLAG_INV_SMEM_L1;
4023 }