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radv: rework the TC-compat HTILE hardware bug with COND_EXEC
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count,
628 HAVE_32BIT_POINTERS);
629 for (int i = 0; i < count; i++) {
630 struct radv_descriptor_set *set =
631 descriptors_state->sets[start + i];
632
633 radv_emit_shader_pointer_body(device, cs, set->va,
634 HAVE_32BIT_POINTERS);
635 }
636 }
637 }
638
639 static void
640 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
641 struct radv_pipeline *pipeline)
642 {
643 int num_samples = pipeline->graphics.ms.num_samples;
644 struct radv_multisample_state *ms = &pipeline->graphics.ms;
645 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
646
647 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
648 cmd_buffer->sample_positions_needed = true;
649
650 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
651 return;
652
653 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
654 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
655 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
656
657 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
658
659 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
660
661 /* GFX9: Flush DFSM when the AA mode changes. */
662 if (cmd_buffer->device->dfsm_allowed) {
663 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
664 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
665 }
666 }
667
668 static void
669 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_shader_variant *shader)
671 {
672 uint64_t va;
673
674 if (!shader)
675 return;
676
677 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
678
679 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
680 }
681
682 static void
683 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_pipeline *pipeline,
685 bool vertex_stage_only)
686 {
687 struct radv_cmd_state *state = &cmd_buffer->state;
688 uint32_t mask = state->prefetch_L2_mask;
689
690 if (vertex_stage_only) {
691 /* Fast prefetch path for starting draws as soon as possible.
692 */
693 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
694 RADV_PREFETCH_VBO_DESCRIPTORS);
695 }
696
697 if (mask & RADV_PREFETCH_VS)
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700
701 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
702 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
703
704 if (mask & RADV_PREFETCH_TCS)
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
707
708 if (mask & RADV_PREFETCH_TES)
709 radv_emit_shader_prefetch(cmd_buffer,
710 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
711
712 if (mask & RADV_PREFETCH_GS) {
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_GEOMETRY]);
715 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
716 }
717
718 if (mask & RADV_PREFETCH_PS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_FRAGMENT]);
721
722 state->prefetch_L2_mask &= ~mask;
723 }
724
725 static void
726 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
727 {
728 if (!cmd_buffer->device->physical_device->rbplus_allowed)
729 return;
730
731 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
732 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
733 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
734
735 unsigned sx_ps_downconvert = 0;
736 unsigned sx_blend_opt_epsilon = 0;
737 unsigned sx_blend_opt_control = 0;
738
739 for (unsigned i = 0; i < subpass->color_count; ++i) {
740 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
741 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
742 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
743 continue;
744 }
745
746 int idx = subpass->color_attachments[i].attachment;
747 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
748
749 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
750 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
751 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
752 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
753
754 bool has_alpha, has_rgb;
755
756 /* Set if RGB and A are present. */
757 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
758
759 if (format == V_028C70_COLOR_8 ||
760 format == V_028C70_COLOR_16 ||
761 format == V_028C70_COLOR_32)
762 has_rgb = !has_alpha;
763 else
764 has_rgb = true;
765
766 /* Check the colormask and export format. */
767 if (!(colormask & 0x7))
768 has_rgb = false;
769 if (!(colormask & 0x8))
770 has_alpha = false;
771
772 if (spi_format == V_028714_SPI_SHADER_ZERO) {
773 has_rgb = false;
774 has_alpha = false;
775 }
776
777 /* Disable value checking for disabled channels. */
778 if (!has_rgb)
779 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
780 if (!has_alpha)
781 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
782
783 /* Enable down-conversion for 32bpp and smaller formats. */
784 switch (format) {
785 case V_028C70_COLOR_8:
786 case V_028C70_COLOR_8_8:
787 case V_028C70_COLOR_8_8_8_8:
788 /* For 1 and 2-channel formats, use the superset thereof. */
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
790 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
791 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
792 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
793 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
794 }
795 break;
796
797 case V_028C70_COLOR_5_6_5:
798 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
799 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
800 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
801 }
802 break;
803
804 case V_028C70_COLOR_1_5_5_5:
805 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_4_4_4_4:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_32:
819 if (swap == V_028C70_SWAP_STD &&
820 spi_format == V_028714_SPI_SHADER_32_R)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
822 else if (swap == V_028C70_SWAP_ALT_REV &&
823 spi_format == V_028714_SPI_SHADER_32_AR)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
825 break;
826
827 case V_028C70_COLOR_16:
828 case V_028C70_COLOR_16_16:
829 /* For 1-channel formats, use the superset thereof. */
830 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
832 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
833 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
834 if (swap == V_028C70_SWAP_STD ||
835 swap == V_028C70_SWAP_STD_REV)
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
837 else
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
839 }
840 break;
841
842 case V_028C70_COLOR_10_11_11:
843 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
844 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
845 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
846 }
847 break;
848
849 case V_028C70_COLOR_2_10_10_10:
850 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
851 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
852 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
853 }
854 break;
855 }
856 }
857
858 for (unsigned i = subpass->color_count; i < 8; ++i) {
859 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
860 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
861 }
862 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
863 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
864 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
865 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
866 }
867
868 static void
869 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
870 {
871 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
872
873 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
874 return;
875
876 radv_update_multisample_state(cmd_buffer, pipeline);
877
878 cmd_buffer->scratch_size_needed =
879 MAX2(cmd_buffer->scratch_size_needed,
880 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
881
882 if (!cmd_buffer->state.emitted_pipeline ||
883 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
884 pipeline->graphics.can_use_guardband)
885 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
886
887 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
888
889 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
890 if (!pipeline->shaders[i])
891 continue;
892
893 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
894 pipeline->shaders[i]->bo);
895 }
896
897 if (radv_pipeline_has_gs(pipeline))
898 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
899 pipeline->gs_copy_shader->bo);
900
901 if (unlikely(cmd_buffer->device->trace_bo))
902 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
903
904 cmd_buffer->state.emitted_pipeline = pipeline;
905
906 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
907 }
908
909 static void
910 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
911 {
912 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
913 cmd_buffer->state.dynamic.viewport.viewports);
914 }
915
916 static void
917 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
918 {
919 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
920
921 si_write_scissors(cmd_buffer->cs, 0, count,
922 cmd_buffer->state.dynamic.scissor.scissors,
923 cmd_buffer->state.dynamic.viewport.viewports,
924 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
925 }
926
927 static void
928 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
929 {
930 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
931 return;
932
933 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
934 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
935 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
936 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
937 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
938 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
939 S_028214_BR_Y(rect.offset.y + rect.extent.height));
940 }
941 }
942
943 static void
944 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
945 {
946 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
947
948 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
949 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
950 }
951
952 static void
953 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
954 {
955 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
956
957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
958 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
959 }
960
961 static void
962 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg_seq(cmd_buffer->cs,
967 R_028430_DB_STENCILREFMASK, 2);
968 radeon_emit(cmd_buffer->cs,
969 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
970 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
971 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
972 S_028430_STENCILOPVAL(1));
973 radeon_emit(cmd_buffer->cs,
974 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
975 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
976 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
977 S_028434_STENCILOPVAL_BF(1));
978 }
979
980 static void
981 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
986 fui(d->depth_bounds.min));
987 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
988 fui(d->depth_bounds.max));
989 }
990
991 static void
992 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
993 {
994 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
995 unsigned slope = fui(d->depth_bias.slope * 16.0f);
996 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
997
998
999 radeon_set_context_reg_seq(cmd_buffer->cs,
1000 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1001 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1002 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1003 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1004 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1005 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1006 }
1007
1008 static void
1009 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1010 int index,
1011 struct radv_attachment_info *att,
1012 struct radv_image *image,
1013 VkImageLayout layout)
1014 {
1015 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1016 struct radv_color_buffer_info *cb = &att->cb;
1017 uint32_t cb_color_info = cb->cb_color_info;
1018
1019 if (!radv_layout_dcc_compressed(image, layout,
1020 radv_image_queue_family_mask(image,
1021 cmd_buffer->queue_family_index,
1022 cmd_buffer->queue_family_index))) {
1023 cb_color_info &= C_028C70_DCC_ENABLE;
1024 }
1025
1026 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1027 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1029 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1032 radeon_emit(cmd_buffer->cs, cb_color_info);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1034 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1036 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1038 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1041 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1042 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1043
1044 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1045 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1046 } else {
1047 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1050 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1052 radeon_emit(cmd_buffer->cs, cb_color_info);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1054 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1059
1060 if (is_vi) { /* DCC BASE */
1061 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1062 }
1063 }
1064 }
1065
1066 static void
1067 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1068 struct radv_ds_buffer_info *ds,
1069 struct radv_image *image, VkImageLayout layout,
1070 bool requires_cond_exec)
1071 {
1072 uint32_t db_z_info = ds->db_z_info;
1073 uint32_t db_z_info_reg;
1074
1075 if (!radv_image_is_tc_compat_htile(image))
1076 return;
1077
1078 if (!radv_layout_has_htile(image, layout,
1079 radv_image_queue_family_mask(image,
1080 cmd_buffer->queue_family_index,
1081 cmd_buffer->queue_family_index))) {
1082 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1083 }
1084
1085 db_z_info &= C_028040_ZRANGE_PRECISION;
1086
1087 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1088 db_z_info_reg = R_028038_DB_Z_INFO;
1089 } else {
1090 db_z_info_reg = R_028040_DB_Z_INFO;
1091 }
1092
1093 /* When we don't know the last fast clear value we need to emit a
1094 * conditional packet that will eventually skip the following
1095 * SET_CONTEXT_REG packet.
1096 */
1097 if (requires_cond_exec) {
1098 uint64_t va = radv_buffer_get_va(image->bo);
1099 va += image->offset + image->tc_compat_zrange_offset;
1100
1101 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1102 radeon_emit(cmd_buffer->cs, va);
1103 radeon_emit(cmd_buffer->cs, va >> 32);
1104 radeon_emit(cmd_buffer->cs, 0);
1105 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1106 }
1107
1108 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1109 }
1110
1111 static void
1112 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1113 struct radv_ds_buffer_info *ds,
1114 struct radv_image *image,
1115 VkImageLayout layout)
1116 {
1117 uint32_t db_z_info = ds->db_z_info;
1118 uint32_t db_stencil_info = ds->db_stencil_info;
1119
1120 if (!radv_layout_has_htile(image, layout,
1121 radv_image_queue_family_mask(image,
1122 cmd_buffer->queue_family_index,
1123 cmd_buffer->queue_family_index))) {
1124 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1125 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1126 }
1127
1128 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1129 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1130
1131
1132 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1133 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1134 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1135 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1136 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1137
1138 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1139 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1140 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1141 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1144 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1147 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1148 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1149
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1151 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1152 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1153 } else {
1154 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1155
1156 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1157 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1158 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1159 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1166
1167 }
1168
1169 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1170 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1171
1172 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1173 ds->pa_su_poly_offset_db_fmt_cntl);
1174 }
1175
1176 /**
1177 * Update the fast clear depth/stencil values if the image is bound as a
1178 * depth/stencil buffer.
1179 */
1180 static void
1181 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1182 struct radv_image *image,
1183 VkClearDepthStencilValue ds_clear_value,
1184 VkImageAspectFlags aspects)
1185 {
1186 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1187 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1188 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1189 struct radv_attachment_info *att;
1190 uint32_t att_idx;
1191
1192 if (!framebuffer || !subpass)
1193 return;
1194
1195 att_idx = subpass->depth_stencil_attachment.attachment;
1196 if (att_idx == VK_ATTACHMENT_UNUSED)
1197 return;
1198
1199 att = &framebuffer->attachments[att_idx];
1200 if (att->attachment->image != image)
1201 return;
1202
1203 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1204 radeon_emit(cs, ds_clear_value.stencil);
1205 radeon_emit(cs, fui(ds_clear_value.depth));
1206
1207 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1208 * only needed when clearing Z to 0.0.
1209 */
1210 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1211 ds_clear_value.depth == 0.0) {
1212 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1213
1214 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1215 layout, false);
1216 }
1217 }
1218
1219 /**
1220 * Set the clear depth/stencil values to the image's metadata.
1221 */
1222 static void
1223 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1224 struct radv_image *image,
1225 VkClearDepthStencilValue ds_clear_value,
1226 VkImageAspectFlags aspects)
1227 {
1228 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1229 uint64_t va = radv_buffer_get_va(image->bo);
1230 unsigned reg_offset = 0, reg_count = 0;
1231
1232 va += image->offset + image->clear_value_offset;
1233
1234 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1235 ++reg_count;
1236 } else {
1237 ++reg_offset;
1238 va += 4;
1239 }
1240 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1241 ++reg_count;
1242
1243 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1244 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1245 S_370_WR_CONFIRM(1) |
1246 S_370_ENGINE_SEL(V_370_PFP));
1247 radeon_emit(cs, va);
1248 radeon_emit(cs, va >> 32);
1249 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1250 radeon_emit(cs, ds_clear_value.stencil);
1251 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1252 radeon_emit(cs, fui(ds_clear_value.depth));
1253 }
1254
1255 /**
1256 * Update the TC-compat metadata value for this image.
1257 */
1258 static void
1259 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1260 struct radv_image *image,
1261 uint32_t value)
1262 {
1263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 va += image->offset + image->tc_compat_zrange_offset;
1266
1267 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1268 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1269 S_370_WR_CONFIRM(1) |
1270 S_370_ENGINE_SEL(V_370_PFP));
1271 radeon_emit(cs, va);
1272 radeon_emit(cs, va >> 32);
1273 radeon_emit(cs, value);
1274 }
1275
1276 static void
1277 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image,
1279 VkClearDepthStencilValue ds_clear_value)
1280 {
1281 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 va += image->offset + image->tc_compat_zrange_offset;
1284 uint32_t cond_val;
1285
1286 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1287 * depth clear value is 0.0f.
1288 */
1289 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1290
1291 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1292 }
1293
1294 /**
1295 * Update the clear depth/stencil values for this image.
1296 */
1297 void
1298 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1299 struct radv_image *image,
1300 VkClearDepthStencilValue ds_clear_value,
1301 VkImageAspectFlags aspects)
1302 {
1303 assert(radv_image_has_htile(image));
1304
1305 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1306
1307 if (radv_image_is_tc_compat_htile(image) &&
1308 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1309 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1310 ds_clear_value);
1311 }
1312
1313 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1314 aspects);
1315 }
1316
1317 /**
1318 * Load the clear depth/stencil values from the image's metadata.
1319 */
1320 static void
1321 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1322 struct radv_image *image)
1323 {
1324 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1325 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1326 uint64_t va = radv_buffer_get_va(image->bo);
1327 unsigned reg_offset = 0, reg_count = 0;
1328
1329 va += image->offset + image->clear_value_offset;
1330
1331 if (!radv_image_has_htile(image))
1332 return;
1333
1334 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1335 ++reg_count;
1336 } else {
1337 ++reg_offset;
1338 va += 4;
1339 }
1340 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1341 ++reg_count;
1342
1343 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1344
1345 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1346 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1347 radeon_emit(cs, va);
1348 radeon_emit(cs, va >> 32);
1349 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1350 radeon_emit(cs, reg_count);
1351 } else {
1352 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1353 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1354 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1355 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1356 radeon_emit(cs, va);
1357 radeon_emit(cs, va >> 32);
1358 radeon_emit(cs, reg >> 2);
1359 radeon_emit(cs, 0);
1360
1361 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1362 radeon_emit(cs, 0);
1363 }
1364 }
1365
1366 /*
1367 * With DCC some colors don't require CMASK elimination before being
1368 * used as a texture. This sets a predicate value to determine if the
1369 * cmask eliminate is required.
1370 */
1371 void
1372 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1373 struct radv_image *image, bool value)
1374 {
1375 uint64_t pred_val = value;
1376 uint64_t va = radv_buffer_get_va(image->bo);
1377 va += image->offset + image->fce_pred_offset;
1378
1379 assert(radv_image_has_dcc(image));
1380
1381 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1382 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1383 S_370_WR_CONFIRM(1) |
1384 S_370_ENGINE_SEL(V_370_PFP));
1385 radeon_emit(cmd_buffer->cs, va);
1386 radeon_emit(cmd_buffer->cs, va >> 32);
1387 radeon_emit(cmd_buffer->cs, pred_val);
1388 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1389 }
1390
1391 /**
1392 * Update the fast clear color values if the image is bound as a color buffer.
1393 */
1394 static void
1395 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_image *image,
1397 int cb_idx,
1398 uint32_t color_values[2])
1399 {
1400 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1401 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1402 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1403 struct radv_attachment_info *att;
1404 uint32_t att_idx;
1405
1406 if (!framebuffer || !subpass)
1407 return;
1408
1409 att_idx = subpass->color_attachments[cb_idx].attachment;
1410 if (att_idx == VK_ATTACHMENT_UNUSED)
1411 return;
1412
1413 att = &framebuffer->attachments[att_idx];
1414 if (att->attachment->image != image)
1415 return;
1416
1417 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1418 radeon_emit(cs, color_values[0]);
1419 radeon_emit(cs, color_values[1]);
1420 }
1421
1422 /**
1423 * Set the clear color values to the image's metadata.
1424 */
1425 static void
1426 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_image *image,
1428 uint32_t color_values[2])
1429 {
1430 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1431 uint64_t va = radv_buffer_get_va(image->bo);
1432
1433 va += image->offset + image->clear_value_offset;
1434
1435 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1436
1437 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1438 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1439 S_370_WR_CONFIRM(1) |
1440 S_370_ENGINE_SEL(V_370_PFP));
1441 radeon_emit(cs, va);
1442 radeon_emit(cs, va >> 32);
1443 radeon_emit(cs, color_values[0]);
1444 radeon_emit(cs, color_values[1]);
1445 }
1446
1447 /**
1448 * Update the clear color values for this image.
1449 */
1450 void
1451 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1452 struct radv_image *image,
1453 int cb_idx,
1454 uint32_t color_values[2])
1455 {
1456 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1457
1458 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1459
1460 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1461 color_values);
1462 }
1463
1464 /**
1465 * Load the clear color values from the image's metadata.
1466 */
1467 static void
1468 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1469 struct radv_image *image,
1470 int cb_idx)
1471 {
1472 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1473 uint64_t va = radv_buffer_get_va(image->bo);
1474
1475 va += image->offset + image->clear_value_offset;
1476
1477 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1478 return;
1479
1480 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1481
1482 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1483 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1484 radeon_emit(cs, va);
1485 radeon_emit(cs, va >> 32);
1486 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1487 radeon_emit(cs, 2);
1488 } else {
1489 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1490 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1491 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1492 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1493 COPY_DATA_COUNT_SEL);
1494 radeon_emit(cs, va);
1495 radeon_emit(cs, va >> 32);
1496 radeon_emit(cs, reg >> 2);
1497 radeon_emit(cs, 0);
1498
1499 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1500 radeon_emit(cs, 0);
1501 }
1502 }
1503
1504 static void
1505 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1506 {
1507 int i;
1508 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1509 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1510 unsigned num_bpp64_colorbufs = 0;
1511
1512 /* this may happen for inherited secondary recording */
1513 if (!framebuffer)
1514 return;
1515
1516 for (i = 0; i < 8; ++i) {
1517 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1518 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1519 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1520 continue;
1521 }
1522
1523 int idx = subpass->color_attachments[i].attachment;
1524 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1525 struct radv_image *image = att->attachment->image;
1526 VkImageLayout layout = subpass->color_attachments[i].layout;
1527
1528 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1529
1530 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1531 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1532
1533 radv_load_color_clear_metadata(cmd_buffer, image, i);
1534
1535 if (image->surface.bpe >= 8)
1536 num_bpp64_colorbufs++;
1537 }
1538
1539 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1540 int idx = subpass->depth_stencil_attachment.attachment;
1541 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1542 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1543 struct radv_image *image = att->attachment->image;
1544 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1545 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1546 cmd_buffer->queue_family_index,
1547 cmd_buffer->queue_family_index);
1548 /* We currently don't support writing decompressed HTILE */
1549 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1550 radv_layout_is_htile_compressed(image, layout, queue_mask));
1551
1552 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1553
1554 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1555 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1556 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1557 }
1558 radv_load_ds_clear_metadata(cmd_buffer, image);
1559 } else {
1560 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1561 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1562 else
1563 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1564
1565 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1566 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1567 }
1568 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1569 S_028208_BR_X(framebuffer->width) |
1570 S_028208_BR_Y(framebuffer->height));
1571
1572 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1573 uint8_t watermark = 4; /* Default value for VI. */
1574
1575 /* For optimal DCC performance. */
1576 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1577 if (num_bpp64_colorbufs >= 5) {
1578 watermark = 8;
1579 } else {
1580 watermark = 6;
1581 }
1582 }
1583
1584 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1585 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1586 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1587 }
1588
1589 if (cmd_buffer->device->dfsm_allowed) {
1590 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1591 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1592 }
1593
1594 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1595 }
1596
1597 static void
1598 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1599 {
1600 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1601 struct radv_cmd_state *state = &cmd_buffer->state;
1602
1603 if (state->index_type != state->last_index_type) {
1604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1605 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1606 2, state->index_type);
1607 } else {
1608 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1609 radeon_emit(cs, state->index_type);
1610 }
1611
1612 state->last_index_type = state->index_type;
1613 }
1614
1615 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1616 radeon_emit(cs, state->index_va);
1617 radeon_emit(cs, state->index_va >> 32);
1618
1619 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1620 radeon_emit(cs, state->max_index_count);
1621
1622 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1623 }
1624
1625 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1626 {
1627 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1628 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1629 uint32_t pa_sc_mode_cntl_1 =
1630 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1631 uint32_t db_count_control;
1632
1633 if(!cmd_buffer->state.active_occlusion_queries) {
1634 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1635 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1636 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1637 has_perfect_queries) {
1638 /* Re-enable out-of-order rasterization if the
1639 * bound pipeline supports it and if it's has
1640 * been disabled before starting any perfect
1641 * occlusion queries.
1642 */
1643 radeon_set_context_reg(cmd_buffer->cs,
1644 R_028A4C_PA_SC_MODE_CNTL_1,
1645 pa_sc_mode_cntl_1);
1646 }
1647 }
1648 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1649 } else {
1650 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1651 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1652
1653 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1654 db_count_control =
1655 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1656 S_028004_SAMPLE_RATE(sample_rate) |
1657 S_028004_ZPASS_ENABLE(1) |
1658 S_028004_SLICE_EVEN_ENABLE(1) |
1659 S_028004_SLICE_ODD_ENABLE(1);
1660
1661 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1662 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1663 has_perfect_queries) {
1664 /* If the bound pipeline has enabled
1665 * out-of-order rasterization, we should
1666 * disable it before starting any perfect
1667 * occlusion queries.
1668 */
1669 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1670
1671 radeon_set_context_reg(cmd_buffer->cs,
1672 R_028A4C_PA_SC_MODE_CNTL_1,
1673 pa_sc_mode_cntl_1);
1674 }
1675 } else {
1676 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1677 S_028004_SAMPLE_RATE(sample_rate);
1678 }
1679 }
1680
1681 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1682 }
1683
1684 static void
1685 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1686 {
1687 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1688
1689 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1690 radv_emit_viewport(cmd_buffer);
1691
1692 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1693 !cmd_buffer->device->physical_device->has_scissor_bug)
1694 radv_emit_scissor(cmd_buffer);
1695
1696 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1697 radv_emit_line_width(cmd_buffer);
1698
1699 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1700 radv_emit_blend_constants(cmd_buffer);
1701
1702 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1703 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1704 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1705 radv_emit_stencil(cmd_buffer);
1706
1707 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1708 radv_emit_depth_bounds(cmd_buffer);
1709
1710 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1711 radv_emit_depth_bias(cmd_buffer);
1712
1713 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1714 radv_emit_discard_rectangle(cmd_buffer);
1715
1716 cmd_buffer->state.dirty &= ~states;
1717 }
1718
1719 static void
1720 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1721 VkPipelineBindPoint bind_point)
1722 {
1723 struct radv_descriptor_state *descriptors_state =
1724 radv_get_descriptors_state(cmd_buffer, bind_point);
1725 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1726 unsigned bo_offset;
1727
1728 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1729 set->mapped_ptr,
1730 &bo_offset))
1731 return;
1732
1733 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1734 set->va += bo_offset;
1735 }
1736
1737 static void
1738 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1739 VkPipelineBindPoint bind_point)
1740 {
1741 struct radv_descriptor_state *descriptors_state =
1742 radv_get_descriptors_state(cmd_buffer, bind_point);
1743 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1744 uint32_t size = MAX_SETS * 4 * ptr_size;
1745 uint32_t offset;
1746 void *ptr;
1747
1748 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1749 256, &offset, &ptr))
1750 return;
1751
1752 for (unsigned i = 0; i < MAX_SETS; i++) {
1753 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1754 uint64_t set_va = 0;
1755 struct radv_descriptor_set *set = descriptors_state->sets[i];
1756 if (descriptors_state->valid & (1u << i))
1757 set_va = set->va;
1758 uptr[0] = set_va & 0xffffffff;
1759 if (ptr_size == 2)
1760 uptr[1] = set_va >> 32;
1761 }
1762
1763 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1764 va += offset;
1765
1766 if (cmd_buffer->state.pipeline) {
1767 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1768 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1769 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1770
1771 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1772 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1773 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1774
1775 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1776 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1777 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1778
1779 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1780 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1781 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1782
1783 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1784 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1785 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1786 }
1787
1788 if (cmd_buffer->state.compute_pipeline)
1789 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1790 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1791 }
1792
1793 static void
1794 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1795 VkShaderStageFlags stages)
1796 {
1797 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1798 VK_PIPELINE_BIND_POINT_COMPUTE :
1799 VK_PIPELINE_BIND_POINT_GRAPHICS;
1800 struct radv_descriptor_state *descriptors_state =
1801 radv_get_descriptors_state(cmd_buffer, bind_point);
1802 struct radv_cmd_state *state = &cmd_buffer->state;
1803 bool flush_indirect_descriptors;
1804
1805 if (!descriptors_state->dirty)
1806 return;
1807
1808 if (descriptors_state->push_dirty)
1809 radv_flush_push_descriptors(cmd_buffer, bind_point);
1810
1811 flush_indirect_descriptors =
1812 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1813 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1814 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1815 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1816
1817 if (flush_indirect_descriptors)
1818 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1819
1820 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1821 cmd_buffer->cs,
1822 MAX_SETS * MESA_SHADER_STAGES * 4);
1823
1824 if (cmd_buffer->state.pipeline) {
1825 radv_foreach_stage(stage, stages) {
1826 if (!cmd_buffer->state.pipeline->shaders[stage])
1827 continue;
1828
1829 radv_emit_descriptor_pointers(cmd_buffer,
1830 cmd_buffer->state.pipeline,
1831 descriptors_state, stage);
1832 }
1833 }
1834
1835 if (cmd_buffer->state.compute_pipeline &&
1836 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1837 radv_emit_descriptor_pointers(cmd_buffer,
1838 cmd_buffer->state.compute_pipeline,
1839 descriptors_state,
1840 MESA_SHADER_COMPUTE);
1841 }
1842
1843 descriptors_state->dirty = 0;
1844 descriptors_state->push_dirty = false;
1845
1846 assert(cmd_buffer->cs->cdw <= cdw_max);
1847
1848 if (unlikely(cmd_buffer->device->trace_bo))
1849 radv_save_descriptors(cmd_buffer, bind_point);
1850 }
1851
1852 static void
1853 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1854 VkShaderStageFlags stages)
1855 {
1856 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1857 ? cmd_buffer->state.compute_pipeline
1858 : cmd_buffer->state.pipeline;
1859 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1860 VK_PIPELINE_BIND_POINT_COMPUTE :
1861 VK_PIPELINE_BIND_POINT_GRAPHICS;
1862 struct radv_descriptor_state *descriptors_state =
1863 radv_get_descriptors_state(cmd_buffer, bind_point);
1864 struct radv_pipeline_layout *layout = pipeline->layout;
1865 struct radv_shader_variant *shader, *prev_shader;
1866 unsigned offset;
1867 void *ptr;
1868 uint64_t va;
1869
1870 stages &= cmd_buffer->push_constant_stages;
1871 if (!stages ||
1872 (!layout->push_constant_size && !layout->dynamic_offset_count))
1873 return;
1874
1875 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1876 16 * layout->dynamic_offset_count,
1877 256, &offset, &ptr))
1878 return;
1879
1880 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1881 memcpy((char*)ptr + layout->push_constant_size,
1882 descriptors_state->dynamic_buffers,
1883 16 * layout->dynamic_offset_count);
1884
1885 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1886 va += offset;
1887
1888 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1889 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1890
1891 prev_shader = NULL;
1892 radv_foreach_stage(stage, stages) {
1893 shader = radv_get_shader(pipeline, stage);
1894
1895 /* Avoid redundantly emitting the address for merged stages. */
1896 if (shader && shader != prev_shader) {
1897 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1898 AC_UD_PUSH_CONSTANTS, va);
1899
1900 prev_shader = shader;
1901 }
1902 }
1903
1904 cmd_buffer->push_constant_stages &= ~stages;
1905 assert(cmd_buffer->cs->cdw <= cdw_max);
1906 }
1907
1908 static void
1909 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1910 bool pipeline_is_dirty)
1911 {
1912 if ((pipeline_is_dirty ||
1913 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1914 cmd_buffer->state.pipeline->vertex_elements.count &&
1915 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1916 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1917 unsigned vb_offset;
1918 void *vb_ptr;
1919 uint32_t i = 0;
1920 uint32_t count = velems->count;
1921 uint64_t va;
1922
1923 /* allocate some descriptor state for vertex buffers */
1924 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1925 &vb_offset, &vb_ptr))
1926 return;
1927
1928 for (i = 0; i < count; i++) {
1929 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1930 uint32_t offset;
1931 int vb = velems->binding[i];
1932 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1933 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1934
1935 va = radv_buffer_get_va(buffer->bo);
1936
1937 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1938 va += offset + buffer->offset;
1939 desc[0] = va;
1940 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1941 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1942 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1943 else
1944 desc[2] = buffer->size - offset;
1945 desc[3] = velems->rsrc_word3[i];
1946 }
1947
1948 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1949 va += vb_offset;
1950
1951 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1952 AC_UD_VS_VERTEX_BUFFERS, va);
1953
1954 cmd_buffer->state.vb_va = va;
1955 cmd_buffer->state.vb_size = count * 16;
1956 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1957 }
1958 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1959 }
1960
1961 static void
1962 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1963 {
1964 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1965 struct radv_userdata_info *loc;
1966 uint32_t base_reg;
1967
1968 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1969 if (!radv_get_shader(pipeline, stage))
1970 continue;
1971
1972 loc = radv_lookup_user_sgpr(pipeline, stage,
1973 AC_UD_STREAMOUT_BUFFERS);
1974 if (loc->sgpr_idx == -1)
1975 continue;
1976
1977 base_reg = pipeline->user_data_0[stage];
1978
1979 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1980 base_reg + loc->sgpr_idx * 4, va, false);
1981 }
1982
1983 if (pipeline->gs_copy_shader) {
1984 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1985 if (loc->sgpr_idx != -1) {
1986 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1987
1988 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1989 base_reg + loc->sgpr_idx * 4, va, false);
1990 }
1991 }
1992 }
1993
1994 static void
1995 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1996 {
1997 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1998 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1999 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2000 unsigned so_offset;
2001 void *so_ptr;
2002 uint64_t va;
2003
2004 /* Allocate some descriptor state for streamout buffers. */
2005 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2006 MAX_SO_BUFFERS * 16, 256,
2007 &so_offset, &so_ptr))
2008 return;
2009
2010 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2011 struct radv_buffer *buffer = sb[i].buffer;
2012 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2013
2014 if (!(so->enabled_mask & (1 << i)))
2015 continue;
2016
2017 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2018
2019 va += sb[i].offset;
2020
2021 /* Set the descriptor.
2022 *
2023 * On VI, the format must be non-INVALID, otherwise
2024 * the buffer will be considered not bound and store
2025 * instructions will be no-ops.
2026 */
2027 desc[0] = va;
2028 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2029 desc[2] = 0xffffffff;
2030 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2031 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2032 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2033 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2034 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2035 }
2036
2037 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2038 va += so_offset;
2039
2040 radv_emit_streamout_buffers(cmd_buffer, va);
2041 }
2042
2043 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2044 }
2045
2046 static void
2047 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2048 {
2049 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2050 radv_flush_streamout_descriptors(cmd_buffer);
2051 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2052 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2053 }
2054
2055 static void
2056 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2057 bool instanced_draw, bool indirect_draw,
2058 uint32_t draw_vertex_count)
2059 {
2060 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2061 struct radv_cmd_state *state = &cmd_buffer->state;
2062 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2063 uint32_t ia_multi_vgt_param;
2064 int32_t primitive_reset_en;
2065
2066 /* Draw state. */
2067 ia_multi_vgt_param =
2068 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2069 indirect_draw, draw_vertex_count);
2070
2071 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2072 if (info->chip_class >= GFX9) {
2073 radeon_set_uconfig_reg_idx(cs,
2074 R_030960_IA_MULTI_VGT_PARAM,
2075 4, ia_multi_vgt_param);
2076 } else if (info->chip_class >= CIK) {
2077 radeon_set_context_reg_idx(cs,
2078 R_028AA8_IA_MULTI_VGT_PARAM,
2079 1, ia_multi_vgt_param);
2080 } else {
2081 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2082 ia_multi_vgt_param);
2083 }
2084 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2085 }
2086
2087 /* Primitive restart. */
2088 primitive_reset_en =
2089 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2090
2091 if (primitive_reset_en != state->last_primitive_reset_en) {
2092 state->last_primitive_reset_en = primitive_reset_en;
2093 if (info->chip_class >= GFX9) {
2094 radeon_set_uconfig_reg(cs,
2095 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2096 primitive_reset_en);
2097 } else {
2098 radeon_set_context_reg(cs,
2099 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2100 primitive_reset_en);
2101 }
2102 }
2103
2104 if (primitive_reset_en) {
2105 uint32_t primitive_reset_index =
2106 state->index_type ? 0xffffffffu : 0xffffu;
2107
2108 if (primitive_reset_index != state->last_primitive_reset_index) {
2109 radeon_set_context_reg(cs,
2110 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2111 primitive_reset_index);
2112 state->last_primitive_reset_index = primitive_reset_index;
2113 }
2114 }
2115 }
2116
2117 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2118 VkPipelineStageFlags src_stage_mask)
2119 {
2120 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2121 VK_PIPELINE_STAGE_TRANSFER_BIT |
2122 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2123 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2124 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2125 }
2126
2127 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2128 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2129 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2130 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2131 VK_PIPELINE_STAGE_TRANSFER_BIT |
2132 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2133 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2134 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2135 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2136 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2137 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2138 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2139 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2140 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2141 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2142 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2143 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2144 }
2145 }
2146
2147 static enum radv_cmd_flush_bits
2148 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2149 VkAccessFlags src_flags,
2150 struct radv_image *image)
2151 {
2152 bool flush_CB_meta = true, flush_DB_meta = true;
2153 enum radv_cmd_flush_bits flush_bits = 0;
2154 uint32_t b;
2155
2156 if (image) {
2157 if (!radv_image_has_CB_metadata(image))
2158 flush_CB_meta = false;
2159 if (!radv_image_has_htile(image))
2160 flush_DB_meta = false;
2161 }
2162
2163 for_each_bit(b, src_flags) {
2164 switch ((VkAccessFlagBits)(1 << b)) {
2165 case VK_ACCESS_SHADER_WRITE_BIT:
2166 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2167 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2168 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2169 break;
2170 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2171 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2172 if (flush_CB_meta)
2173 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2174 break;
2175 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2176 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2177 if (flush_DB_meta)
2178 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2179 break;
2180 case VK_ACCESS_TRANSFER_WRITE_BIT:
2181 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2182 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2183 RADV_CMD_FLAG_INV_GLOBAL_L2;
2184
2185 if (flush_CB_meta)
2186 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2187 if (flush_DB_meta)
2188 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2189 break;
2190 default:
2191 break;
2192 }
2193 }
2194 return flush_bits;
2195 }
2196
2197 static enum radv_cmd_flush_bits
2198 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2199 VkAccessFlags dst_flags,
2200 struct radv_image *image)
2201 {
2202 bool flush_CB_meta = true, flush_DB_meta = true;
2203 enum radv_cmd_flush_bits flush_bits = 0;
2204 bool flush_CB = true, flush_DB = true;
2205 bool image_is_coherent = false;
2206 uint32_t b;
2207
2208 if (image) {
2209 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2210 flush_CB = false;
2211 flush_DB = false;
2212 }
2213
2214 if (!radv_image_has_CB_metadata(image))
2215 flush_CB_meta = false;
2216 if (!radv_image_has_htile(image))
2217 flush_DB_meta = false;
2218
2219 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2220 if (image->info.samples == 1 &&
2221 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2222 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2223 !vk_format_is_stencil(image->vk_format)) {
2224 /* Single-sample color and single-sample depth
2225 * (not stencil) are coherent with shaders on
2226 * GFX9.
2227 */
2228 image_is_coherent = true;
2229 }
2230 }
2231 }
2232
2233 for_each_bit(b, dst_flags) {
2234 switch ((VkAccessFlagBits)(1 << b)) {
2235 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2236 case VK_ACCESS_INDEX_READ_BIT:
2237 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2238 break;
2239 case VK_ACCESS_UNIFORM_READ_BIT:
2240 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2241 break;
2242 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2243 case VK_ACCESS_TRANSFER_READ_BIT:
2244 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2245 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2246 RADV_CMD_FLAG_INV_GLOBAL_L2;
2247 break;
2248 case VK_ACCESS_SHADER_READ_BIT:
2249 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2250
2251 if (!image_is_coherent)
2252 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2253 break;
2254 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2255 if (flush_CB)
2256 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2257 if (flush_CB_meta)
2258 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2259 break;
2260 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2261 if (flush_DB)
2262 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2263 if (flush_DB_meta)
2264 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2265 break;
2266 default:
2267 break;
2268 }
2269 }
2270 return flush_bits;
2271 }
2272
2273 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2274 const struct radv_subpass_barrier *barrier)
2275 {
2276 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2277 NULL);
2278 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2279 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2280 NULL);
2281 }
2282
2283 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2284 struct radv_subpass_attachment att)
2285 {
2286 unsigned idx = att.attachment;
2287 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2288 VkImageSubresourceRange range;
2289 range.aspectMask = 0;
2290 range.baseMipLevel = view->base_mip;
2291 range.levelCount = 1;
2292 range.baseArrayLayer = view->base_layer;
2293 range.layerCount = cmd_buffer->state.framebuffer->layers;
2294
2295 radv_handle_image_transition(cmd_buffer,
2296 view->image,
2297 cmd_buffer->state.attachments[idx].current_layout,
2298 att.layout, 0, 0, &range);
2299
2300 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2301
2302
2303 }
2304
2305 void
2306 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2307 const struct radv_subpass *subpass, bool transitions)
2308 {
2309 if (transitions) {
2310 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2311
2312 for (unsigned i = 0; i < subpass->color_count; ++i) {
2313 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2314 radv_handle_subpass_image_transition(cmd_buffer,
2315 subpass->color_attachments[i]);
2316 }
2317
2318 for (unsigned i = 0; i < subpass->input_count; ++i) {
2319 radv_handle_subpass_image_transition(cmd_buffer,
2320 subpass->input_attachments[i]);
2321 }
2322
2323 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2324 radv_handle_subpass_image_transition(cmd_buffer,
2325 subpass->depth_stencil_attachment);
2326 }
2327 }
2328
2329 cmd_buffer->state.subpass = subpass;
2330
2331 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2332 }
2333
2334 static VkResult
2335 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2336 struct radv_render_pass *pass,
2337 const VkRenderPassBeginInfo *info)
2338 {
2339 struct radv_cmd_state *state = &cmd_buffer->state;
2340
2341 if (pass->attachment_count == 0) {
2342 state->attachments = NULL;
2343 return VK_SUCCESS;
2344 }
2345
2346 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2347 pass->attachment_count *
2348 sizeof(state->attachments[0]),
2349 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2350 if (state->attachments == NULL) {
2351 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2352 return cmd_buffer->record_result;
2353 }
2354
2355 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2356 struct radv_render_pass_attachment *att = &pass->attachments[i];
2357 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2358 VkImageAspectFlags clear_aspects = 0;
2359
2360 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2361 /* color attachment */
2362 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2363 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2364 }
2365 } else {
2366 /* depthstencil attachment */
2367 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2368 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2369 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2370 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2371 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2372 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2373 }
2374 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2375 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2376 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2377 }
2378 }
2379
2380 state->attachments[i].pending_clear_aspects = clear_aspects;
2381 state->attachments[i].cleared_views = 0;
2382 if (clear_aspects && info) {
2383 assert(info->clearValueCount > i);
2384 state->attachments[i].clear_value = info->pClearValues[i];
2385 }
2386
2387 state->attachments[i].current_layout = att->initial_layout;
2388 }
2389
2390 return VK_SUCCESS;
2391 }
2392
2393 VkResult radv_AllocateCommandBuffers(
2394 VkDevice _device,
2395 const VkCommandBufferAllocateInfo *pAllocateInfo,
2396 VkCommandBuffer *pCommandBuffers)
2397 {
2398 RADV_FROM_HANDLE(radv_device, device, _device);
2399 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2400
2401 VkResult result = VK_SUCCESS;
2402 uint32_t i;
2403
2404 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2405
2406 if (!list_empty(&pool->free_cmd_buffers)) {
2407 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2408
2409 list_del(&cmd_buffer->pool_link);
2410 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2411
2412 result = radv_reset_cmd_buffer(cmd_buffer);
2413 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2414 cmd_buffer->level = pAllocateInfo->level;
2415
2416 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2417 } else {
2418 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2419 &pCommandBuffers[i]);
2420 }
2421 if (result != VK_SUCCESS)
2422 break;
2423 }
2424
2425 if (result != VK_SUCCESS) {
2426 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2427 i, pCommandBuffers);
2428
2429 /* From the Vulkan 1.0.66 spec:
2430 *
2431 * "vkAllocateCommandBuffers can be used to create multiple
2432 * command buffers. If the creation of any of those command
2433 * buffers fails, the implementation must destroy all
2434 * successfully created command buffer objects from this
2435 * command, set all entries of the pCommandBuffers array to
2436 * NULL and return the error."
2437 */
2438 memset(pCommandBuffers, 0,
2439 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2440 }
2441
2442 return result;
2443 }
2444
2445 void radv_FreeCommandBuffers(
2446 VkDevice device,
2447 VkCommandPool commandPool,
2448 uint32_t commandBufferCount,
2449 const VkCommandBuffer *pCommandBuffers)
2450 {
2451 for (uint32_t i = 0; i < commandBufferCount; i++) {
2452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2453
2454 if (cmd_buffer) {
2455 if (cmd_buffer->pool) {
2456 list_del(&cmd_buffer->pool_link);
2457 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2458 } else
2459 radv_cmd_buffer_destroy(cmd_buffer);
2460
2461 }
2462 }
2463 }
2464
2465 VkResult radv_ResetCommandBuffer(
2466 VkCommandBuffer commandBuffer,
2467 VkCommandBufferResetFlags flags)
2468 {
2469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2470 return radv_reset_cmd_buffer(cmd_buffer);
2471 }
2472
2473 VkResult radv_BeginCommandBuffer(
2474 VkCommandBuffer commandBuffer,
2475 const VkCommandBufferBeginInfo *pBeginInfo)
2476 {
2477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2478 VkResult result = VK_SUCCESS;
2479
2480 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2481 /* If the command buffer has already been resetted with
2482 * vkResetCommandBuffer, no need to do it again.
2483 */
2484 result = radv_reset_cmd_buffer(cmd_buffer);
2485 if (result != VK_SUCCESS)
2486 return result;
2487 }
2488
2489 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2490 cmd_buffer->state.last_primitive_reset_en = -1;
2491 cmd_buffer->state.last_index_type = -1;
2492 cmd_buffer->state.last_num_instances = -1;
2493 cmd_buffer->state.last_vertex_offset = -1;
2494 cmd_buffer->state.last_first_instance = -1;
2495 cmd_buffer->state.predication_type = -1;
2496 cmd_buffer->usage_flags = pBeginInfo->flags;
2497
2498 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2499 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2500 assert(pBeginInfo->pInheritanceInfo);
2501 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2502 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2503
2504 struct radv_subpass *subpass =
2505 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2506
2507 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2508 if (result != VK_SUCCESS)
2509 return result;
2510
2511 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2512 }
2513
2514 if (unlikely(cmd_buffer->device->trace_bo)) {
2515 struct radv_device *device = cmd_buffer->device;
2516
2517 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2518 device->trace_bo);
2519
2520 radv_cmd_buffer_trace_emit(cmd_buffer);
2521 }
2522
2523 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2524
2525 return result;
2526 }
2527
2528 void radv_CmdBindVertexBuffers(
2529 VkCommandBuffer commandBuffer,
2530 uint32_t firstBinding,
2531 uint32_t bindingCount,
2532 const VkBuffer* pBuffers,
2533 const VkDeviceSize* pOffsets)
2534 {
2535 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2536 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2537 bool changed = false;
2538
2539 /* We have to defer setting up vertex buffer since we need the buffer
2540 * stride from the pipeline. */
2541
2542 assert(firstBinding + bindingCount <= MAX_VBS);
2543 for (uint32_t i = 0; i < bindingCount; i++) {
2544 uint32_t idx = firstBinding + i;
2545
2546 if (!changed &&
2547 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2548 vb[idx].offset != pOffsets[i])) {
2549 changed = true;
2550 }
2551
2552 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2553 vb[idx].offset = pOffsets[i];
2554
2555 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2556 vb[idx].buffer->bo);
2557 }
2558
2559 if (!changed) {
2560 /* No state changes. */
2561 return;
2562 }
2563
2564 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2565 }
2566
2567 void radv_CmdBindIndexBuffer(
2568 VkCommandBuffer commandBuffer,
2569 VkBuffer buffer,
2570 VkDeviceSize offset,
2571 VkIndexType indexType)
2572 {
2573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2574 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2575
2576 if (cmd_buffer->state.index_buffer == index_buffer &&
2577 cmd_buffer->state.index_offset == offset &&
2578 cmd_buffer->state.index_type == indexType) {
2579 /* No state changes. */
2580 return;
2581 }
2582
2583 cmd_buffer->state.index_buffer = index_buffer;
2584 cmd_buffer->state.index_offset = offset;
2585 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2586 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2587 cmd_buffer->state.index_va += index_buffer->offset + offset;
2588
2589 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2590 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2591 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2592 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2593 }
2594
2595
2596 static void
2597 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2598 VkPipelineBindPoint bind_point,
2599 struct radv_descriptor_set *set, unsigned idx)
2600 {
2601 struct radeon_winsys *ws = cmd_buffer->device->ws;
2602
2603 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2604
2605 assert(set);
2606 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2607
2608 if (!cmd_buffer->device->use_global_bo_list) {
2609 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2610 if (set->descriptors[j])
2611 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2612 }
2613
2614 if(set->bo)
2615 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2616 }
2617
2618 void radv_CmdBindDescriptorSets(
2619 VkCommandBuffer commandBuffer,
2620 VkPipelineBindPoint pipelineBindPoint,
2621 VkPipelineLayout _layout,
2622 uint32_t firstSet,
2623 uint32_t descriptorSetCount,
2624 const VkDescriptorSet* pDescriptorSets,
2625 uint32_t dynamicOffsetCount,
2626 const uint32_t* pDynamicOffsets)
2627 {
2628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2629 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2630 unsigned dyn_idx = 0;
2631
2632 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2633 struct radv_descriptor_state *descriptors_state =
2634 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2635
2636 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2637 unsigned idx = i + firstSet;
2638 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2639 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2640
2641 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2642 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2643 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2644 assert(dyn_idx < dynamicOffsetCount);
2645
2646 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2647 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2648 dst[0] = va;
2649 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2650 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2651 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2652 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2653 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2654 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2655 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2656 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2657 cmd_buffer->push_constant_stages |=
2658 set->layout->dynamic_shader_stages;
2659 }
2660 }
2661 }
2662
2663 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2664 struct radv_descriptor_set *set,
2665 struct radv_descriptor_set_layout *layout,
2666 VkPipelineBindPoint bind_point)
2667 {
2668 struct radv_descriptor_state *descriptors_state =
2669 radv_get_descriptors_state(cmd_buffer, bind_point);
2670 set->size = layout->size;
2671 set->layout = layout;
2672
2673 if (descriptors_state->push_set.capacity < set->size) {
2674 size_t new_size = MAX2(set->size, 1024);
2675 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2676 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2677
2678 free(set->mapped_ptr);
2679 set->mapped_ptr = malloc(new_size);
2680
2681 if (!set->mapped_ptr) {
2682 descriptors_state->push_set.capacity = 0;
2683 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2684 return false;
2685 }
2686
2687 descriptors_state->push_set.capacity = new_size;
2688 }
2689
2690 return true;
2691 }
2692
2693 void radv_meta_push_descriptor_set(
2694 struct radv_cmd_buffer* cmd_buffer,
2695 VkPipelineBindPoint pipelineBindPoint,
2696 VkPipelineLayout _layout,
2697 uint32_t set,
2698 uint32_t descriptorWriteCount,
2699 const VkWriteDescriptorSet* pDescriptorWrites)
2700 {
2701 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2702 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2703 unsigned bo_offset;
2704
2705 assert(set == 0);
2706 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2707
2708 push_set->size = layout->set[set].layout->size;
2709 push_set->layout = layout->set[set].layout;
2710
2711 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2712 &bo_offset,
2713 (void**) &push_set->mapped_ptr))
2714 return;
2715
2716 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2717 push_set->va += bo_offset;
2718
2719 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2720 radv_descriptor_set_to_handle(push_set),
2721 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2722
2723 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2724 }
2725
2726 void radv_CmdPushDescriptorSetKHR(
2727 VkCommandBuffer commandBuffer,
2728 VkPipelineBindPoint pipelineBindPoint,
2729 VkPipelineLayout _layout,
2730 uint32_t set,
2731 uint32_t descriptorWriteCount,
2732 const VkWriteDescriptorSet* pDescriptorWrites)
2733 {
2734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2735 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2736 struct radv_descriptor_state *descriptors_state =
2737 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2738 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2739
2740 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2741
2742 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2743 layout->set[set].layout,
2744 pipelineBindPoint))
2745 return;
2746
2747 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2748 radv_descriptor_set_to_handle(push_set),
2749 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2750
2751 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2752 descriptors_state->push_dirty = true;
2753 }
2754
2755 void radv_CmdPushDescriptorSetWithTemplateKHR(
2756 VkCommandBuffer commandBuffer,
2757 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2758 VkPipelineLayout _layout,
2759 uint32_t set,
2760 const void* pData)
2761 {
2762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2763 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2764 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2765 struct radv_descriptor_state *descriptors_state =
2766 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2767 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2768
2769 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2770
2771 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2772 layout->set[set].layout,
2773 templ->bind_point))
2774 return;
2775
2776 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2777 descriptorUpdateTemplate, pData);
2778
2779 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2780 descriptors_state->push_dirty = true;
2781 }
2782
2783 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2784 VkPipelineLayout layout,
2785 VkShaderStageFlags stageFlags,
2786 uint32_t offset,
2787 uint32_t size,
2788 const void* pValues)
2789 {
2790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2791 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2792 cmd_buffer->push_constant_stages |= stageFlags;
2793 }
2794
2795 VkResult radv_EndCommandBuffer(
2796 VkCommandBuffer commandBuffer)
2797 {
2798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2799
2800 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2801 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2802 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2803 si_emit_cache_flush(cmd_buffer);
2804 }
2805
2806 /* Make sure CP DMA is idle at the end of IBs because the kernel
2807 * doesn't wait for it.
2808 */
2809 si_cp_dma_wait_for_idle(cmd_buffer);
2810
2811 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2812
2813 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2814 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2815
2816 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2817
2818 return cmd_buffer->record_result;
2819 }
2820
2821 static void
2822 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2823 {
2824 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2825
2826 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2827 return;
2828
2829 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2830
2831 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2832 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2833
2834 cmd_buffer->compute_scratch_size_needed =
2835 MAX2(cmd_buffer->compute_scratch_size_needed,
2836 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2837
2838 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2839 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2840
2841 if (unlikely(cmd_buffer->device->trace_bo))
2842 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2843 }
2844
2845 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2846 VkPipelineBindPoint bind_point)
2847 {
2848 struct radv_descriptor_state *descriptors_state =
2849 radv_get_descriptors_state(cmd_buffer, bind_point);
2850
2851 descriptors_state->dirty |= descriptors_state->valid;
2852 }
2853
2854 void radv_CmdBindPipeline(
2855 VkCommandBuffer commandBuffer,
2856 VkPipelineBindPoint pipelineBindPoint,
2857 VkPipeline _pipeline)
2858 {
2859 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2860 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2861
2862 switch (pipelineBindPoint) {
2863 case VK_PIPELINE_BIND_POINT_COMPUTE:
2864 if (cmd_buffer->state.compute_pipeline == pipeline)
2865 return;
2866 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2867
2868 cmd_buffer->state.compute_pipeline = pipeline;
2869 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2870 break;
2871 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2872 if (cmd_buffer->state.pipeline == pipeline)
2873 return;
2874 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2875
2876 cmd_buffer->state.pipeline = pipeline;
2877 if (!pipeline)
2878 break;
2879
2880 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2881 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2882
2883 /* the new vertex shader might not have the same user regs */
2884 cmd_buffer->state.last_first_instance = -1;
2885 cmd_buffer->state.last_vertex_offset = -1;
2886
2887 /* Prefetch all pipeline shaders at first draw time. */
2888 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2889
2890 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2891 radv_bind_streamout_state(cmd_buffer, pipeline);
2892
2893 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2894 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2895 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2896 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2897
2898 if (radv_pipeline_has_tess(pipeline))
2899 cmd_buffer->tess_rings_needed = true;
2900 break;
2901 default:
2902 assert(!"invalid bind point");
2903 break;
2904 }
2905 }
2906
2907 void radv_CmdSetViewport(
2908 VkCommandBuffer commandBuffer,
2909 uint32_t firstViewport,
2910 uint32_t viewportCount,
2911 const VkViewport* pViewports)
2912 {
2913 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2914 struct radv_cmd_state *state = &cmd_buffer->state;
2915 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2916
2917 assert(firstViewport < MAX_VIEWPORTS);
2918 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2919
2920 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2921 viewportCount * sizeof(*pViewports));
2922
2923 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2924 }
2925
2926 void radv_CmdSetScissor(
2927 VkCommandBuffer commandBuffer,
2928 uint32_t firstScissor,
2929 uint32_t scissorCount,
2930 const VkRect2D* pScissors)
2931 {
2932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2933 struct radv_cmd_state *state = &cmd_buffer->state;
2934 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2935
2936 assert(firstScissor < MAX_SCISSORS);
2937 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2938
2939 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2940 scissorCount * sizeof(*pScissors));
2941
2942 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2943 }
2944
2945 void radv_CmdSetLineWidth(
2946 VkCommandBuffer commandBuffer,
2947 float lineWidth)
2948 {
2949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2950 cmd_buffer->state.dynamic.line_width = lineWidth;
2951 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2952 }
2953
2954 void radv_CmdSetDepthBias(
2955 VkCommandBuffer commandBuffer,
2956 float depthBiasConstantFactor,
2957 float depthBiasClamp,
2958 float depthBiasSlopeFactor)
2959 {
2960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2961
2962 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2963 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2964 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2965
2966 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2967 }
2968
2969 void radv_CmdSetBlendConstants(
2970 VkCommandBuffer commandBuffer,
2971 const float blendConstants[4])
2972 {
2973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2974
2975 memcpy(cmd_buffer->state.dynamic.blend_constants,
2976 blendConstants, sizeof(float) * 4);
2977
2978 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2979 }
2980
2981 void radv_CmdSetDepthBounds(
2982 VkCommandBuffer commandBuffer,
2983 float minDepthBounds,
2984 float maxDepthBounds)
2985 {
2986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2987
2988 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2989 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2990
2991 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2992 }
2993
2994 void radv_CmdSetStencilCompareMask(
2995 VkCommandBuffer commandBuffer,
2996 VkStencilFaceFlags faceMask,
2997 uint32_t compareMask)
2998 {
2999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3000
3001 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3002 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
3003 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3004 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
3005
3006 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3007 }
3008
3009 void radv_CmdSetStencilWriteMask(
3010 VkCommandBuffer commandBuffer,
3011 VkStencilFaceFlags faceMask,
3012 uint32_t writeMask)
3013 {
3014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3015
3016 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3017 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
3018 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3019 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
3020
3021 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3022 }
3023
3024 void radv_CmdSetStencilReference(
3025 VkCommandBuffer commandBuffer,
3026 VkStencilFaceFlags faceMask,
3027 uint32_t reference)
3028 {
3029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3030
3031 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3032 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3033 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3034 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3035
3036 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3037 }
3038
3039 void radv_CmdSetDiscardRectangleEXT(
3040 VkCommandBuffer commandBuffer,
3041 uint32_t firstDiscardRectangle,
3042 uint32_t discardRectangleCount,
3043 const VkRect2D* pDiscardRectangles)
3044 {
3045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3046 struct radv_cmd_state *state = &cmd_buffer->state;
3047 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3048
3049 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3050 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3051
3052 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3053 pDiscardRectangles, discardRectangleCount);
3054
3055 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3056 }
3057
3058 void radv_CmdExecuteCommands(
3059 VkCommandBuffer commandBuffer,
3060 uint32_t commandBufferCount,
3061 const VkCommandBuffer* pCmdBuffers)
3062 {
3063 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3064
3065 assert(commandBufferCount > 0);
3066
3067 /* Emit pending flushes on primary prior to executing secondary */
3068 si_emit_cache_flush(primary);
3069
3070 for (uint32_t i = 0; i < commandBufferCount; i++) {
3071 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3072
3073 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3074 secondary->scratch_size_needed);
3075 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3076 secondary->compute_scratch_size_needed);
3077
3078 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3079 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3080 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3081 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3082 if (secondary->tess_rings_needed)
3083 primary->tess_rings_needed = true;
3084 if (secondary->sample_positions_needed)
3085 primary->sample_positions_needed = true;
3086
3087 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3088
3089
3090 /* When the secondary command buffer is compute only we don't
3091 * need to re-emit the current graphics pipeline.
3092 */
3093 if (secondary->state.emitted_pipeline) {
3094 primary->state.emitted_pipeline =
3095 secondary->state.emitted_pipeline;
3096 }
3097
3098 /* When the secondary command buffer is graphics only we don't
3099 * need to re-emit the current compute pipeline.
3100 */
3101 if (secondary->state.emitted_compute_pipeline) {
3102 primary->state.emitted_compute_pipeline =
3103 secondary->state.emitted_compute_pipeline;
3104 }
3105
3106 /* Only re-emit the draw packets when needed. */
3107 if (secondary->state.last_primitive_reset_en != -1) {
3108 primary->state.last_primitive_reset_en =
3109 secondary->state.last_primitive_reset_en;
3110 }
3111
3112 if (secondary->state.last_primitive_reset_index) {
3113 primary->state.last_primitive_reset_index =
3114 secondary->state.last_primitive_reset_index;
3115 }
3116
3117 if (secondary->state.last_ia_multi_vgt_param) {
3118 primary->state.last_ia_multi_vgt_param =
3119 secondary->state.last_ia_multi_vgt_param;
3120 }
3121
3122 primary->state.last_first_instance = secondary->state.last_first_instance;
3123 primary->state.last_num_instances = secondary->state.last_num_instances;
3124 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3125
3126 if (secondary->state.last_index_type != -1) {
3127 primary->state.last_index_type =
3128 secondary->state.last_index_type;
3129 }
3130 }
3131
3132 /* After executing commands from secondary buffers we have to dirty
3133 * some states.
3134 */
3135 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3136 RADV_CMD_DIRTY_INDEX_BUFFER |
3137 RADV_CMD_DIRTY_DYNAMIC_ALL;
3138 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3139 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3140 }
3141
3142 VkResult radv_CreateCommandPool(
3143 VkDevice _device,
3144 const VkCommandPoolCreateInfo* pCreateInfo,
3145 const VkAllocationCallbacks* pAllocator,
3146 VkCommandPool* pCmdPool)
3147 {
3148 RADV_FROM_HANDLE(radv_device, device, _device);
3149 struct radv_cmd_pool *pool;
3150
3151 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3153 if (pool == NULL)
3154 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3155
3156 if (pAllocator)
3157 pool->alloc = *pAllocator;
3158 else
3159 pool->alloc = device->alloc;
3160
3161 list_inithead(&pool->cmd_buffers);
3162 list_inithead(&pool->free_cmd_buffers);
3163
3164 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3165
3166 *pCmdPool = radv_cmd_pool_to_handle(pool);
3167
3168 return VK_SUCCESS;
3169
3170 }
3171
3172 void radv_DestroyCommandPool(
3173 VkDevice _device,
3174 VkCommandPool commandPool,
3175 const VkAllocationCallbacks* pAllocator)
3176 {
3177 RADV_FROM_HANDLE(radv_device, device, _device);
3178 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3179
3180 if (!pool)
3181 return;
3182
3183 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3184 &pool->cmd_buffers, pool_link) {
3185 radv_cmd_buffer_destroy(cmd_buffer);
3186 }
3187
3188 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3189 &pool->free_cmd_buffers, pool_link) {
3190 radv_cmd_buffer_destroy(cmd_buffer);
3191 }
3192
3193 vk_free2(&device->alloc, pAllocator, pool);
3194 }
3195
3196 VkResult radv_ResetCommandPool(
3197 VkDevice device,
3198 VkCommandPool commandPool,
3199 VkCommandPoolResetFlags flags)
3200 {
3201 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3202 VkResult result;
3203
3204 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3205 &pool->cmd_buffers, pool_link) {
3206 result = radv_reset_cmd_buffer(cmd_buffer);
3207 if (result != VK_SUCCESS)
3208 return result;
3209 }
3210
3211 return VK_SUCCESS;
3212 }
3213
3214 void radv_TrimCommandPool(
3215 VkDevice device,
3216 VkCommandPool commandPool,
3217 VkCommandPoolTrimFlagsKHR flags)
3218 {
3219 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3220
3221 if (!pool)
3222 return;
3223
3224 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3225 &pool->free_cmd_buffers, pool_link) {
3226 radv_cmd_buffer_destroy(cmd_buffer);
3227 }
3228 }
3229
3230 void radv_CmdBeginRenderPass(
3231 VkCommandBuffer commandBuffer,
3232 const VkRenderPassBeginInfo* pRenderPassBegin,
3233 VkSubpassContents contents)
3234 {
3235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3236 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3237 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3238
3239 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3240 cmd_buffer->cs, 2048);
3241 MAYBE_UNUSED VkResult result;
3242
3243 cmd_buffer->state.framebuffer = framebuffer;
3244 cmd_buffer->state.pass = pass;
3245 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3246
3247 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3248 if (result != VK_SUCCESS)
3249 return;
3250
3251 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3252 assert(cmd_buffer->cs->cdw <= cdw_max);
3253
3254 radv_cmd_buffer_clear_subpass(cmd_buffer);
3255 }
3256
3257 void radv_CmdBeginRenderPass2KHR(
3258 VkCommandBuffer commandBuffer,
3259 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3260 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3261 {
3262 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3263 pSubpassBeginInfo->contents);
3264 }
3265
3266 void radv_CmdNextSubpass(
3267 VkCommandBuffer commandBuffer,
3268 VkSubpassContents contents)
3269 {
3270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3271
3272 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3273
3274 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3275 2048);
3276
3277 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3278 radv_cmd_buffer_clear_subpass(cmd_buffer);
3279 }
3280
3281 void radv_CmdNextSubpass2KHR(
3282 VkCommandBuffer commandBuffer,
3283 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3284 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3285 {
3286 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3287 }
3288
3289 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3290 {
3291 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3292 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3293 if (!radv_get_shader(pipeline, stage))
3294 continue;
3295
3296 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3297 if (loc->sgpr_idx == -1)
3298 continue;
3299 uint32_t base_reg = pipeline->user_data_0[stage];
3300 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3301
3302 }
3303 if (pipeline->gs_copy_shader) {
3304 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3305 if (loc->sgpr_idx != -1) {
3306 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3307 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3308 }
3309 }
3310 }
3311
3312 static void
3313 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3314 uint32_t vertex_count,
3315 bool use_opaque)
3316 {
3317 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3318 radeon_emit(cmd_buffer->cs, vertex_count);
3319 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3320 S_0287F0_USE_OPAQUE(use_opaque));
3321 }
3322
3323 static void
3324 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3325 uint64_t index_va,
3326 uint32_t index_count)
3327 {
3328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3329 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3330 radeon_emit(cmd_buffer->cs, index_va);
3331 radeon_emit(cmd_buffer->cs, index_va >> 32);
3332 radeon_emit(cmd_buffer->cs, index_count);
3333 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3334 }
3335
3336 static void
3337 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3338 bool indexed,
3339 uint32_t draw_count,
3340 uint64_t count_va,
3341 uint32_t stride)
3342 {
3343 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3344 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3345 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3346 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3347 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3348 bool predicating = cmd_buffer->state.predicating;
3349 assert(base_reg);
3350
3351 /* just reset draw state for vertex data */
3352 cmd_buffer->state.last_first_instance = -1;
3353 cmd_buffer->state.last_num_instances = -1;
3354 cmd_buffer->state.last_vertex_offset = -1;
3355
3356 if (draw_count == 1 && !count_va && !draw_id_enable) {
3357 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3358 PKT3_DRAW_INDIRECT, 3, predicating));
3359 radeon_emit(cs, 0);
3360 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3361 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3362 radeon_emit(cs, di_src_sel);
3363 } else {
3364 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3365 PKT3_DRAW_INDIRECT_MULTI,
3366 8, predicating));
3367 radeon_emit(cs, 0);
3368 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3369 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3370 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3371 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3372 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3373 radeon_emit(cs, draw_count); /* count */
3374 radeon_emit(cs, count_va); /* count_addr */
3375 radeon_emit(cs, count_va >> 32);
3376 radeon_emit(cs, stride); /* stride */
3377 radeon_emit(cs, di_src_sel);
3378 }
3379 }
3380
3381 struct radv_draw_info {
3382 /**
3383 * Number of vertices.
3384 */
3385 uint32_t count;
3386
3387 /**
3388 * Index of the first vertex.
3389 */
3390 int32_t vertex_offset;
3391
3392 /**
3393 * First instance id.
3394 */
3395 uint32_t first_instance;
3396
3397 /**
3398 * Number of instances.
3399 */
3400 uint32_t instance_count;
3401
3402 /**
3403 * First index (indexed draws only).
3404 */
3405 uint32_t first_index;
3406
3407 /**
3408 * Whether it's an indexed draw.
3409 */
3410 bool indexed;
3411
3412 /**
3413 * Indirect draw parameters resource.
3414 */
3415 struct radv_buffer *indirect;
3416 uint64_t indirect_offset;
3417 uint32_t stride;
3418
3419 /**
3420 * Draw count parameters resource.
3421 */
3422 struct radv_buffer *count_buffer;
3423 uint64_t count_buffer_offset;
3424
3425 /**
3426 * Stream output parameters resource.
3427 */
3428 struct radv_buffer *strmout_buffer;
3429 uint64_t strmout_buffer_offset;
3430 };
3431
3432 static void
3433 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3434 const struct radv_draw_info *info)
3435 {
3436 struct radv_cmd_state *state = &cmd_buffer->state;
3437 struct radeon_winsys *ws = cmd_buffer->device->ws;
3438 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3439
3440 if (info->strmout_buffer) {
3441 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3442
3443 va += info->strmout_buffer->offset +
3444 info->strmout_buffer_offset;
3445
3446 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3447 info->stride);
3448
3449 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3450 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3451 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3452 COPY_DATA_WR_CONFIRM);
3453 radeon_emit(cs, va);
3454 radeon_emit(cs, va >> 32);
3455 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3456 radeon_emit(cs, 0); /* unused */
3457
3458 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3459 }
3460
3461 if (info->indirect) {
3462 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3463 uint64_t count_va = 0;
3464
3465 va += info->indirect->offset + info->indirect_offset;
3466
3467 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3468
3469 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3470 radeon_emit(cs, 1);
3471 radeon_emit(cs, va);
3472 radeon_emit(cs, va >> 32);
3473
3474 if (info->count_buffer) {
3475 count_va = radv_buffer_get_va(info->count_buffer->bo);
3476 count_va += info->count_buffer->offset +
3477 info->count_buffer_offset;
3478
3479 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3480 }
3481
3482 if (!state->subpass->view_mask) {
3483 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3484 info->indexed,
3485 info->count,
3486 count_va,
3487 info->stride);
3488 } else {
3489 unsigned i;
3490 for_each_bit(i, state->subpass->view_mask) {
3491 radv_emit_view_index(cmd_buffer, i);
3492
3493 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3494 info->indexed,
3495 info->count,
3496 count_va,
3497 info->stride);
3498 }
3499 }
3500 } else {
3501 assert(state->pipeline->graphics.vtx_base_sgpr);
3502
3503 if (info->vertex_offset != state->last_vertex_offset ||
3504 info->first_instance != state->last_first_instance) {
3505 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3506 state->pipeline->graphics.vtx_emit_num);
3507
3508 radeon_emit(cs, info->vertex_offset);
3509 radeon_emit(cs, info->first_instance);
3510 if (state->pipeline->graphics.vtx_emit_num == 3)
3511 radeon_emit(cs, 0);
3512 state->last_first_instance = info->first_instance;
3513 state->last_vertex_offset = info->vertex_offset;
3514 }
3515
3516 if (state->last_num_instances != info->instance_count) {
3517 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3518 radeon_emit(cs, info->instance_count);
3519 state->last_num_instances = info->instance_count;
3520 }
3521
3522 if (info->indexed) {
3523 int index_size = state->index_type ? 4 : 2;
3524 uint64_t index_va;
3525
3526 index_va = state->index_va;
3527 index_va += info->first_index * index_size;
3528
3529 if (!state->subpass->view_mask) {
3530 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3531 index_va,
3532 info->count);
3533 } else {
3534 unsigned i;
3535 for_each_bit(i, state->subpass->view_mask) {
3536 radv_emit_view_index(cmd_buffer, i);
3537
3538 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3539 index_va,
3540 info->count);
3541 }
3542 }
3543 } else {
3544 if (!state->subpass->view_mask) {
3545 radv_cs_emit_draw_packet(cmd_buffer,
3546 info->count,
3547 !!info->strmout_buffer);
3548 } else {
3549 unsigned i;
3550 for_each_bit(i, state->subpass->view_mask) {
3551 radv_emit_view_index(cmd_buffer, i);
3552
3553 radv_cs_emit_draw_packet(cmd_buffer,
3554 info->count,
3555 !!info->strmout_buffer);
3556 }
3557 }
3558 }
3559 }
3560 }
3561
3562 /*
3563 * Vega and raven have a bug which triggers if there are multiple context
3564 * register contexts active at the same time with different scissor values.
3565 *
3566 * There are two possible workarounds:
3567 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3568 * there is only ever 1 active set of scissor values at the same time.
3569 *
3570 * 2) Whenever the hardware switches contexts we have to set the scissor
3571 * registers again even if it is a noop. That way the new context gets
3572 * the correct scissor values.
3573 *
3574 * This implements option 2. radv_need_late_scissor_emission needs to
3575 * return true on affected HW if radv_emit_all_graphics_states sets
3576 * any context registers.
3577 */
3578 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3579 bool indexed_draw)
3580 {
3581 struct radv_cmd_state *state = &cmd_buffer->state;
3582
3583 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3584 return false;
3585
3586 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3587
3588 /* Index, vertex and streamout buffers don't change context regs, and
3589 * pipeline is handled later.
3590 */
3591 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3592 RADV_CMD_DIRTY_VERTEX_BUFFER |
3593 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3594 RADV_CMD_DIRTY_PIPELINE);
3595
3596 /* Assume all state changes except these two can imply context rolls. */
3597 if (cmd_buffer->state.dirty & used_states)
3598 return true;
3599
3600 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3601 return true;
3602
3603 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3604 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3605 return true;
3606
3607 return false;
3608 }
3609
3610 static void
3611 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3612 const struct radv_draw_info *info)
3613 {
3614 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3615
3616 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3617 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3618 radv_emit_rbplus_state(cmd_buffer);
3619
3620 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3621 radv_emit_graphics_pipeline(cmd_buffer);
3622
3623 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3624 radv_emit_framebuffer_state(cmd_buffer);
3625
3626 if (info->indexed) {
3627 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3628 radv_emit_index_buffer(cmd_buffer);
3629 } else {
3630 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3631 * so the state must be re-emitted before the next indexed
3632 * draw.
3633 */
3634 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3635 cmd_buffer->state.last_index_type = -1;
3636 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3637 }
3638 }
3639
3640 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3641
3642 radv_emit_draw_registers(cmd_buffer, info->indexed,
3643 info->instance_count > 1, info->indirect,
3644 info->indirect ? 0 : info->count);
3645
3646 if (late_scissor_emission)
3647 radv_emit_scissor(cmd_buffer);
3648 }
3649
3650 static void
3651 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3652 const struct radv_draw_info *info)
3653 {
3654 struct radeon_info *rad_info =
3655 &cmd_buffer->device->physical_device->rad_info;
3656 bool has_prefetch =
3657 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3658 bool pipeline_is_dirty =
3659 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3660 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3661
3662 MAYBE_UNUSED unsigned cdw_max =
3663 radeon_check_space(cmd_buffer->device->ws,
3664 cmd_buffer->cs, 4096);
3665
3666 /* Use optimal packet order based on whether we need to sync the
3667 * pipeline.
3668 */
3669 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3670 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3671 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3672 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3673 /* If we have to wait for idle, set all states first, so that
3674 * all SET packets are processed in parallel with previous draw
3675 * calls. Then upload descriptors, set shader pointers, and
3676 * draw, and prefetch at the end. This ensures that the time
3677 * the CUs are idle is very short. (there are only SET_SH
3678 * packets between the wait and the draw)
3679 */
3680 radv_emit_all_graphics_states(cmd_buffer, info);
3681 si_emit_cache_flush(cmd_buffer);
3682 /* <-- CUs are idle here --> */
3683
3684 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3685
3686 radv_emit_draw_packets(cmd_buffer, info);
3687 /* <-- CUs are busy here --> */
3688
3689 /* Start prefetches after the draw has been started. Both will
3690 * run in parallel, but starting the draw first is more
3691 * important.
3692 */
3693 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3694 radv_emit_prefetch_L2(cmd_buffer,
3695 cmd_buffer->state.pipeline, false);
3696 }
3697 } else {
3698 /* If we don't wait for idle, start prefetches first, then set
3699 * states, and draw at the end.
3700 */
3701 si_emit_cache_flush(cmd_buffer);
3702
3703 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3704 /* Only prefetch the vertex shader and VBO descriptors
3705 * in order to start the draw as soon as possible.
3706 */
3707 radv_emit_prefetch_L2(cmd_buffer,
3708 cmd_buffer->state.pipeline, true);
3709 }
3710
3711 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3712
3713 radv_emit_all_graphics_states(cmd_buffer, info);
3714 radv_emit_draw_packets(cmd_buffer, info);
3715
3716 /* Prefetch the remaining shaders after the draw has been
3717 * started.
3718 */
3719 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3720 radv_emit_prefetch_L2(cmd_buffer,
3721 cmd_buffer->state.pipeline, false);
3722 }
3723 }
3724
3725 /* Workaround for a VGT hang when streamout is enabled.
3726 * It must be done after drawing.
3727 */
3728 if (cmd_buffer->state.streamout.streamout_enabled &&
3729 (rad_info->family == CHIP_HAWAII ||
3730 rad_info->family == CHIP_TONGA ||
3731 rad_info->family == CHIP_FIJI)) {
3732 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3733 }
3734
3735 assert(cmd_buffer->cs->cdw <= cdw_max);
3736 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3737 }
3738
3739 void radv_CmdDraw(
3740 VkCommandBuffer commandBuffer,
3741 uint32_t vertexCount,
3742 uint32_t instanceCount,
3743 uint32_t firstVertex,
3744 uint32_t firstInstance)
3745 {
3746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3747 struct radv_draw_info info = {};
3748
3749 info.count = vertexCount;
3750 info.instance_count = instanceCount;
3751 info.first_instance = firstInstance;
3752 info.vertex_offset = firstVertex;
3753
3754 radv_draw(cmd_buffer, &info);
3755 }
3756
3757 void radv_CmdDrawIndexed(
3758 VkCommandBuffer commandBuffer,
3759 uint32_t indexCount,
3760 uint32_t instanceCount,
3761 uint32_t firstIndex,
3762 int32_t vertexOffset,
3763 uint32_t firstInstance)
3764 {
3765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3766 struct radv_draw_info info = {};
3767
3768 info.indexed = true;
3769 info.count = indexCount;
3770 info.instance_count = instanceCount;
3771 info.first_index = firstIndex;
3772 info.vertex_offset = vertexOffset;
3773 info.first_instance = firstInstance;
3774
3775 radv_draw(cmd_buffer, &info);
3776 }
3777
3778 void radv_CmdDrawIndirect(
3779 VkCommandBuffer commandBuffer,
3780 VkBuffer _buffer,
3781 VkDeviceSize offset,
3782 uint32_t drawCount,
3783 uint32_t stride)
3784 {
3785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3786 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3787 struct radv_draw_info info = {};
3788
3789 info.count = drawCount;
3790 info.indirect = buffer;
3791 info.indirect_offset = offset;
3792 info.stride = stride;
3793
3794 radv_draw(cmd_buffer, &info);
3795 }
3796
3797 void radv_CmdDrawIndexedIndirect(
3798 VkCommandBuffer commandBuffer,
3799 VkBuffer _buffer,
3800 VkDeviceSize offset,
3801 uint32_t drawCount,
3802 uint32_t stride)
3803 {
3804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3805 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3806 struct radv_draw_info info = {};
3807
3808 info.indexed = true;
3809 info.count = drawCount;
3810 info.indirect = buffer;
3811 info.indirect_offset = offset;
3812 info.stride = stride;
3813
3814 radv_draw(cmd_buffer, &info);
3815 }
3816
3817 void radv_CmdDrawIndirectCountAMD(
3818 VkCommandBuffer commandBuffer,
3819 VkBuffer _buffer,
3820 VkDeviceSize offset,
3821 VkBuffer _countBuffer,
3822 VkDeviceSize countBufferOffset,
3823 uint32_t maxDrawCount,
3824 uint32_t stride)
3825 {
3826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3827 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3828 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3829 struct radv_draw_info info = {};
3830
3831 info.count = maxDrawCount;
3832 info.indirect = buffer;
3833 info.indirect_offset = offset;
3834 info.count_buffer = count_buffer;
3835 info.count_buffer_offset = countBufferOffset;
3836 info.stride = stride;
3837
3838 radv_draw(cmd_buffer, &info);
3839 }
3840
3841 void radv_CmdDrawIndexedIndirectCountAMD(
3842 VkCommandBuffer commandBuffer,
3843 VkBuffer _buffer,
3844 VkDeviceSize offset,
3845 VkBuffer _countBuffer,
3846 VkDeviceSize countBufferOffset,
3847 uint32_t maxDrawCount,
3848 uint32_t stride)
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3851 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3852 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3853 struct radv_draw_info info = {};
3854
3855 info.indexed = true;
3856 info.count = maxDrawCount;
3857 info.indirect = buffer;
3858 info.indirect_offset = offset;
3859 info.count_buffer = count_buffer;
3860 info.count_buffer_offset = countBufferOffset;
3861 info.stride = stride;
3862
3863 radv_draw(cmd_buffer, &info);
3864 }
3865
3866 void radv_CmdDrawIndirectCountKHR(
3867 VkCommandBuffer commandBuffer,
3868 VkBuffer _buffer,
3869 VkDeviceSize offset,
3870 VkBuffer _countBuffer,
3871 VkDeviceSize countBufferOffset,
3872 uint32_t maxDrawCount,
3873 uint32_t stride)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3877 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3878 struct radv_draw_info info = {};
3879
3880 info.count = maxDrawCount;
3881 info.indirect = buffer;
3882 info.indirect_offset = offset;
3883 info.count_buffer = count_buffer;
3884 info.count_buffer_offset = countBufferOffset;
3885 info.stride = stride;
3886
3887 radv_draw(cmd_buffer, &info);
3888 }
3889
3890 void radv_CmdDrawIndexedIndirectCountKHR(
3891 VkCommandBuffer commandBuffer,
3892 VkBuffer _buffer,
3893 VkDeviceSize offset,
3894 VkBuffer _countBuffer,
3895 VkDeviceSize countBufferOffset,
3896 uint32_t maxDrawCount,
3897 uint32_t stride)
3898 {
3899 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3900 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3901 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3902 struct radv_draw_info info = {};
3903
3904 info.indexed = true;
3905 info.count = maxDrawCount;
3906 info.indirect = buffer;
3907 info.indirect_offset = offset;
3908 info.count_buffer = count_buffer;
3909 info.count_buffer_offset = countBufferOffset;
3910 info.stride = stride;
3911
3912 radv_draw(cmd_buffer, &info);
3913 }
3914
3915 struct radv_dispatch_info {
3916 /**
3917 * Determine the layout of the grid (in block units) to be used.
3918 */
3919 uint32_t blocks[3];
3920
3921 /**
3922 * A starting offset for the grid. If unaligned is set, the offset
3923 * must still be aligned.
3924 */
3925 uint32_t offsets[3];
3926 /**
3927 * Whether it's an unaligned compute dispatch.
3928 */
3929 bool unaligned;
3930
3931 /**
3932 * Indirect compute parameters resource.
3933 */
3934 struct radv_buffer *indirect;
3935 uint64_t indirect_offset;
3936 };
3937
3938 static void
3939 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3940 const struct radv_dispatch_info *info)
3941 {
3942 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3943 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3944 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3945 struct radeon_winsys *ws = cmd_buffer->device->ws;
3946 bool predicating = cmd_buffer->state.predicating;
3947 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3948 struct radv_userdata_info *loc;
3949
3950 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3951 AC_UD_CS_GRID_SIZE);
3952
3953 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3954
3955 if (info->indirect) {
3956 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3957
3958 va += info->indirect->offset + info->indirect_offset;
3959
3960 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3961
3962 if (loc->sgpr_idx != -1) {
3963 for (unsigned i = 0; i < 3; ++i) {
3964 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3965 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3966 COPY_DATA_DST_SEL(COPY_DATA_REG));
3967 radeon_emit(cs, (va + 4 * i));
3968 radeon_emit(cs, (va + 4 * i) >> 32);
3969 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3970 + loc->sgpr_idx * 4) >> 2) + i);
3971 radeon_emit(cs, 0);
3972 }
3973 }
3974
3975 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3976 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3977 PKT3_SHADER_TYPE_S(1));
3978 radeon_emit(cs, va);
3979 radeon_emit(cs, va >> 32);
3980 radeon_emit(cs, dispatch_initiator);
3981 } else {
3982 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3983 PKT3_SHADER_TYPE_S(1));
3984 radeon_emit(cs, 1);
3985 radeon_emit(cs, va);
3986 radeon_emit(cs, va >> 32);
3987
3988 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3989 PKT3_SHADER_TYPE_S(1));
3990 radeon_emit(cs, 0);
3991 radeon_emit(cs, dispatch_initiator);
3992 }
3993 } else {
3994 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3995 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3996
3997 if (info->unaligned) {
3998 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3999 unsigned remainder[3];
4000
4001 /* If aligned, these should be an entire block size,
4002 * not 0.
4003 */
4004 remainder[0] = blocks[0] + cs_block_size[0] -
4005 align_u32_npot(blocks[0], cs_block_size[0]);
4006 remainder[1] = blocks[1] + cs_block_size[1] -
4007 align_u32_npot(blocks[1], cs_block_size[1]);
4008 remainder[2] = blocks[2] + cs_block_size[2] -
4009 align_u32_npot(blocks[2], cs_block_size[2]);
4010
4011 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4012 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4013 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4014
4015 for(unsigned i = 0; i < 3; ++i) {
4016 assert(offsets[i] % cs_block_size[i] == 0);
4017 offsets[i] /= cs_block_size[i];
4018 }
4019
4020 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4021 radeon_emit(cs,
4022 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4023 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4024 radeon_emit(cs,
4025 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4026 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4027 radeon_emit(cs,
4028 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4029 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4030
4031 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4032 }
4033
4034 if (loc->sgpr_idx != -1) {
4035 assert(!loc->indirect);
4036 assert(loc->num_sgprs == 3);
4037
4038 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4039 loc->sgpr_idx * 4, 3);
4040 radeon_emit(cs, blocks[0]);
4041 radeon_emit(cs, blocks[1]);
4042 radeon_emit(cs, blocks[2]);
4043 }
4044
4045 if (offsets[0] || offsets[1] || offsets[2]) {
4046 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4047 radeon_emit(cs, offsets[0]);
4048 radeon_emit(cs, offsets[1]);
4049 radeon_emit(cs, offsets[2]);
4050
4051 /* The blocks in the packet are not counts but end values. */
4052 for (unsigned i = 0; i < 3; ++i)
4053 blocks[i] += offsets[i];
4054 } else {
4055 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4056 }
4057
4058 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4059 PKT3_SHADER_TYPE_S(1));
4060 radeon_emit(cs, blocks[0]);
4061 radeon_emit(cs, blocks[1]);
4062 radeon_emit(cs, blocks[2]);
4063 radeon_emit(cs, dispatch_initiator);
4064 }
4065
4066 assert(cmd_buffer->cs->cdw <= cdw_max);
4067 }
4068
4069 static void
4070 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4071 {
4072 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4073 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4074 }
4075
4076 static void
4077 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4078 const struct radv_dispatch_info *info)
4079 {
4080 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4081 bool has_prefetch =
4082 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4083 bool pipeline_is_dirty = pipeline &&
4084 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4085
4086 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4087 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4088 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4089 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4090 /* If we have to wait for idle, set all states first, so that
4091 * all SET packets are processed in parallel with previous draw
4092 * calls. Then upload descriptors, set shader pointers, and
4093 * dispatch, and prefetch at the end. This ensures that the
4094 * time the CUs are idle is very short. (there are only SET_SH
4095 * packets between the wait and the draw)
4096 */
4097 radv_emit_compute_pipeline(cmd_buffer);
4098 si_emit_cache_flush(cmd_buffer);
4099 /* <-- CUs are idle here --> */
4100
4101 radv_upload_compute_shader_descriptors(cmd_buffer);
4102
4103 radv_emit_dispatch_packets(cmd_buffer, info);
4104 /* <-- CUs are busy here --> */
4105
4106 /* Start prefetches after the dispatch has been started. Both
4107 * will run in parallel, but starting the dispatch first is
4108 * more important.
4109 */
4110 if (has_prefetch && pipeline_is_dirty) {
4111 radv_emit_shader_prefetch(cmd_buffer,
4112 pipeline->shaders[MESA_SHADER_COMPUTE]);
4113 }
4114 } else {
4115 /* If we don't wait for idle, start prefetches first, then set
4116 * states, and dispatch at the end.
4117 */
4118 si_emit_cache_flush(cmd_buffer);
4119
4120 if (has_prefetch && pipeline_is_dirty) {
4121 radv_emit_shader_prefetch(cmd_buffer,
4122 pipeline->shaders[MESA_SHADER_COMPUTE]);
4123 }
4124
4125 radv_upload_compute_shader_descriptors(cmd_buffer);
4126
4127 radv_emit_compute_pipeline(cmd_buffer);
4128 radv_emit_dispatch_packets(cmd_buffer, info);
4129 }
4130
4131 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4132 }
4133
4134 void radv_CmdDispatchBase(
4135 VkCommandBuffer commandBuffer,
4136 uint32_t base_x,
4137 uint32_t base_y,
4138 uint32_t base_z,
4139 uint32_t x,
4140 uint32_t y,
4141 uint32_t z)
4142 {
4143 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4144 struct radv_dispatch_info info = {};
4145
4146 info.blocks[0] = x;
4147 info.blocks[1] = y;
4148 info.blocks[2] = z;
4149
4150 info.offsets[0] = base_x;
4151 info.offsets[1] = base_y;
4152 info.offsets[2] = base_z;
4153 radv_dispatch(cmd_buffer, &info);
4154 }
4155
4156 void radv_CmdDispatch(
4157 VkCommandBuffer commandBuffer,
4158 uint32_t x,
4159 uint32_t y,
4160 uint32_t z)
4161 {
4162 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4163 }
4164
4165 void radv_CmdDispatchIndirect(
4166 VkCommandBuffer commandBuffer,
4167 VkBuffer _buffer,
4168 VkDeviceSize offset)
4169 {
4170 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4171 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4172 struct radv_dispatch_info info = {};
4173
4174 info.indirect = buffer;
4175 info.indirect_offset = offset;
4176
4177 radv_dispatch(cmd_buffer, &info);
4178 }
4179
4180 void radv_unaligned_dispatch(
4181 struct radv_cmd_buffer *cmd_buffer,
4182 uint32_t x,
4183 uint32_t y,
4184 uint32_t z)
4185 {
4186 struct radv_dispatch_info info = {};
4187
4188 info.blocks[0] = x;
4189 info.blocks[1] = y;
4190 info.blocks[2] = z;
4191 info.unaligned = 1;
4192
4193 radv_dispatch(cmd_buffer, &info);
4194 }
4195
4196 void radv_CmdEndRenderPass(
4197 VkCommandBuffer commandBuffer)
4198 {
4199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4200
4201 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4202
4203 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4204
4205 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4206 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4207 radv_handle_subpass_image_transition(cmd_buffer,
4208 (struct radv_subpass_attachment){i, layout});
4209 }
4210
4211 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4212
4213 cmd_buffer->state.pass = NULL;
4214 cmd_buffer->state.subpass = NULL;
4215 cmd_buffer->state.attachments = NULL;
4216 cmd_buffer->state.framebuffer = NULL;
4217 }
4218
4219 void radv_CmdEndRenderPass2KHR(
4220 VkCommandBuffer commandBuffer,
4221 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4222 {
4223 radv_CmdEndRenderPass(commandBuffer);
4224 }
4225
4226 /*
4227 * For HTILE we have the following interesting clear words:
4228 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4229 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4230 * 0xfffffff0: Clear depth to 1.0
4231 * 0x00000000: Clear depth to 0.0
4232 */
4233 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4234 struct radv_image *image,
4235 const VkImageSubresourceRange *range,
4236 uint32_t clear_word)
4237 {
4238 assert(range->baseMipLevel == 0);
4239 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4240 unsigned layer_count = radv_get_layerCount(image, range);
4241 uint64_t size = image->surface.htile_slice_size * layer_count;
4242 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4243 uint64_t offset = image->offset + image->htile_offset +
4244 image->surface.htile_slice_size * range->baseArrayLayer;
4245 struct radv_cmd_state *state = &cmd_buffer->state;
4246 VkClearDepthStencilValue value = {};
4247
4248 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4249 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4250
4251 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4252 size, clear_word);
4253
4254 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4255
4256 if (vk_format_is_stencil(image->vk_format))
4257 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4258
4259 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4260
4261 if (radv_image_is_tc_compat_htile(image)) {
4262 /* Initialize the TC-compat metada value to 0 because by
4263 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4264 * need have to conditionally update its value when performing
4265 * a fast depth clear.
4266 */
4267 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4268 }
4269 }
4270
4271 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4272 struct radv_image *image,
4273 VkImageLayout src_layout,
4274 VkImageLayout dst_layout,
4275 unsigned src_queue_mask,
4276 unsigned dst_queue_mask,
4277 const VkImageSubresourceRange *range)
4278 {
4279 if (!radv_image_has_htile(image))
4280 return;
4281
4282 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4283 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4284 /* TODO: merge with the clear if applicable */
4285 radv_initialize_htile(cmd_buffer, image, range, 0);
4286 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4287 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4288 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4289 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4290 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4291 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4292 VkImageSubresourceRange local_range = *range;
4293 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4294 local_range.baseMipLevel = 0;
4295 local_range.levelCount = 1;
4296
4297 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4298 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4299
4300 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4301
4302 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4303 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4304 }
4305 }
4306
4307 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4308 struct radv_image *image, uint32_t value)
4309 {
4310 struct radv_cmd_state *state = &cmd_buffer->state;
4311
4312 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4313 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4314
4315 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4316
4317 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4318 }
4319
4320 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4321 struct radv_image *image, uint32_t value)
4322 {
4323 struct radv_cmd_state *state = &cmd_buffer->state;
4324
4325 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4326 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4327
4328 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4329
4330 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4331 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4332 }
4333
4334 /**
4335 * Initialize DCC/FMASK/CMASK metadata for a color image.
4336 */
4337 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4338 struct radv_image *image,
4339 VkImageLayout src_layout,
4340 VkImageLayout dst_layout,
4341 unsigned src_queue_mask,
4342 unsigned dst_queue_mask)
4343 {
4344 if (radv_image_has_cmask(image)) {
4345 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4346
4347 /* TODO: clarify this. */
4348 if (radv_image_has_fmask(image)) {
4349 value = 0xccccccccu;
4350 }
4351
4352 radv_initialise_cmask(cmd_buffer, image, value);
4353 }
4354
4355 if (radv_image_has_dcc(image)) {
4356 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4357 bool need_decompress_pass = false;
4358
4359 if (radv_layout_dcc_compressed(image, dst_layout,
4360 dst_queue_mask)) {
4361 value = 0x20202020u;
4362 need_decompress_pass = true;
4363 }
4364
4365 radv_initialize_dcc(cmd_buffer, image, value);
4366
4367 radv_update_fce_metadata(cmd_buffer, image,
4368 need_decompress_pass);
4369 }
4370
4371 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4372 uint32_t color_values[2] = {};
4373 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4374 }
4375 }
4376
4377 /**
4378 * Handle color image transitions for DCC/FMASK/CMASK.
4379 */
4380 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4381 struct radv_image *image,
4382 VkImageLayout src_layout,
4383 VkImageLayout dst_layout,
4384 unsigned src_queue_mask,
4385 unsigned dst_queue_mask,
4386 const VkImageSubresourceRange *range)
4387 {
4388 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4389 radv_init_color_image_metadata(cmd_buffer, image,
4390 src_layout, dst_layout,
4391 src_queue_mask, dst_queue_mask);
4392 return;
4393 }
4394
4395 if (radv_image_has_dcc(image)) {
4396 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4397 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4398 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4399 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4400 radv_decompress_dcc(cmd_buffer, image, range);
4401 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4402 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4403 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4404 }
4405 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4406 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4407 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4408 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4409 }
4410 }
4411 }
4412
4413 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4414 struct radv_image *image,
4415 VkImageLayout src_layout,
4416 VkImageLayout dst_layout,
4417 uint32_t src_family,
4418 uint32_t dst_family,
4419 const VkImageSubresourceRange *range)
4420 {
4421 if (image->exclusive && src_family != dst_family) {
4422 /* This is an acquire or a release operation and there will be
4423 * a corresponding release/acquire. Do the transition in the
4424 * most flexible queue. */
4425
4426 assert(src_family == cmd_buffer->queue_family_index ||
4427 dst_family == cmd_buffer->queue_family_index);
4428
4429 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4430 return;
4431
4432 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4433 (src_family == RADV_QUEUE_GENERAL ||
4434 dst_family == RADV_QUEUE_GENERAL))
4435 return;
4436 }
4437
4438 unsigned src_queue_mask =
4439 radv_image_queue_family_mask(image, src_family,
4440 cmd_buffer->queue_family_index);
4441 unsigned dst_queue_mask =
4442 radv_image_queue_family_mask(image, dst_family,
4443 cmd_buffer->queue_family_index);
4444
4445 if (vk_format_is_depth(image->vk_format)) {
4446 radv_handle_depth_image_transition(cmd_buffer, image,
4447 src_layout, dst_layout,
4448 src_queue_mask, dst_queue_mask,
4449 range);
4450 } else {
4451 radv_handle_color_image_transition(cmd_buffer, image,
4452 src_layout, dst_layout,
4453 src_queue_mask, dst_queue_mask,
4454 range);
4455 }
4456 }
4457
4458 struct radv_barrier_info {
4459 uint32_t eventCount;
4460 const VkEvent *pEvents;
4461 VkPipelineStageFlags srcStageMask;
4462 };
4463
4464 static void
4465 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4466 uint32_t memoryBarrierCount,
4467 const VkMemoryBarrier *pMemoryBarriers,
4468 uint32_t bufferMemoryBarrierCount,
4469 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4470 uint32_t imageMemoryBarrierCount,
4471 const VkImageMemoryBarrier *pImageMemoryBarriers,
4472 const struct radv_barrier_info *info)
4473 {
4474 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4475 enum radv_cmd_flush_bits src_flush_bits = 0;
4476 enum radv_cmd_flush_bits dst_flush_bits = 0;
4477
4478 for (unsigned i = 0; i < info->eventCount; ++i) {
4479 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4480 uint64_t va = radv_buffer_get_va(event->bo);
4481
4482 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4483
4484 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4485
4486 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4487 assert(cmd_buffer->cs->cdw <= cdw_max);
4488 }
4489
4490 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4491 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4492 NULL);
4493 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4494 NULL);
4495 }
4496
4497 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4498 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4499 NULL);
4500 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4501 NULL);
4502 }
4503
4504 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4505 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4506
4507 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4508 image);
4509 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4510 image);
4511 }
4512
4513 radv_stage_flush(cmd_buffer, info->srcStageMask);
4514 cmd_buffer->state.flush_bits |= src_flush_bits;
4515
4516 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4517 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4518 radv_handle_image_transition(cmd_buffer, image,
4519 pImageMemoryBarriers[i].oldLayout,
4520 pImageMemoryBarriers[i].newLayout,
4521 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4522 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4523 &pImageMemoryBarriers[i].subresourceRange);
4524 }
4525
4526 /* Make sure CP DMA is idle because the driver might have performed a
4527 * DMA operation for copying or filling buffers/images.
4528 */
4529 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4530 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4531 si_cp_dma_wait_for_idle(cmd_buffer);
4532
4533 cmd_buffer->state.flush_bits |= dst_flush_bits;
4534 }
4535
4536 void radv_CmdPipelineBarrier(
4537 VkCommandBuffer commandBuffer,
4538 VkPipelineStageFlags srcStageMask,
4539 VkPipelineStageFlags destStageMask,
4540 VkBool32 byRegion,
4541 uint32_t memoryBarrierCount,
4542 const VkMemoryBarrier* pMemoryBarriers,
4543 uint32_t bufferMemoryBarrierCount,
4544 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4545 uint32_t imageMemoryBarrierCount,
4546 const VkImageMemoryBarrier* pImageMemoryBarriers)
4547 {
4548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4549 struct radv_barrier_info info;
4550
4551 info.eventCount = 0;
4552 info.pEvents = NULL;
4553 info.srcStageMask = srcStageMask;
4554
4555 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4556 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4557 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4558 }
4559
4560
4561 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4562 struct radv_event *event,
4563 VkPipelineStageFlags stageMask,
4564 unsigned value)
4565 {
4566 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4567 uint64_t va = radv_buffer_get_va(event->bo);
4568
4569 si_emit_cache_flush(cmd_buffer);
4570
4571 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4572
4573 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4574
4575 /* Flags that only require a top-of-pipe event. */
4576 VkPipelineStageFlags top_of_pipe_flags =
4577 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4578
4579 /* Flags that only require a post-index-fetch event. */
4580 VkPipelineStageFlags post_index_fetch_flags =
4581 top_of_pipe_flags |
4582 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4583 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4584
4585 /* Make sure CP DMA is idle because the driver might have performed a
4586 * DMA operation for copying or filling buffers/images.
4587 */
4588 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4589 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4590 si_cp_dma_wait_for_idle(cmd_buffer);
4591
4592 /* TODO: Emit EOS events for syncing PS/CS stages. */
4593
4594 if (!(stageMask & ~top_of_pipe_flags)) {
4595 /* Just need to sync the PFP engine. */
4596 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4597 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4598 S_370_WR_CONFIRM(1) |
4599 S_370_ENGINE_SEL(V_370_PFP));
4600 radeon_emit(cs, va);
4601 radeon_emit(cs, va >> 32);
4602 radeon_emit(cs, value);
4603 } else if (!(stageMask & ~post_index_fetch_flags)) {
4604 /* Sync ME because PFP reads index and indirect buffers. */
4605 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4606 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4607 S_370_WR_CONFIRM(1) |
4608 S_370_ENGINE_SEL(V_370_ME));
4609 radeon_emit(cs, va);
4610 radeon_emit(cs, va >> 32);
4611 radeon_emit(cs, value);
4612 } else {
4613 /* Otherwise, sync all prior GPU work using an EOP event. */
4614 si_cs_emit_write_event_eop(cs,
4615 cmd_buffer->device->physical_device->rad_info.chip_class,
4616 radv_cmd_buffer_uses_mec(cmd_buffer),
4617 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4618 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4619 cmd_buffer->gfx9_eop_bug_va);
4620 }
4621
4622 assert(cmd_buffer->cs->cdw <= cdw_max);
4623 }
4624
4625 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4626 VkEvent _event,
4627 VkPipelineStageFlags stageMask)
4628 {
4629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4630 RADV_FROM_HANDLE(radv_event, event, _event);
4631
4632 write_event(cmd_buffer, event, stageMask, 1);
4633 }
4634
4635 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4636 VkEvent _event,
4637 VkPipelineStageFlags stageMask)
4638 {
4639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4640 RADV_FROM_HANDLE(radv_event, event, _event);
4641
4642 write_event(cmd_buffer, event, stageMask, 0);
4643 }
4644
4645 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4646 uint32_t eventCount,
4647 const VkEvent* pEvents,
4648 VkPipelineStageFlags srcStageMask,
4649 VkPipelineStageFlags dstStageMask,
4650 uint32_t memoryBarrierCount,
4651 const VkMemoryBarrier* pMemoryBarriers,
4652 uint32_t bufferMemoryBarrierCount,
4653 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4654 uint32_t imageMemoryBarrierCount,
4655 const VkImageMemoryBarrier* pImageMemoryBarriers)
4656 {
4657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4658 struct radv_barrier_info info;
4659
4660 info.eventCount = eventCount;
4661 info.pEvents = pEvents;
4662 info.srcStageMask = 0;
4663
4664 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4665 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4666 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4667 }
4668
4669
4670 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4671 uint32_t deviceMask)
4672 {
4673 /* No-op */
4674 }
4675
4676 /* VK_EXT_conditional_rendering */
4677 void radv_CmdBeginConditionalRenderingEXT(
4678 VkCommandBuffer commandBuffer,
4679 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4680 {
4681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4682 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4683 bool draw_visible = true;
4684 uint64_t va;
4685
4686 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4687
4688 /* By default, if the 32-bit value at offset in buffer memory is zero,
4689 * then the rendering commands are discarded, otherwise they are
4690 * executed as normal. If the inverted flag is set, all commands are
4691 * discarded if the value is non zero.
4692 */
4693 if (pConditionalRenderingBegin->flags &
4694 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4695 draw_visible = false;
4696 }
4697
4698 /* Enable predication for this command buffer. */
4699 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4700 cmd_buffer->state.predicating = true;
4701
4702 /* Store conditional rendering user info. */
4703 cmd_buffer->state.predication_type = draw_visible;
4704 cmd_buffer->state.predication_va = va;
4705 }
4706
4707 void radv_CmdEndConditionalRenderingEXT(
4708 VkCommandBuffer commandBuffer)
4709 {
4710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4711
4712 /* Disable predication for this command buffer. */
4713 si_emit_set_predication_state(cmd_buffer, false, 0);
4714 cmd_buffer->state.predicating = false;
4715
4716 /* Reset conditional rendering user info. */
4717 cmd_buffer->state.predication_type = -1;
4718 cmd_buffer->state.predication_va = 0;
4719 }
4720
4721 /* VK_EXT_transform_feedback */
4722 void radv_CmdBindTransformFeedbackBuffersEXT(
4723 VkCommandBuffer commandBuffer,
4724 uint32_t firstBinding,
4725 uint32_t bindingCount,
4726 const VkBuffer* pBuffers,
4727 const VkDeviceSize* pOffsets,
4728 const VkDeviceSize* pSizes)
4729 {
4730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4731 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4732 uint8_t enabled_mask = 0;
4733
4734 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4735 for (uint32_t i = 0; i < bindingCount; i++) {
4736 uint32_t idx = firstBinding + i;
4737
4738 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4739 sb[idx].offset = pOffsets[i];
4740 sb[idx].size = pSizes[i];
4741
4742 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4743 sb[idx].buffer->bo);
4744
4745 enabled_mask |= 1 << idx;
4746 }
4747
4748 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4749
4750 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4751 }
4752
4753 static void
4754 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4755 {
4756 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4757 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4758
4759 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4760 radeon_emit(cs,
4761 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4762 S_028B94_RAST_STREAM(0) |
4763 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4764 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4765 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4766 radeon_emit(cs, so->hw_enabled_mask &
4767 so->enabled_stream_buffers_mask);
4768 }
4769
4770 static void
4771 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4772 {
4773 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4774 bool old_streamout_enabled = so->streamout_enabled;
4775 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4776
4777 so->streamout_enabled = enable;
4778
4779 so->hw_enabled_mask = so->enabled_mask |
4780 (so->enabled_mask << 4) |
4781 (so->enabled_mask << 8) |
4782 (so->enabled_mask << 12);
4783
4784 if ((old_streamout_enabled != so->streamout_enabled) ||
4785 (old_hw_enabled_mask != so->hw_enabled_mask))
4786 radv_emit_streamout_enable(cmd_buffer);
4787 }
4788
4789 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4790 {
4791 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4792 unsigned reg_strmout_cntl;
4793
4794 /* The register is at different places on different ASICs. */
4795 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4796 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4797 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4798 } else {
4799 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4800 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4801 }
4802
4803 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4804 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4805
4806 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4807 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4808 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4809 radeon_emit(cs, 0);
4810 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4811 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4812 radeon_emit(cs, 4); /* poll interval */
4813 }
4814
4815 void radv_CmdBeginTransformFeedbackEXT(
4816 VkCommandBuffer commandBuffer,
4817 uint32_t firstCounterBuffer,
4818 uint32_t counterBufferCount,
4819 const VkBuffer* pCounterBuffers,
4820 const VkDeviceSize* pCounterBufferOffsets)
4821 {
4822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4823 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4824 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4825 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4826 uint32_t i;
4827
4828 radv_flush_vgt_streamout(cmd_buffer);
4829
4830 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4831 for_each_bit(i, so->enabled_mask) {
4832 int32_t counter_buffer_idx = i - firstCounterBuffer;
4833 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4834 counter_buffer_idx = -1;
4835
4836 /* SI binds streamout buffers as shader resources.
4837 * VGT only counts primitives and tells the shader through
4838 * SGPRs what to do.
4839 */
4840 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4841 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4842 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4843
4844 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4845 /* The array of counter buffers is optional. */
4846 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4847 uint64_t va = radv_buffer_get_va(buffer->bo);
4848
4849 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4850
4851 /* Append */
4852 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4853 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4854 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4855 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4856 radeon_emit(cs, 0); /* unused */
4857 radeon_emit(cs, 0); /* unused */
4858 radeon_emit(cs, va); /* src address lo */
4859 radeon_emit(cs, va >> 32); /* src address hi */
4860
4861 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4862 } else {
4863 /* Start from the beginning. */
4864 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4865 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4866 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4867 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4868 radeon_emit(cs, 0); /* unused */
4869 radeon_emit(cs, 0); /* unused */
4870 radeon_emit(cs, 0); /* unused */
4871 radeon_emit(cs, 0); /* unused */
4872 }
4873 }
4874
4875 radv_set_streamout_enable(cmd_buffer, true);
4876 }
4877
4878 void radv_CmdEndTransformFeedbackEXT(
4879 VkCommandBuffer commandBuffer,
4880 uint32_t firstCounterBuffer,
4881 uint32_t counterBufferCount,
4882 const VkBuffer* pCounterBuffers,
4883 const VkDeviceSize* pCounterBufferOffsets)
4884 {
4885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4886 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4887 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4888 uint32_t i;
4889
4890 radv_flush_vgt_streamout(cmd_buffer);
4891
4892 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4893 for_each_bit(i, so->enabled_mask) {
4894 int32_t counter_buffer_idx = i - firstCounterBuffer;
4895 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4896 counter_buffer_idx = -1;
4897
4898 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4899 /* The array of counters buffer is optional. */
4900 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4901 uint64_t va = radv_buffer_get_va(buffer->bo);
4902
4903 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4904
4905 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4906 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4907 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4908 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4909 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4910 radeon_emit(cs, va); /* dst address lo */
4911 radeon_emit(cs, va >> 32); /* dst address hi */
4912 radeon_emit(cs, 0); /* unused */
4913 radeon_emit(cs, 0); /* unused */
4914
4915 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4916 }
4917
4918 /* Deactivate transform feedback by zeroing the buffer size.
4919 * The counters (primitives generated, primitives emitted) may
4920 * be enabled even if there is not buffer bound. This ensures
4921 * that the primitives-emitted query won't increment.
4922 */
4923 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4924 }
4925
4926 radv_set_streamout_enable(cmd_buffer, false);
4927 }
4928
4929 void radv_CmdDrawIndirectByteCountEXT(
4930 VkCommandBuffer commandBuffer,
4931 uint32_t instanceCount,
4932 uint32_t firstInstance,
4933 VkBuffer _counterBuffer,
4934 VkDeviceSize counterBufferOffset,
4935 uint32_t counterOffset,
4936 uint32_t vertexStride)
4937 {
4938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4939 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4940 struct radv_draw_info info = {};
4941
4942 info.instance_count = instanceCount;
4943 info.first_instance = firstInstance;
4944 info.strmout_buffer = counterBuffer;
4945 info.strmout_buffer_offset = counterBufferOffset;
4946 info.stride = vertexStride;
4947
4948 radv_draw(cmd_buffer, &info);
4949 }