projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: load the fast color clear values from the base level
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image_view *iview,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249 struct radv_image *image = iview->image;
1250
1251 if (!radv_layout_dcc_compressed(image, layout,
1252 radv_image_queue_family_mask(image,
1253 cmd_buffer->queue_family_index,
1254 cmd_buffer->queue_family_index))) {
1255 cb_color_info &= C_028C70_DCC_ENABLE;
1256 }
1257
1258 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1259 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1260 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1261 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1262 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1263 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1264 radeon_emit(cmd_buffer->cs, cb_color_info);
1265 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1266 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1267 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1268 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1270 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1271
1272 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1273 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1274 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1275
1276 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1277 cb->cb_mrt_epitch);
1278 } else {
1279 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1282 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1283 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1284 radeon_emit(cmd_buffer->cs, cb_color_info);
1285 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1286 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1288 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1290 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1291
1292 if (is_vi) { /* DCC BASE */
1293 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1294 }
1295 }
1296
1297 if (radv_image_has_dcc(image)) {
1298 /* Drawing with DCC enabled also compresses colorbuffers. */
1299 VkImageSubresourceRange range = {
1300 .aspectMask = iview->aspect_mask,
1301 .baseMipLevel = iview->base_mip,
1302 .levelCount = iview->level_count,
1303 .baseArrayLayer = iview->base_layer,
1304 .layerCount = iview->layer_count,
1305 };
1306
1307 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1308 }
1309 }
1310
1311 static void
1312 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_ds_buffer_info *ds,
1314 struct radv_image *image, VkImageLayout layout,
1315 bool requires_cond_exec)
1316 {
1317 uint32_t db_z_info = ds->db_z_info;
1318 uint32_t db_z_info_reg;
1319
1320 if (!radv_image_is_tc_compat_htile(image))
1321 return;
1322
1323 if (!radv_layout_has_htile(image, layout,
1324 radv_image_queue_family_mask(image,
1325 cmd_buffer->queue_family_index,
1326 cmd_buffer->queue_family_index))) {
1327 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1328 }
1329
1330 db_z_info &= C_028040_ZRANGE_PRECISION;
1331
1332 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1333 db_z_info_reg = R_028038_DB_Z_INFO;
1334 } else {
1335 db_z_info_reg = R_028040_DB_Z_INFO;
1336 }
1337
1338 /* When we don't know the last fast clear value we need to emit a
1339 * conditional packet that will eventually skip the following
1340 * SET_CONTEXT_REG packet.
1341 */
1342 if (requires_cond_exec) {
1343 uint64_t va = radv_buffer_get_va(image->bo);
1344 va += image->offset + image->tc_compat_zrange_offset;
1345
1346 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1347 radeon_emit(cmd_buffer->cs, va);
1348 radeon_emit(cmd_buffer->cs, va >> 32);
1349 radeon_emit(cmd_buffer->cs, 0);
1350 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1351 }
1352
1353 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1354 }
1355
1356 static void
1357 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1358 struct radv_ds_buffer_info *ds,
1359 struct radv_image *image,
1360 VkImageLayout layout)
1361 {
1362 uint32_t db_z_info = ds->db_z_info;
1363 uint32_t db_stencil_info = ds->db_stencil_info;
1364
1365 if (!radv_layout_has_htile(image, layout,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1370 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1371 }
1372
1373 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1374 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1375
1376
1377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1378 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1379 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1380 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1381 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1382
1383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1384 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1385 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1386 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1387 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1388 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1389 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1390 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1391 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1392 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1393 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1394
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1396 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1398 } else {
1399 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1400
1401 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1402 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1403 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1404 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1405 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1406 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1407 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1408 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1409 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1410 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1411
1412 }
1413
1414 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1415 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1416
1417 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1418 ds->pa_su_poly_offset_db_fmt_cntl);
1419 }
1420
1421 /**
1422 * Update the fast clear depth/stencil values if the image is bound as a
1423 * depth/stencil buffer.
1424 */
1425 static void
1426 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_image *image,
1428 VkClearDepthStencilValue ds_clear_value,
1429 VkImageAspectFlags aspects)
1430 {
1431 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1432 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1433 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1434 struct radv_attachment_info *att;
1435 uint32_t att_idx;
1436
1437 if (!framebuffer || !subpass)
1438 return;
1439
1440 if (!subpass->depth_stencil_attachment)
1441 return;
1442
1443 att_idx = subpass->depth_stencil_attachment->attachment;
1444 att = &framebuffer->attachments[att_idx];
1445 if (att->attachment->image != image)
1446 return;
1447
1448 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1449 radeon_emit(cs, ds_clear_value.stencil);
1450 radeon_emit(cs, fui(ds_clear_value.depth));
1451
1452 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1453 * only needed when clearing Z to 0.0.
1454 */
1455 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1456 ds_clear_value.depth == 0.0) {
1457 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1458
1459 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1460 layout, false);
1461 }
1462
1463 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1464 }
1465
1466 /**
1467 * Set the clear depth/stencil values to the image's metadata.
1468 */
1469 static void
1470 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1471 struct radv_image *image,
1472 VkClearDepthStencilValue ds_clear_value,
1473 VkImageAspectFlags aspects)
1474 {
1475 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1476 uint64_t va = radv_buffer_get_va(image->bo);
1477 unsigned reg_offset = 0, reg_count = 0;
1478
1479 va += image->offset + image->clear_value_offset;
1480
1481 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1482 ++reg_count;
1483 } else {
1484 ++reg_offset;
1485 va += 4;
1486 }
1487 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1488 ++reg_count;
1489
1490 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1491 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1492 S_370_WR_CONFIRM(1) |
1493 S_370_ENGINE_SEL(V_370_PFP));
1494 radeon_emit(cs, va);
1495 radeon_emit(cs, va >> 32);
1496 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1497 radeon_emit(cs, ds_clear_value.stencil);
1498 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1499 radeon_emit(cs, fui(ds_clear_value.depth));
1500 }
1501
1502 /**
1503 * Update the TC-compat metadata value for this image.
1504 */
1505 static void
1506 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1507 struct radv_image *image,
1508 uint32_t value)
1509 {
1510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1511 uint64_t va = radv_buffer_get_va(image->bo);
1512 va += image->offset + image->tc_compat_zrange_offset;
1513
1514 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1515 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1516 S_370_WR_CONFIRM(1) |
1517 S_370_ENGINE_SEL(V_370_PFP));
1518 radeon_emit(cs, va);
1519 radeon_emit(cs, va >> 32);
1520 radeon_emit(cs, value);
1521 }
1522
1523 static void
1524 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1525 struct radv_image *image,
1526 VkClearDepthStencilValue ds_clear_value)
1527 {
1528 uint64_t va = radv_buffer_get_va(image->bo);
1529 va += image->offset + image->tc_compat_zrange_offset;
1530 uint32_t cond_val;
1531
1532 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1533 * depth clear value is 0.0f.
1534 */
1535 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1536
1537 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1538 }
1539
1540 /**
1541 * Update the clear depth/stencil values for this image.
1542 */
1543 void
1544 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1545 struct radv_image *image,
1546 VkClearDepthStencilValue ds_clear_value,
1547 VkImageAspectFlags aspects)
1548 {
1549 assert(radv_image_has_htile(image));
1550
1551 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1552
1553 if (radv_image_is_tc_compat_htile(image) &&
1554 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1555 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1556 ds_clear_value);
1557 }
1558
1559 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1560 aspects);
1561 }
1562
1563 /**
1564 * Load the clear depth/stencil values from the image's metadata.
1565 */
1566 static void
1567 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_image *image)
1569 {
1570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1571 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1572 uint64_t va = radv_buffer_get_va(image->bo);
1573 unsigned reg_offset = 0, reg_count = 0;
1574
1575 va += image->offset + image->clear_value_offset;
1576
1577 if (!radv_image_has_htile(image))
1578 return;
1579
1580 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1581 ++reg_count;
1582 } else {
1583 ++reg_offset;
1584 va += 4;
1585 }
1586 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1587 ++reg_count;
1588
1589 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1590
1591 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1592 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1593 radeon_emit(cs, va);
1594 radeon_emit(cs, va >> 32);
1595 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1596 radeon_emit(cs, reg_count);
1597 } else {
1598 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1599 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1600 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1601 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1602 radeon_emit(cs, va);
1603 radeon_emit(cs, va >> 32);
1604 radeon_emit(cs, reg >> 2);
1605 radeon_emit(cs, 0);
1606
1607 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1608 radeon_emit(cs, 0);
1609 }
1610 }
1611
1612 /*
1613 * With DCC some colors don't require CMASK elimination before being
1614 * used as a texture. This sets a predicate value to determine if the
1615 * cmask eliminate is required.
1616 */
1617 void
1618 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1619 struct radv_image *image,
1620 const VkImageSubresourceRange *range, bool value)
1621 {
1622 uint64_t pred_val = value;
1623 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1624 uint32_t level_count = radv_get_levelCount(image, range);
1625 uint32_t count = 2 * level_count;
1626
1627 assert(radv_image_has_dcc(image));
1628
1629 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1630 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1631 S_370_WR_CONFIRM(1) |
1632 S_370_ENGINE_SEL(V_370_PFP));
1633 radeon_emit(cmd_buffer->cs, va);
1634 radeon_emit(cmd_buffer->cs, va >> 32);
1635
1636 for (uint32_t l = 0; l < level_count; l++) {
1637 radeon_emit(cmd_buffer->cs, pred_val);
1638 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1639 }
1640 }
1641
1642 /**
1643 * Update the DCC predicate to reflect the compression state.
1644 */
1645 void
1646 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1647 struct radv_image *image,
1648 const VkImageSubresourceRange *range, bool value)
1649 {
1650 uint64_t pred_val = value;
1651 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1652 uint32_t level_count = radv_get_levelCount(image, range);
1653 uint32_t count = 2 * level_count;
1654
1655 assert(radv_image_has_dcc(image));
1656
1657 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1658 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1659 S_370_WR_CONFIRM(1) |
1660 S_370_ENGINE_SEL(V_370_PFP));
1661 radeon_emit(cmd_buffer->cs, va);
1662 radeon_emit(cmd_buffer->cs, va >> 32);
1663
1664 for (uint32_t l = 0; l < level_count; l++) {
1665 radeon_emit(cmd_buffer->cs, pred_val);
1666 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1667 }
1668 }
1669
1670 /**
1671 * Update the fast clear color values if the image is bound as a color buffer.
1672 */
1673 static void
1674 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1675 struct radv_image *image,
1676 int cb_idx,
1677 uint32_t color_values[2])
1678 {
1679 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1680 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1681 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1682 struct radv_attachment_info *att;
1683 uint32_t att_idx;
1684
1685 if (!framebuffer || !subpass)
1686 return;
1687
1688 att_idx = subpass->color_attachments[cb_idx].attachment;
1689 if (att_idx == VK_ATTACHMENT_UNUSED)
1690 return;
1691
1692 att = &framebuffer->attachments[att_idx];
1693 if (att->attachment->image != image)
1694 return;
1695
1696 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1697 radeon_emit(cs, color_values[0]);
1698 radeon_emit(cs, color_values[1]);
1699
1700 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1701 }
1702
1703 /**
1704 * Set the clear color values to the image's metadata.
1705 */
1706 static void
1707 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 uint32_t color_values[2])
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1714 uint32_t level_count = radv_get_levelCount(image, range);
1715 uint32_t count = 2 * level_count;
1716
1717 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1718
1719 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1720 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1721 S_370_WR_CONFIRM(1) |
1722 S_370_ENGINE_SEL(V_370_PFP));
1723 radeon_emit(cs, va);
1724 radeon_emit(cs, va >> 32);
1725
1726 for (uint32_t l = 0; l < level_count; l++) {
1727 radeon_emit(cs, color_values[0]);
1728 radeon_emit(cs, color_values[1]);
1729 }
1730 }
1731
1732 /**
1733 * Update the clear color values for this image.
1734 */
1735 void
1736 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1737 const struct radv_image_view *iview,
1738 int cb_idx,
1739 uint32_t color_values[2])
1740 {
1741 struct radv_image *image = iview->image;
1742 VkImageSubresourceRange range = {
1743 .aspectMask = iview->aspect_mask,
1744 .baseMipLevel = iview->base_mip,
1745 .levelCount = iview->level_count,
1746 .baseArrayLayer = iview->base_layer,
1747 .layerCount = iview->layer_count,
1748 };
1749
1750 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1751
1752 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1753
1754 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1755 color_values);
1756 }
1757
1758 /**
1759 * Load the clear color values from the image's metadata.
1760 */
1761 static void
1762 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1763 struct radv_image_view *iview,
1764 int cb_idx)
1765 {
1766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1767 struct radv_image *image = iview->image;
1768 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1769
1770 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1771 return;
1772
1773 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1774
1775 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1776 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1777 radeon_emit(cs, va);
1778 radeon_emit(cs, va >> 32);
1779 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1780 radeon_emit(cs, 2);
1781 } else {
1782 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1783 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1784 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1785 COPY_DATA_COUNT_SEL);
1786 radeon_emit(cs, va);
1787 radeon_emit(cs, va >> 32);
1788 radeon_emit(cs, reg >> 2);
1789 radeon_emit(cs, 0);
1790
1791 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1792 radeon_emit(cs, 0);
1793 }
1794 }
1795
1796 static void
1797 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1798 {
1799 int i;
1800 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1801 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1802 unsigned num_bpp64_colorbufs = 0;
1803
1804 /* this may happen for inherited secondary recording */
1805 if (!framebuffer)
1806 return;
1807
1808 for (i = 0; i < 8; ++i) {
1809 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1810 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1811 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1812 continue;
1813 }
1814
1815 int idx = subpass->color_attachments[i].attachment;
1816 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1817 struct radv_image_view *iview = att->attachment;
1818 struct radv_image *image = iview->image;
1819 VkImageLayout layout = subpass->color_attachments[i].layout;
1820
1821 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1822
1823 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1824 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1825 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1826
1827 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1828
1829 if (image->planes[0].surface.bpe >= 8)
1830 num_bpp64_colorbufs++;
1831 }
1832
1833 if (subpass->depth_stencil_attachment) {
1834 int idx = subpass->depth_stencil_attachment->attachment;
1835 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1836 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1837 struct radv_image *image = att->attachment->image;
1838 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1839 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1840 cmd_buffer->queue_family_index,
1841 cmd_buffer->queue_family_index);
1842 /* We currently don't support writing decompressed HTILE */
1843 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1844 radv_layout_is_htile_compressed(image, layout, queue_mask));
1845
1846 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1847
1848 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1849 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1850 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1851 }
1852 radv_load_ds_clear_metadata(cmd_buffer, image);
1853 } else {
1854 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1855 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1856 else
1857 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1858
1859 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1860 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1861 }
1862 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1863 S_028208_BR_X(framebuffer->width) |
1864 S_028208_BR_Y(framebuffer->height));
1865
1866 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1867 uint8_t watermark = 4; /* Default value for GFX8. */
1868
1869 /* For optimal DCC performance. */
1870 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1871 if (num_bpp64_colorbufs >= 5) {
1872 watermark = 8;
1873 } else {
1874 watermark = 6;
1875 }
1876 }
1877
1878 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1879 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1880 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1881 }
1882
1883 if (cmd_buffer->device->dfsm_allowed) {
1884 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1885 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1886 }
1887
1888 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1889 }
1890
1891 static void
1892 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1893 {
1894 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1895 struct radv_cmd_state *state = &cmd_buffer->state;
1896
1897 if (state->index_type != state->last_index_type) {
1898 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1899 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1900 2, state->index_type);
1901 } else {
1902 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1903 radeon_emit(cs, state->index_type);
1904 }
1905
1906 state->last_index_type = state->index_type;
1907 }
1908
1909 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1910 radeon_emit(cs, state->index_va);
1911 radeon_emit(cs, state->index_va >> 32);
1912
1913 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1914 radeon_emit(cs, state->max_index_count);
1915
1916 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1917 }
1918
1919 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1920 {
1921 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1922 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1923 uint32_t pa_sc_mode_cntl_1 =
1924 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1925 uint32_t db_count_control;
1926
1927 if(!cmd_buffer->state.active_occlusion_queries) {
1928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1929 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1930 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1931 has_perfect_queries) {
1932 /* Re-enable out-of-order rasterization if the
1933 * bound pipeline supports it and if it's has
1934 * been disabled before starting any perfect
1935 * occlusion queries.
1936 */
1937 radeon_set_context_reg(cmd_buffer->cs,
1938 R_028A4C_PA_SC_MODE_CNTL_1,
1939 pa_sc_mode_cntl_1);
1940 }
1941 }
1942 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1943 } else {
1944 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1945 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1946
1947 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1948 db_count_control =
1949 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1950 S_028004_SAMPLE_RATE(sample_rate) |
1951 S_028004_ZPASS_ENABLE(1) |
1952 S_028004_SLICE_EVEN_ENABLE(1) |
1953 S_028004_SLICE_ODD_ENABLE(1);
1954
1955 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1956 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1957 has_perfect_queries) {
1958 /* If the bound pipeline has enabled
1959 * out-of-order rasterization, we should
1960 * disable it before starting any perfect
1961 * occlusion queries.
1962 */
1963 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1964
1965 radeon_set_context_reg(cmd_buffer->cs,
1966 R_028A4C_PA_SC_MODE_CNTL_1,
1967 pa_sc_mode_cntl_1);
1968 }
1969 } else {
1970 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1971 S_028004_SAMPLE_RATE(sample_rate);
1972 }
1973 }
1974
1975 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1976
1977 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1978 }
1979
1980 static void
1981 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1982 {
1983 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1984
1985 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1986 radv_emit_viewport(cmd_buffer);
1987
1988 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1989 !cmd_buffer->device->physical_device->has_scissor_bug)
1990 radv_emit_scissor(cmd_buffer);
1991
1992 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1993 radv_emit_line_width(cmd_buffer);
1994
1995 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1996 radv_emit_blend_constants(cmd_buffer);
1997
1998 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1999 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2000 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2001 radv_emit_stencil(cmd_buffer);
2002
2003 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2004 radv_emit_depth_bounds(cmd_buffer);
2005
2006 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2007 radv_emit_depth_bias(cmd_buffer);
2008
2009 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2010 radv_emit_discard_rectangle(cmd_buffer);
2011
2012 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2013 radv_emit_sample_locations(cmd_buffer);
2014
2015 cmd_buffer->state.dirty &= ~states;
2016 }
2017
2018 static void
2019 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2020 VkPipelineBindPoint bind_point)
2021 {
2022 struct radv_descriptor_state *descriptors_state =
2023 radv_get_descriptors_state(cmd_buffer, bind_point);
2024 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2025 unsigned bo_offset;
2026
2027 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2028 set->mapped_ptr,
2029 &bo_offset))
2030 return;
2031
2032 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2033 set->va += bo_offset;
2034 }
2035
2036 static void
2037 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2038 VkPipelineBindPoint bind_point)
2039 {
2040 struct radv_descriptor_state *descriptors_state =
2041 radv_get_descriptors_state(cmd_buffer, bind_point);
2042 uint32_t size = MAX_SETS * 4;
2043 uint32_t offset;
2044 void *ptr;
2045
2046 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2047 256, &offset, &ptr))
2048 return;
2049
2050 for (unsigned i = 0; i < MAX_SETS; i++) {
2051 uint32_t *uptr = ((uint32_t *)ptr) + i;
2052 uint64_t set_va = 0;
2053 struct radv_descriptor_set *set = descriptors_state->sets[i];
2054 if (descriptors_state->valid & (1u << i))
2055 set_va = set->va;
2056 uptr[0] = set_va & 0xffffffff;
2057 }
2058
2059 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2060 va += offset;
2061
2062 if (cmd_buffer->state.pipeline) {
2063 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2064 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2065 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2066
2067 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2068 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2069 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2070
2071 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2072 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2073 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2074
2075 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2076 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2077 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2078
2079 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2080 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2081 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2082 }
2083
2084 if (cmd_buffer->state.compute_pipeline)
2085 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2086 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2087 }
2088
2089 static void
2090 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2091 VkShaderStageFlags stages)
2092 {
2093 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2094 VK_PIPELINE_BIND_POINT_COMPUTE :
2095 VK_PIPELINE_BIND_POINT_GRAPHICS;
2096 struct radv_descriptor_state *descriptors_state =
2097 radv_get_descriptors_state(cmd_buffer, bind_point);
2098 struct radv_cmd_state *state = &cmd_buffer->state;
2099 bool flush_indirect_descriptors;
2100
2101 if (!descriptors_state->dirty)
2102 return;
2103
2104 if (descriptors_state->push_dirty)
2105 radv_flush_push_descriptors(cmd_buffer, bind_point);
2106
2107 flush_indirect_descriptors =
2108 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2109 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2110 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2111 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2112
2113 if (flush_indirect_descriptors)
2114 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2115
2116 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2117 cmd_buffer->cs,
2118 MAX_SETS * MESA_SHADER_STAGES * 4);
2119
2120 if (cmd_buffer->state.pipeline) {
2121 radv_foreach_stage(stage, stages) {
2122 if (!cmd_buffer->state.pipeline->shaders[stage])
2123 continue;
2124
2125 radv_emit_descriptor_pointers(cmd_buffer,
2126 cmd_buffer->state.pipeline,
2127 descriptors_state, stage);
2128 }
2129 }
2130
2131 if (cmd_buffer->state.compute_pipeline &&
2132 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2133 radv_emit_descriptor_pointers(cmd_buffer,
2134 cmd_buffer->state.compute_pipeline,
2135 descriptors_state,
2136 MESA_SHADER_COMPUTE);
2137 }
2138
2139 descriptors_state->dirty = 0;
2140 descriptors_state->push_dirty = false;
2141
2142 assert(cmd_buffer->cs->cdw <= cdw_max);
2143
2144 if (unlikely(cmd_buffer->device->trace_bo))
2145 radv_save_descriptors(cmd_buffer, bind_point);
2146 }
2147
2148 static void
2149 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2150 VkShaderStageFlags stages)
2151 {
2152 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2153 ? cmd_buffer->state.compute_pipeline
2154 : cmd_buffer->state.pipeline;
2155 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2156 VK_PIPELINE_BIND_POINT_COMPUTE :
2157 VK_PIPELINE_BIND_POINT_GRAPHICS;
2158 struct radv_descriptor_state *descriptors_state =
2159 radv_get_descriptors_state(cmd_buffer, bind_point);
2160 struct radv_pipeline_layout *layout = pipeline->layout;
2161 struct radv_shader_variant *shader, *prev_shader;
2162 bool need_push_constants = false;
2163 unsigned offset;
2164 void *ptr;
2165 uint64_t va;
2166
2167 stages &= cmd_buffer->push_constant_stages;
2168 if (!stages ||
2169 (!layout->push_constant_size && !layout->dynamic_offset_count))
2170 return;
2171
2172 radv_foreach_stage(stage, stages) {
2173 if (!pipeline->shaders[stage])
2174 continue;
2175
2176 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2177 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2178
2179 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2180 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2181
2182 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2183 AC_UD_INLINE_PUSH_CONSTANTS,
2184 count,
2185 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2186 }
2187
2188 if (need_push_constants) {
2189 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2190 16 * layout->dynamic_offset_count,
2191 256, &offset, &ptr))
2192 return;
2193
2194 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2195 memcpy((char*)ptr + layout->push_constant_size,
2196 descriptors_state->dynamic_buffers,
2197 16 * layout->dynamic_offset_count);
2198
2199 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2200 va += offset;
2201
2202 MAYBE_UNUSED unsigned cdw_max =
2203 radeon_check_space(cmd_buffer->device->ws,
2204 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2205
2206 prev_shader = NULL;
2207 radv_foreach_stage(stage, stages) {
2208 shader = radv_get_shader(pipeline, stage);
2209
2210 /* Avoid redundantly emitting the address for merged stages. */
2211 if (shader && shader != prev_shader) {
2212 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2213 AC_UD_PUSH_CONSTANTS, va);
2214
2215 prev_shader = shader;
2216 }
2217 }
2218 assert(cmd_buffer->cs->cdw <= cdw_max);
2219 }
2220
2221 cmd_buffer->push_constant_stages &= ~stages;
2222 }
2223
2224 static void
2225 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2226 bool pipeline_is_dirty)
2227 {
2228 if ((pipeline_is_dirty ||
2229 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2230 cmd_buffer->state.pipeline->num_vertex_bindings &&
2231 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2232 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2233 unsigned vb_offset;
2234 void *vb_ptr;
2235 uint32_t i = 0;
2236 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2237 uint64_t va;
2238
2239 /* allocate some descriptor state for vertex buffers */
2240 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2241 &vb_offset, &vb_ptr))
2242 return;
2243
2244 for (i = 0; i < count; i++) {
2245 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2246 uint32_t offset;
2247 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2248 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2249
2250 if (!buffer)
2251 continue;
2252
2253 va = radv_buffer_get_va(buffer->bo);
2254
2255 offset = cmd_buffer->vertex_bindings[i].offset;
2256 va += offset + buffer->offset;
2257 desc[0] = va;
2258 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2259 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2260 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2261 else
2262 desc[2] = buffer->size - offset;
2263 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2264 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2265 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2266 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2267 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2268 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2269 }
2270
2271 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2272 va += vb_offset;
2273
2274 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2275 AC_UD_VS_VERTEX_BUFFERS, va);
2276
2277 cmd_buffer->state.vb_va = va;
2278 cmd_buffer->state.vb_size = count * 16;
2279 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2280 }
2281 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2282 }
2283
2284 static void
2285 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2286 {
2287 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2288 struct radv_userdata_info *loc;
2289 uint32_t base_reg;
2290
2291 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2292 if (!radv_get_shader(pipeline, stage))
2293 continue;
2294
2295 loc = radv_lookup_user_sgpr(pipeline, stage,
2296 AC_UD_STREAMOUT_BUFFERS);
2297 if (loc->sgpr_idx == -1)
2298 continue;
2299
2300 base_reg = pipeline->user_data_0[stage];
2301
2302 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2303 base_reg + loc->sgpr_idx * 4, va, false);
2304 }
2305
2306 if (pipeline->gs_copy_shader) {
2307 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2308 if (loc->sgpr_idx != -1) {
2309 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2310
2311 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2312 base_reg + loc->sgpr_idx * 4, va, false);
2313 }
2314 }
2315 }
2316
2317 static void
2318 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2319 {
2320 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2321 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2322 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2323 unsigned so_offset;
2324 void *so_ptr;
2325 uint64_t va;
2326
2327 /* Allocate some descriptor state for streamout buffers. */
2328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2329 MAX_SO_BUFFERS * 16, 256,
2330 &so_offset, &so_ptr))
2331 return;
2332
2333 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2334 struct radv_buffer *buffer = sb[i].buffer;
2335 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2336
2337 if (!(so->enabled_mask & (1 << i)))
2338 continue;
2339
2340 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2341
2342 va += sb[i].offset;
2343
2344 /* Set the descriptor.
2345 *
2346 * On GFX8, the format must be non-INVALID, otherwise
2347 * the buffer will be considered not bound and store
2348 * instructions will be no-ops.
2349 */
2350 desc[0] = va;
2351 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2352 desc[2] = 0xffffffff;
2353 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2354 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2355 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2356 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2357 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2358 }
2359
2360 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2361 va += so_offset;
2362
2363 radv_emit_streamout_buffers(cmd_buffer, va);
2364 }
2365
2366 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2367 }
2368
2369 static void
2370 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2371 {
2372 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2373 radv_flush_streamout_descriptors(cmd_buffer);
2374 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2375 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2376 }
2377
2378 struct radv_draw_info {
2379 /**
2380 * Number of vertices.
2381 */
2382 uint32_t count;
2383
2384 /**
2385 * Index of the first vertex.
2386 */
2387 int32_t vertex_offset;
2388
2389 /**
2390 * First instance id.
2391 */
2392 uint32_t first_instance;
2393
2394 /**
2395 * Number of instances.
2396 */
2397 uint32_t instance_count;
2398
2399 /**
2400 * First index (indexed draws only).
2401 */
2402 uint32_t first_index;
2403
2404 /**
2405 * Whether it's an indexed draw.
2406 */
2407 bool indexed;
2408
2409 /**
2410 * Indirect draw parameters resource.
2411 */
2412 struct radv_buffer *indirect;
2413 uint64_t indirect_offset;
2414 uint32_t stride;
2415
2416 /**
2417 * Draw count parameters resource.
2418 */
2419 struct radv_buffer *count_buffer;
2420 uint64_t count_buffer_offset;
2421
2422 /**
2423 * Stream output parameters resource.
2424 */
2425 struct radv_buffer *strmout_buffer;
2426 uint64_t strmout_buffer_offset;
2427 };
2428
2429 static void
2430 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2431 const struct radv_draw_info *draw_info)
2432 {
2433 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2434 struct radv_cmd_state *state = &cmd_buffer->state;
2435 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2436 uint32_t ia_multi_vgt_param;
2437 int32_t primitive_reset_en;
2438
2439 /* Draw state. */
2440 ia_multi_vgt_param =
2441 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2442 draw_info->indirect,
2443 !!draw_info->strmout_buffer,
2444 draw_info->indirect ? 0 : draw_info->count);
2445
2446 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2447 if (info->chip_class >= GFX9) {
2448 radeon_set_uconfig_reg_idx(cs,
2449 R_030960_IA_MULTI_VGT_PARAM,
2450 4, ia_multi_vgt_param);
2451 } else if (info->chip_class >= GFX7) {
2452 radeon_set_context_reg_idx(cs,
2453 R_028AA8_IA_MULTI_VGT_PARAM,
2454 1, ia_multi_vgt_param);
2455 } else {
2456 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2457 ia_multi_vgt_param);
2458 }
2459 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2460 }
2461
2462 /* Primitive restart. */
2463 primitive_reset_en =
2464 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2465
2466 if (primitive_reset_en != state->last_primitive_reset_en) {
2467 state->last_primitive_reset_en = primitive_reset_en;
2468 if (info->chip_class >= GFX9) {
2469 radeon_set_uconfig_reg(cs,
2470 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2471 primitive_reset_en);
2472 } else {
2473 radeon_set_context_reg(cs,
2474 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2475 primitive_reset_en);
2476 }
2477 }
2478
2479 if (primitive_reset_en) {
2480 uint32_t primitive_reset_index =
2481 state->index_type ? 0xffffffffu : 0xffffu;
2482
2483 if (primitive_reset_index != state->last_primitive_reset_index) {
2484 radeon_set_context_reg(cs,
2485 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2486 primitive_reset_index);
2487 state->last_primitive_reset_index = primitive_reset_index;
2488 }
2489 }
2490
2491 if (draw_info->strmout_buffer) {
2492 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2493
2494 va += draw_info->strmout_buffer->offset +
2495 draw_info->strmout_buffer_offset;
2496
2497 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2498 draw_info->stride);
2499
2500 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2501 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2502 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2503 COPY_DATA_WR_CONFIRM);
2504 radeon_emit(cs, va);
2505 radeon_emit(cs, va >> 32);
2506 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2507 radeon_emit(cs, 0); /* unused */
2508
2509 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2510 }
2511 }
2512
2513 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2514 VkPipelineStageFlags src_stage_mask)
2515 {
2516 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2517 VK_PIPELINE_STAGE_TRANSFER_BIT |
2518 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2519 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2520 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2521 }
2522
2523 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2524 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2525 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2526 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2527 VK_PIPELINE_STAGE_TRANSFER_BIT |
2528 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2529 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2530 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2531 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2532 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2533 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2534 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2535 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2536 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2537 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2538 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2539 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2540 }
2541 }
2542
2543 static enum radv_cmd_flush_bits
2544 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2545 VkAccessFlags src_flags,
2546 struct radv_image *image)
2547 {
2548 bool flush_CB_meta = true, flush_DB_meta = true;
2549 enum radv_cmd_flush_bits flush_bits = 0;
2550 uint32_t b;
2551
2552 if (image) {
2553 if (!radv_image_has_CB_metadata(image))
2554 flush_CB_meta = false;
2555 if (!radv_image_has_htile(image))
2556 flush_DB_meta = false;
2557 }
2558
2559 for_each_bit(b, src_flags) {
2560 switch ((VkAccessFlagBits)(1 << b)) {
2561 case VK_ACCESS_SHADER_WRITE_BIT:
2562 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2563 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2564 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2565 break;
2566 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2567 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2568 if (flush_CB_meta)
2569 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2570 break;
2571 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2572 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2573 if (flush_DB_meta)
2574 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2575 break;
2576 case VK_ACCESS_TRANSFER_WRITE_BIT:
2577 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2578 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2579 RADV_CMD_FLAG_INV_GLOBAL_L2;
2580
2581 if (flush_CB_meta)
2582 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2583 if (flush_DB_meta)
2584 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2585 break;
2586 default:
2587 break;
2588 }
2589 }
2590 return flush_bits;
2591 }
2592
2593 static enum radv_cmd_flush_bits
2594 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2595 VkAccessFlags dst_flags,
2596 struct radv_image *image)
2597 {
2598 bool flush_CB_meta = true, flush_DB_meta = true;
2599 enum radv_cmd_flush_bits flush_bits = 0;
2600 bool flush_CB = true, flush_DB = true;
2601 bool image_is_coherent = false;
2602 uint32_t b;
2603
2604 if (image) {
2605 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2606 flush_CB = false;
2607 flush_DB = false;
2608 }
2609
2610 if (!radv_image_has_CB_metadata(image))
2611 flush_CB_meta = false;
2612 if (!radv_image_has_htile(image))
2613 flush_DB_meta = false;
2614
2615 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2616 if (image->info.samples == 1 &&
2617 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2618 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2619 !vk_format_is_stencil(image->vk_format)) {
2620 /* Single-sample color and single-sample depth
2621 * (not stencil) are coherent with shaders on
2622 * GFX9.
2623 */
2624 image_is_coherent = true;
2625 }
2626 }
2627 }
2628
2629 for_each_bit(b, dst_flags) {
2630 switch ((VkAccessFlagBits)(1 << b)) {
2631 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2632 case VK_ACCESS_INDEX_READ_BIT:
2633 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2634 break;
2635 case VK_ACCESS_UNIFORM_READ_BIT:
2636 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2637 break;
2638 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2639 case VK_ACCESS_TRANSFER_READ_BIT:
2640 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2641 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2642 RADV_CMD_FLAG_INV_GLOBAL_L2;
2643 break;
2644 case VK_ACCESS_SHADER_READ_BIT:
2645 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2646
2647 if (!image_is_coherent)
2648 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2649 break;
2650 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2651 if (flush_CB)
2652 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2653 if (flush_CB_meta)
2654 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2655 break;
2656 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2657 if (flush_DB)
2658 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2659 if (flush_DB_meta)
2660 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2661 break;
2662 default:
2663 break;
2664 }
2665 }
2666 return flush_bits;
2667 }
2668
2669 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2670 const struct radv_subpass_barrier *barrier)
2671 {
2672 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2673 NULL);
2674 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2675 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2676 NULL);
2677 }
2678
2679 static uint32_t
2680 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2681 {
2682 struct radv_cmd_state *state = &cmd_buffer->state;
2683 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2684
2685 /* The id of this subpass shouldn't exceed the number of subpasses in
2686 * this render pass minus 1.
2687 */
2688 assert(subpass_id < state->pass->subpass_count);
2689 return subpass_id;
2690 }
2691
2692 static struct radv_sample_locations_state *
2693 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2694 uint32_t att_idx,
2695 bool begin_subpass)
2696 {
2697 struct radv_cmd_state *state = &cmd_buffer->state;
2698 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2699 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2700
2701 if (view->image->info.samples == 1)
2702 return NULL;
2703
2704 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2705 /* Return the initial sample locations if this is the initial
2706 * layout transition of the given subpass attachemnt.
2707 */
2708 if (state->attachments[att_idx].sample_location.count > 0)
2709 return &state->attachments[att_idx].sample_location;
2710 } else {
2711 /* Otherwise return the subpass sample locations if defined. */
2712 if (state->subpass_sample_locs) {
2713 /* Because the driver sets the current subpass before
2714 * initial layout transitions, we should use the sample
2715 * locations from the previous subpass to avoid an
2716 * off-by-one problem. Otherwise, use the sample
2717 * locations for the current subpass for final layout
2718 * transitions.
2719 */
2720 if (begin_subpass)
2721 subpass_id--;
2722
2723 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2724 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2725 return &state->subpass_sample_locs[i].sample_location;
2726 }
2727 }
2728 }
2729
2730 return NULL;
2731 }
2732
2733 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2734 struct radv_subpass_attachment att,
2735 bool begin_subpass)
2736 {
2737 unsigned idx = att.attachment;
2738 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2739 struct radv_sample_locations_state *sample_locs;
2740 VkImageSubresourceRange range;
2741 range.aspectMask = 0;
2742 range.baseMipLevel = view->base_mip;
2743 range.levelCount = 1;
2744 range.baseArrayLayer = view->base_layer;
2745 range.layerCount = cmd_buffer->state.framebuffer->layers;
2746
2747 if (cmd_buffer->state.subpass->view_mask) {
2748 /* If the current subpass uses multiview, the driver might have
2749 * performed a fast color/depth clear to the whole image
2750 * (including all layers). To make sure the driver will
2751 * decompress the image correctly (if needed), we have to
2752 * account for the "real" number of layers. If the view mask is
2753 * sparse, this will decompress more layers than needed.
2754 */
2755 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2756 }
2757
2758 /* Get the subpass sample locations for the given attachment, if NULL
2759 * is returned the driver will use the default HW locations.
2760 */
2761 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2762 begin_subpass);
2763
2764 radv_handle_image_transition(cmd_buffer,
2765 view->image,
2766 cmd_buffer->state.attachments[idx].current_layout,
2767 att.layout, 0, 0, &range, sample_locs);
2768
2769 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2770
2771
2772 }
2773
2774 void
2775 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2776 const struct radv_subpass *subpass)
2777 {
2778 cmd_buffer->state.subpass = subpass;
2779
2780 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2781 }
2782
2783 static VkResult
2784 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2785 struct radv_render_pass *pass,
2786 const VkRenderPassBeginInfo *info)
2787 {
2788 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2789 vk_find_struct_const(info->pNext,
2790 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2791 struct radv_cmd_state *state = &cmd_buffer->state;
2792 struct radv_framebuffer *framebuffer = state->framebuffer;
2793
2794 if (!sample_locs) {
2795 state->subpass_sample_locs = NULL;
2796 return VK_SUCCESS;
2797 }
2798
2799 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2800 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2801 &sample_locs->pAttachmentInitialSampleLocations[i];
2802 uint32_t att_idx = att_sample_locs->attachmentIndex;
2803 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2804 struct radv_image *image = att->attachment->image;
2805
2806 assert(vk_format_is_depth_or_stencil(image->vk_format));
2807
2808 /* From the Vulkan spec 1.1.108:
2809 *
2810 * "If the image referenced by the framebuffer attachment at
2811 * index attachmentIndex was not created with
2812 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2813 * then the values specified in sampleLocationsInfo are
2814 * ignored."
2815 */
2816 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2817 continue;
2818
2819 const VkSampleLocationsInfoEXT *sample_locs_info =
2820 &att_sample_locs->sampleLocationsInfo;
2821
2822 state->attachments[att_idx].sample_location.per_pixel =
2823 sample_locs_info->sampleLocationsPerPixel;
2824 state->attachments[att_idx].sample_location.grid_size =
2825 sample_locs_info->sampleLocationGridSize;
2826 state->attachments[att_idx].sample_location.count =
2827 sample_locs_info->sampleLocationsCount;
2828 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2829 sample_locs_info->pSampleLocations,
2830 sample_locs_info->sampleLocationsCount);
2831 }
2832
2833 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2834 sample_locs->postSubpassSampleLocationsCount *
2835 sizeof(state->subpass_sample_locs[0]),
2836 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2837 if (state->subpass_sample_locs == NULL) {
2838 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2839 return cmd_buffer->record_result;
2840 }
2841
2842 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2843
2844 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2845 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2846 &sample_locs->pPostSubpassSampleLocations[i];
2847 const VkSampleLocationsInfoEXT *sample_locs_info =
2848 &subpass_sample_locs_info->sampleLocationsInfo;
2849
2850 state->subpass_sample_locs[i].subpass_idx =
2851 subpass_sample_locs_info->subpassIndex;
2852 state->subpass_sample_locs[i].sample_location.per_pixel =
2853 sample_locs_info->sampleLocationsPerPixel;
2854 state->subpass_sample_locs[i].sample_location.grid_size =
2855 sample_locs_info->sampleLocationGridSize;
2856 state->subpass_sample_locs[i].sample_location.count =
2857 sample_locs_info->sampleLocationsCount;
2858 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2859 sample_locs_info->pSampleLocations,
2860 sample_locs_info->sampleLocationsCount);
2861 }
2862
2863 return VK_SUCCESS;
2864 }
2865
2866 static VkResult
2867 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2868 struct radv_render_pass *pass,
2869 const VkRenderPassBeginInfo *info)
2870 {
2871 struct radv_cmd_state *state = &cmd_buffer->state;
2872
2873 if (pass->attachment_count == 0) {
2874 state->attachments = NULL;
2875 return VK_SUCCESS;
2876 }
2877
2878 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2879 pass->attachment_count *
2880 sizeof(state->attachments[0]),
2881 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2882 if (state->attachments == NULL) {
2883 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2884 return cmd_buffer->record_result;
2885 }
2886
2887 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2888 struct radv_render_pass_attachment *att = &pass->attachments[i];
2889 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2890 VkImageAspectFlags clear_aspects = 0;
2891
2892 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2893 /* color attachment */
2894 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2895 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2896 }
2897 } else {
2898 /* depthstencil attachment */
2899 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2900 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2901 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2902 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2903 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2904 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2905 }
2906 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2907 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2908 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2909 }
2910 }
2911
2912 state->attachments[i].pending_clear_aspects = clear_aspects;
2913 state->attachments[i].cleared_views = 0;
2914 if (clear_aspects && info) {
2915 assert(info->clearValueCount > i);
2916 state->attachments[i].clear_value = info->pClearValues[i];
2917 }
2918
2919 state->attachments[i].current_layout = att->initial_layout;
2920 state->attachments[i].sample_location.count = 0;
2921 }
2922
2923 return VK_SUCCESS;
2924 }
2925
2926 VkResult radv_AllocateCommandBuffers(
2927 VkDevice _device,
2928 const VkCommandBufferAllocateInfo *pAllocateInfo,
2929 VkCommandBuffer *pCommandBuffers)
2930 {
2931 RADV_FROM_HANDLE(radv_device, device, _device);
2932 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2933
2934 VkResult result = VK_SUCCESS;
2935 uint32_t i;
2936
2937 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2938
2939 if (!list_empty(&pool->free_cmd_buffers)) {
2940 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2941
2942 list_del(&cmd_buffer->pool_link);
2943 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2944
2945 result = radv_reset_cmd_buffer(cmd_buffer);
2946 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2947 cmd_buffer->level = pAllocateInfo->level;
2948
2949 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2950 } else {
2951 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2952 &pCommandBuffers[i]);
2953 }
2954 if (result != VK_SUCCESS)
2955 break;
2956 }
2957
2958 if (result != VK_SUCCESS) {
2959 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2960 i, pCommandBuffers);
2961
2962 /* From the Vulkan 1.0.66 spec:
2963 *
2964 * "vkAllocateCommandBuffers can be used to create multiple
2965 * command buffers. If the creation of any of those command
2966 * buffers fails, the implementation must destroy all
2967 * successfully created command buffer objects from this
2968 * command, set all entries of the pCommandBuffers array to
2969 * NULL and return the error."
2970 */
2971 memset(pCommandBuffers, 0,
2972 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2973 }
2974
2975 return result;
2976 }
2977
2978 void radv_FreeCommandBuffers(
2979 VkDevice device,
2980 VkCommandPool commandPool,
2981 uint32_t commandBufferCount,
2982 const VkCommandBuffer *pCommandBuffers)
2983 {
2984 for (uint32_t i = 0; i < commandBufferCount; i++) {
2985 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2986
2987 if (cmd_buffer) {
2988 if (cmd_buffer->pool) {
2989 list_del(&cmd_buffer->pool_link);
2990 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2991 } else
2992 radv_cmd_buffer_destroy(cmd_buffer);
2993
2994 }
2995 }
2996 }
2997
2998 VkResult radv_ResetCommandBuffer(
2999 VkCommandBuffer commandBuffer,
3000 VkCommandBufferResetFlags flags)
3001 {
3002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3003 return radv_reset_cmd_buffer(cmd_buffer);
3004 }
3005
3006 VkResult radv_BeginCommandBuffer(
3007 VkCommandBuffer commandBuffer,
3008 const VkCommandBufferBeginInfo *pBeginInfo)
3009 {
3010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3011 VkResult result = VK_SUCCESS;
3012
3013 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3014 /* If the command buffer has already been resetted with
3015 * vkResetCommandBuffer, no need to do it again.
3016 */
3017 result = radv_reset_cmd_buffer(cmd_buffer);
3018 if (result != VK_SUCCESS)
3019 return result;
3020 }
3021
3022 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3023 cmd_buffer->state.last_primitive_reset_en = -1;
3024 cmd_buffer->state.last_index_type = -1;
3025 cmd_buffer->state.last_num_instances = -1;
3026 cmd_buffer->state.last_vertex_offset = -1;
3027 cmd_buffer->state.last_first_instance = -1;
3028 cmd_buffer->state.predication_type = -1;
3029 cmd_buffer->usage_flags = pBeginInfo->flags;
3030
3031 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3032 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3033 assert(pBeginInfo->pInheritanceInfo);
3034 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3035 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3036
3037 struct radv_subpass *subpass =
3038 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3039
3040 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3041 if (result != VK_SUCCESS)
3042 return result;
3043
3044 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3045 }
3046
3047 if (unlikely(cmd_buffer->device->trace_bo)) {
3048 struct radv_device *device = cmd_buffer->device;
3049
3050 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3051 device->trace_bo);
3052
3053 radv_cmd_buffer_trace_emit(cmd_buffer);
3054 }
3055
3056 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3057
3058 return result;
3059 }
3060
3061 void radv_CmdBindVertexBuffers(
3062 VkCommandBuffer commandBuffer,
3063 uint32_t firstBinding,
3064 uint32_t bindingCount,
3065 const VkBuffer* pBuffers,
3066 const VkDeviceSize* pOffsets)
3067 {
3068 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3069 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3070 bool changed = false;
3071
3072 /* We have to defer setting up vertex buffer since we need the buffer
3073 * stride from the pipeline. */
3074
3075 assert(firstBinding + bindingCount <= MAX_VBS);
3076 for (uint32_t i = 0; i < bindingCount; i++) {
3077 uint32_t idx = firstBinding + i;
3078
3079 if (!changed &&
3080 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3081 vb[idx].offset != pOffsets[i])) {
3082 changed = true;
3083 }
3084
3085 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3086 vb[idx].offset = pOffsets[i];
3087
3088 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3089 vb[idx].buffer->bo);
3090 }
3091
3092 if (!changed) {
3093 /* No state changes. */
3094 return;
3095 }
3096
3097 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3098 }
3099
3100 void radv_CmdBindIndexBuffer(
3101 VkCommandBuffer commandBuffer,
3102 VkBuffer buffer,
3103 VkDeviceSize offset,
3104 VkIndexType indexType)
3105 {
3106 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3107 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3108
3109 if (cmd_buffer->state.index_buffer == index_buffer &&
3110 cmd_buffer->state.index_offset == offset &&
3111 cmd_buffer->state.index_type == indexType) {
3112 /* No state changes. */
3113 return;
3114 }
3115
3116 cmd_buffer->state.index_buffer = index_buffer;
3117 cmd_buffer->state.index_offset = offset;
3118 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3119 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3120 cmd_buffer->state.index_va += index_buffer->offset + offset;
3121
3122 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3123 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3124 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3125 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3126 }
3127
3128
3129 static void
3130 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3131 VkPipelineBindPoint bind_point,
3132 struct radv_descriptor_set *set, unsigned idx)
3133 {
3134 struct radeon_winsys *ws = cmd_buffer->device->ws;
3135
3136 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3137
3138 assert(set);
3139 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3140
3141 if (!cmd_buffer->device->use_global_bo_list) {
3142 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3143 if (set->descriptors[j])
3144 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3145 }
3146
3147 if(set->bo)
3148 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3149 }
3150
3151 void radv_CmdBindDescriptorSets(
3152 VkCommandBuffer commandBuffer,
3153 VkPipelineBindPoint pipelineBindPoint,
3154 VkPipelineLayout _layout,
3155 uint32_t firstSet,
3156 uint32_t descriptorSetCount,
3157 const VkDescriptorSet* pDescriptorSets,
3158 uint32_t dynamicOffsetCount,
3159 const uint32_t* pDynamicOffsets)
3160 {
3161 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3162 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3163 unsigned dyn_idx = 0;
3164
3165 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3166 struct radv_descriptor_state *descriptors_state =
3167 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3168
3169 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3170 unsigned idx = i + firstSet;
3171 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3172 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3173
3174 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3175 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3176 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3177 assert(dyn_idx < dynamicOffsetCount);
3178
3179 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3180 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3181 dst[0] = va;
3182 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3183 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3184 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3185 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3186 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3187 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3188 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3189 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3190 cmd_buffer->push_constant_stages |=
3191 set->layout->dynamic_shader_stages;
3192 }
3193 }
3194 }
3195
3196 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3197 struct radv_descriptor_set *set,
3198 struct radv_descriptor_set_layout *layout,
3199 VkPipelineBindPoint bind_point)
3200 {
3201 struct radv_descriptor_state *descriptors_state =
3202 radv_get_descriptors_state(cmd_buffer, bind_point);
3203 set->size = layout->size;
3204 set->layout = layout;
3205
3206 if (descriptors_state->push_set.capacity < set->size) {
3207 size_t new_size = MAX2(set->size, 1024);
3208 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3209 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3210
3211 free(set->mapped_ptr);
3212 set->mapped_ptr = malloc(new_size);
3213
3214 if (!set->mapped_ptr) {
3215 descriptors_state->push_set.capacity = 0;
3216 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3217 return false;
3218 }
3219
3220 descriptors_state->push_set.capacity = new_size;
3221 }
3222
3223 return true;
3224 }
3225
3226 void radv_meta_push_descriptor_set(
3227 struct radv_cmd_buffer* cmd_buffer,
3228 VkPipelineBindPoint pipelineBindPoint,
3229 VkPipelineLayout _layout,
3230 uint32_t set,
3231 uint32_t descriptorWriteCount,
3232 const VkWriteDescriptorSet* pDescriptorWrites)
3233 {
3234 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3235 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3236 unsigned bo_offset;
3237
3238 assert(set == 0);
3239 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3240
3241 push_set->size = layout->set[set].layout->size;
3242 push_set->layout = layout->set[set].layout;
3243
3244 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3245 &bo_offset,
3246 (void**) &push_set->mapped_ptr))
3247 return;
3248
3249 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3250 push_set->va += bo_offset;
3251
3252 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3253 radv_descriptor_set_to_handle(push_set),
3254 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3255
3256 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3257 }
3258
3259 void radv_CmdPushDescriptorSetKHR(
3260 VkCommandBuffer commandBuffer,
3261 VkPipelineBindPoint pipelineBindPoint,
3262 VkPipelineLayout _layout,
3263 uint32_t set,
3264 uint32_t descriptorWriteCount,
3265 const VkWriteDescriptorSet* pDescriptorWrites)
3266 {
3267 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3268 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3269 struct radv_descriptor_state *descriptors_state =
3270 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3271 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3272
3273 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3274
3275 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3276 layout->set[set].layout,
3277 pipelineBindPoint))
3278 return;
3279
3280 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3281 * because it is invalid, according to Vulkan spec.
3282 */
3283 for (int i = 0; i < descriptorWriteCount; i++) {
3284 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3285 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3286 }
3287
3288 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3289 radv_descriptor_set_to_handle(push_set),
3290 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3291
3292 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3293 descriptors_state->push_dirty = true;
3294 }
3295
3296 void radv_CmdPushDescriptorSetWithTemplateKHR(
3297 VkCommandBuffer commandBuffer,
3298 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3299 VkPipelineLayout _layout,
3300 uint32_t set,
3301 const void* pData)
3302 {
3303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3304 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3305 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3306 struct radv_descriptor_state *descriptors_state =
3307 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3308 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3309
3310 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3311
3312 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3313 layout->set[set].layout,
3314 templ->bind_point))
3315 return;
3316
3317 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3318 descriptorUpdateTemplate, pData);
3319
3320 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3321 descriptors_state->push_dirty = true;
3322 }
3323
3324 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3325 VkPipelineLayout layout,
3326 VkShaderStageFlags stageFlags,
3327 uint32_t offset,
3328 uint32_t size,
3329 const void* pValues)
3330 {
3331 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3332 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3333 cmd_buffer->push_constant_stages |= stageFlags;
3334 }
3335
3336 VkResult radv_EndCommandBuffer(
3337 VkCommandBuffer commandBuffer)
3338 {
3339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3340
3341 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3342 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3343 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3344
3345 /* Make sure to sync all pending active queries at the end of
3346 * command buffer.
3347 */
3348 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3349
3350 si_emit_cache_flush(cmd_buffer);
3351 }
3352
3353 /* Make sure CP DMA is idle at the end of IBs because the kernel
3354 * doesn't wait for it.
3355 */
3356 si_cp_dma_wait_for_idle(cmd_buffer);
3357
3358 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3359 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3360
3361 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3362 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3363
3364 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3365
3366 return cmd_buffer->record_result;
3367 }
3368
3369 static void
3370 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3371 {
3372 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3373
3374 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3375 return;
3376
3377 assert(!pipeline->ctx_cs.cdw);
3378
3379 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3380
3381 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3382 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3383
3384 cmd_buffer->compute_scratch_size_needed =
3385 MAX2(cmd_buffer->compute_scratch_size_needed,
3386 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3387
3388 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3389 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3390
3391 if (unlikely(cmd_buffer->device->trace_bo))
3392 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3393 }
3394
3395 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3396 VkPipelineBindPoint bind_point)
3397 {
3398 struct radv_descriptor_state *descriptors_state =
3399 radv_get_descriptors_state(cmd_buffer, bind_point);
3400
3401 descriptors_state->dirty |= descriptors_state->valid;
3402 }
3403
3404 void radv_CmdBindPipeline(
3405 VkCommandBuffer commandBuffer,
3406 VkPipelineBindPoint pipelineBindPoint,
3407 VkPipeline _pipeline)
3408 {
3409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3410 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3411
3412 switch (pipelineBindPoint) {
3413 case VK_PIPELINE_BIND_POINT_COMPUTE:
3414 if (cmd_buffer->state.compute_pipeline == pipeline)
3415 return;
3416 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3417
3418 cmd_buffer->state.compute_pipeline = pipeline;
3419 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3420 break;
3421 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3422 if (cmd_buffer->state.pipeline == pipeline)
3423 return;
3424 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3425
3426 cmd_buffer->state.pipeline = pipeline;
3427 if (!pipeline)
3428 break;
3429
3430 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3431 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3432
3433 /* the new vertex shader might not have the same user regs */
3434 cmd_buffer->state.last_first_instance = -1;
3435 cmd_buffer->state.last_vertex_offset = -1;
3436
3437 /* Prefetch all pipeline shaders at first draw time. */
3438 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3439
3440 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3441 radv_bind_streamout_state(cmd_buffer, pipeline);
3442
3443 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3444 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3445 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3446 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3447
3448 if (radv_pipeline_has_tess(pipeline))
3449 cmd_buffer->tess_rings_needed = true;
3450 break;
3451 default:
3452 assert(!"invalid bind point");
3453 break;
3454 }
3455 }
3456
3457 void radv_CmdSetViewport(
3458 VkCommandBuffer commandBuffer,
3459 uint32_t firstViewport,
3460 uint32_t viewportCount,
3461 const VkViewport* pViewports)
3462 {
3463 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3464 struct radv_cmd_state *state = &cmd_buffer->state;
3465 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3466
3467 assert(firstViewport < MAX_VIEWPORTS);
3468 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3469
3470 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3471 pViewports, viewportCount * sizeof(*pViewports))) {
3472 return;
3473 }
3474
3475 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3476 viewportCount * sizeof(*pViewports));
3477
3478 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3479 }
3480
3481 void radv_CmdSetScissor(
3482 VkCommandBuffer commandBuffer,
3483 uint32_t firstScissor,
3484 uint32_t scissorCount,
3485 const VkRect2D* pScissors)
3486 {
3487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3488 struct radv_cmd_state *state = &cmd_buffer->state;
3489 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3490
3491 assert(firstScissor < MAX_SCISSORS);
3492 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3493
3494 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3495 scissorCount * sizeof(*pScissors))) {
3496 return;
3497 }
3498
3499 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3500 scissorCount * sizeof(*pScissors));
3501
3502 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3503 }
3504
3505 void radv_CmdSetLineWidth(
3506 VkCommandBuffer commandBuffer,
3507 float lineWidth)
3508 {
3509 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3510
3511 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3512 return;
3513
3514 cmd_buffer->state.dynamic.line_width = lineWidth;
3515 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3516 }
3517
3518 void radv_CmdSetDepthBias(
3519 VkCommandBuffer commandBuffer,
3520 float depthBiasConstantFactor,
3521 float depthBiasClamp,
3522 float depthBiasSlopeFactor)
3523 {
3524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3525 struct radv_cmd_state *state = &cmd_buffer->state;
3526
3527 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3528 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3529 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3530 return;
3531 }
3532
3533 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3534 state->dynamic.depth_bias.clamp = depthBiasClamp;
3535 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3536
3537 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3538 }
3539
3540 void radv_CmdSetBlendConstants(
3541 VkCommandBuffer commandBuffer,
3542 const float blendConstants[4])
3543 {
3544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3545 struct radv_cmd_state *state = &cmd_buffer->state;
3546
3547 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3548 return;
3549
3550 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3551
3552 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3553 }
3554
3555 void radv_CmdSetDepthBounds(
3556 VkCommandBuffer commandBuffer,
3557 float minDepthBounds,
3558 float maxDepthBounds)
3559 {
3560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3561 struct radv_cmd_state *state = &cmd_buffer->state;
3562
3563 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3564 state->dynamic.depth_bounds.max == maxDepthBounds) {
3565 return;
3566 }
3567
3568 state->dynamic.depth_bounds.min = minDepthBounds;
3569 state->dynamic.depth_bounds.max = maxDepthBounds;
3570
3571 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3572 }
3573
3574 void radv_CmdSetStencilCompareMask(
3575 VkCommandBuffer commandBuffer,
3576 VkStencilFaceFlags faceMask,
3577 uint32_t compareMask)
3578 {
3579 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3580 struct radv_cmd_state *state = &cmd_buffer->state;
3581 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3582 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3583
3584 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3585 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3586 return;
3587 }
3588
3589 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3590 state->dynamic.stencil_compare_mask.front = compareMask;
3591 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3592 state->dynamic.stencil_compare_mask.back = compareMask;
3593
3594 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3595 }
3596
3597 void radv_CmdSetStencilWriteMask(
3598 VkCommandBuffer commandBuffer,
3599 VkStencilFaceFlags faceMask,
3600 uint32_t writeMask)
3601 {
3602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3603 struct radv_cmd_state *state = &cmd_buffer->state;
3604 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3605 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3606
3607 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3608 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3609 return;
3610 }
3611
3612 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3613 state->dynamic.stencil_write_mask.front = writeMask;
3614 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3615 state->dynamic.stencil_write_mask.back = writeMask;
3616
3617 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3618 }
3619
3620 void radv_CmdSetStencilReference(
3621 VkCommandBuffer commandBuffer,
3622 VkStencilFaceFlags faceMask,
3623 uint32_t reference)
3624 {
3625 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3626 struct radv_cmd_state *state = &cmd_buffer->state;
3627 bool front_same = state->dynamic.stencil_reference.front == reference;
3628 bool back_same = state->dynamic.stencil_reference.back == reference;
3629
3630 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3631 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3632 return;
3633 }
3634
3635 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3636 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3637 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3638 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3639
3640 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3641 }
3642
3643 void radv_CmdSetDiscardRectangleEXT(
3644 VkCommandBuffer commandBuffer,
3645 uint32_t firstDiscardRectangle,
3646 uint32_t discardRectangleCount,
3647 const VkRect2D* pDiscardRectangles)
3648 {
3649 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3650 struct radv_cmd_state *state = &cmd_buffer->state;
3651 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3652
3653 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3654 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3655
3656 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3657 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3658 return;
3659 }
3660
3661 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3662 pDiscardRectangles, discardRectangleCount);
3663
3664 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3665 }
3666
3667 void radv_CmdSetSampleLocationsEXT(
3668 VkCommandBuffer commandBuffer,
3669 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3670 {
3671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3672 struct radv_cmd_state *state = &cmd_buffer->state;
3673
3674 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3675
3676 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3677 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3678 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3679 typed_memcpy(&state->dynamic.sample_location.locations[0],
3680 pSampleLocationsInfo->pSampleLocations,
3681 pSampleLocationsInfo->sampleLocationsCount);
3682
3683 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3684 }
3685
3686 void radv_CmdExecuteCommands(
3687 VkCommandBuffer commandBuffer,
3688 uint32_t commandBufferCount,
3689 const VkCommandBuffer* pCmdBuffers)
3690 {
3691 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3692
3693 assert(commandBufferCount > 0);
3694
3695 /* Emit pending flushes on primary prior to executing secondary */
3696 si_emit_cache_flush(primary);
3697
3698 for (uint32_t i = 0; i < commandBufferCount; i++) {
3699 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3700
3701 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3702 secondary->scratch_size_needed);
3703 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3704 secondary->compute_scratch_size_needed);
3705
3706 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3707 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3708 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3709 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3710 if (secondary->tess_rings_needed)
3711 primary->tess_rings_needed = true;
3712 if (secondary->sample_positions_needed)
3713 primary->sample_positions_needed = true;
3714
3715 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3716
3717
3718 /* When the secondary command buffer is compute only we don't
3719 * need to re-emit the current graphics pipeline.
3720 */
3721 if (secondary->state.emitted_pipeline) {
3722 primary->state.emitted_pipeline =
3723 secondary->state.emitted_pipeline;
3724 }
3725
3726 /* When the secondary command buffer is graphics only we don't
3727 * need to re-emit the current compute pipeline.
3728 */
3729 if (secondary->state.emitted_compute_pipeline) {
3730 primary->state.emitted_compute_pipeline =
3731 secondary->state.emitted_compute_pipeline;
3732 }
3733
3734 /* Only re-emit the draw packets when needed. */
3735 if (secondary->state.last_primitive_reset_en != -1) {
3736 primary->state.last_primitive_reset_en =
3737 secondary->state.last_primitive_reset_en;
3738 }
3739
3740 if (secondary->state.last_primitive_reset_index) {
3741 primary->state.last_primitive_reset_index =
3742 secondary->state.last_primitive_reset_index;
3743 }
3744
3745 if (secondary->state.last_ia_multi_vgt_param) {
3746 primary->state.last_ia_multi_vgt_param =
3747 secondary->state.last_ia_multi_vgt_param;
3748 }
3749
3750 primary->state.last_first_instance = secondary->state.last_first_instance;
3751 primary->state.last_num_instances = secondary->state.last_num_instances;
3752 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3753
3754 if (secondary->state.last_index_type != -1) {
3755 primary->state.last_index_type =
3756 secondary->state.last_index_type;
3757 }
3758 }
3759
3760 /* After executing commands from secondary buffers we have to dirty
3761 * some states.
3762 */
3763 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3764 RADV_CMD_DIRTY_INDEX_BUFFER |
3765 RADV_CMD_DIRTY_DYNAMIC_ALL;
3766 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3767 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3768 }
3769
3770 VkResult radv_CreateCommandPool(
3771 VkDevice _device,
3772 const VkCommandPoolCreateInfo* pCreateInfo,
3773 const VkAllocationCallbacks* pAllocator,
3774 VkCommandPool* pCmdPool)
3775 {
3776 RADV_FROM_HANDLE(radv_device, device, _device);
3777 struct radv_cmd_pool *pool;
3778
3779 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3780 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3781 if (pool == NULL)
3782 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3783
3784 if (pAllocator)
3785 pool->alloc = *pAllocator;
3786 else
3787 pool->alloc = device->alloc;
3788
3789 list_inithead(&pool->cmd_buffers);
3790 list_inithead(&pool->free_cmd_buffers);
3791
3792 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3793
3794 *pCmdPool = radv_cmd_pool_to_handle(pool);
3795
3796 return VK_SUCCESS;
3797
3798 }
3799
3800 void radv_DestroyCommandPool(
3801 VkDevice _device,
3802 VkCommandPool commandPool,
3803 const VkAllocationCallbacks* pAllocator)
3804 {
3805 RADV_FROM_HANDLE(radv_device, device, _device);
3806 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3807
3808 if (!pool)
3809 return;
3810
3811 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3812 &pool->cmd_buffers, pool_link) {
3813 radv_cmd_buffer_destroy(cmd_buffer);
3814 }
3815
3816 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3817 &pool->free_cmd_buffers, pool_link) {
3818 radv_cmd_buffer_destroy(cmd_buffer);
3819 }
3820
3821 vk_free2(&device->alloc, pAllocator, pool);
3822 }
3823
3824 VkResult radv_ResetCommandPool(
3825 VkDevice device,
3826 VkCommandPool commandPool,
3827 VkCommandPoolResetFlags flags)
3828 {
3829 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3830 VkResult result;
3831
3832 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3833 &pool->cmd_buffers, pool_link) {
3834 result = radv_reset_cmd_buffer(cmd_buffer);
3835 if (result != VK_SUCCESS)
3836 return result;
3837 }
3838
3839 return VK_SUCCESS;
3840 }
3841
3842 void radv_TrimCommandPool(
3843 VkDevice device,
3844 VkCommandPool commandPool,
3845 VkCommandPoolTrimFlags flags)
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3848
3849 if (!pool)
3850 return;
3851
3852 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3853 &pool->free_cmd_buffers, pool_link) {
3854 radv_cmd_buffer_destroy(cmd_buffer);
3855 }
3856 }
3857
3858 static void
3859 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3860 uint32_t subpass_id)
3861 {
3862 struct radv_cmd_state *state = &cmd_buffer->state;
3863 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3864
3865 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3866 cmd_buffer->cs, 4096);
3867
3868 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3869
3870 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3871
3872 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3873 const uint32_t a = subpass->attachments[i].attachment;
3874 if (a == VK_ATTACHMENT_UNUSED)
3875 continue;
3876
3877 radv_handle_subpass_image_transition(cmd_buffer,
3878 subpass->attachments[i],
3879 true);
3880 }
3881
3882 radv_cmd_buffer_clear_subpass(cmd_buffer);
3883
3884 assert(cmd_buffer->cs->cdw <= cdw_max);
3885 }
3886
3887 static void
3888 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3889 {
3890 struct radv_cmd_state *state = &cmd_buffer->state;
3891 const struct radv_subpass *subpass = state->subpass;
3892 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3893
3894 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3895
3896 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3897 const uint32_t a = subpass->attachments[i].attachment;
3898 if (a == VK_ATTACHMENT_UNUSED)
3899 continue;
3900
3901 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3902 continue;
3903
3904 VkImageLayout layout = state->pass->attachments[a].final_layout;
3905 struct radv_subpass_attachment att = { a, layout };
3906 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3907 }
3908 }
3909
3910 void radv_CmdBeginRenderPass(
3911 VkCommandBuffer commandBuffer,
3912 const VkRenderPassBeginInfo* pRenderPassBegin,
3913 VkSubpassContents contents)
3914 {
3915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3916 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3917 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3918 VkResult result;
3919
3920 cmd_buffer->state.framebuffer = framebuffer;
3921 cmd_buffer->state.pass = pass;
3922 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3923
3924 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3925 if (result != VK_SUCCESS)
3926 return;
3927
3928 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
3929 if (result != VK_SUCCESS)
3930 return;
3931
3932 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3933 }
3934
3935 void radv_CmdBeginRenderPass2KHR(
3936 VkCommandBuffer commandBuffer,
3937 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3938 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3939 {
3940 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3941 pSubpassBeginInfo->contents);
3942 }
3943
3944 void radv_CmdNextSubpass(
3945 VkCommandBuffer commandBuffer,
3946 VkSubpassContents contents)
3947 {
3948 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3949
3950 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3951 radv_cmd_buffer_end_subpass(cmd_buffer);
3952 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3953 }
3954
3955 void radv_CmdNextSubpass2KHR(
3956 VkCommandBuffer commandBuffer,
3957 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3958 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3959 {
3960 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3961 }
3962
3963 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3964 {
3965 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3966 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3967 if (!radv_get_shader(pipeline, stage))
3968 continue;
3969
3970 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3971 if (loc->sgpr_idx == -1)
3972 continue;
3973 uint32_t base_reg = pipeline->user_data_0[stage];
3974 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3975
3976 }
3977 if (pipeline->gs_copy_shader) {
3978 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3979 if (loc->sgpr_idx != -1) {
3980 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3981 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3982 }
3983 }
3984 }
3985
3986 static void
3987 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3988 uint32_t vertex_count,
3989 bool use_opaque)
3990 {
3991 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3992 radeon_emit(cmd_buffer->cs, vertex_count);
3993 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3994 S_0287F0_USE_OPAQUE(use_opaque));
3995 }
3996
3997 static void
3998 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3999 uint64_t index_va,
4000 uint32_t index_count)
4001 {
4002 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4003 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4004 radeon_emit(cmd_buffer->cs, index_va);
4005 radeon_emit(cmd_buffer->cs, index_va >> 32);
4006 radeon_emit(cmd_buffer->cs, index_count);
4007 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4008 }
4009
4010 static void
4011 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4012 bool indexed,
4013 uint32_t draw_count,
4014 uint64_t count_va,
4015 uint32_t stride)
4016 {
4017 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4018 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4019 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4020 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4021 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4022 bool predicating = cmd_buffer->state.predicating;
4023 assert(base_reg);
4024
4025 /* just reset draw state for vertex data */
4026 cmd_buffer->state.last_first_instance = -1;
4027 cmd_buffer->state.last_num_instances = -1;
4028 cmd_buffer->state.last_vertex_offset = -1;
4029
4030 if (draw_count == 1 && !count_va && !draw_id_enable) {
4031 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4032 PKT3_DRAW_INDIRECT, 3, predicating));
4033 radeon_emit(cs, 0);
4034 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4035 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4036 radeon_emit(cs, di_src_sel);
4037 } else {
4038 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4039 PKT3_DRAW_INDIRECT_MULTI,
4040 8, predicating));
4041 radeon_emit(cs, 0);
4042 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4043 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4044 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4045 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4046 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4047 radeon_emit(cs, draw_count); /* count */
4048 radeon_emit(cs, count_va); /* count_addr */
4049 radeon_emit(cs, count_va >> 32);
4050 radeon_emit(cs, stride); /* stride */
4051 radeon_emit(cs, di_src_sel);
4052 }
4053 }
4054
4055 static void
4056 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4057 const struct radv_draw_info *info)
4058 {
4059 struct radv_cmd_state *state = &cmd_buffer->state;
4060 struct radeon_winsys *ws = cmd_buffer->device->ws;
4061 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4062
4063 if (info->indirect) {
4064 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4065 uint64_t count_va = 0;
4066
4067 va += info->indirect->offset + info->indirect_offset;
4068
4069 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4070
4071 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4072 radeon_emit(cs, 1);
4073 radeon_emit(cs, va);
4074 radeon_emit(cs, va >> 32);
4075
4076 if (info->count_buffer) {
4077 count_va = radv_buffer_get_va(info->count_buffer->bo);
4078 count_va += info->count_buffer->offset +
4079 info->count_buffer_offset;
4080
4081 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4082 }
4083
4084 if (!state->subpass->view_mask) {
4085 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4086 info->indexed,
4087 info->count,
4088 count_va,
4089 info->stride);
4090 } else {
4091 unsigned i;
4092 for_each_bit(i, state->subpass->view_mask) {
4093 radv_emit_view_index(cmd_buffer, i);
4094
4095 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4096 info->indexed,
4097 info->count,
4098 count_va,
4099 info->stride);
4100 }
4101 }
4102 } else {
4103 assert(state->pipeline->graphics.vtx_base_sgpr);
4104
4105 if (info->vertex_offset != state->last_vertex_offset ||
4106 info->first_instance != state->last_first_instance) {
4107 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4108 state->pipeline->graphics.vtx_emit_num);
4109
4110 radeon_emit(cs, info->vertex_offset);
4111 radeon_emit(cs, info->first_instance);
4112 if (state->pipeline->graphics.vtx_emit_num == 3)
4113 radeon_emit(cs, 0);
4114 state->last_first_instance = info->first_instance;
4115 state->last_vertex_offset = info->vertex_offset;
4116 }
4117
4118 if (state->last_num_instances != info->instance_count) {
4119 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4120 radeon_emit(cs, info->instance_count);
4121 state->last_num_instances = info->instance_count;
4122 }
4123
4124 if (info->indexed) {
4125 int index_size = state->index_type ? 4 : 2;
4126 uint64_t index_va;
4127
4128 index_va = state->index_va;
4129 index_va += info->first_index * index_size;
4130
4131 if (!state->subpass->view_mask) {
4132 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4133 index_va,
4134 info->count);
4135 } else {
4136 unsigned i;
4137 for_each_bit(i, state->subpass->view_mask) {
4138 radv_emit_view_index(cmd_buffer, i);
4139
4140 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4141 index_va,
4142 info->count);
4143 }
4144 }
4145 } else {
4146 if (!state->subpass->view_mask) {
4147 radv_cs_emit_draw_packet(cmd_buffer,
4148 info->count,
4149 !!info->strmout_buffer);
4150 } else {
4151 unsigned i;
4152 for_each_bit(i, state->subpass->view_mask) {
4153 radv_emit_view_index(cmd_buffer, i);
4154
4155 radv_cs_emit_draw_packet(cmd_buffer,
4156 info->count,
4157 !!info->strmout_buffer);
4158 }
4159 }
4160 }
4161 }
4162 }
4163
4164 /*
4165 * Vega and raven have a bug which triggers if there are multiple context
4166 * register contexts active at the same time with different scissor values.
4167 *
4168 * There are two possible workarounds:
4169 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4170 * there is only ever 1 active set of scissor values at the same time.
4171 *
4172 * 2) Whenever the hardware switches contexts we have to set the scissor
4173 * registers again even if it is a noop. That way the new context gets
4174 * the correct scissor values.
4175 *
4176 * This implements option 2. radv_need_late_scissor_emission needs to
4177 * return true on affected HW if radv_emit_all_graphics_states sets
4178 * any context registers.
4179 */
4180 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4181 const struct radv_draw_info *info)
4182 {
4183 struct radv_cmd_state *state = &cmd_buffer->state;
4184
4185 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4186 return false;
4187
4188 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4189 return true;
4190
4191 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4192
4193 /* Index, vertex and streamout buffers don't change context regs, and
4194 * pipeline is already handled.
4195 */
4196 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4197 RADV_CMD_DIRTY_VERTEX_BUFFER |
4198 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4199 RADV_CMD_DIRTY_PIPELINE);
4200
4201 if (cmd_buffer->state.dirty & used_states)
4202 return true;
4203
4204 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4205 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4206 return true;
4207
4208 return false;
4209 }
4210
4211 static void
4212 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4213 const struct radv_draw_info *info)
4214 {
4215 bool late_scissor_emission;
4216
4217 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4218 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4219 radv_emit_rbplus_state(cmd_buffer);
4220
4221 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4222 radv_emit_graphics_pipeline(cmd_buffer);
4223
4224 /* This should be before the cmd_buffer->state.dirty is cleared
4225 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4226 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4227 late_scissor_emission =
4228 radv_need_late_scissor_emission(cmd_buffer, info);
4229
4230 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4231 radv_emit_framebuffer_state(cmd_buffer);
4232
4233 if (info->indexed) {
4234 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4235 radv_emit_index_buffer(cmd_buffer);
4236 } else {
4237 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4238 * so the state must be re-emitted before the next indexed
4239 * draw.
4240 */
4241 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4242 cmd_buffer->state.last_index_type = -1;
4243 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4244 }
4245 }
4246
4247 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4248
4249 radv_emit_draw_registers(cmd_buffer, info);
4250
4251 if (late_scissor_emission)
4252 radv_emit_scissor(cmd_buffer);
4253 }
4254
4255 static void
4256 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4257 const struct radv_draw_info *info)
4258 {
4259 struct radeon_info *rad_info =
4260 &cmd_buffer->device->physical_device->rad_info;
4261 bool has_prefetch =
4262 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4263 bool pipeline_is_dirty =
4264 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4265 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4266
4267 MAYBE_UNUSED unsigned cdw_max =
4268 radeon_check_space(cmd_buffer->device->ws,
4269 cmd_buffer->cs, 4096);
4270
4271 if (likely(!info->indirect)) {
4272 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4273 * no workaround for indirect draws, but we can at least skip
4274 * direct draws.
4275 */
4276 if (unlikely(!info->instance_count))
4277 return;
4278
4279 /* Handle count == 0. */
4280 if (unlikely(!info->count && !info->strmout_buffer))
4281 return;
4282 }
4283
4284 /* Use optimal packet order based on whether we need to sync the
4285 * pipeline.
4286 */
4287 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4288 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4289 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4290 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4291 /* If we have to wait for idle, set all states first, so that
4292 * all SET packets are processed in parallel with previous draw
4293 * calls. Then upload descriptors, set shader pointers, and
4294 * draw, and prefetch at the end. This ensures that the time
4295 * the CUs are idle is very short. (there are only SET_SH
4296 * packets between the wait and the draw)
4297 */
4298 radv_emit_all_graphics_states(cmd_buffer, info);
4299 si_emit_cache_flush(cmd_buffer);
4300 /* <-- CUs are idle here --> */
4301
4302 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4303
4304 radv_emit_draw_packets(cmd_buffer, info);
4305 /* <-- CUs are busy here --> */
4306
4307 /* Start prefetches after the draw has been started. Both will
4308 * run in parallel, but starting the draw first is more
4309 * important.
4310 */
4311 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4312 radv_emit_prefetch_L2(cmd_buffer,
4313 cmd_buffer->state.pipeline, false);
4314 }
4315 } else {
4316 /* If we don't wait for idle, start prefetches first, then set
4317 * states, and draw at the end.
4318 */
4319 si_emit_cache_flush(cmd_buffer);
4320
4321 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4322 /* Only prefetch the vertex shader and VBO descriptors
4323 * in order to start the draw as soon as possible.
4324 */
4325 radv_emit_prefetch_L2(cmd_buffer,
4326 cmd_buffer->state.pipeline, true);
4327 }
4328
4329 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4330
4331 radv_emit_all_graphics_states(cmd_buffer, info);
4332 radv_emit_draw_packets(cmd_buffer, info);
4333
4334 /* Prefetch the remaining shaders after the draw has been
4335 * started.
4336 */
4337 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4338 radv_emit_prefetch_L2(cmd_buffer,
4339 cmd_buffer->state.pipeline, false);
4340 }
4341 }
4342
4343 /* Workaround for a VGT hang when streamout is enabled.
4344 * It must be done after drawing.
4345 */
4346 if (cmd_buffer->state.streamout.streamout_enabled &&
4347 (rad_info->family == CHIP_HAWAII ||
4348 rad_info->family == CHIP_TONGA ||
4349 rad_info->family == CHIP_FIJI)) {
4350 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4351 }
4352
4353 assert(cmd_buffer->cs->cdw <= cdw_max);
4354 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4355 }
4356
4357 void radv_CmdDraw(
4358 VkCommandBuffer commandBuffer,
4359 uint32_t vertexCount,
4360 uint32_t instanceCount,
4361 uint32_t firstVertex,
4362 uint32_t firstInstance)
4363 {
4364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4365 struct radv_draw_info info = {};
4366
4367 info.count = vertexCount;
4368 info.instance_count = instanceCount;
4369 info.first_instance = firstInstance;
4370 info.vertex_offset = firstVertex;
4371
4372 radv_draw(cmd_buffer, &info);
4373 }
4374
4375 void radv_CmdDrawIndexed(
4376 VkCommandBuffer commandBuffer,
4377 uint32_t indexCount,
4378 uint32_t instanceCount,
4379 uint32_t firstIndex,
4380 int32_t vertexOffset,
4381 uint32_t firstInstance)
4382 {
4383 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4384 struct radv_draw_info info = {};
4385
4386 info.indexed = true;
4387 info.count = indexCount;
4388 info.instance_count = instanceCount;
4389 info.first_index = firstIndex;
4390 info.vertex_offset = vertexOffset;
4391 info.first_instance = firstInstance;
4392
4393 radv_draw(cmd_buffer, &info);
4394 }
4395
4396 void radv_CmdDrawIndirect(
4397 VkCommandBuffer commandBuffer,
4398 VkBuffer _buffer,
4399 VkDeviceSize offset,
4400 uint32_t drawCount,
4401 uint32_t stride)
4402 {
4403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4404 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4405 struct radv_draw_info info = {};
4406
4407 info.count = drawCount;
4408 info.indirect = buffer;
4409 info.indirect_offset = offset;
4410 info.stride = stride;
4411
4412 radv_draw(cmd_buffer, &info);
4413 }
4414
4415 void radv_CmdDrawIndexedIndirect(
4416 VkCommandBuffer commandBuffer,
4417 VkBuffer _buffer,
4418 VkDeviceSize offset,
4419 uint32_t drawCount,
4420 uint32_t stride)
4421 {
4422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4423 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4424 struct radv_draw_info info = {};
4425
4426 info.indexed = true;
4427 info.count = drawCount;
4428 info.indirect = buffer;
4429 info.indirect_offset = offset;
4430 info.stride = stride;
4431
4432 radv_draw(cmd_buffer, &info);
4433 }
4434
4435 void radv_CmdDrawIndirectCountKHR(
4436 VkCommandBuffer commandBuffer,
4437 VkBuffer _buffer,
4438 VkDeviceSize offset,
4439 VkBuffer _countBuffer,
4440 VkDeviceSize countBufferOffset,
4441 uint32_t maxDrawCount,
4442 uint32_t stride)
4443 {
4444 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4445 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4446 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4447 struct radv_draw_info info = {};
4448
4449 info.count = maxDrawCount;
4450 info.indirect = buffer;
4451 info.indirect_offset = offset;
4452 info.count_buffer = count_buffer;
4453 info.count_buffer_offset = countBufferOffset;
4454 info.stride = stride;
4455
4456 radv_draw(cmd_buffer, &info);
4457 }
4458
4459 void radv_CmdDrawIndexedIndirectCountKHR(
4460 VkCommandBuffer commandBuffer,
4461 VkBuffer _buffer,
4462 VkDeviceSize offset,
4463 VkBuffer _countBuffer,
4464 VkDeviceSize countBufferOffset,
4465 uint32_t maxDrawCount,
4466 uint32_t stride)
4467 {
4468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4469 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4470 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4471 struct radv_draw_info info = {};
4472
4473 info.indexed = true;
4474 info.count = maxDrawCount;
4475 info.indirect = buffer;
4476 info.indirect_offset = offset;
4477 info.count_buffer = count_buffer;
4478 info.count_buffer_offset = countBufferOffset;
4479 info.stride = stride;
4480
4481 radv_draw(cmd_buffer, &info);
4482 }
4483
4484 struct radv_dispatch_info {
4485 /**
4486 * Determine the layout of the grid (in block units) to be used.
4487 */
4488 uint32_t blocks[3];
4489
4490 /**
4491 * A starting offset for the grid. If unaligned is set, the offset
4492 * must still be aligned.
4493 */
4494 uint32_t offsets[3];
4495 /**
4496 * Whether it's an unaligned compute dispatch.
4497 */
4498 bool unaligned;
4499
4500 /**
4501 * Indirect compute parameters resource.
4502 */
4503 struct radv_buffer *indirect;
4504 uint64_t indirect_offset;
4505 };
4506
4507 static void
4508 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4509 const struct radv_dispatch_info *info)
4510 {
4511 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4512 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4513 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4514 struct radeon_winsys *ws = cmd_buffer->device->ws;
4515 bool predicating = cmd_buffer->state.predicating;
4516 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4517 struct radv_userdata_info *loc;
4518
4519 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4520 AC_UD_CS_GRID_SIZE);
4521
4522 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4523
4524 if (info->indirect) {
4525 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4526
4527 va += info->indirect->offset + info->indirect_offset;
4528
4529 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4530
4531 if (loc->sgpr_idx != -1) {
4532 for (unsigned i = 0; i < 3; ++i) {
4533 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4534 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4535 COPY_DATA_DST_SEL(COPY_DATA_REG));
4536 radeon_emit(cs, (va + 4 * i));
4537 radeon_emit(cs, (va + 4 * i) >> 32);
4538 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4539 + loc->sgpr_idx * 4) >> 2) + i);
4540 radeon_emit(cs, 0);
4541 }
4542 }
4543
4544 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4545 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4546 PKT3_SHADER_TYPE_S(1));
4547 radeon_emit(cs, va);
4548 radeon_emit(cs, va >> 32);
4549 radeon_emit(cs, dispatch_initiator);
4550 } else {
4551 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4552 PKT3_SHADER_TYPE_S(1));
4553 radeon_emit(cs, 1);
4554 radeon_emit(cs, va);
4555 radeon_emit(cs, va >> 32);
4556
4557 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4558 PKT3_SHADER_TYPE_S(1));
4559 radeon_emit(cs, 0);
4560 radeon_emit(cs, dispatch_initiator);
4561 }
4562 } else {
4563 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4564 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4565
4566 if (info->unaligned) {
4567 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4568 unsigned remainder[3];
4569
4570 /* If aligned, these should be an entire block size,
4571 * not 0.
4572 */
4573 remainder[0] = blocks[0] + cs_block_size[0] -
4574 align_u32_npot(blocks[0], cs_block_size[0]);
4575 remainder[1] = blocks[1] + cs_block_size[1] -
4576 align_u32_npot(blocks[1], cs_block_size[1]);
4577 remainder[2] = blocks[2] + cs_block_size[2] -
4578 align_u32_npot(blocks[2], cs_block_size[2]);
4579
4580 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4581 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4582 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4583
4584 for(unsigned i = 0; i < 3; ++i) {
4585 assert(offsets[i] % cs_block_size[i] == 0);
4586 offsets[i] /= cs_block_size[i];
4587 }
4588
4589 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4590 radeon_emit(cs,
4591 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4592 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4593 radeon_emit(cs,
4594 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4595 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4596 radeon_emit(cs,
4597 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4598 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4599
4600 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4601 }
4602
4603 if (loc->sgpr_idx != -1) {
4604 assert(loc->num_sgprs == 3);
4605
4606 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4607 loc->sgpr_idx * 4, 3);
4608 radeon_emit(cs, blocks[0]);
4609 radeon_emit(cs, blocks[1]);
4610 radeon_emit(cs, blocks[2]);
4611 }
4612
4613 if (offsets[0] || offsets[1] || offsets[2]) {
4614 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4615 radeon_emit(cs, offsets[0]);
4616 radeon_emit(cs, offsets[1]);
4617 radeon_emit(cs, offsets[2]);
4618
4619 /* The blocks in the packet are not counts but end values. */
4620 for (unsigned i = 0; i < 3; ++i)
4621 blocks[i] += offsets[i];
4622 } else {
4623 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4624 }
4625
4626 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4627 PKT3_SHADER_TYPE_S(1));
4628 radeon_emit(cs, blocks[0]);
4629 radeon_emit(cs, blocks[1]);
4630 radeon_emit(cs, blocks[2]);
4631 radeon_emit(cs, dispatch_initiator);
4632 }
4633
4634 assert(cmd_buffer->cs->cdw <= cdw_max);
4635 }
4636
4637 static void
4638 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4639 {
4640 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4641 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4642 }
4643
4644 static void
4645 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4646 const struct radv_dispatch_info *info)
4647 {
4648 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4649 bool has_prefetch =
4650 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4651 bool pipeline_is_dirty = pipeline &&
4652 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4653
4654 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4655 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4656 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4657 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4658 /* If we have to wait for idle, set all states first, so that
4659 * all SET packets are processed in parallel with previous draw
4660 * calls. Then upload descriptors, set shader pointers, and
4661 * dispatch, and prefetch at the end. This ensures that the
4662 * time the CUs are idle is very short. (there are only SET_SH
4663 * packets between the wait and the draw)
4664 */
4665 radv_emit_compute_pipeline(cmd_buffer);
4666 si_emit_cache_flush(cmd_buffer);
4667 /* <-- CUs are idle here --> */
4668
4669 radv_upload_compute_shader_descriptors(cmd_buffer);
4670
4671 radv_emit_dispatch_packets(cmd_buffer, info);
4672 /* <-- CUs are busy here --> */
4673
4674 /* Start prefetches after the dispatch has been started. Both
4675 * will run in parallel, but starting the dispatch first is
4676 * more important.
4677 */
4678 if (has_prefetch && pipeline_is_dirty) {
4679 radv_emit_shader_prefetch(cmd_buffer,
4680 pipeline->shaders[MESA_SHADER_COMPUTE]);
4681 }
4682 } else {
4683 /* If we don't wait for idle, start prefetches first, then set
4684 * states, and dispatch at the end.
4685 */
4686 si_emit_cache_flush(cmd_buffer);
4687
4688 if (has_prefetch && pipeline_is_dirty) {
4689 radv_emit_shader_prefetch(cmd_buffer,
4690 pipeline->shaders[MESA_SHADER_COMPUTE]);
4691 }
4692
4693 radv_upload_compute_shader_descriptors(cmd_buffer);
4694
4695 radv_emit_compute_pipeline(cmd_buffer);
4696 radv_emit_dispatch_packets(cmd_buffer, info);
4697 }
4698
4699 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4700 }
4701
4702 void radv_CmdDispatchBase(
4703 VkCommandBuffer commandBuffer,
4704 uint32_t base_x,
4705 uint32_t base_y,
4706 uint32_t base_z,
4707 uint32_t x,
4708 uint32_t y,
4709 uint32_t z)
4710 {
4711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4712 struct radv_dispatch_info info = {};
4713
4714 info.blocks[0] = x;
4715 info.blocks[1] = y;
4716 info.blocks[2] = z;
4717
4718 info.offsets[0] = base_x;
4719 info.offsets[1] = base_y;
4720 info.offsets[2] = base_z;
4721 radv_dispatch(cmd_buffer, &info);
4722 }
4723
4724 void radv_CmdDispatch(
4725 VkCommandBuffer commandBuffer,
4726 uint32_t x,
4727 uint32_t y,
4728 uint32_t z)
4729 {
4730 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4731 }
4732
4733 void radv_CmdDispatchIndirect(
4734 VkCommandBuffer commandBuffer,
4735 VkBuffer _buffer,
4736 VkDeviceSize offset)
4737 {
4738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4739 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4740 struct radv_dispatch_info info = {};
4741
4742 info.indirect = buffer;
4743 info.indirect_offset = offset;
4744
4745 radv_dispatch(cmd_buffer, &info);
4746 }
4747
4748 void radv_unaligned_dispatch(
4749 struct radv_cmd_buffer *cmd_buffer,
4750 uint32_t x,
4751 uint32_t y,
4752 uint32_t z)
4753 {
4754 struct radv_dispatch_info info = {};
4755
4756 info.blocks[0] = x;
4757 info.blocks[1] = y;
4758 info.blocks[2] = z;
4759 info.unaligned = 1;
4760
4761 radv_dispatch(cmd_buffer, &info);
4762 }
4763
4764 void radv_CmdEndRenderPass(
4765 VkCommandBuffer commandBuffer)
4766 {
4767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4768
4769 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4770
4771 radv_cmd_buffer_end_subpass(cmd_buffer);
4772
4773 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4774 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4775
4776 cmd_buffer->state.pass = NULL;
4777 cmd_buffer->state.subpass = NULL;
4778 cmd_buffer->state.attachments = NULL;
4779 cmd_buffer->state.framebuffer = NULL;
4780 cmd_buffer->state.subpass_sample_locs = NULL;
4781 }
4782
4783 void radv_CmdEndRenderPass2KHR(
4784 VkCommandBuffer commandBuffer,
4785 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4786 {
4787 radv_CmdEndRenderPass(commandBuffer);
4788 }
4789
4790 /*
4791 * For HTILE we have the following interesting clear words:
4792 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4793 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4794 * 0xfffffff0: Clear depth to 1.0
4795 * 0x00000000: Clear depth to 0.0
4796 */
4797 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4798 struct radv_image *image,
4799 const VkImageSubresourceRange *range,
4800 uint32_t clear_word)
4801 {
4802 assert(range->baseMipLevel == 0);
4803 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4804 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4805 struct radv_cmd_state *state = &cmd_buffer->state;
4806 VkClearDepthStencilValue value = {};
4807
4808 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4809 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4810
4811 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4812
4813 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4814
4815 if (vk_format_is_stencil(image->vk_format))
4816 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4817
4818 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4819
4820 if (radv_image_is_tc_compat_htile(image)) {
4821 /* Initialize the TC-compat metada value to 0 because by
4822 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4823 * need have to conditionally update its value when performing
4824 * a fast depth clear.
4825 */
4826 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4827 }
4828 }
4829
4830 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4831 struct radv_image *image,
4832 VkImageLayout src_layout,
4833 VkImageLayout dst_layout,
4834 unsigned src_queue_mask,
4835 unsigned dst_queue_mask,
4836 const VkImageSubresourceRange *range,
4837 struct radv_sample_locations_state *sample_locs)
4838 {
4839 if (!radv_image_has_htile(image))
4840 return;
4841
4842 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4843 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4844
4845 if (radv_layout_is_htile_compressed(image, dst_layout,
4846 dst_queue_mask)) {
4847 clear_value = 0;
4848 }
4849
4850 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4851 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4852 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4853 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4854 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4855 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4856 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4857 VkImageSubresourceRange local_range = *range;
4858 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4859 local_range.baseMipLevel = 0;
4860 local_range.levelCount = 1;
4861
4862 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4863 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4864
4865 radv_decompress_depth_image_inplace(cmd_buffer, image,
4866 &local_range, sample_locs);
4867
4868 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4869 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4870 }
4871 }
4872
4873 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4874 struct radv_image *image, uint32_t value)
4875 {
4876 struct radv_cmd_state *state = &cmd_buffer->state;
4877
4878 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4879 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4880
4881 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4882
4883 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4884 }
4885
4886 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4887 struct radv_image *image)
4888 {
4889 struct radv_cmd_state *state = &cmd_buffer->state;
4890 static const uint32_t fmask_clear_values[4] = {
4891 0x00000000,
4892 0x02020202,
4893 0xE4E4E4E4,
4894 0x76543210
4895 };
4896 uint32_t log2_samples = util_logbase2(image->info.samples);
4897 uint32_t value = fmask_clear_values[log2_samples];
4898
4899 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4900 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4901
4902 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4903
4904 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4905 }
4906
4907 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4908 struct radv_image *image,
4909 const VkImageSubresourceRange *range, uint32_t value)
4910 {
4911 struct radv_cmd_state *state = &cmd_buffer->state;
4912
4913 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4914 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4915
4916 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
4917
4918 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4919 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4920 }
4921
4922 /**
4923 * Initialize DCC/FMASK/CMASK metadata for a color image.
4924 */
4925 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4926 struct radv_image *image,
4927 VkImageLayout src_layout,
4928 VkImageLayout dst_layout,
4929 unsigned src_queue_mask,
4930 unsigned dst_queue_mask,
4931 const VkImageSubresourceRange *range)
4932 {
4933 if (radv_image_has_cmask(image)) {
4934 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4935
4936 /* TODO: clarify this. */
4937 if (radv_image_has_fmask(image)) {
4938 value = 0xccccccccu;
4939 }
4940
4941 radv_initialise_cmask(cmd_buffer, image, value);
4942 }
4943
4944 if (radv_image_has_fmask(image)) {
4945 radv_initialize_fmask(cmd_buffer, image);
4946 }
4947
4948 if (radv_image_has_dcc(image)) {
4949 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4950 bool need_decompress_pass = false;
4951
4952 if (radv_layout_dcc_compressed(image, dst_layout,
4953 dst_queue_mask)) {
4954 value = 0x20202020u;
4955 need_decompress_pass = true;
4956 }
4957
4958 radv_initialize_dcc(cmd_buffer, image, range, value);
4959
4960 radv_update_fce_metadata(cmd_buffer, image, range,
4961 need_decompress_pass);
4962 }
4963
4964 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4965 uint32_t color_values[2] = {};
4966 radv_set_color_clear_metadata(cmd_buffer, image, range,
4967 color_values);
4968 }
4969 }
4970
4971 /**
4972 * Handle color image transitions for DCC/FMASK/CMASK.
4973 */
4974 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4975 struct radv_image *image,
4976 VkImageLayout src_layout,
4977 VkImageLayout dst_layout,
4978 unsigned src_queue_mask,
4979 unsigned dst_queue_mask,
4980 const VkImageSubresourceRange *range)
4981 {
4982 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4983 radv_init_color_image_metadata(cmd_buffer, image,
4984 src_layout, dst_layout,
4985 src_queue_mask, dst_queue_mask,
4986 range);
4987 return;
4988 }
4989
4990 if (radv_image_has_dcc(image)) {
4991 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4992 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
4993 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4994 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4995 radv_decompress_dcc(cmd_buffer, image, range);
4996 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4997 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4998 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4999 }
5000 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5001 bool fce_eliminate = false, fmask_expand = false;
5002
5003 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5004 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5005 fce_eliminate = true;
5006 }
5007
5008 if (radv_image_has_fmask(image)) {
5009 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5010 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5011 /* A FMASK decompress is required before doing
5012 * a MSAA decompress using FMASK.
5013 */
5014 fmask_expand = true;
5015 }
5016 }
5017
5018 if (fce_eliminate || fmask_expand)
5019 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5020
5021 if (fmask_expand)
5022 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5023 }
5024 }
5025
5026 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5027 struct radv_image *image,
5028 VkImageLayout src_layout,
5029 VkImageLayout dst_layout,
5030 uint32_t src_family,
5031 uint32_t dst_family,
5032 const VkImageSubresourceRange *range,
5033 struct radv_sample_locations_state *sample_locs)
5034 {
5035 if (image->exclusive && src_family != dst_family) {
5036 /* This is an acquire or a release operation and there will be
5037 * a corresponding release/acquire. Do the transition in the
5038 * most flexible queue. */
5039
5040 assert(src_family == cmd_buffer->queue_family_index ||
5041 dst_family == cmd_buffer->queue_family_index);
5042
5043 if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
5044 return;
5045
5046 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5047 return;
5048
5049 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5050 (src_family == RADV_QUEUE_GENERAL ||
5051 dst_family == RADV_QUEUE_GENERAL))
5052 return;
5053 }
5054
5055 if (src_layout == dst_layout)
5056 return;
5057
5058 unsigned src_queue_mask =
5059 radv_image_queue_family_mask(image, src_family,
5060 cmd_buffer->queue_family_index);
5061 unsigned dst_queue_mask =
5062 radv_image_queue_family_mask(image, dst_family,
5063 cmd_buffer->queue_family_index);
5064
5065 if (vk_format_is_depth(image->vk_format)) {
5066 radv_handle_depth_image_transition(cmd_buffer, image,
5067 src_layout, dst_layout,
5068 src_queue_mask, dst_queue_mask,
5069 range, sample_locs);
5070 } else {
5071 radv_handle_color_image_transition(cmd_buffer, image,
5072 src_layout, dst_layout,
5073 src_queue_mask, dst_queue_mask,
5074 range);
5075 }
5076 }
5077
5078 struct radv_barrier_info {
5079 uint32_t eventCount;
5080 const VkEvent *pEvents;
5081 VkPipelineStageFlags srcStageMask;
5082 VkPipelineStageFlags dstStageMask;
5083 };
5084
5085 static void
5086 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5087 uint32_t memoryBarrierCount,
5088 const VkMemoryBarrier *pMemoryBarriers,
5089 uint32_t bufferMemoryBarrierCount,
5090 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5091 uint32_t imageMemoryBarrierCount,
5092 const VkImageMemoryBarrier *pImageMemoryBarriers,
5093 const struct radv_barrier_info *info)
5094 {
5095 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5096 enum radv_cmd_flush_bits src_flush_bits = 0;
5097 enum radv_cmd_flush_bits dst_flush_bits = 0;
5098
5099 for (unsigned i = 0; i < info->eventCount; ++i) {
5100 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5101 uint64_t va = radv_buffer_get_va(event->bo);
5102
5103 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5104
5105 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5106
5107 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5108 assert(cmd_buffer->cs->cdw <= cdw_max);
5109 }
5110
5111 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5112 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5113 NULL);
5114 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5115 NULL);
5116 }
5117
5118 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5119 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5120 NULL);
5121 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5122 NULL);
5123 }
5124
5125 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5126 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5127
5128 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5129 image);
5130 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5131 image);
5132 }
5133
5134 /* The Vulkan spec 1.1.98 says:
5135 *
5136 * "An execution dependency with only
5137 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5138 * will only prevent that stage from executing in subsequently
5139 * submitted commands. As this stage does not perform any actual
5140 * execution, this is not observable - in effect, it does not delay
5141 * processing of subsequent commands. Similarly an execution dependency
5142 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5143 * will effectively not wait for any prior commands to complete."
5144 */
5145 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5146 radv_stage_flush(cmd_buffer, info->srcStageMask);
5147 cmd_buffer->state.flush_bits |= src_flush_bits;
5148
5149 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5150 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5151
5152 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5153 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5154 SAMPLE_LOCATIONS_INFO_EXT);
5155 struct radv_sample_locations_state sample_locations = {};
5156
5157 if (sample_locs_info) {
5158 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5159 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5160 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5161 sample_locations.count = sample_locs_info->sampleLocationsCount;
5162 typed_memcpy(&sample_locations.locations[0],
5163 sample_locs_info->pSampleLocations,
5164 sample_locs_info->sampleLocationsCount);
5165 }
5166
5167 radv_handle_image_transition(cmd_buffer, image,
5168 pImageMemoryBarriers[i].oldLayout,
5169 pImageMemoryBarriers[i].newLayout,
5170 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5171 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5172 &pImageMemoryBarriers[i].subresourceRange,
5173 sample_locs_info ? &sample_locations : NULL);
5174 }
5175
5176 /* Make sure CP DMA is idle because the driver might have performed a
5177 * DMA operation for copying or filling buffers/images.
5178 */
5179 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5180 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5181 si_cp_dma_wait_for_idle(cmd_buffer);
5182
5183 cmd_buffer->state.flush_bits |= dst_flush_bits;
5184 }
5185
5186 void radv_CmdPipelineBarrier(
5187 VkCommandBuffer commandBuffer,
5188 VkPipelineStageFlags srcStageMask,
5189 VkPipelineStageFlags destStageMask,
5190 VkBool32 byRegion,
5191 uint32_t memoryBarrierCount,
5192 const VkMemoryBarrier* pMemoryBarriers,
5193 uint32_t bufferMemoryBarrierCount,
5194 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5195 uint32_t imageMemoryBarrierCount,
5196 const VkImageMemoryBarrier* pImageMemoryBarriers)
5197 {
5198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5199 struct radv_barrier_info info;
5200
5201 info.eventCount = 0;
5202 info.pEvents = NULL;
5203 info.srcStageMask = srcStageMask;
5204 info.dstStageMask = destStageMask;
5205
5206 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5207 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5208 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5209 }
5210
5211
5212 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5213 struct radv_event *event,
5214 VkPipelineStageFlags stageMask,
5215 unsigned value)
5216 {
5217 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5218 uint64_t va = radv_buffer_get_va(event->bo);
5219
5220 si_emit_cache_flush(cmd_buffer);
5221
5222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5223
5224 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5225
5226 /* Flags that only require a top-of-pipe event. */
5227 VkPipelineStageFlags top_of_pipe_flags =
5228 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5229
5230 /* Flags that only require a post-index-fetch event. */
5231 VkPipelineStageFlags post_index_fetch_flags =
5232 top_of_pipe_flags |
5233 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5234 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5235
5236 /* Make sure CP DMA is idle because the driver might have performed a
5237 * DMA operation for copying or filling buffers/images.
5238 */
5239 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5240 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5241 si_cp_dma_wait_for_idle(cmd_buffer);
5242
5243 /* TODO: Emit EOS events for syncing PS/CS stages. */
5244
5245 if (!(stageMask & ~top_of_pipe_flags)) {
5246 /* Just need to sync the PFP engine. */
5247 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5248 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5249 S_370_WR_CONFIRM(1) |
5250 S_370_ENGINE_SEL(V_370_PFP));
5251 radeon_emit(cs, va);
5252 radeon_emit(cs, va >> 32);
5253 radeon_emit(cs, value);
5254 } else if (!(stageMask & ~post_index_fetch_flags)) {
5255 /* Sync ME because PFP reads index and indirect buffers. */
5256 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5257 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5258 S_370_WR_CONFIRM(1) |
5259 S_370_ENGINE_SEL(V_370_ME));
5260 radeon_emit(cs, va);
5261 radeon_emit(cs, va >> 32);
5262 radeon_emit(cs, value);
5263 } else {
5264 /* Otherwise, sync all prior GPU work using an EOP event. */
5265 si_cs_emit_write_event_eop(cs,
5266 cmd_buffer->device->physical_device->rad_info.chip_class,
5267 radv_cmd_buffer_uses_mec(cmd_buffer),
5268 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5269 EOP_DATA_SEL_VALUE_32BIT, va, value,
5270 cmd_buffer->gfx9_eop_bug_va);
5271 }
5272
5273 assert(cmd_buffer->cs->cdw <= cdw_max);
5274 }
5275
5276 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5277 VkEvent _event,
5278 VkPipelineStageFlags stageMask)
5279 {
5280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5281 RADV_FROM_HANDLE(radv_event, event, _event);
5282
5283 write_event(cmd_buffer, event, stageMask, 1);
5284 }
5285
5286 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5287 VkEvent _event,
5288 VkPipelineStageFlags stageMask)
5289 {
5290 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5291 RADV_FROM_HANDLE(radv_event, event, _event);
5292
5293 write_event(cmd_buffer, event, stageMask, 0);
5294 }
5295
5296 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5297 uint32_t eventCount,
5298 const VkEvent* pEvents,
5299 VkPipelineStageFlags srcStageMask,
5300 VkPipelineStageFlags dstStageMask,
5301 uint32_t memoryBarrierCount,
5302 const VkMemoryBarrier* pMemoryBarriers,
5303 uint32_t bufferMemoryBarrierCount,
5304 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5305 uint32_t imageMemoryBarrierCount,
5306 const VkImageMemoryBarrier* pImageMemoryBarriers)
5307 {
5308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5309 struct radv_barrier_info info;
5310
5311 info.eventCount = eventCount;
5312 info.pEvents = pEvents;
5313 info.srcStageMask = 0;
5314
5315 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5316 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5317 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5318 }
5319
5320
5321 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5322 uint32_t deviceMask)
5323 {
5324 /* No-op */
5325 }
5326
5327 /* VK_EXT_conditional_rendering */
5328 void radv_CmdBeginConditionalRenderingEXT(
5329 VkCommandBuffer commandBuffer,
5330 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5331 {
5332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5333 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5334 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5335 bool draw_visible = true;
5336 uint64_t pred_value = 0;
5337 uint64_t va, new_va;
5338 unsigned pred_offset;
5339
5340 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5341
5342 /* By default, if the 32-bit value at offset in buffer memory is zero,
5343 * then the rendering commands are discarded, otherwise they are
5344 * executed as normal. If the inverted flag is set, all commands are
5345 * discarded if the value is non zero.
5346 */
5347 if (pConditionalRenderingBegin->flags &
5348 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5349 draw_visible = false;
5350 }
5351
5352 si_emit_cache_flush(cmd_buffer);
5353
5354 /* From the Vulkan spec 1.1.107:
5355 *
5356 * "If the 32-bit value at offset in buffer memory is zero, then the
5357 * rendering commands are discarded, otherwise they are executed as
5358 * normal. If the value of the predicate in buffer memory changes while
5359 * conditional rendering is active, the rendering commands may be
5360 * discarded in an implementation-dependent way. Some implementations
5361 * may latch the value of the predicate upon beginning conditional
5362 * rendering while others may read it before every rendering command."
5363 *
5364 * But, the AMD hardware treats the predicate as a 64-bit value which
5365 * means we need a workaround in the driver. Luckily, it's not required
5366 * to support if the value changes when predication is active.
5367 *
5368 * The workaround is as follows:
5369 * 1) allocate a 64-value in the upload BO and initialize it to 0
5370 * 2) copy the 32-bit predicate value to the upload BO
5371 * 3) use the new allocated VA address for predication
5372 *
5373 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5374 * in ME (+ sync PFP) instead of PFP.
5375 */
5376 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5377
5378 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5379
5380 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5381 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5382 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5383 COPY_DATA_WR_CONFIRM);
5384 radeon_emit(cs, va);
5385 radeon_emit(cs, va >> 32);
5386 radeon_emit(cs, new_va);
5387 radeon_emit(cs, new_va >> 32);
5388
5389 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5390 radeon_emit(cs, 0);
5391
5392 /* Enable predication for this command buffer. */
5393 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5394 cmd_buffer->state.predicating = true;
5395
5396 /* Store conditional rendering user info. */
5397 cmd_buffer->state.predication_type = draw_visible;
5398 cmd_buffer->state.predication_va = new_va;
5399 }
5400
5401 void radv_CmdEndConditionalRenderingEXT(
5402 VkCommandBuffer commandBuffer)
5403 {
5404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5405
5406 /* Disable predication for this command buffer. */
5407 si_emit_set_predication_state(cmd_buffer, false, 0);
5408 cmd_buffer->state.predicating = false;
5409
5410 /* Reset conditional rendering user info. */
5411 cmd_buffer->state.predication_type = -1;
5412 cmd_buffer->state.predication_va = 0;
5413 }
5414
5415 /* VK_EXT_transform_feedback */
5416 void radv_CmdBindTransformFeedbackBuffersEXT(
5417 VkCommandBuffer commandBuffer,
5418 uint32_t firstBinding,
5419 uint32_t bindingCount,
5420 const VkBuffer* pBuffers,
5421 const VkDeviceSize* pOffsets,
5422 const VkDeviceSize* pSizes)
5423 {
5424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5425 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5426 uint8_t enabled_mask = 0;
5427
5428 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5429 for (uint32_t i = 0; i < bindingCount; i++) {
5430 uint32_t idx = firstBinding + i;
5431
5432 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5433 sb[idx].offset = pOffsets[i];
5434 sb[idx].size = pSizes[i];
5435
5436 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5437 sb[idx].buffer->bo);
5438
5439 enabled_mask |= 1 << idx;
5440 }
5441
5442 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5443
5444 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5445 }
5446
5447 static void
5448 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5449 {
5450 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5452
5453 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5454 radeon_emit(cs,
5455 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5456 S_028B94_RAST_STREAM(0) |
5457 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5458 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5459 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5460 radeon_emit(cs, so->hw_enabled_mask &
5461 so->enabled_stream_buffers_mask);
5462
5463 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5464 }
5465
5466 static void
5467 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5468 {
5469 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5470 bool old_streamout_enabled = so->streamout_enabled;
5471 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5472
5473 so->streamout_enabled = enable;
5474
5475 so->hw_enabled_mask = so->enabled_mask |
5476 (so->enabled_mask << 4) |
5477 (so->enabled_mask << 8) |
5478 (so->enabled_mask << 12);
5479
5480 if ((old_streamout_enabled != so->streamout_enabled) ||
5481 (old_hw_enabled_mask != so->hw_enabled_mask))
5482 radv_emit_streamout_enable(cmd_buffer);
5483 }
5484
5485 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5486 {
5487 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5488 unsigned reg_strmout_cntl;
5489
5490 /* The register is at different places on different ASICs. */
5491 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5492 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5493 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5494 } else {
5495 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5496 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5497 }
5498
5499 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5500 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5501
5502 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5503 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5504 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5505 radeon_emit(cs, 0);
5506 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5507 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5508 radeon_emit(cs, 4); /* poll interval */
5509 }
5510
5511 void radv_CmdBeginTransformFeedbackEXT(
5512 VkCommandBuffer commandBuffer,
5513 uint32_t firstCounterBuffer,
5514 uint32_t counterBufferCount,
5515 const VkBuffer* pCounterBuffers,
5516 const VkDeviceSize* pCounterBufferOffsets)
5517 {
5518 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5519 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5520 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5521 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5522 uint32_t i;
5523
5524 radv_flush_vgt_streamout(cmd_buffer);
5525
5526 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5527 for_each_bit(i, so->enabled_mask) {
5528 int32_t counter_buffer_idx = i - firstCounterBuffer;
5529 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5530 counter_buffer_idx = -1;
5531
5532 /* AMD GCN binds streamout buffers as shader resources.
5533 * VGT only counts primitives and tells the shader through
5534 * SGPRs what to do.
5535 */
5536 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5537 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5538 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5539
5540 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5541
5542 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5543 /* The array of counter buffers is optional. */
5544 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5545 uint64_t va = radv_buffer_get_va(buffer->bo);
5546
5547 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5548
5549 /* Append */
5550 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5551 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5552 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5553 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5554 radeon_emit(cs, 0); /* unused */
5555 radeon_emit(cs, 0); /* unused */
5556 radeon_emit(cs, va); /* src address lo */
5557 radeon_emit(cs, va >> 32); /* src address hi */
5558
5559 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5560 } else {
5561 /* Start from the beginning. */
5562 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5563 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5564 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5565 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5566 radeon_emit(cs, 0); /* unused */
5567 radeon_emit(cs, 0); /* unused */
5568 radeon_emit(cs, 0); /* unused */
5569 radeon_emit(cs, 0); /* unused */
5570 }
5571 }
5572
5573 radv_set_streamout_enable(cmd_buffer, true);
5574 }
5575
5576 void radv_CmdEndTransformFeedbackEXT(
5577 VkCommandBuffer commandBuffer,
5578 uint32_t firstCounterBuffer,
5579 uint32_t counterBufferCount,
5580 const VkBuffer* pCounterBuffers,
5581 const VkDeviceSize* pCounterBufferOffsets)
5582 {
5583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5584 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5585 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5586 uint32_t i;
5587
5588 radv_flush_vgt_streamout(cmd_buffer);
5589
5590 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5591 for_each_bit(i, so->enabled_mask) {
5592 int32_t counter_buffer_idx = i - firstCounterBuffer;
5593 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5594 counter_buffer_idx = -1;
5595
5596 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5597 /* The array of counters buffer is optional. */
5598 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5599 uint64_t va = radv_buffer_get_va(buffer->bo);
5600
5601 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5602
5603 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5604 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5605 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5606 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5607 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5608 radeon_emit(cs, va); /* dst address lo */
5609 radeon_emit(cs, va >> 32); /* dst address hi */
5610 radeon_emit(cs, 0); /* unused */
5611 radeon_emit(cs, 0); /* unused */
5612
5613 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5614 }
5615
5616 /* Deactivate transform feedback by zeroing the buffer size.
5617 * The counters (primitives generated, primitives emitted) may
5618 * be enabled even if there is not buffer bound. This ensures
5619 * that the primitives-emitted query won't increment.
5620 */
5621 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5622
5623 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5624 }
5625
5626 radv_set_streamout_enable(cmd_buffer, false);
5627 }
5628
5629 void radv_CmdDrawIndirectByteCountEXT(
5630 VkCommandBuffer commandBuffer,
5631 uint32_t instanceCount,
5632 uint32_t firstInstance,
5633 VkBuffer _counterBuffer,
5634 VkDeviceSize counterBufferOffset,
5635 uint32_t counterOffset,
5636 uint32_t vertexStride)
5637 {
5638 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5639 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5640 struct radv_draw_info info = {};
5641
5642 info.instance_count = instanceCount;
5643 info.first_instance = firstInstance;
5644 info.strmout_buffer = counterBuffer;
5645 info.strmout_buffer_offset = counterBufferOffset;
5646 info.stride = vertexStride;
5647
5648 radv_draw(cmd_buffer, &info);
5649 }