2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
83 const struct radv_dynamic_state
*src
,
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
89 dest
->viewport
.count
= src
->viewport
.count
;
90 dest
->scissor
.count
= src
->scissor
.count
;
92 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
93 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
97 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
98 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
103 dest
->line_width
= src
->line_width
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
106 dest
->depth_bias
= src
->depth_bias
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
109 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
112 dest
->depth_bounds
= src
->depth_bounds
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
115 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
117 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
118 dest
->stencil_write_mask
= src
->stencil_write_mask
;
120 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
121 dest
->stencil_reference
= src
->stencil_reference
;
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
126 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
127 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
130 enum ring_type
radv_queue_family_to_ring(int f
) {
132 case RADV_QUEUE_GENERAL
:
134 case RADV_QUEUE_COMPUTE
:
136 case RADV_QUEUE_TRANSFER
:
139 unreachable("Unknown queue family");
143 static VkResult
radv_create_cmd_buffer(
144 struct radv_device
* device
,
145 struct radv_cmd_pool
* pool
,
146 VkCommandBufferLevel level
,
147 VkCommandBuffer
* pCommandBuffer
)
149 struct radv_cmd_buffer
*cmd_buffer
;
151 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
153 if (cmd_buffer
== NULL
)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
156 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
157 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
158 cmd_buffer
->device
= device
;
159 cmd_buffer
->pool
= pool
;
160 cmd_buffer
->level
= level
;
163 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
164 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
167 /* Init the pool_link so we can safefly call list_del when we destroy
170 list_inithead(&cmd_buffer
->pool_link
);
171 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
174 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
176 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
177 if (!cmd_buffer
->cs
) {
178 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
182 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
184 cmd_buffer
->upload
.offset
= 0;
185 cmd_buffer
->upload
.size
= 0;
186 list_inithead(&cmd_buffer
->upload
.list
);
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
194 list_del(&cmd_buffer
->pool_link
);
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
197 &cmd_buffer
->upload
.list
, list
) {
198 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
203 if (cmd_buffer
->upload
.upload_bo
)
204 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
205 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
206 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
207 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
211 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
214 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
217 &cmd_buffer
->upload
.list
, list
) {
218 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
223 cmd_buffer
->push_constant_stages
= 0;
224 cmd_buffer
->scratch_size_needed
= 0;
225 cmd_buffer
->compute_scratch_size_needed
= 0;
226 cmd_buffer
->esgs_ring_size_needed
= 0;
227 cmd_buffer
->gsvs_ring_size_needed
= 0;
228 cmd_buffer
->tess_rings_needed
= false;
229 cmd_buffer
->sample_positions_needed
= false;
231 if (cmd_buffer
->upload
.upload_bo
)
232 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
233 cmd_buffer
->upload
.upload_bo
, 8);
234 cmd_buffer
->upload
.offset
= 0;
236 cmd_buffer
->record_result
= VK_SUCCESS
;
238 cmd_buffer
->ring_offsets_idx
= -1;
240 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
242 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
243 &cmd_buffer
->gfx9_fence_offset
,
245 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
248 return cmd_buffer
->record_result
;
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
256 struct radeon_winsys_bo
*bo
;
257 struct radv_cmd_buffer_upload
*upload
;
258 struct radv_device
*device
= cmd_buffer
->device
;
260 new_size
= MAX2(min_needed
, 16 * 1024);
261 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
263 bo
= device
->ws
->buffer_create(device
->ws
,
266 RADEON_FLAG_CPU_ACCESS
);
269 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
273 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
274 if (cmd_buffer
->upload
.upload_bo
) {
275 upload
= malloc(sizeof(*upload
));
278 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
279 device
->ws
->buffer_destroy(bo
);
283 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
284 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
287 cmd_buffer
->upload
.upload_bo
= bo
;
288 cmd_buffer
->upload
.size
= new_size
;
289 cmd_buffer
->upload
.offset
= 0;
290 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
292 if (!cmd_buffer
->upload
.map
) {
293 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
304 unsigned *out_offset
,
307 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
308 if (offset
+ size
> cmd_buffer
->upload
.size
) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
314 *out_offset
= offset
;
315 *ptr
= cmd_buffer
->upload
.map
+ offset
;
317 cmd_buffer
->upload
.offset
= offset
+ size
;
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
323 unsigned size
, unsigned alignment
,
324 const void *data
, unsigned *out_offset
)
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
329 out_offset
, (void **)&ptr
))
333 memcpy(ptr
, data
, size
);
339 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
340 unsigned count
, const uint32_t *data
)
342 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
343 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME
));
347 radeon_emit(cs
, va
>> 32);
348 radeon_emit_array(cs
, data
, count
);
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
353 struct radv_device
*device
= cmd_buffer
->device
;
354 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
357 if (!device
->trace_bo
)
360 va
= radv_buffer_get_va(device
->trace_bo
);
361 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
364 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
366 ++cmd_buffer
->state
.trace_id
;
367 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
368 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
369 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
370 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
376 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
377 enum radv_cmd_flush_bits flags
;
379 /* Force wait for graphics/compute engines to be idle. */
380 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
383 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
384 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
386 radv_cmd_buffer_uses_mec(cmd_buffer
),
390 radv_cmd_buffer_trace_emit(cmd_buffer
);
394 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
395 struct radv_pipeline
*pipeline
, enum ring_type ring
)
397 struct radv_device
*device
= cmd_buffer
->device
;
398 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
402 if (!device
->trace_bo
)
405 va
= radv_buffer_get_va(device
->trace_bo
);
415 assert(!"invalid ring type");
418 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
421 data
[0] = (uintptr_t)pipeline
;
422 data
[1] = (uintptr_t)pipeline
>> 32;
424 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
425 radv_emit_write_data_packet(cs
, va
, 2, data
);
429 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
431 struct radv_device
*device
= cmd_buffer
->device
;
432 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
433 uint32_t data
[MAX_SETS
* 2] = {};
436 if (!device
->trace_bo
)
439 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
441 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
442 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
444 for (int i
= 0; i
< MAX_SETS
; i
++) {
445 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
449 data
[i
* 2] = (uintptr_t)set
;
450 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
453 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
454 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
459 struct radv_pipeline
*pipeline
)
461 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
462 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
464 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
465 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
467 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
469 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
470 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
472 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
473 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
481 struct radv_pipeline
*pipeline
)
483 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
484 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
485 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
487 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
488 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
491 struct ac_userdata_info
*
492 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
493 gl_shader_stage stage
,
496 if (stage
== MESA_SHADER_VERTEX
) {
497 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
498 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.user_sgprs_locs
.shader_data
[idx
];
499 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
500 return &pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.user_sgprs_locs
.shader_data
[idx
];
501 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
502 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
503 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
504 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
505 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.user_sgprs_locs
.shader_data
[idx
];
506 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
507 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
509 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
513 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
514 struct radv_pipeline
*pipeline
,
515 gl_shader_stage stage
,
516 int idx
, uint64_t va
)
518 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
519 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
520 if (loc
->sgpr_idx
== -1)
522 assert(loc
->num_sgprs
== 2);
523 assert(!loc
->indirect
);
524 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
525 radeon_emit(cmd_buffer
->cs
, va
);
526 radeon_emit(cmd_buffer
->cs
, va
>> 32);
530 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
531 struct radv_pipeline
*pipeline
)
533 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
534 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
535 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
537 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
538 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
539 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
541 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
542 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
544 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
547 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
548 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
549 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
551 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
553 /* GFX9: Flush DFSM when the AA mode changes. */
554 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
555 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
556 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
558 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
560 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
561 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
562 if (loc
->sgpr_idx
== -1)
564 assert(loc
->num_sgprs
== 1);
565 assert(!loc
->indirect
);
566 switch (num_samples
) {
584 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
585 cmd_buffer
->sample_positions_needed
= true;
590 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
591 struct radv_pipeline
*pipeline
)
593 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
595 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
596 raster
->pa_cl_clip_cntl
);
597 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
598 raster
->spi_interp_control
);
599 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
600 raster
->pa_su_vtx_cntl
);
601 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
602 raster
->pa_su_sc_mode_cntl
);
606 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
609 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
610 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
614 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
615 struct radv_pipeline
*pipeline
,
616 struct radv_shader_variant
*shader
,
617 struct ac_vs_output_info
*outinfo
)
619 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
620 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
621 unsigned export_count
;
623 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
624 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
626 export_count
= MAX2(1, outinfo
->param_exports
);
627 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
628 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
630 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
631 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
632 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
633 V_02870C_SPI_SHADER_4COMP
:
634 V_02870C_SPI_SHADER_NONE
) |
635 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
636 V_02870C_SPI_SHADER_4COMP
:
637 V_02870C_SPI_SHADER_NONE
) |
638 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
639 V_02870C_SPI_SHADER_4COMP
:
640 V_02870C_SPI_SHADER_NONE
));
643 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
644 radeon_emit(cmd_buffer
->cs
, va
>> 8);
645 radeon_emit(cmd_buffer
->cs
, va
>> 40);
646 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
647 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
649 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
650 S_028818_VTX_W0_FMT(1) |
651 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
652 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
653 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
656 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
657 pipeline
->graphics
.pa_cl_vs_out_cntl
);
659 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
660 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
661 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
665 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
666 struct radv_shader_variant
*shader
,
667 struct ac_es_output_info
*outinfo
)
669 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
670 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
672 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
673 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
675 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
676 outinfo
->esgs_itemsize
/ 4);
677 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
678 radeon_emit(cmd_buffer
->cs
, va
>> 8);
679 radeon_emit(cmd_buffer
->cs
, va
>> 40);
680 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
681 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
685 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
686 struct radv_shader_variant
*shader
)
688 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
689 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
690 uint32_t rsrc2
= shader
->rsrc2
;
692 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
693 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
695 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
696 radeon_emit(cmd_buffer
->cs
, va
>> 8);
697 radeon_emit(cmd_buffer
->cs
, va
>> 40);
699 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
700 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
701 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
702 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
704 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
705 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
706 radeon_emit(cmd_buffer
->cs
, rsrc2
);
710 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
711 struct radv_shader_variant
*shader
)
713 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
714 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
716 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
717 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
719 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
720 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
721 radeon_emit(cmd_buffer
->cs
, va
>> 8);
722 radeon_emit(cmd_buffer
->cs
, va
>> 40);
724 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
725 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
726 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
|
727 S_00B42C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
));
729 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
730 radeon_emit(cmd_buffer
->cs
, va
>> 8);
731 radeon_emit(cmd_buffer
->cs
, va
>> 40);
732 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
733 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
738 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
739 struct radv_pipeline
*pipeline
)
741 struct radv_shader_variant
*vs
;
743 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
745 /* Skip shaders merged into HS/GS */
746 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
750 if (vs
->info
.vs
.as_ls
)
751 radv_emit_hw_ls(cmd_buffer
, vs
);
752 else if (vs
->info
.vs
.as_es
)
753 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
755 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
760 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
761 struct radv_pipeline
*pipeline
)
763 if (!radv_pipeline_has_tess(pipeline
))
766 struct radv_shader_variant
*tes
, *tcs
;
768 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
769 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
772 if (tes
->info
.tes
.as_es
)
773 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
775 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
778 radv_emit_hw_hs(cmd_buffer
, tcs
);
780 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
781 pipeline
->graphics
.tess
.tf_param
);
783 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
784 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
785 pipeline
->graphics
.tess
.ls_hs_config
);
787 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
788 pipeline
->graphics
.tess
.ls_hs_config
);
790 struct ac_userdata_info
*loc
;
792 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
793 if (loc
->sgpr_idx
!= -1) {
794 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
795 assert(loc
->num_sgprs
== 4);
796 assert(!loc
->indirect
);
797 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
798 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
799 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
800 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
801 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
802 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
805 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
806 if (loc
->sgpr_idx
!= -1) {
807 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
808 assert(loc
->num_sgprs
== 1);
809 assert(!loc
->indirect
);
811 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
812 pipeline
->graphics
.tess
.offchip_layout
);
815 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
816 if (loc
->sgpr_idx
!= -1) {
817 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
818 assert(loc
->num_sgprs
== 1);
819 assert(!loc
->indirect
);
821 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
822 pipeline
->graphics
.tess
.tcs_in_layout
);
827 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
828 struct radv_pipeline
*pipeline
)
830 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
831 struct radv_shader_variant
*gs
;
834 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
836 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
840 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
842 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
843 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
844 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
845 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
847 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
849 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
851 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
852 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
853 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
854 radeon_emit(cmd_buffer
->cs
, 0);
855 radeon_emit(cmd_buffer
->cs
, 0);
856 radeon_emit(cmd_buffer
->cs
, 0);
858 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
859 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
860 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
861 S_028B90_ENABLE(gs_num_invocations
> 0));
863 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
864 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
865 radv_emit_prefetch(cmd_buffer
, va
, gs
->code_size
);
867 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
868 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
869 radeon_emit(cmd_buffer
->cs
, va
>> 8);
870 radeon_emit(cmd_buffer
->cs
, va
>> 40);
872 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
873 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
874 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
|
875 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
877 radeon_set_context_reg(cmd_buffer
->cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
878 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
879 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
, pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
881 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
882 radeon_emit(cmd_buffer
->cs
, va
>> 8);
883 radeon_emit(cmd_buffer
->cs
, va
>> 40);
884 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
885 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
888 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
890 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
891 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
892 if (loc
->sgpr_idx
!= -1) {
893 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
894 uint32_t num_entries
= 64;
895 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
898 num_entries
*= stride
;
900 stride
= S_008F04_STRIDE(stride
);
901 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
902 radeon_emit(cmd_buffer
->cs
, stride
);
903 radeon_emit(cmd_buffer
->cs
, num_entries
);
908 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
909 struct radv_pipeline
*pipeline
)
911 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
912 struct radv_shader_variant
*ps
;
914 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
915 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
916 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
918 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
919 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
920 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
921 radv_emit_prefetch(cmd_buffer
, va
, ps
->code_size
);
923 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
924 radeon_emit(cmd_buffer
->cs
, va
>> 8);
925 radeon_emit(cmd_buffer
->cs
, va
>> 40);
926 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
927 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
929 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
930 pipeline
->graphics
.db_shader_control
);
932 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
933 ps
->config
.spi_ps_input_ena
);
935 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
936 ps
->config
.spi_ps_input_addr
);
938 if (ps
->info
.info
.ps
.force_persample
)
939 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
941 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
942 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
944 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
946 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
947 pipeline
->graphics
.shader_z_format
);
949 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
951 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
952 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
954 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
956 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
957 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
960 if (pipeline
->graphics
.ps_input_cntl_num
) {
961 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
962 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
963 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
969 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
970 struct radv_pipeline
*pipeline
)
972 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
974 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
977 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
978 pipeline
->graphics
.vtx_reuse_depth
);
982 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
984 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
986 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
989 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
990 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
991 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
992 radv_update_multisample_state(cmd_buffer
, pipeline
);
993 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
994 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
995 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
996 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
997 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
999 cmd_buffer
->scratch_size_needed
=
1000 MAX2(cmd_buffer
->scratch_size_needed
,
1001 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1003 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
1004 S_0286E8_WAVES(pipeline
->max_waves
) |
1005 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
1007 if (!cmd_buffer
->state
.emitted_pipeline
||
1008 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1009 pipeline
->graphics
.can_use_guardband
)
1010 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1012 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1014 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1015 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
1017 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
1019 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
1021 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1023 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1025 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1029 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1031 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1032 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1036 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1038 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1040 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1041 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1042 si_emit_cache_flush(cmd_buffer
);
1044 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1045 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1046 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1047 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1048 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1049 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1053 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1055 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1057 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1058 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1062 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1064 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1066 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1067 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1071 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1073 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1075 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1076 R_028430_DB_STENCILREFMASK
, 2);
1077 radeon_emit(cmd_buffer
->cs
,
1078 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1079 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1080 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1081 S_028430_STENCILOPVAL(1));
1082 radeon_emit(cmd_buffer
->cs
,
1083 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1084 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1085 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1086 S_028434_STENCILOPVAL_BF(1));
1090 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1092 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1094 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1095 fui(d
->depth_bounds
.min
));
1096 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1097 fui(d
->depth_bounds
.max
));
1101 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1103 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1104 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1105 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1106 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1108 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1109 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1110 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1111 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1112 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1113 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1114 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1115 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1120 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1122 struct radv_color_buffer_info
*cb
)
1124 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1126 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1127 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1128 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1129 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1130 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1131 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1132 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1133 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1134 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1135 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1136 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1137 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1138 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1140 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1141 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1142 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1144 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1147 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1148 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1149 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1150 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1151 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1152 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1153 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1154 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1155 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1156 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1157 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1158 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1160 if (is_vi
) { /* DCC BASE */
1161 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1167 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1168 struct radv_ds_buffer_info
*ds
,
1169 struct radv_image
*image
,
1170 VkImageLayout layout
)
1172 uint32_t db_z_info
= ds
->db_z_info
;
1173 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1175 if (!radv_layout_has_htile(image
, layout
,
1176 radv_image_queue_family_mask(image
,
1177 cmd_buffer
->queue_family_index
,
1178 cmd_buffer
->queue_family_index
))) {
1179 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1180 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1183 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1184 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1187 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1188 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1189 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1190 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1191 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1193 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1194 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1195 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1196 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1197 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1198 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1199 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1200 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1201 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1202 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1203 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1205 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1206 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1207 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1209 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1211 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1212 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1213 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1214 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1215 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1216 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1217 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1218 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1219 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1220 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1224 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1225 ds
->pa_su_poly_offset_db_fmt_cntl
);
1229 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1230 struct radv_image
*image
,
1231 VkClearDepthStencilValue ds_clear_value
,
1232 VkImageAspectFlags aspects
)
1234 uint64_t va
= radv_buffer_get_va(image
->bo
);
1235 va
+= image
->offset
+ image
->clear_value_offset
;
1236 unsigned reg_offset
= 0, reg_count
= 0;
1238 if (!image
->surface
.htile_size
|| !aspects
)
1241 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1247 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1250 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1252 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1253 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1254 S_370_WR_CONFIRM(1) |
1255 S_370_ENGINE_SEL(V_370_PFP
));
1256 radeon_emit(cmd_buffer
->cs
, va
);
1257 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1258 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1259 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1260 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1261 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1263 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1264 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1265 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1266 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1267 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1271 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1272 struct radv_image
*image
)
1274 uint64_t va
= radv_buffer_get_va(image
->bo
);
1275 va
+= image
->offset
+ image
->clear_value_offset
;
1277 if (!image
->surface
.htile_size
)
1280 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1282 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1283 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1284 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1285 COPY_DATA_COUNT_SEL
);
1286 radeon_emit(cmd_buffer
->cs
, va
);
1287 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1288 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1289 radeon_emit(cmd_buffer
->cs
, 0);
1291 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1292 radeon_emit(cmd_buffer
->cs
, 0);
1296 *with DCC some colors don't require CMASK elimiation before being
1297 * used as a texture. This sets a predicate value to determine if the
1298 * cmask eliminate is required.
1301 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1302 struct radv_image
*image
,
1305 uint64_t pred_val
= value
;
1306 uint64_t va
= radv_buffer_get_va(image
->bo
);
1307 va
+= image
->offset
+ image
->dcc_pred_offset
;
1309 if (!image
->surface
.dcc_size
)
1312 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1314 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1315 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP
));
1318 radeon_emit(cmd_buffer
->cs
, va
);
1319 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1320 radeon_emit(cmd_buffer
->cs
, pred_val
);
1321 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1325 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1326 struct radv_image
*image
,
1328 uint32_t color_values
[2])
1330 uint64_t va
= radv_buffer_get_va(image
->bo
);
1331 va
+= image
->offset
+ image
->clear_value_offset
;
1333 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1336 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1338 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1339 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1340 S_370_WR_CONFIRM(1) |
1341 S_370_ENGINE_SEL(V_370_PFP
));
1342 radeon_emit(cmd_buffer
->cs
, va
);
1343 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1344 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1345 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1347 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1348 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1349 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1353 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1354 struct radv_image
*image
,
1357 uint64_t va
= radv_buffer_get_va(image
->bo
);
1358 va
+= image
->offset
+ image
->clear_value_offset
;
1360 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1363 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1364 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1366 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1367 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1368 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1369 COPY_DATA_COUNT_SEL
);
1370 radeon_emit(cmd_buffer
->cs
, va
);
1371 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1372 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1373 radeon_emit(cmd_buffer
->cs
, 0);
1375 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1376 radeon_emit(cmd_buffer
->cs
, 0);
1380 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1383 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1384 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1386 /* this may happen for inherited secondary recording */
1390 for (i
= 0; i
< 8; ++i
) {
1391 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1392 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1393 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1397 int idx
= subpass
->color_attachments
[i
].attachment
;
1398 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1400 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1402 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1403 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1405 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1408 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1409 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1410 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1411 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1412 struct radv_image
*image
= att
->attachment
->image
;
1413 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1414 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1415 cmd_buffer
->queue_family_index
,
1416 cmd_buffer
->queue_family_index
);
1417 /* We currently don't support writing decompressed HTILE */
1418 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1419 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1421 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1423 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1424 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1425 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1427 radv_load_depth_clear_regs(cmd_buffer
, image
);
1429 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1430 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1432 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1434 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1435 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1437 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1438 S_028208_BR_X(framebuffer
->width
) |
1439 S_028208_BR_Y(framebuffer
->height
));
1441 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1442 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1443 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1446 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1450 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1452 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1454 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1455 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1456 2, cmd_buffer
->state
.index_type
);
1458 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1459 radeon_emit(cs
, cmd_buffer
->state
.index_type
);
1462 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1463 radeon_emit(cs
, cmd_buffer
->state
.index_va
);
1464 radeon_emit(cs
, cmd_buffer
->state
.index_va
>> 32);
1466 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1467 radeon_emit(cs
, cmd_buffer
->state
.max_index_count
);
1469 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1472 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1474 uint32_t db_count_control
;
1476 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1477 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1478 db_count_control
= 0;
1480 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1483 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1484 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1485 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1486 S_028004_ZPASS_ENABLE(1) |
1487 S_028004_SLICE_EVEN_ENABLE(1) |
1488 S_028004_SLICE_ODD_ENABLE(1);
1490 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1491 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1495 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1499 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1501 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1504 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1505 radv_emit_viewport(cmd_buffer
);
1507 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1508 radv_emit_scissor(cmd_buffer
);
1510 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1511 radv_emit_line_width(cmd_buffer
);
1513 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1514 radv_emit_blend_constants(cmd_buffer
);
1516 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1517 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1518 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1519 radv_emit_stencil(cmd_buffer
);
1521 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1522 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
))
1523 radv_emit_depth_bounds(cmd_buffer
);
1525 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1526 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1527 radv_emit_depth_biais(cmd_buffer
);
1529 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
1533 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1534 struct radv_pipeline
*pipeline
,
1537 gl_shader_stage stage
)
1539 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1540 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1542 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1545 assert(!desc_set_loc
->indirect
);
1546 assert(desc_set_loc
->num_sgprs
== 2);
1547 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1548 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1549 radeon_emit(cmd_buffer
->cs
, va
);
1550 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1554 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1555 VkShaderStageFlags stages
,
1556 struct radv_descriptor_set
*set
,
1559 if (cmd_buffer
->state
.pipeline
) {
1560 radv_foreach_stage(stage
, stages
) {
1561 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1562 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1568 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1569 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1571 MESA_SHADER_COMPUTE
);
1575 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1577 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1580 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1585 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1586 set
->va
+= bo_offset
;
1590 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1592 uint32_t size
= MAX_SETS
* 2 * 4;
1596 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1597 256, &offset
, &ptr
))
1600 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1601 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1602 uint64_t set_va
= 0;
1603 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1606 uptr
[0] = set_va
& 0xffffffff;
1607 uptr
[1] = set_va
>> 32;
1610 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1613 if (cmd_buffer
->state
.pipeline
) {
1614 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1615 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1616 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1618 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1619 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1620 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1622 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1623 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1624 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1626 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1627 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1628 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1630 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1631 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1632 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1635 if (cmd_buffer
->state
.compute_pipeline
)
1636 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1637 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1641 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1642 VkShaderStageFlags stages
)
1646 if (!cmd_buffer
->state
.descriptors_dirty
)
1649 if (cmd_buffer
->state
.push_descriptors_dirty
)
1650 radv_flush_push_descriptors(cmd_buffer
);
1652 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1653 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1654 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1657 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1659 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1661 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1662 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1666 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1668 cmd_buffer
->state
.descriptors_dirty
= 0;
1669 cmd_buffer
->state
.push_descriptors_dirty
= false;
1671 radv_save_descriptors(cmd_buffer
);
1673 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1677 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1678 struct radv_pipeline
*pipeline
,
1679 VkShaderStageFlags stages
)
1681 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1686 stages
&= cmd_buffer
->push_constant_stages
;
1687 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1690 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1691 16 * layout
->dynamic_offset_count
,
1692 256, &offset
, &ptr
))
1695 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1696 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1697 16 * layout
->dynamic_offset_count
);
1699 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1702 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1703 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1705 radv_foreach_stage(stage
, stages
) {
1706 if (pipeline
->shaders
[stage
]) {
1707 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1708 AC_UD_PUSH_CONSTANTS
, va
);
1712 cmd_buffer
->push_constant_stages
&= ~stages
;
1713 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1717 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1719 struct radv_device
*device
= cmd_buffer
->device
;
1721 if ((cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
|| cmd_buffer
->state
.vb_dirty
) &&
1722 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1723 radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.has_vertex_buffers
) {
1724 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1728 uint32_t count
= velems
->count
;
1731 /* allocate some descriptor state for vertex buffers */
1732 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1733 &vb_offset
, &vb_ptr
))
1736 for (i
= 0; i
< count
; i
++) {
1737 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1739 int vb
= velems
->binding
[i
];
1740 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1741 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1743 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1744 va
= radv_buffer_get_va(buffer
->bo
);
1746 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1747 va
+= offset
+ buffer
->offset
;
1749 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1750 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1751 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1753 desc
[2] = buffer
->size
- offset
;
1754 desc
[3] = velems
->rsrc_word3
[i
];
1757 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1760 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1761 AC_UD_VS_VERTEX_BUFFERS
, va
);
1763 cmd_buffer
->state
.vb_dirty
= false;
1769 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1770 bool instanced_draw
, bool indirect_draw
,
1771 uint32_t draw_vertex_count
)
1773 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1774 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1775 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1776 uint32_t ia_multi_vgt_param
;
1777 int32_t primitive_reset_en
;
1780 ia_multi_vgt_param
=
1781 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1782 indirect_draw
, draw_vertex_count
);
1784 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1785 if (info
->chip_class
>= GFX9
) {
1786 radeon_set_uconfig_reg_idx(cs
,
1787 R_030960_IA_MULTI_VGT_PARAM
,
1788 4, ia_multi_vgt_param
);
1789 } else if (info
->chip_class
>= CIK
) {
1790 radeon_set_context_reg_idx(cs
,
1791 R_028AA8_IA_MULTI_VGT_PARAM
,
1792 1, ia_multi_vgt_param
);
1794 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1795 ia_multi_vgt_param
);
1797 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1800 /* Primitive restart. */
1801 primitive_reset_en
=
1802 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1804 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1805 state
->last_primitive_reset_en
= primitive_reset_en
;
1806 if (info
->chip_class
>= GFX9
) {
1807 radeon_set_uconfig_reg(cs
,
1808 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1809 primitive_reset_en
);
1811 radeon_set_context_reg(cs
,
1812 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1813 primitive_reset_en
);
1817 if (primitive_reset_en
) {
1818 uint32_t primitive_reset_index
=
1819 state
->index_type
? 0xffffffffu
: 0xffffu
;
1821 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1822 radeon_set_context_reg(cs
,
1823 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1824 primitive_reset_index
);
1825 state
->last_primitive_reset_index
= primitive_reset_index
;
1830 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1831 VkPipelineStageFlags src_stage_mask
)
1833 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1834 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1835 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1836 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1837 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1840 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1841 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1842 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1843 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1844 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1845 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1846 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1847 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1848 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1849 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1850 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1851 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1852 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1853 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1854 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1855 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1856 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1860 static enum radv_cmd_flush_bits
1861 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1862 VkAccessFlags src_flags
)
1864 enum radv_cmd_flush_bits flush_bits
= 0;
1866 for_each_bit(b
, src_flags
) {
1867 switch ((VkAccessFlagBits
)(1 << b
)) {
1868 case VK_ACCESS_SHADER_WRITE_BIT
:
1869 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1871 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1872 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1873 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1875 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1876 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1877 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1879 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1880 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1881 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1882 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1883 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1884 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1893 static enum radv_cmd_flush_bits
1894 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1895 VkAccessFlags dst_flags
,
1896 struct radv_image
*image
)
1898 enum radv_cmd_flush_bits flush_bits
= 0;
1900 for_each_bit(b
, dst_flags
) {
1901 switch ((VkAccessFlagBits
)(1 << b
)) {
1902 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1903 case VK_ACCESS_INDEX_READ_BIT
:
1904 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1906 case VK_ACCESS_UNIFORM_READ_BIT
:
1907 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1909 case VK_ACCESS_SHADER_READ_BIT
:
1910 case VK_ACCESS_TRANSFER_READ_BIT
:
1911 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1912 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1913 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1915 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1916 /* TODO: change to image && when the image gets passed
1917 * through from the subpass. */
1918 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1919 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1920 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1922 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1923 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1924 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1925 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1934 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1936 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1937 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1938 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1942 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1943 VkAttachmentReference att
)
1945 unsigned idx
= att
.attachment
;
1946 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1947 VkImageSubresourceRange range
;
1948 range
.aspectMask
= 0;
1949 range
.baseMipLevel
= view
->base_mip
;
1950 range
.levelCount
= 1;
1951 range
.baseArrayLayer
= view
->base_layer
;
1952 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1954 radv_handle_image_transition(cmd_buffer
,
1956 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1957 att
.layout
, 0, 0, &range
,
1958 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1960 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1966 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1967 const struct radv_subpass
*subpass
, bool transitions
)
1970 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1972 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1973 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1974 radv_handle_subpass_image_transition(cmd_buffer
,
1975 subpass
->color_attachments
[i
]);
1978 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1979 radv_handle_subpass_image_transition(cmd_buffer
,
1980 subpass
->input_attachments
[i
]);
1983 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1984 radv_handle_subpass_image_transition(cmd_buffer
,
1985 subpass
->depth_stencil_attachment
);
1989 cmd_buffer
->state
.subpass
= subpass
;
1991 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
1995 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1996 struct radv_render_pass
*pass
,
1997 const VkRenderPassBeginInfo
*info
)
1999 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2001 if (pass
->attachment_count
== 0) {
2002 state
->attachments
= NULL
;
2006 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2007 pass
->attachment_count
*
2008 sizeof(state
->attachments
[0]),
2009 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2010 if (state
->attachments
== NULL
) {
2011 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2012 return cmd_buffer
->record_result
;
2015 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2016 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2017 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2018 VkImageAspectFlags clear_aspects
= 0;
2020 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2021 /* color attachment */
2022 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2023 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2026 /* depthstencil attachment */
2027 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2028 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2029 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2030 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2031 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2032 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2034 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2035 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2036 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2040 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2041 state
->attachments
[i
].cleared_views
= 0;
2042 if (clear_aspects
&& info
) {
2043 assert(info
->clearValueCount
> i
);
2044 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2047 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2053 VkResult
radv_AllocateCommandBuffers(
2055 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2056 VkCommandBuffer
*pCommandBuffers
)
2058 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2059 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2061 VkResult result
= VK_SUCCESS
;
2064 memset(pCommandBuffers
, 0,
2065 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
2067 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2069 if (!list_empty(&pool
->free_cmd_buffers
)) {
2070 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2072 list_del(&cmd_buffer
->pool_link
);
2073 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2075 result
= radv_reset_cmd_buffer(cmd_buffer
);
2076 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2077 cmd_buffer
->level
= pAllocateInfo
->level
;
2079 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2081 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2082 &pCommandBuffers
[i
]);
2084 if (result
!= VK_SUCCESS
)
2088 if (result
!= VK_SUCCESS
)
2089 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2090 i
, pCommandBuffers
);
2095 void radv_FreeCommandBuffers(
2097 VkCommandPool commandPool
,
2098 uint32_t commandBufferCount
,
2099 const VkCommandBuffer
*pCommandBuffers
)
2101 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2102 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2105 if (cmd_buffer
->pool
) {
2106 list_del(&cmd_buffer
->pool_link
);
2107 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2109 radv_cmd_buffer_destroy(cmd_buffer
);
2115 VkResult
radv_ResetCommandBuffer(
2116 VkCommandBuffer commandBuffer
,
2117 VkCommandBufferResetFlags flags
)
2119 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2120 return radv_reset_cmd_buffer(cmd_buffer
);
2123 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2125 struct radv_device
*device
= cmd_buffer
->device
;
2126 if (device
->gfx_init
) {
2127 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2128 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
2129 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2130 radeon_emit(cmd_buffer
->cs
, va
);
2131 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2132 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2134 si_init_config(cmd_buffer
);
2137 VkResult
radv_BeginCommandBuffer(
2138 VkCommandBuffer commandBuffer
,
2139 const VkCommandBufferBeginInfo
*pBeginInfo
)
2141 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2144 result
= radv_reset_cmd_buffer(cmd_buffer
);
2145 if (result
!= VK_SUCCESS
)
2148 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2149 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2150 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2152 /* setup initial configuration into command buffer */
2153 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2154 switch (cmd_buffer
->queue_family_index
) {
2155 case RADV_QUEUE_GENERAL
:
2156 emit_gfx_buffer_state(cmd_buffer
);
2158 case RADV_QUEUE_COMPUTE
:
2159 si_init_compute(cmd_buffer
);
2161 case RADV_QUEUE_TRANSFER
:
2167 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2168 assert(pBeginInfo
->pInheritanceInfo
);
2169 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2170 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2172 struct radv_subpass
*subpass
=
2173 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2175 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2176 if (result
!= VK_SUCCESS
)
2179 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2182 radv_cmd_buffer_trace_emit(cmd_buffer
);
2186 void radv_CmdBindVertexBuffers(
2187 VkCommandBuffer commandBuffer
,
2188 uint32_t firstBinding
,
2189 uint32_t bindingCount
,
2190 const VkBuffer
* pBuffers
,
2191 const VkDeviceSize
* pOffsets
)
2193 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2194 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2196 /* We have to defer setting up vertex buffer since we need the buffer
2197 * stride from the pipeline. */
2199 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2200 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2201 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2202 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2205 cmd_buffer
->state
.vb_dirty
= true;
2208 void radv_CmdBindIndexBuffer(
2209 VkCommandBuffer commandBuffer
,
2211 VkDeviceSize offset
,
2212 VkIndexType indexType
)
2214 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2215 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2217 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2218 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2219 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2221 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2222 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2223 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2224 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2228 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2229 struct radv_descriptor_set
*set
,
2232 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2234 cmd_buffer
->state
.descriptors
[idx
] = set
;
2235 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2239 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2241 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2242 if (set
->descriptors
[j
])
2243 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2246 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2249 void radv_CmdBindDescriptorSets(
2250 VkCommandBuffer commandBuffer
,
2251 VkPipelineBindPoint pipelineBindPoint
,
2252 VkPipelineLayout _layout
,
2254 uint32_t descriptorSetCount
,
2255 const VkDescriptorSet
* pDescriptorSets
,
2256 uint32_t dynamicOffsetCount
,
2257 const uint32_t* pDynamicOffsets
)
2259 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2260 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2261 unsigned dyn_idx
= 0;
2263 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2264 unsigned idx
= i
+ firstSet
;
2265 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2266 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2268 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2269 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2270 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2271 assert(dyn_idx
< dynamicOffsetCount
);
2273 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2274 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2276 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2277 dst
[2] = range
->size
;
2278 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2279 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2280 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2281 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2282 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2284 cmd_buffer
->push_constant_stages
|=
2285 set
->layout
->dynamic_shader_stages
;
2290 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2291 struct radv_descriptor_set
*set
,
2292 struct radv_descriptor_set_layout
*layout
)
2294 set
->size
= layout
->size
;
2295 set
->layout
= layout
;
2297 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2298 size_t new_size
= MAX2(set
->size
, 1024);
2299 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2300 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2302 free(set
->mapped_ptr
);
2303 set
->mapped_ptr
= malloc(new_size
);
2305 if (!set
->mapped_ptr
) {
2306 cmd_buffer
->push_descriptors
.capacity
= 0;
2307 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2311 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2317 void radv_meta_push_descriptor_set(
2318 struct radv_cmd_buffer
* cmd_buffer
,
2319 VkPipelineBindPoint pipelineBindPoint
,
2320 VkPipelineLayout _layout
,
2322 uint32_t descriptorWriteCount
,
2323 const VkWriteDescriptorSet
* pDescriptorWrites
)
2325 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2326 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2330 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2332 push_set
->size
= layout
->set
[set
].layout
->size
;
2333 push_set
->layout
= layout
->set
[set
].layout
;
2335 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2337 (void**) &push_set
->mapped_ptr
))
2340 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2341 push_set
->va
+= bo_offset
;
2343 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2344 radv_descriptor_set_to_handle(push_set
),
2345 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2347 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2348 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2351 void radv_CmdPushDescriptorSetKHR(
2352 VkCommandBuffer commandBuffer
,
2353 VkPipelineBindPoint pipelineBindPoint
,
2354 VkPipelineLayout _layout
,
2356 uint32_t descriptorWriteCount
,
2357 const VkWriteDescriptorSet
* pDescriptorWrites
)
2359 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2360 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2361 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2363 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2365 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2368 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2369 radv_descriptor_set_to_handle(push_set
),
2370 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2372 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2373 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2374 cmd_buffer
->state
.push_descriptors_dirty
= true;
2377 void radv_CmdPushDescriptorSetWithTemplateKHR(
2378 VkCommandBuffer commandBuffer
,
2379 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2380 VkPipelineLayout _layout
,
2384 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2385 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2386 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2388 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2390 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2393 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2394 descriptorUpdateTemplate
, pData
);
2396 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2397 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2398 cmd_buffer
->state
.push_descriptors_dirty
= true;
2401 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2402 VkPipelineLayout layout
,
2403 VkShaderStageFlags stageFlags
,
2406 const void* pValues
)
2408 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2409 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2410 cmd_buffer
->push_constant_stages
|= stageFlags
;
2413 VkResult
radv_EndCommandBuffer(
2414 VkCommandBuffer commandBuffer
)
2416 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2418 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2419 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2420 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2421 si_emit_cache_flush(cmd_buffer
);
2424 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2425 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2427 return cmd_buffer
->record_result
;
2431 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2433 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2434 struct radv_shader_variant
*compute_shader
;
2435 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2438 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2441 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2443 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2444 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2446 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2447 radv_emit_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2449 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2450 cmd_buffer
->cs
, 16);
2452 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2453 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2454 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2456 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2457 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2458 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2461 cmd_buffer
->compute_scratch_size_needed
=
2462 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2463 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2465 /* change these once we have scratch support */
2466 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2467 S_00B860_WAVES(pipeline
->max_waves
) |
2468 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2470 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2471 radeon_emit(cmd_buffer
->cs
,
2472 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2473 radeon_emit(cmd_buffer
->cs
,
2474 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2475 radeon_emit(cmd_buffer
->cs
,
2476 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2478 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2479 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2482 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2484 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2485 if (cmd_buffer
->state
.descriptors
[i
])
2486 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2490 void radv_CmdBindPipeline(
2491 VkCommandBuffer commandBuffer
,
2492 VkPipelineBindPoint pipelineBindPoint
,
2493 VkPipeline _pipeline
)
2495 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2496 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2498 switch (pipelineBindPoint
) {
2499 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2500 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2502 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2504 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2505 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2507 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2508 if (cmd_buffer
->state
.pipeline
== pipeline
)
2510 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2512 cmd_buffer
->state
.pipeline
= pipeline
;
2516 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2517 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2519 /* Apply the dynamic state from the pipeline */
2520 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2521 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2522 &pipeline
->dynamic_state
,
2523 pipeline
->dynamic_state_mask
);
2525 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2526 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2527 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2528 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2530 if (radv_pipeline_has_tess(pipeline
))
2531 cmd_buffer
->tess_rings_needed
= true;
2533 if (radv_pipeline_has_gs(pipeline
)) {
2534 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2535 AC_UD_SCRATCH_RING_OFFSETS
);
2536 if (cmd_buffer
->ring_offsets_idx
== -1)
2537 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2538 else if (loc
->sgpr_idx
!= -1)
2539 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2543 assert(!"invalid bind point");
2548 void radv_CmdSetViewport(
2549 VkCommandBuffer commandBuffer
,
2550 uint32_t firstViewport
,
2551 uint32_t viewportCount
,
2552 const VkViewport
* pViewports
)
2554 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2555 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2557 assert(firstViewport
< MAX_VIEWPORTS
);
2558 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2560 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2561 pViewports
, viewportCount
* sizeof(*pViewports
));
2563 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2566 void radv_CmdSetScissor(
2567 VkCommandBuffer commandBuffer
,
2568 uint32_t firstScissor
,
2569 uint32_t scissorCount
,
2570 const VkRect2D
* pScissors
)
2572 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2573 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2575 assert(firstScissor
< MAX_SCISSORS
);
2576 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2578 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2579 pScissors
, scissorCount
* sizeof(*pScissors
));
2580 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2583 void radv_CmdSetLineWidth(
2584 VkCommandBuffer commandBuffer
,
2587 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2588 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2589 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2592 void radv_CmdSetDepthBias(
2593 VkCommandBuffer commandBuffer
,
2594 float depthBiasConstantFactor
,
2595 float depthBiasClamp
,
2596 float depthBiasSlopeFactor
)
2598 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2600 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2601 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2602 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2604 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2607 void radv_CmdSetBlendConstants(
2608 VkCommandBuffer commandBuffer
,
2609 const float blendConstants
[4])
2611 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2613 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2614 blendConstants
, sizeof(float) * 4);
2616 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2619 void radv_CmdSetDepthBounds(
2620 VkCommandBuffer commandBuffer
,
2621 float minDepthBounds
,
2622 float maxDepthBounds
)
2624 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2626 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2627 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2629 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2632 void radv_CmdSetStencilCompareMask(
2633 VkCommandBuffer commandBuffer
,
2634 VkStencilFaceFlags faceMask
,
2635 uint32_t compareMask
)
2637 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2639 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2640 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2641 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2642 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2644 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2647 void radv_CmdSetStencilWriteMask(
2648 VkCommandBuffer commandBuffer
,
2649 VkStencilFaceFlags faceMask
,
2652 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2654 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2655 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2656 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2657 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2659 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2662 void radv_CmdSetStencilReference(
2663 VkCommandBuffer commandBuffer
,
2664 VkStencilFaceFlags faceMask
,
2667 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2669 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2670 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2671 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2672 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2674 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2677 void radv_CmdExecuteCommands(
2678 VkCommandBuffer commandBuffer
,
2679 uint32_t commandBufferCount
,
2680 const VkCommandBuffer
* pCmdBuffers
)
2682 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2684 assert(commandBufferCount
> 0);
2686 /* Emit pending flushes on primary prior to executing secondary */
2687 si_emit_cache_flush(primary
);
2689 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2690 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2692 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2693 secondary
->scratch_size_needed
);
2694 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2695 secondary
->compute_scratch_size_needed
);
2697 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2698 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2699 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2700 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2701 if (secondary
->tess_rings_needed
)
2702 primary
->tess_rings_needed
= true;
2703 if (secondary
->sample_positions_needed
)
2704 primary
->sample_positions_needed
= true;
2706 if (secondary
->ring_offsets_idx
!= -1) {
2707 if (primary
->ring_offsets_idx
== -1)
2708 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2710 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2712 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2715 /* When the secondary command buffer is compute only we don't
2716 * need to re-emit the current graphics pipeline.
2718 if (secondary
->state
.emitted_pipeline
) {
2719 primary
->state
.emitted_pipeline
=
2720 secondary
->state
.emitted_pipeline
;
2723 /* When the secondary command buffer is graphics only we don't
2724 * need to re-emit the current compute pipeline.
2726 if (secondary
->state
.emitted_compute_pipeline
) {
2727 primary
->state
.emitted_compute_pipeline
=
2728 secondary
->state
.emitted_compute_pipeline
;
2731 /* Only re-emit the draw packets when needed. */
2732 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2733 primary
->state
.last_primitive_reset_en
=
2734 secondary
->state
.last_primitive_reset_en
;
2737 if (secondary
->state
.last_primitive_reset_index
) {
2738 primary
->state
.last_primitive_reset_index
=
2739 secondary
->state
.last_primitive_reset_index
;
2742 if (secondary
->state
.last_ia_multi_vgt_param
) {
2743 primary
->state
.last_ia_multi_vgt_param
=
2744 secondary
->state
.last_ia_multi_vgt_param
;
2748 /* After executing commands from secondary buffers we have to dirty
2751 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2752 RADV_CMD_DIRTY_INDEX_BUFFER
|
2753 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2754 radv_mark_descriptor_sets_dirty(primary
);
2757 VkResult
radv_CreateCommandPool(
2759 const VkCommandPoolCreateInfo
* pCreateInfo
,
2760 const VkAllocationCallbacks
* pAllocator
,
2761 VkCommandPool
* pCmdPool
)
2763 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2764 struct radv_cmd_pool
*pool
;
2766 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2767 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2769 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2772 pool
->alloc
= *pAllocator
;
2774 pool
->alloc
= device
->alloc
;
2776 list_inithead(&pool
->cmd_buffers
);
2777 list_inithead(&pool
->free_cmd_buffers
);
2779 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2781 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2787 void radv_DestroyCommandPool(
2789 VkCommandPool commandPool
,
2790 const VkAllocationCallbacks
* pAllocator
)
2792 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2793 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2798 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2799 &pool
->cmd_buffers
, pool_link
) {
2800 radv_cmd_buffer_destroy(cmd_buffer
);
2803 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2804 &pool
->free_cmd_buffers
, pool_link
) {
2805 radv_cmd_buffer_destroy(cmd_buffer
);
2808 vk_free2(&device
->alloc
, pAllocator
, pool
);
2811 VkResult
radv_ResetCommandPool(
2813 VkCommandPool commandPool
,
2814 VkCommandPoolResetFlags flags
)
2816 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2819 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2820 &pool
->cmd_buffers
, pool_link
) {
2821 result
= radv_reset_cmd_buffer(cmd_buffer
);
2822 if (result
!= VK_SUCCESS
)
2829 void radv_TrimCommandPoolKHR(
2831 VkCommandPool commandPool
,
2832 VkCommandPoolTrimFlagsKHR flags
)
2834 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2839 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2840 &pool
->free_cmd_buffers
, pool_link
) {
2841 radv_cmd_buffer_destroy(cmd_buffer
);
2845 void radv_CmdBeginRenderPass(
2846 VkCommandBuffer commandBuffer
,
2847 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2848 VkSubpassContents contents
)
2850 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2851 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2852 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2854 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2855 cmd_buffer
->cs
, 2048);
2856 MAYBE_UNUSED VkResult result
;
2858 cmd_buffer
->state
.framebuffer
= framebuffer
;
2859 cmd_buffer
->state
.pass
= pass
;
2860 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2862 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2863 if (result
!= VK_SUCCESS
)
2866 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2867 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2869 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2872 void radv_CmdNextSubpass(
2873 VkCommandBuffer commandBuffer
,
2874 VkSubpassContents contents
)
2876 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2878 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2880 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2883 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2884 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2887 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2889 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2890 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2891 if (!pipeline
->shaders
[stage
])
2893 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2894 if (loc
->sgpr_idx
== -1)
2896 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2897 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2900 if (pipeline
->gs_copy_shader
) {
2901 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2902 if (loc
->sgpr_idx
!= -1) {
2903 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2904 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2910 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2911 uint32_t vertex_count
)
2913 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2914 radeon_emit(cmd_buffer
->cs
, vertex_count
);
2915 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2916 S_0287F0_USE_OPAQUE(0));
2920 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
2922 uint32_t index_count
)
2924 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2925 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2926 radeon_emit(cmd_buffer
->cs
, index_va
);
2927 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
2928 radeon_emit(cmd_buffer
->cs
, index_count
);
2929 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2933 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2935 uint32_t draw_count
,
2939 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2940 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2941 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2942 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2943 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
2946 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
2947 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
2948 PKT3_DRAW_INDIRECT
, 3, false));
2950 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2951 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2952 radeon_emit(cs
, di_src_sel
);
2954 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2955 PKT3_DRAW_INDIRECT_MULTI
,
2958 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2959 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2960 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
2961 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2962 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2963 radeon_emit(cs
, draw_count
); /* count */
2964 radeon_emit(cs
, count_va
); /* count_addr */
2965 radeon_emit(cs
, count_va
>> 32);
2966 radeon_emit(cs
, stride
); /* stride */
2967 radeon_emit(cs
, di_src_sel
);
2971 struct radv_draw_info
{
2973 * Number of vertices.
2978 * Index of the first vertex.
2980 int32_t vertex_offset
;
2983 * First instance id.
2985 uint32_t first_instance
;
2988 * Number of instances.
2990 uint32_t instance_count
;
2993 * First index (indexed draws only).
2995 uint32_t first_index
;
2998 * Whether it's an indexed draw.
3003 * Indirect draw parameters resource.
3005 struct radv_buffer
*indirect
;
3006 uint64_t indirect_offset
;
3010 * Draw count parameters resource.
3012 struct radv_buffer
*count_buffer
;
3013 uint64_t count_buffer_offset
;
3017 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3018 const struct radv_draw_info
*info
)
3020 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3021 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3022 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3024 if (info
->indirect
) {
3025 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3026 uint64_t count_va
= 0;
3028 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3030 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3032 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3034 radeon_emit(cs
, va
);
3035 radeon_emit(cs
, va
>> 32);
3037 if (info
->count_buffer
) {
3038 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3039 count_va
+= info
->count_buffer
->offset
+
3040 info
->count_buffer_offset
;
3042 ws
->cs_add_buffer(cs
, info
->count_buffer
->bo
, 8);
3045 if (!state
->subpass
->view_mask
) {
3046 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3053 for_each_bit(i
, state
->subpass
->view_mask
) {
3054 radv_emit_view_index(cmd_buffer
, i
);
3056 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3064 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3065 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3066 state
->pipeline
->graphics
.vtx_emit_num
);
3067 radeon_emit(cs
, info
->vertex_offset
);
3068 radeon_emit(cs
, info
->first_instance
);
3069 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3072 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, state
->predicating
));
3073 radeon_emit(cs
, info
->instance_count
);
3075 if (info
->indexed
) {
3076 int index_size
= state
->index_type
? 4 : 2;
3079 index_va
= state
->index_va
;
3080 index_va
+= info
->first_index
* index_size
;
3082 if (!state
->subpass
->view_mask
) {
3083 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3088 for_each_bit(i
, state
->subpass
->view_mask
) {
3089 radv_emit_view_index(cmd_buffer
, i
);
3091 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3097 if (!state
->subpass
->view_mask
) {
3098 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3101 for_each_bit(i
, state
->subpass
->view_mask
) {
3102 radv_emit_view_index(cmd_buffer
, i
);
3104 radv_cs_emit_draw_packet(cmd_buffer
,
3113 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3114 const struct radv_draw_info
*info
)
3116 MAYBE_UNUSED
unsigned cdw_max
=
3117 radeon_check_space(cmd_buffer
->device
->ws
,
3118 cmd_buffer
->cs
, 4096);
3120 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
))
3123 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3124 radv_emit_graphics_pipeline(cmd_buffer
);
3126 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3127 radv_emit_framebuffer_state(cmd_buffer
);
3129 if (info
->indexed
) {
3130 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3131 radv_emit_index_buffer(cmd_buffer
);
3133 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3134 * so the state must be re-emitted before the next indexed
3137 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
3138 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3141 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3142 info
->instance_count
> 1, info
->indirect
,
3143 info
->indirect
? 0 : info
->count
);
3145 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3147 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
3148 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
3149 VK_SHADER_STAGE_ALL_GRAPHICS
);
3151 si_emit_cache_flush(cmd_buffer
);
3153 radv_emit_draw_packets(cmd_buffer
, info
);
3155 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3156 radv_cmd_buffer_after_draw(cmd_buffer
);
3160 VkCommandBuffer commandBuffer
,
3161 uint32_t vertexCount
,
3162 uint32_t instanceCount
,
3163 uint32_t firstVertex
,
3164 uint32_t firstInstance
)
3166 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3167 struct radv_draw_info info
= {};
3169 info
.count
= vertexCount
;
3170 info
.instance_count
= instanceCount
;
3171 info
.first_instance
= firstInstance
;
3172 info
.vertex_offset
= firstVertex
;
3174 radv_draw(cmd_buffer
, &info
);
3177 void radv_CmdDrawIndexed(
3178 VkCommandBuffer commandBuffer
,
3179 uint32_t indexCount
,
3180 uint32_t instanceCount
,
3181 uint32_t firstIndex
,
3182 int32_t vertexOffset
,
3183 uint32_t firstInstance
)
3185 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3186 struct radv_draw_info info
= {};
3188 info
.indexed
= true;
3189 info
.count
= indexCount
;
3190 info
.instance_count
= instanceCount
;
3191 info
.first_index
= firstIndex
;
3192 info
.vertex_offset
= vertexOffset
;
3193 info
.first_instance
= firstInstance
;
3195 radv_draw(cmd_buffer
, &info
);
3198 void radv_CmdDrawIndirect(
3199 VkCommandBuffer commandBuffer
,
3201 VkDeviceSize offset
,
3205 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3206 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3207 struct radv_draw_info info
= {};
3209 info
.count
= drawCount
;
3210 info
.indirect
= buffer
;
3211 info
.indirect_offset
= offset
;
3212 info
.stride
= stride
;
3214 radv_draw(cmd_buffer
, &info
);
3217 void radv_CmdDrawIndexedIndirect(
3218 VkCommandBuffer commandBuffer
,
3220 VkDeviceSize offset
,
3224 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3225 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3226 struct radv_draw_info info
= {};
3228 info
.indexed
= true;
3229 info
.count
= drawCount
;
3230 info
.indirect
= buffer
;
3231 info
.indirect_offset
= offset
;
3232 info
.stride
= stride
;
3234 radv_draw(cmd_buffer
, &info
);
3237 void radv_CmdDrawIndirectCountAMD(
3238 VkCommandBuffer commandBuffer
,
3240 VkDeviceSize offset
,
3241 VkBuffer _countBuffer
,
3242 VkDeviceSize countBufferOffset
,
3243 uint32_t maxDrawCount
,
3246 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3247 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3248 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3249 struct radv_draw_info info
= {};
3251 info
.count
= maxDrawCount
;
3252 info
.indirect
= buffer
;
3253 info
.indirect_offset
= offset
;
3254 info
.count_buffer
= count_buffer
;
3255 info
.count_buffer_offset
= countBufferOffset
;
3256 info
.stride
= stride
;
3258 radv_draw(cmd_buffer
, &info
);
3261 void radv_CmdDrawIndexedIndirectCountAMD(
3262 VkCommandBuffer commandBuffer
,
3264 VkDeviceSize offset
,
3265 VkBuffer _countBuffer
,
3266 VkDeviceSize countBufferOffset
,
3267 uint32_t maxDrawCount
,
3270 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3271 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3272 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3273 struct radv_draw_info info
= {};
3275 info
.indexed
= true;
3276 info
.count
= maxDrawCount
;
3277 info
.indirect
= buffer
;
3278 info
.indirect_offset
= offset
;
3279 info
.count_buffer
= count_buffer
;
3280 info
.count_buffer_offset
= countBufferOffset
;
3281 info
.stride
= stride
;
3283 radv_draw(cmd_buffer
, &info
);
3286 struct radv_dispatch_info
{
3288 * Determine the layout of the grid (in block units) to be used.
3293 * Whether it's an unaligned compute dispatch.
3298 * Indirect compute parameters resource.
3300 struct radv_buffer
*indirect
;
3301 uint64_t indirect_offset
;
3305 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3306 const struct radv_dispatch_info
*info
)
3308 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3309 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3310 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3311 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3312 struct ac_userdata_info
*loc
;
3313 unsigned dispatch_initiator
;
3316 grid_used
= compute_shader
->info
.info
.cs
.grid_components_used
;
3318 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3319 AC_UD_CS_GRID_SIZE
);
3321 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3323 dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
3324 S_00B800_FORCE_START_AT_000(1);
3326 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3327 /* If the KMD allows it (there is a KMD hw register for it),
3328 * allow launching waves out-of-order.
3330 dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3333 if (info
->indirect
) {
3334 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3336 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3338 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3340 if (loc
->sgpr_idx
!= -1) {
3341 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3342 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3343 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3344 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3345 radeon_emit(cs
, (va
+ 4 * i
));
3346 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3347 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3348 + loc
->sgpr_idx
* 4) >> 2) + i
);
3353 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3354 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3355 PKT3_SHADER_TYPE_S(1));
3356 radeon_emit(cs
, va
);
3357 radeon_emit(cs
, va
>> 32);
3358 radeon_emit(cs
, dispatch_initiator
);
3360 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3361 PKT3_SHADER_TYPE_S(1));
3363 radeon_emit(cs
, va
);
3364 radeon_emit(cs
, va
>> 32);
3366 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3367 PKT3_SHADER_TYPE_S(1));
3369 radeon_emit(cs
, dispatch_initiator
);
3372 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3374 if (info
->unaligned
) {
3375 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3376 unsigned remainder
[3];
3378 /* If aligned, these should be an entire block size,
3381 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3382 align_u32_npot(blocks
[0], cs_block_size
[0]);
3383 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3384 align_u32_npot(blocks
[1], cs_block_size
[1]);
3385 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3386 align_u32_npot(blocks
[2], cs_block_size
[2]);
3388 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3389 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3390 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3392 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3394 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3395 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3397 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3398 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3400 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3401 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3403 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3406 if (loc
->sgpr_idx
!= -1) {
3407 assert(!loc
->indirect
);
3408 assert(loc
->num_sgprs
== grid_used
);
3410 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3411 loc
->sgpr_idx
* 4, grid_used
);
3412 radeon_emit(cs
, blocks
[0]);
3414 radeon_emit(cs
, blocks
[1]);
3416 radeon_emit(cs
, blocks
[2]);
3419 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3420 PKT3_SHADER_TYPE_S(1));
3421 radeon_emit(cs
, blocks
[0]);
3422 radeon_emit(cs
, blocks
[1]);
3423 radeon_emit(cs
, blocks
[2]);
3424 radeon_emit(cs
, dispatch_initiator
);
3427 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3431 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3432 const struct radv_dispatch_info
*info
)
3434 radv_emit_compute_pipeline(cmd_buffer
);
3436 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3437 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3438 VK_SHADER_STAGE_COMPUTE_BIT
);
3440 si_emit_cache_flush(cmd_buffer
);
3442 radv_emit_dispatch_packets(cmd_buffer
, info
);
3444 radv_cmd_buffer_after_draw(cmd_buffer
);
3447 void radv_CmdDispatch(
3448 VkCommandBuffer commandBuffer
,
3453 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3454 struct radv_dispatch_info info
= {};
3460 radv_dispatch(cmd_buffer
, &info
);
3463 void radv_CmdDispatchIndirect(
3464 VkCommandBuffer commandBuffer
,
3466 VkDeviceSize offset
)
3468 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3469 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3470 struct radv_dispatch_info info
= {};
3472 info
.indirect
= buffer
;
3473 info
.indirect_offset
= offset
;
3475 radv_dispatch(cmd_buffer
, &info
);
3478 void radv_unaligned_dispatch(
3479 struct radv_cmd_buffer
*cmd_buffer
,
3484 struct radv_dispatch_info info
= {};
3491 radv_dispatch(cmd_buffer
, &info
);
3494 void radv_CmdEndRenderPass(
3495 VkCommandBuffer commandBuffer
)
3497 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3499 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3501 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3503 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3504 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3505 radv_handle_subpass_image_transition(cmd_buffer
,
3506 (VkAttachmentReference
){i
, layout
});
3509 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3511 cmd_buffer
->state
.pass
= NULL
;
3512 cmd_buffer
->state
.subpass
= NULL
;
3513 cmd_buffer
->state
.attachments
= NULL
;
3514 cmd_buffer
->state
.framebuffer
= NULL
;
3518 * For HTILE we have the following interesting clear words:
3519 * 0x0000030f: Uncompressed.
3520 * 0xfffffff0: Clear depth to 1.0
3521 * 0x00000000: Clear depth to 0.0
3523 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3524 struct radv_image
*image
,
3525 const VkImageSubresourceRange
*range
,
3526 uint32_t clear_word
)
3528 assert(range
->baseMipLevel
== 0);
3529 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3530 unsigned layer_count
= radv_get_layerCount(image
, range
);
3531 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3532 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3533 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3535 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3536 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3538 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3540 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3541 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3542 RADV_CMD_FLAG_INV_VMEM_L1
|
3543 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3546 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3547 struct radv_image
*image
,
3548 VkImageLayout src_layout
,
3549 VkImageLayout dst_layout
,
3550 unsigned src_queue_mask
,
3551 unsigned dst_queue_mask
,
3552 const VkImageSubresourceRange
*range
,
3553 VkImageAspectFlags pending_clears
)
3555 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3556 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3557 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3558 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3559 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3560 /* The clear will initialize htile. */
3562 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3563 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3564 /* TODO: merge with the clear if applicable */
3565 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3566 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3567 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3568 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3569 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3570 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3571 VkImageSubresourceRange local_range
= *range
;
3572 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3573 local_range
.baseMipLevel
= 0;
3574 local_range
.levelCount
= 1;
3576 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3577 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3579 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3581 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3582 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3586 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3587 struct radv_image
*image
, uint32_t value
)
3589 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3590 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3592 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3593 image
->cmask
.size
, value
);
3595 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3596 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3597 RADV_CMD_FLAG_INV_VMEM_L1
|
3598 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3601 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3602 struct radv_image
*image
,
3603 VkImageLayout src_layout
,
3604 VkImageLayout dst_layout
,
3605 unsigned src_queue_mask
,
3606 unsigned dst_queue_mask
,
3607 const VkImageSubresourceRange
*range
)
3609 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3610 if (image
->fmask
.size
)
3611 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3613 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3614 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3615 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3616 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3620 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3621 struct radv_image
*image
, uint32_t value
)
3624 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3625 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3627 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3628 image
->surface
.dcc_size
, value
);
3630 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3631 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3632 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3633 RADV_CMD_FLAG_INV_VMEM_L1
|
3634 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3637 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3638 struct radv_image
*image
,
3639 VkImageLayout src_layout
,
3640 VkImageLayout dst_layout
,
3641 unsigned src_queue_mask
,
3642 unsigned dst_queue_mask
,
3643 const VkImageSubresourceRange
*range
)
3645 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3646 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3647 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3648 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3649 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3653 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3654 struct radv_image
*image
,
3655 VkImageLayout src_layout
,
3656 VkImageLayout dst_layout
,
3657 uint32_t src_family
,
3658 uint32_t dst_family
,
3659 const VkImageSubresourceRange
*range
,
3660 VkImageAspectFlags pending_clears
)
3662 if (image
->exclusive
&& src_family
!= dst_family
) {
3663 /* This is an acquire or a release operation and there will be
3664 * a corresponding release/acquire. Do the transition in the
3665 * most flexible queue. */
3667 assert(src_family
== cmd_buffer
->queue_family_index
||
3668 dst_family
== cmd_buffer
->queue_family_index
);
3670 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3673 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3674 (src_family
== RADV_QUEUE_GENERAL
||
3675 dst_family
== RADV_QUEUE_GENERAL
))
3679 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3680 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3682 if (image
->surface
.htile_size
)
3683 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3684 dst_layout
, src_queue_mask
,
3685 dst_queue_mask
, range
,
3688 if (image
->cmask
.size
|| image
->fmask
.size
)
3689 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3690 dst_layout
, src_queue_mask
,
3691 dst_queue_mask
, range
);
3693 if (image
->surface
.dcc_size
)
3694 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3695 dst_layout
, src_queue_mask
,
3696 dst_queue_mask
, range
);
3699 void radv_CmdPipelineBarrier(
3700 VkCommandBuffer commandBuffer
,
3701 VkPipelineStageFlags srcStageMask
,
3702 VkPipelineStageFlags destStageMask
,
3704 uint32_t memoryBarrierCount
,
3705 const VkMemoryBarrier
* pMemoryBarriers
,
3706 uint32_t bufferMemoryBarrierCount
,
3707 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3708 uint32_t imageMemoryBarrierCount
,
3709 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3711 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3712 enum radv_cmd_flush_bits src_flush_bits
= 0;
3713 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3715 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3716 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3717 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3721 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3722 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3723 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3727 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3728 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3729 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3730 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3734 radv_stage_flush(cmd_buffer
, srcStageMask
);
3735 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3737 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3738 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3739 radv_handle_image_transition(cmd_buffer
, image
,
3740 pImageMemoryBarriers
[i
].oldLayout
,
3741 pImageMemoryBarriers
[i
].newLayout
,
3742 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3743 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3744 &pImageMemoryBarriers
[i
].subresourceRange
,
3748 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3752 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3753 struct radv_event
*event
,
3754 VkPipelineStageFlags stageMask
,
3757 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3758 uint64_t va
= radv_buffer_get_va(event
->bo
);
3760 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3762 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3764 /* TODO: this is overkill. Probably should figure something out from
3765 * the stage mask. */
3767 si_cs_emit_write_event_eop(cs
,
3768 cmd_buffer
->state
.predicating
,
3769 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3771 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
3774 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3777 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3779 VkPipelineStageFlags stageMask
)
3781 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3782 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3784 write_event(cmd_buffer
, event
, stageMask
, 1);
3787 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3789 VkPipelineStageFlags stageMask
)
3791 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3792 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3794 write_event(cmd_buffer
, event
, stageMask
, 0);
3797 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3798 uint32_t eventCount
,
3799 const VkEvent
* pEvents
,
3800 VkPipelineStageFlags srcStageMask
,
3801 VkPipelineStageFlags dstStageMask
,
3802 uint32_t memoryBarrierCount
,
3803 const VkMemoryBarrier
* pMemoryBarriers
,
3804 uint32_t bufferMemoryBarrierCount
,
3805 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3806 uint32_t imageMemoryBarrierCount
,
3807 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3809 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3810 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3812 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3813 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3814 uint64_t va
= radv_buffer_get_va(event
->bo
);
3816 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3818 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3820 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3821 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3825 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3826 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3828 radv_handle_image_transition(cmd_buffer
, image
,
3829 pImageMemoryBarriers
[i
].oldLayout
,
3830 pImageMemoryBarriers
[i
].newLayout
,
3831 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3832 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3833 &pImageMemoryBarriers
[i
].subresourceRange
,
3837 /* TODO: figure out how to do memory barriers without waiting */
3838 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3839 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3840 RADV_CMD_FLAG_INV_VMEM_L1
|
3841 RADV_CMD_FLAG_INV_SMEM_L1
;