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2df43ab15e4341c09b63f50568451836ceab9373
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uintptr_t)set;
588 data[i * 2 + 1] = (uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image *image,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249
1250 if (!radv_layout_dcc_compressed(image, layout,
1251 radv_image_queue_family_mask(image,
1252 cmd_buffer->queue_family_index,
1253 cmd_buffer->queue_family_index))) {
1254 cb_color_info &= C_028C70_DCC_ENABLE;
1255 }
1256
1257 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1259 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1260 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1261 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1262 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1263 radeon_emit(cmd_buffer->cs, cb_color_info);
1264 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1265 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1266 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1267 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1268 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1269 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1270
1271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1272 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1273 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1274
1275 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1276 cb->cb_mrt_epitch);
1277 } else {
1278 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1282 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1283 radeon_emit(cmd_buffer->cs, cb_color_info);
1284 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1285 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1286 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1288 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1290
1291 if (is_vi) { /* DCC BASE */
1292 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1293 }
1294 }
1295
1296 if (radv_image_has_dcc(image)) {
1297 /* Drawing with DCC enabled also compresses colorbuffers. */
1298 radv_update_dcc_metadata(cmd_buffer, image, true);
1299 }
1300 }
1301
1302 static void
1303 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1304 struct radv_ds_buffer_info *ds,
1305 struct radv_image *image, VkImageLayout layout,
1306 bool requires_cond_exec)
1307 {
1308 uint32_t db_z_info = ds->db_z_info;
1309 uint32_t db_z_info_reg;
1310
1311 if (!radv_image_is_tc_compat_htile(image))
1312 return;
1313
1314 if (!radv_layout_has_htile(image, layout,
1315 radv_image_queue_family_mask(image,
1316 cmd_buffer->queue_family_index,
1317 cmd_buffer->queue_family_index))) {
1318 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1319 }
1320
1321 db_z_info &= C_028040_ZRANGE_PRECISION;
1322
1323 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1324 db_z_info_reg = R_028038_DB_Z_INFO;
1325 } else {
1326 db_z_info_reg = R_028040_DB_Z_INFO;
1327 }
1328
1329 /* When we don't know the last fast clear value we need to emit a
1330 * conditional packet that will eventually skip the following
1331 * SET_CONTEXT_REG packet.
1332 */
1333 if (requires_cond_exec) {
1334 uint64_t va = radv_buffer_get_va(image->bo);
1335 va += image->offset + image->tc_compat_zrange_offset;
1336
1337 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1338 radeon_emit(cmd_buffer->cs, va);
1339 radeon_emit(cmd_buffer->cs, va >> 32);
1340 radeon_emit(cmd_buffer->cs, 0);
1341 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1342 }
1343
1344 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1345 }
1346
1347 static void
1348 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1349 struct radv_ds_buffer_info *ds,
1350 struct radv_image *image,
1351 VkImageLayout layout)
1352 {
1353 uint32_t db_z_info = ds->db_z_info;
1354 uint32_t db_stencil_info = ds->db_stencil_info;
1355
1356 if (!radv_layout_has_htile(image, layout,
1357 radv_image_queue_family_mask(image,
1358 cmd_buffer->queue_family_index,
1359 cmd_buffer->queue_family_index))) {
1360 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1361 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1362 }
1363
1364 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1365 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1366
1367
1368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1369 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1370 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1371 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1372 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1373
1374 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1375 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1376 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1377 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1378 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1379 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1380 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1381 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1382 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1383 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1384 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1385
1386 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1387 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1388 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1389 } else {
1390 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1391
1392 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1393 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1394 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1395 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1396 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1398 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1399 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1400 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1401 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1402
1403 }
1404
1405 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1406 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1407
1408 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1409 ds->pa_su_poly_offset_db_fmt_cntl);
1410 }
1411
1412 /**
1413 * Update the fast clear depth/stencil values if the image is bound as a
1414 * depth/stencil buffer.
1415 */
1416 static void
1417 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1418 struct radv_image *image,
1419 VkClearDepthStencilValue ds_clear_value,
1420 VkImageAspectFlags aspects)
1421 {
1422 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1423 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1424 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1425 struct radv_attachment_info *att;
1426 uint32_t att_idx;
1427
1428 if (!framebuffer || !subpass)
1429 return;
1430
1431 if (!subpass->depth_stencil_attachment)
1432 return;
1433
1434 att_idx = subpass->depth_stencil_attachment->attachment;
1435 att = &framebuffer->attachments[att_idx];
1436 if (att->attachment->image != image)
1437 return;
1438
1439 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1440 radeon_emit(cs, ds_clear_value.stencil);
1441 radeon_emit(cs, fui(ds_clear_value.depth));
1442
1443 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1444 * only needed when clearing Z to 0.0.
1445 */
1446 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1447 ds_clear_value.depth == 0.0) {
1448 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1449
1450 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1451 layout, false);
1452 }
1453
1454 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1455 }
1456
1457 /**
1458 * Set the clear depth/stencil values to the image's metadata.
1459 */
1460 static void
1461 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1462 struct radv_image *image,
1463 VkClearDepthStencilValue ds_clear_value,
1464 VkImageAspectFlags aspects)
1465 {
1466 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1467 uint64_t va = radv_buffer_get_va(image->bo);
1468 unsigned reg_offset = 0, reg_count = 0;
1469
1470 va += image->offset + image->clear_value_offset;
1471
1472 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1473 ++reg_count;
1474 } else {
1475 ++reg_offset;
1476 va += 4;
1477 }
1478 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1479 ++reg_count;
1480
1481 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1482 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1483 S_370_WR_CONFIRM(1) |
1484 S_370_ENGINE_SEL(V_370_PFP));
1485 radeon_emit(cs, va);
1486 radeon_emit(cs, va >> 32);
1487 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1488 radeon_emit(cs, ds_clear_value.stencil);
1489 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1490 radeon_emit(cs, fui(ds_clear_value.depth));
1491 }
1492
1493 /**
1494 * Update the TC-compat metadata value for this image.
1495 */
1496 static void
1497 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1498 struct radv_image *image,
1499 uint32_t value)
1500 {
1501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1502 uint64_t va = radv_buffer_get_va(image->bo);
1503 va += image->offset + image->tc_compat_zrange_offset;
1504
1505 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1506 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1507 S_370_WR_CONFIRM(1) |
1508 S_370_ENGINE_SEL(V_370_PFP));
1509 radeon_emit(cs, va);
1510 radeon_emit(cs, va >> 32);
1511 radeon_emit(cs, value);
1512 }
1513
1514 static void
1515 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_image *image,
1517 VkClearDepthStencilValue ds_clear_value)
1518 {
1519 uint64_t va = radv_buffer_get_va(image->bo);
1520 va += image->offset + image->tc_compat_zrange_offset;
1521 uint32_t cond_val;
1522
1523 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1524 * depth clear value is 0.0f.
1525 */
1526 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1527
1528 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1529 }
1530
1531 /**
1532 * Update the clear depth/stencil values for this image.
1533 */
1534 void
1535 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1536 struct radv_image *image,
1537 VkClearDepthStencilValue ds_clear_value,
1538 VkImageAspectFlags aspects)
1539 {
1540 assert(radv_image_has_htile(image));
1541
1542 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1543
1544 if (radv_image_is_tc_compat_htile(image) &&
1545 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1546 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1547 ds_clear_value);
1548 }
1549
1550 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1551 aspects);
1552 }
1553
1554 /**
1555 * Load the clear depth/stencil values from the image's metadata.
1556 */
1557 static void
1558 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1559 struct radv_image *image)
1560 {
1561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1562 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1563 uint64_t va = radv_buffer_get_va(image->bo);
1564 unsigned reg_offset = 0, reg_count = 0;
1565
1566 va += image->offset + image->clear_value_offset;
1567
1568 if (!radv_image_has_htile(image))
1569 return;
1570
1571 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1572 ++reg_count;
1573 } else {
1574 ++reg_offset;
1575 va += 4;
1576 }
1577 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1578 ++reg_count;
1579
1580 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1581
1582 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1583 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1584 radeon_emit(cs, va);
1585 radeon_emit(cs, va >> 32);
1586 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1587 radeon_emit(cs, reg_count);
1588 } else {
1589 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1590 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1591 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1592 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1593 radeon_emit(cs, va);
1594 radeon_emit(cs, va >> 32);
1595 radeon_emit(cs, reg >> 2);
1596 radeon_emit(cs, 0);
1597
1598 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1599 radeon_emit(cs, 0);
1600 }
1601 }
1602
1603 /*
1604 * With DCC some colors don't require CMASK elimination before being
1605 * used as a texture. This sets a predicate value to determine if the
1606 * cmask eliminate is required.
1607 */
1608 void
1609 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1610 struct radv_image *image, bool value)
1611 {
1612 uint64_t pred_val = value;
1613 uint64_t va = radv_buffer_get_va(image->bo);
1614 va += image->offset + image->fce_pred_offset;
1615
1616 assert(radv_image_has_dcc(image));
1617
1618 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1619 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1620 S_370_WR_CONFIRM(1) |
1621 S_370_ENGINE_SEL(V_370_PFP));
1622 radeon_emit(cmd_buffer->cs, va);
1623 radeon_emit(cmd_buffer->cs, va >> 32);
1624 radeon_emit(cmd_buffer->cs, pred_val);
1625 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1626 }
1627
1628 /**
1629 * Update the DCC predicate to reflect the compression state.
1630 */
1631 void
1632 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1633 struct radv_image *image, bool value)
1634 {
1635 uint64_t pred_val = value;
1636 uint64_t va = radv_buffer_get_va(image->bo);
1637 va += image->offset + image->dcc_pred_offset;
1638
1639 assert(radv_image_has_dcc(image));
1640
1641 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1642 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1643 S_370_WR_CONFIRM(1) |
1644 S_370_ENGINE_SEL(V_370_PFP));
1645 radeon_emit(cmd_buffer->cs, va);
1646 radeon_emit(cmd_buffer->cs, va >> 32);
1647 radeon_emit(cmd_buffer->cs, pred_val);
1648 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1649 }
1650
1651 /**
1652 * Update the fast clear color values if the image is bound as a color buffer.
1653 */
1654 static void
1655 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1656 struct radv_image *image,
1657 int cb_idx,
1658 uint32_t color_values[2])
1659 {
1660 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1661 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1662 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1663 struct radv_attachment_info *att;
1664 uint32_t att_idx;
1665
1666 if (!framebuffer || !subpass)
1667 return;
1668
1669 att_idx = subpass->color_attachments[cb_idx].attachment;
1670 if (att_idx == VK_ATTACHMENT_UNUSED)
1671 return;
1672
1673 att = &framebuffer->attachments[att_idx];
1674 if (att->attachment->image != image)
1675 return;
1676
1677 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1678 radeon_emit(cs, color_values[0]);
1679 radeon_emit(cs, color_values[1]);
1680
1681 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1682 }
1683
1684 /**
1685 * Set the clear color values to the image's metadata.
1686 */
1687 static void
1688 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1689 struct radv_image *image,
1690 uint32_t color_values[2])
1691 {
1692 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1693 uint64_t va = radv_buffer_get_va(image->bo);
1694
1695 va += image->offset + image->clear_value_offset;
1696
1697 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1698
1699 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
1700 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1701 S_370_WR_CONFIRM(1) |
1702 S_370_ENGINE_SEL(V_370_PFP));
1703 radeon_emit(cs, va);
1704 radeon_emit(cs, va >> 32);
1705 radeon_emit(cs, color_values[0]);
1706 radeon_emit(cs, color_values[1]);
1707 }
1708
1709 /**
1710 * Update the clear color values for this image.
1711 */
1712 void
1713 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1714 struct radv_image *image,
1715 int cb_idx,
1716 uint32_t color_values[2])
1717 {
1718 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1719
1720 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1721
1722 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1723 color_values);
1724 }
1725
1726 /**
1727 * Load the clear color values from the image's metadata.
1728 */
1729 static void
1730 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1731 struct radv_image *image,
1732 int cb_idx)
1733 {
1734 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1735 uint64_t va = radv_buffer_get_va(image->bo);
1736
1737 va += image->offset + image->clear_value_offset;
1738
1739 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1740 return;
1741
1742 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1743
1744 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1745 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1746 radeon_emit(cs, va);
1747 radeon_emit(cs, va >> 32);
1748 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1749 radeon_emit(cs, 2);
1750 } else {
1751 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1752 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1753 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1754 COPY_DATA_COUNT_SEL);
1755 radeon_emit(cs, va);
1756 radeon_emit(cs, va >> 32);
1757 radeon_emit(cs, reg >> 2);
1758 radeon_emit(cs, 0);
1759
1760 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1761 radeon_emit(cs, 0);
1762 }
1763 }
1764
1765 static void
1766 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1767 {
1768 int i;
1769 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1770 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1771 unsigned num_bpp64_colorbufs = 0;
1772
1773 /* this may happen for inherited secondary recording */
1774 if (!framebuffer)
1775 return;
1776
1777 for (i = 0; i < 8; ++i) {
1778 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1779 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1780 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1781 continue;
1782 }
1783
1784 int idx = subpass->color_attachments[i].attachment;
1785 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1786 struct radv_image *image = att->attachment->image;
1787 VkImageLayout layout = subpass->color_attachments[i].layout;
1788
1789 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1790
1791 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1792 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1793 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1794
1795 radv_load_color_clear_metadata(cmd_buffer, image, i);
1796
1797 if (image->planes[0].surface.bpe >= 8)
1798 num_bpp64_colorbufs++;
1799 }
1800
1801 if (subpass->depth_stencil_attachment) {
1802 int idx = subpass->depth_stencil_attachment->attachment;
1803 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1804 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1805 struct radv_image *image = att->attachment->image;
1806 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1807 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1808 cmd_buffer->queue_family_index,
1809 cmd_buffer->queue_family_index);
1810 /* We currently don't support writing decompressed HTILE */
1811 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1812 radv_layout_is_htile_compressed(image, layout, queue_mask));
1813
1814 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1815
1816 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1817 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1818 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1819 }
1820 radv_load_ds_clear_metadata(cmd_buffer, image);
1821 } else {
1822 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1823 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1824 else
1825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1826
1827 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1828 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1829 }
1830 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1831 S_028208_BR_X(framebuffer->width) |
1832 S_028208_BR_Y(framebuffer->height));
1833
1834 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1835 uint8_t watermark = 4; /* Default value for GFX8. */
1836
1837 /* For optimal DCC performance. */
1838 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1839 if (num_bpp64_colorbufs >= 5) {
1840 watermark = 8;
1841 } else {
1842 watermark = 6;
1843 }
1844 }
1845
1846 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1847 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1848 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1849 }
1850
1851 if (cmd_buffer->device->dfsm_allowed) {
1852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1853 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1854 }
1855
1856 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1857 }
1858
1859 static void
1860 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1861 {
1862 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1863 struct radv_cmd_state *state = &cmd_buffer->state;
1864
1865 if (state->index_type != state->last_index_type) {
1866 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1867 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1868 2, state->index_type);
1869 } else {
1870 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1871 radeon_emit(cs, state->index_type);
1872 }
1873
1874 state->last_index_type = state->index_type;
1875 }
1876
1877 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1878 radeon_emit(cs, state->index_va);
1879 radeon_emit(cs, state->index_va >> 32);
1880
1881 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1882 radeon_emit(cs, state->max_index_count);
1883
1884 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1885 }
1886
1887 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1888 {
1889 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1890 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1891 uint32_t pa_sc_mode_cntl_1 =
1892 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1893 uint32_t db_count_control;
1894
1895 if(!cmd_buffer->state.active_occlusion_queries) {
1896 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1897 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1898 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1899 has_perfect_queries) {
1900 /* Re-enable out-of-order rasterization if the
1901 * bound pipeline supports it and if it's has
1902 * been disabled before starting any perfect
1903 * occlusion queries.
1904 */
1905 radeon_set_context_reg(cmd_buffer->cs,
1906 R_028A4C_PA_SC_MODE_CNTL_1,
1907 pa_sc_mode_cntl_1);
1908 }
1909 }
1910 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1911 } else {
1912 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1913 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1914
1915 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1916 db_count_control =
1917 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1918 S_028004_SAMPLE_RATE(sample_rate) |
1919 S_028004_ZPASS_ENABLE(1) |
1920 S_028004_SLICE_EVEN_ENABLE(1) |
1921 S_028004_SLICE_ODD_ENABLE(1);
1922
1923 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1924 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1925 has_perfect_queries) {
1926 /* If the bound pipeline has enabled
1927 * out-of-order rasterization, we should
1928 * disable it before starting any perfect
1929 * occlusion queries.
1930 */
1931 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1932
1933 radeon_set_context_reg(cmd_buffer->cs,
1934 R_028A4C_PA_SC_MODE_CNTL_1,
1935 pa_sc_mode_cntl_1);
1936 }
1937 } else {
1938 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1939 S_028004_SAMPLE_RATE(sample_rate);
1940 }
1941 }
1942
1943 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1944
1945 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1946 }
1947
1948 static void
1949 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1950 {
1951 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1952
1953 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1954 radv_emit_viewport(cmd_buffer);
1955
1956 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1957 !cmd_buffer->device->physical_device->has_scissor_bug)
1958 radv_emit_scissor(cmd_buffer);
1959
1960 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1961 radv_emit_line_width(cmd_buffer);
1962
1963 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1964 radv_emit_blend_constants(cmd_buffer);
1965
1966 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1968 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1969 radv_emit_stencil(cmd_buffer);
1970
1971 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1972 radv_emit_depth_bounds(cmd_buffer);
1973
1974 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1975 radv_emit_depth_bias(cmd_buffer);
1976
1977 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1978 radv_emit_discard_rectangle(cmd_buffer);
1979
1980 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
1981 radv_emit_sample_locations(cmd_buffer);
1982
1983 cmd_buffer->state.dirty &= ~states;
1984 }
1985
1986 static void
1987 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1988 VkPipelineBindPoint bind_point)
1989 {
1990 struct radv_descriptor_state *descriptors_state =
1991 radv_get_descriptors_state(cmd_buffer, bind_point);
1992 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1993 unsigned bo_offset;
1994
1995 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1996 set->mapped_ptr,
1997 &bo_offset))
1998 return;
1999
2000 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2001 set->va += bo_offset;
2002 }
2003
2004 static void
2005 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2006 VkPipelineBindPoint bind_point)
2007 {
2008 struct radv_descriptor_state *descriptors_state =
2009 radv_get_descriptors_state(cmd_buffer, bind_point);
2010 uint32_t size = MAX_SETS * 4;
2011 uint32_t offset;
2012 void *ptr;
2013
2014 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2015 256, &offset, &ptr))
2016 return;
2017
2018 for (unsigned i = 0; i < MAX_SETS; i++) {
2019 uint32_t *uptr = ((uint32_t *)ptr) + i;
2020 uint64_t set_va = 0;
2021 struct radv_descriptor_set *set = descriptors_state->sets[i];
2022 if (descriptors_state->valid & (1u << i))
2023 set_va = set->va;
2024 uptr[0] = set_va & 0xffffffff;
2025 }
2026
2027 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2028 va += offset;
2029
2030 if (cmd_buffer->state.pipeline) {
2031 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2032 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2033 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2034
2035 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2036 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2037 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2038
2039 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2040 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2041 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2042
2043 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2044 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2045 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2046
2047 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2048 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2049 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2050 }
2051
2052 if (cmd_buffer->state.compute_pipeline)
2053 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2054 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2055 }
2056
2057 static void
2058 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2059 VkShaderStageFlags stages)
2060 {
2061 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2062 VK_PIPELINE_BIND_POINT_COMPUTE :
2063 VK_PIPELINE_BIND_POINT_GRAPHICS;
2064 struct radv_descriptor_state *descriptors_state =
2065 radv_get_descriptors_state(cmd_buffer, bind_point);
2066 struct radv_cmd_state *state = &cmd_buffer->state;
2067 bool flush_indirect_descriptors;
2068
2069 if (!descriptors_state->dirty)
2070 return;
2071
2072 if (descriptors_state->push_dirty)
2073 radv_flush_push_descriptors(cmd_buffer, bind_point);
2074
2075 flush_indirect_descriptors =
2076 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2077 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2078 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2079 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2080
2081 if (flush_indirect_descriptors)
2082 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2083
2084 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2085 cmd_buffer->cs,
2086 MAX_SETS * MESA_SHADER_STAGES * 4);
2087
2088 if (cmd_buffer->state.pipeline) {
2089 radv_foreach_stage(stage, stages) {
2090 if (!cmd_buffer->state.pipeline->shaders[stage])
2091 continue;
2092
2093 radv_emit_descriptor_pointers(cmd_buffer,
2094 cmd_buffer->state.pipeline,
2095 descriptors_state, stage);
2096 }
2097 }
2098
2099 if (cmd_buffer->state.compute_pipeline &&
2100 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2101 radv_emit_descriptor_pointers(cmd_buffer,
2102 cmd_buffer->state.compute_pipeline,
2103 descriptors_state,
2104 MESA_SHADER_COMPUTE);
2105 }
2106
2107 descriptors_state->dirty = 0;
2108 descriptors_state->push_dirty = false;
2109
2110 assert(cmd_buffer->cs->cdw <= cdw_max);
2111
2112 if (unlikely(cmd_buffer->device->trace_bo))
2113 radv_save_descriptors(cmd_buffer, bind_point);
2114 }
2115
2116 static void
2117 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2118 VkShaderStageFlags stages)
2119 {
2120 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2121 ? cmd_buffer->state.compute_pipeline
2122 : cmd_buffer->state.pipeline;
2123 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2124 VK_PIPELINE_BIND_POINT_COMPUTE :
2125 VK_PIPELINE_BIND_POINT_GRAPHICS;
2126 struct radv_descriptor_state *descriptors_state =
2127 radv_get_descriptors_state(cmd_buffer, bind_point);
2128 struct radv_pipeline_layout *layout = pipeline->layout;
2129 struct radv_shader_variant *shader, *prev_shader;
2130 bool need_push_constants = false;
2131 unsigned offset;
2132 void *ptr;
2133 uint64_t va;
2134
2135 stages &= cmd_buffer->push_constant_stages;
2136 if (!stages ||
2137 (!layout->push_constant_size && !layout->dynamic_offset_count))
2138 return;
2139
2140 radv_foreach_stage(stage, stages) {
2141 if (!pipeline->shaders[stage])
2142 continue;
2143
2144 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2145 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2146
2147 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2148 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2149
2150 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2151 AC_UD_INLINE_PUSH_CONSTANTS,
2152 count,
2153 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2154 }
2155
2156 if (need_push_constants) {
2157 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2158 16 * layout->dynamic_offset_count,
2159 256, &offset, &ptr))
2160 return;
2161
2162 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2163 memcpy((char*)ptr + layout->push_constant_size,
2164 descriptors_state->dynamic_buffers,
2165 16 * layout->dynamic_offset_count);
2166
2167 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2168 va += offset;
2169
2170 MAYBE_UNUSED unsigned cdw_max =
2171 radeon_check_space(cmd_buffer->device->ws,
2172 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2173
2174 prev_shader = NULL;
2175 radv_foreach_stage(stage, stages) {
2176 shader = radv_get_shader(pipeline, stage);
2177
2178 /* Avoid redundantly emitting the address for merged stages. */
2179 if (shader && shader != prev_shader) {
2180 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2181 AC_UD_PUSH_CONSTANTS, va);
2182
2183 prev_shader = shader;
2184 }
2185 }
2186 assert(cmd_buffer->cs->cdw <= cdw_max);
2187 }
2188
2189 cmd_buffer->push_constant_stages &= ~stages;
2190 }
2191
2192 static void
2193 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2194 bool pipeline_is_dirty)
2195 {
2196 if ((pipeline_is_dirty ||
2197 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2198 cmd_buffer->state.pipeline->num_vertex_bindings &&
2199 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2200 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2201 unsigned vb_offset;
2202 void *vb_ptr;
2203 uint32_t i = 0;
2204 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2205 uint64_t va;
2206
2207 /* allocate some descriptor state for vertex buffers */
2208 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2209 &vb_offset, &vb_ptr))
2210 return;
2211
2212 for (i = 0; i < count; i++) {
2213 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2214 uint32_t offset;
2215 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2216 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2217
2218 if (!buffer)
2219 continue;
2220
2221 va = radv_buffer_get_va(buffer->bo);
2222
2223 offset = cmd_buffer->vertex_bindings[i].offset;
2224 va += offset + buffer->offset;
2225 desc[0] = va;
2226 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2227 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2228 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2229 else
2230 desc[2] = buffer->size - offset;
2231 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2232 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2233 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2234 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2235 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2236 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2237 }
2238
2239 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2240 va += vb_offset;
2241
2242 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2243 AC_UD_VS_VERTEX_BUFFERS, va);
2244
2245 cmd_buffer->state.vb_va = va;
2246 cmd_buffer->state.vb_size = count * 16;
2247 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2248 }
2249 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2250 }
2251
2252 static void
2253 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2254 {
2255 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2256 struct radv_userdata_info *loc;
2257 uint32_t base_reg;
2258
2259 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2260 if (!radv_get_shader(pipeline, stage))
2261 continue;
2262
2263 loc = radv_lookup_user_sgpr(pipeline, stage,
2264 AC_UD_STREAMOUT_BUFFERS);
2265 if (loc->sgpr_idx == -1)
2266 continue;
2267
2268 base_reg = pipeline->user_data_0[stage];
2269
2270 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2271 base_reg + loc->sgpr_idx * 4, va, false);
2272 }
2273
2274 if (pipeline->gs_copy_shader) {
2275 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2276 if (loc->sgpr_idx != -1) {
2277 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2278
2279 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2280 base_reg + loc->sgpr_idx * 4, va, false);
2281 }
2282 }
2283 }
2284
2285 static void
2286 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2287 {
2288 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2289 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2290 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2291 unsigned so_offset;
2292 void *so_ptr;
2293 uint64_t va;
2294
2295 /* Allocate some descriptor state for streamout buffers. */
2296 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2297 MAX_SO_BUFFERS * 16, 256,
2298 &so_offset, &so_ptr))
2299 return;
2300
2301 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2302 struct radv_buffer *buffer = sb[i].buffer;
2303 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2304
2305 if (!(so->enabled_mask & (1 << i)))
2306 continue;
2307
2308 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2309
2310 va += sb[i].offset;
2311
2312 /* Set the descriptor.
2313 *
2314 * On GFX8, the format must be non-INVALID, otherwise
2315 * the buffer will be considered not bound and store
2316 * instructions will be no-ops.
2317 */
2318 desc[0] = va;
2319 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2320 desc[2] = 0xffffffff;
2321 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2322 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2323 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2324 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2325 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2326 }
2327
2328 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2329 va += so_offset;
2330
2331 radv_emit_streamout_buffers(cmd_buffer, va);
2332 }
2333
2334 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2335 }
2336
2337 static void
2338 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2339 {
2340 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2341 radv_flush_streamout_descriptors(cmd_buffer);
2342 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2343 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2344 }
2345
2346 struct radv_draw_info {
2347 /**
2348 * Number of vertices.
2349 */
2350 uint32_t count;
2351
2352 /**
2353 * Index of the first vertex.
2354 */
2355 int32_t vertex_offset;
2356
2357 /**
2358 * First instance id.
2359 */
2360 uint32_t first_instance;
2361
2362 /**
2363 * Number of instances.
2364 */
2365 uint32_t instance_count;
2366
2367 /**
2368 * First index (indexed draws only).
2369 */
2370 uint32_t first_index;
2371
2372 /**
2373 * Whether it's an indexed draw.
2374 */
2375 bool indexed;
2376
2377 /**
2378 * Indirect draw parameters resource.
2379 */
2380 struct radv_buffer *indirect;
2381 uint64_t indirect_offset;
2382 uint32_t stride;
2383
2384 /**
2385 * Draw count parameters resource.
2386 */
2387 struct radv_buffer *count_buffer;
2388 uint64_t count_buffer_offset;
2389
2390 /**
2391 * Stream output parameters resource.
2392 */
2393 struct radv_buffer *strmout_buffer;
2394 uint64_t strmout_buffer_offset;
2395 };
2396
2397 static void
2398 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2399 const struct radv_draw_info *draw_info)
2400 {
2401 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2402 struct radv_cmd_state *state = &cmd_buffer->state;
2403 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2404 uint32_t ia_multi_vgt_param;
2405 int32_t primitive_reset_en;
2406
2407 /* Draw state. */
2408 ia_multi_vgt_param =
2409 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2410 draw_info->indirect,
2411 !!draw_info->strmout_buffer,
2412 draw_info->indirect ? 0 : draw_info->count);
2413
2414 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2415 if (info->chip_class >= GFX9) {
2416 radeon_set_uconfig_reg_idx(cs,
2417 R_030960_IA_MULTI_VGT_PARAM,
2418 4, ia_multi_vgt_param);
2419 } else if (info->chip_class >= GFX7) {
2420 radeon_set_context_reg_idx(cs,
2421 R_028AA8_IA_MULTI_VGT_PARAM,
2422 1, ia_multi_vgt_param);
2423 } else {
2424 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2425 ia_multi_vgt_param);
2426 }
2427 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2428 }
2429
2430 /* Primitive restart. */
2431 primitive_reset_en =
2432 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2433
2434 if (primitive_reset_en != state->last_primitive_reset_en) {
2435 state->last_primitive_reset_en = primitive_reset_en;
2436 if (info->chip_class >= GFX9) {
2437 radeon_set_uconfig_reg(cs,
2438 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2439 primitive_reset_en);
2440 } else {
2441 radeon_set_context_reg(cs,
2442 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2443 primitive_reset_en);
2444 }
2445 }
2446
2447 if (primitive_reset_en) {
2448 uint32_t primitive_reset_index =
2449 state->index_type ? 0xffffffffu : 0xffffu;
2450
2451 if (primitive_reset_index != state->last_primitive_reset_index) {
2452 radeon_set_context_reg(cs,
2453 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2454 primitive_reset_index);
2455 state->last_primitive_reset_index = primitive_reset_index;
2456 }
2457 }
2458
2459 if (draw_info->strmout_buffer) {
2460 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2461
2462 va += draw_info->strmout_buffer->offset +
2463 draw_info->strmout_buffer_offset;
2464
2465 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2466 draw_info->stride);
2467
2468 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2469 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2470 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2471 COPY_DATA_WR_CONFIRM);
2472 radeon_emit(cs, va);
2473 radeon_emit(cs, va >> 32);
2474 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2475 radeon_emit(cs, 0); /* unused */
2476
2477 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2478 }
2479 }
2480
2481 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2482 VkPipelineStageFlags src_stage_mask)
2483 {
2484 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2485 VK_PIPELINE_STAGE_TRANSFER_BIT |
2486 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2487 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2488 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2489 }
2490
2491 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2492 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2493 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2494 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2495 VK_PIPELINE_STAGE_TRANSFER_BIT |
2496 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2497 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2498 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2499 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2500 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2501 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2502 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2503 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2504 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2505 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2506 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2507 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2508 }
2509 }
2510
2511 static enum radv_cmd_flush_bits
2512 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2513 VkAccessFlags src_flags,
2514 struct radv_image *image)
2515 {
2516 bool flush_CB_meta = true, flush_DB_meta = true;
2517 enum radv_cmd_flush_bits flush_bits = 0;
2518 uint32_t b;
2519
2520 if (image) {
2521 if (!radv_image_has_CB_metadata(image))
2522 flush_CB_meta = false;
2523 if (!radv_image_has_htile(image))
2524 flush_DB_meta = false;
2525 }
2526
2527 for_each_bit(b, src_flags) {
2528 switch ((VkAccessFlagBits)(1 << b)) {
2529 case VK_ACCESS_SHADER_WRITE_BIT:
2530 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2531 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2532 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2533 break;
2534 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2535 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2536 if (flush_CB_meta)
2537 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2538 break;
2539 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2540 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2541 if (flush_DB_meta)
2542 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2543 break;
2544 case VK_ACCESS_TRANSFER_WRITE_BIT:
2545 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2546 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2547 RADV_CMD_FLAG_INV_GLOBAL_L2;
2548
2549 if (flush_CB_meta)
2550 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2551 if (flush_DB_meta)
2552 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2553 break;
2554 default:
2555 break;
2556 }
2557 }
2558 return flush_bits;
2559 }
2560
2561 static enum radv_cmd_flush_bits
2562 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2563 VkAccessFlags dst_flags,
2564 struct radv_image *image)
2565 {
2566 bool flush_CB_meta = true, flush_DB_meta = true;
2567 enum radv_cmd_flush_bits flush_bits = 0;
2568 bool flush_CB = true, flush_DB = true;
2569 bool image_is_coherent = false;
2570 uint32_t b;
2571
2572 if (image) {
2573 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2574 flush_CB = false;
2575 flush_DB = false;
2576 }
2577
2578 if (!radv_image_has_CB_metadata(image))
2579 flush_CB_meta = false;
2580 if (!radv_image_has_htile(image))
2581 flush_DB_meta = false;
2582
2583 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2584 if (image->info.samples == 1 &&
2585 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2586 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2587 !vk_format_is_stencil(image->vk_format)) {
2588 /* Single-sample color and single-sample depth
2589 * (not stencil) are coherent with shaders on
2590 * GFX9.
2591 */
2592 image_is_coherent = true;
2593 }
2594 }
2595 }
2596
2597 for_each_bit(b, dst_flags) {
2598 switch ((VkAccessFlagBits)(1 << b)) {
2599 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2600 case VK_ACCESS_INDEX_READ_BIT:
2601 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2602 break;
2603 case VK_ACCESS_UNIFORM_READ_BIT:
2604 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2605 break;
2606 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2607 case VK_ACCESS_TRANSFER_READ_BIT:
2608 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2609 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2610 RADV_CMD_FLAG_INV_GLOBAL_L2;
2611 break;
2612 case VK_ACCESS_SHADER_READ_BIT:
2613 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2614
2615 if (!image_is_coherent)
2616 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2617 break;
2618 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2619 if (flush_CB)
2620 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2621 if (flush_CB_meta)
2622 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2623 break;
2624 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2625 if (flush_DB)
2626 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2627 if (flush_DB_meta)
2628 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2629 break;
2630 default:
2631 break;
2632 }
2633 }
2634 return flush_bits;
2635 }
2636
2637 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2638 const struct radv_subpass_barrier *barrier)
2639 {
2640 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2641 NULL);
2642 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2643 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2644 NULL);
2645 }
2646
2647 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2648 struct radv_subpass_attachment att)
2649 {
2650 unsigned idx = att.attachment;
2651 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2652 VkImageSubresourceRange range;
2653 range.aspectMask = 0;
2654 range.baseMipLevel = view->base_mip;
2655 range.levelCount = 1;
2656 range.baseArrayLayer = view->base_layer;
2657 range.layerCount = cmd_buffer->state.framebuffer->layers;
2658
2659 if (cmd_buffer->state.subpass->view_mask) {
2660 /* If the current subpass uses multiview, the driver might have
2661 * performed a fast color/depth clear to the whole image
2662 * (including all layers). To make sure the driver will
2663 * decompress the image correctly (if needed), we have to
2664 * account for the "real" number of layers. If the view mask is
2665 * sparse, this will decompress more layers than needed.
2666 */
2667 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2668 }
2669
2670 radv_handle_image_transition(cmd_buffer,
2671 view->image,
2672 cmd_buffer->state.attachments[idx].current_layout,
2673 att.layout, 0, 0, &range, NULL);
2674
2675 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2676
2677
2678 }
2679
2680 void
2681 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2682 const struct radv_subpass *subpass)
2683 {
2684 cmd_buffer->state.subpass = subpass;
2685
2686 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2687 }
2688
2689 static VkResult
2690 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2691 struct radv_render_pass *pass,
2692 const VkRenderPassBeginInfo *info)
2693 {
2694 struct radv_cmd_state *state = &cmd_buffer->state;
2695
2696 if (pass->attachment_count == 0) {
2697 state->attachments = NULL;
2698 return VK_SUCCESS;
2699 }
2700
2701 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2702 pass->attachment_count *
2703 sizeof(state->attachments[0]),
2704 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2705 if (state->attachments == NULL) {
2706 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2707 return cmd_buffer->record_result;
2708 }
2709
2710 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2711 struct radv_render_pass_attachment *att = &pass->attachments[i];
2712 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2713 VkImageAspectFlags clear_aspects = 0;
2714
2715 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2716 /* color attachment */
2717 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2718 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2719 }
2720 } else {
2721 /* depthstencil attachment */
2722 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2723 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2724 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2725 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2726 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2727 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2728 }
2729 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2730 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2731 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2732 }
2733 }
2734
2735 state->attachments[i].pending_clear_aspects = clear_aspects;
2736 state->attachments[i].cleared_views = 0;
2737 if (clear_aspects && info) {
2738 assert(info->clearValueCount > i);
2739 state->attachments[i].clear_value = info->pClearValues[i];
2740 }
2741
2742 state->attachments[i].current_layout = att->initial_layout;
2743 }
2744
2745 return VK_SUCCESS;
2746 }
2747
2748 VkResult radv_AllocateCommandBuffers(
2749 VkDevice _device,
2750 const VkCommandBufferAllocateInfo *pAllocateInfo,
2751 VkCommandBuffer *pCommandBuffers)
2752 {
2753 RADV_FROM_HANDLE(radv_device, device, _device);
2754 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2755
2756 VkResult result = VK_SUCCESS;
2757 uint32_t i;
2758
2759 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2760
2761 if (!list_empty(&pool->free_cmd_buffers)) {
2762 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2763
2764 list_del(&cmd_buffer->pool_link);
2765 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2766
2767 result = radv_reset_cmd_buffer(cmd_buffer);
2768 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2769 cmd_buffer->level = pAllocateInfo->level;
2770
2771 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2772 } else {
2773 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2774 &pCommandBuffers[i]);
2775 }
2776 if (result != VK_SUCCESS)
2777 break;
2778 }
2779
2780 if (result != VK_SUCCESS) {
2781 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2782 i, pCommandBuffers);
2783
2784 /* From the Vulkan 1.0.66 spec:
2785 *
2786 * "vkAllocateCommandBuffers can be used to create multiple
2787 * command buffers. If the creation of any of those command
2788 * buffers fails, the implementation must destroy all
2789 * successfully created command buffer objects from this
2790 * command, set all entries of the pCommandBuffers array to
2791 * NULL and return the error."
2792 */
2793 memset(pCommandBuffers, 0,
2794 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2795 }
2796
2797 return result;
2798 }
2799
2800 void radv_FreeCommandBuffers(
2801 VkDevice device,
2802 VkCommandPool commandPool,
2803 uint32_t commandBufferCount,
2804 const VkCommandBuffer *pCommandBuffers)
2805 {
2806 for (uint32_t i = 0; i < commandBufferCount; i++) {
2807 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2808
2809 if (cmd_buffer) {
2810 if (cmd_buffer->pool) {
2811 list_del(&cmd_buffer->pool_link);
2812 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2813 } else
2814 radv_cmd_buffer_destroy(cmd_buffer);
2815
2816 }
2817 }
2818 }
2819
2820 VkResult radv_ResetCommandBuffer(
2821 VkCommandBuffer commandBuffer,
2822 VkCommandBufferResetFlags flags)
2823 {
2824 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2825 return radv_reset_cmd_buffer(cmd_buffer);
2826 }
2827
2828 VkResult radv_BeginCommandBuffer(
2829 VkCommandBuffer commandBuffer,
2830 const VkCommandBufferBeginInfo *pBeginInfo)
2831 {
2832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2833 VkResult result = VK_SUCCESS;
2834
2835 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2836 /* If the command buffer has already been resetted with
2837 * vkResetCommandBuffer, no need to do it again.
2838 */
2839 result = radv_reset_cmd_buffer(cmd_buffer);
2840 if (result != VK_SUCCESS)
2841 return result;
2842 }
2843
2844 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2845 cmd_buffer->state.last_primitive_reset_en = -1;
2846 cmd_buffer->state.last_index_type = -1;
2847 cmd_buffer->state.last_num_instances = -1;
2848 cmd_buffer->state.last_vertex_offset = -1;
2849 cmd_buffer->state.last_first_instance = -1;
2850 cmd_buffer->state.predication_type = -1;
2851 cmd_buffer->usage_flags = pBeginInfo->flags;
2852
2853 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2854 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2855 assert(pBeginInfo->pInheritanceInfo);
2856 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2857 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2858
2859 struct radv_subpass *subpass =
2860 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2861
2862 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2863 if (result != VK_SUCCESS)
2864 return result;
2865
2866 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2867 }
2868
2869 if (unlikely(cmd_buffer->device->trace_bo)) {
2870 struct radv_device *device = cmd_buffer->device;
2871
2872 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2873 device->trace_bo);
2874
2875 radv_cmd_buffer_trace_emit(cmd_buffer);
2876 }
2877
2878 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2879
2880 return result;
2881 }
2882
2883 void radv_CmdBindVertexBuffers(
2884 VkCommandBuffer commandBuffer,
2885 uint32_t firstBinding,
2886 uint32_t bindingCount,
2887 const VkBuffer* pBuffers,
2888 const VkDeviceSize* pOffsets)
2889 {
2890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2891 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2892 bool changed = false;
2893
2894 /* We have to defer setting up vertex buffer since we need the buffer
2895 * stride from the pipeline. */
2896
2897 assert(firstBinding + bindingCount <= MAX_VBS);
2898 for (uint32_t i = 0; i < bindingCount; i++) {
2899 uint32_t idx = firstBinding + i;
2900
2901 if (!changed &&
2902 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2903 vb[idx].offset != pOffsets[i])) {
2904 changed = true;
2905 }
2906
2907 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2908 vb[idx].offset = pOffsets[i];
2909
2910 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2911 vb[idx].buffer->bo);
2912 }
2913
2914 if (!changed) {
2915 /* No state changes. */
2916 return;
2917 }
2918
2919 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2920 }
2921
2922 void radv_CmdBindIndexBuffer(
2923 VkCommandBuffer commandBuffer,
2924 VkBuffer buffer,
2925 VkDeviceSize offset,
2926 VkIndexType indexType)
2927 {
2928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2929 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2930
2931 if (cmd_buffer->state.index_buffer == index_buffer &&
2932 cmd_buffer->state.index_offset == offset &&
2933 cmd_buffer->state.index_type == indexType) {
2934 /* No state changes. */
2935 return;
2936 }
2937
2938 cmd_buffer->state.index_buffer = index_buffer;
2939 cmd_buffer->state.index_offset = offset;
2940 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2941 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2942 cmd_buffer->state.index_va += index_buffer->offset + offset;
2943
2944 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2945 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2947 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2948 }
2949
2950
2951 static void
2952 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2953 VkPipelineBindPoint bind_point,
2954 struct radv_descriptor_set *set, unsigned idx)
2955 {
2956 struct radeon_winsys *ws = cmd_buffer->device->ws;
2957
2958 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2959
2960 assert(set);
2961 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2962
2963 if (!cmd_buffer->device->use_global_bo_list) {
2964 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2965 if (set->descriptors[j])
2966 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2967 }
2968
2969 if(set->bo)
2970 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2971 }
2972
2973 void radv_CmdBindDescriptorSets(
2974 VkCommandBuffer commandBuffer,
2975 VkPipelineBindPoint pipelineBindPoint,
2976 VkPipelineLayout _layout,
2977 uint32_t firstSet,
2978 uint32_t descriptorSetCount,
2979 const VkDescriptorSet* pDescriptorSets,
2980 uint32_t dynamicOffsetCount,
2981 const uint32_t* pDynamicOffsets)
2982 {
2983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2984 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2985 unsigned dyn_idx = 0;
2986
2987 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2988 struct radv_descriptor_state *descriptors_state =
2989 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2990
2991 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2992 unsigned idx = i + firstSet;
2993 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2994 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2995
2996 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2997 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2998 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2999 assert(dyn_idx < dynamicOffsetCount);
3000
3001 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3002 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3003 dst[0] = va;
3004 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3005 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3006 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3007 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3008 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3009 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3010 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3011 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3012 cmd_buffer->push_constant_stages |=
3013 set->layout->dynamic_shader_stages;
3014 }
3015 }
3016 }
3017
3018 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3019 struct radv_descriptor_set *set,
3020 struct radv_descriptor_set_layout *layout,
3021 VkPipelineBindPoint bind_point)
3022 {
3023 struct radv_descriptor_state *descriptors_state =
3024 radv_get_descriptors_state(cmd_buffer, bind_point);
3025 set->size = layout->size;
3026 set->layout = layout;
3027
3028 if (descriptors_state->push_set.capacity < set->size) {
3029 size_t new_size = MAX2(set->size, 1024);
3030 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3031 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3032
3033 free(set->mapped_ptr);
3034 set->mapped_ptr = malloc(new_size);
3035
3036 if (!set->mapped_ptr) {
3037 descriptors_state->push_set.capacity = 0;
3038 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3039 return false;
3040 }
3041
3042 descriptors_state->push_set.capacity = new_size;
3043 }
3044
3045 return true;
3046 }
3047
3048 void radv_meta_push_descriptor_set(
3049 struct radv_cmd_buffer* cmd_buffer,
3050 VkPipelineBindPoint pipelineBindPoint,
3051 VkPipelineLayout _layout,
3052 uint32_t set,
3053 uint32_t descriptorWriteCount,
3054 const VkWriteDescriptorSet* pDescriptorWrites)
3055 {
3056 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3057 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3058 unsigned bo_offset;
3059
3060 assert(set == 0);
3061 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3062
3063 push_set->size = layout->set[set].layout->size;
3064 push_set->layout = layout->set[set].layout;
3065
3066 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3067 &bo_offset,
3068 (void**) &push_set->mapped_ptr))
3069 return;
3070
3071 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3072 push_set->va += bo_offset;
3073
3074 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3075 radv_descriptor_set_to_handle(push_set),
3076 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3077
3078 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3079 }
3080
3081 void radv_CmdPushDescriptorSetKHR(
3082 VkCommandBuffer commandBuffer,
3083 VkPipelineBindPoint pipelineBindPoint,
3084 VkPipelineLayout _layout,
3085 uint32_t set,
3086 uint32_t descriptorWriteCount,
3087 const VkWriteDescriptorSet* pDescriptorWrites)
3088 {
3089 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3090 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3091 struct radv_descriptor_state *descriptors_state =
3092 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3093 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3094
3095 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3096
3097 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3098 layout->set[set].layout,
3099 pipelineBindPoint))
3100 return;
3101
3102 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3103 radv_descriptor_set_to_handle(push_set),
3104 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3105
3106 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3107 descriptors_state->push_dirty = true;
3108 }
3109
3110 void radv_CmdPushDescriptorSetWithTemplateKHR(
3111 VkCommandBuffer commandBuffer,
3112 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3113 VkPipelineLayout _layout,
3114 uint32_t set,
3115 const void* pData)
3116 {
3117 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3118 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3119 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3120 struct radv_descriptor_state *descriptors_state =
3121 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3122 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3123
3124 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3125
3126 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3127 layout->set[set].layout,
3128 templ->bind_point))
3129 return;
3130
3131 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3132 descriptorUpdateTemplate, pData);
3133
3134 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3135 descriptors_state->push_dirty = true;
3136 }
3137
3138 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3139 VkPipelineLayout layout,
3140 VkShaderStageFlags stageFlags,
3141 uint32_t offset,
3142 uint32_t size,
3143 const void* pValues)
3144 {
3145 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3146 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3147 cmd_buffer->push_constant_stages |= stageFlags;
3148 }
3149
3150 VkResult radv_EndCommandBuffer(
3151 VkCommandBuffer commandBuffer)
3152 {
3153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3154
3155 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3156 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3157 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3158
3159 /* Make sure to sync all pending active queries at the end of
3160 * command buffer.
3161 */
3162 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3163
3164 si_emit_cache_flush(cmd_buffer);
3165 }
3166
3167 /* Make sure CP DMA is idle at the end of IBs because the kernel
3168 * doesn't wait for it.
3169 */
3170 si_cp_dma_wait_for_idle(cmd_buffer);
3171
3172 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3173
3174 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3175 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3176
3177 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3178
3179 return cmd_buffer->record_result;
3180 }
3181
3182 static void
3183 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3184 {
3185 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3186
3187 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3188 return;
3189
3190 assert(!pipeline->ctx_cs.cdw);
3191
3192 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3193
3194 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3195 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3196
3197 cmd_buffer->compute_scratch_size_needed =
3198 MAX2(cmd_buffer->compute_scratch_size_needed,
3199 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3200
3201 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3202 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3203
3204 if (unlikely(cmd_buffer->device->trace_bo))
3205 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3206 }
3207
3208 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3209 VkPipelineBindPoint bind_point)
3210 {
3211 struct radv_descriptor_state *descriptors_state =
3212 radv_get_descriptors_state(cmd_buffer, bind_point);
3213
3214 descriptors_state->dirty |= descriptors_state->valid;
3215 }
3216
3217 void radv_CmdBindPipeline(
3218 VkCommandBuffer commandBuffer,
3219 VkPipelineBindPoint pipelineBindPoint,
3220 VkPipeline _pipeline)
3221 {
3222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3223 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3224
3225 switch (pipelineBindPoint) {
3226 case VK_PIPELINE_BIND_POINT_COMPUTE:
3227 if (cmd_buffer->state.compute_pipeline == pipeline)
3228 return;
3229 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3230
3231 cmd_buffer->state.compute_pipeline = pipeline;
3232 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3233 break;
3234 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3235 if (cmd_buffer->state.pipeline == pipeline)
3236 return;
3237 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3238
3239 cmd_buffer->state.pipeline = pipeline;
3240 if (!pipeline)
3241 break;
3242
3243 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3244 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3245
3246 /* the new vertex shader might not have the same user regs */
3247 cmd_buffer->state.last_first_instance = -1;
3248 cmd_buffer->state.last_vertex_offset = -1;
3249
3250 /* Prefetch all pipeline shaders at first draw time. */
3251 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3252
3253 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3254 radv_bind_streamout_state(cmd_buffer, pipeline);
3255
3256 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3257 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3258 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3259 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3260
3261 if (radv_pipeline_has_tess(pipeline))
3262 cmd_buffer->tess_rings_needed = true;
3263 break;
3264 default:
3265 assert(!"invalid bind point");
3266 break;
3267 }
3268 }
3269
3270 void radv_CmdSetViewport(
3271 VkCommandBuffer commandBuffer,
3272 uint32_t firstViewport,
3273 uint32_t viewportCount,
3274 const VkViewport* pViewports)
3275 {
3276 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3277 struct radv_cmd_state *state = &cmd_buffer->state;
3278 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3279
3280 assert(firstViewport < MAX_VIEWPORTS);
3281 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3282
3283 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3284 pViewports, viewportCount * sizeof(*pViewports))) {
3285 return;
3286 }
3287
3288 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3289 viewportCount * sizeof(*pViewports));
3290
3291 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3292 }
3293
3294 void radv_CmdSetScissor(
3295 VkCommandBuffer commandBuffer,
3296 uint32_t firstScissor,
3297 uint32_t scissorCount,
3298 const VkRect2D* pScissors)
3299 {
3300 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3301 struct radv_cmd_state *state = &cmd_buffer->state;
3302 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3303
3304 assert(firstScissor < MAX_SCISSORS);
3305 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3306
3307 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3308 scissorCount * sizeof(*pScissors))) {
3309 return;
3310 }
3311
3312 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3313 scissorCount * sizeof(*pScissors));
3314
3315 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3316 }
3317
3318 void radv_CmdSetLineWidth(
3319 VkCommandBuffer commandBuffer,
3320 float lineWidth)
3321 {
3322 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3323
3324 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3325 return;
3326
3327 cmd_buffer->state.dynamic.line_width = lineWidth;
3328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3329 }
3330
3331 void radv_CmdSetDepthBias(
3332 VkCommandBuffer commandBuffer,
3333 float depthBiasConstantFactor,
3334 float depthBiasClamp,
3335 float depthBiasSlopeFactor)
3336 {
3337 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3338 struct radv_cmd_state *state = &cmd_buffer->state;
3339
3340 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3341 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3342 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3343 return;
3344 }
3345
3346 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3347 state->dynamic.depth_bias.clamp = depthBiasClamp;
3348 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3349
3350 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3351 }
3352
3353 void radv_CmdSetBlendConstants(
3354 VkCommandBuffer commandBuffer,
3355 const float blendConstants[4])
3356 {
3357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3358 struct radv_cmd_state *state = &cmd_buffer->state;
3359
3360 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3361 return;
3362
3363 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3364
3365 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3366 }
3367
3368 void radv_CmdSetDepthBounds(
3369 VkCommandBuffer commandBuffer,
3370 float minDepthBounds,
3371 float maxDepthBounds)
3372 {
3373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3374 struct radv_cmd_state *state = &cmd_buffer->state;
3375
3376 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3377 state->dynamic.depth_bounds.max == maxDepthBounds) {
3378 return;
3379 }
3380
3381 state->dynamic.depth_bounds.min = minDepthBounds;
3382 state->dynamic.depth_bounds.max = maxDepthBounds;
3383
3384 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3385 }
3386
3387 void radv_CmdSetStencilCompareMask(
3388 VkCommandBuffer commandBuffer,
3389 VkStencilFaceFlags faceMask,
3390 uint32_t compareMask)
3391 {
3392 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3393 struct radv_cmd_state *state = &cmd_buffer->state;
3394 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3395 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3396
3397 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3398 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3399 return;
3400 }
3401
3402 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3403 state->dynamic.stencil_compare_mask.front = compareMask;
3404 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3405 state->dynamic.stencil_compare_mask.back = compareMask;
3406
3407 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3408 }
3409
3410 void radv_CmdSetStencilWriteMask(
3411 VkCommandBuffer commandBuffer,
3412 VkStencilFaceFlags faceMask,
3413 uint32_t writeMask)
3414 {
3415 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3416 struct radv_cmd_state *state = &cmd_buffer->state;
3417 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3418 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3419
3420 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3421 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3422 return;
3423 }
3424
3425 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3426 state->dynamic.stencil_write_mask.front = writeMask;
3427 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3428 state->dynamic.stencil_write_mask.back = writeMask;
3429
3430 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3431 }
3432
3433 void radv_CmdSetStencilReference(
3434 VkCommandBuffer commandBuffer,
3435 VkStencilFaceFlags faceMask,
3436 uint32_t reference)
3437 {
3438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3439 struct radv_cmd_state *state = &cmd_buffer->state;
3440 bool front_same = state->dynamic.stencil_reference.front == reference;
3441 bool back_same = state->dynamic.stencil_reference.back == reference;
3442
3443 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3444 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3445 return;
3446 }
3447
3448 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3449 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3450 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3451 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3452
3453 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3454 }
3455
3456 void radv_CmdSetDiscardRectangleEXT(
3457 VkCommandBuffer commandBuffer,
3458 uint32_t firstDiscardRectangle,
3459 uint32_t discardRectangleCount,
3460 const VkRect2D* pDiscardRectangles)
3461 {
3462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3463 struct radv_cmd_state *state = &cmd_buffer->state;
3464 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3465
3466 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3467 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3468
3469 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3470 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3471 return;
3472 }
3473
3474 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3475 pDiscardRectangles, discardRectangleCount);
3476
3477 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3478 }
3479
3480 void radv_CmdSetSampleLocationsEXT(
3481 VkCommandBuffer commandBuffer,
3482 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3483 {
3484 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3485 struct radv_cmd_state *state = &cmd_buffer->state;
3486
3487 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3488
3489 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3490 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3491 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3492 typed_memcpy(&state->dynamic.sample_location.locations[0],
3493 pSampleLocationsInfo->pSampleLocations,
3494 pSampleLocationsInfo->sampleLocationsCount);
3495
3496 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3497 }
3498
3499 void radv_CmdExecuteCommands(
3500 VkCommandBuffer commandBuffer,
3501 uint32_t commandBufferCount,
3502 const VkCommandBuffer* pCmdBuffers)
3503 {
3504 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3505
3506 assert(commandBufferCount > 0);
3507
3508 /* Emit pending flushes on primary prior to executing secondary */
3509 si_emit_cache_flush(primary);
3510
3511 for (uint32_t i = 0; i < commandBufferCount; i++) {
3512 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3513
3514 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3515 secondary->scratch_size_needed);
3516 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3517 secondary->compute_scratch_size_needed);
3518
3519 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3520 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3521 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3522 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3523 if (secondary->tess_rings_needed)
3524 primary->tess_rings_needed = true;
3525 if (secondary->sample_positions_needed)
3526 primary->sample_positions_needed = true;
3527
3528 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3529
3530
3531 /* When the secondary command buffer is compute only we don't
3532 * need to re-emit the current graphics pipeline.
3533 */
3534 if (secondary->state.emitted_pipeline) {
3535 primary->state.emitted_pipeline =
3536 secondary->state.emitted_pipeline;
3537 }
3538
3539 /* When the secondary command buffer is graphics only we don't
3540 * need to re-emit the current compute pipeline.
3541 */
3542 if (secondary->state.emitted_compute_pipeline) {
3543 primary->state.emitted_compute_pipeline =
3544 secondary->state.emitted_compute_pipeline;
3545 }
3546
3547 /* Only re-emit the draw packets when needed. */
3548 if (secondary->state.last_primitive_reset_en != -1) {
3549 primary->state.last_primitive_reset_en =
3550 secondary->state.last_primitive_reset_en;
3551 }
3552
3553 if (secondary->state.last_primitive_reset_index) {
3554 primary->state.last_primitive_reset_index =
3555 secondary->state.last_primitive_reset_index;
3556 }
3557
3558 if (secondary->state.last_ia_multi_vgt_param) {
3559 primary->state.last_ia_multi_vgt_param =
3560 secondary->state.last_ia_multi_vgt_param;
3561 }
3562
3563 primary->state.last_first_instance = secondary->state.last_first_instance;
3564 primary->state.last_num_instances = secondary->state.last_num_instances;
3565 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3566
3567 if (secondary->state.last_index_type != -1) {
3568 primary->state.last_index_type =
3569 secondary->state.last_index_type;
3570 }
3571 }
3572
3573 /* After executing commands from secondary buffers we have to dirty
3574 * some states.
3575 */
3576 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3577 RADV_CMD_DIRTY_INDEX_BUFFER |
3578 RADV_CMD_DIRTY_DYNAMIC_ALL;
3579 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3580 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3581 }
3582
3583 VkResult radv_CreateCommandPool(
3584 VkDevice _device,
3585 const VkCommandPoolCreateInfo* pCreateInfo,
3586 const VkAllocationCallbacks* pAllocator,
3587 VkCommandPool* pCmdPool)
3588 {
3589 RADV_FROM_HANDLE(radv_device, device, _device);
3590 struct radv_cmd_pool *pool;
3591
3592 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3593 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3594 if (pool == NULL)
3595 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3596
3597 if (pAllocator)
3598 pool->alloc = *pAllocator;
3599 else
3600 pool->alloc = device->alloc;
3601
3602 list_inithead(&pool->cmd_buffers);
3603 list_inithead(&pool->free_cmd_buffers);
3604
3605 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3606
3607 *pCmdPool = radv_cmd_pool_to_handle(pool);
3608
3609 return VK_SUCCESS;
3610
3611 }
3612
3613 void radv_DestroyCommandPool(
3614 VkDevice _device,
3615 VkCommandPool commandPool,
3616 const VkAllocationCallbacks* pAllocator)
3617 {
3618 RADV_FROM_HANDLE(radv_device, device, _device);
3619 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3620
3621 if (!pool)
3622 return;
3623
3624 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3625 &pool->cmd_buffers, pool_link) {
3626 radv_cmd_buffer_destroy(cmd_buffer);
3627 }
3628
3629 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3630 &pool->free_cmd_buffers, pool_link) {
3631 radv_cmd_buffer_destroy(cmd_buffer);
3632 }
3633
3634 vk_free2(&device->alloc, pAllocator, pool);
3635 }
3636
3637 VkResult radv_ResetCommandPool(
3638 VkDevice device,
3639 VkCommandPool commandPool,
3640 VkCommandPoolResetFlags flags)
3641 {
3642 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3643 VkResult result;
3644
3645 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3646 &pool->cmd_buffers, pool_link) {
3647 result = radv_reset_cmd_buffer(cmd_buffer);
3648 if (result != VK_SUCCESS)
3649 return result;
3650 }
3651
3652 return VK_SUCCESS;
3653 }
3654
3655 void radv_TrimCommandPool(
3656 VkDevice device,
3657 VkCommandPool commandPool,
3658 VkCommandPoolTrimFlags flags)
3659 {
3660 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3661
3662 if (!pool)
3663 return;
3664
3665 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3666 &pool->free_cmd_buffers, pool_link) {
3667 radv_cmd_buffer_destroy(cmd_buffer);
3668 }
3669 }
3670
3671 static uint32_t
3672 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3673 {
3674 struct radv_cmd_state *state = &cmd_buffer->state;
3675 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3676
3677 /* The id of this subpass shouldn't exceed the number of subpasses in
3678 * this render pass minus 1.
3679 */
3680 assert(subpass_id < state->pass->subpass_count);
3681 return subpass_id;
3682 }
3683
3684 static void
3685 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3686 uint32_t subpass_id)
3687 {
3688 struct radv_cmd_state *state = &cmd_buffer->state;
3689 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3690
3691 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3692 cmd_buffer->cs, 4096);
3693
3694 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3695
3696 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3697
3698 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3699 const uint32_t a = subpass->attachments[i].attachment;
3700 if (a == VK_ATTACHMENT_UNUSED)
3701 continue;
3702
3703 radv_handle_subpass_image_transition(cmd_buffer,
3704 subpass->attachments[i]);
3705 }
3706
3707 radv_cmd_buffer_clear_subpass(cmd_buffer);
3708
3709 assert(cmd_buffer->cs->cdw <= cdw_max);
3710 }
3711
3712 static void
3713 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3714 {
3715 struct radv_cmd_state *state = &cmd_buffer->state;
3716 const struct radv_subpass *subpass = state->subpass;
3717 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3718
3719 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3720
3721 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3722 const uint32_t a = subpass->attachments[i].attachment;
3723 if (a == VK_ATTACHMENT_UNUSED)
3724 continue;
3725
3726 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3727 continue;
3728
3729 VkImageLayout layout = state->pass->attachments[a].final_layout;
3730 radv_handle_subpass_image_transition(cmd_buffer,
3731 (struct radv_subpass_attachment){a, layout});
3732 }
3733 }
3734
3735 void radv_CmdBeginRenderPass(
3736 VkCommandBuffer commandBuffer,
3737 const VkRenderPassBeginInfo* pRenderPassBegin,
3738 VkSubpassContents contents)
3739 {
3740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3741 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3742 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3743 VkResult result;
3744
3745 cmd_buffer->state.framebuffer = framebuffer;
3746 cmd_buffer->state.pass = pass;
3747 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3748
3749 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3750 if (result != VK_SUCCESS)
3751 return;
3752
3753 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3754 }
3755
3756 void radv_CmdBeginRenderPass2KHR(
3757 VkCommandBuffer commandBuffer,
3758 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3759 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3760 {
3761 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3762 pSubpassBeginInfo->contents);
3763 }
3764
3765 void radv_CmdNextSubpass(
3766 VkCommandBuffer commandBuffer,
3767 VkSubpassContents contents)
3768 {
3769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3770
3771 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3772 radv_cmd_buffer_end_subpass(cmd_buffer);
3773 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3774 }
3775
3776 void radv_CmdNextSubpass2KHR(
3777 VkCommandBuffer commandBuffer,
3778 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3779 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3780 {
3781 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3782 }
3783
3784 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3785 {
3786 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3787 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3788 if (!radv_get_shader(pipeline, stage))
3789 continue;
3790
3791 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3792 if (loc->sgpr_idx == -1)
3793 continue;
3794 uint32_t base_reg = pipeline->user_data_0[stage];
3795 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3796
3797 }
3798 if (pipeline->gs_copy_shader) {
3799 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3800 if (loc->sgpr_idx != -1) {
3801 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3802 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3803 }
3804 }
3805 }
3806
3807 static void
3808 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3809 uint32_t vertex_count,
3810 bool use_opaque)
3811 {
3812 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3813 radeon_emit(cmd_buffer->cs, vertex_count);
3814 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3815 S_0287F0_USE_OPAQUE(use_opaque));
3816 }
3817
3818 static void
3819 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3820 uint64_t index_va,
3821 uint32_t index_count)
3822 {
3823 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3824 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3825 radeon_emit(cmd_buffer->cs, index_va);
3826 radeon_emit(cmd_buffer->cs, index_va >> 32);
3827 radeon_emit(cmd_buffer->cs, index_count);
3828 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3829 }
3830
3831 static void
3832 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3833 bool indexed,
3834 uint32_t draw_count,
3835 uint64_t count_va,
3836 uint32_t stride)
3837 {
3838 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3839 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3840 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3841 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3842 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3843 bool predicating = cmd_buffer->state.predicating;
3844 assert(base_reg);
3845
3846 /* just reset draw state for vertex data */
3847 cmd_buffer->state.last_first_instance = -1;
3848 cmd_buffer->state.last_num_instances = -1;
3849 cmd_buffer->state.last_vertex_offset = -1;
3850
3851 if (draw_count == 1 && !count_va && !draw_id_enable) {
3852 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3853 PKT3_DRAW_INDIRECT, 3, predicating));
3854 radeon_emit(cs, 0);
3855 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3856 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3857 radeon_emit(cs, di_src_sel);
3858 } else {
3859 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3860 PKT3_DRAW_INDIRECT_MULTI,
3861 8, predicating));
3862 radeon_emit(cs, 0);
3863 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3864 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3865 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3866 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3867 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3868 radeon_emit(cs, draw_count); /* count */
3869 radeon_emit(cs, count_va); /* count_addr */
3870 radeon_emit(cs, count_va >> 32);
3871 radeon_emit(cs, stride); /* stride */
3872 radeon_emit(cs, di_src_sel);
3873 }
3874 }
3875
3876 static void
3877 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3878 const struct radv_draw_info *info)
3879 {
3880 struct radv_cmd_state *state = &cmd_buffer->state;
3881 struct radeon_winsys *ws = cmd_buffer->device->ws;
3882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3883
3884 if (info->indirect) {
3885 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3886 uint64_t count_va = 0;
3887
3888 va += info->indirect->offset + info->indirect_offset;
3889
3890 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3891
3892 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3893 radeon_emit(cs, 1);
3894 radeon_emit(cs, va);
3895 radeon_emit(cs, va >> 32);
3896
3897 if (info->count_buffer) {
3898 count_va = radv_buffer_get_va(info->count_buffer->bo);
3899 count_va += info->count_buffer->offset +
3900 info->count_buffer_offset;
3901
3902 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3903 }
3904
3905 if (!state->subpass->view_mask) {
3906 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3907 info->indexed,
3908 info->count,
3909 count_va,
3910 info->stride);
3911 } else {
3912 unsigned i;
3913 for_each_bit(i, state->subpass->view_mask) {
3914 radv_emit_view_index(cmd_buffer, i);
3915
3916 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3917 info->indexed,
3918 info->count,
3919 count_va,
3920 info->stride);
3921 }
3922 }
3923 } else {
3924 assert(state->pipeline->graphics.vtx_base_sgpr);
3925
3926 if (info->vertex_offset != state->last_vertex_offset ||
3927 info->first_instance != state->last_first_instance) {
3928 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3929 state->pipeline->graphics.vtx_emit_num);
3930
3931 radeon_emit(cs, info->vertex_offset);
3932 radeon_emit(cs, info->first_instance);
3933 if (state->pipeline->graphics.vtx_emit_num == 3)
3934 radeon_emit(cs, 0);
3935 state->last_first_instance = info->first_instance;
3936 state->last_vertex_offset = info->vertex_offset;
3937 }
3938
3939 if (state->last_num_instances != info->instance_count) {
3940 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3941 radeon_emit(cs, info->instance_count);
3942 state->last_num_instances = info->instance_count;
3943 }
3944
3945 if (info->indexed) {
3946 int index_size = state->index_type ? 4 : 2;
3947 uint64_t index_va;
3948
3949 index_va = state->index_va;
3950 index_va += info->first_index * index_size;
3951
3952 if (!state->subpass->view_mask) {
3953 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3954 index_va,
3955 info->count);
3956 } else {
3957 unsigned i;
3958 for_each_bit(i, state->subpass->view_mask) {
3959 radv_emit_view_index(cmd_buffer, i);
3960
3961 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3962 index_va,
3963 info->count);
3964 }
3965 }
3966 } else {
3967 if (!state->subpass->view_mask) {
3968 radv_cs_emit_draw_packet(cmd_buffer,
3969 info->count,
3970 !!info->strmout_buffer);
3971 } else {
3972 unsigned i;
3973 for_each_bit(i, state->subpass->view_mask) {
3974 radv_emit_view_index(cmd_buffer, i);
3975
3976 radv_cs_emit_draw_packet(cmd_buffer,
3977 info->count,
3978 !!info->strmout_buffer);
3979 }
3980 }
3981 }
3982 }
3983 }
3984
3985 /*
3986 * Vega and raven have a bug which triggers if there are multiple context
3987 * register contexts active at the same time with different scissor values.
3988 *
3989 * There are two possible workarounds:
3990 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3991 * there is only ever 1 active set of scissor values at the same time.
3992 *
3993 * 2) Whenever the hardware switches contexts we have to set the scissor
3994 * registers again even if it is a noop. That way the new context gets
3995 * the correct scissor values.
3996 *
3997 * This implements option 2. radv_need_late_scissor_emission needs to
3998 * return true on affected HW if radv_emit_all_graphics_states sets
3999 * any context registers.
4000 */
4001 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4002 const struct radv_draw_info *info)
4003 {
4004 struct radv_cmd_state *state = &cmd_buffer->state;
4005
4006 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4007 return false;
4008
4009 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4010 return true;
4011
4012 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4013
4014 /* Index, vertex and streamout buffers don't change context regs, and
4015 * pipeline is already handled.
4016 */
4017 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4018 RADV_CMD_DIRTY_VERTEX_BUFFER |
4019 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4020 RADV_CMD_DIRTY_PIPELINE);
4021
4022 if (cmd_buffer->state.dirty & used_states)
4023 return true;
4024
4025 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4026 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4027 return true;
4028
4029 return false;
4030 }
4031
4032 static void
4033 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4034 const struct radv_draw_info *info)
4035 {
4036 bool late_scissor_emission;
4037
4038 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4039 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4040 radv_emit_rbplus_state(cmd_buffer);
4041
4042 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4043 radv_emit_graphics_pipeline(cmd_buffer);
4044
4045 /* This should be before the cmd_buffer->state.dirty is cleared
4046 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4047 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4048 late_scissor_emission =
4049 radv_need_late_scissor_emission(cmd_buffer, info);
4050
4051 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4052 radv_emit_framebuffer_state(cmd_buffer);
4053
4054 if (info->indexed) {
4055 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4056 radv_emit_index_buffer(cmd_buffer);
4057 } else {
4058 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4059 * so the state must be re-emitted before the next indexed
4060 * draw.
4061 */
4062 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4063 cmd_buffer->state.last_index_type = -1;
4064 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4065 }
4066 }
4067
4068 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4069
4070 radv_emit_draw_registers(cmd_buffer, info);
4071
4072 if (late_scissor_emission)
4073 radv_emit_scissor(cmd_buffer);
4074 }
4075
4076 static void
4077 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4078 const struct radv_draw_info *info)
4079 {
4080 struct radeon_info *rad_info =
4081 &cmd_buffer->device->physical_device->rad_info;
4082 bool has_prefetch =
4083 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4084 bool pipeline_is_dirty =
4085 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4086 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4087
4088 MAYBE_UNUSED unsigned cdw_max =
4089 radeon_check_space(cmd_buffer->device->ws,
4090 cmd_buffer->cs, 4096);
4091
4092 if (likely(!info->indirect)) {
4093 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4094 * no workaround for indirect draws, but we can at least skip
4095 * direct draws.
4096 */
4097 if (unlikely(!info->instance_count))
4098 return;
4099
4100 /* Handle count == 0. */
4101 if (unlikely(!info->count && !info->strmout_buffer))
4102 return;
4103 }
4104
4105 /* Use optimal packet order based on whether we need to sync the
4106 * pipeline.
4107 */
4108 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4109 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4110 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4111 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4112 /* If we have to wait for idle, set all states first, so that
4113 * all SET packets are processed in parallel with previous draw
4114 * calls. Then upload descriptors, set shader pointers, and
4115 * draw, and prefetch at the end. This ensures that the time
4116 * the CUs are idle is very short. (there are only SET_SH
4117 * packets between the wait and the draw)
4118 */
4119 radv_emit_all_graphics_states(cmd_buffer, info);
4120 si_emit_cache_flush(cmd_buffer);
4121 /* <-- CUs are idle here --> */
4122
4123 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4124
4125 radv_emit_draw_packets(cmd_buffer, info);
4126 /* <-- CUs are busy here --> */
4127
4128 /* Start prefetches after the draw has been started. Both will
4129 * run in parallel, but starting the draw first is more
4130 * important.
4131 */
4132 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4133 radv_emit_prefetch_L2(cmd_buffer,
4134 cmd_buffer->state.pipeline, false);
4135 }
4136 } else {
4137 /* If we don't wait for idle, start prefetches first, then set
4138 * states, and draw at the end.
4139 */
4140 si_emit_cache_flush(cmd_buffer);
4141
4142 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4143 /* Only prefetch the vertex shader and VBO descriptors
4144 * in order to start the draw as soon as possible.
4145 */
4146 radv_emit_prefetch_L2(cmd_buffer,
4147 cmd_buffer->state.pipeline, true);
4148 }
4149
4150 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4151
4152 radv_emit_all_graphics_states(cmd_buffer, info);
4153 radv_emit_draw_packets(cmd_buffer, info);
4154
4155 /* Prefetch the remaining shaders after the draw has been
4156 * started.
4157 */
4158 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4159 radv_emit_prefetch_L2(cmd_buffer,
4160 cmd_buffer->state.pipeline, false);
4161 }
4162 }
4163
4164 /* Workaround for a VGT hang when streamout is enabled.
4165 * It must be done after drawing.
4166 */
4167 if (cmd_buffer->state.streamout.streamout_enabled &&
4168 (rad_info->family == CHIP_HAWAII ||
4169 rad_info->family == CHIP_TONGA ||
4170 rad_info->family == CHIP_FIJI)) {
4171 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4172 }
4173
4174 assert(cmd_buffer->cs->cdw <= cdw_max);
4175 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4176 }
4177
4178 void radv_CmdDraw(
4179 VkCommandBuffer commandBuffer,
4180 uint32_t vertexCount,
4181 uint32_t instanceCount,
4182 uint32_t firstVertex,
4183 uint32_t firstInstance)
4184 {
4185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4186 struct radv_draw_info info = {};
4187
4188 info.count = vertexCount;
4189 info.instance_count = instanceCount;
4190 info.first_instance = firstInstance;
4191 info.vertex_offset = firstVertex;
4192
4193 radv_draw(cmd_buffer, &info);
4194 }
4195
4196 void radv_CmdDrawIndexed(
4197 VkCommandBuffer commandBuffer,
4198 uint32_t indexCount,
4199 uint32_t instanceCount,
4200 uint32_t firstIndex,
4201 int32_t vertexOffset,
4202 uint32_t firstInstance)
4203 {
4204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4205 struct radv_draw_info info = {};
4206
4207 info.indexed = true;
4208 info.count = indexCount;
4209 info.instance_count = instanceCount;
4210 info.first_index = firstIndex;
4211 info.vertex_offset = vertexOffset;
4212 info.first_instance = firstInstance;
4213
4214 radv_draw(cmd_buffer, &info);
4215 }
4216
4217 void radv_CmdDrawIndirect(
4218 VkCommandBuffer commandBuffer,
4219 VkBuffer _buffer,
4220 VkDeviceSize offset,
4221 uint32_t drawCount,
4222 uint32_t stride)
4223 {
4224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4225 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4226 struct radv_draw_info info = {};
4227
4228 info.count = drawCount;
4229 info.indirect = buffer;
4230 info.indirect_offset = offset;
4231 info.stride = stride;
4232
4233 radv_draw(cmd_buffer, &info);
4234 }
4235
4236 void radv_CmdDrawIndexedIndirect(
4237 VkCommandBuffer commandBuffer,
4238 VkBuffer _buffer,
4239 VkDeviceSize offset,
4240 uint32_t drawCount,
4241 uint32_t stride)
4242 {
4243 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4244 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4245 struct radv_draw_info info = {};
4246
4247 info.indexed = true;
4248 info.count = drawCount;
4249 info.indirect = buffer;
4250 info.indirect_offset = offset;
4251 info.stride = stride;
4252
4253 radv_draw(cmd_buffer, &info);
4254 }
4255
4256 void radv_CmdDrawIndirectCountKHR(
4257 VkCommandBuffer commandBuffer,
4258 VkBuffer _buffer,
4259 VkDeviceSize offset,
4260 VkBuffer _countBuffer,
4261 VkDeviceSize countBufferOffset,
4262 uint32_t maxDrawCount,
4263 uint32_t stride)
4264 {
4265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4266 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4267 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4268 struct radv_draw_info info = {};
4269
4270 info.count = maxDrawCount;
4271 info.indirect = buffer;
4272 info.indirect_offset = offset;
4273 info.count_buffer = count_buffer;
4274 info.count_buffer_offset = countBufferOffset;
4275 info.stride = stride;
4276
4277 radv_draw(cmd_buffer, &info);
4278 }
4279
4280 void radv_CmdDrawIndexedIndirectCountKHR(
4281 VkCommandBuffer commandBuffer,
4282 VkBuffer _buffer,
4283 VkDeviceSize offset,
4284 VkBuffer _countBuffer,
4285 VkDeviceSize countBufferOffset,
4286 uint32_t maxDrawCount,
4287 uint32_t stride)
4288 {
4289 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4290 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4291 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4292 struct radv_draw_info info = {};
4293
4294 info.indexed = true;
4295 info.count = maxDrawCount;
4296 info.indirect = buffer;
4297 info.indirect_offset = offset;
4298 info.count_buffer = count_buffer;
4299 info.count_buffer_offset = countBufferOffset;
4300 info.stride = stride;
4301
4302 radv_draw(cmd_buffer, &info);
4303 }
4304
4305 struct radv_dispatch_info {
4306 /**
4307 * Determine the layout of the grid (in block units) to be used.
4308 */
4309 uint32_t blocks[3];
4310
4311 /**
4312 * A starting offset for the grid. If unaligned is set, the offset
4313 * must still be aligned.
4314 */
4315 uint32_t offsets[3];
4316 /**
4317 * Whether it's an unaligned compute dispatch.
4318 */
4319 bool unaligned;
4320
4321 /**
4322 * Indirect compute parameters resource.
4323 */
4324 struct radv_buffer *indirect;
4325 uint64_t indirect_offset;
4326 };
4327
4328 static void
4329 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4330 const struct radv_dispatch_info *info)
4331 {
4332 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4333 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4334 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4335 struct radeon_winsys *ws = cmd_buffer->device->ws;
4336 bool predicating = cmd_buffer->state.predicating;
4337 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4338 struct radv_userdata_info *loc;
4339
4340 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4341 AC_UD_CS_GRID_SIZE);
4342
4343 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4344
4345 if (info->indirect) {
4346 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4347
4348 va += info->indirect->offset + info->indirect_offset;
4349
4350 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4351
4352 if (loc->sgpr_idx != -1) {
4353 for (unsigned i = 0; i < 3; ++i) {
4354 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4355 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4356 COPY_DATA_DST_SEL(COPY_DATA_REG));
4357 radeon_emit(cs, (va + 4 * i));
4358 radeon_emit(cs, (va + 4 * i) >> 32);
4359 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4360 + loc->sgpr_idx * 4) >> 2) + i);
4361 radeon_emit(cs, 0);
4362 }
4363 }
4364
4365 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4366 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4367 PKT3_SHADER_TYPE_S(1));
4368 radeon_emit(cs, va);
4369 radeon_emit(cs, va >> 32);
4370 radeon_emit(cs, dispatch_initiator);
4371 } else {
4372 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4373 PKT3_SHADER_TYPE_S(1));
4374 radeon_emit(cs, 1);
4375 radeon_emit(cs, va);
4376 radeon_emit(cs, va >> 32);
4377
4378 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4379 PKT3_SHADER_TYPE_S(1));
4380 radeon_emit(cs, 0);
4381 radeon_emit(cs, dispatch_initiator);
4382 }
4383 } else {
4384 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4385 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4386
4387 if (info->unaligned) {
4388 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4389 unsigned remainder[3];
4390
4391 /* If aligned, these should be an entire block size,
4392 * not 0.
4393 */
4394 remainder[0] = blocks[0] + cs_block_size[0] -
4395 align_u32_npot(blocks[0], cs_block_size[0]);
4396 remainder[1] = blocks[1] + cs_block_size[1] -
4397 align_u32_npot(blocks[1], cs_block_size[1]);
4398 remainder[2] = blocks[2] + cs_block_size[2] -
4399 align_u32_npot(blocks[2], cs_block_size[2]);
4400
4401 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4402 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4403 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4404
4405 for(unsigned i = 0; i < 3; ++i) {
4406 assert(offsets[i] % cs_block_size[i] == 0);
4407 offsets[i] /= cs_block_size[i];
4408 }
4409
4410 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4411 radeon_emit(cs,
4412 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4413 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4414 radeon_emit(cs,
4415 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4416 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4417 radeon_emit(cs,
4418 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4419 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4420
4421 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4422 }
4423
4424 if (loc->sgpr_idx != -1) {
4425 assert(loc->num_sgprs == 3);
4426
4427 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4428 loc->sgpr_idx * 4, 3);
4429 radeon_emit(cs, blocks[0]);
4430 radeon_emit(cs, blocks[1]);
4431 radeon_emit(cs, blocks[2]);
4432 }
4433
4434 if (offsets[0] || offsets[1] || offsets[2]) {
4435 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4436 radeon_emit(cs, offsets[0]);
4437 radeon_emit(cs, offsets[1]);
4438 radeon_emit(cs, offsets[2]);
4439
4440 /* The blocks in the packet are not counts but end values. */
4441 for (unsigned i = 0; i < 3; ++i)
4442 blocks[i] += offsets[i];
4443 } else {
4444 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4445 }
4446
4447 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4448 PKT3_SHADER_TYPE_S(1));
4449 radeon_emit(cs, blocks[0]);
4450 radeon_emit(cs, blocks[1]);
4451 radeon_emit(cs, blocks[2]);
4452 radeon_emit(cs, dispatch_initiator);
4453 }
4454
4455 assert(cmd_buffer->cs->cdw <= cdw_max);
4456 }
4457
4458 static void
4459 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4460 {
4461 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4462 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4463 }
4464
4465 static void
4466 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4467 const struct radv_dispatch_info *info)
4468 {
4469 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4470 bool has_prefetch =
4471 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4472 bool pipeline_is_dirty = pipeline &&
4473 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4474
4475 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4476 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4477 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4478 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4479 /* If we have to wait for idle, set all states first, so that
4480 * all SET packets are processed in parallel with previous draw
4481 * calls. Then upload descriptors, set shader pointers, and
4482 * dispatch, and prefetch at the end. This ensures that the
4483 * time the CUs are idle is very short. (there are only SET_SH
4484 * packets between the wait and the draw)
4485 */
4486 radv_emit_compute_pipeline(cmd_buffer);
4487 si_emit_cache_flush(cmd_buffer);
4488 /* <-- CUs are idle here --> */
4489
4490 radv_upload_compute_shader_descriptors(cmd_buffer);
4491
4492 radv_emit_dispatch_packets(cmd_buffer, info);
4493 /* <-- CUs are busy here --> */
4494
4495 /* Start prefetches after the dispatch has been started. Both
4496 * will run in parallel, but starting the dispatch first is
4497 * more important.
4498 */
4499 if (has_prefetch && pipeline_is_dirty) {
4500 radv_emit_shader_prefetch(cmd_buffer,
4501 pipeline->shaders[MESA_SHADER_COMPUTE]);
4502 }
4503 } else {
4504 /* If we don't wait for idle, start prefetches first, then set
4505 * states, and dispatch at the end.
4506 */
4507 si_emit_cache_flush(cmd_buffer);
4508
4509 if (has_prefetch && pipeline_is_dirty) {
4510 radv_emit_shader_prefetch(cmd_buffer,
4511 pipeline->shaders[MESA_SHADER_COMPUTE]);
4512 }
4513
4514 radv_upload_compute_shader_descriptors(cmd_buffer);
4515
4516 radv_emit_compute_pipeline(cmd_buffer);
4517 radv_emit_dispatch_packets(cmd_buffer, info);
4518 }
4519
4520 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4521 }
4522
4523 void radv_CmdDispatchBase(
4524 VkCommandBuffer commandBuffer,
4525 uint32_t base_x,
4526 uint32_t base_y,
4527 uint32_t base_z,
4528 uint32_t x,
4529 uint32_t y,
4530 uint32_t z)
4531 {
4532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4533 struct radv_dispatch_info info = {};
4534
4535 info.blocks[0] = x;
4536 info.blocks[1] = y;
4537 info.blocks[2] = z;
4538
4539 info.offsets[0] = base_x;
4540 info.offsets[1] = base_y;
4541 info.offsets[2] = base_z;
4542 radv_dispatch(cmd_buffer, &info);
4543 }
4544
4545 void radv_CmdDispatch(
4546 VkCommandBuffer commandBuffer,
4547 uint32_t x,
4548 uint32_t y,
4549 uint32_t z)
4550 {
4551 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4552 }
4553
4554 void radv_CmdDispatchIndirect(
4555 VkCommandBuffer commandBuffer,
4556 VkBuffer _buffer,
4557 VkDeviceSize offset)
4558 {
4559 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4560 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4561 struct radv_dispatch_info info = {};
4562
4563 info.indirect = buffer;
4564 info.indirect_offset = offset;
4565
4566 radv_dispatch(cmd_buffer, &info);
4567 }
4568
4569 void radv_unaligned_dispatch(
4570 struct radv_cmd_buffer *cmd_buffer,
4571 uint32_t x,
4572 uint32_t y,
4573 uint32_t z)
4574 {
4575 struct radv_dispatch_info info = {};
4576
4577 info.blocks[0] = x;
4578 info.blocks[1] = y;
4579 info.blocks[2] = z;
4580 info.unaligned = 1;
4581
4582 radv_dispatch(cmd_buffer, &info);
4583 }
4584
4585 void radv_CmdEndRenderPass(
4586 VkCommandBuffer commandBuffer)
4587 {
4588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4589
4590 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4591
4592 radv_cmd_buffer_end_subpass(cmd_buffer);
4593
4594 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4595
4596 cmd_buffer->state.pass = NULL;
4597 cmd_buffer->state.subpass = NULL;
4598 cmd_buffer->state.attachments = NULL;
4599 cmd_buffer->state.framebuffer = NULL;
4600 }
4601
4602 void radv_CmdEndRenderPass2KHR(
4603 VkCommandBuffer commandBuffer,
4604 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4605 {
4606 radv_CmdEndRenderPass(commandBuffer);
4607 }
4608
4609 /*
4610 * For HTILE we have the following interesting clear words:
4611 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4612 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4613 * 0xfffffff0: Clear depth to 1.0
4614 * 0x00000000: Clear depth to 0.0
4615 */
4616 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4617 struct radv_image *image,
4618 const VkImageSubresourceRange *range,
4619 uint32_t clear_word)
4620 {
4621 assert(range->baseMipLevel == 0);
4622 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4623 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4624 struct radv_cmd_state *state = &cmd_buffer->state;
4625 VkClearDepthStencilValue value = {};
4626
4627 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4628 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4629
4630 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4631
4632 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4633
4634 if (vk_format_is_stencil(image->vk_format))
4635 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4636
4637 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4638
4639 if (radv_image_is_tc_compat_htile(image)) {
4640 /* Initialize the TC-compat metada value to 0 because by
4641 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4642 * need have to conditionally update its value when performing
4643 * a fast depth clear.
4644 */
4645 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4646 }
4647 }
4648
4649 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4650 struct radv_image *image,
4651 VkImageLayout src_layout,
4652 VkImageLayout dst_layout,
4653 unsigned src_queue_mask,
4654 unsigned dst_queue_mask,
4655 const VkImageSubresourceRange *range,
4656 struct radv_sample_locations_state *sample_locs)
4657 {
4658 if (!radv_image_has_htile(image))
4659 return;
4660
4661 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4662 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4663
4664 if (radv_layout_is_htile_compressed(image, dst_layout,
4665 dst_queue_mask)) {
4666 clear_value = 0;
4667 }
4668
4669 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4670 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4671 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4672 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4673 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4674 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4675 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4676 VkImageSubresourceRange local_range = *range;
4677 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4678 local_range.baseMipLevel = 0;
4679 local_range.levelCount = 1;
4680
4681 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4682 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4683
4684 radv_decompress_depth_image_inplace(cmd_buffer, image,
4685 &local_range, sample_locs);
4686
4687 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4688 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4689 }
4690 }
4691
4692 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4693 struct radv_image *image, uint32_t value)
4694 {
4695 struct radv_cmd_state *state = &cmd_buffer->state;
4696
4697 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4698 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4699
4700 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4701
4702 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4703 }
4704
4705 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4706 struct radv_image *image)
4707 {
4708 struct radv_cmd_state *state = &cmd_buffer->state;
4709 static const uint32_t fmask_clear_values[4] = {
4710 0x00000000,
4711 0x02020202,
4712 0xE4E4E4E4,
4713 0x76543210
4714 };
4715 uint32_t log2_samples = util_logbase2(image->info.samples);
4716 uint32_t value = fmask_clear_values[log2_samples];
4717
4718 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4719 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4720
4721 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4722
4723 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4724 }
4725
4726 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4727 struct radv_image *image, uint32_t value)
4728 {
4729 struct radv_cmd_state *state = &cmd_buffer->state;
4730
4731 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4732 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4733
4734 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4735
4736 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4737 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4738 }
4739
4740 /**
4741 * Initialize DCC/FMASK/CMASK metadata for a color image.
4742 */
4743 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4744 struct radv_image *image,
4745 VkImageLayout src_layout,
4746 VkImageLayout dst_layout,
4747 unsigned src_queue_mask,
4748 unsigned dst_queue_mask)
4749 {
4750 if (radv_image_has_cmask(image)) {
4751 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4752
4753 /* TODO: clarify this. */
4754 if (radv_image_has_fmask(image)) {
4755 value = 0xccccccccu;
4756 }
4757
4758 radv_initialise_cmask(cmd_buffer, image, value);
4759 }
4760
4761 if (radv_image_has_fmask(image)) {
4762 radv_initialize_fmask(cmd_buffer, image);
4763 }
4764
4765 if (radv_image_has_dcc(image)) {
4766 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4767 bool need_decompress_pass = false;
4768
4769 if (radv_layout_dcc_compressed(image, dst_layout,
4770 dst_queue_mask)) {
4771 value = 0x20202020u;
4772 need_decompress_pass = true;
4773 }
4774
4775 radv_initialize_dcc(cmd_buffer, image, value);
4776
4777 radv_update_fce_metadata(cmd_buffer, image,
4778 need_decompress_pass);
4779 }
4780
4781 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4782 uint32_t color_values[2] = {};
4783 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4784 }
4785 }
4786
4787 /**
4788 * Handle color image transitions for DCC/FMASK/CMASK.
4789 */
4790 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4791 struct radv_image *image,
4792 VkImageLayout src_layout,
4793 VkImageLayout dst_layout,
4794 unsigned src_queue_mask,
4795 unsigned dst_queue_mask,
4796 const VkImageSubresourceRange *range)
4797 {
4798 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4799 radv_init_color_image_metadata(cmd_buffer, image,
4800 src_layout, dst_layout,
4801 src_queue_mask, dst_queue_mask);
4802 return;
4803 }
4804
4805 if (radv_image_has_dcc(image)) {
4806 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4807 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4808 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4809 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4810 radv_decompress_dcc(cmd_buffer, image, range);
4811 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4812 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4813 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4814 }
4815 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4816 bool fce_eliminate = false, fmask_expand = false;
4817
4818 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4819 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4820 fce_eliminate = true;
4821 }
4822
4823 if (radv_image_has_fmask(image)) {
4824 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4825 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4826 /* A FMASK decompress is required before doing
4827 * a MSAA decompress using FMASK.
4828 */
4829 fmask_expand = true;
4830 }
4831 }
4832
4833 if (fce_eliminate || fmask_expand)
4834 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4835
4836 if (fmask_expand)
4837 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4838 }
4839 }
4840
4841 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4842 struct radv_image *image,
4843 VkImageLayout src_layout,
4844 VkImageLayout dst_layout,
4845 uint32_t src_family,
4846 uint32_t dst_family,
4847 const VkImageSubresourceRange *range,
4848 struct radv_sample_locations_state *sample_locs)
4849 {
4850 if (image->exclusive && src_family != dst_family) {
4851 /* This is an acquire or a release operation and there will be
4852 * a corresponding release/acquire. Do the transition in the
4853 * most flexible queue. */
4854
4855 assert(src_family == cmd_buffer->queue_family_index ||
4856 dst_family == cmd_buffer->queue_family_index);
4857
4858 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4859 return;
4860
4861 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4862 (src_family == RADV_QUEUE_GENERAL ||
4863 dst_family == RADV_QUEUE_GENERAL))
4864 return;
4865 }
4866
4867 if (src_layout == dst_layout)
4868 return;
4869
4870 unsigned src_queue_mask =
4871 radv_image_queue_family_mask(image, src_family,
4872 cmd_buffer->queue_family_index);
4873 unsigned dst_queue_mask =
4874 radv_image_queue_family_mask(image, dst_family,
4875 cmd_buffer->queue_family_index);
4876
4877 if (vk_format_is_depth(image->vk_format)) {
4878 radv_handle_depth_image_transition(cmd_buffer, image,
4879 src_layout, dst_layout,
4880 src_queue_mask, dst_queue_mask,
4881 range, sample_locs);
4882 } else {
4883 radv_handle_color_image_transition(cmd_buffer, image,
4884 src_layout, dst_layout,
4885 src_queue_mask, dst_queue_mask,
4886 range);
4887 }
4888 }
4889
4890 struct radv_barrier_info {
4891 uint32_t eventCount;
4892 const VkEvent *pEvents;
4893 VkPipelineStageFlags srcStageMask;
4894 VkPipelineStageFlags dstStageMask;
4895 };
4896
4897 static void
4898 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4899 uint32_t memoryBarrierCount,
4900 const VkMemoryBarrier *pMemoryBarriers,
4901 uint32_t bufferMemoryBarrierCount,
4902 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4903 uint32_t imageMemoryBarrierCount,
4904 const VkImageMemoryBarrier *pImageMemoryBarriers,
4905 const struct radv_barrier_info *info)
4906 {
4907 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4908 enum radv_cmd_flush_bits src_flush_bits = 0;
4909 enum radv_cmd_flush_bits dst_flush_bits = 0;
4910
4911 for (unsigned i = 0; i < info->eventCount; ++i) {
4912 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4913 uint64_t va = radv_buffer_get_va(event->bo);
4914
4915 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4916
4917 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4918
4919 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4920 assert(cmd_buffer->cs->cdw <= cdw_max);
4921 }
4922
4923 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4924 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4925 NULL);
4926 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4927 NULL);
4928 }
4929
4930 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4931 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4932 NULL);
4933 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4934 NULL);
4935 }
4936
4937 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4938 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4939
4940 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4941 image);
4942 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4943 image);
4944 }
4945
4946 /* The Vulkan spec 1.1.98 says:
4947 *
4948 * "An execution dependency with only
4949 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4950 * will only prevent that stage from executing in subsequently
4951 * submitted commands. As this stage does not perform any actual
4952 * execution, this is not observable - in effect, it does not delay
4953 * processing of subsequent commands. Similarly an execution dependency
4954 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4955 * will effectively not wait for any prior commands to complete."
4956 */
4957 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4958 radv_stage_flush(cmd_buffer, info->srcStageMask);
4959 cmd_buffer->state.flush_bits |= src_flush_bits;
4960
4961 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4962 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4963
4964 const struct VkSampleLocationsInfoEXT *sample_locs_info =
4965 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
4966 SAMPLE_LOCATIONS_INFO_EXT);
4967 struct radv_sample_locations_state sample_locations = {};
4968
4969 if (sample_locs_info) {
4970 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
4971 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
4972 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
4973 sample_locations.count = sample_locs_info->sampleLocationsCount;
4974 typed_memcpy(&sample_locations.locations[0],
4975 sample_locs_info->pSampleLocations,
4976 sample_locs_info->sampleLocationsCount);
4977 }
4978
4979 radv_handle_image_transition(cmd_buffer, image,
4980 pImageMemoryBarriers[i].oldLayout,
4981 pImageMemoryBarriers[i].newLayout,
4982 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4983 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4984 &pImageMemoryBarriers[i].subresourceRange,
4985 sample_locs_info ? &sample_locations : NULL);
4986 }
4987
4988 /* Make sure CP DMA is idle because the driver might have performed a
4989 * DMA operation for copying or filling buffers/images.
4990 */
4991 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4992 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4993 si_cp_dma_wait_for_idle(cmd_buffer);
4994
4995 cmd_buffer->state.flush_bits |= dst_flush_bits;
4996 }
4997
4998 void radv_CmdPipelineBarrier(
4999 VkCommandBuffer commandBuffer,
5000 VkPipelineStageFlags srcStageMask,
5001 VkPipelineStageFlags destStageMask,
5002 VkBool32 byRegion,
5003 uint32_t memoryBarrierCount,
5004 const VkMemoryBarrier* pMemoryBarriers,
5005 uint32_t bufferMemoryBarrierCount,
5006 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5007 uint32_t imageMemoryBarrierCount,
5008 const VkImageMemoryBarrier* pImageMemoryBarriers)
5009 {
5010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5011 struct radv_barrier_info info;
5012
5013 info.eventCount = 0;
5014 info.pEvents = NULL;
5015 info.srcStageMask = srcStageMask;
5016 info.dstStageMask = destStageMask;
5017
5018 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5019 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5020 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5021 }
5022
5023
5024 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5025 struct radv_event *event,
5026 VkPipelineStageFlags stageMask,
5027 unsigned value)
5028 {
5029 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5030 uint64_t va = radv_buffer_get_va(event->bo);
5031
5032 si_emit_cache_flush(cmd_buffer);
5033
5034 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5035
5036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5037
5038 /* Flags that only require a top-of-pipe event. */
5039 VkPipelineStageFlags top_of_pipe_flags =
5040 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5041
5042 /* Flags that only require a post-index-fetch event. */
5043 VkPipelineStageFlags post_index_fetch_flags =
5044 top_of_pipe_flags |
5045 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5046 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5047
5048 /* Make sure CP DMA is idle because the driver might have performed a
5049 * DMA operation for copying or filling buffers/images.
5050 */
5051 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5052 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5053 si_cp_dma_wait_for_idle(cmd_buffer);
5054
5055 /* TODO: Emit EOS events for syncing PS/CS stages. */
5056
5057 if (!(stageMask & ~top_of_pipe_flags)) {
5058 /* Just need to sync the PFP engine. */
5059 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5060 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5061 S_370_WR_CONFIRM(1) |
5062 S_370_ENGINE_SEL(V_370_PFP));
5063 radeon_emit(cs, va);
5064 radeon_emit(cs, va >> 32);
5065 radeon_emit(cs, value);
5066 } else if (!(stageMask & ~post_index_fetch_flags)) {
5067 /* Sync ME because PFP reads index and indirect buffers. */
5068 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5069 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5070 S_370_WR_CONFIRM(1) |
5071 S_370_ENGINE_SEL(V_370_ME));
5072 radeon_emit(cs, va);
5073 radeon_emit(cs, va >> 32);
5074 radeon_emit(cs, value);
5075 } else {
5076 /* Otherwise, sync all prior GPU work using an EOP event. */
5077 si_cs_emit_write_event_eop(cs,
5078 cmd_buffer->device->physical_device->rad_info.chip_class,
5079 radv_cmd_buffer_uses_mec(cmd_buffer),
5080 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5081 EOP_DATA_SEL_VALUE_32BIT, va, value,
5082 cmd_buffer->gfx9_eop_bug_va);
5083 }
5084
5085 assert(cmd_buffer->cs->cdw <= cdw_max);
5086 }
5087
5088 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5089 VkEvent _event,
5090 VkPipelineStageFlags stageMask)
5091 {
5092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5093 RADV_FROM_HANDLE(radv_event, event, _event);
5094
5095 write_event(cmd_buffer, event, stageMask, 1);
5096 }
5097
5098 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5099 VkEvent _event,
5100 VkPipelineStageFlags stageMask)
5101 {
5102 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5103 RADV_FROM_HANDLE(radv_event, event, _event);
5104
5105 write_event(cmd_buffer, event, stageMask, 0);
5106 }
5107
5108 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5109 uint32_t eventCount,
5110 const VkEvent* pEvents,
5111 VkPipelineStageFlags srcStageMask,
5112 VkPipelineStageFlags dstStageMask,
5113 uint32_t memoryBarrierCount,
5114 const VkMemoryBarrier* pMemoryBarriers,
5115 uint32_t bufferMemoryBarrierCount,
5116 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5117 uint32_t imageMemoryBarrierCount,
5118 const VkImageMemoryBarrier* pImageMemoryBarriers)
5119 {
5120 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5121 struct radv_barrier_info info;
5122
5123 info.eventCount = eventCount;
5124 info.pEvents = pEvents;
5125 info.srcStageMask = 0;
5126
5127 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5128 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5129 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5130 }
5131
5132
5133 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5134 uint32_t deviceMask)
5135 {
5136 /* No-op */
5137 }
5138
5139 /* VK_EXT_conditional_rendering */
5140 void radv_CmdBeginConditionalRenderingEXT(
5141 VkCommandBuffer commandBuffer,
5142 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5143 {
5144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5145 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5146 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5147 bool draw_visible = true;
5148 uint64_t pred_value = 0;
5149 uint64_t va, new_va;
5150 unsigned pred_offset;
5151
5152 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5153
5154 /* By default, if the 32-bit value at offset in buffer memory is zero,
5155 * then the rendering commands are discarded, otherwise they are
5156 * executed as normal. If the inverted flag is set, all commands are
5157 * discarded if the value is non zero.
5158 */
5159 if (pConditionalRenderingBegin->flags &
5160 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5161 draw_visible = false;
5162 }
5163
5164 si_emit_cache_flush(cmd_buffer);
5165
5166 /* From the Vulkan spec 1.1.107:
5167 *
5168 * "If the 32-bit value at offset in buffer memory is zero, then the
5169 * rendering commands are discarded, otherwise they are executed as
5170 * normal. If the value of the predicate in buffer memory changes while
5171 * conditional rendering is active, the rendering commands may be
5172 * discarded in an implementation-dependent way. Some implementations
5173 * may latch the value of the predicate upon beginning conditional
5174 * rendering while others may read it before every rendering command."
5175 *
5176 * But, the AMD hardware treats the predicate as a 64-bit value which
5177 * means we need a workaround in the driver. Luckily, it's not required
5178 * to support if the value changes when predication is active.
5179 *
5180 * The workaround is as follows:
5181 * 1) allocate a 64-value in the upload BO and initialize it to 0
5182 * 2) copy the 32-bit predicate value to the upload BO
5183 * 3) use the new allocated VA address for predication
5184 *
5185 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5186 * in ME (+ sync PFP) instead of PFP.
5187 */
5188 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5189
5190 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5191
5192 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5193 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5194 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5195 COPY_DATA_WR_CONFIRM);
5196 radeon_emit(cs, va);
5197 radeon_emit(cs, va >> 32);
5198 radeon_emit(cs, new_va);
5199 radeon_emit(cs, new_va >> 32);
5200
5201 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5202 radeon_emit(cs, 0);
5203
5204 /* Enable predication for this command buffer. */
5205 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5206 cmd_buffer->state.predicating = true;
5207
5208 /* Store conditional rendering user info. */
5209 cmd_buffer->state.predication_type = draw_visible;
5210 cmd_buffer->state.predication_va = new_va;
5211 }
5212
5213 void radv_CmdEndConditionalRenderingEXT(
5214 VkCommandBuffer commandBuffer)
5215 {
5216 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5217
5218 /* Disable predication for this command buffer. */
5219 si_emit_set_predication_state(cmd_buffer, false, 0);
5220 cmd_buffer->state.predicating = false;
5221
5222 /* Reset conditional rendering user info. */
5223 cmd_buffer->state.predication_type = -1;
5224 cmd_buffer->state.predication_va = 0;
5225 }
5226
5227 /* VK_EXT_transform_feedback */
5228 void radv_CmdBindTransformFeedbackBuffersEXT(
5229 VkCommandBuffer commandBuffer,
5230 uint32_t firstBinding,
5231 uint32_t bindingCount,
5232 const VkBuffer* pBuffers,
5233 const VkDeviceSize* pOffsets,
5234 const VkDeviceSize* pSizes)
5235 {
5236 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5237 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5238 uint8_t enabled_mask = 0;
5239
5240 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5241 for (uint32_t i = 0; i < bindingCount; i++) {
5242 uint32_t idx = firstBinding + i;
5243
5244 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5245 sb[idx].offset = pOffsets[i];
5246 sb[idx].size = pSizes[i];
5247
5248 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5249 sb[idx].buffer->bo);
5250
5251 enabled_mask |= 1 << idx;
5252 }
5253
5254 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5255
5256 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5257 }
5258
5259 static void
5260 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5261 {
5262 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5263 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5264
5265 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5266 radeon_emit(cs,
5267 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5268 S_028B94_RAST_STREAM(0) |
5269 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5270 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5271 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5272 radeon_emit(cs, so->hw_enabled_mask &
5273 so->enabled_stream_buffers_mask);
5274
5275 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5276 }
5277
5278 static void
5279 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5280 {
5281 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5282 bool old_streamout_enabled = so->streamout_enabled;
5283 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5284
5285 so->streamout_enabled = enable;
5286
5287 so->hw_enabled_mask = so->enabled_mask |
5288 (so->enabled_mask << 4) |
5289 (so->enabled_mask << 8) |
5290 (so->enabled_mask << 12);
5291
5292 if ((old_streamout_enabled != so->streamout_enabled) ||
5293 (old_hw_enabled_mask != so->hw_enabled_mask))
5294 radv_emit_streamout_enable(cmd_buffer);
5295 }
5296
5297 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5298 {
5299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5300 unsigned reg_strmout_cntl;
5301
5302 /* The register is at different places on different ASICs. */
5303 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5304 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5305 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5306 } else {
5307 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5308 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5309 }
5310
5311 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5312 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5313
5314 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5315 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5316 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5317 radeon_emit(cs, 0);
5318 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5319 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5320 radeon_emit(cs, 4); /* poll interval */
5321 }
5322
5323 void radv_CmdBeginTransformFeedbackEXT(
5324 VkCommandBuffer commandBuffer,
5325 uint32_t firstCounterBuffer,
5326 uint32_t counterBufferCount,
5327 const VkBuffer* pCounterBuffers,
5328 const VkDeviceSize* pCounterBufferOffsets)
5329 {
5330 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5331 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5332 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5333 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5334 uint32_t i;
5335
5336 radv_flush_vgt_streamout(cmd_buffer);
5337
5338 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5339 for_each_bit(i, so->enabled_mask) {
5340 int32_t counter_buffer_idx = i - firstCounterBuffer;
5341 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5342 counter_buffer_idx = -1;
5343
5344 /* AMD GCN binds streamout buffers as shader resources.
5345 * VGT only counts primitives and tells the shader through
5346 * SGPRs what to do.
5347 */
5348 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5349 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5350 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5351
5352 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5353
5354 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5355 /* The array of counter buffers is optional. */
5356 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5357 uint64_t va = radv_buffer_get_va(buffer->bo);
5358
5359 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5360
5361 /* Append */
5362 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5363 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5364 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5365 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5366 radeon_emit(cs, 0); /* unused */
5367 radeon_emit(cs, 0); /* unused */
5368 radeon_emit(cs, va); /* src address lo */
5369 radeon_emit(cs, va >> 32); /* src address hi */
5370
5371 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5372 } else {
5373 /* Start from the beginning. */
5374 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5375 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5376 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5377 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5378 radeon_emit(cs, 0); /* unused */
5379 radeon_emit(cs, 0); /* unused */
5380 radeon_emit(cs, 0); /* unused */
5381 radeon_emit(cs, 0); /* unused */
5382 }
5383 }
5384
5385 radv_set_streamout_enable(cmd_buffer, true);
5386 }
5387
5388 void radv_CmdEndTransformFeedbackEXT(
5389 VkCommandBuffer commandBuffer,
5390 uint32_t firstCounterBuffer,
5391 uint32_t counterBufferCount,
5392 const VkBuffer* pCounterBuffers,
5393 const VkDeviceSize* pCounterBufferOffsets)
5394 {
5395 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5396 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5397 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5398 uint32_t i;
5399
5400 radv_flush_vgt_streamout(cmd_buffer);
5401
5402 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5403 for_each_bit(i, so->enabled_mask) {
5404 int32_t counter_buffer_idx = i - firstCounterBuffer;
5405 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5406 counter_buffer_idx = -1;
5407
5408 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5409 /* The array of counters buffer is optional. */
5410 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5411 uint64_t va = radv_buffer_get_va(buffer->bo);
5412
5413 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5414
5415 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5416 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5417 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5418 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5419 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5420 radeon_emit(cs, va); /* dst address lo */
5421 radeon_emit(cs, va >> 32); /* dst address hi */
5422 radeon_emit(cs, 0); /* unused */
5423 radeon_emit(cs, 0); /* unused */
5424
5425 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5426 }
5427
5428 /* Deactivate transform feedback by zeroing the buffer size.
5429 * The counters (primitives generated, primitives emitted) may
5430 * be enabled even if there is not buffer bound. This ensures
5431 * that the primitives-emitted query won't increment.
5432 */
5433 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5434
5435 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5436 }
5437
5438 radv_set_streamout_enable(cmd_buffer, false);
5439 }
5440
5441 void radv_CmdDrawIndirectByteCountEXT(
5442 VkCommandBuffer commandBuffer,
5443 uint32_t instanceCount,
5444 uint32_t firstInstance,
5445 VkBuffer _counterBuffer,
5446 VkDeviceSize counterBufferOffset,
5447 uint32_t counterOffset,
5448 uint32_t vertexStride)
5449 {
5450 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5451 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5452 struct radv_draw_info info = {};
5453
5454 info.instance_count = instanceCount;
5455 info.first_instance = firstInstance;
5456 info.strmout_buffer = counterBuffer;
5457 info.strmout_buffer_offset = counterBufferOffset;
5458 info.stride = vertexStride;
5459
5460 radv_draw(cmd_buffer, &info);
5461 }