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39383b0dbe40052309f1012c822f34d797b91e9f
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_meta.h"
36
37 #include "ac_debug.h"
38
39 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
40 struct radv_image *image,
41 VkImageLayout src_layout,
42 VkImageLayout dst_layout,
43 uint32_t src_family,
44 uint32_t dst_family,
45 const VkImageSubresourceRange *range,
46 VkImageAspectFlags pending_clears);
47
48 const struct radv_dynamic_state default_dynamic_state = {
49 .viewport = {
50 .count = 0,
51 },
52 .scissor = {
53 .count = 0,
54 },
55 .line_width = 1.0f,
56 .depth_bias = {
57 .bias = 0.0f,
58 .clamp = 0.0f,
59 .slope = 0.0f,
60 },
61 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .depth_bounds = {
63 .min = 0.0f,
64 .max = 1.0f,
65 },
66 .stencil_compare_mask = {
67 .front = ~0u,
68 .back = ~0u,
69 },
70 .stencil_write_mask = {
71 .front = ~0u,
72 .back = ~0u,
73 },
74 .stencil_reference = {
75 .front = 0u,
76 .back = 0u,
77 },
78 };
79
80 void
81 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
82 const struct radv_dynamic_state *src,
83 uint32_t copy_mask)
84 {
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
86 dest->viewport.count = src->viewport.count;
87 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
88 src->viewport.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
92 dest->scissor.count = src->scissor.count;
93 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
94 src->scissor.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
98 dest->line_width = src->line_width;
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
101 dest->depth_bias = src->depth_bias;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
104 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
107 dest->depth_bounds = src->depth_bounds;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
110 dest->stencil_compare_mask = src->stencil_compare_mask;
111
112 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
113 dest->stencil_write_mask = src->stencil_write_mask;
114
115 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
116 dest->stencil_reference = src->stencil_reference;
117 }
118
119 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
120 {
121 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
122 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
123 }
124
125 enum ring_type radv_queue_family_to_ring(int f) {
126 switch (f) {
127 case RADV_QUEUE_GENERAL:
128 return RING_GFX;
129 case RADV_QUEUE_COMPUTE:
130 return RING_COMPUTE;
131 case RADV_QUEUE_TRANSFER:
132 return RING_DMA;
133 default:
134 unreachable("Unknown queue family");
135 }
136 }
137
138 static VkResult radv_create_cmd_buffer(
139 struct radv_device * device,
140 struct radv_cmd_pool * pool,
141 VkCommandBufferLevel level,
142 VkCommandBuffer* pCommandBuffer)
143 {
144 struct radv_cmd_buffer *cmd_buffer;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184 }
185
186 static void
187 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
188 {
189 list_del(&cmd_buffer->pool_link);
190
191 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
192 &cmd_buffer->upload.list, list) {
193 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
194 list_del(&up->list);
195 free(up);
196 }
197
198 if (cmd_buffer->upload.upload_bo)
199 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
200 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
201 free(cmd_buffer->push_descriptors.set.mapped_ptr);
202 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
203 }
204
205 static VkResult
206 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
207 {
208
209 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
210
211 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
212 &cmd_buffer->upload.list, list) {
213 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
214 list_del(&up->list);
215 free(up);
216 }
217
218 cmd_buffer->scratch_size_needed = 0;
219 cmd_buffer->compute_scratch_size_needed = 0;
220 cmd_buffer->esgs_ring_size_needed = 0;
221 cmd_buffer->gsvs_ring_size_needed = 0;
222 cmd_buffer->tess_rings_needed = false;
223 cmd_buffer->sample_positions_needed = false;
224
225 if (cmd_buffer->upload.upload_bo)
226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
227 cmd_buffer->upload.upload_bo, 8);
228 cmd_buffer->upload.offset = 0;
229
230 cmd_buffer->record_result = VK_SUCCESS;
231
232 cmd_buffer->ring_offsets_idx = -1;
233
234 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
235 void *fence_ptr;
236 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
237 &cmd_buffer->gfx9_fence_offset,
238 &fence_ptr);
239 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
240 }
241
242 return cmd_buffer->record_result;
243 }
244
245 static bool
246 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
247 uint64_t min_needed)
248 {
249 uint64_t new_size;
250 struct radeon_winsys_bo *bo;
251 struct radv_cmd_buffer_upload *upload;
252 struct radv_device *device = cmd_buffer->device;
253
254 new_size = MAX2(min_needed, 16 * 1024);
255 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
256
257 bo = device->ws->buffer_create(device->ws,
258 new_size, 4096,
259 RADEON_DOMAIN_GTT,
260 RADEON_FLAG_CPU_ACCESS);
261
262 if (!bo) {
263 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
264 return false;
265 }
266
267 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
268 if (cmd_buffer->upload.upload_bo) {
269 upload = malloc(sizeof(*upload));
270
271 if (!upload) {
272 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
273 device->ws->buffer_destroy(bo);
274 return false;
275 }
276
277 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
278 list_add(&upload->list, &cmd_buffer->upload.list);
279 }
280
281 cmd_buffer->upload.upload_bo = bo;
282 cmd_buffer->upload.size = new_size;
283 cmd_buffer->upload.offset = 0;
284 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
285
286 if (!cmd_buffer->upload.map) {
287 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
288 return false;
289 }
290
291 return true;
292 }
293
294 bool
295 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
296 unsigned size,
297 unsigned alignment,
298 unsigned *out_offset,
299 void **ptr)
300 {
301 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
302 if (offset + size > cmd_buffer->upload.size) {
303 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
304 return false;
305 offset = 0;
306 }
307
308 *out_offset = offset;
309 *ptr = cmd_buffer->upload.map + offset;
310
311 cmd_buffer->upload.offset = offset + size;
312 return true;
313 }
314
315 bool
316 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
317 unsigned size, unsigned alignment,
318 const void *data, unsigned *out_offset)
319 {
320 uint8_t *ptr;
321
322 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
323 out_offset, (void **)&ptr))
324 return false;
325
326 if (ptr)
327 memcpy(ptr, data, size);
328
329 return true;
330 }
331
332 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 struct radeon_winsys_cs *cs = cmd_buffer->cs;
336 uint64_t va;
337
338 if (!device->trace_bo)
339 return;
340
341 va = device->ws->buffer_get_va(device->trace_bo);
342 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
343 va += 4;
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371
372 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
373 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
374
375 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
376 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
377 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
378 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
379 }
380 }
381
382 static void
383 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
384 struct radv_pipeline *pipeline)
385 {
386 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
387 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
388 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
389
390 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
391 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
392 }
393
394 /* 12.4 fixed-point */
395 static unsigned radv_pack_float_12p4(float x)
396 {
397 return x <= 0 ? 0 :
398 x >= 4096 ? 0xffff : x * 16;
399 }
400
401 struct ac_userdata_info *
402 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
403 gl_shader_stage stage,
404 int idx)
405 {
406 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
407 }
408
409 static void
410 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
411 struct radv_pipeline *pipeline,
412 gl_shader_stage stage,
413 int idx, uint64_t va)
414 {
415 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
416 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
417 if (loc->sgpr_idx == -1)
418 return;
419 assert(loc->num_sgprs == 2);
420 assert(!loc->indirect);
421 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
422 radeon_emit(cmd_buffer->cs, va);
423 radeon_emit(cmd_buffer->cs, va >> 32);
424 }
425
426 static void
427 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
428 struct radv_pipeline *pipeline)
429 {
430 int num_samples = pipeline->graphics.ms.num_samples;
431 struct radv_multisample_state *ms = &pipeline->graphics.ms;
432 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
433
434 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
435 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
436 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
437
438 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
439 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
440
441 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
442 return;
443
444 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
445 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
446 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
447
448 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
449
450 /* GFX9: Flush DFSM when the AA mode changes. */
451 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
452 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
453 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
454 }
455 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
456 uint32_t offset;
457 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
458 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
459 if (loc->sgpr_idx == -1)
460 return;
461 assert(loc->num_sgprs == 1);
462 assert(!loc->indirect);
463 switch (num_samples) {
464 default:
465 offset = 0;
466 break;
467 case 2:
468 offset = 1;
469 break;
470 case 4:
471 offset = 3;
472 break;
473 case 8:
474 offset = 7;
475 break;
476 case 16:
477 offset = 15;
478 break;
479 }
480
481 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
482 cmd_buffer->sample_positions_needed = true;
483 }
484 }
485
486 static void
487 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
488 struct radv_pipeline *pipeline)
489 {
490 struct radv_raster_state *raster = &pipeline->graphics.raster;
491
492 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
493 raster->pa_cl_clip_cntl);
494
495 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
496 raster->spi_interp_control);
497
498 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
499 unsigned tmp = (unsigned)(1.0 * 8.0);
500 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
501 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
502 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
503
504 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
505 raster->pa_su_vtx_cntl);
506
507 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
508 raster->pa_su_sc_mode_cntl);
509 }
510
511 static inline void
512 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
513 unsigned size)
514 {
515 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
516 si_cp_dma_prefetch(cmd_buffer, va, size);
517 }
518
519 static void
520 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_pipeline *pipeline,
522 struct radv_shader_variant *shader,
523 struct ac_vs_output_info *outinfo)
524 {
525 struct radeon_winsys *ws = cmd_buffer->device->ws;
526 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
527 unsigned export_count;
528
529 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
530 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
531
532 export_count = MAX2(1, outinfo->param_exports);
533 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
534 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
535
536 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
537 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
538 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE) |
541 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
542 V_02870C_SPI_SHADER_4COMP :
543 V_02870C_SPI_SHADER_NONE) |
544 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
545 V_02870C_SPI_SHADER_4COMP :
546 V_02870C_SPI_SHADER_NONE));
547
548
549 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
550 radeon_emit(cmd_buffer->cs, va >> 8);
551 radeon_emit(cmd_buffer->cs, va >> 40);
552 radeon_emit(cmd_buffer->cs, shader->rsrc1);
553 radeon_emit(cmd_buffer->cs, shader->rsrc2);
554
555 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
556 S_028818_VTX_W0_FMT(1) |
557 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
558 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
559 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
560
561
562 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
563 pipeline->graphics.pa_cl_vs_out_cntl);
564
565 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
566 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
567 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
568 }
569
570 static void
571 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_shader_variant *shader,
573 struct ac_es_output_info *outinfo)
574 {
575 struct radeon_winsys *ws = cmd_buffer->device->ws;
576 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
577
578 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
579 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
580
581 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 outinfo->esgs_itemsize / 4);
583 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
584 radeon_emit(cmd_buffer->cs, va >> 8);
585 radeon_emit(cmd_buffer->cs, va >> 40);
586 radeon_emit(cmd_buffer->cs, shader->rsrc1);
587 radeon_emit(cmd_buffer->cs, shader->rsrc2);
588 }
589
590 static void
591 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
592 struct radv_shader_variant *shader)
593 {
594 struct radeon_winsys *ws = cmd_buffer->device->ws;
595 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
596 uint32_t rsrc2 = shader->rsrc2;
597
598 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
599 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
600
601 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
602 radeon_emit(cmd_buffer->cs, va >> 8);
603 radeon_emit(cmd_buffer->cs, va >> 40);
604
605 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
606 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
607 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
608 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
609
610 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
611 radeon_emit(cmd_buffer->cs, shader->rsrc1);
612 radeon_emit(cmd_buffer->cs, rsrc2);
613 }
614
615 static void
616 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
617 struct radv_shader_variant *shader)
618 {
619 struct radeon_winsys *ws = cmd_buffer->device->ws;
620 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
621
622 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
623 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
624
625 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
626 radeon_emit(cmd_buffer->cs, va >> 8);
627 radeon_emit(cmd_buffer->cs, va >> 40);
628 radeon_emit(cmd_buffer->cs, shader->rsrc1);
629 radeon_emit(cmd_buffer->cs, shader->rsrc2);
630 }
631
632 static void
633 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
634 struct radv_pipeline *pipeline)
635 {
636 struct radv_shader_variant *vs;
637
638 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
639
640 vs = pipeline->shaders[MESA_SHADER_VERTEX];
641
642 if (vs->info.vs.as_ls)
643 radv_emit_hw_ls(cmd_buffer, vs);
644 else if (vs->info.vs.as_es)
645 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
646 else
647 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
648
649 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
650 }
651
652
653 static void
654 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
655 struct radv_pipeline *pipeline)
656 {
657 if (!radv_pipeline_has_tess(pipeline))
658 return;
659
660 struct radv_shader_variant *tes, *tcs;
661
662 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
663 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
664
665 if (tes->info.tes.as_es)
666 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
667 else
668 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
669
670 radv_emit_hw_hs(cmd_buffer, tcs);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
673 pipeline->graphics.tess.tf_param);
674
675 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
676 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
677 pipeline->graphics.tess.ls_hs_config);
678 else
679 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
680 pipeline->graphics.tess.ls_hs_config);
681
682 struct ac_userdata_info *loc;
683
684 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
685 if (loc->sgpr_idx != -1) {
686 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
687 assert(loc->num_sgprs == 4);
688 assert(!loc->indirect);
689 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
690 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
691 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
692 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
693 pipeline->graphics.tess.num_tcs_input_cp << 26);
694 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
695 }
696
697 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
698 if (loc->sgpr_idx != -1) {
699 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
700 assert(loc->num_sgprs == 1);
701 assert(!loc->indirect);
702
703 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
704 pipeline->graphics.tess.offchip_layout);
705 }
706
707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
708 if (loc->sgpr_idx != -1) {
709 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
710 assert(loc->num_sgprs == 1);
711 assert(!loc->indirect);
712
713 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
714 pipeline->graphics.tess.tcs_in_layout);
715 }
716 }
717
718 static void
719 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
720 struct radv_pipeline *pipeline)
721 {
722 struct radeon_winsys *ws = cmd_buffer->device->ws;
723 struct radv_shader_variant *gs;
724 uint64_t va;
725
726 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
727
728 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
729 if (!gs)
730 return;
731
732 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
733
734 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
735 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
736 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
737 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
738
739 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
740
741 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
742
743 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
744 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
745 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
746 radeon_emit(cmd_buffer->cs, 0);
747 radeon_emit(cmd_buffer->cs, 0);
748 radeon_emit(cmd_buffer->cs, 0);
749
750 uint32_t gs_num_invocations = gs->info.gs.invocations;
751 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
752 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
753 S_028B90_ENABLE(gs_num_invocations > 0));
754
755 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
756 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
757 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
758
759 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
760 radeon_emit(cmd_buffer->cs, va >> 8);
761 radeon_emit(cmd_buffer->cs, va >> 40);
762 radeon_emit(cmd_buffer->cs, gs->rsrc1);
763 radeon_emit(cmd_buffer->cs, gs->rsrc2);
764
765 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
766
767 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
768 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
769 if (loc->sgpr_idx != -1) {
770 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
771 uint32_t num_entries = 64;
772 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
773
774 if (is_vi)
775 num_entries *= stride;
776
777 stride = S_008F04_STRIDE(stride);
778 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
779 radeon_emit(cmd_buffer->cs, stride);
780 radeon_emit(cmd_buffer->cs, num_entries);
781 }
782 }
783
784 static void
785 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
786 struct radv_pipeline *pipeline)
787 {
788 struct radeon_winsys *ws = cmd_buffer->device->ws;
789 struct radv_shader_variant *ps;
790 uint64_t va;
791 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
792 struct radv_blend_state *blend = &pipeline->graphics.blend;
793 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
794
795 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
796 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
797 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
798 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
799
800 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
801 radeon_emit(cmd_buffer->cs, va >> 8);
802 radeon_emit(cmd_buffer->cs, va >> 40);
803 radeon_emit(cmd_buffer->cs, ps->rsrc1);
804 radeon_emit(cmd_buffer->cs, ps->rsrc2);
805
806 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
807 pipeline->graphics.db_shader_control);
808
809 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
810 ps->config.spi_ps_input_ena);
811
812 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
813 ps->config.spi_ps_input_addr);
814
815 if (ps->info.info.ps.force_persample)
816 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
817
818 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
819 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
820
821 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
822
823 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
824 pipeline->graphics.shader_z_format);
825
826 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
827
828 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
829 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
830
831 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
832 /* optimise this? */
833 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
834 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
835 }
836
837 if (pipeline->graphics.ps_input_cntl_num) {
838 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
839 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
840 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
841 }
842 }
843 }
844
845 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
846 struct radv_pipeline *pipeline)
847 {
848 uint32_t vtx_reuse_depth = 30;
849 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
850 return;
851
852 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
853 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
854 vtx_reuse_depth = 14;
855 }
856 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
857 vtx_reuse_depth);
858 }
859
860 static void
861 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
862 {
863 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
864
865 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
866 return;
867
868 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
869 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
870 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
871 radv_update_multisample_state(cmd_buffer, pipeline);
872 radv_emit_vertex_shader(cmd_buffer, pipeline);
873 radv_emit_tess_shaders(cmd_buffer, pipeline);
874 radv_emit_geometry_shader(cmd_buffer, pipeline);
875 radv_emit_fragment_shader(cmd_buffer, pipeline);
876 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
877
878 cmd_buffer->scratch_size_needed =
879 MAX2(cmd_buffer->scratch_size_needed,
880 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
881
882 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
883 S_0286E8_WAVES(pipeline->max_waves) |
884 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
885
886 if (!cmd_buffer->state.emitted_pipeline ||
887 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
888 pipeline->graphics.can_use_guardband)
889 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
890
891 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
892
893 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
894 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
895 } else {
896 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
897 }
898 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
899
900 cmd_buffer->state.emitted_pipeline = pipeline;
901 }
902
903 static void
904 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
905 {
906 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
907 cmd_buffer->state.dynamic.viewport.viewports);
908 }
909
910 static void
911 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
912 {
913 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
914 si_write_scissors(cmd_buffer->cs, 0, count,
915 cmd_buffer->state.dynamic.scissor.scissors,
916 cmd_buffer->state.dynamic.viewport.viewports,
917 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
918 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
919 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
920 }
921
922 static void
923 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
924 int index,
925 struct radv_color_buffer_info *cb)
926 {
927 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
928
929 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
930 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
931 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
932 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
933 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
934 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
935 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
936 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
937 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
938 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
939 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
940 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
941 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
942
943 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
944 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
945 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
946
947 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
948 cb->gfx9_epitch);
949 } else {
950 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
951 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
952 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
953 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
957 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
962
963 if (is_vi) { /* DCC BASE */
964 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
965 }
966 }
967 }
968
969 static void
970 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
971 struct radv_ds_buffer_info *ds,
972 struct radv_image *image,
973 VkImageLayout layout)
974 {
975 uint32_t db_z_info = ds->db_z_info;
976 uint32_t db_stencil_info = ds->db_stencil_info;
977
978 if (!radv_layout_has_htile(image, layout,
979 radv_image_queue_family_mask(image,
980 cmd_buffer->queue_family_index,
981 cmd_buffer->queue_family_index))) {
982 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
983 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
984 }
985
986 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
987 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
988
989
990 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
991 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
992 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
993 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
994 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
995
996 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
997 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
998 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
999 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1000 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1001 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1002 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1003 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1004 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1005 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1006 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1007
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1009 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1010 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1011 } else {
1012 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1013
1014 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1015 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1016 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1017 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1018 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1019 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1021 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1022 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1023 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1024
1025 }
1026
1027 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1028 ds->pa_su_poly_offset_db_fmt_cntl);
1029 }
1030
1031 void
1032 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_image *image,
1034 VkClearDepthStencilValue ds_clear_value,
1035 VkImageAspectFlags aspects)
1036 {
1037 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1038 va += image->offset + image->clear_value_offset;
1039 unsigned reg_offset = 0, reg_count = 0;
1040
1041 if (!image->surface.htile_size || !aspects)
1042 return;
1043
1044 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1045 ++reg_count;
1046 } else {
1047 ++reg_offset;
1048 va += 4;
1049 }
1050 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1051 ++reg_count;
1052
1053 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1054
1055 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1056 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1057 S_370_WR_CONFIRM(1) |
1058 S_370_ENGINE_SEL(V_370_PFP));
1059 radeon_emit(cmd_buffer->cs, va);
1060 radeon_emit(cmd_buffer->cs, va >> 32);
1061 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1062 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1063 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1064 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1065
1066 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1067 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1068 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1069 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1070 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1071 }
1072
1073 static void
1074 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1075 struct radv_image *image)
1076 {
1077 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1078 va += image->offset + image->clear_value_offset;
1079
1080 if (!image->surface.htile_size)
1081 return;
1082
1083 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1084
1085 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1086 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1087 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1088 COPY_DATA_COUNT_SEL);
1089 radeon_emit(cmd_buffer->cs, va);
1090 radeon_emit(cmd_buffer->cs, va >> 32);
1091 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1092 radeon_emit(cmd_buffer->cs, 0);
1093
1094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1095 radeon_emit(cmd_buffer->cs, 0);
1096 }
1097
1098 /*
1099 *with DCC some colors don't require CMASK elimiation before being
1100 * used as a texture. This sets a predicate value to determine if the
1101 * cmask eliminate is required.
1102 */
1103 void
1104 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1105 struct radv_image *image,
1106 bool value)
1107 {
1108 uint64_t pred_val = value;
1109 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1110 va += image->offset + image->dcc_pred_offset;
1111
1112 if (!image->surface.dcc_size)
1113 return;
1114
1115 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1116
1117 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1118 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1119 S_370_WR_CONFIRM(1) |
1120 S_370_ENGINE_SEL(V_370_PFP));
1121 radeon_emit(cmd_buffer->cs, va);
1122 radeon_emit(cmd_buffer->cs, va >> 32);
1123 radeon_emit(cmd_buffer->cs, pred_val);
1124 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1125 }
1126
1127 void
1128 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1129 struct radv_image *image,
1130 int idx,
1131 uint32_t color_values[2])
1132 {
1133 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1134 va += image->offset + image->clear_value_offset;
1135
1136 if (!image->cmask.size && !image->surface.dcc_size)
1137 return;
1138
1139 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1140
1141 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1142 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1143 S_370_WR_CONFIRM(1) |
1144 S_370_ENGINE_SEL(V_370_PFP));
1145 radeon_emit(cmd_buffer->cs, va);
1146 radeon_emit(cmd_buffer->cs, va >> 32);
1147 radeon_emit(cmd_buffer->cs, color_values[0]);
1148 radeon_emit(cmd_buffer->cs, color_values[1]);
1149
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1151 radeon_emit(cmd_buffer->cs, color_values[0]);
1152 radeon_emit(cmd_buffer->cs, color_values[1]);
1153 }
1154
1155 static void
1156 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_image *image,
1158 int idx)
1159 {
1160 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1161 va += image->offset + image->clear_value_offset;
1162
1163 if (!image->cmask.size && !image->surface.dcc_size)
1164 return;
1165
1166 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1167 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1170 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1171 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1172 COPY_DATA_COUNT_SEL);
1173 radeon_emit(cmd_buffer->cs, va);
1174 radeon_emit(cmd_buffer->cs, va >> 32);
1175 radeon_emit(cmd_buffer->cs, reg >> 2);
1176 radeon_emit(cmd_buffer->cs, 0);
1177
1178 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1179 radeon_emit(cmd_buffer->cs, 0);
1180 }
1181
1182 void
1183 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 int i;
1186 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1187 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1188
1189 /* this may happen for inherited secondary recording */
1190 if (!framebuffer)
1191 return;
1192
1193 for (i = 0; i < 8; ++i) {
1194 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1195 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1196 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1197 continue;
1198 }
1199
1200 int idx = subpass->color_attachments[i].attachment;
1201 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1202
1203 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1204
1205 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1206 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1207
1208 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1209 }
1210
1211 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1212 int idx = subpass->depth_stencil_attachment.attachment;
1213 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1214 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1215 struct radv_image *image = att->attachment->image;
1216 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1217 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1218 cmd_buffer->queue_family_index,
1219 cmd_buffer->queue_family_index);
1220 /* We currently don't support writing decompressed HTILE */
1221 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1222 radv_layout_is_htile_compressed(image, layout, queue_mask));
1223
1224 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1225
1226 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1227 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1228 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1229 }
1230 radv_load_depth_clear_regs(cmd_buffer, image);
1231 } else {
1232 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1233 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1234 else
1235 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1236
1237 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1238 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1239 }
1240 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1241 S_028208_BR_X(framebuffer->width) |
1242 S_028208_BR_Y(framebuffer->height));
1243
1244 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1245 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1246 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1247 }
1248 }
1249
1250 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1251 {
1252 uint32_t db_count_control;
1253
1254 if(!cmd_buffer->state.active_occlusion_queries) {
1255 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1256 db_count_control = 0;
1257 } else {
1258 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1259 }
1260 } else {
1261 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1262 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1263 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1264 S_028004_ZPASS_ENABLE(1) |
1265 S_028004_SLICE_EVEN_ENABLE(1) |
1266 S_028004_SLICE_ODD_ENABLE(1);
1267 } else {
1268 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1269 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1270 }
1271 }
1272
1273 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1274 }
1275
1276 static void
1277 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1278 {
1279 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1280
1281 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1282 return;
1283
1284 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1285 radv_emit_viewport(cmd_buffer);
1286
1287 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1288 radv_emit_scissor(cmd_buffer);
1289
1290 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1291 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1292 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1293 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1294 }
1295
1296 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1297 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1298 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1299 }
1300
1301 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1302 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1303 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1304 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1305 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1306 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1307 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1308 S_028430_STENCILOPVAL(1));
1309 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1310 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1311 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1312 S_028434_STENCILOPVAL_BF(1));
1313 }
1314
1315 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1316 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1317 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1318 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1319 }
1320
1321 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1322 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1323 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1324 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1325 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1326
1327 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1328 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1329 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1330 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1331 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1332 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1333 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1334 }
1335 }
1336
1337 cmd_buffer->state.dirty = 0;
1338 }
1339
1340 static void
1341 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1342 struct radv_pipeline *pipeline,
1343 int idx,
1344 uint64_t va,
1345 gl_shader_stage stage)
1346 {
1347 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1348 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1349
1350 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1351 return;
1352
1353 assert(!desc_set_loc->indirect);
1354 assert(desc_set_loc->num_sgprs == 2);
1355 radeon_set_sh_reg_seq(cmd_buffer->cs,
1356 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1357 radeon_emit(cmd_buffer->cs, va);
1358 radeon_emit(cmd_buffer->cs, va >> 32);
1359 }
1360
1361 static void
1362 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1363 VkShaderStageFlags stages,
1364 struct radv_descriptor_set *set,
1365 unsigned idx)
1366 {
1367 if (cmd_buffer->state.pipeline) {
1368 radv_foreach_stage(stage, stages) {
1369 if (cmd_buffer->state.pipeline->shaders[stage])
1370 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1371 idx, set->va,
1372 stage);
1373 }
1374 }
1375
1376 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1377 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1378 idx, set->va,
1379 MESA_SHADER_COMPUTE);
1380 }
1381
1382 static void
1383 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1384 {
1385 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1386 uint32_t *ptr = NULL;
1387 unsigned bo_offset;
1388
1389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1390 &bo_offset,
1391 (void**) &ptr))
1392 return;
1393
1394 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1395 set->va += bo_offset;
1396
1397 memcpy(ptr, set->mapped_ptr, set->size);
1398 }
1399
1400 static void
1401 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1402 {
1403 uint32_t size = MAX_SETS * 2 * 4;
1404 uint32_t offset;
1405 void *ptr;
1406
1407 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1408 256, &offset, &ptr))
1409 return;
1410
1411 for (unsigned i = 0; i < MAX_SETS; i++) {
1412 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1413 uint64_t set_va = 0;
1414 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1415 if (set)
1416 set_va = set->va;
1417 uptr[0] = set_va & 0xffffffff;
1418 uptr[1] = set_va >> 32;
1419 }
1420
1421 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1422 va += offset;
1423
1424 if (cmd_buffer->state.pipeline) {
1425 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1426 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1427 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1428
1429 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1430 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1431 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1432
1433 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1434 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1435 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1436
1437 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1438 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1439 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1440
1441 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1442 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1443 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1444 }
1445
1446 if (cmd_buffer->state.compute_pipeline)
1447 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1448 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1449 }
1450
1451 static void
1452 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1453 VkShaderStageFlags stages)
1454 {
1455 unsigned i;
1456
1457 if (!cmd_buffer->state.descriptors_dirty)
1458 return;
1459
1460 if (cmd_buffer->state.push_descriptors_dirty)
1461 radv_flush_push_descriptors(cmd_buffer);
1462
1463 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1464 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1465 radv_flush_indirect_descriptor_sets(cmd_buffer);
1466 }
1467
1468 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1469 cmd_buffer->cs,
1470 MAX_SETS * MESA_SHADER_STAGES * 4);
1471
1472 for (i = 0; i < MAX_SETS; i++) {
1473 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1474 continue;
1475 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1476 if (!set)
1477 continue;
1478
1479 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1480 }
1481 cmd_buffer->state.descriptors_dirty = 0;
1482 cmd_buffer->state.push_descriptors_dirty = false;
1483 assert(cmd_buffer->cs->cdw <= cdw_max);
1484 }
1485
1486 static void
1487 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1488 struct radv_pipeline *pipeline,
1489 VkShaderStageFlags stages)
1490 {
1491 struct radv_pipeline_layout *layout = pipeline->layout;
1492 unsigned offset;
1493 void *ptr;
1494 uint64_t va;
1495
1496 stages &= cmd_buffer->push_constant_stages;
1497 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1498 return;
1499
1500 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1501 16 * layout->dynamic_offset_count,
1502 256, &offset, &ptr))
1503 return;
1504
1505 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1506 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1507 16 * layout->dynamic_offset_count);
1508
1509 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1510 va += offset;
1511
1512 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1513 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1514
1515 radv_foreach_stage(stage, stages) {
1516 if (pipeline->shaders[stage]) {
1517 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1518 AC_UD_PUSH_CONSTANTS, va);
1519 }
1520 }
1521
1522 cmd_buffer->push_constant_stages &= ~stages;
1523 assert(cmd_buffer->cs->cdw <= cdw_max);
1524 }
1525
1526 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1527 bool indexed_draw)
1528 {
1529 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1530
1531 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1532 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1534 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1535 primitive_reset_en);
1536 } else {
1537 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1538 primitive_reset_en);
1539 }
1540 }
1541
1542 if (primitive_reset_en) {
1543 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1544
1545 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1546 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1547 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1548 primitive_reset_index);
1549 }
1550 }
1551 }
1552
1553 static bool
1554 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1555 {
1556 struct radv_device *device = cmd_buffer->device;
1557
1558 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1559 cmd_buffer->state.pipeline->vertex_elements.count &&
1560 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1561 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1562 unsigned vb_offset;
1563 void *vb_ptr;
1564 uint32_t i = 0;
1565 uint32_t count = velems->count;
1566 uint64_t va;
1567
1568 /* allocate some descriptor state for vertex buffers */
1569 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1570 &vb_offset, &vb_ptr))
1571 return false;
1572
1573 for (i = 0; i < count; i++) {
1574 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1575 uint32_t offset;
1576 int vb = velems->binding[i];
1577 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1578 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1579
1580 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1581 va = device->ws->buffer_get_va(buffer->bo);
1582
1583 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1584 va += offset + buffer->offset;
1585 desc[0] = va;
1586 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1588 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1589 else
1590 desc[2] = buffer->size - offset;
1591 desc[3] = velems->rsrc_word3[i];
1592 }
1593
1594 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1595 va += vb_offset;
1596
1597 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1598 AC_UD_VS_VERTEX_BUFFERS, va);
1599 }
1600 cmd_buffer->state.vb_dirty = false;
1601
1602 return true;
1603 }
1604
1605 static void
1606 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1607 bool indexed_draw, bool instanced_draw,
1608 bool indirect_draw,
1609 uint32_t draw_vertex_count)
1610 {
1611 uint32_t ia_multi_vgt_param;
1612
1613 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1614 cmd_buffer->cs, 4096);
1615
1616 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1617 return;
1618
1619 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1620 radv_emit_graphics_pipeline(cmd_buffer);
1621
1622 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1623 radv_emit_framebuffer_state(cmd_buffer);
1624
1625 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1626 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1627 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1628 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1629 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1630 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1631 else
1632 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1633 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1634 }
1635
1636 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1637
1638 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1639
1640 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1641 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1642 VK_SHADER_STAGE_ALL_GRAPHICS);
1643
1644 assert(cmd_buffer->cs->cdw <= cdw_max);
1645
1646 si_emit_cache_flush(cmd_buffer);
1647 }
1648
1649 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1650 VkPipelineStageFlags src_stage_mask)
1651 {
1652 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1653 VK_PIPELINE_STAGE_TRANSFER_BIT |
1654 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1655 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1656 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1657 }
1658
1659 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1660 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1661 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1662 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1663 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1664 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1665 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1666 VK_PIPELINE_STAGE_TRANSFER_BIT |
1667 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1668 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1669 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1670 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1671 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1672 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1673 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1674 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1675 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1676 }
1677 }
1678
1679 static enum radv_cmd_flush_bits
1680 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1681 VkAccessFlags src_flags)
1682 {
1683 enum radv_cmd_flush_bits flush_bits = 0;
1684 uint32_t b;
1685 for_each_bit(b, src_flags) {
1686 switch ((VkAccessFlagBits)(1 << b)) {
1687 case VK_ACCESS_SHADER_WRITE_BIT:
1688 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1689 break;
1690 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1691 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1692 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1693 break;
1694 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1695 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1696 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1697 break;
1698 case VK_ACCESS_TRANSFER_WRITE_BIT:
1699 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1700 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1701 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1702 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1703 RADV_CMD_FLAG_INV_GLOBAL_L2;
1704 break;
1705 default:
1706 break;
1707 }
1708 }
1709 return flush_bits;
1710 }
1711
1712 static enum radv_cmd_flush_bits
1713 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1714 VkAccessFlags dst_flags,
1715 struct radv_image *image)
1716 {
1717 enum radv_cmd_flush_bits flush_bits = 0;
1718 uint32_t b;
1719 for_each_bit(b, dst_flags) {
1720 switch ((VkAccessFlagBits)(1 << b)) {
1721 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1722 case VK_ACCESS_INDEX_READ_BIT:
1723 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1724 break;
1725 case VK_ACCESS_UNIFORM_READ_BIT:
1726 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1727 break;
1728 case VK_ACCESS_SHADER_READ_BIT:
1729 case VK_ACCESS_TRANSFER_READ_BIT:
1730 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1731 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1732 RADV_CMD_FLAG_INV_GLOBAL_L2;
1733 break;
1734 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1735 /* TODO: change to image && when the image gets passed
1736 * through from the subpass. */
1737 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1738 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1739 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1740 break;
1741 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1742 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1743 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1744 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1745 break;
1746 default:
1747 break;
1748 }
1749 }
1750 return flush_bits;
1751 }
1752
1753 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1754 {
1755 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1756 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1757 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1758 NULL);
1759 }
1760
1761 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1762 VkAttachmentReference att)
1763 {
1764 unsigned idx = att.attachment;
1765 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1766 VkImageSubresourceRange range;
1767 range.aspectMask = 0;
1768 range.baseMipLevel = view->base_mip;
1769 range.levelCount = 1;
1770 range.baseArrayLayer = view->base_layer;
1771 range.layerCount = cmd_buffer->state.framebuffer->layers;
1772
1773 radv_handle_image_transition(cmd_buffer,
1774 view->image,
1775 cmd_buffer->state.attachments[idx].current_layout,
1776 att.layout, 0, 0, &range,
1777 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1778
1779 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1780
1781
1782 }
1783
1784 void
1785 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1786 const struct radv_subpass *subpass, bool transitions)
1787 {
1788 if (transitions) {
1789 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1790
1791 for (unsigned i = 0; i < subpass->color_count; ++i) {
1792 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1793 radv_handle_subpass_image_transition(cmd_buffer,
1794 subpass->color_attachments[i]);
1795 }
1796
1797 for (unsigned i = 0; i < subpass->input_count; ++i) {
1798 radv_handle_subpass_image_transition(cmd_buffer,
1799 subpass->input_attachments[i]);
1800 }
1801
1802 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1803 radv_handle_subpass_image_transition(cmd_buffer,
1804 subpass->depth_stencil_attachment);
1805 }
1806 }
1807
1808 cmd_buffer->state.subpass = subpass;
1809
1810 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1811 }
1812
1813 static VkResult
1814 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1815 struct radv_render_pass *pass,
1816 const VkRenderPassBeginInfo *info)
1817 {
1818 struct radv_cmd_state *state = &cmd_buffer->state;
1819
1820 if (pass->attachment_count == 0) {
1821 state->attachments = NULL;
1822 return VK_SUCCESS;
1823 }
1824
1825 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1826 pass->attachment_count *
1827 sizeof(state->attachments[0]),
1828 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1829 if (state->attachments == NULL) {
1830 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1831 return cmd_buffer->record_result;
1832 }
1833
1834 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1835 struct radv_render_pass_attachment *att = &pass->attachments[i];
1836 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1837 VkImageAspectFlags clear_aspects = 0;
1838
1839 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1840 /* color attachment */
1841 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1842 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1843 }
1844 } else {
1845 /* depthstencil attachment */
1846 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1847 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1848 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1849 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1850 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1851 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1852 }
1853 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1854 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1855 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1856 }
1857 }
1858
1859 state->attachments[i].pending_clear_aspects = clear_aspects;
1860 state->attachments[i].cleared_views = 0;
1861 if (clear_aspects && info) {
1862 assert(info->clearValueCount > i);
1863 state->attachments[i].clear_value = info->pClearValues[i];
1864 }
1865
1866 state->attachments[i].current_layout = att->initial_layout;
1867 }
1868
1869 return VK_SUCCESS;
1870 }
1871
1872 VkResult radv_AllocateCommandBuffers(
1873 VkDevice _device,
1874 const VkCommandBufferAllocateInfo *pAllocateInfo,
1875 VkCommandBuffer *pCommandBuffers)
1876 {
1877 RADV_FROM_HANDLE(radv_device, device, _device);
1878 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1879
1880 VkResult result = VK_SUCCESS;
1881 uint32_t i;
1882
1883 memset(pCommandBuffers, 0,
1884 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1885
1886 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1887
1888 if (!list_empty(&pool->free_cmd_buffers)) {
1889 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1890
1891 list_del(&cmd_buffer->pool_link);
1892 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1893
1894 result = radv_reset_cmd_buffer(cmd_buffer);
1895 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1896 cmd_buffer->level = pAllocateInfo->level;
1897
1898 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1899 } else {
1900 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1901 &pCommandBuffers[i]);
1902 }
1903 if (result != VK_SUCCESS)
1904 break;
1905 }
1906
1907 if (result != VK_SUCCESS)
1908 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1909 i, pCommandBuffers);
1910
1911 return result;
1912 }
1913
1914 void radv_FreeCommandBuffers(
1915 VkDevice device,
1916 VkCommandPool commandPool,
1917 uint32_t commandBufferCount,
1918 const VkCommandBuffer *pCommandBuffers)
1919 {
1920 for (uint32_t i = 0; i < commandBufferCount; i++) {
1921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1922
1923 if (cmd_buffer) {
1924 if (cmd_buffer->pool) {
1925 list_del(&cmd_buffer->pool_link);
1926 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1927 } else
1928 radv_cmd_buffer_destroy(cmd_buffer);
1929
1930 }
1931 }
1932 }
1933
1934 VkResult radv_ResetCommandBuffer(
1935 VkCommandBuffer commandBuffer,
1936 VkCommandBufferResetFlags flags)
1937 {
1938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1939 return radv_reset_cmd_buffer(cmd_buffer);
1940 }
1941
1942 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1943 {
1944 struct radv_device *device = cmd_buffer->device;
1945 if (device->gfx_init) {
1946 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1947 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1948 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1949 radeon_emit(cmd_buffer->cs, va);
1950 radeon_emit(cmd_buffer->cs, va >> 32);
1951 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1952 } else
1953 si_init_config(cmd_buffer);
1954 }
1955
1956 VkResult radv_BeginCommandBuffer(
1957 VkCommandBuffer commandBuffer,
1958 const VkCommandBufferBeginInfo *pBeginInfo)
1959 {
1960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1961 VkResult result;
1962
1963 result = radv_reset_cmd_buffer(cmd_buffer);
1964 if (result != VK_SUCCESS)
1965 return result;
1966
1967 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1968 cmd_buffer->state.last_primitive_reset_en = -1;
1969 cmd_buffer->usage_flags = pBeginInfo->flags;
1970
1971 /* setup initial configuration into command buffer */
1972 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1973 switch (cmd_buffer->queue_family_index) {
1974 case RADV_QUEUE_GENERAL:
1975 emit_gfx_buffer_state(cmd_buffer);
1976 radv_set_db_count_control(cmd_buffer);
1977 break;
1978 case RADV_QUEUE_COMPUTE:
1979 si_init_compute(cmd_buffer);
1980 break;
1981 case RADV_QUEUE_TRANSFER:
1982 default:
1983 break;
1984 }
1985 }
1986
1987 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1988 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1989 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1990
1991 struct radv_subpass *subpass =
1992 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1993
1994 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1995 if (result != VK_SUCCESS)
1996 return result;
1997
1998 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1999 }
2000
2001 radv_cmd_buffer_trace_emit(cmd_buffer);
2002 return result;
2003 }
2004
2005 void radv_CmdBindVertexBuffers(
2006 VkCommandBuffer commandBuffer,
2007 uint32_t firstBinding,
2008 uint32_t bindingCount,
2009 const VkBuffer* pBuffers,
2010 const VkDeviceSize* pOffsets)
2011 {
2012 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2013 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2014
2015 /* We have to defer setting up vertex buffer since we need the buffer
2016 * stride from the pipeline. */
2017
2018 assert(firstBinding + bindingCount <= MAX_VBS);
2019 for (uint32_t i = 0; i < bindingCount; i++) {
2020 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2021 vb[firstBinding + i].offset = pOffsets[i];
2022 }
2023
2024 cmd_buffer->state.vb_dirty = true;
2025 }
2026
2027 void radv_CmdBindIndexBuffer(
2028 VkCommandBuffer commandBuffer,
2029 VkBuffer buffer,
2030 VkDeviceSize offset,
2031 VkIndexType indexType)
2032 {
2033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2034 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2035
2036 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2037 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2038 cmd_buffer->state.index_va += index_buffer->offset + offset;
2039
2040 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2041 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2042 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2043 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2044 }
2045
2046
2047 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2048 struct radv_descriptor_set *set,
2049 unsigned idx)
2050 {
2051 struct radeon_winsys *ws = cmd_buffer->device->ws;
2052
2053 cmd_buffer->state.descriptors[idx] = set;
2054 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2055 if (!set)
2056 return;
2057
2058 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2059
2060 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2061 if (set->descriptors[j])
2062 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2063
2064 if(set->bo)
2065 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2066 }
2067
2068 void radv_CmdBindDescriptorSets(
2069 VkCommandBuffer commandBuffer,
2070 VkPipelineBindPoint pipelineBindPoint,
2071 VkPipelineLayout _layout,
2072 uint32_t firstSet,
2073 uint32_t descriptorSetCount,
2074 const VkDescriptorSet* pDescriptorSets,
2075 uint32_t dynamicOffsetCount,
2076 const uint32_t* pDynamicOffsets)
2077 {
2078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2079 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2080 unsigned dyn_idx = 0;
2081
2082 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2083 unsigned idx = i + firstSet;
2084 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2085 radv_bind_descriptor_set(cmd_buffer, set, idx);
2086
2087 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2088 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2089 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2090 assert(dyn_idx < dynamicOffsetCount);
2091
2092 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2093 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2094 dst[0] = va;
2095 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2096 dst[2] = range->size;
2097 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2098 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2099 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2100 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2101 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2102 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2103 cmd_buffer->push_constant_stages |=
2104 set->layout->dynamic_shader_stages;
2105 }
2106 }
2107 }
2108
2109 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2110 struct radv_descriptor_set *set,
2111 struct radv_descriptor_set_layout *layout)
2112 {
2113 set->size = layout->size;
2114 set->layout = layout;
2115
2116 if (cmd_buffer->push_descriptors.capacity < set->size) {
2117 size_t new_size = MAX2(set->size, 1024);
2118 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2119 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2120
2121 free(set->mapped_ptr);
2122 set->mapped_ptr = malloc(new_size);
2123
2124 if (!set->mapped_ptr) {
2125 cmd_buffer->push_descriptors.capacity = 0;
2126 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2127 return false;
2128 }
2129
2130 cmd_buffer->push_descriptors.capacity = new_size;
2131 }
2132
2133 return true;
2134 }
2135
2136 void radv_meta_push_descriptor_set(
2137 struct radv_cmd_buffer* cmd_buffer,
2138 VkPipelineBindPoint pipelineBindPoint,
2139 VkPipelineLayout _layout,
2140 uint32_t set,
2141 uint32_t descriptorWriteCount,
2142 const VkWriteDescriptorSet* pDescriptorWrites)
2143 {
2144 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2145 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2146 unsigned bo_offset;
2147
2148 assert(set == 0);
2149 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2150
2151 push_set->size = layout->set[set].layout->size;
2152 push_set->layout = layout->set[set].layout;
2153
2154 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2155 &bo_offset,
2156 (void**) &push_set->mapped_ptr))
2157 return;
2158
2159 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2160 push_set->va += bo_offset;
2161
2162 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2163 radv_descriptor_set_to_handle(push_set),
2164 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2165
2166 cmd_buffer->state.descriptors[set] = push_set;
2167 cmd_buffer->state.descriptors_dirty |= (1u << set);
2168 }
2169
2170 void radv_CmdPushDescriptorSetKHR(
2171 VkCommandBuffer commandBuffer,
2172 VkPipelineBindPoint pipelineBindPoint,
2173 VkPipelineLayout _layout,
2174 uint32_t set,
2175 uint32_t descriptorWriteCount,
2176 const VkWriteDescriptorSet* pDescriptorWrites)
2177 {
2178 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2179 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2180 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2181
2182 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2183
2184 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2185 return;
2186
2187 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2188 radv_descriptor_set_to_handle(push_set),
2189 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2190
2191 cmd_buffer->state.descriptors[set] = push_set;
2192 cmd_buffer->state.descriptors_dirty |= (1u << set);
2193 cmd_buffer->state.push_descriptors_dirty = true;
2194 }
2195
2196 void radv_CmdPushDescriptorSetWithTemplateKHR(
2197 VkCommandBuffer commandBuffer,
2198 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2199 VkPipelineLayout _layout,
2200 uint32_t set,
2201 const void* pData)
2202 {
2203 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2204 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2205 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2206
2207 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2208
2209 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2210 return;
2211
2212 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2213 descriptorUpdateTemplate, pData);
2214
2215 cmd_buffer->state.descriptors[set] = push_set;
2216 cmd_buffer->state.descriptors_dirty |= (1u << set);
2217 cmd_buffer->state.push_descriptors_dirty = true;
2218 }
2219
2220 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2221 VkPipelineLayout layout,
2222 VkShaderStageFlags stageFlags,
2223 uint32_t offset,
2224 uint32_t size,
2225 const void* pValues)
2226 {
2227 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2228 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2229 cmd_buffer->push_constant_stages |= stageFlags;
2230 }
2231
2232 VkResult radv_EndCommandBuffer(
2233 VkCommandBuffer commandBuffer)
2234 {
2235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236
2237 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2238 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2239 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2240 si_emit_cache_flush(cmd_buffer);
2241 }
2242
2243 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2244 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2245
2246 return cmd_buffer->record_result;
2247 }
2248
2249 static void
2250 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2251 {
2252 struct radeon_winsys *ws = cmd_buffer->device->ws;
2253 struct radv_shader_variant *compute_shader;
2254 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2255 uint64_t va;
2256
2257 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2258 return;
2259
2260 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2261
2262 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2263 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2264
2265 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2266 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2267
2268 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2269 cmd_buffer->cs, 16);
2270
2271 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2272 radeon_emit(cmd_buffer->cs, va >> 8);
2273 radeon_emit(cmd_buffer->cs, va >> 40);
2274
2275 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2276 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2277 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2278
2279
2280 cmd_buffer->compute_scratch_size_needed =
2281 MAX2(cmd_buffer->compute_scratch_size_needed,
2282 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2283
2284 /* change these once we have scratch support */
2285 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2286 S_00B860_WAVES(pipeline->max_waves) |
2287 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2288
2289 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2290 radeon_emit(cmd_buffer->cs,
2291 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2292 radeon_emit(cmd_buffer->cs,
2293 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2294 radeon_emit(cmd_buffer->cs,
2295 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2296
2297 assert(cmd_buffer->cs->cdw <= cdw_max);
2298 }
2299
2300 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2301 {
2302 for (unsigned i = 0; i < MAX_SETS; i++) {
2303 if (cmd_buffer->state.descriptors[i])
2304 cmd_buffer->state.descriptors_dirty |= (1u << i);
2305 }
2306 }
2307
2308 void radv_CmdBindPipeline(
2309 VkCommandBuffer commandBuffer,
2310 VkPipelineBindPoint pipelineBindPoint,
2311 VkPipeline _pipeline)
2312 {
2313 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2314 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2315
2316 radv_mark_descriptor_sets_dirty(cmd_buffer);
2317
2318 switch (pipelineBindPoint) {
2319 case VK_PIPELINE_BIND_POINT_COMPUTE:
2320 cmd_buffer->state.compute_pipeline = pipeline;
2321 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2322 break;
2323 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2324 cmd_buffer->state.pipeline = pipeline;
2325 if (!pipeline)
2326 break;
2327
2328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2329 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2330
2331 /* Apply the dynamic state from the pipeline */
2332 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2333 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2334 &pipeline->dynamic_state,
2335 pipeline->dynamic_state_mask);
2336
2337 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2338 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2339 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2340 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2341
2342 if (radv_pipeline_has_tess(pipeline))
2343 cmd_buffer->tess_rings_needed = true;
2344
2345 if (radv_pipeline_has_gs(pipeline)) {
2346 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2347 AC_UD_SCRATCH_RING_OFFSETS);
2348 if (cmd_buffer->ring_offsets_idx == -1)
2349 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2350 else if (loc->sgpr_idx != -1)
2351 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2352 }
2353 break;
2354 default:
2355 assert(!"invalid bind point");
2356 break;
2357 }
2358 }
2359
2360 void radv_CmdSetViewport(
2361 VkCommandBuffer commandBuffer,
2362 uint32_t firstViewport,
2363 uint32_t viewportCount,
2364 const VkViewport* pViewports)
2365 {
2366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2367
2368 const uint32_t total_count = firstViewport + viewportCount;
2369 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2370 cmd_buffer->state.dynamic.viewport.count = total_count;
2371
2372 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2373 pViewports, viewportCount * sizeof(*pViewports));
2374
2375 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2376 }
2377
2378 void radv_CmdSetScissor(
2379 VkCommandBuffer commandBuffer,
2380 uint32_t firstScissor,
2381 uint32_t scissorCount,
2382 const VkRect2D* pScissors)
2383 {
2384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2385
2386 const uint32_t total_count = firstScissor + scissorCount;
2387 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2388 cmd_buffer->state.dynamic.scissor.count = total_count;
2389
2390 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2391 pScissors, scissorCount * sizeof(*pScissors));
2392 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2393 }
2394
2395 void radv_CmdSetLineWidth(
2396 VkCommandBuffer commandBuffer,
2397 float lineWidth)
2398 {
2399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2400 cmd_buffer->state.dynamic.line_width = lineWidth;
2401 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2402 }
2403
2404 void radv_CmdSetDepthBias(
2405 VkCommandBuffer commandBuffer,
2406 float depthBiasConstantFactor,
2407 float depthBiasClamp,
2408 float depthBiasSlopeFactor)
2409 {
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2411
2412 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2413 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2414 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2415
2416 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2417 }
2418
2419 void radv_CmdSetBlendConstants(
2420 VkCommandBuffer commandBuffer,
2421 const float blendConstants[4])
2422 {
2423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2424
2425 memcpy(cmd_buffer->state.dynamic.blend_constants,
2426 blendConstants, sizeof(float) * 4);
2427
2428 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2429 }
2430
2431 void radv_CmdSetDepthBounds(
2432 VkCommandBuffer commandBuffer,
2433 float minDepthBounds,
2434 float maxDepthBounds)
2435 {
2436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2437
2438 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2439 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2440
2441 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2442 }
2443
2444 void radv_CmdSetStencilCompareMask(
2445 VkCommandBuffer commandBuffer,
2446 VkStencilFaceFlags faceMask,
2447 uint32_t compareMask)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450
2451 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2452 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2453 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2454 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2455
2456 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2457 }
2458
2459 void radv_CmdSetStencilWriteMask(
2460 VkCommandBuffer commandBuffer,
2461 VkStencilFaceFlags faceMask,
2462 uint32_t writeMask)
2463 {
2464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2465
2466 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2467 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2468 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2469 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2470
2471 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2472 }
2473
2474 void radv_CmdSetStencilReference(
2475 VkCommandBuffer commandBuffer,
2476 VkStencilFaceFlags faceMask,
2477 uint32_t reference)
2478 {
2479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2480
2481 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2482 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2483 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2484 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2485
2486 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2487 }
2488
2489 void radv_CmdExecuteCommands(
2490 VkCommandBuffer commandBuffer,
2491 uint32_t commandBufferCount,
2492 const VkCommandBuffer* pCmdBuffers)
2493 {
2494 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2495
2496 /* Emit pending flushes on primary prior to executing secondary */
2497 si_emit_cache_flush(primary);
2498
2499 for (uint32_t i = 0; i < commandBufferCount; i++) {
2500 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2501
2502 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2503 secondary->scratch_size_needed);
2504 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2505 secondary->compute_scratch_size_needed);
2506
2507 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2508 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2509 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2510 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2511 if (secondary->tess_rings_needed)
2512 primary->tess_rings_needed = true;
2513 if (secondary->sample_positions_needed)
2514 primary->sample_positions_needed = true;
2515
2516 if (secondary->ring_offsets_idx != -1) {
2517 if (primary->ring_offsets_idx == -1)
2518 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2519 else
2520 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2521 }
2522 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2523 }
2524
2525 /* if we execute secondary we need to re-emit out pipelines */
2526 if (commandBufferCount) {
2527 primary->state.emitted_pipeline = NULL;
2528 primary->state.emitted_compute_pipeline = NULL;
2529 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2530 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2531 primary->state.last_primitive_reset_en = -1;
2532 primary->state.last_primitive_reset_index = 0;
2533 radv_mark_descriptor_sets_dirty(primary);
2534 }
2535 }
2536
2537 VkResult radv_CreateCommandPool(
2538 VkDevice _device,
2539 const VkCommandPoolCreateInfo* pCreateInfo,
2540 const VkAllocationCallbacks* pAllocator,
2541 VkCommandPool* pCmdPool)
2542 {
2543 RADV_FROM_HANDLE(radv_device, device, _device);
2544 struct radv_cmd_pool *pool;
2545
2546 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2547 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2548 if (pool == NULL)
2549 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2550
2551 if (pAllocator)
2552 pool->alloc = *pAllocator;
2553 else
2554 pool->alloc = device->alloc;
2555
2556 list_inithead(&pool->cmd_buffers);
2557 list_inithead(&pool->free_cmd_buffers);
2558
2559 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2560
2561 *pCmdPool = radv_cmd_pool_to_handle(pool);
2562
2563 return VK_SUCCESS;
2564
2565 }
2566
2567 void radv_DestroyCommandPool(
2568 VkDevice _device,
2569 VkCommandPool commandPool,
2570 const VkAllocationCallbacks* pAllocator)
2571 {
2572 RADV_FROM_HANDLE(radv_device, device, _device);
2573 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2574
2575 if (!pool)
2576 return;
2577
2578 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2579 &pool->cmd_buffers, pool_link) {
2580 radv_cmd_buffer_destroy(cmd_buffer);
2581 }
2582
2583 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2584 &pool->free_cmd_buffers, pool_link) {
2585 radv_cmd_buffer_destroy(cmd_buffer);
2586 }
2587
2588 vk_free2(&device->alloc, pAllocator, pool);
2589 }
2590
2591 VkResult radv_ResetCommandPool(
2592 VkDevice device,
2593 VkCommandPool commandPool,
2594 VkCommandPoolResetFlags flags)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2597 VkResult result;
2598
2599 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2600 &pool->cmd_buffers, pool_link) {
2601 result = radv_reset_cmd_buffer(cmd_buffer);
2602 if (result != VK_SUCCESS)
2603 return result;
2604 }
2605
2606 return VK_SUCCESS;
2607 }
2608
2609 void radv_TrimCommandPoolKHR(
2610 VkDevice device,
2611 VkCommandPool commandPool,
2612 VkCommandPoolTrimFlagsKHR flags)
2613 {
2614 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2615
2616 if (!pool)
2617 return;
2618
2619 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2620 &pool->free_cmd_buffers, pool_link) {
2621 radv_cmd_buffer_destroy(cmd_buffer);
2622 }
2623 }
2624
2625 void radv_CmdBeginRenderPass(
2626 VkCommandBuffer commandBuffer,
2627 const VkRenderPassBeginInfo* pRenderPassBegin,
2628 VkSubpassContents contents)
2629 {
2630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2631 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2632 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2633
2634 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2635 cmd_buffer->cs, 2048);
2636 MAYBE_UNUSED VkResult result;
2637
2638 cmd_buffer->state.framebuffer = framebuffer;
2639 cmd_buffer->state.pass = pass;
2640 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2641 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2642 if (result != VK_SUCCESS)
2643 cmd_buffer->record_result = result;
2644
2645 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2646 assert(cmd_buffer->cs->cdw <= cdw_max);
2647
2648 radv_cmd_buffer_clear_subpass(cmd_buffer);
2649 }
2650
2651 void radv_CmdNextSubpass(
2652 VkCommandBuffer commandBuffer,
2653 VkSubpassContents contents)
2654 {
2655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2656
2657 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2658
2659 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2660 2048);
2661
2662 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2663 radv_cmd_buffer_clear_subpass(cmd_buffer);
2664 }
2665
2666 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2667 {
2668 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2669 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2670 if (!pipeline->shaders[stage])
2671 continue;
2672 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2673 if (loc->sgpr_idx == -1)
2674 continue;
2675 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2676 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2677
2678 }
2679 if (pipeline->gs_copy_shader) {
2680 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2681 if (loc->sgpr_idx != -1) {
2682 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2683 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2684 }
2685 }
2686 }
2687
2688 static void
2689 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2690 uint32_t vertex_count)
2691 {
2692 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2693 radeon_emit(cmd_buffer->cs, vertex_count);
2694 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2695 S_0287F0_USE_OPAQUE(0));
2696 }
2697
2698 void radv_CmdDraw(
2699 VkCommandBuffer commandBuffer,
2700 uint32_t vertexCount,
2701 uint32_t instanceCount,
2702 uint32_t firstVertex,
2703 uint32_t firstInstance)
2704 {
2705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2706
2707 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2708
2709 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2710
2711 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2712 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2713 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2714 radeon_emit(cmd_buffer->cs, firstVertex);
2715 radeon_emit(cmd_buffer->cs, firstInstance);
2716 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2717 radeon_emit(cmd_buffer->cs, 0);
2718
2719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2720 radeon_emit(cmd_buffer->cs, instanceCount);
2721
2722 if (!cmd_buffer->state.subpass->view_mask) {
2723 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2724 } else {
2725 unsigned i;
2726 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2727 radv_emit_view_index(cmd_buffer, i);
2728
2729 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2730 }
2731 }
2732
2733 assert(cmd_buffer->cs->cdw <= cdw_max);
2734
2735 radv_cmd_buffer_trace_emit(cmd_buffer);
2736 }
2737
2738
2739 static void
2740 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2741 uint64_t index_va,
2742 uint32_t index_count)
2743 {
2744 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2745 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2746 radeon_emit(cmd_buffer->cs, index_va);
2747 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2748 radeon_emit(cmd_buffer->cs, index_count);
2749 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2750 }
2751
2752 void radv_CmdDrawIndexed(
2753 VkCommandBuffer commandBuffer,
2754 uint32_t indexCount,
2755 uint32_t instanceCount,
2756 uint32_t firstIndex,
2757 int32_t vertexOffset,
2758 uint32_t firstInstance)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2762 uint64_t index_va;
2763
2764 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2765
2766 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2767
2768 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2769 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2770 2, cmd_buffer->state.index_type);
2771 } else {
2772 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2773 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2774 }
2775
2776 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2777 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2778 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2779 radeon_emit(cmd_buffer->cs, vertexOffset);
2780 radeon_emit(cmd_buffer->cs, firstInstance);
2781 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2782 radeon_emit(cmd_buffer->cs, 0);
2783
2784 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2785 radeon_emit(cmd_buffer->cs, instanceCount);
2786
2787 index_va = cmd_buffer->state.index_va;
2788 index_va += firstIndex * index_size;
2789 if (!cmd_buffer->state.subpass->view_mask) {
2790 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2791 } else {
2792 unsigned i;
2793 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2794 radv_emit_view_index(cmd_buffer, i);
2795
2796 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2797 }
2798 }
2799
2800 assert(cmd_buffer->cs->cdw <= cdw_max);
2801 radv_cmd_buffer_trace_emit(cmd_buffer);
2802 }
2803
2804 static void
2805 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2806 bool indexed,
2807 uint32_t draw_count,
2808 uint64_t count_va,
2809 uint32_t stride)
2810 {
2811 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2812 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2813 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2814 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2815 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2816 assert(base_reg);
2817
2818 if (draw_count == 1 && !count_va && !draw_id_enable) {
2819 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2820 PKT3_DRAW_INDIRECT, 3, false));
2821 radeon_emit(cs, 0);
2822 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2823 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2824 radeon_emit(cs, di_src_sel);
2825 } else {
2826 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2827 PKT3_DRAW_INDIRECT_MULTI,
2828 8, false));
2829 radeon_emit(cs, 0);
2830 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2831 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2832 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2833 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2834 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2835 radeon_emit(cs, draw_count); /* count */
2836 radeon_emit(cs, count_va); /* count_addr */
2837 radeon_emit(cs, count_va >> 32);
2838 radeon_emit(cs, stride); /* stride */
2839 radeon_emit(cs, di_src_sel);
2840 }
2841 }
2842
2843 static void
2844 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2845 VkBuffer _buffer,
2846 VkDeviceSize offset,
2847 VkBuffer _count_buffer,
2848 VkDeviceSize count_offset,
2849 uint32_t draw_count,
2850 uint32_t stride,
2851 bool indexed)
2852 {
2853 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2854 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2855 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2856
2857 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2858 indirect_va += offset + buffer->offset;
2859 uint64_t count_va = 0;
2860
2861 if (count_buffer) {
2862 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2863 count_va += count_offset + count_buffer->offset;
2864 }
2865
2866 if (!draw_count)
2867 return;
2868
2869 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2870
2871 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2872 radeon_emit(cs, 1);
2873 radeon_emit(cs, indirect_va);
2874 radeon_emit(cs, indirect_va >> 32);
2875
2876 if (!cmd_buffer->state.subpass->view_mask) {
2877 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2878 } else {
2879 unsigned i;
2880 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2881 radv_emit_view_index(cmd_buffer, i);
2882
2883 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2884 }
2885 }
2886 radv_cmd_buffer_trace_emit(cmd_buffer);
2887 }
2888
2889 static void
2890 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2891 VkBuffer buffer,
2892 VkDeviceSize offset,
2893 VkBuffer countBuffer,
2894 VkDeviceSize countBufferOffset,
2895 uint32_t maxDrawCount,
2896 uint32_t stride)
2897 {
2898 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2899 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2900
2901 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2902 cmd_buffer->cs, 24 * MAX_VIEWS);
2903
2904 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2905 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2906
2907 assert(cmd_buffer->cs->cdw <= cdw_max);
2908 }
2909
2910 static void
2911 radv_cmd_draw_indexed_indirect_count(
2912 VkCommandBuffer commandBuffer,
2913 VkBuffer buffer,
2914 VkDeviceSize offset,
2915 VkBuffer countBuffer,
2916 VkDeviceSize countBufferOffset,
2917 uint32_t maxDrawCount,
2918 uint32_t stride)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921 uint64_t index_va;
2922 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2923
2924 index_va = cmd_buffer->state.index_va;
2925
2926 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
2927
2928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2929 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2930
2931 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2932 radeon_emit(cmd_buffer->cs, index_va);
2933 radeon_emit(cmd_buffer->cs, index_va >> 32);
2934
2935 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2936 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2937
2938 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2939 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2940
2941 assert(cmd_buffer->cs->cdw <= cdw_max);
2942 }
2943
2944 void radv_CmdDrawIndirect(
2945 VkCommandBuffer commandBuffer,
2946 VkBuffer buffer,
2947 VkDeviceSize offset,
2948 uint32_t drawCount,
2949 uint32_t stride)
2950 {
2951 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2952 VK_NULL_HANDLE, 0, drawCount, stride);
2953 }
2954
2955 void radv_CmdDrawIndexedIndirect(
2956 VkCommandBuffer commandBuffer,
2957 VkBuffer buffer,
2958 VkDeviceSize offset,
2959 uint32_t drawCount,
2960 uint32_t stride)
2961 {
2962 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2963 VK_NULL_HANDLE, 0, drawCount, stride);
2964 }
2965
2966 void radv_CmdDrawIndirectCountAMD(
2967 VkCommandBuffer commandBuffer,
2968 VkBuffer buffer,
2969 VkDeviceSize offset,
2970 VkBuffer countBuffer,
2971 VkDeviceSize countBufferOffset,
2972 uint32_t maxDrawCount,
2973 uint32_t stride)
2974 {
2975 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2976 countBuffer, countBufferOffset,
2977 maxDrawCount, stride);
2978 }
2979
2980 void radv_CmdDrawIndexedIndirectCountAMD(
2981 VkCommandBuffer commandBuffer,
2982 VkBuffer buffer,
2983 VkDeviceSize offset,
2984 VkBuffer countBuffer,
2985 VkDeviceSize countBufferOffset,
2986 uint32_t maxDrawCount,
2987 uint32_t stride)
2988 {
2989 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2990 countBuffer, countBufferOffset,
2991 maxDrawCount, stride);
2992 }
2993
2994 static void
2995 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2996 {
2997 radv_emit_compute_pipeline(cmd_buffer);
2998 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2999 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3000 VK_SHADER_STAGE_COMPUTE_BIT);
3001 si_emit_cache_flush(cmd_buffer);
3002 }
3003
3004 void radv_CmdDispatch(
3005 VkCommandBuffer commandBuffer,
3006 uint32_t x,
3007 uint32_t y,
3008 uint32_t z)
3009 {
3010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3011
3012 radv_flush_compute_state(cmd_buffer);
3013
3014 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
3015
3016 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3017 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3018 if (loc->sgpr_idx != -1) {
3019 assert(!loc->indirect);
3020 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3021 assert(loc->num_sgprs == grid_used);
3022 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3023 radeon_emit(cmd_buffer->cs, x);
3024 if (grid_used > 1)
3025 radeon_emit(cmd_buffer->cs, y);
3026 if (grid_used > 2)
3027 radeon_emit(cmd_buffer->cs, z);
3028 }
3029
3030 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3031 PKT3_SHADER_TYPE_S(1));
3032 radeon_emit(cmd_buffer->cs, x);
3033 radeon_emit(cmd_buffer->cs, y);
3034 radeon_emit(cmd_buffer->cs, z);
3035 radeon_emit(cmd_buffer->cs, 1);
3036
3037 assert(cmd_buffer->cs->cdw <= cdw_max);
3038 radv_cmd_buffer_trace_emit(cmd_buffer);
3039 }
3040
3041 void radv_CmdDispatchIndirect(
3042 VkCommandBuffer commandBuffer,
3043 VkBuffer _buffer,
3044 VkDeviceSize offset)
3045 {
3046 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3047 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3048 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
3049 va += buffer->offset + offset;
3050
3051 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
3052
3053 radv_flush_compute_state(cmd_buffer);
3054
3055 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
3056 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3057 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3058 if (loc->sgpr_idx != -1) {
3059 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3060 for (unsigned i = 0; i < grid_used; ++i) {
3061 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
3062 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3063 COPY_DATA_DST_SEL(COPY_DATA_REG));
3064 radeon_emit(cmd_buffer->cs, (va + 4 * i));
3065 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
3066 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
3067 radeon_emit(cmd_buffer->cs, 0);
3068 }
3069 }
3070
3071 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3072 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3073 PKT3_SHADER_TYPE_S(1));
3074 radeon_emit(cmd_buffer->cs, va);
3075 radeon_emit(cmd_buffer->cs, va >> 32);
3076 radeon_emit(cmd_buffer->cs, 1);
3077 } else {
3078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
3079 PKT3_SHADER_TYPE_S(1));
3080 radeon_emit(cmd_buffer->cs, 1);
3081 radeon_emit(cmd_buffer->cs, va);
3082 radeon_emit(cmd_buffer->cs, va >> 32);
3083
3084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3085 PKT3_SHADER_TYPE_S(1));
3086 radeon_emit(cmd_buffer->cs, 0);
3087 radeon_emit(cmd_buffer->cs, 1);
3088 }
3089
3090 assert(cmd_buffer->cs->cdw <= cdw_max);
3091 radv_cmd_buffer_trace_emit(cmd_buffer);
3092 }
3093
3094 void radv_unaligned_dispatch(
3095 struct radv_cmd_buffer *cmd_buffer,
3096 uint32_t x,
3097 uint32_t y,
3098 uint32_t z)
3099 {
3100 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3101 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3102 uint32_t blocks[3], remainder[3];
3103
3104 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3105 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3106 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3107
3108 /* If aligned, these should be an entire block size, not 0 */
3109 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3110 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3111 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3112
3113 radv_flush_compute_state(cmd_buffer);
3114
3115 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3116
3117 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3118 radeon_emit(cmd_buffer->cs,
3119 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3120 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3121 radeon_emit(cmd_buffer->cs,
3122 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3123 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3124 radeon_emit(cmd_buffer->cs,
3125 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3126 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3127
3128 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3129 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3130 if (loc->sgpr_idx != -1) {
3131 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3132 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3133 radeon_emit(cmd_buffer->cs, blocks[0]);
3134 if (grid_used > 1)
3135 radeon_emit(cmd_buffer->cs, blocks[1]);
3136 if (grid_used > 2)
3137 radeon_emit(cmd_buffer->cs, blocks[2]);
3138 }
3139 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3140 PKT3_SHADER_TYPE_S(1));
3141 radeon_emit(cmd_buffer->cs, blocks[0]);
3142 radeon_emit(cmd_buffer->cs, blocks[1]);
3143 radeon_emit(cmd_buffer->cs, blocks[2]);
3144 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3145 S_00B800_PARTIAL_TG_EN(1));
3146
3147 assert(cmd_buffer->cs->cdw <= cdw_max);
3148 radv_cmd_buffer_trace_emit(cmd_buffer);
3149 }
3150
3151 void radv_CmdEndRenderPass(
3152 VkCommandBuffer commandBuffer)
3153 {
3154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3155
3156 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3157
3158 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3159
3160 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3161 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3162 radv_handle_subpass_image_transition(cmd_buffer,
3163 (VkAttachmentReference){i, layout});
3164 }
3165
3166 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3167
3168 cmd_buffer->state.pass = NULL;
3169 cmd_buffer->state.subpass = NULL;
3170 cmd_buffer->state.attachments = NULL;
3171 cmd_buffer->state.framebuffer = NULL;
3172 }
3173
3174 /*
3175 * For HTILE we have the following interesting clear words:
3176 * 0x0000030f: Uncompressed.
3177 * 0xfffffff0: Clear depth to 1.0
3178 * 0x00000000: Clear depth to 0.0
3179 */
3180 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3181 struct radv_image *image,
3182 const VkImageSubresourceRange *range,
3183 uint32_t clear_word)
3184 {
3185 assert(range->baseMipLevel == 0);
3186 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3187 unsigned layer_count = radv_get_layerCount(image, range);
3188 uint64_t size = image->surface.htile_slice_size * layer_count;
3189 uint64_t offset = image->offset + image->htile_offset +
3190 image->surface.htile_slice_size * range->baseArrayLayer;
3191
3192 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3193 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3194
3195 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3196
3197 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3198 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3199 RADV_CMD_FLAG_INV_VMEM_L1 |
3200 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3201 }
3202
3203 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3204 struct radv_image *image,
3205 VkImageLayout src_layout,
3206 VkImageLayout dst_layout,
3207 unsigned src_queue_mask,
3208 unsigned dst_queue_mask,
3209 const VkImageSubresourceRange *range,
3210 VkImageAspectFlags pending_clears)
3211 {
3212 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3213 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3214 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3215 cmd_buffer->state.render_area.extent.width == image->info.width &&
3216 cmd_buffer->state.render_area.extent.height == image->info.height) {
3217 /* The clear will initialize htile. */
3218 return;
3219 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3220 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3221 /* TODO: merge with the clear if applicable */
3222 radv_initialize_htile(cmd_buffer, image, range, 0);
3223 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3224 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3225 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3226 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3227 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3228 VkImageSubresourceRange local_range = *range;
3229 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3230 local_range.baseMipLevel = 0;
3231 local_range.levelCount = 1;
3232
3233 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3234 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3235
3236 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3237
3238 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3239 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3240 }
3241 }
3242
3243 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3244 struct radv_image *image, uint32_t value)
3245 {
3246 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3247 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3248
3249 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3250 image->cmask.size, value);
3251
3252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3253 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3254 RADV_CMD_FLAG_INV_VMEM_L1 |
3255 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3256 }
3257
3258 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3259 struct radv_image *image,
3260 VkImageLayout src_layout,
3261 VkImageLayout dst_layout,
3262 unsigned src_queue_mask,
3263 unsigned dst_queue_mask,
3264 const VkImageSubresourceRange *range,
3265 VkImageAspectFlags pending_clears)
3266 {
3267 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3268 if (image->fmask.size)
3269 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3270 else
3271 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3272 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3273 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3274 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3275 }
3276 }
3277
3278 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3279 struct radv_image *image, uint32_t value)
3280 {
3281
3282 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3283 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3284
3285 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3286 image->surface.dcc_size, value);
3287
3288 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3289 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3290 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3291 RADV_CMD_FLAG_INV_VMEM_L1 |
3292 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3293 }
3294
3295 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3296 struct radv_image *image,
3297 VkImageLayout src_layout,
3298 VkImageLayout dst_layout,
3299 unsigned src_queue_mask,
3300 unsigned dst_queue_mask,
3301 const VkImageSubresourceRange *range,
3302 VkImageAspectFlags pending_clears)
3303 {
3304 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3305 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3306 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3307 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3308 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3309 }
3310 }
3311
3312 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3313 struct radv_image *image,
3314 VkImageLayout src_layout,
3315 VkImageLayout dst_layout,
3316 uint32_t src_family,
3317 uint32_t dst_family,
3318 const VkImageSubresourceRange *range,
3319 VkImageAspectFlags pending_clears)
3320 {
3321 if (image->exclusive && src_family != dst_family) {
3322 /* This is an acquire or a release operation and there will be
3323 * a corresponding release/acquire. Do the transition in the
3324 * most flexible queue. */
3325
3326 assert(src_family == cmd_buffer->queue_family_index ||
3327 dst_family == cmd_buffer->queue_family_index);
3328
3329 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3330 return;
3331
3332 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3333 (src_family == RADV_QUEUE_GENERAL ||
3334 dst_family == RADV_QUEUE_GENERAL))
3335 return;
3336 }
3337
3338 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3339 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3340
3341 if (image->surface.htile_size)
3342 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3343 dst_layout, src_queue_mask,
3344 dst_queue_mask, range,
3345 pending_clears);
3346
3347 if (image->cmask.size)
3348 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3349 dst_layout, src_queue_mask,
3350 dst_queue_mask, range,
3351 pending_clears);
3352
3353 if (image->surface.dcc_size)
3354 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3355 dst_layout, src_queue_mask,
3356 dst_queue_mask, range,
3357 pending_clears);
3358 }
3359
3360 void radv_CmdPipelineBarrier(
3361 VkCommandBuffer commandBuffer,
3362 VkPipelineStageFlags srcStageMask,
3363 VkPipelineStageFlags destStageMask,
3364 VkBool32 byRegion,
3365 uint32_t memoryBarrierCount,
3366 const VkMemoryBarrier* pMemoryBarriers,
3367 uint32_t bufferMemoryBarrierCount,
3368 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3369 uint32_t imageMemoryBarrierCount,
3370 const VkImageMemoryBarrier* pImageMemoryBarriers)
3371 {
3372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3373 enum radv_cmd_flush_bits src_flush_bits = 0;
3374 enum radv_cmd_flush_bits dst_flush_bits = 0;
3375
3376 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3377 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3378 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3379 NULL);
3380 }
3381
3382 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3383 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3384 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3385 NULL);
3386 }
3387
3388 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3389 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3390 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3391 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3392 image);
3393 }
3394
3395 radv_stage_flush(cmd_buffer, srcStageMask);
3396 cmd_buffer->state.flush_bits |= src_flush_bits;
3397
3398 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3399 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3400 radv_handle_image_transition(cmd_buffer, image,
3401 pImageMemoryBarriers[i].oldLayout,
3402 pImageMemoryBarriers[i].newLayout,
3403 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3404 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3405 &pImageMemoryBarriers[i].subresourceRange,
3406 0);
3407 }
3408
3409 cmd_buffer->state.flush_bits |= dst_flush_bits;
3410 }
3411
3412
3413 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3414 struct radv_event *event,
3415 VkPipelineStageFlags stageMask,
3416 unsigned value)
3417 {
3418 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3419 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3420
3421 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3422
3423 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3424
3425 /* TODO: this is overkill. Probably should figure something out from
3426 * the stage mask. */
3427
3428 si_cs_emit_write_event_eop(cs,
3429 cmd_buffer->state.predicating,
3430 cmd_buffer->device->physical_device->rad_info.chip_class,
3431 false,
3432 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3433 1, va, 2, value);
3434
3435 assert(cmd_buffer->cs->cdw <= cdw_max);
3436 }
3437
3438 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3439 VkEvent _event,
3440 VkPipelineStageFlags stageMask)
3441 {
3442 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3443 RADV_FROM_HANDLE(radv_event, event, _event);
3444
3445 write_event(cmd_buffer, event, stageMask, 1);
3446 }
3447
3448 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3449 VkEvent _event,
3450 VkPipelineStageFlags stageMask)
3451 {
3452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3453 RADV_FROM_HANDLE(radv_event, event, _event);
3454
3455 write_event(cmd_buffer, event, stageMask, 0);
3456 }
3457
3458 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3459 uint32_t eventCount,
3460 const VkEvent* pEvents,
3461 VkPipelineStageFlags srcStageMask,
3462 VkPipelineStageFlags dstStageMask,
3463 uint32_t memoryBarrierCount,
3464 const VkMemoryBarrier* pMemoryBarriers,
3465 uint32_t bufferMemoryBarrierCount,
3466 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3467 uint32_t imageMemoryBarrierCount,
3468 const VkImageMemoryBarrier* pImageMemoryBarriers)
3469 {
3470 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3471 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3472
3473 for (unsigned i = 0; i < eventCount; ++i) {
3474 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3475 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3476
3477 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3478
3479 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3480
3481 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3482 assert(cmd_buffer->cs->cdw <= cdw_max);
3483 }
3484
3485
3486 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3487 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3488
3489 radv_handle_image_transition(cmd_buffer, image,
3490 pImageMemoryBarriers[i].oldLayout,
3491 pImageMemoryBarriers[i].newLayout,
3492 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3493 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3494 &pImageMemoryBarriers[i].subresourceRange,
3495 0);
3496 }
3497
3498 /* TODO: figure out how to do memory barriers without waiting */
3499 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3500 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3501 RADV_CMD_FLAG_INV_VMEM_L1 |
3502 RADV_CMD_FLAG_INV_SMEM_L1;
3503 }