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3b1d6aedc81a43b78c1647050cc938bbe08c35ea
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safefly call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING);
351
352 if (!bo) {
353 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
354 return false;
355 }
356
357 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
358 if (cmd_buffer->upload.upload_bo) {
359 upload = malloc(sizeof(*upload));
360
361 if (!upload) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
363 device->ws->buffer_destroy(bo);
364 return false;
365 }
366
367 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
368 list_add(&upload->list, &cmd_buffer->upload.list);
369 }
370
371 cmd_buffer->upload.upload_bo = bo;
372 cmd_buffer->upload.size = new_size;
373 cmd_buffer->upload.offset = 0;
374 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
375
376 if (!cmd_buffer->upload.map) {
377 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
378 return false;
379 }
380
381 return true;
382 }
383
384 bool
385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
386 unsigned size,
387 unsigned alignment,
388 unsigned *out_offset,
389 void **ptr)
390 {
391 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
392 if (offset + size > cmd_buffer->upload.size) {
393 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
394 return false;
395 offset = 0;
396 }
397
398 *out_offset = offset;
399 *ptr = cmd_buffer->upload.map + offset;
400
401 cmd_buffer->upload.offset = offset + size;
402 return true;
403 }
404
405 bool
406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
407 unsigned size, unsigned alignment,
408 const void *data, unsigned *out_offset)
409 {
410 uint8_t *ptr;
411
412 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
413 out_offset, (void **)&ptr))
414 return false;
415
416 if (ptr)
417 memcpy(ptr, data, size);
418
419 return true;
420 }
421
422 static void
423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
424 unsigned count, const uint32_t *data)
425 {
426 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
427 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
428 S_370_WR_CONFIRM(1) |
429 S_370_ENGINE_SEL(V_370_ME));
430 radeon_emit(cs, va);
431 radeon_emit(cs, va >> 32);
432 radeon_emit_array(cs, data, count);
433 }
434
435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
436 {
437 struct radv_device *device = cmd_buffer->device;
438 struct radeon_winsys_cs *cs = cmd_buffer->cs;
439 uint64_t va;
440
441 va = radv_buffer_get_va(device->trace_bo);
442 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
443 va += 4;
444
445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
446
447 ++cmd_buffer->state.trace_id;
448 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
449 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
451 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
452 }
453
454 static void
455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
456 enum radv_cmd_flush_bits flags)
457 {
458 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
459 uint32_t *ptr = NULL;
460 uint64_t va = 0;
461
462 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
464
465 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
466 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
467 cmd_buffer->gfx9_fence_offset;
468 ptr = &cmd_buffer->gfx9_fence_idx;
469 }
470
471 /* Force wait for graphics or compute engines to be idle. */
472 si_cs_emit_cache_flush(cmd_buffer->cs,
473 cmd_buffer->device->physical_device->rad_info.chip_class,
474 ptr, va,
475 radv_cmd_buffer_uses_mec(cmd_buffer),
476 flags);
477 }
478
479 if (unlikely(cmd_buffer->device->trace_bo))
480 radv_cmd_buffer_trace_emit(cmd_buffer);
481 }
482
483 static void
484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
485 struct radv_pipeline *pipeline, enum ring_type ring)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[2];
490 uint64_t va;
491
492 va = radv_buffer_get_va(device->trace_bo);
493
494 switch (ring) {
495 case RING_GFX:
496 va += 8;
497 break;
498 case RING_COMPUTE:
499 va += 16;
500 break;
501 default:
502 assert(!"invalid ring type");
503 }
504
505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
506 cmd_buffer->cs, 6);
507
508 data[0] = (uintptr_t)pipeline;
509 data[1] = (uintptr_t)pipeline >> 32;
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, 2, data);
513 }
514
515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
516 VkPipelineBindPoint bind_point,
517 struct radv_descriptor_set *set,
518 unsigned idx)
519 {
520 struct radv_descriptor_state *descriptors_state =
521 radv_get_descriptors_state(cmd_buffer, bind_point);
522
523 descriptors_state->sets[idx] = set;
524 if (set)
525 descriptors_state->valid |= (1u << idx);
526 else
527 descriptors_state->valid &= ~(1u << idx);
528 descriptors_state->dirty |= (1u << idx);
529 }
530
531 static void
532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
533 VkPipelineBindPoint bind_point)
534 {
535 struct radv_descriptor_state *descriptors_state =
536 radv_get_descriptors_state(cmd_buffer, bind_point);
537 struct radv_device *device = cmd_buffer->device;
538 struct radeon_winsys_cs *cs = cmd_buffer->cs;
539 uint32_t data[MAX_SETS * 2] = {};
540 uint64_t va;
541 unsigned i;
542 va = radv_buffer_get_va(device->trace_bo) + 24;
543
544 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
545 cmd_buffer->cs, 4 + MAX_SETS * 2);
546
547 for_each_bit(i, descriptors_state->valid) {
548 struct radv_descriptor_set *set = descriptors_state->sets[i];
549 data[i * 2] = (uintptr_t)set;
550 data[i * 2 + 1] = (uintptr_t)set >> 32;
551 }
552
553 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
554 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
555 }
556
557 struct radv_userdata_info *
558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
559 gl_shader_stage stage,
560 int idx)
561 {
562 if (stage == MESA_SHADER_VERTEX) {
563 if (pipeline->shaders[MESA_SHADER_VERTEX])
564 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
565 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
566 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
567 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
568 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
569 } else if (stage == MESA_SHADER_TESS_EVAL) {
570 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
571 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 }
575 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
576 }
577
578 static void
579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
580 struct radv_pipeline *pipeline,
581 gl_shader_stage stage,
582 int idx, uint64_t va)
583 {
584 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
585 uint32_t base_reg = pipeline->user_data_0[stage];
586 if (loc->sgpr_idx == -1)
587 return;
588 assert(loc->num_sgprs == 2);
589 assert(!loc->indirect);
590 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
591 radeon_emit(cmd_buffer->cs, va);
592 radeon_emit(cmd_buffer->cs, va >> 32);
593 }
594
595 static void
596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
597 struct radv_pipeline *pipeline)
598 {
599 int num_samples = pipeline->graphics.ms.num_samples;
600 struct radv_multisample_state *ms = &pipeline->graphics.ms;
601 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
602
603 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
604 cmd_buffer->sample_positions_needed = true;
605
606 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
607 return;
608
609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
611 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
614
615 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
616
617 /* GFX9: Flush DFSM when the AA mode changes. */
618 if (cmd_buffer->device->dfsm_allowed) {
619 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
620 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
621 }
622 }
623
624 static void
625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
626 struct radv_shader_variant *shader)
627 {
628 uint64_t va;
629
630 if (!shader)
631 return;
632
633 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
634
635 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
636 }
637
638 static void
639 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_pipeline *pipeline,
641 bool vertex_stage_only)
642 {
643 struct radv_cmd_state *state = &cmd_buffer->state;
644 uint32_t mask = state->prefetch_L2_mask;
645
646 if (vertex_stage_only) {
647 /* Fast prefetch path for starting draws as soon as possible.
648 */
649 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
650 RADV_PREFETCH_VBO_DESCRIPTORS);
651 }
652
653 if (mask & RADV_PREFETCH_VS)
654 radv_emit_shader_prefetch(cmd_buffer,
655 pipeline->shaders[MESA_SHADER_VERTEX]);
656
657 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
658 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
659
660 if (mask & RADV_PREFETCH_TCS)
661 radv_emit_shader_prefetch(cmd_buffer,
662 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
663
664 if (mask & RADV_PREFETCH_TES)
665 radv_emit_shader_prefetch(cmd_buffer,
666 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
667
668 if (mask & RADV_PREFETCH_GS) {
669 radv_emit_shader_prefetch(cmd_buffer,
670 pipeline->shaders[MESA_SHADER_GEOMETRY]);
671 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
672 }
673
674 if (mask & RADV_PREFETCH_PS)
675 radv_emit_shader_prefetch(cmd_buffer,
676 pipeline->shaders[MESA_SHADER_FRAGMENT]);
677
678 state->prefetch_L2_mask &= ~mask;
679 }
680
681 static void
682 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
683 {
684 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
685
686 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
687 return;
688
689 radv_update_multisample_state(cmd_buffer, pipeline);
690
691 cmd_buffer->scratch_size_needed =
692 MAX2(cmd_buffer->scratch_size_needed,
693 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
694
695 if (!cmd_buffer->state.emitted_pipeline ||
696 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
697 pipeline->graphics.can_use_guardband)
698 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
699
700 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
701
702 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
703 if (!pipeline->shaders[i])
704 continue;
705
706 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
707 pipeline->shaders[i]->bo, 8);
708 }
709
710 if (radv_pipeline_has_gs(pipeline))
711 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
712 pipeline->gs_copy_shader->bo, 8);
713
714 if (unlikely(cmd_buffer->device->trace_bo))
715 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
716
717 cmd_buffer->state.emitted_pipeline = pipeline;
718
719 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
720 }
721
722 static void
723 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
724 {
725 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
726 cmd_buffer->state.dynamic.viewport.viewports);
727 }
728
729 static void
730 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
731 {
732 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
733
734 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
735 * scissor registers are changed. There is also a more efficient but
736 * more involved alternative workaround.
737 */
738 if (cmd_buffer->device->physical_device->has_scissor_bug) {
739 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
740 si_emit_cache_flush(cmd_buffer);
741 }
742 si_write_scissors(cmd_buffer->cs, 0, count,
743 cmd_buffer->state.dynamic.scissor.scissors,
744 cmd_buffer->state.dynamic.viewport.viewports,
745 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
746 }
747
748 static void
749 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
750 {
751 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
752 return;
753
754 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
755 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
756 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
757 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
758 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
759 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
760 S_028214_BR_Y(rect.offset.y + rect.extent.height));
761 }
762 }
763
764 static void
765 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
766 {
767 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
768
769 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
770 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
771 }
772
773 static void
774 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
777
778 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
779 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
780 }
781
782 static void
783 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
784 {
785 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
786
787 radeon_set_context_reg_seq(cmd_buffer->cs,
788 R_028430_DB_STENCILREFMASK, 2);
789 radeon_emit(cmd_buffer->cs,
790 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
791 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
792 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
793 S_028430_STENCILOPVAL(1));
794 radeon_emit(cmd_buffer->cs,
795 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
796 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
797 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
798 S_028434_STENCILOPVAL_BF(1));
799 }
800
801 static void
802 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
803 {
804 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
805
806 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
807 fui(d->depth_bounds.min));
808 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
809 fui(d->depth_bounds.max));
810 }
811
812 static void
813 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
814 {
815 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
816 unsigned slope = fui(d->depth_bias.slope * 16.0f);
817 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
818
819
820 radeon_set_context_reg_seq(cmd_buffer->cs,
821 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
822 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
823 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
824 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
825 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
826 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
827 }
828
829 static void
830 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
831 int index,
832 struct radv_attachment_info *att,
833 struct radv_image *image,
834 VkImageLayout layout)
835 {
836 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
837 struct radv_color_buffer_info *cb = &att->cb;
838 uint32_t cb_color_info = cb->cb_color_info;
839
840 if (!radv_layout_dcc_compressed(image, layout,
841 radv_image_queue_family_mask(image,
842 cmd_buffer->queue_family_index,
843 cmd_buffer->queue_family_index))) {
844 cb_color_info &= C_028C70_DCC_ENABLE;
845 }
846
847 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
848 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
849 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
850 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
851 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
852 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
853 radeon_emit(cmd_buffer->cs, cb_color_info);
854 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
855 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
856 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
857 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
858 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
859 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
860
861 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
862 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
863 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
864
865 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
866 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
867 } else {
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
869 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
870 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
871 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
872 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
873 radeon_emit(cmd_buffer->cs, cb_color_info);
874 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
875 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
876 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
877 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
878 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
879 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
880
881 if (is_vi) { /* DCC BASE */
882 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
883 }
884 }
885 }
886
887 static void
888 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_ds_buffer_info *ds,
890 struct radv_image *image,
891 VkImageLayout layout)
892 {
893 uint32_t db_z_info = ds->db_z_info;
894 uint32_t db_stencil_info = ds->db_stencil_info;
895
896 if (!radv_layout_has_htile(image, layout,
897 radv_image_queue_family_mask(image,
898 cmd_buffer->queue_family_index,
899 cmd_buffer->queue_family_index))) {
900 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
901 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
902 }
903
904 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
905 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
906
907
908 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
909 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
910 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
911 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
912 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
915 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
916 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
917 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
918 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
919 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
920 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
921 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
922 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
923 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
924 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
925
926 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
927 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
928 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
929 } else {
930 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
931
932 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
933 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
934 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
935 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
936 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
937 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
938 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
939 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
940 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
941 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
942
943 }
944
945 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
946 ds->pa_su_poly_offset_db_fmt_cntl);
947 }
948
949 void
950 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
951 struct radv_image *image,
952 VkClearDepthStencilValue ds_clear_value,
953 VkImageAspectFlags aspects)
954 {
955 uint64_t va = radv_buffer_get_va(image->bo);
956 va += image->offset + image->clear_value_offset;
957 unsigned reg_offset = 0, reg_count = 0;
958
959 assert(radv_image_has_htile(image));
960
961 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
962 ++reg_count;
963 } else {
964 ++reg_offset;
965 va += 4;
966 }
967 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
968 ++reg_count;
969
970 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
971 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
972 S_370_WR_CONFIRM(1) |
973 S_370_ENGINE_SEL(V_370_PFP));
974 radeon_emit(cmd_buffer->cs, va);
975 radeon_emit(cmd_buffer->cs, va >> 32);
976 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
977 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
978 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
979 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
980
981 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
982 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
983 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
984 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
985 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
986 }
987
988 static void
989 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
990 struct radv_image *image)
991 {
992 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
993 uint64_t va = radv_buffer_get_va(image->bo);
994 va += image->offset + image->clear_value_offset;
995 unsigned reg_offset = 0, reg_count = 0;
996
997 if (!radv_image_has_htile(image))
998 return;
999
1000 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1001 ++reg_count;
1002 } else {
1003 ++reg_offset;
1004 va += 4;
1005 }
1006 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1007 ++reg_count;
1008
1009 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1010 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1011 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1012 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1013 radeon_emit(cmd_buffer->cs, va);
1014 radeon_emit(cmd_buffer->cs, va >> 32);
1015 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1016 radeon_emit(cmd_buffer->cs, 0);
1017
1018 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1019 radeon_emit(cmd_buffer->cs, 0);
1020 }
1021
1022 /*
1023 *with DCC some colors don't require CMASK elimiation before being
1024 * used as a texture. This sets a predicate value to determine if the
1025 * cmask eliminate is required.
1026 */
1027 void
1028 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1029 struct radv_image *image,
1030 bool value)
1031 {
1032 uint64_t pred_val = value;
1033 uint64_t va = radv_buffer_get_va(image->bo);
1034 va += image->offset + image->dcc_pred_offset;
1035
1036 assert(radv_image_has_dcc(image));
1037
1038 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1039 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1040 S_370_WR_CONFIRM(1) |
1041 S_370_ENGINE_SEL(V_370_PFP));
1042 radeon_emit(cmd_buffer->cs, va);
1043 radeon_emit(cmd_buffer->cs, va >> 32);
1044 radeon_emit(cmd_buffer->cs, pred_val);
1045 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1046 }
1047
1048 void
1049 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1050 struct radv_image *image,
1051 int idx,
1052 uint32_t color_values[2])
1053 {
1054 uint64_t va = radv_buffer_get_va(image->bo);
1055 va += image->offset + image->clear_value_offset;
1056
1057 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1058
1059 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1060 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1061 S_370_WR_CONFIRM(1) |
1062 S_370_ENGINE_SEL(V_370_PFP));
1063 radeon_emit(cmd_buffer->cs, va);
1064 radeon_emit(cmd_buffer->cs, va >> 32);
1065 radeon_emit(cmd_buffer->cs, color_values[0]);
1066 radeon_emit(cmd_buffer->cs, color_values[1]);
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1069 radeon_emit(cmd_buffer->cs, color_values[0]);
1070 radeon_emit(cmd_buffer->cs, color_values[1]);
1071 }
1072
1073 static void
1074 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1075 struct radv_image *image,
1076 int idx)
1077 {
1078 uint64_t va = radv_buffer_get_va(image->bo);
1079 va += image->offset + image->clear_value_offset;
1080
1081 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1082 return;
1083
1084 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1085
1086 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1087 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1088 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1089 COPY_DATA_COUNT_SEL);
1090 radeon_emit(cmd_buffer->cs, va);
1091 radeon_emit(cmd_buffer->cs, va >> 32);
1092 radeon_emit(cmd_buffer->cs, reg >> 2);
1093 radeon_emit(cmd_buffer->cs, 0);
1094
1095 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1096 radeon_emit(cmd_buffer->cs, 0);
1097 }
1098
1099 static void
1100 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1101 {
1102 int i;
1103 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1104 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1105
1106 /* this may happen for inherited secondary recording */
1107 if (!framebuffer)
1108 return;
1109
1110 for (i = 0; i < 8; ++i) {
1111 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1112 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1113 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1114 continue;
1115 }
1116
1117 int idx = subpass->color_attachments[i].attachment;
1118 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1119 struct radv_image *image = att->attachment->image;
1120 VkImageLayout layout = subpass->color_attachments[i].layout;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1123
1124 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1125 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1126
1127 radv_load_color_clear_regs(cmd_buffer, image, i);
1128 }
1129
1130 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1131 int idx = subpass->depth_stencil_attachment.attachment;
1132 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1133 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1134 struct radv_image *image = att->attachment->image;
1135 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1136 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1137 cmd_buffer->queue_family_index,
1138 cmd_buffer->queue_family_index);
1139 /* We currently don't support writing decompressed HTILE */
1140 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1141 radv_layout_is_htile_compressed(image, layout, queue_mask));
1142
1143 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1144
1145 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1146 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1147 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1148 }
1149 radv_load_depth_clear_regs(cmd_buffer, image);
1150 } else {
1151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1153 else
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1155
1156 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1158 }
1159 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1160 S_028208_BR_X(framebuffer->width) |
1161 S_028208_BR_Y(framebuffer->height));
1162
1163 if (cmd_buffer->device->dfsm_allowed) {
1164 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1165 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1166 }
1167
1168 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1169 }
1170
1171 static void
1172 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1173 {
1174 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1175 struct radv_cmd_state *state = &cmd_buffer->state;
1176
1177 if (state->index_type != state->last_index_type) {
1178 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1179 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1180 2, state->index_type);
1181 } else {
1182 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1183 radeon_emit(cs, state->index_type);
1184 }
1185
1186 state->last_index_type = state->index_type;
1187 }
1188
1189 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1190 radeon_emit(cs, state->index_va);
1191 radeon_emit(cs, state->index_va >> 32);
1192
1193 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1194 radeon_emit(cs, state->max_index_count);
1195
1196 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1197 }
1198
1199 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1200 {
1201 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1202 uint32_t pa_sc_mode_cntl_1 =
1203 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1204 uint32_t db_count_control;
1205
1206 if(!cmd_buffer->state.active_occlusion_queries) {
1207 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1208 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1209 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1210 /* Re-enable out-of-order rasterization if the
1211 * bound pipeline supports it and if it's has
1212 * been disabled before starting occlusion
1213 * queries.
1214 */
1215 radeon_set_context_reg(cmd_buffer->cs,
1216 R_028A4C_PA_SC_MODE_CNTL_1,
1217 pa_sc_mode_cntl_1);
1218 }
1219 db_count_control = 0;
1220 } else {
1221 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1222 }
1223 } else {
1224 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1225 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1226 bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled;
1227
1228 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1229 db_count_control =
1230 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1231 S_028004_SAMPLE_RATE(sample_rate) |
1232 S_028004_ZPASS_ENABLE(1) |
1233 S_028004_SLICE_EVEN_ENABLE(1) |
1234 S_028004_SLICE_ODD_ENABLE(1);
1235
1236 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1237 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1238 /* If the bound pipeline has enabled
1239 * out-of-order rasterization, we should
1240 * disable it before starting occlusion
1241 * queries.
1242 */
1243 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1244
1245 radeon_set_context_reg(cmd_buffer->cs,
1246 R_028A4C_PA_SC_MODE_CNTL_1,
1247 pa_sc_mode_cntl_1);
1248 }
1249 } else {
1250 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1251 S_028004_SAMPLE_RATE(sample_rate);
1252 }
1253 }
1254
1255 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1256 }
1257
1258 static void
1259 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1260 {
1261 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1262
1263 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1264 radv_emit_viewport(cmd_buffer);
1265
1266 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1267 radv_emit_scissor(cmd_buffer);
1268
1269 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1270 radv_emit_line_width(cmd_buffer);
1271
1272 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1273 radv_emit_blend_constants(cmd_buffer);
1274
1275 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1276 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1277 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1278 radv_emit_stencil(cmd_buffer);
1279
1280 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1281 radv_emit_depth_bounds(cmd_buffer);
1282
1283 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1284 radv_emit_depth_bias(cmd_buffer);
1285
1286 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1287 radv_emit_discard_rectangle(cmd_buffer);
1288
1289 cmd_buffer->state.dirty &= ~states;
1290 }
1291
1292 static void
1293 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1294 struct radv_pipeline *pipeline,
1295 int idx,
1296 uint64_t va,
1297 gl_shader_stage stage)
1298 {
1299 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1300 uint32_t base_reg = pipeline->user_data_0[stage];
1301
1302 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1303 return;
1304
1305 assert(!desc_set_loc->indirect);
1306 assert(desc_set_loc->num_sgprs == 2);
1307 radeon_set_sh_reg_seq(cmd_buffer->cs,
1308 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1309 radeon_emit(cmd_buffer->cs, va);
1310 radeon_emit(cmd_buffer->cs, va >> 32);
1311 }
1312
1313 static void
1314 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1315 VkShaderStageFlags stages,
1316 struct radv_descriptor_set *set,
1317 unsigned idx)
1318 {
1319 if (cmd_buffer->state.pipeline) {
1320 radv_foreach_stage(stage, stages) {
1321 if (cmd_buffer->state.pipeline->shaders[stage])
1322 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1323 idx, set->va,
1324 stage);
1325 }
1326 }
1327
1328 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1329 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1330 idx, set->va,
1331 MESA_SHADER_COMPUTE);
1332 }
1333
1334 static void
1335 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1336 VkPipelineBindPoint bind_point)
1337 {
1338 struct radv_descriptor_state *descriptors_state =
1339 radv_get_descriptors_state(cmd_buffer, bind_point);
1340 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1341 unsigned bo_offset;
1342
1343 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1344 set->mapped_ptr,
1345 &bo_offset))
1346 return;
1347
1348 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1349 set->va += bo_offset;
1350 }
1351
1352 static void
1353 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1354 VkPipelineBindPoint bind_point)
1355 {
1356 struct radv_descriptor_state *descriptors_state =
1357 radv_get_descriptors_state(cmd_buffer, bind_point);
1358 uint32_t size = MAX_SETS * 2 * 4;
1359 uint32_t offset;
1360 void *ptr;
1361
1362 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1363 256, &offset, &ptr))
1364 return;
1365
1366 for (unsigned i = 0; i < MAX_SETS; i++) {
1367 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1368 uint64_t set_va = 0;
1369 struct radv_descriptor_set *set = descriptors_state->sets[i];
1370 if (descriptors_state->valid & (1u << i))
1371 set_va = set->va;
1372 uptr[0] = set_va & 0xffffffff;
1373 uptr[1] = set_va >> 32;
1374 }
1375
1376 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1377 va += offset;
1378
1379 if (cmd_buffer->state.pipeline) {
1380 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1381 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1382 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1383
1384 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1385 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1386 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1387
1388 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1389 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1390 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1391
1392 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1393 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1394 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1395
1396 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1397 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1398 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1399 }
1400
1401 if (cmd_buffer->state.compute_pipeline)
1402 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1403 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1404 }
1405
1406 static void
1407 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1408 VkShaderStageFlags stages)
1409 {
1410 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1411 VK_PIPELINE_BIND_POINT_COMPUTE :
1412 VK_PIPELINE_BIND_POINT_GRAPHICS;
1413 struct radv_descriptor_state *descriptors_state =
1414 radv_get_descriptors_state(cmd_buffer, bind_point);
1415 unsigned i;
1416
1417 if (!descriptors_state->dirty)
1418 return;
1419
1420 if (descriptors_state->push_dirty)
1421 radv_flush_push_descriptors(cmd_buffer, bind_point);
1422
1423 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1424 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1425 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1426 }
1427
1428 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1429 cmd_buffer->cs,
1430 MAX_SETS * MESA_SHADER_STAGES * 4);
1431
1432 for_each_bit(i, descriptors_state->dirty) {
1433 struct radv_descriptor_set *set = descriptors_state->sets[i];
1434 if (!(descriptors_state->valid & (1u << i)))
1435 continue;
1436
1437 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1438 }
1439 descriptors_state->dirty = 0;
1440 descriptors_state->push_dirty = false;
1441
1442 if (unlikely(cmd_buffer->device->trace_bo))
1443 radv_save_descriptors(cmd_buffer, bind_point);
1444
1445 assert(cmd_buffer->cs->cdw <= cdw_max);
1446 }
1447
1448 static void
1449 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1450 VkShaderStageFlags stages)
1451 {
1452 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1453 ? cmd_buffer->state.compute_pipeline
1454 : cmd_buffer->state.pipeline;
1455 struct radv_pipeline_layout *layout = pipeline->layout;
1456 unsigned offset;
1457 void *ptr;
1458 uint64_t va;
1459
1460 stages &= cmd_buffer->push_constant_stages;
1461 if (!stages ||
1462 (!layout->push_constant_size && !layout->dynamic_offset_count))
1463 return;
1464
1465 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1466 16 * layout->dynamic_offset_count,
1467 256, &offset, &ptr))
1468 return;
1469
1470 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1471 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1472 16 * layout->dynamic_offset_count);
1473
1474 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1475 va += offset;
1476
1477 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1478 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1479
1480 radv_foreach_stage(stage, stages) {
1481 if (pipeline->shaders[stage]) {
1482 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1483 AC_UD_PUSH_CONSTANTS, va);
1484 }
1485 }
1486
1487 cmd_buffer->push_constant_stages &= ~stages;
1488 assert(cmd_buffer->cs->cdw <= cdw_max);
1489 }
1490
1491 static void
1492 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1493 bool pipeline_is_dirty)
1494 {
1495 if ((pipeline_is_dirty ||
1496 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1497 cmd_buffer->state.pipeline->vertex_elements.count &&
1498 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1499 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1500 unsigned vb_offset;
1501 void *vb_ptr;
1502 uint32_t i = 0;
1503 uint32_t count = velems->count;
1504 uint64_t va;
1505
1506 /* allocate some descriptor state for vertex buffers */
1507 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1508 &vb_offset, &vb_ptr))
1509 return;
1510
1511 for (i = 0; i < count; i++) {
1512 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1513 uint32_t offset;
1514 int vb = velems->binding[i];
1515 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1516 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1517
1518 va = radv_buffer_get_va(buffer->bo);
1519
1520 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1521 va += offset + buffer->offset;
1522 desc[0] = va;
1523 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1524 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1525 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1526 else
1527 desc[2] = buffer->size - offset;
1528 desc[3] = velems->rsrc_word3[i];
1529 }
1530
1531 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1532 va += vb_offset;
1533
1534 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1535 AC_UD_VS_VERTEX_BUFFERS, va);
1536
1537 cmd_buffer->state.vb_va = va;
1538 cmd_buffer->state.vb_size = count * 16;
1539 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1540 }
1541 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1542 }
1543
1544 static void
1545 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1546 {
1547 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1548 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1549 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1550 }
1551
1552 static void
1553 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1554 bool instanced_draw, bool indirect_draw,
1555 uint32_t draw_vertex_count)
1556 {
1557 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1558 struct radv_cmd_state *state = &cmd_buffer->state;
1559 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1560 uint32_t ia_multi_vgt_param;
1561 int32_t primitive_reset_en;
1562
1563 /* Draw state. */
1564 ia_multi_vgt_param =
1565 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1566 indirect_draw, draw_vertex_count);
1567
1568 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1569 if (info->chip_class >= GFX9) {
1570 radeon_set_uconfig_reg_idx(cs,
1571 R_030960_IA_MULTI_VGT_PARAM,
1572 4, ia_multi_vgt_param);
1573 } else if (info->chip_class >= CIK) {
1574 radeon_set_context_reg_idx(cs,
1575 R_028AA8_IA_MULTI_VGT_PARAM,
1576 1, ia_multi_vgt_param);
1577 } else {
1578 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1579 ia_multi_vgt_param);
1580 }
1581 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1582 }
1583
1584 /* Primitive restart. */
1585 primitive_reset_en =
1586 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1587
1588 if (primitive_reset_en != state->last_primitive_reset_en) {
1589 state->last_primitive_reset_en = primitive_reset_en;
1590 if (info->chip_class >= GFX9) {
1591 radeon_set_uconfig_reg(cs,
1592 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1593 primitive_reset_en);
1594 } else {
1595 radeon_set_context_reg(cs,
1596 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1597 primitive_reset_en);
1598 }
1599 }
1600
1601 if (primitive_reset_en) {
1602 uint32_t primitive_reset_index =
1603 state->index_type ? 0xffffffffu : 0xffffu;
1604
1605 if (primitive_reset_index != state->last_primitive_reset_index) {
1606 radeon_set_context_reg(cs,
1607 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1608 primitive_reset_index);
1609 state->last_primitive_reset_index = primitive_reset_index;
1610 }
1611 }
1612 }
1613
1614 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1615 VkPipelineStageFlags src_stage_mask)
1616 {
1617 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1618 VK_PIPELINE_STAGE_TRANSFER_BIT |
1619 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1620 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1621 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1622 }
1623
1624 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1625 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1626 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1627 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1628 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1629 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1630 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1631 VK_PIPELINE_STAGE_TRANSFER_BIT |
1632 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1633 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1634 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1635 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1636 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1637 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1638 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1639 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1640 }
1641 }
1642
1643 static enum radv_cmd_flush_bits
1644 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1645 VkAccessFlags src_flags)
1646 {
1647 enum radv_cmd_flush_bits flush_bits = 0;
1648 uint32_t b;
1649 for_each_bit(b, src_flags) {
1650 switch ((VkAccessFlagBits)(1 << b)) {
1651 case VK_ACCESS_SHADER_WRITE_BIT:
1652 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1653 break;
1654 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1655 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1656 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1657 break;
1658 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1659 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1660 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1661 break;
1662 case VK_ACCESS_TRANSFER_WRITE_BIT:
1663 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1664 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1665 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1666 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1667 RADV_CMD_FLAG_INV_GLOBAL_L2;
1668 break;
1669 default:
1670 break;
1671 }
1672 }
1673 return flush_bits;
1674 }
1675
1676 static enum radv_cmd_flush_bits
1677 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1678 VkAccessFlags dst_flags,
1679 struct radv_image *image)
1680 {
1681 enum radv_cmd_flush_bits flush_bits = 0;
1682 uint32_t b;
1683 for_each_bit(b, dst_flags) {
1684 switch ((VkAccessFlagBits)(1 << b)) {
1685 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1686 case VK_ACCESS_INDEX_READ_BIT:
1687 break;
1688 case VK_ACCESS_UNIFORM_READ_BIT:
1689 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1690 break;
1691 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1692 case VK_ACCESS_SHADER_READ_BIT:
1693 case VK_ACCESS_TRANSFER_READ_BIT:
1694 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1695 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1696 RADV_CMD_FLAG_INV_GLOBAL_L2;
1697 break;
1698 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1699 /* TODO: change to image && when the image gets passed
1700 * through from the subpass. */
1701 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1702 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1703 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1704 break;
1705 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1706 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1707 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1708 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1709 break;
1710 default:
1711 break;
1712 }
1713 }
1714 return flush_bits;
1715 }
1716
1717 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1718 {
1719 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1720 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1721 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1722 NULL);
1723 }
1724
1725 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1726 VkAttachmentReference att)
1727 {
1728 unsigned idx = att.attachment;
1729 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1730 VkImageSubresourceRange range;
1731 range.aspectMask = 0;
1732 range.baseMipLevel = view->base_mip;
1733 range.levelCount = 1;
1734 range.baseArrayLayer = view->base_layer;
1735 range.layerCount = cmd_buffer->state.framebuffer->layers;
1736
1737 radv_handle_image_transition(cmd_buffer,
1738 view->image,
1739 cmd_buffer->state.attachments[idx].current_layout,
1740 att.layout, 0, 0, &range,
1741 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1742
1743 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1744
1745
1746 }
1747
1748 void
1749 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1750 const struct radv_subpass *subpass, bool transitions)
1751 {
1752 if (transitions) {
1753 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1754
1755 for (unsigned i = 0; i < subpass->color_count; ++i) {
1756 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1757 radv_handle_subpass_image_transition(cmd_buffer,
1758 subpass->color_attachments[i]);
1759 }
1760
1761 for (unsigned i = 0; i < subpass->input_count; ++i) {
1762 radv_handle_subpass_image_transition(cmd_buffer,
1763 subpass->input_attachments[i]);
1764 }
1765
1766 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1767 radv_handle_subpass_image_transition(cmd_buffer,
1768 subpass->depth_stencil_attachment);
1769 }
1770 }
1771
1772 cmd_buffer->state.subpass = subpass;
1773
1774 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1775 }
1776
1777 static VkResult
1778 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1779 struct radv_render_pass *pass,
1780 const VkRenderPassBeginInfo *info)
1781 {
1782 struct radv_cmd_state *state = &cmd_buffer->state;
1783
1784 if (pass->attachment_count == 0) {
1785 state->attachments = NULL;
1786 return VK_SUCCESS;
1787 }
1788
1789 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1790 pass->attachment_count *
1791 sizeof(state->attachments[0]),
1792 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1793 if (state->attachments == NULL) {
1794 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1795 return cmd_buffer->record_result;
1796 }
1797
1798 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1799 struct radv_render_pass_attachment *att = &pass->attachments[i];
1800 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1801 VkImageAspectFlags clear_aspects = 0;
1802
1803 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1804 /* color attachment */
1805 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1806 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1807 }
1808 } else {
1809 /* depthstencil attachment */
1810 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1811 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1812 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1813 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1814 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1815 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1816 }
1817 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1818 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1819 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1820 }
1821 }
1822
1823 state->attachments[i].pending_clear_aspects = clear_aspects;
1824 state->attachments[i].cleared_views = 0;
1825 if (clear_aspects && info) {
1826 assert(info->clearValueCount > i);
1827 state->attachments[i].clear_value = info->pClearValues[i];
1828 }
1829
1830 state->attachments[i].current_layout = att->initial_layout;
1831 }
1832
1833 return VK_SUCCESS;
1834 }
1835
1836 VkResult radv_AllocateCommandBuffers(
1837 VkDevice _device,
1838 const VkCommandBufferAllocateInfo *pAllocateInfo,
1839 VkCommandBuffer *pCommandBuffers)
1840 {
1841 RADV_FROM_HANDLE(radv_device, device, _device);
1842 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1843
1844 VkResult result = VK_SUCCESS;
1845 uint32_t i;
1846
1847 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1848
1849 if (!list_empty(&pool->free_cmd_buffers)) {
1850 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1851
1852 list_del(&cmd_buffer->pool_link);
1853 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1854
1855 result = radv_reset_cmd_buffer(cmd_buffer);
1856 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1857 cmd_buffer->level = pAllocateInfo->level;
1858
1859 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1860 } else {
1861 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1862 &pCommandBuffers[i]);
1863 }
1864 if (result != VK_SUCCESS)
1865 break;
1866 }
1867
1868 if (result != VK_SUCCESS) {
1869 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1870 i, pCommandBuffers);
1871
1872 /* From the Vulkan 1.0.66 spec:
1873 *
1874 * "vkAllocateCommandBuffers can be used to create multiple
1875 * command buffers. If the creation of any of those command
1876 * buffers fails, the implementation must destroy all
1877 * successfully created command buffer objects from this
1878 * command, set all entries of the pCommandBuffers array to
1879 * NULL and return the error."
1880 */
1881 memset(pCommandBuffers, 0,
1882 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1883 }
1884
1885 return result;
1886 }
1887
1888 void radv_FreeCommandBuffers(
1889 VkDevice device,
1890 VkCommandPool commandPool,
1891 uint32_t commandBufferCount,
1892 const VkCommandBuffer *pCommandBuffers)
1893 {
1894 for (uint32_t i = 0; i < commandBufferCount; i++) {
1895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1896
1897 if (cmd_buffer) {
1898 if (cmd_buffer->pool) {
1899 list_del(&cmd_buffer->pool_link);
1900 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1901 } else
1902 radv_cmd_buffer_destroy(cmd_buffer);
1903
1904 }
1905 }
1906 }
1907
1908 VkResult radv_ResetCommandBuffer(
1909 VkCommandBuffer commandBuffer,
1910 VkCommandBufferResetFlags flags)
1911 {
1912 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1913 return radv_reset_cmd_buffer(cmd_buffer);
1914 }
1915
1916 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1917 {
1918 struct radv_device *device = cmd_buffer->device;
1919 if (device->gfx_init) {
1920 uint64_t va = radv_buffer_get_va(device->gfx_init);
1921 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1922 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1923 radeon_emit(cmd_buffer->cs, va);
1924 radeon_emit(cmd_buffer->cs, va >> 32);
1925 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1926 } else
1927 si_init_config(cmd_buffer);
1928 }
1929
1930 VkResult radv_BeginCommandBuffer(
1931 VkCommandBuffer commandBuffer,
1932 const VkCommandBufferBeginInfo *pBeginInfo)
1933 {
1934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1935 VkResult result = VK_SUCCESS;
1936
1937 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1938 /* If the command buffer has already been resetted with
1939 * vkResetCommandBuffer, no need to do it again.
1940 */
1941 result = radv_reset_cmd_buffer(cmd_buffer);
1942 if (result != VK_SUCCESS)
1943 return result;
1944 }
1945
1946 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1947 cmd_buffer->state.last_primitive_reset_en = -1;
1948 cmd_buffer->state.last_index_type = -1;
1949 cmd_buffer->state.last_num_instances = -1;
1950 cmd_buffer->state.last_vertex_offset = -1;
1951 cmd_buffer->state.last_first_instance = -1;
1952 cmd_buffer->usage_flags = pBeginInfo->flags;
1953
1954 /* setup initial configuration into command buffer */
1955 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1956 switch (cmd_buffer->queue_family_index) {
1957 case RADV_QUEUE_GENERAL:
1958 emit_gfx_buffer_state(cmd_buffer);
1959 break;
1960 case RADV_QUEUE_COMPUTE:
1961 si_init_compute(cmd_buffer);
1962 break;
1963 case RADV_QUEUE_TRANSFER:
1964 default:
1965 break;
1966 }
1967 }
1968
1969 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1970 assert(pBeginInfo->pInheritanceInfo);
1971 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1972 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1973
1974 struct radv_subpass *subpass =
1975 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1976
1977 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1978 if (result != VK_SUCCESS)
1979 return result;
1980
1981 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1982 }
1983
1984 if (unlikely(cmd_buffer->device->trace_bo))
1985 radv_cmd_buffer_trace_emit(cmd_buffer);
1986
1987 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1988
1989 return result;
1990 }
1991
1992 void radv_CmdBindVertexBuffers(
1993 VkCommandBuffer commandBuffer,
1994 uint32_t firstBinding,
1995 uint32_t bindingCount,
1996 const VkBuffer* pBuffers,
1997 const VkDeviceSize* pOffsets)
1998 {
1999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2000 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2001 bool changed = false;
2002
2003 /* We have to defer setting up vertex buffer since we need the buffer
2004 * stride from the pipeline. */
2005
2006 assert(firstBinding + bindingCount <= MAX_VBS);
2007 for (uint32_t i = 0; i < bindingCount; i++) {
2008 uint32_t idx = firstBinding + i;
2009
2010 if (!changed &&
2011 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2012 vb[idx].offset != pOffsets[i])) {
2013 changed = true;
2014 }
2015
2016 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2017 vb[idx].offset = pOffsets[i];
2018
2019 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2020 vb[idx].buffer->bo, 8);
2021 }
2022
2023 if (!changed) {
2024 /* No state changes. */
2025 return;
2026 }
2027
2028 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2029 }
2030
2031 void radv_CmdBindIndexBuffer(
2032 VkCommandBuffer commandBuffer,
2033 VkBuffer buffer,
2034 VkDeviceSize offset,
2035 VkIndexType indexType)
2036 {
2037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2038 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2039
2040 if (cmd_buffer->state.index_buffer == index_buffer &&
2041 cmd_buffer->state.index_offset == offset &&
2042 cmd_buffer->state.index_type == indexType) {
2043 /* No state changes. */
2044 return;
2045 }
2046
2047 cmd_buffer->state.index_buffer = index_buffer;
2048 cmd_buffer->state.index_offset = offset;
2049 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2050 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2051 cmd_buffer->state.index_va += index_buffer->offset + offset;
2052
2053 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2054 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2055 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2056 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2057 }
2058
2059
2060 static void
2061 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2062 VkPipelineBindPoint bind_point,
2063 struct radv_descriptor_set *set, unsigned idx)
2064 {
2065 struct radeon_winsys *ws = cmd_buffer->device->ws;
2066
2067 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2068 if (!set)
2069 return;
2070
2071 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2072
2073 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2074 if (set->descriptors[j])
2075 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2076
2077 if(set->bo)
2078 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2079 }
2080
2081 void radv_CmdBindDescriptorSets(
2082 VkCommandBuffer commandBuffer,
2083 VkPipelineBindPoint pipelineBindPoint,
2084 VkPipelineLayout _layout,
2085 uint32_t firstSet,
2086 uint32_t descriptorSetCount,
2087 const VkDescriptorSet* pDescriptorSets,
2088 uint32_t dynamicOffsetCount,
2089 const uint32_t* pDynamicOffsets)
2090 {
2091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2092 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2093 unsigned dyn_idx = 0;
2094
2095 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2096 unsigned idx = i + firstSet;
2097 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2098 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2099
2100 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2101 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2102 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2103 assert(dyn_idx < dynamicOffsetCount);
2104
2105 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2106 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2107 dst[0] = va;
2108 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2109 dst[2] = range->size;
2110 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2111 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2112 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2113 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2114 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2115 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2116 cmd_buffer->push_constant_stages |=
2117 set->layout->dynamic_shader_stages;
2118 }
2119 }
2120 }
2121
2122 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2123 struct radv_descriptor_set *set,
2124 struct radv_descriptor_set_layout *layout,
2125 VkPipelineBindPoint bind_point)
2126 {
2127 struct radv_descriptor_state *descriptors_state =
2128 radv_get_descriptors_state(cmd_buffer, bind_point);
2129 set->size = layout->size;
2130 set->layout = layout;
2131
2132 if (descriptors_state->push_set.capacity < set->size) {
2133 size_t new_size = MAX2(set->size, 1024);
2134 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2135 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2136
2137 free(set->mapped_ptr);
2138 set->mapped_ptr = malloc(new_size);
2139
2140 if (!set->mapped_ptr) {
2141 descriptors_state->push_set.capacity = 0;
2142 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2143 return false;
2144 }
2145
2146 descriptors_state->push_set.capacity = new_size;
2147 }
2148
2149 return true;
2150 }
2151
2152 void radv_meta_push_descriptor_set(
2153 struct radv_cmd_buffer* cmd_buffer,
2154 VkPipelineBindPoint pipelineBindPoint,
2155 VkPipelineLayout _layout,
2156 uint32_t set,
2157 uint32_t descriptorWriteCount,
2158 const VkWriteDescriptorSet* pDescriptorWrites)
2159 {
2160 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2161 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2162 unsigned bo_offset;
2163
2164 assert(set == 0);
2165 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2166
2167 push_set->size = layout->set[set].layout->size;
2168 push_set->layout = layout->set[set].layout;
2169
2170 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2171 &bo_offset,
2172 (void**) &push_set->mapped_ptr))
2173 return;
2174
2175 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2176 push_set->va += bo_offset;
2177
2178 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2179 radv_descriptor_set_to_handle(push_set),
2180 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2181
2182 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2183 }
2184
2185 void radv_CmdPushDescriptorSetKHR(
2186 VkCommandBuffer commandBuffer,
2187 VkPipelineBindPoint pipelineBindPoint,
2188 VkPipelineLayout _layout,
2189 uint32_t set,
2190 uint32_t descriptorWriteCount,
2191 const VkWriteDescriptorSet* pDescriptorWrites)
2192 {
2193 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2194 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2195 struct radv_descriptor_state *descriptors_state =
2196 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2197 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2198
2199 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2200
2201 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2202 layout->set[set].layout,
2203 pipelineBindPoint))
2204 return;
2205
2206 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2207 radv_descriptor_set_to_handle(push_set),
2208 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2209
2210 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2211 descriptors_state->push_dirty = true;
2212 }
2213
2214 void radv_CmdPushDescriptorSetWithTemplateKHR(
2215 VkCommandBuffer commandBuffer,
2216 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2217 VkPipelineLayout _layout,
2218 uint32_t set,
2219 const void* pData)
2220 {
2221 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2222 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2223 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2224 struct radv_descriptor_state *descriptors_state =
2225 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2226 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2227
2228 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2229
2230 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2231 layout->set[set].layout,
2232 templ->bind_point))
2233 return;
2234
2235 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2236 descriptorUpdateTemplate, pData);
2237
2238 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2239 descriptors_state->push_dirty = true;
2240 }
2241
2242 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2243 VkPipelineLayout layout,
2244 VkShaderStageFlags stageFlags,
2245 uint32_t offset,
2246 uint32_t size,
2247 const void* pValues)
2248 {
2249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2250 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2251 cmd_buffer->push_constant_stages |= stageFlags;
2252 }
2253
2254 VkResult radv_EndCommandBuffer(
2255 VkCommandBuffer commandBuffer)
2256 {
2257 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2258
2259 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2260 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2261 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2262 si_emit_cache_flush(cmd_buffer);
2263 }
2264
2265 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2266
2267 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2268 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2269
2270 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2271
2272 return cmd_buffer->record_result;
2273 }
2274
2275 static void
2276 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2277 {
2278 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2279
2280 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2281 return;
2282
2283 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2284
2285 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2286 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2287
2288 cmd_buffer->compute_scratch_size_needed =
2289 MAX2(cmd_buffer->compute_scratch_size_needed,
2290 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2291
2292 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2293 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2294
2295 if (unlikely(cmd_buffer->device->trace_bo))
2296 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2297 }
2298
2299 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2300 VkPipelineBindPoint bind_point)
2301 {
2302 struct radv_descriptor_state *descriptors_state =
2303 radv_get_descriptors_state(cmd_buffer, bind_point);
2304
2305 descriptors_state->dirty |= descriptors_state->valid;
2306 }
2307
2308 void radv_CmdBindPipeline(
2309 VkCommandBuffer commandBuffer,
2310 VkPipelineBindPoint pipelineBindPoint,
2311 VkPipeline _pipeline)
2312 {
2313 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2314 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2315
2316 switch (pipelineBindPoint) {
2317 case VK_PIPELINE_BIND_POINT_COMPUTE:
2318 if (cmd_buffer->state.compute_pipeline == pipeline)
2319 return;
2320 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2321
2322 cmd_buffer->state.compute_pipeline = pipeline;
2323 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2324 break;
2325 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2326 if (cmd_buffer->state.pipeline == pipeline)
2327 return;
2328 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2329
2330 cmd_buffer->state.pipeline = pipeline;
2331 if (!pipeline)
2332 break;
2333
2334 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2335 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2336
2337 /* the new vertex shader might not have the same user regs */
2338 cmd_buffer->state.last_first_instance = -1;
2339 cmd_buffer->state.last_vertex_offset = -1;
2340
2341 /* Prefetch all pipeline shaders at first draw time. */
2342 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2343
2344 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2345
2346 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2347 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2348 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2349 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2350
2351 if (radv_pipeline_has_tess(pipeline))
2352 cmd_buffer->tess_rings_needed = true;
2353
2354 if (radv_pipeline_has_gs(pipeline)) {
2355 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2356 AC_UD_SCRATCH_RING_OFFSETS);
2357 if (cmd_buffer->ring_offsets_idx == -1)
2358 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2359 else if (loc->sgpr_idx != -1)
2360 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2361 }
2362 break;
2363 default:
2364 assert(!"invalid bind point");
2365 break;
2366 }
2367 }
2368
2369 void radv_CmdSetViewport(
2370 VkCommandBuffer commandBuffer,
2371 uint32_t firstViewport,
2372 uint32_t viewportCount,
2373 const VkViewport* pViewports)
2374 {
2375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2376 struct radv_cmd_state *state = &cmd_buffer->state;
2377 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2378
2379 assert(firstViewport < MAX_VIEWPORTS);
2380 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2381
2382 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2383 /* Try to skip unnecessary PS partial flushes when the viewports
2384 * don't change.
2385 */
2386 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2387 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2388 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2389 pViewports, viewportCount * sizeof(*pViewports))) {
2390 return;
2391 }
2392 }
2393
2394 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2395 viewportCount * sizeof(*pViewports));
2396
2397 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2398 }
2399
2400 void radv_CmdSetScissor(
2401 VkCommandBuffer commandBuffer,
2402 uint32_t firstScissor,
2403 uint32_t scissorCount,
2404 const VkRect2D* pScissors)
2405 {
2406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2407 struct radv_cmd_state *state = &cmd_buffer->state;
2408 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2409
2410 assert(firstScissor < MAX_SCISSORS);
2411 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2412
2413 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2414 /* Try to skip unnecessary PS partial flushes when the scissors
2415 * don't change.
2416 */
2417 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2418 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2419 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2420 pScissors, scissorCount * sizeof(*pScissors))) {
2421 return;
2422 }
2423 }
2424
2425 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2426 scissorCount * sizeof(*pScissors));
2427
2428 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2429 }
2430
2431 void radv_CmdSetLineWidth(
2432 VkCommandBuffer commandBuffer,
2433 float lineWidth)
2434 {
2435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2436 cmd_buffer->state.dynamic.line_width = lineWidth;
2437 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2438 }
2439
2440 void radv_CmdSetDepthBias(
2441 VkCommandBuffer commandBuffer,
2442 float depthBiasConstantFactor,
2443 float depthBiasClamp,
2444 float depthBiasSlopeFactor)
2445 {
2446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2447
2448 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2449 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2450 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2451
2452 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2453 }
2454
2455 void radv_CmdSetBlendConstants(
2456 VkCommandBuffer commandBuffer,
2457 const float blendConstants[4])
2458 {
2459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2460
2461 memcpy(cmd_buffer->state.dynamic.blend_constants,
2462 blendConstants, sizeof(float) * 4);
2463
2464 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2465 }
2466
2467 void radv_CmdSetDepthBounds(
2468 VkCommandBuffer commandBuffer,
2469 float minDepthBounds,
2470 float maxDepthBounds)
2471 {
2472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2473
2474 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2475 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2476
2477 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2478 }
2479
2480 void radv_CmdSetStencilCompareMask(
2481 VkCommandBuffer commandBuffer,
2482 VkStencilFaceFlags faceMask,
2483 uint32_t compareMask)
2484 {
2485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2486
2487 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2488 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2489 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2490 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2491
2492 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2493 }
2494
2495 void radv_CmdSetStencilWriteMask(
2496 VkCommandBuffer commandBuffer,
2497 VkStencilFaceFlags faceMask,
2498 uint32_t writeMask)
2499 {
2500 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2501
2502 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2503 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2504 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2505 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2506
2507 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2508 }
2509
2510 void radv_CmdSetStencilReference(
2511 VkCommandBuffer commandBuffer,
2512 VkStencilFaceFlags faceMask,
2513 uint32_t reference)
2514 {
2515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2516
2517 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2518 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2519 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2520 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2521
2522 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2523 }
2524
2525 void radv_CmdSetDiscardRectangleEXT(
2526 VkCommandBuffer commandBuffer,
2527 uint32_t firstDiscardRectangle,
2528 uint32_t discardRectangleCount,
2529 const VkRect2D* pDiscardRectangles)
2530 {
2531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2532 struct radv_cmd_state *state = &cmd_buffer->state;
2533 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2534
2535 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2536 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2537
2538 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2539 pDiscardRectangles, discardRectangleCount);
2540
2541 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2542 }
2543
2544 void radv_CmdExecuteCommands(
2545 VkCommandBuffer commandBuffer,
2546 uint32_t commandBufferCount,
2547 const VkCommandBuffer* pCmdBuffers)
2548 {
2549 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2550
2551 assert(commandBufferCount > 0);
2552
2553 /* Emit pending flushes on primary prior to executing secondary */
2554 si_emit_cache_flush(primary);
2555
2556 for (uint32_t i = 0; i < commandBufferCount; i++) {
2557 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2558
2559 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2560 secondary->scratch_size_needed);
2561 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2562 secondary->compute_scratch_size_needed);
2563
2564 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2565 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2566 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2567 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2568 if (secondary->tess_rings_needed)
2569 primary->tess_rings_needed = true;
2570 if (secondary->sample_positions_needed)
2571 primary->sample_positions_needed = true;
2572
2573 if (secondary->ring_offsets_idx != -1) {
2574 if (primary->ring_offsets_idx == -1)
2575 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2576 else
2577 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2578 }
2579 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2580
2581
2582 /* When the secondary command buffer is compute only we don't
2583 * need to re-emit the current graphics pipeline.
2584 */
2585 if (secondary->state.emitted_pipeline) {
2586 primary->state.emitted_pipeline =
2587 secondary->state.emitted_pipeline;
2588 }
2589
2590 /* When the secondary command buffer is graphics only we don't
2591 * need to re-emit the current compute pipeline.
2592 */
2593 if (secondary->state.emitted_compute_pipeline) {
2594 primary->state.emitted_compute_pipeline =
2595 secondary->state.emitted_compute_pipeline;
2596 }
2597
2598 /* Only re-emit the draw packets when needed. */
2599 if (secondary->state.last_primitive_reset_en != -1) {
2600 primary->state.last_primitive_reset_en =
2601 secondary->state.last_primitive_reset_en;
2602 }
2603
2604 if (secondary->state.last_primitive_reset_index) {
2605 primary->state.last_primitive_reset_index =
2606 secondary->state.last_primitive_reset_index;
2607 }
2608
2609 if (secondary->state.last_ia_multi_vgt_param) {
2610 primary->state.last_ia_multi_vgt_param =
2611 secondary->state.last_ia_multi_vgt_param;
2612 }
2613
2614 primary->state.last_first_instance = secondary->state.last_first_instance;
2615 primary->state.last_num_instances = secondary->state.last_num_instances;
2616 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2617
2618 if (secondary->state.last_index_type != -1) {
2619 primary->state.last_index_type =
2620 secondary->state.last_index_type;
2621 }
2622 }
2623
2624 /* After executing commands from secondary buffers we have to dirty
2625 * some states.
2626 */
2627 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2628 RADV_CMD_DIRTY_INDEX_BUFFER |
2629 RADV_CMD_DIRTY_DYNAMIC_ALL;
2630 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2631 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2632 }
2633
2634 VkResult radv_CreateCommandPool(
2635 VkDevice _device,
2636 const VkCommandPoolCreateInfo* pCreateInfo,
2637 const VkAllocationCallbacks* pAllocator,
2638 VkCommandPool* pCmdPool)
2639 {
2640 RADV_FROM_HANDLE(radv_device, device, _device);
2641 struct radv_cmd_pool *pool;
2642
2643 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2644 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2645 if (pool == NULL)
2646 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2647
2648 if (pAllocator)
2649 pool->alloc = *pAllocator;
2650 else
2651 pool->alloc = device->alloc;
2652
2653 list_inithead(&pool->cmd_buffers);
2654 list_inithead(&pool->free_cmd_buffers);
2655
2656 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2657
2658 *pCmdPool = radv_cmd_pool_to_handle(pool);
2659
2660 return VK_SUCCESS;
2661
2662 }
2663
2664 void radv_DestroyCommandPool(
2665 VkDevice _device,
2666 VkCommandPool commandPool,
2667 const VkAllocationCallbacks* pAllocator)
2668 {
2669 RADV_FROM_HANDLE(radv_device, device, _device);
2670 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2671
2672 if (!pool)
2673 return;
2674
2675 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2676 &pool->cmd_buffers, pool_link) {
2677 radv_cmd_buffer_destroy(cmd_buffer);
2678 }
2679
2680 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2681 &pool->free_cmd_buffers, pool_link) {
2682 radv_cmd_buffer_destroy(cmd_buffer);
2683 }
2684
2685 vk_free2(&device->alloc, pAllocator, pool);
2686 }
2687
2688 VkResult radv_ResetCommandPool(
2689 VkDevice device,
2690 VkCommandPool commandPool,
2691 VkCommandPoolResetFlags flags)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2694 VkResult result;
2695
2696 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2697 &pool->cmd_buffers, pool_link) {
2698 result = radv_reset_cmd_buffer(cmd_buffer);
2699 if (result != VK_SUCCESS)
2700 return result;
2701 }
2702
2703 return VK_SUCCESS;
2704 }
2705
2706 void radv_TrimCommandPool(
2707 VkDevice device,
2708 VkCommandPool commandPool,
2709 VkCommandPoolTrimFlagsKHR flags)
2710 {
2711 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2712
2713 if (!pool)
2714 return;
2715
2716 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2717 &pool->free_cmd_buffers, pool_link) {
2718 radv_cmd_buffer_destroy(cmd_buffer);
2719 }
2720 }
2721
2722 void radv_CmdBeginRenderPass(
2723 VkCommandBuffer commandBuffer,
2724 const VkRenderPassBeginInfo* pRenderPassBegin,
2725 VkSubpassContents contents)
2726 {
2727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2728 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2729 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2730
2731 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2732 cmd_buffer->cs, 2048);
2733 MAYBE_UNUSED VkResult result;
2734
2735 cmd_buffer->state.framebuffer = framebuffer;
2736 cmd_buffer->state.pass = pass;
2737 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2738
2739 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2740 if (result != VK_SUCCESS)
2741 return;
2742
2743 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2744 assert(cmd_buffer->cs->cdw <= cdw_max);
2745
2746 radv_cmd_buffer_clear_subpass(cmd_buffer);
2747 }
2748
2749 void radv_CmdNextSubpass(
2750 VkCommandBuffer commandBuffer,
2751 VkSubpassContents contents)
2752 {
2753 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2754
2755 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2756
2757 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2758 2048);
2759
2760 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2761 radv_cmd_buffer_clear_subpass(cmd_buffer);
2762 }
2763
2764 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2765 {
2766 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2767 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2768 if (!pipeline->shaders[stage])
2769 continue;
2770 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2771 if (loc->sgpr_idx == -1)
2772 continue;
2773 uint32_t base_reg = pipeline->user_data_0[stage];
2774 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2775
2776 }
2777 if (pipeline->gs_copy_shader) {
2778 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2779 if (loc->sgpr_idx != -1) {
2780 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2781 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2782 }
2783 }
2784 }
2785
2786 static void
2787 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2788 uint32_t vertex_count)
2789 {
2790 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2791 radeon_emit(cmd_buffer->cs, vertex_count);
2792 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2793 S_0287F0_USE_OPAQUE(0));
2794 }
2795
2796 static void
2797 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2798 uint64_t index_va,
2799 uint32_t index_count)
2800 {
2801 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2802 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2803 radeon_emit(cmd_buffer->cs, index_va);
2804 radeon_emit(cmd_buffer->cs, index_va >> 32);
2805 radeon_emit(cmd_buffer->cs, index_count);
2806 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2807 }
2808
2809 static void
2810 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2811 bool indexed,
2812 uint32_t draw_count,
2813 uint64_t count_va,
2814 uint32_t stride)
2815 {
2816 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2817 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2818 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2819 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2820 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2821 assert(base_reg);
2822
2823 /* just reset draw state for vertex data */
2824 cmd_buffer->state.last_first_instance = -1;
2825 cmd_buffer->state.last_num_instances = -1;
2826 cmd_buffer->state.last_vertex_offset = -1;
2827
2828 if (draw_count == 1 && !count_va && !draw_id_enable) {
2829 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2830 PKT3_DRAW_INDIRECT, 3, false));
2831 radeon_emit(cs, 0);
2832 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2833 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2834 radeon_emit(cs, di_src_sel);
2835 } else {
2836 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2837 PKT3_DRAW_INDIRECT_MULTI,
2838 8, false));
2839 radeon_emit(cs, 0);
2840 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2841 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2842 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2843 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2844 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2845 radeon_emit(cs, draw_count); /* count */
2846 radeon_emit(cs, count_va); /* count_addr */
2847 radeon_emit(cs, count_va >> 32);
2848 radeon_emit(cs, stride); /* stride */
2849 radeon_emit(cs, di_src_sel);
2850 }
2851 }
2852
2853 struct radv_draw_info {
2854 /**
2855 * Number of vertices.
2856 */
2857 uint32_t count;
2858
2859 /**
2860 * Index of the first vertex.
2861 */
2862 int32_t vertex_offset;
2863
2864 /**
2865 * First instance id.
2866 */
2867 uint32_t first_instance;
2868
2869 /**
2870 * Number of instances.
2871 */
2872 uint32_t instance_count;
2873
2874 /**
2875 * First index (indexed draws only).
2876 */
2877 uint32_t first_index;
2878
2879 /**
2880 * Whether it's an indexed draw.
2881 */
2882 bool indexed;
2883
2884 /**
2885 * Indirect draw parameters resource.
2886 */
2887 struct radv_buffer *indirect;
2888 uint64_t indirect_offset;
2889 uint32_t stride;
2890
2891 /**
2892 * Draw count parameters resource.
2893 */
2894 struct radv_buffer *count_buffer;
2895 uint64_t count_buffer_offset;
2896 };
2897
2898 static void
2899 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2900 const struct radv_draw_info *info)
2901 {
2902 struct radv_cmd_state *state = &cmd_buffer->state;
2903 struct radeon_winsys *ws = cmd_buffer->device->ws;
2904 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2905
2906 if (info->indirect) {
2907 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2908 uint64_t count_va = 0;
2909
2910 va += info->indirect->offset + info->indirect_offset;
2911
2912 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2913
2914 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2915 radeon_emit(cs, 1);
2916 radeon_emit(cs, va);
2917 radeon_emit(cs, va >> 32);
2918
2919 if (info->count_buffer) {
2920 count_va = radv_buffer_get_va(info->count_buffer->bo);
2921 count_va += info->count_buffer->offset +
2922 info->count_buffer_offset;
2923
2924 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2925 }
2926
2927 if (!state->subpass->view_mask) {
2928 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2929 info->indexed,
2930 info->count,
2931 count_va,
2932 info->stride);
2933 } else {
2934 unsigned i;
2935 for_each_bit(i, state->subpass->view_mask) {
2936 radv_emit_view_index(cmd_buffer, i);
2937
2938 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2939 info->indexed,
2940 info->count,
2941 count_va,
2942 info->stride);
2943 }
2944 }
2945 } else {
2946 assert(state->pipeline->graphics.vtx_base_sgpr);
2947
2948 if (info->vertex_offset != state->last_vertex_offset ||
2949 info->first_instance != state->last_first_instance) {
2950 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2951 state->pipeline->graphics.vtx_emit_num);
2952
2953 radeon_emit(cs, info->vertex_offset);
2954 radeon_emit(cs, info->first_instance);
2955 if (state->pipeline->graphics.vtx_emit_num == 3)
2956 radeon_emit(cs, 0);
2957 state->last_first_instance = info->first_instance;
2958 state->last_vertex_offset = info->vertex_offset;
2959 }
2960
2961 if (state->last_num_instances != info->instance_count) {
2962 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
2963 radeon_emit(cs, info->instance_count);
2964 state->last_num_instances = info->instance_count;
2965 }
2966
2967 if (info->indexed) {
2968 int index_size = state->index_type ? 4 : 2;
2969 uint64_t index_va;
2970
2971 index_va = state->index_va;
2972 index_va += info->first_index * index_size;
2973
2974 if (!state->subpass->view_mask) {
2975 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2976 index_va,
2977 info->count);
2978 } else {
2979 unsigned i;
2980 for_each_bit(i, state->subpass->view_mask) {
2981 radv_emit_view_index(cmd_buffer, i);
2982
2983 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2984 index_va,
2985 info->count);
2986 }
2987 }
2988 } else {
2989 if (!state->subpass->view_mask) {
2990 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2991 } else {
2992 unsigned i;
2993 for_each_bit(i, state->subpass->view_mask) {
2994 radv_emit_view_index(cmd_buffer, i);
2995
2996 radv_cs_emit_draw_packet(cmd_buffer,
2997 info->count);
2998 }
2999 }
3000 }
3001 }
3002 }
3003
3004 static void
3005 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3006 const struct radv_draw_info *info)
3007 {
3008 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3009 radv_emit_graphics_pipeline(cmd_buffer);
3010
3011 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3012 radv_emit_framebuffer_state(cmd_buffer);
3013
3014 if (info->indexed) {
3015 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3016 radv_emit_index_buffer(cmd_buffer);
3017 } else {
3018 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3019 * so the state must be re-emitted before the next indexed
3020 * draw.
3021 */
3022 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3023 cmd_buffer->state.last_index_type = -1;
3024 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3025 }
3026 }
3027
3028 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3029
3030 radv_emit_draw_registers(cmd_buffer, info->indexed,
3031 info->instance_count > 1, info->indirect,
3032 info->indirect ? 0 : info->count);
3033 }
3034
3035 static void
3036 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3037 const struct radv_draw_info *info)
3038 {
3039 bool has_prefetch =
3040 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3041 bool pipeline_is_dirty =
3042 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3043 cmd_buffer->state.pipeline &&
3044 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3045
3046 MAYBE_UNUSED unsigned cdw_max =
3047 radeon_check_space(cmd_buffer->device->ws,
3048 cmd_buffer->cs, 4096);
3049
3050 /* Use optimal packet order based on whether we need to sync the
3051 * pipeline.
3052 */
3053 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3054 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3055 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3056 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3057 /* If we have to wait for idle, set all states first, so that
3058 * all SET packets are processed in parallel with previous draw
3059 * calls. Then upload descriptors, set shader pointers, and
3060 * draw, and prefetch at the end. This ensures that the time
3061 * the CUs are idle is very short. (there are only SET_SH
3062 * packets between the wait and the draw)
3063 */
3064 radv_emit_all_graphics_states(cmd_buffer, info);
3065 si_emit_cache_flush(cmd_buffer);
3066 /* <-- CUs are idle here --> */
3067
3068 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3069
3070 radv_emit_draw_packets(cmd_buffer, info);
3071 /* <-- CUs are busy here --> */
3072
3073 /* Start prefetches after the draw has been started. Both will
3074 * run in parallel, but starting the draw first is more
3075 * important.
3076 */
3077 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3078 radv_emit_prefetch_L2(cmd_buffer,
3079 cmd_buffer->state.pipeline, false);
3080 }
3081 } else {
3082 /* If we don't wait for idle, start prefetches first, then set
3083 * states, and draw at the end.
3084 */
3085 si_emit_cache_flush(cmd_buffer);
3086
3087 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3088 /* Only prefetch the vertex shader and VBO descriptors
3089 * in order to start the draw as soon as possible.
3090 */
3091 radv_emit_prefetch_L2(cmd_buffer,
3092 cmd_buffer->state.pipeline, true);
3093 }
3094
3095 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3096
3097 radv_emit_all_graphics_states(cmd_buffer, info);
3098 radv_emit_draw_packets(cmd_buffer, info);
3099
3100 /* Prefetch the remaining shaders after the draw has been
3101 * started.
3102 */
3103 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3104 radv_emit_prefetch_L2(cmd_buffer,
3105 cmd_buffer->state.pipeline, false);
3106 }
3107 }
3108
3109 assert(cmd_buffer->cs->cdw <= cdw_max);
3110 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3111 }
3112
3113 void radv_CmdDraw(
3114 VkCommandBuffer commandBuffer,
3115 uint32_t vertexCount,
3116 uint32_t instanceCount,
3117 uint32_t firstVertex,
3118 uint32_t firstInstance)
3119 {
3120 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3121 struct radv_draw_info info = {};
3122
3123 info.count = vertexCount;
3124 info.instance_count = instanceCount;
3125 info.first_instance = firstInstance;
3126 info.vertex_offset = firstVertex;
3127
3128 radv_draw(cmd_buffer, &info);
3129 }
3130
3131 void radv_CmdDrawIndexed(
3132 VkCommandBuffer commandBuffer,
3133 uint32_t indexCount,
3134 uint32_t instanceCount,
3135 uint32_t firstIndex,
3136 int32_t vertexOffset,
3137 uint32_t firstInstance)
3138 {
3139 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3140 struct radv_draw_info info = {};
3141
3142 info.indexed = true;
3143 info.count = indexCount;
3144 info.instance_count = instanceCount;
3145 info.first_index = firstIndex;
3146 info.vertex_offset = vertexOffset;
3147 info.first_instance = firstInstance;
3148
3149 radv_draw(cmd_buffer, &info);
3150 }
3151
3152 void radv_CmdDrawIndirect(
3153 VkCommandBuffer commandBuffer,
3154 VkBuffer _buffer,
3155 VkDeviceSize offset,
3156 uint32_t drawCount,
3157 uint32_t stride)
3158 {
3159 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3160 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3161 struct radv_draw_info info = {};
3162
3163 info.count = drawCount;
3164 info.indirect = buffer;
3165 info.indirect_offset = offset;
3166 info.stride = stride;
3167
3168 radv_draw(cmd_buffer, &info);
3169 }
3170
3171 void radv_CmdDrawIndexedIndirect(
3172 VkCommandBuffer commandBuffer,
3173 VkBuffer _buffer,
3174 VkDeviceSize offset,
3175 uint32_t drawCount,
3176 uint32_t stride)
3177 {
3178 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3179 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3180 struct radv_draw_info info = {};
3181
3182 info.indexed = true;
3183 info.count = drawCount;
3184 info.indirect = buffer;
3185 info.indirect_offset = offset;
3186 info.stride = stride;
3187
3188 radv_draw(cmd_buffer, &info);
3189 }
3190
3191 void radv_CmdDrawIndirectCountAMD(
3192 VkCommandBuffer commandBuffer,
3193 VkBuffer _buffer,
3194 VkDeviceSize offset,
3195 VkBuffer _countBuffer,
3196 VkDeviceSize countBufferOffset,
3197 uint32_t maxDrawCount,
3198 uint32_t stride)
3199 {
3200 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3201 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3202 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3203 struct radv_draw_info info = {};
3204
3205 info.count = maxDrawCount;
3206 info.indirect = buffer;
3207 info.indirect_offset = offset;
3208 info.count_buffer = count_buffer;
3209 info.count_buffer_offset = countBufferOffset;
3210 info.stride = stride;
3211
3212 radv_draw(cmd_buffer, &info);
3213 }
3214
3215 void radv_CmdDrawIndexedIndirectCountAMD(
3216 VkCommandBuffer commandBuffer,
3217 VkBuffer _buffer,
3218 VkDeviceSize offset,
3219 VkBuffer _countBuffer,
3220 VkDeviceSize countBufferOffset,
3221 uint32_t maxDrawCount,
3222 uint32_t stride)
3223 {
3224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3225 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3226 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3227 struct radv_draw_info info = {};
3228
3229 info.indexed = true;
3230 info.count = maxDrawCount;
3231 info.indirect = buffer;
3232 info.indirect_offset = offset;
3233 info.count_buffer = count_buffer;
3234 info.count_buffer_offset = countBufferOffset;
3235 info.stride = stride;
3236
3237 radv_draw(cmd_buffer, &info);
3238 }
3239
3240 struct radv_dispatch_info {
3241 /**
3242 * Determine the layout of the grid (in block units) to be used.
3243 */
3244 uint32_t blocks[3];
3245
3246 /**
3247 * A starting offset for the grid. If unaligned is set, the offset
3248 * must still be aligned.
3249 */
3250 uint32_t offsets[3];
3251 /**
3252 * Whether it's an unaligned compute dispatch.
3253 */
3254 bool unaligned;
3255
3256 /**
3257 * Indirect compute parameters resource.
3258 */
3259 struct radv_buffer *indirect;
3260 uint64_t indirect_offset;
3261 };
3262
3263 static void
3264 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3265 const struct radv_dispatch_info *info)
3266 {
3267 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3268 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3269 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3270 struct radeon_winsys *ws = cmd_buffer->device->ws;
3271 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3272 struct radv_userdata_info *loc;
3273
3274 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3275 AC_UD_CS_GRID_SIZE);
3276
3277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3278
3279 if (info->indirect) {
3280 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3281
3282 va += info->indirect->offset + info->indirect_offset;
3283
3284 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3285
3286 if (loc->sgpr_idx != -1) {
3287 for (unsigned i = 0; i < 3; ++i) {
3288 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3289 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3290 COPY_DATA_DST_SEL(COPY_DATA_REG));
3291 radeon_emit(cs, (va + 4 * i));
3292 radeon_emit(cs, (va + 4 * i) >> 32);
3293 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3294 + loc->sgpr_idx * 4) >> 2) + i);
3295 radeon_emit(cs, 0);
3296 }
3297 }
3298
3299 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3300 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3301 PKT3_SHADER_TYPE_S(1));
3302 radeon_emit(cs, va);
3303 radeon_emit(cs, va >> 32);
3304 radeon_emit(cs, dispatch_initiator);
3305 } else {
3306 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3307 PKT3_SHADER_TYPE_S(1));
3308 radeon_emit(cs, 1);
3309 radeon_emit(cs, va);
3310 radeon_emit(cs, va >> 32);
3311
3312 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3313 PKT3_SHADER_TYPE_S(1));
3314 radeon_emit(cs, 0);
3315 radeon_emit(cs, dispatch_initiator);
3316 }
3317 } else {
3318 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3319 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3320
3321 if (info->unaligned) {
3322 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3323 unsigned remainder[3];
3324
3325 /* If aligned, these should be an entire block size,
3326 * not 0.
3327 */
3328 remainder[0] = blocks[0] + cs_block_size[0] -
3329 align_u32_npot(blocks[0], cs_block_size[0]);
3330 remainder[1] = blocks[1] + cs_block_size[1] -
3331 align_u32_npot(blocks[1], cs_block_size[1]);
3332 remainder[2] = blocks[2] + cs_block_size[2] -
3333 align_u32_npot(blocks[2], cs_block_size[2]);
3334
3335 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3336 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3337 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3338
3339 for(unsigned i = 0; i < 3; ++i) {
3340 assert(offsets[i] % cs_block_size[i] == 0);
3341 offsets[i] /= cs_block_size[i];
3342 }
3343
3344 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3345 radeon_emit(cs,
3346 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3347 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3348 radeon_emit(cs,
3349 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3350 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3351 radeon_emit(cs,
3352 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3353 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3354
3355 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3356 }
3357
3358 if (loc->sgpr_idx != -1) {
3359 assert(!loc->indirect);
3360 assert(loc->num_sgprs == 3);
3361
3362 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3363 loc->sgpr_idx * 4, 3);
3364 radeon_emit(cs, blocks[0]);
3365 radeon_emit(cs, blocks[1]);
3366 radeon_emit(cs, blocks[2]);
3367 }
3368
3369 if (offsets[0] || offsets[1] || offsets[2]) {
3370 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3371 radeon_emit(cs, offsets[0]);
3372 radeon_emit(cs, offsets[1]);
3373 radeon_emit(cs, offsets[2]);
3374
3375 /* The blocks in the packet are not counts but end values. */
3376 for (unsigned i = 0; i < 3; ++i)
3377 blocks[i] += offsets[i];
3378 } else {
3379 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3380 }
3381
3382 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3383 PKT3_SHADER_TYPE_S(1));
3384 radeon_emit(cs, blocks[0]);
3385 radeon_emit(cs, blocks[1]);
3386 radeon_emit(cs, blocks[2]);
3387 radeon_emit(cs, dispatch_initiator);
3388 }
3389
3390 assert(cmd_buffer->cs->cdw <= cdw_max);
3391 }
3392
3393 static void
3394 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3395 {
3396 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3397 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3398 }
3399
3400 static void
3401 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3402 const struct radv_dispatch_info *info)
3403 {
3404 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3405 bool has_prefetch =
3406 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3407 bool pipeline_is_dirty = pipeline &&
3408 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3409
3410 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3411 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3412 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3413 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3414 /* If we have to wait for idle, set all states first, so that
3415 * all SET packets are processed in parallel with previous draw
3416 * calls. Then upload descriptors, set shader pointers, and
3417 * dispatch, and prefetch at the end. This ensures that the
3418 * time the CUs are idle is very short. (there are only SET_SH
3419 * packets between the wait and the draw)
3420 */
3421 radv_emit_compute_pipeline(cmd_buffer);
3422 si_emit_cache_flush(cmd_buffer);
3423 /* <-- CUs are idle here --> */
3424
3425 radv_upload_compute_shader_descriptors(cmd_buffer);
3426
3427 radv_emit_dispatch_packets(cmd_buffer, info);
3428 /* <-- CUs are busy here --> */
3429
3430 /* Start prefetches after the dispatch has been started. Both
3431 * will run in parallel, but starting the dispatch first is
3432 * more important.
3433 */
3434 if (has_prefetch && pipeline_is_dirty) {
3435 radv_emit_shader_prefetch(cmd_buffer,
3436 pipeline->shaders[MESA_SHADER_COMPUTE]);
3437 }
3438 } else {
3439 /* If we don't wait for idle, start prefetches first, then set
3440 * states, and dispatch at the end.
3441 */
3442 si_emit_cache_flush(cmd_buffer);
3443
3444 if (has_prefetch && pipeline_is_dirty) {
3445 radv_emit_shader_prefetch(cmd_buffer,
3446 pipeline->shaders[MESA_SHADER_COMPUTE]);
3447 }
3448
3449 radv_upload_compute_shader_descriptors(cmd_buffer);
3450
3451 radv_emit_compute_pipeline(cmd_buffer);
3452 radv_emit_dispatch_packets(cmd_buffer, info);
3453 }
3454
3455 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3456 }
3457
3458 void radv_CmdDispatchBase(
3459 VkCommandBuffer commandBuffer,
3460 uint32_t base_x,
3461 uint32_t base_y,
3462 uint32_t base_z,
3463 uint32_t x,
3464 uint32_t y,
3465 uint32_t z)
3466 {
3467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3468 struct radv_dispatch_info info = {};
3469
3470 info.blocks[0] = x;
3471 info.blocks[1] = y;
3472 info.blocks[2] = z;
3473
3474 info.offsets[0] = base_x;
3475 info.offsets[1] = base_y;
3476 info.offsets[2] = base_z;
3477 radv_dispatch(cmd_buffer, &info);
3478 }
3479
3480 void radv_CmdDispatch(
3481 VkCommandBuffer commandBuffer,
3482 uint32_t x,
3483 uint32_t y,
3484 uint32_t z)
3485 {
3486 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3487 }
3488
3489 void radv_CmdDispatchIndirect(
3490 VkCommandBuffer commandBuffer,
3491 VkBuffer _buffer,
3492 VkDeviceSize offset)
3493 {
3494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3495 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3496 struct radv_dispatch_info info = {};
3497
3498 info.indirect = buffer;
3499 info.indirect_offset = offset;
3500
3501 radv_dispatch(cmd_buffer, &info);
3502 }
3503
3504 void radv_unaligned_dispatch(
3505 struct radv_cmd_buffer *cmd_buffer,
3506 uint32_t x,
3507 uint32_t y,
3508 uint32_t z)
3509 {
3510 struct radv_dispatch_info info = {};
3511
3512 info.blocks[0] = x;
3513 info.blocks[1] = y;
3514 info.blocks[2] = z;
3515 info.unaligned = 1;
3516
3517 radv_dispatch(cmd_buffer, &info);
3518 }
3519
3520 void radv_CmdEndRenderPass(
3521 VkCommandBuffer commandBuffer)
3522 {
3523 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3524
3525 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3526
3527 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3528
3529 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3530 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3531 radv_handle_subpass_image_transition(cmd_buffer,
3532 (VkAttachmentReference){i, layout});
3533 }
3534
3535 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3536
3537 cmd_buffer->state.pass = NULL;
3538 cmd_buffer->state.subpass = NULL;
3539 cmd_buffer->state.attachments = NULL;
3540 cmd_buffer->state.framebuffer = NULL;
3541 }
3542
3543 /*
3544 * For HTILE we have the following interesting clear words:
3545 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3546 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3547 * 0xfffffff0: Clear depth to 1.0
3548 * 0x00000000: Clear depth to 0.0
3549 */
3550 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3551 struct radv_image *image,
3552 const VkImageSubresourceRange *range,
3553 uint32_t clear_word)
3554 {
3555 assert(range->baseMipLevel == 0);
3556 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3557 unsigned layer_count = radv_get_layerCount(image, range);
3558 uint64_t size = image->surface.htile_slice_size * layer_count;
3559 uint64_t offset = image->offset + image->htile_offset +
3560 image->surface.htile_slice_size * range->baseArrayLayer;
3561 struct radv_cmd_state *state = &cmd_buffer->state;
3562
3563 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3564 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3565
3566 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3567 size, clear_word);
3568
3569 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3570 }
3571
3572 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3573 struct radv_image *image,
3574 VkImageLayout src_layout,
3575 VkImageLayout dst_layout,
3576 unsigned src_queue_mask,
3577 unsigned dst_queue_mask,
3578 const VkImageSubresourceRange *range,
3579 VkImageAspectFlags pending_clears)
3580 {
3581 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3582 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3583 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3584 cmd_buffer->state.render_area.extent.width == image->info.width &&
3585 cmd_buffer->state.render_area.extent.height == image->info.height) {
3586 /* The clear will initialize htile. */
3587 return;
3588 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3589 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3590 /* TODO: merge with the clear if applicable */
3591 radv_initialize_htile(cmd_buffer, image, range, 0);
3592 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3593 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3594 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3595 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3596 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3597 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3598 VkImageSubresourceRange local_range = *range;
3599 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3600 local_range.baseMipLevel = 0;
3601 local_range.levelCount = 1;
3602
3603 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3604 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3605
3606 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3607
3608 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3609 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3610 }
3611 }
3612
3613 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3614 struct radv_image *image, uint32_t value)
3615 {
3616 struct radv_cmd_state *state = &cmd_buffer->state;
3617
3618 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3619 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3620
3621 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3622
3623 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3624 }
3625
3626 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3627 struct radv_image *image,
3628 VkImageLayout src_layout,
3629 VkImageLayout dst_layout,
3630 unsigned src_queue_mask,
3631 unsigned dst_queue_mask,
3632 const VkImageSubresourceRange *range)
3633 {
3634 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3635 if (radv_image_has_fmask(image))
3636 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3637 else
3638 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3639 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3640 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3641 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3642 }
3643 }
3644
3645 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3646 struct radv_image *image, uint32_t value)
3647 {
3648 struct radv_cmd_state *state = &cmd_buffer->state;
3649
3650 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3651 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3652
3653 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3654
3655 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3656 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3657 }
3658
3659 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3660 struct radv_image *image,
3661 VkImageLayout src_layout,
3662 VkImageLayout dst_layout,
3663 unsigned src_queue_mask,
3664 unsigned dst_queue_mask,
3665 const VkImageSubresourceRange *range)
3666 {
3667 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3668 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3669 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3670 radv_initialize_dcc(cmd_buffer, image,
3671 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3672 0x20202020u : 0xffffffffu);
3673 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3674 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3675 radv_decompress_dcc(cmd_buffer, image, range);
3676 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3677 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3678 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3679 }
3680 }
3681
3682 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3683 struct radv_image *image,
3684 VkImageLayout src_layout,
3685 VkImageLayout dst_layout,
3686 uint32_t src_family,
3687 uint32_t dst_family,
3688 const VkImageSubresourceRange *range,
3689 VkImageAspectFlags pending_clears)
3690 {
3691 if (image->exclusive && src_family != dst_family) {
3692 /* This is an acquire or a release operation and there will be
3693 * a corresponding release/acquire. Do the transition in the
3694 * most flexible queue. */
3695
3696 assert(src_family == cmd_buffer->queue_family_index ||
3697 dst_family == cmd_buffer->queue_family_index);
3698
3699 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3700 return;
3701
3702 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3703 (src_family == RADV_QUEUE_GENERAL ||
3704 dst_family == RADV_QUEUE_GENERAL))
3705 return;
3706 }
3707
3708 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3709 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3710
3711 if (radv_image_has_htile(image))
3712 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3713 dst_layout, src_queue_mask,
3714 dst_queue_mask, range,
3715 pending_clears);
3716
3717 if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
3718 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3719 dst_layout, src_queue_mask,
3720 dst_queue_mask, range);
3721
3722 if (radv_image_has_dcc(image))
3723 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3724 dst_layout, src_queue_mask,
3725 dst_queue_mask, range);
3726 }
3727
3728 void radv_CmdPipelineBarrier(
3729 VkCommandBuffer commandBuffer,
3730 VkPipelineStageFlags srcStageMask,
3731 VkPipelineStageFlags destStageMask,
3732 VkBool32 byRegion,
3733 uint32_t memoryBarrierCount,
3734 const VkMemoryBarrier* pMemoryBarriers,
3735 uint32_t bufferMemoryBarrierCount,
3736 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3737 uint32_t imageMemoryBarrierCount,
3738 const VkImageMemoryBarrier* pImageMemoryBarriers)
3739 {
3740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3741 enum radv_cmd_flush_bits src_flush_bits = 0;
3742 enum radv_cmd_flush_bits dst_flush_bits = 0;
3743
3744 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3745 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3746 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3747 NULL);
3748 }
3749
3750 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3751 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3752 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3753 NULL);
3754 }
3755
3756 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3757 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3758 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3759 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3760 image);
3761 }
3762
3763 radv_stage_flush(cmd_buffer, srcStageMask);
3764 cmd_buffer->state.flush_bits |= src_flush_bits;
3765
3766 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3767 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3768 radv_handle_image_transition(cmd_buffer, image,
3769 pImageMemoryBarriers[i].oldLayout,
3770 pImageMemoryBarriers[i].newLayout,
3771 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3772 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3773 &pImageMemoryBarriers[i].subresourceRange,
3774 0);
3775 }
3776
3777 cmd_buffer->state.flush_bits |= dst_flush_bits;
3778 }
3779
3780
3781 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3782 struct radv_event *event,
3783 VkPipelineStageFlags stageMask,
3784 unsigned value)
3785 {
3786 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3787 uint64_t va = radv_buffer_get_va(event->bo);
3788
3789 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3790
3791 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3792
3793 /* TODO: this is overkill. Probably should figure something out from
3794 * the stage mask. */
3795
3796 si_cs_emit_write_event_eop(cs,
3797 cmd_buffer->state.predicating,
3798 cmd_buffer->device->physical_device->rad_info.chip_class,
3799 radv_cmd_buffer_uses_mec(cmd_buffer),
3800 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3801 1, va, 2, value);
3802
3803 assert(cmd_buffer->cs->cdw <= cdw_max);
3804 }
3805
3806 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3807 VkEvent _event,
3808 VkPipelineStageFlags stageMask)
3809 {
3810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3811 RADV_FROM_HANDLE(radv_event, event, _event);
3812
3813 write_event(cmd_buffer, event, stageMask, 1);
3814 }
3815
3816 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3817 VkEvent _event,
3818 VkPipelineStageFlags stageMask)
3819 {
3820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3821 RADV_FROM_HANDLE(radv_event, event, _event);
3822
3823 write_event(cmd_buffer, event, stageMask, 0);
3824 }
3825
3826 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3827 uint32_t eventCount,
3828 const VkEvent* pEvents,
3829 VkPipelineStageFlags srcStageMask,
3830 VkPipelineStageFlags dstStageMask,
3831 uint32_t memoryBarrierCount,
3832 const VkMemoryBarrier* pMemoryBarriers,
3833 uint32_t bufferMemoryBarrierCount,
3834 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3835 uint32_t imageMemoryBarrierCount,
3836 const VkImageMemoryBarrier* pImageMemoryBarriers)
3837 {
3838 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3839 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3840
3841 for (unsigned i = 0; i < eventCount; ++i) {
3842 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3843 uint64_t va = radv_buffer_get_va(event->bo);
3844
3845 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3846
3847 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3848
3849 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3850 assert(cmd_buffer->cs->cdw <= cdw_max);
3851 }
3852
3853
3854 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3855 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3856
3857 radv_handle_image_transition(cmd_buffer, image,
3858 pImageMemoryBarriers[i].oldLayout,
3859 pImageMemoryBarriers[i].newLayout,
3860 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3861 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3862 &pImageMemoryBarriers[i].subresourceRange,
3863 0);
3864 }
3865
3866 /* TODO: figure out how to do memory barriers without waiting */
3867 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3868 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3869 RADV_CMD_FLAG_INV_VMEM_L1 |
3870 RADV_CMD_FLAG_INV_SMEM_L1;
3871 }
3872
3873
3874 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3875 uint32_t deviceMask)
3876 {
3877 /* No-op */
3878 }