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3bf2d4a8b933c97668c77b51eb573b272224a015
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
207 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
208 cmd_buffer->device = device;
209 cmd_buffer->pool = pool;
210 cmd_buffer->level = level;
211
212 if (pool) {
213 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
214 cmd_buffer->queue_family_index = pool->queue_family_index;
215
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
222 }
223
224 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
225
226 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
227 if (!cmd_buffer->cs) {
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230 }
231
232 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
233
234 cmd_buffer->upload.offset = 0;
235 cmd_buffer->upload.size = 0;
236 list_inithead(&cmd_buffer->upload.list);
237
238 return VK_SUCCESS;
239 }
240
241 static void
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
243 {
244 list_del(&cmd_buffer->pool_link);
245
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
247 &cmd_buffer->upload.list, list) {
248 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
249 list_del(&up->list);
250 free(up);
251 }
252
253 if (cmd_buffer->upload.upload_bo)
254 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
255 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
256 free(cmd_buffer->push_descriptors.set.mapped_ptr);
257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
258 }
259
260 static VkResult
261 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
262 {
263
264 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
265
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
267 &cmd_buffer->upload.list, list) {
268 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
269 list_del(&up->list);
270 free(up);
271 }
272
273 cmd_buffer->push_constant_stages = 0;
274 cmd_buffer->scratch_size_needed = 0;
275 cmd_buffer->compute_scratch_size_needed = 0;
276 cmd_buffer->esgs_ring_size_needed = 0;
277 cmd_buffer->gsvs_ring_size_needed = 0;
278 cmd_buffer->tess_rings_needed = false;
279 cmd_buffer->sample_positions_needed = false;
280
281 if (cmd_buffer->upload.upload_bo)
282 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
283 cmd_buffer->upload.upload_bo, 8);
284 cmd_buffer->upload.offset = 0;
285
286 cmd_buffer->record_result = VK_SUCCESS;
287
288 cmd_buffer->ring_offsets_idx = -1;
289
290 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
291 void *fence_ptr;
292 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
293 &cmd_buffer->gfx9_fence_offset,
294 &fence_ptr);
295 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
296 }
297
298 return cmd_buffer->record_result;
299 }
300
301 static bool
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
303 uint64_t min_needed)
304 {
305 uint64_t new_size;
306 struct radeon_winsys_bo *bo;
307 struct radv_cmd_buffer_upload *upload;
308 struct radv_device *device = cmd_buffer->device;
309
310 new_size = MAX2(min_needed, 16 * 1024);
311 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
312
313 bo = device->ws->buffer_create(device->ws,
314 new_size, 4096,
315 RADEON_DOMAIN_GTT,
316 RADEON_FLAG_CPU_ACCESS|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING);
318
319 if (!bo) {
320 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
321 return false;
322 }
323
324 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
325 if (cmd_buffer->upload.upload_bo) {
326 upload = malloc(sizeof(*upload));
327
328 if (!upload) {
329 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
330 device->ws->buffer_destroy(bo);
331 return false;
332 }
333
334 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
335 list_add(&upload->list, &cmd_buffer->upload.list);
336 }
337
338 cmd_buffer->upload.upload_bo = bo;
339 cmd_buffer->upload.size = new_size;
340 cmd_buffer->upload.offset = 0;
341 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
342
343 if (!cmd_buffer->upload.map) {
344 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
345 return false;
346 }
347
348 return true;
349 }
350
351 bool
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
353 unsigned size,
354 unsigned alignment,
355 unsigned *out_offset,
356 void **ptr)
357 {
358 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
359 if (offset + size > cmd_buffer->upload.size) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
361 return false;
362 offset = 0;
363 }
364
365 *out_offset = offset;
366 *ptr = cmd_buffer->upload.map + offset;
367
368 cmd_buffer->upload.offset = offset + size;
369 return true;
370 }
371
372 bool
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
374 unsigned size, unsigned alignment,
375 const void *data, unsigned *out_offset)
376 {
377 uint8_t *ptr;
378
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
380 out_offset, (void **)&ptr))
381 return false;
382
383 if (ptr)
384 memcpy(ptr, data, size);
385
386 return true;
387 }
388
389 static void
390 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
391 unsigned count, const uint32_t *data)
392 {
393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME));
397 radeon_emit(cs, va);
398 radeon_emit(cs, va >> 32);
399 radeon_emit_array(cs, data, count);
400 }
401
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
403 {
404 struct radv_device *device = cmd_buffer->device;
405 struct radeon_winsys_cs *cs = cmd_buffer->cs;
406 uint64_t va;
407
408 if (!device->trace_bo)
409 return;
410
411 va = radv_buffer_get_va(device->trace_bo);
412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
413 va += 4;
414
415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
416
417 ++cmd_buffer->state.trace_id;
418 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
419 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
421 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
422 }
423
424 static void
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
426 {
427 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
428 enum radv_cmd_flush_bits flags;
429
430 /* Force wait for graphics/compute engines to be idle. */
431 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
433
434 si_cs_emit_cache_flush(cmd_buffer->cs, false,
435 cmd_buffer->device->physical_device->rad_info.chip_class,
436 NULL, 0,
437 radv_cmd_buffer_uses_mec(cmd_buffer),
438 flags);
439 }
440
441 radv_cmd_buffer_trace_emit(cmd_buffer);
442 }
443
444 static void
445 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
446 struct radv_pipeline *pipeline, enum ring_type ring)
447 {
448 struct radv_device *device = cmd_buffer->device;
449 struct radeon_winsys_cs *cs = cmd_buffer->cs;
450 uint32_t data[2];
451 uint64_t va;
452
453 if (!device->trace_bo)
454 return;
455
456 va = radv_buffer_get_va(device->trace_bo);
457
458 switch (ring) {
459 case RING_GFX:
460 va += 8;
461 break;
462 case RING_COMPUTE:
463 va += 16;
464 break;
465 default:
466 assert(!"invalid ring type");
467 }
468
469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
470 cmd_buffer->cs, 6);
471
472 data[0] = (uintptr_t)pipeline;
473 data[1] = (uintptr_t)pipeline >> 32;
474
475 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
476 radv_emit_write_data_packet(cs, va, 2, data);
477 }
478
479 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
480 struct radv_descriptor_set *set,
481 unsigned idx)
482 {
483 cmd_buffer->descriptors[idx] = set;
484 if (set)
485 cmd_buffer->state.valid_descriptors |= (1u << idx);
486 else
487 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
488 cmd_buffer->state.descriptors_dirty |= (1u << idx);
489
490 }
491
492 static void
493 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_winsys_cs *cs = cmd_buffer->cs;
497 uint32_t data[MAX_SETS * 2] = {};
498 uint64_t va;
499 unsigned i;
500 va = radv_buffer_get_va(device->trace_bo) + 24;
501
502 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
503 cmd_buffer->cs, 4 + MAX_SETS * 2);
504
505 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
506 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
507 data[i * 2] = (uintptr_t)set;
508 data[i * 2 + 1] = (uintptr_t)set >> 32;
509 }
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
513 }
514
515 static void
516 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline)
518 {
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
521 8);
522 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
523 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
524
525 if (cmd_buffer->device->physical_device->has_rbplus) {
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
528 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
529
530 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
531 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
532 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
533 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
534 }
535 }
536
537 static void
538 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline)
540 {
541 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
542 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
543 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
544
545 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
546 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
547 }
548
549 struct ac_userdata_info *
550 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
551 gl_shader_stage stage,
552 int idx)
553 {
554 if (stage == MESA_SHADER_VERTEX) {
555 if (pipeline->shaders[MESA_SHADER_VERTEX])
556 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
557 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
558 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
559 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
560 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
561 } else if (stage == MESA_SHADER_TESS_EVAL) {
562 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
563 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
564 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
565 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
566 }
567 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580 assert(loc->num_sgprs == 2);
581 assert(!loc->indirect);
582 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
583 radeon_emit(cmd_buffer->cs, va);
584 radeon_emit(cmd_buffer->cs, va >> 32);
585 }
586
587 static void
588 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
589 struct radv_pipeline *pipeline)
590 {
591 int num_samples = pipeline->graphics.ms.num_samples;
592 struct radv_multisample_state *ms = &pipeline->graphics.ms;
593 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
596 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
597 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
598
599 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
600 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
601
602 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
603 return;
604
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
606 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
607 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
608
609 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
610
611 /* GFX9: Flush DFSM when the AA mode changes. */
612 if (cmd_buffer->device->dfsm_allowed) {
613 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
614 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
615 }
616 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
617 uint32_t offset;
618 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
619 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
620 if (loc->sgpr_idx == -1)
621 return;
622 assert(loc->num_sgprs == 1);
623 assert(!loc->indirect);
624 switch (num_samples) {
625 default:
626 offset = 0;
627 break;
628 case 2:
629 offset = 1;
630 break;
631 case 4:
632 offset = 3;
633 break;
634 case 8:
635 offset = 7;
636 break;
637 case 16:
638 offset = 15;
639 break;
640 }
641
642 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
643 cmd_buffer->sample_positions_needed = true;
644 }
645 }
646
647 static void
648 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 struct radv_raster_state *raster = &pipeline->graphics.raster;
652
653 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
654 raster->pa_cl_clip_cntl);
655 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
656 raster->spi_interp_control);
657 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
658 raster->pa_su_vtx_cntl);
659 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
660 raster->pa_su_sc_mode_cntl);
661 }
662
663 static void
664 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
665 struct radv_shader_variant *shader)
666 {
667 struct radeon_winsys *ws = cmd_buffer->device->ws;
668 struct radeon_winsys_cs *cs = cmd_buffer->cs;
669 uint64_t va;
670
671 if (!shader)
672 return;
673
674 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
675
676 radv_cs_add_buffer(ws, cs, shader->bo, 8);
677 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
678 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
679 }
680
681 static void
682 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
683 struct radv_pipeline *pipeline)
684 {
685 radv_emit_shader_prefetch(cmd_buffer,
686 pipeline->shaders[MESA_SHADER_VERTEX]);
687 radv_emit_shader_prefetch(cmd_buffer,
688 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
691 radv_emit_shader_prefetch(cmd_buffer,
692 pipeline->shaders[MESA_SHADER_GEOMETRY]);
693 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
694 radv_emit_shader_prefetch(cmd_buffer,
695 pipeline->shaders[MESA_SHADER_FRAGMENT]);
696 }
697
698 static void
699 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
700 struct radv_pipeline *pipeline,
701 struct radv_shader_variant *shader)
702 {
703 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
704
705 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
706 pipeline->graphics.vs.spi_vs_out_config);
707
708 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
709 pipeline->graphics.vs.spi_shader_pos_format);
710
711 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
712 radeon_emit(cmd_buffer->cs, va >> 8);
713 radeon_emit(cmd_buffer->cs, va >> 40);
714 radeon_emit(cmd_buffer->cs, shader->rsrc1);
715 radeon_emit(cmd_buffer->cs, shader->rsrc2);
716
717 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
718 S_028818_VTX_W0_FMT(1) |
719 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
720 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
721 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
722
723
724 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
725 pipeline->graphics.vs.pa_cl_vs_out_cntl);
726
727 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
728 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
729 pipeline->graphics.vs.vgt_reuse_off);
730 }
731
732 static void
733 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
734 struct radv_pipeline *pipeline,
735 struct radv_shader_variant *shader)
736 {
737 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
738
739 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
740 radeon_emit(cmd_buffer->cs, va >> 8);
741 radeon_emit(cmd_buffer->cs, va >> 40);
742 radeon_emit(cmd_buffer->cs, shader->rsrc1);
743 radeon_emit(cmd_buffer->cs, shader->rsrc2);
744 }
745
746 static void
747 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_shader_variant *shader)
749 {
750 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
751 uint32_t rsrc2 = shader->rsrc2;
752
753 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
754 radeon_emit(cmd_buffer->cs, va >> 8);
755 radeon_emit(cmd_buffer->cs, va >> 40);
756
757 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
758 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
759 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
760 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
761
762 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
763 radeon_emit(cmd_buffer->cs, shader->rsrc1);
764 radeon_emit(cmd_buffer->cs, rsrc2);
765 }
766
767 static void
768 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
769 struct radv_shader_variant *shader)
770 {
771 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
772
773 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
774 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
775 radeon_emit(cmd_buffer->cs, va >> 8);
776 radeon_emit(cmd_buffer->cs, va >> 40);
777
778 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
779 radeon_emit(cmd_buffer->cs, shader->rsrc1);
780 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
781 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
782 } else {
783 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
784 radeon_emit(cmd_buffer->cs, va >> 8);
785 radeon_emit(cmd_buffer->cs, va >> 40);
786 radeon_emit(cmd_buffer->cs, shader->rsrc1);
787 radeon_emit(cmd_buffer->cs, shader->rsrc2);
788 }
789 }
790
791 static void
792 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
793 struct radv_pipeline *pipeline)
794 {
795 struct radv_shader_variant *vs;
796
797 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
798
799 /* Skip shaders merged into HS/GS */
800 vs = pipeline->shaders[MESA_SHADER_VERTEX];
801 if (!vs)
802 return;
803
804 if (vs->info.vs.as_ls)
805 radv_emit_hw_ls(cmd_buffer, vs);
806 else if (vs->info.vs.as_es)
807 radv_emit_hw_es(cmd_buffer, pipeline, vs);
808 else
809 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
810 }
811
812
813 static void
814 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
815 struct radv_pipeline *pipeline)
816 {
817 if (!radv_pipeline_has_tess(pipeline))
818 return;
819
820 struct radv_shader_variant *tes, *tcs;
821
822 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
823 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
824
825 if (tes) {
826 if (tes->info.tes.as_es)
827 radv_emit_hw_es(cmd_buffer, pipeline, tes);
828 else
829 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
830 }
831
832 radv_emit_hw_hs(cmd_buffer, tcs);
833
834 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
835 pipeline->graphics.tess.tf_param);
836
837 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
838 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
839 pipeline->graphics.tess.ls_hs_config);
840 else
841 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
842 pipeline->graphics.tess.ls_hs_config);
843
844 struct ac_userdata_info *loc;
845
846 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
847 if (loc->sgpr_idx != -1) {
848 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
849 assert(loc->num_sgprs == 4);
850 assert(!loc->indirect);
851 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
852 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
853 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
854 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
855 pipeline->graphics.tess.num_tcs_input_cp << 26);
856 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
857 }
858
859 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
860 if (loc->sgpr_idx != -1) {
861 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
862 assert(loc->num_sgprs == 1);
863 assert(!loc->indirect);
864
865 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
866 pipeline->graphics.tess.offchip_layout);
867 }
868
869 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
870 if (loc->sgpr_idx != -1) {
871 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
872 assert(loc->num_sgprs == 1);
873 assert(!loc->indirect);
874
875 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
876 pipeline->graphics.tess.tcs_in_layout);
877 }
878 }
879
880 static void
881 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
882 struct radv_pipeline *pipeline)
883 {
884 struct radv_shader_variant *gs;
885 uint64_t va;
886
887 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
888
889 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
890 if (!gs)
891 return;
892
893 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
894
895 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
896 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
897 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
898 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
899
900 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
901
902 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
903
904 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
905 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
906 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
907 radeon_emit(cmd_buffer->cs, 0);
908 radeon_emit(cmd_buffer->cs, 0);
909 radeon_emit(cmd_buffer->cs, 0);
910
911 uint32_t gs_num_invocations = gs->info.gs.invocations;
912 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
913 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
914 S_028B90_ENABLE(gs_num_invocations > 0));
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
917 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
918
919 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
922 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
923 radeon_emit(cmd_buffer->cs, va >> 8);
924 radeon_emit(cmd_buffer->cs, va >> 40);
925
926 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
927 radeon_emit(cmd_buffer->cs, gs->rsrc1);
928 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
929 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
930
931 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
932 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
933 } else {
934 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
935 radeon_emit(cmd_buffer->cs, va >> 8);
936 radeon_emit(cmd_buffer->cs, va >> 40);
937 radeon_emit(cmd_buffer->cs, gs->rsrc1);
938 radeon_emit(cmd_buffer->cs, gs->rsrc2);
939 }
940
941 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
942
943 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
944 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
945 if (loc->sgpr_idx != -1) {
946 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
947 uint32_t num_entries = 64;
948 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
949
950 if (is_vi)
951 num_entries *= stride;
952
953 stride = S_008F04_STRIDE(stride);
954 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
955 radeon_emit(cmd_buffer->cs, stride);
956 radeon_emit(cmd_buffer->cs, num_entries);
957 }
958 }
959
960 static void
961 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
962 struct radv_pipeline *pipeline)
963 {
964 struct radv_shader_variant *ps;
965 uint64_t va;
966 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
967 struct radv_blend_state *blend = &pipeline->graphics.blend;
968 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
969
970 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
971 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
972
973 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
974 radeon_emit(cmd_buffer->cs, va >> 8);
975 radeon_emit(cmd_buffer->cs, va >> 40);
976 radeon_emit(cmd_buffer->cs, ps->rsrc1);
977 radeon_emit(cmd_buffer->cs, ps->rsrc2);
978
979 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
980 pipeline->graphics.db_shader_control);
981
982 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
983 ps->config.spi_ps_input_ena);
984
985 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
986 ps->config.spi_ps_input_addr);
987
988 if (ps->info.info.ps.force_persample)
989 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
990
991 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
992 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
993
994 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
997 pipeline->graphics.shader_z_format);
998
999 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1000
1001 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1002 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1003
1004 if (cmd_buffer->device->dfsm_allowed) {
1005 /* optimise this? */
1006 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1007 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1008 }
1009
1010 if (pipeline->graphics.ps_input_cntl_num) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1012 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1013 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1014 }
1015 }
1016 }
1017
1018 static void
1019 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1020 struct radv_pipeline *pipeline)
1021 {
1022 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1023
1024 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1025 return;
1026
1027 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1028 pipeline->graphics.vtx_reuse_depth);
1029 }
1030
1031 static void
1032 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1033 {
1034 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1035
1036 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1037 return;
1038
1039 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1040 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1041 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1042 radv_update_multisample_state(cmd_buffer, pipeline);
1043 radv_emit_vertex_shader(cmd_buffer, pipeline);
1044 radv_emit_tess_shaders(cmd_buffer, pipeline);
1045 radv_emit_geometry_shader(cmd_buffer, pipeline);
1046 radv_emit_fragment_shader(cmd_buffer, pipeline);
1047 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1048
1049 cmd_buffer->scratch_size_needed =
1050 MAX2(cmd_buffer->scratch_size_needed,
1051 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1052
1053 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1054 S_0286E8_WAVES(pipeline->max_waves) |
1055 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1056
1057 if (!cmd_buffer->state.emitted_pipeline ||
1058 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1059 pipeline->graphics.can_use_guardband)
1060 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1061
1062 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1063
1064 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1065 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1066 } else {
1067 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1068 }
1069 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1070
1071 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1072
1073 cmd_buffer->state.emitted_pipeline = pipeline;
1074
1075 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1076 }
1077
1078 static void
1079 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1080 {
1081 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1082 cmd_buffer->state.dynamic.viewport.viewports);
1083 }
1084
1085 static void
1086 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1087 {
1088 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1089
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1092 si_emit_cache_flush(cmd_buffer);
1093 }
1094 si_write_scissors(cmd_buffer->cs, 0, count,
1095 cmd_buffer->state.dynamic.scissor.scissors,
1096 cmd_buffer->state.dynamic.viewport.viewports,
1097 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1098 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1099 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1100 }
1101
1102 static void
1103 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1104 {
1105 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1106
1107 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1108 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1109 }
1110
1111 static void
1112 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1113 {
1114 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1115
1116 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1117 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1118 }
1119
1120 static void
1121 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1122 {
1123 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1124
1125 radeon_set_context_reg_seq(cmd_buffer->cs,
1126 R_028430_DB_STENCILREFMASK, 2);
1127 radeon_emit(cmd_buffer->cs,
1128 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1129 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1130 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1131 S_028430_STENCILOPVAL(1));
1132 radeon_emit(cmd_buffer->cs,
1133 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1134 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1135 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1136 S_028434_STENCILOPVAL_BF(1));
1137 }
1138
1139 static void
1140 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1141 {
1142 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1143
1144 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1145 fui(d->depth_bounds.min));
1146 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1147 fui(d->depth_bounds.max));
1148 }
1149
1150 static void
1151 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1152 {
1153 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1154 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1155 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1156 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1157
1158 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1159 radeon_set_context_reg_seq(cmd_buffer->cs,
1160 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1161 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1162 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1163 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1164 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1165 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1166 }
1167 }
1168
1169 static void
1170 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1171 int index,
1172 struct radv_color_buffer_info *cb)
1173 {
1174 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1175
1176 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1177 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1178 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1179 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1180 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1181 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1182 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1183 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1184 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1185 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1186 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1187 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1188 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1189
1190 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1191 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1192 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1193
1194 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1195 cb->gfx9_epitch);
1196 } else {
1197 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1204 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1205 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1206 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1207 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1208 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1209
1210 if (is_vi) { /* DCC BASE */
1211 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1212 }
1213 }
1214 }
1215
1216 static void
1217 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1218 struct radv_ds_buffer_info *ds,
1219 struct radv_image *image,
1220 VkImageLayout layout)
1221 {
1222 uint32_t db_z_info = ds->db_z_info;
1223 uint32_t db_stencil_info = ds->db_stencil_info;
1224
1225 if (!radv_layout_has_htile(image, layout,
1226 radv_image_queue_family_mask(image,
1227 cmd_buffer->queue_family_index,
1228 cmd_buffer->queue_family_index))) {
1229 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1230 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1231 }
1232
1233 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1234 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1235
1236
1237 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1238 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1239 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1240 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1241 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1242
1243 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1244 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1245 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1246 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1247 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1248 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1249 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1250 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1251 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1252 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1253 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1254
1255 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1256 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1257 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1258 } else {
1259 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1260
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1262 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1263 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1264 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1265 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1267 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1269 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1270 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1271
1272 }
1273
1274 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1275 ds->pa_su_poly_offset_db_fmt_cntl);
1276 }
1277
1278 void
1279 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1280 struct radv_image *image,
1281 VkClearDepthStencilValue ds_clear_value,
1282 VkImageAspectFlags aspects)
1283 {
1284 uint64_t va = radv_buffer_get_va(image->bo);
1285 va += image->offset + image->clear_value_offset;
1286 unsigned reg_offset = 0, reg_count = 0;
1287
1288 if (!image->surface.htile_size || !aspects)
1289 return;
1290
1291 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1292 ++reg_count;
1293 } else {
1294 ++reg_offset;
1295 va += 4;
1296 }
1297 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1298 ++reg_count;
1299
1300 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1301
1302 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1303 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1304 S_370_WR_CONFIRM(1) |
1305 S_370_ENGINE_SEL(V_370_PFP));
1306 radeon_emit(cmd_buffer->cs, va);
1307 radeon_emit(cmd_buffer->cs, va >> 32);
1308 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1309 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1310 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1311 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1312
1313 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1314 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1315 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1316 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1317 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1318 }
1319
1320 static void
1321 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1322 struct radv_image *image)
1323 {
1324 uint64_t va = radv_buffer_get_va(image->bo);
1325 va += image->offset + image->clear_value_offset;
1326
1327 if (!image->surface.htile_size)
1328 return;
1329
1330
1331 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1332 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1333 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1334 COPY_DATA_COUNT_SEL);
1335 radeon_emit(cmd_buffer->cs, va);
1336 radeon_emit(cmd_buffer->cs, va >> 32);
1337 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1338 radeon_emit(cmd_buffer->cs, 0);
1339
1340 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1341 radeon_emit(cmd_buffer->cs, 0);
1342 }
1343
1344 /*
1345 *with DCC some colors don't require CMASK elimiation before being
1346 * used as a texture. This sets a predicate value to determine if the
1347 * cmask eliminate is required.
1348 */
1349 void
1350 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1351 struct radv_image *image,
1352 bool value)
1353 {
1354 uint64_t pred_val = value;
1355 uint64_t va = radv_buffer_get_va(image->bo);
1356 va += image->offset + image->dcc_pred_offset;
1357
1358 if (!image->surface.dcc_size)
1359 return;
1360
1361 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1362
1363 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1364 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1365 S_370_WR_CONFIRM(1) |
1366 S_370_ENGINE_SEL(V_370_PFP));
1367 radeon_emit(cmd_buffer->cs, va);
1368 radeon_emit(cmd_buffer->cs, va >> 32);
1369 radeon_emit(cmd_buffer->cs, pred_val);
1370 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1371 }
1372
1373 void
1374 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1375 struct radv_image *image,
1376 int idx,
1377 uint32_t color_values[2])
1378 {
1379 uint64_t va = radv_buffer_get_va(image->bo);
1380 va += image->offset + image->clear_value_offset;
1381
1382 if (!image->cmask.size && !image->surface.dcc_size)
1383 return;
1384
1385 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1386
1387 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1388 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1389 S_370_WR_CONFIRM(1) |
1390 S_370_ENGINE_SEL(V_370_PFP));
1391 radeon_emit(cmd_buffer->cs, va);
1392 radeon_emit(cmd_buffer->cs, va >> 32);
1393 radeon_emit(cmd_buffer->cs, color_values[0]);
1394 radeon_emit(cmd_buffer->cs, color_values[1]);
1395
1396 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1397 radeon_emit(cmd_buffer->cs, color_values[0]);
1398 radeon_emit(cmd_buffer->cs, color_values[1]);
1399 }
1400
1401 static void
1402 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1403 struct radv_image *image,
1404 int idx)
1405 {
1406 uint64_t va = radv_buffer_get_va(image->bo);
1407 va += image->offset + image->clear_value_offset;
1408
1409 if (!image->cmask.size && !image->surface.dcc_size)
1410 return;
1411
1412 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1413
1414 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1415 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1416 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1417 COPY_DATA_COUNT_SEL);
1418 radeon_emit(cmd_buffer->cs, va);
1419 radeon_emit(cmd_buffer->cs, va >> 32);
1420 radeon_emit(cmd_buffer->cs, reg >> 2);
1421 radeon_emit(cmd_buffer->cs, 0);
1422
1423 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1424 radeon_emit(cmd_buffer->cs, 0);
1425 }
1426
1427 void
1428 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1429 {
1430 int i;
1431 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1432 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1433
1434 /* this may happen for inherited secondary recording */
1435 if (!framebuffer)
1436 return;
1437
1438 for (i = 0; i < 8; ++i) {
1439 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1440 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1441 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1442 continue;
1443 }
1444
1445 int idx = subpass->color_attachments[i].attachment;
1446 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1447
1448 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1449
1450 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1451 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1452
1453 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1454 }
1455
1456 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1457 int idx = subpass->depth_stencil_attachment.attachment;
1458 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1459 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1460 struct radv_image *image = att->attachment->image;
1461 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1462 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1463 cmd_buffer->queue_family_index,
1464 cmd_buffer->queue_family_index);
1465 /* We currently don't support writing decompressed HTILE */
1466 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1467 radv_layout_is_htile_compressed(image, layout, queue_mask));
1468
1469 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1470
1471 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1472 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1473 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1474 }
1475 radv_load_depth_clear_regs(cmd_buffer, image);
1476 } else {
1477 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1478 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1479 else
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1481
1482 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1483 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1484 }
1485 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1486 S_028208_BR_X(framebuffer->width) |
1487 S_028208_BR_Y(framebuffer->height));
1488
1489 if (cmd_buffer->device->dfsm_allowed) {
1490 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1491 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1492 }
1493
1494 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1495 }
1496
1497 static void
1498 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1499 {
1500 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1501
1502 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1503 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1504 2, cmd_buffer->state.index_type);
1505 } else {
1506 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1507 radeon_emit(cs, cmd_buffer->state.index_type);
1508 }
1509
1510 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1511 radeon_emit(cs, cmd_buffer->state.index_va);
1512 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1513
1514 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1515 radeon_emit(cs, cmd_buffer->state.max_index_count);
1516
1517 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1518 }
1519
1520 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1521 {
1522 uint32_t db_count_control;
1523
1524 if(!cmd_buffer->state.active_occlusion_queries) {
1525 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1526 db_count_control = 0;
1527 } else {
1528 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1529 }
1530 } else {
1531 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1532 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1533 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1534 S_028004_ZPASS_ENABLE(1) |
1535 S_028004_SLICE_EVEN_ENABLE(1) |
1536 S_028004_SLICE_ODD_ENABLE(1);
1537 } else {
1538 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1539 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1540 }
1541 }
1542
1543 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1544 }
1545
1546 static void
1547 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1548 {
1549 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1550 return;
1551
1552 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1553 radv_emit_viewport(cmd_buffer);
1554
1555 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1556 radv_emit_scissor(cmd_buffer);
1557
1558 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1559 radv_emit_line_width(cmd_buffer);
1560
1561 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1562 radv_emit_blend_constants(cmd_buffer);
1563
1564 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1565 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1566 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1567 radv_emit_stencil(cmd_buffer);
1568
1569 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1570 radv_emit_depth_bounds(cmd_buffer);
1571
1572 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1573 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1574 radv_emit_depth_biais(cmd_buffer);
1575
1576 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1577 }
1578
1579 static void
1580 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1581 struct radv_pipeline *pipeline,
1582 int idx,
1583 uint64_t va,
1584 gl_shader_stage stage)
1585 {
1586 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1587 uint32_t base_reg = pipeline->user_data_0[stage];
1588
1589 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1590 return;
1591
1592 assert(!desc_set_loc->indirect);
1593 assert(desc_set_loc->num_sgprs == 2);
1594 radeon_set_sh_reg_seq(cmd_buffer->cs,
1595 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1596 radeon_emit(cmd_buffer->cs, va);
1597 radeon_emit(cmd_buffer->cs, va >> 32);
1598 }
1599
1600 static void
1601 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1602 VkShaderStageFlags stages,
1603 struct radv_descriptor_set *set,
1604 unsigned idx)
1605 {
1606 if (cmd_buffer->state.pipeline) {
1607 radv_foreach_stage(stage, stages) {
1608 if (cmd_buffer->state.pipeline->shaders[stage])
1609 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1610 idx, set->va,
1611 stage);
1612 }
1613 }
1614
1615 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1616 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1617 idx, set->va,
1618 MESA_SHADER_COMPUTE);
1619 }
1620
1621 static void
1622 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1623 {
1624 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1625 unsigned bo_offset;
1626
1627 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1628 set->mapped_ptr,
1629 &bo_offset))
1630 return;
1631
1632 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1633 set->va += bo_offset;
1634 }
1635
1636 static void
1637 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1638 {
1639 uint32_t size = MAX_SETS * 2 * 4;
1640 uint32_t offset;
1641 void *ptr;
1642
1643 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1644 256, &offset, &ptr))
1645 return;
1646
1647 for (unsigned i = 0; i < MAX_SETS; i++) {
1648 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1649 uint64_t set_va = 0;
1650 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1651 if (cmd_buffer->state.valid_descriptors & (1u << i))
1652 set_va = set->va;
1653 uptr[0] = set_va & 0xffffffff;
1654 uptr[1] = set_va >> 32;
1655 }
1656
1657 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1658 va += offset;
1659
1660 if (cmd_buffer->state.pipeline) {
1661 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1662 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1663 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1664
1665 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1666 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1667 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1668
1669 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1670 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1671 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1672
1673 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1674 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1675 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1676
1677 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680 }
1681
1682 if (cmd_buffer->state.compute_pipeline)
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685 }
1686
1687 static void
1688 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1689 VkShaderStageFlags stages)
1690 {
1691 unsigned i;
1692
1693 if (!cmd_buffer->state.descriptors_dirty)
1694 return;
1695
1696 if (cmd_buffer->state.push_descriptors_dirty)
1697 radv_flush_push_descriptors(cmd_buffer);
1698
1699 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1700 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1701 radv_flush_indirect_descriptor_sets(cmd_buffer);
1702 }
1703
1704 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1705 cmd_buffer->cs,
1706 MAX_SETS * MESA_SHADER_STAGES * 4);
1707
1708 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1709 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1710 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1711 continue;
1712
1713 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1714 }
1715 cmd_buffer->state.descriptors_dirty = 0;
1716 cmd_buffer->state.push_descriptors_dirty = false;
1717
1718 if (cmd_buffer->device->trace_bo)
1719 radv_save_descriptors(cmd_buffer);
1720
1721 assert(cmd_buffer->cs->cdw <= cdw_max);
1722 }
1723
1724 static void
1725 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1726 struct radv_pipeline *pipeline,
1727 VkShaderStageFlags stages)
1728 {
1729 struct radv_pipeline_layout *layout = pipeline->layout;
1730 unsigned offset;
1731 void *ptr;
1732 uint64_t va;
1733
1734 stages &= cmd_buffer->push_constant_stages;
1735 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1736 return;
1737
1738 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1739 16 * layout->dynamic_offset_count,
1740 256, &offset, &ptr))
1741 return;
1742
1743 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1744 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1745 16 * layout->dynamic_offset_count);
1746
1747 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1748 va += offset;
1749
1750 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1751 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1752
1753 radv_foreach_stage(stage, stages) {
1754 if (pipeline->shaders[stage]) {
1755 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1756 AC_UD_PUSH_CONSTANTS, va);
1757 }
1758 }
1759
1760 cmd_buffer->push_constant_stages &= ~stages;
1761 assert(cmd_buffer->cs->cdw <= cdw_max);
1762 }
1763
1764 static bool
1765 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1766 {
1767 struct radv_device *device = cmd_buffer->device;
1768
1769 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1770 cmd_buffer->state.pipeline->vertex_elements.count &&
1771 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1772 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1773 unsigned vb_offset;
1774 void *vb_ptr;
1775 uint32_t i = 0;
1776 uint32_t count = velems->count;
1777 uint64_t va;
1778
1779 /* allocate some descriptor state for vertex buffers */
1780 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1781 &vb_offset, &vb_ptr))
1782 return false;
1783
1784 for (i = 0; i < count; i++) {
1785 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1786 uint32_t offset;
1787 int vb = velems->binding[i];
1788 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1789 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1790
1791 radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 8);
1792 va = radv_buffer_get_va(buffer->bo);
1793
1794 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1795 va += offset + buffer->offset;
1796 desc[0] = va;
1797 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1798 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1799 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1800 else
1801 desc[2] = buffer->size - offset;
1802 desc[3] = velems->rsrc_word3[i];
1803 }
1804
1805 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1806 va += vb_offset;
1807
1808 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1809 AC_UD_VS_VERTEX_BUFFERS, va);
1810 }
1811 cmd_buffer->state.vb_dirty = false;
1812
1813 return true;
1814 }
1815
1816 static bool
1817 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1818 {
1819 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1820 return false;
1821
1822 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1823 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1824 VK_SHADER_STAGE_ALL_GRAPHICS);
1825
1826 return true;
1827 }
1828
1829 static void
1830 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1831 bool instanced_draw, bool indirect_draw,
1832 uint32_t draw_vertex_count)
1833 {
1834 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1835 struct radv_cmd_state *state = &cmd_buffer->state;
1836 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1837 uint32_t ia_multi_vgt_param;
1838 int32_t primitive_reset_en;
1839
1840 /* Draw state. */
1841 ia_multi_vgt_param =
1842 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1843 indirect_draw, draw_vertex_count);
1844
1845 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1846 if (info->chip_class >= GFX9) {
1847 radeon_set_uconfig_reg_idx(cs,
1848 R_030960_IA_MULTI_VGT_PARAM,
1849 4, ia_multi_vgt_param);
1850 } else if (info->chip_class >= CIK) {
1851 radeon_set_context_reg_idx(cs,
1852 R_028AA8_IA_MULTI_VGT_PARAM,
1853 1, ia_multi_vgt_param);
1854 } else {
1855 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1856 ia_multi_vgt_param);
1857 }
1858 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1859 }
1860
1861 /* Primitive restart. */
1862 primitive_reset_en =
1863 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1864
1865 if (primitive_reset_en != state->last_primitive_reset_en) {
1866 state->last_primitive_reset_en = primitive_reset_en;
1867 if (info->chip_class >= GFX9) {
1868 radeon_set_uconfig_reg(cs,
1869 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1870 primitive_reset_en);
1871 } else {
1872 radeon_set_context_reg(cs,
1873 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1874 primitive_reset_en);
1875 }
1876 }
1877
1878 if (primitive_reset_en) {
1879 uint32_t primitive_reset_index =
1880 state->index_type ? 0xffffffffu : 0xffffu;
1881
1882 if (primitive_reset_index != state->last_primitive_reset_index) {
1883 radeon_set_context_reg(cs,
1884 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1885 primitive_reset_index);
1886 state->last_primitive_reset_index = primitive_reset_index;
1887 }
1888 }
1889 }
1890
1891 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1892 VkPipelineStageFlags src_stage_mask)
1893 {
1894 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1895 VK_PIPELINE_STAGE_TRANSFER_BIT |
1896 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1897 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1898 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1899 }
1900
1901 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1902 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1903 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1904 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1905 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1906 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1907 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1908 VK_PIPELINE_STAGE_TRANSFER_BIT |
1909 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1910 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1911 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1912 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1913 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1914 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1915 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1916 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1917 }
1918 }
1919
1920 static enum radv_cmd_flush_bits
1921 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1922 VkAccessFlags src_flags)
1923 {
1924 enum radv_cmd_flush_bits flush_bits = 0;
1925 uint32_t b;
1926 for_each_bit(b, src_flags) {
1927 switch ((VkAccessFlagBits)(1 << b)) {
1928 case VK_ACCESS_SHADER_WRITE_BIT:
1929 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1930 break;
1931 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1932 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1933 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1934 break;
1935 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1936 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1937 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1938 break;
1939 case VK_ACCESS_TRANSFER_WRITE_BIT:
1940 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1941 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1942 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1943 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1944 RADV_CMD_FLAG_INV_GLOBAL_L2;
1945 break;
1946 default:
1947 break;
1948 }
1949 }
1950 return flush_bits;
1951 }
1952
1953 static enum radv_cmd_flush_bits
1954 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1955 VkAccessFlags dst_flags,
1956 struct radv_image *image)
1957 {
1958 enum radv_cmd_flush_bits flush_bits = 0;
1959 uint32_t b;
1960 for_each_bit(b, dst_flags) {
1961 switch ((VkAccessFlagBits)(1 << b)) {
1962 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1963 case VK_ACCESS_INDEX_READ_BIT:
1964 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1965 break;
1966 case VK_ACCESS_UNIFORM_READ_BIT:
1967 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1968 break;
1969 case VK_ACCESS_SHADER_READ_BIT:
1970 case VK_ACCESS_TRANSFER_READ_BIT:
1971 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1972 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1973 RADV_CMD_FLAG_INV_GLOBAL_L2;
1974 break;
1975 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1976 /* TODO: change to image && when the image gets passed
1977 * through from the subpass. */
1978 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1979 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1980 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1981 break;
1982 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1983 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1985 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1986 break;
1987 default:
1988 break;
1989 }
1990 }
1991 return flush_bits;
1992 }
1993
1994 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1995 {
1996 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1997 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1998 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1999 NULL);
2000 }
2001
2002 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2003 VkAttachmentReference att)
2004 {
2005 unsigned idx = att.attachment;
2006 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2007 VkImageSubresourceRange range;
2008 range.aspectMask = 0;
2009 range.baseMipLevel = view->base_mip;
2010 range.levelCount = 1;
2011 range.baseArrayLayer = view->base_layer;
2012 range.layerCount = cmd_buffer->state.framebuffer->layers;
2013
2014 radv_handle_image_transition(cmd_buffer,
2015 view->image,
2016 cmd_buffer->state.attachments[idx].current_layout,
2017 att.layout, 0, 0, &range,
2018 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2019
2020 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2021
2022
2023 }
2024
2025 void
2026 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2027 const struct radv_subpass *subpass, bool transitions)
2028 {
2029 if (transitions) {
2030 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2031
2032 for (unsigned i = 0; i < subpass->color_count; ++i) {
2033 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2034 radv_handle_subpass_image_transition(cmd_buffer,
2035 subpass->color_attachments[i]);
2036 }
2037
2038 for (unsigned i = 0; i < subpass->input_count; ++i) {
2039 radv_handle_subpass_image_transition(cmd_buffer,
2040 subpass->input_attachments[i]);
2041 }
2042
2043 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2044 radv_handle_subpass_image_transition(cmd_buffer,
2045 subpass->depth_stencil_attachment);
2046 }
2047 }
2048
2049 cmd_buffer->state.subpass = subpass;
2050
2051 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2052 }
2053
2054 static VkResult
2055 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2056 struct radv_render_pass *pass,
2057 const VkRenderPassBeginInfo *info)
2058 {
2059 struct radv_cmd_state *state = &cmd_buffer->state;
2060
2061 if (pass->attachment_count == 0) {
2062 state->attachments = NULL;
2063 return VK_SUCCESS;
2064 }
2065
2066 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2067 pass->attachment_count *
2068 sizeof(state->attachments[0]),
2069 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2070 if (state->attachments == NULL) {
2071 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2072 return cmd_buffer->record_result;
2073 }
2074
2075 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2076 struct radv_render_pass_attachment *att = &pass->attachments[i];
2077 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2078 VkImageAspectFlags clear_aspects = 0;
2079
2080 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2081 /* color attachment */
2082 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2083 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2084 }
2085 } else {
2086 /* depthstencil attachment */
2087 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2088 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2089 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2090 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2091 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2092 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2093 }
2094 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2095 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2096 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2097 }
2098 }
2099
2100 state->attachments[i].pending_clear_aspects = clear_aspects;
2101 state->attachments[i].cleared_views = 0;
2102 if (clear_aspects && info) {
2103 assert(info->clearValueCount > i);
2104 state->attachments[i].clear_value = info->pClearValues[i];
2105 }
2106
2107 state->attachments[i].current_layout = att->initial_layout;
2108 }
2109
2110 return VK_SUCCESS;
2111 }
2112
2113 VkResult radv_AllocateCommandBuffers(
2114 VkDevice _device,
2115 const VkCommandBufferAllocateInfo *pAllocateInfo,
2116 VkCommandBuffer *pCommandBuffers)
2117 {
2118 RADV_FROM_HANDLE(radv_device, device, _device);
2119 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2120
2121 VkResult result = VK_SUCCESS;
2122 uint32_t i;
2123
2124 memset(pCommandBuffers, 0,
2125 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2126
2127 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2128
2129 if (!list_empty(&pool->free_cmd_buffers)) {
2130 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2131
2132 list_del(&cmd_buffer->pool_link);
2133 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2134
2135 result = radv_reset_cmd_buffer(cmd_buffer);
2136 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2137 cmd_buffer->level = pAllocateInfo->level;
2138
2139 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2140 } else {
2141 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2142 &pCommandBuffers[i]);
2143 }
2144 if (result != VK_SUCCESS)
2145 break;
2146 }
2147
2148 if (result != VK_SUCCESS)
2149 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2150 i, pCommandBuffers);
2151
2152 return result;
2153 }
2154
2155 void radv_FreeCommandBuffers(
2156 VkDevice device,
2157 VkCommandPool commandPool,
2158 uint32_t commandBufferCount,
2159 const VkCommandBuffer *pCommandBuffers)
2160 {
2161 for (uint32_t i = 0; i < commandBufferCount; i++) {
2162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2163
2164 if (cmd_buffer) {
2165 if (cmd_buffer->pool) {
2166 list_del(&cmd_buffer->pool_link);
2167 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2168 } else
2169 radv_cmd_buffer_destroy(cmd_buffer);
2170
2171 }
2172 }
2173 }
2174
2175 VkResult radv_ResetCommandBuffer(
2176 VkCommandBuffer commandBuffer,
2177 VkCommandBufferResetFlags flags)
2178 {
2179 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2180 return radv_reset_cmd_buffer(cmd_buffer);
2181 }
2182
2183 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2184 {
2185 struct radv_device *device = cmd_buffer->device;
2186 if (device->gfx_init) {
2187 uint64_t va = radv_buffer_get_va(device->gfx_init);
2188 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2189 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2190 radeon_emit(cmd_buffer->cs, va);
2191 radeon_emit(cmd_buffer->cs, va >> 32);
2192 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2193 } else
2194 si_init_config(cmd_buffer);
2195 }
2196
2197 VkResult radv_BeginCommandBuffer(
2198 VkCommandBuffer commandBuffer,
2199 const VkCommandBufferBeginInfo *pBeginInfo)
2200 {
2201 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2202 VkResult result;
2203
2204 result = radv_reset_cmd_buffer(cmd_buffer);
2205 if (result != VK_SUCCESS)
2206 return result;
2207
2208 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2209 cmd_buffer->state.last_primitive_reset_en = -1;
2210 cmd_buffer->usage_flags = pBeginInfo->flags;
2211
2212 /* setup initial configuration into command buffer */
2213 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2214 switch (cmd_buffer->queue_family_index) {
2215 case RADV_QUEUE_GENERAL:
2216 emit_gfx_buffer_state(cmd_buffer);
2217 break;
2218 case RADV_QUEUE_COMPUTE:
2219 si_init_compute(cmd_buffer);
2220 break;
2221 case RADV_QUEUE_TRANSFER:
2222 default:
2223 break;
2224 }
2225 }
2226
2227 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2228 assert(pBeginInfo->pInheritanceInfo);
2229 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2230 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2231
2232 struct radv_subpass *subpass =
2233 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2234
2235 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2236 if (result != VK_SUCCESS)
2237 return result;
2238
2239 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2240 }
2241
2242 radv_cmd_buffer_trace_emit(cmd_buffer);
2243 return result;
2244 }
2245
2246 void radv_CmdBindVertexBuffers(
2247 VkCommandBuffer commandBuffer,
2248 uint32_t firstBinding,
2249 uint32_t bindingCount,
2250 const VkBuffer* pBuffers,
2251 const VkDeviceSize* pOffsets)
2252 {
2253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2254 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2255 bool changed = false;
2256
2257 /* We have to defer setting up vertex buffer since we need the buffer
2258 * stride from the pipeline. */
2259
2260 assert(firstBinding + bindingCount <= MAX_VBS);
2261 for (uint32_t i = 0; i < bindingCount; i++) {
2262 uint32_t idx = firstBinding + i;
2263
2264 if (!changed &&
2265 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2266 vb[idx].offset != pOffsets[i])) {
2267 changed = true;
2268 }
2269
2270 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2271 vb[idx].offset = pOffsets[i];
2272 }
2273
2274 if (!changed) {
2275 /* No state changes. */
2276 return;
2277 }
2278
2279 cmd_buffer->state.vb_dirty = true;
2280 }
2281
2282 void radv_CmdBindIndexBuffer(
2283 VkCommandBuffer commandBuffer,
2284 VkBuffer buffer,
2285 VkDeviceSize offset,
2286 VkIndexType indexType)
2287 {
2288 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2289 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2290
2291 if (cmd_buffer->state.index_buffer == index_buffer &&
2292 cmd_buffer->state.index_offset == offset &&
2293 cmd_buffer->state.index_type == indexType) {
2294 /* No state changes. */
2295 return;
2296 }
2297
2298 cmd_buffer->state.index_buffer = index_buffer;
2299 cmd_buffer->state.index_offset = offset;
2300 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2301 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2302 cmd_buffer->state.index_va += index_buffer->offset + offset;
2303
2304 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2305 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2306 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2308 }
2309
2310
2311 static void
2312 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2313 struct radv_descriptor_set *set, unsigned idx)
2314 {
2315 struct radeon_winsys *ws = cmd_buffer->device->ws;
2316
2317 radv_set_descriptor_set(cmd_buffer, set, idx);
2318 if (!set)
2319 return;
2320
2321 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2322
2323 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2324 if (set->descriptors[j])
2325 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2326
2327 if(set->bo)
2328 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2329 }
2330
2331 void radv_CmdBindDescriptorSets(
2332 VkCommandBuffer commandBuffer,
2333 VkPipelineBindPoint pipelineBindPoint,
2334 VkPipelineLayout _layout,
2335 uint32_t firstSet,
2336 uint32_t descriptorSetCount,
2337 const VkDescriptorSet* pDescriptorSets,
2338 uint32_t dynamicOffsetCount,
2339 const uint32_t* pDynamicOffsets)
2340 {
2341 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2342 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2343 unsigned dyn_idx = 0;
2344
2345 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2346 unsigned idx = i + firstSet;
2347 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2348 radv_bind_descriptor_set(cmd_buffer, set, idx);
2349
2350 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2351 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2352 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2353 assert(dyn_idx < dynamicOffsetCount);
2354
2355 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2356 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2357 dst[0] = va;
2358 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2359 dst[2] = range->size;
2360 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2364 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2366 cmd_buffer->push_constant_stages |=
2367 set->layout->dynamic_shader_stages;
2368 }
2369 }
2370 }
2371
2372 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2373 struct radv_descriptor_set *set,
2374 struct radv_descriptor_set_layout *layout)
2375 {
2376 set->size = layout->size;
2377 set->layout = layout;
2378
2379 if (cmd_buffer->push_descriptors.capacity < set->size) {
2380 size_t new_size = MAX2(set->size, 1024);
2381 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2382 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2383
2384 free(set->mapped_ptr);
2385 set->mapped_ptr = malloc(new_size);
2386
2387 if (!set->mapped_ptr) {
2388 cmd_buffer->push_descriptors.capacity = 0;
2389 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2390 return false;
2391 }
2392
2393 cmd_buffer->push_descriptors.capacity = new_size;
2394 }
2395
2396 return true;
2397 }
2398
2399 void radv_meta_push_descriptor_set(
2400 struct radv_cmd_buffer* cmd_buffer,
2401 VkPipelineBindPoint pipelineBindPoint,
2402 VkPipelineLayout _layout,
2403 uint32_t set,
2404 uint32_t descriptorWriteCount,
2405 const VkWriteDescriptorSet* pDescriptorWrites)
2406 {
2407 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2408 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2409 unsigned bo_offset;
2410
2411 assert(set == 0);
2412 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2413
2414 push_set->size = layout->set[set].layout->size;
2415 push_set->layout = layout->set[set].layout;
2416
2417 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2418 &bo_offset,
2419 (void**) &push_set->mapped_ptr))
2420 return;
2421
2422 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2423 push_set->va += bo_offset;
2424
2425 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2426 radv_descriptor_set_to_handle(push_set),
2427 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2428
2429 radv_set_descriptor_set(cmd_buffer, push_set, set);
2430 }
2431
2432 void radv_CmdPushDescriptorSetKHR(
2433 VkCommandBuffer commandBuffer,
2434 VkPipelineBindPoint pipelineBindPoint,
2435 VkPipelineLayout _layout,
2436 uint32_t set,
2437 uint32_t descriptorWriteCount,
2438 const VkWriteDescriptorSet* pDescriptorWrites)
2439 {
2440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2441 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2442 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2443
2444 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2445
2446 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2447 return;
2448
2449 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2450 radv_descriptor_set_to_handle(push_set),
2451 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2452
2453 radv_set_descriptor_set(cmd_buffer, push_set, set);
2454 cmd_buffer->state.push_descriptors_dirty = true;
2455 }
2456
2457 void radv_CmdPushDescriptorSetWithTemplateKHR(
2458 VkCommandBuffer commandBuffer,
2459 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2460 VkPipelineLayout _layout,
2461 uint32_t set,
2462 const void* pData)
2463 {
2464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2465 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2466 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2467
2468 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2469
2470 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2471 return;
2472
2473 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2474 descriptorUpdateTemplate, pData);
2475
2476 radv_set_descriptor_set(cmd_buffer, push_set, set);
2477 cmd_buffer->state.push_descriptors_dirty = true;
2478 }
2479
2480 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2481 VkPipelineLayout layout,
2482 VkShaderStageFlags stageFlags,
2483 uint32_t offset,
2484 uint32_t size,
2485 const void* pValues)
2486 {
2487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2488 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2489 cmd_buffer->push_constant_stages |= stageFlags;
2490 }
2491
2492 VkResult radv_EndCommandBuffer(
2493 VkCommandBuffer commandBuffer)
2494 {
2495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2496
2497 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2498 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2499 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2500 si_emit_cache_flush(cmd_buffer);
2501 }
2502
2503 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2504
2505 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2506 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2507
2508 return cmd_buffer->record_result;
2509 }
2510
2511 static void
2512 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2513 {
2514 struct radv_shader_variant *compute_shader;
2515 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2516 uint64_t va;
2517
2518 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2519 return;
2520
2521 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2522
2523 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2524 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2525
2526 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2527 cmd_buffer->cs, 16);
2528
2529 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2530 radeon_emit(cmd_buffer->cs, va >> 8);
2531 radeon_emit(cmd_buffer->cs, va >> 40);
2532
2533 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2534 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2535 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2536
2537
2538 cmd_buffer->compute_scratch_size_needed =
2539 MAX2(cmd_buffer->compute_scratch_size_needed,
2540 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2541
2542 /* change these once we have scratch support */
2543 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2544 S_00B860_WAVES(pipeline->max_waves) |
2545 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2546
2547 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2548 radeon_emit(cmd_buffer->cs,
2549 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2550 radeon_emit(cmd_buffer->cs,
2551 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2552 radeon_emit(cmd_buffer->cs,
2553 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2554
2555 assert(cmd_buffer->cs->cdw <= cdw_max);
2556 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2557 }
2558
2559 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2560 {
2561 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2562 }
2563
2564 void radv_CmdBindPipeline(
2565 VkCommandBuffer commandBuffer,
2566 VkPipelineBindPoint pipelineBindPoint,
2567 VkPipeline _pipeline)
2568 {
2569 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2570 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2571
2572 switch (pipelineBindPoint) {
2573 case VK_PIPELINE_BIND_POINT_COMPUTE:
2574 if (cmd_buffer->state.compute_pipeline == pipeline)
2575 return;
2576 radv_mark_descriptor_sets_dirty(cmd_buffer);
2577
2578 cmd_buffer->state.compute_pipeline = pipeline;
2579 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2580 break;
2581 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2582 if (cmd_buffer->state.pipeline == pipeline)
2583 return;
2584 radv_mark_descriptor_sets_dirty(cmd_buffer);
2585
2586 cmd_buffer->state.pipeline = pipeline;
2587 if (!pipeline)
2588 break;
2589
2590 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2591 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2592
2593 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2594
2595 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2596 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2597 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2598 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2599
2600 if (radv_pipeline_has_tess(pipeline))
2601 cmd_buffer->tess_rings_needed = true;
2602
2603 if (radv_pipeline_has_gs(pipeline)) {
2604 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2605 AC_UD_SCRATCH_RING_OFFSETS);
2606 if (cmd_buffer->ring_offsets_idx == -1)
2607 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2608 else if (loc->sgpr_idx != -1)
2609 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2610 }
2611 break;
2612 default:
2613 assert(!"invalid bind point");
2614 break;
2615 }
2616 }
2617
2618 void radv_CmdSetViewport(
2619 VkCommandBuffer commandBuffer,
2620 uint32_t firstViewport,
2621 uint32_t viewportCount,
2622 const VkViewport* pViewports)
2623 {
2624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2625 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2626
2627 assert(firstViewport < MAX_VIEWPORTS);
2628 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2629
2630 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2631 pViewports, viewportCount * sizeof(*pViewports));
2632
2633 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2634 }
2635
2636 void radv_CmdSetScissor(
2637 VkCommandBuffer commandBuffer,
2638 uint32_t firstScissor,
2639 uint32_t scissorCount,
2640 const VkRect2D* pScissors)
2641 {
2642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2643 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2644
2645 assert(firstScissor < MAX_SCISSORS);
2646 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2647
2648 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2649 pScissors, scissorCount * sizeof(*pScissors));
2650 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2651 }
2652
2653 void radv_CmdSetLineWidth(
2654 VkCommandBuffer commandBuffer,
2655 float lineWidth)
2656 {
2657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2658 cmd_buffer->state.dynamic.line_width = lineWidth;
2659 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2660 }
2661
2662 void radv_CmdSetDepthBias(
2663 VkCommandBuffer commandBuffer,
2664 float depthBiasConstantFactor,
2665 float depthBiasClamp,
2666 float depthBiasSlopeFactor)
2667 {
2668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2669
2670 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2671 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2672 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2673
2674 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2675 }
2676
2677 void radv_CmdSetBlendConstants(
2678 VkCommandBuffer commandBuffer,
2679 const float blendConstants[4])
2680 {
2681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2682
2683 memcpy(cmd_buffer->state.dynamic.blend_constants,
2684 blendConstants, sizeof(float) * 4);
2685
2686 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2687 }
2688
2689 void radv_CmdSetDepthBounds(
2690 VkCommandBuffer commandBuffer,
2691 float minDepthBounds,
2692 float maxDepthBounds)
2693 {
2694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2695
2696 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2697 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2698
2699 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2700 }
2701
2702 void radv_CmdSetStencilCompareMask(
2703 VkCommandBuffer commandBuffer,
2704 VkStencilFaceFlags faceMask,
2705 uint32_t compareMask)
2706 {
2707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2708
2709 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2710 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2711 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2712 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2713
2714 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2715 }
2716
2717 void radv_CmdSetStencilWriteMask(
2718 VkCommandBuffer commandBuffer,
2719 VkStencilFaceFlags faceMask,
2720 uint32_t writeMask)
2721 {
2722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2723
2724 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2725 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2726 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2727 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2728
2729 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2730 }
2731
2732 void radv_CmdSetStencilReference(
2733 VkCommandBuffer commandBuffer,
2734 VkStencilFaceFlags faceMask,
2735 uint32_t reference)
2736 {
2737 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2738
2739 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2740 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2741 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2742 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2743
2744 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2745 }
2746
2747 void radv_CmdExecuteCommands(
2748 VkCommandBuffer commandBuffer,
2749 uint32_t commandBufferCount,
2750 const VkCommandBuffer* pCmdBuffers)
2751 {
2752 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2753
2754 assert(commandBufferCount > 0);
2755
2756 /* Emit pending flushes on primary prior to executing secondary */
2757 si_emit_cache_flush(primary);
2758
2759 for (uint32_t i = 0; i < commandBufferCount; i++) {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2761
2762 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2763 secondary->scratch_size_needed);
2764 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2765 secondary->compute_scratch_size_needed);
2766
2767 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2768 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2769 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2770 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2771 if (secondary->tess_rings_needed)
2772 primary->tess_rings_needed = true;
2773 if (secondary->sample_positions_needed)
2774 primary->sample_positions_needed = true;
2775
2776 if (secondary->ring_offsets_idx != -1) {
2777 if (primary->ring_offsets_idx == -1)
2778 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2779 else
2780 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2781 }
2782 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2783
2784
2785 /* When the secondary command buffer is compute only we don't
2786 * need to re-emit the current graphics pipeline.
2787 */
2788 if (secondary->state.emitted_pipeline) {
2789 primary->state.emitted_pipeline =
2790 secondary->state.emitted_pipeline;
2791 }
2792
2793 /* When the secondary command buffer is graphics only we don't
2794 * need to re-emit the current compute pipeline.
2795 */
2796 if (secondary->state.emitted_compute_pipeline) {
2797 primary->state.emitted_compute_pipeline =
2798 secondary->state.emitted_compute_pipeline;
2799 }
2800
2801 /* Only re-emit the draw packets when needed. */
2802 if (secondary->state.last_primitive_reset_en != -1) {
2803 primary->state.last_primitive_reset_en =
2804 secondary->state.last_primitive_reset_en;
2805 }
2806
2807 if (secondary->state.last_primitive_reset_index) {
2808 primary->state.last_primitive_reset_index =
2809 secondary->state.last_primitive_reset_index;
2810 }
2811
2812 if (secondary->state.last_ia_multi_vgt_param) {
2813 primary->state.last_ia_multi_vgt_param =
2814 secondary->state.last_ia_multi_vgt_param;
2815 }
2816 }
2817
2818 /* After executing commands from secondary buffers we have to dirty
2819 * some states.
2820 */
2821 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2822 RADV_CMD_DIRTY_INDEX_BUFFER |
2823 RADV_CMD_DIRTY_DYNAMIC_ALL;
2824 radv_mark_descriptor_sets_dirty(primary);
2825 }
2826
2827 VkResult radv_CreateCommandPool(
2828 VkDevice _device,
2829 const VkCommandPoolCreateInfo* pCreateInfo,
2830 const VkAllocationCallbacks* pAllocator,
2831 VkCommandPool* pCmdPool)
2832 {
2833 RADV_FROM_HANDLE(radv_device, device, _device);
2834 struct radv_cmd_pool *pool;
2835
2836 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2837 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2838 if (pool == NULL)
2839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2840
2841 if (pAllocator)
2842 pool->alloc = *pAllocator;
2843 else
2844 pool->alloc = device->alloc;
2845
2846 list_inithead(&pool->cmd_buffers);
2847 list_inithead(&pool->free_cmd_buffers);
2848
2849 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2850
2851 *pCmdPool = radv_cmd_pool_to_handle(pool);
2852
2853 return VK_SUCCESS;
2854
2855 }
2856
2857 void radv_DestroyCommandPool(
2858 VkDevice _device,
2859 VkCommandPool commandPool,
2860 const VkAllocationCallbacks* pAllocator)
2861 {
2862 RADV_FROM_HANDLE(radv_device, device, _device);
2863 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2864
2865 if (!pool)
2866 return;
2867
2868 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2869 &pool->cmd_buffers, pool_link) {
2870 radv_cmd_buffer_destroy(cmd_buffer);
2871 }
2872
2873 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2874 &pool->free_cmd_buffers, pool_link) {
2875 radv_cmd_buffer_destroy(cmd_buffer);
2876 }
2877
2878 vk_free2(&device->alloc, pAllocator, pool);
2879 }
2880
2881 VkResult radv_ResetCommandPool(
2882 VkDevice device,
2883 VkCommandPool commandPool,
2884 VkCommandPoolResetFlags flags)
2885 {
2886 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2887 VkResult result;
2888
2889 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2890 &pool->cmd_buffers, pool_link) {
2891 result = radv_reset_cmd_buffer(cmd_buffer);
2892 if (result != VK_SUCCESS)
2893 return result;
2894 }
2895
2896 return VK_SUCCESS;
2897 }
2898
2899 void radv_TrimCommandPoolKHR(
2900 VkDevice device,
2901 VkCommandPool commandPool,
2902 VkCommandPoolTrimFlagsKHR flags)
2903 {
2904 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2905
2906 if (!pool)
2907 return;
2908
2909 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2910 &pool->free_cmd_buffers, pool_link) {
2911 radv_cmd_buffer_destroy(cmd_buffer);
2912 }
2913 }
2914
2915 void radv_CmdBeginRenderPass(
2916 VkCommandBuffer commandBuffer,
2917 const VkRenderPassBeginInfo* pRenderPassBegin,
2918 VkSubpassContents contents)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2922 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2923
2924 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2925 cmd_buffer->cs, 2048);
2926 MAYBE_UNUSED VkResult result;
2927
2928 cmd_buffer->state.framebuffer = framebuffer;
2929 cmd_buffer->state.pass = pass;
2930 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2931
2932 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2933 if (result != VK_SUCCESS)
2934 return;
2935
2936 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2937 assert(cmd_buffer->cs->cdw <= cdw_max);
2938
2939 radv_cmd_buffer_clear_subpass(cmd_buffer);
2940 }
2941
2942 void radv_CmdNextSubpass(
2943 VkCommandBuffer commandBuffer,
2944 VkSubpassContents contents)
2945 {
2946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2947
2948 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2949
2950 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2951 2048);
2952
2953 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2954 radv_cmd_buffer_clear_subpass(cmd_buffer);
2955 }
2956
2957 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2958 {
2959 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2960 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2961 if (!pipeline->shaders[stage])
2962 continue;
2963 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2964 if (loc->sgpr_idx == -1)
2965 continue;
2966 uint32_t base_reg = pipeline->user_data_0[stage];
2967 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2968
2969 }
2970 if (pipeline->gs_copy_shader) {
2971 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2972 if (loc->sgpr_idx != -1) {
2973 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2974 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2975 }
2976 }
2977 }
2978
2979 static void
2980 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2981 uint32_t vertex_count)
2982 {
2983 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2984 radeon_emit(cmd_buffer->cs, vertex_count);
2985 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2986 S_0287F0_USE_OPAQUE(0));
2987 }
2988
2989 static void
2990 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2991 uint64_t index_va,
2992 uint32_t index_count)
2993 {
2994 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2995 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2996 radeon_emit(cmd_buffer->cs, index_va);
2997 radeon_emit(cmd_buffer->cs, index_va >> 32);
2998 radeon_emit(cmd_buffer->cs, index_count);
2999 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3000 }
3001
3002 static void
3003 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3004 bool indexed,
3005 uint32_t draw_count,
3006 uint64_t count_va,
3007 uint32_t stride)
3008 {
3009 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3010 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3011 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3012 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3013 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3014 assert(base_reg);
3015
3016 if (draw_count == 1 && !count_va && !draw_id_enable) {
3017 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3018 PKT3_DRAW_INDIRECT, 3, false));
3019 radeon_emit(cs, 0);
3020 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3021 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3022 radeon_emit(cs, di_src_sel);
3023 } else {
3024 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3025 PKT3_DRAW_INDIRECT_MULTI,
3026 8, false));
3027 radeon_emit(cs, 0);
3028 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3029 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3030 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3031 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3032 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3033 radeon_emit(cs, draw_count); /* count */
3034 radeon_emit(cs, count_va); /* count_addr */
3035 radeon_emit(cs, count_va >> 32);
3036 radeon_emit(cs, stride); /* stride */
3037 radeon_emit(cs, di_src_sel);
3038 }
3039 }
3040
3041 struct radv_draw_info {
3042 /**
3043 * Number of vertices.
3044 */
3045 uint32_t count;
3046
3047 /**
3048 * Index of the first vertex.
3049 */
3050 int32_t vertex_offset;
3051
3052 /**
3053 * First instance id.
3054 */
3055 uint32_t first_instance;
3056
3057 /**
3058 * Number of instances.
3059 */
3060 uint32_t instance_count;
3061
3062 /**
3063 * First index (indexed draws only).
3064 */
3065 uint32_t first_index;
3066
3067 /**
3068 * Whether it's an indexed draw.
3069 */
3070 bool indexed;
3071
3072 /**
3073 * Indirect draw parameters resource.
3074 */
3075 struct radv_buffer *indirect;
3076 uint64_t indirect_offset;
3077 uint32_t stride;
3078
3079 /**
3080 * Draw count parameters resource.
3081 */
3082 struct radv_buffer *count_buffer;
3083 uint64_t count_buffer_offset;
3084 };
3085
3086 static void
3087 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3088 const struct radv_draw_info *info)
3089 {
3090 struct radv_cmd_state *state = &cmd_buffer->state;
3091 struct radeon_winsys *ws = cmd_buffer->device->ws;
3092 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3093
3094 if (info->indirect) {
3095 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3096 uint64_t count_va = 0;
3097
3098 va += info->indirect->offset + info->indirect_offset;
3099
3100 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3101
3102 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3103 radeon_emit(cs, 1);
3104 radeon_emit(cs, va);
3105 radeon_emit(cs, va >> 32);
3106
3107 if (info->count_buffer) {
3108 count_va = radv_buffer_get_va(info->count_buffer->bo);
3109 count_va += info->count_buffer->offset +
3110 info->count_buffer_offset;
3111
3112 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3113 }
3114
3115 if (!state->subpass->view_mask) {
3116 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3117 info->indexed,
3118 info->count,
3119 count_va,
3120 info->stride);
3121 } else {
3122 unsigned i;
3123 for_each_bit(i, state->subpass->view_mask) {
3124 radv_emit_view_index(cmd_buffer, i);
3125
3126 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3127 info->indexed,
3128 info->count,
3129 count_va,
3130 info->stride);
3131 }
3132 }
3133 } else {
3134 assert(state->pipeline->graphics.vtx_base_sgpr);
3135 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3136 state->pipeline->graphics.vtx_emit_num);
3137 radeon_emit(cs, info->vertex_offset);
3138 radeon_emit(cs, info->first_instance);
3139 if (state->pipeline->graphics.vtx_emit_num == 3)
3140 radeon_emit(cs, 0);
3141
3142 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3143 radeon_emit(cs, info->instance_count);
3144
3145 if (info->indexed) {
3146 int index_size = state->index_type ? 4 : 2;
3147 uint64_t index_va;
3148
3149 index_va = state->index_va;
3150 index_va += info->first_index * index_size;
3151
3152 if (!state->subpass->view_mask) {
3153 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3154 index_va,
3155 info->count);
3156 } else {
3157 unsigned i;
3158 for_each_bit(i, state->subpass->view_mask) {
3159 radv_emit_view_index(cmd_buffer, i);
3160
3161 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3162 index_va,
3163 info->count);
3164 }
3165 }
3166 } else {
3167 if (!state->subpass->view_mask) {
3168 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3169 } else {
3170 unsigned i;
3171 for_each_bit(i, state->subpass->view_mask) {
3172 radv_emit_view_index(cmd_buffer, i);
3173
3174 radv_cs_emit_draw_packet(cmd_buffer,
3175 info->count);
3176 }
3177 }
3178 }
3179 }
3180 }
3181
3182 static void
3183 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3184 const struct radv_draw_info *info)
3185 {
3186 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3187 radv_emit_graphics_pipeline(cmd_buffer);
3188
3189 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3190 radv_emit_framebuffer_state(cmd_buffer);
3191
3192 if (info->indexed) {
3193 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3194 radv_emit_index_buffer(cmd_buffer);
3195 } else {
3196 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3197 * so the state must be re-emitted before the next indexed
3198 * draw.
3199 */
3200 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3201 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3202 }
3203
3204 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3205
3206 radv_emit_draw_registers(cmd_buffer, info->indexed,
3207 info->instance_count > 1, info->indirect,
3208 info->indirect ? 0 : info->count);
3209 }
3210
3211 static void
3212 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3213 const struct radv_draw_info *info)
3214 {
3215 bool pipeline_is_dirty =
3216 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3217 cmd_buffer->state.pipeline &&
3218 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3219
3220 MAYBE_UNUSED unsigned cdw_max =
3221 radeon_check_space(cmd_buffer->device->ws,
3222 cmd_buffer->cs, 4096);
3223
3224 /* Use optimal packet order based on whether we need to sync the
3225 * pipeline.
3226 */
3227 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3228 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3229 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3230 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3231 /* If we have to wait for idle, set all states first, so that
3232 * all SET packets are processed in parallel with previous draw
3233 * calls. Then upload descriptors, set shader pointers, and
3234 * draw, and prefetch at the end. This ensures that the time
3235 * the CUs are idle is very short. (there are only SET_SH
3236 * packets between the wait and the draw)
3237 */
3238 radv_emit_all_graphics_states(cmd_buffer, info);
3239 si_emit_cache_flush(cmd_buffer);
3240 /* <-- CUs are idle here --> */
3241
3242 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3243 return;
3244
3245 radv_emit_draw_packets(cmd_buffer, info);
3246 /* <-- CUs are busy here --> */
3247
3248 /* Start prefetches after the draw has been started. Both will
3249 * run in parallel, but starting the draw first is more
3250 * important.
3251 */
3252 if (pipeline_is_dirty) {
3253 radv_emit_prefetch(cmd_buffer,
3254 cmd_buffer->state.pipeline);
3255 }
3256 } else {
3257 /* If we don't wait for idle, start prefetches first, then set
3258 * states, and draw at the end.
3259 */
3260 si_emit_cache_flush(cmd_buffer);
3261
3262 if (pipeline_is_dirty) {
3263 radv_emit_prefetch(cmd_buffer,
3264 cmd_buffer->state.pipeline);
3265 }
3266
3267 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3268 return;
3269
3270 radv_emit_all_graphics_states(cmd_buffer, info);
3271 radv_emit_draw_packets(cmd_buffer, info);
3272 }
3273
3274 assert(cmd_buffer->cs->cdw <= cdw_max);
3275 radv_cmd_buffer_after_draw(cmd_buffer);
3276 }
3277
3278 void radv_CmdDraw(
3279 VkCommandBuffer commandBuffer,
3280 uint32_t vertexCount,
3281 uint32_t instanceCount,
3282 uint32_t firstVertex,
3283 uint32_t firstInstance)
3284 {
3285 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3286 struct radv_draw_info info = {};
3287
3288 info.count = vertexCount;
3289 info.instance_count = instanceCount;
3290 info.first_instance = firstInstance;
3291 info.vertex_offset = firstVertex;
3292
3293 radv_draw(cmd_buffer, &info);
3294 }
3295
3296 void radv_CmdDrawIndexed(
3297 VkCommandBuffer commandBuffer,
3298 uint32_t indexCount,
3299 uint32_t instanceCount,
3300 uint32_t firstIndex,
3301 int32_t vertexOffset,
3302 uint32_t firstInstance)
3303 {
3304 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3305 struct radv_draw_info info = {};
3306
3307 info.indexed = true;
3308 info.count = indexCount;
3309 info.instance_count = instanceCount;
3310 info.first_index = firstIndex;
3311 info.vertex_offset = vertexOffset;
3312 info.first_instance = firstInstance;
3313
3314 radv_draw(cmd_buffer, &info);
3315 }
3316
3317 void radv_CmdDrawIndirect(
3318 VkCommandBuffer commandBuffer,
3319 VkBuffer _buffer,
3320 VkDeviceSize offset,
3321 uint32_t drawCount,
3322 uint32_t stride)
3323 {
3324 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3325 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3326 struct radv_draw_info info = {};
3327
3328 info.count = drawCount;
3329 info.indirect = buffer;
3330 info.indirect_offset = offset;
3331 info.stride = stride;
3332
3333 radv_draw(cmd_buffer, &info);
3334 }
3335
3336 void radv_CmdDrawIndexedIndirect(
3337 VkCommandBuffer commandBuffer,
3338 VkBuffer _buffer,
3339 VkDeviceSize offset,
3340 uint32_t drawCount,
3341 uint32_t stride)
3342 {
3343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3344 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3345 struct radv_draw_info info = {};
3346
3347 info.indexed = true;
3348 info.count = drawCount;
3349 info.indirect = buffer;
3350 info.indirect_offset = offset;
3351 info.stride = stride;
3352
3353 radv_draw(cmd_buffer, &info);
3354 }
3355
3356 void radv_CmdDrawIndirectCountAMD(
3357 VkCommandBuffer commandBuffer,
3358 VkBuffer _buffer,
3359 VkDeviceSize offset,
3360 VkBuffer _countBuffer,
3361 VkDeviceSize countBufferOffset,
3362 uint32_t maxDrawCount,
3363 uint32_t stride)
3364 {
3365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3366 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3367 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3368 struct radv_draw_info info = {};
3369
3370 info.count = maxDrawCount;
3371 info.indirect = buffer;
3372 info.indirect_offset = offset;
3373 info.count_buffer = count_buffer;
3374 info.count_buffer_offset = countBufferOffset;
3375 info.stride = stride;
3376
3377 radv_draw(cmd_buffer, &info);
3378 }
3379
3380 void radv_CmdDrawIndexedIndirectCountAMD(
3381 VkCommandBuffer commandBuffer,
3382 VkBuffer _buffer,
3383 VkDeviceSize offset,
3384 VkBuffer _countBuffer,
3385 VkDeviceSize countBufferOffset,
3386 uint32_t maxDrawCount,
3387 uint32_t stride)
3388 {
3389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3390 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3391 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3392 struct radv_draw_info info = {};
3393
3394 info.indexed = true;
3395 info.count = maxDrawCount;
3396 info.indirect = buffer;
3397 info.indirect_offset = offset;
3398 info.count_buffer = count_buffer;
3399 info.count_buffer_offset = countBufferOffset;
3400 info.stride = stride;
3401
3402 radv_draw(cmd_buffer, &info);
3403 }
3404
3405 struct radv_dispatch_info {
3406 /**
3407 * Determine the layout of the grid (in block units) to be used.
3408 */
3409 uint32_t blocks[3];
3410
3411 /**
3412 * Whether it's an unaligned compute dispatch.
3413 */
3414 bool unaligned;
3415
3416 /**
3417 * Indirect compute parameters resource.
3418 */
3419 struct radv_buffer *indirect;
3420 uint64_t indirect_offset;
3421 };
3422
3423 static void
3424 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3425 const struct radv_dispatch_info *info)
3426 {
3427 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3428 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3429 struct radeon_winsys *ws = cmd_buffer->device->ws;
3430 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3431 struct ac_userdata_info *loc;
3432 unsigned dispatch_initiator;
3433 uint8_t grid_used;
3434
3435 grid_used = compute_shader->info.info.cs.grid_components_used;
3436
3437 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3438 AC_UD_CS_GRID_SIZE);
3439
3440 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3441
3442 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3443 S_00B800_FORCE_START_AT_000(1);
3444
3445 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3446 /* If the KMD allows it (there is a KMD hw register for it),
3447 * allow launching waves out-of-order.
3448 */
3449 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3450 }
3451
3452 if (info->indirect) {
3453 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3454
3455 va += info->indirect->offset + info->indirect_offset;
3456
3457 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3458
3459 if (loc->sgpr_idx != -1) {
3460 for (unsigned i = 0; i < grid_used; ++i) {
3461 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3462 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3463 COPY_DATA_DST_SEL(COPY_DATA_REG));
3464 radeon_emit(cs, (va + 4 * i));
3465 radeon_emit(cs, (va + 4 * i) >> 32);
3466 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3467 + loc->sgpr_idx * 4) >> 2) + i);
3468 radeon_emit(cs, 0);
3469 }
3470 }
3471
3472 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3473 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3474 PKT3_SHADER_TYPE_S(1));
3475 radeon_emit(cs, va);
3476 radeon_emit(cs, va >> 32);
3477 radeon_emit(cs, dispatch_initiator);
3478 } else {
3479 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3480 PKT3_SHADER_TYPE_S(1));
3481 radeon_emit(cs, 1);
3482 radeon_emit(cs, va);
3483 radeon_emit(cs, va >> 32);
3484
3485 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3486 PKT3_SHADER_TYPE_S(1));
3487 radeon_emit(cs, 0);
3488 radeon_emit(cs, dispatch_initiator);
3489 }
3490 } else {
3491 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3492
3493 if (info->unaligned) {
3494 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3495 unsigned remainder[3];
3496
3497 /* If aligned, these should be an entire block size,
3498 * not 0.
3499 */
3500 remainder[0] = blocks[0] + cs_block_size[0] -
3501 align_u32_npot(blocks[0], cs_block_size[0]);
3502 remainder[1] = blocks[1] + cs_block_size[1] -
3503 align_u32_npot(blocks[1], cs_block_size[1]);
3504 remainder[2] = blocks[2] + cs_block_size[2] -
3505 align_u32_npot(blocks[2], cs_block_size[2]);
3506
3507 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3508 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3509 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3510
3511 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3512 radeon_emit(cs,
3513 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3514 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3515 radeon_emit(cs,
3516 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3517 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3518 radeon_emit(cs,
3519 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3520 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3521
3522 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3523 }
3524
3525 if (loc->sgpr_idx != -1) {
3526 assert(!loc->indirect);
3527 assert(loc->num_sgprs == grid_used);
3528
3529 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3530 loc->sgpr_idx * 4, grid_used);
3531 radeon_emit(cs, blocks[0]);
3532 if (grid_used > 1)
3533 radeon_emit(cs, blocks[1]);
3534 if (grid_used > 2)
3535 radeon_emit(cs, blocks[2]);
3536 }
3537
3538 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3539 PKT3_SHADER_TYPE_S(1));
3540 radeon_emit(cs, blocks[0]);
3541 radeon_emit(cs, blocks[1]);
3542 radeon_emit(cs, blocks[2]);
3543 radeon_emit(cs, dispatch_initiator);
3544 }
3545
3546 assert(cmd_buffer->cs->cdw <= cdw_max);
3547 }
3548
3549 static void
3550 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3551 {
3552 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3553 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3554 VK_SHADER_STAGE_COMPUTE_BIT);
3555 }
3556
3557 static void
3558 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3559 const struct radv_dispatch_info *info)
3560 {
3561 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3562 bool pipeline_is_dirty = pipeline &&
3563 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3564
3565 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3566 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3567 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3568 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3569 /* If we have to wait for idle, set all states first, so that
3570 * all SET packets are processed in parallel with previous draw
3571 * calls. Then upload descriptors, set shader pointers, and
3572 * dispatch, and prefetch at the end. This ensures that the
3573 * time the CUs are idle is very short. (there are only SET_SH
3574 * packets between the wait and the draw)
3575 */
3576 radv_emit_compute_pipeline(cmd_buffer);
3577 si_emit_cache_flush(cmd_buffer);
3578 /* <-- CUs are idle here --> */
3579
3580 radv_upload_compute_shader_descriptors(cmd_buffer);
3581
3582 radv_emit_dispatch_packets(cmd_buffer, info);
3583 /* <-- CUs are busy here --> */
3584
3585 /* Start prefetches after the dispatch has been started. Both
3586 * will run in parallel, but starting the dispatch first is
3587 * more important.
3588 */
3589 if (pipeline_is_dirty) {
3590 radv_emit_shader_prefetch(cmd_buffer,
3591 pipeline->shaders[MESA_SHADER_COMPUTE]);
3592 }
3593 } else {
3594 /* If we don't wait for idle, start prefetches first, then set
3595 * states, and dispatch at the end.
3596 */
3597 si_emit_cache_flush(cmd_buffer);
3598
3599 if (pipeline_is_dirty) {
3600 radv_emit_shader_prefetch(cmd_buffer,
3601 pipeline->shaders[MESA_SHADER_COMPUTE]);
3602 }
3603
3604 radv_upload_compute_shader_descriptors(cmd_buffer);
3605
3606 radv_emit_compute_pipeline(cmd_buffer);
3607 radv_emit_dispatch_packets(cmd_buffer, info);
3608 }
3609
3610 radv_cmd_buffer_after_draw(cmd_buffer);
3611 }
3612
3613 void radv_CmdDispatch(
3614 VkCommandBuffer commandBuffer,
3615 uint32_t x,
3616 uint32_t y,
3617 uint32_t z)
3618 {
3619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3620 struct radv_dispatch_info info = {};
3621
3622 info.blocks[0] = x;
3623 info.blocks[1] = y;
3624 info.blocks[2] = z;
3625
3626 radv_dispatch(cmd_buffer, &info);
3627 }
3628
3629 void radv_CmdDispatchIndirect(
3630 VkCommandBuffer commandBuffer,
3631 VkBuffer _buffer,
3632 VkDeviceSize offset)
3633 {
3634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3635 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3636 struct radv_dispatch_info info = {};
3637
3638 info.indirect = buffer;
3639 info.indirect_offset = offset;
3640
3641 radv_dispatch(cmd_buffer, &info);
3642 }
3643
3644 void radv_unaligned_dispatch(
3645 struct radv_cmd_buffer *cmd_buffer,
3646 uint32_t x,
3647 uint32_t y,
3648 uint32_t z)
3649 {
3650 struct radv_dispatch_info info = {};
3651
3652 info.blocks[0] = x;
3653 info.blocks[1] = y;
3654 info.blocks[2] = z;
3655 info.unaligned = 1;
3656
3657 radv_dispatch(cmd_buffer, &info);
3658 }
3659
3660 void radv_CmdEndRenderPass(
3661 VkCommandBuffer commandBuffer)
3662 {
3663 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3664
3665 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3666
3667 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3668
3669 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3670 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3671 radv_handle_subpass_image_transition(cmd_buffer,
3672 (VkAttachmentReference){i, layout});
3673 }
3674
3675 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3676
3677 cmd_buffer->state.pass = NULL;
3678 cmd_buffer->state.subpass = NULL;
3679 cmd_buffer->state.attachments = NULL;
3680 cmd_buffer->state.framebuffer = NULL;
3681 }
3682
3683 /*
3684 * For HTILE we have the following interesting clear words:
3685 * 0x0000030f: Uncompressed.
3686 * 0xfffffff0: Clear depth to 1.0
3687 * 0x00000000: Clear depth to 0.0
3688 */
3689 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3690 struct radv_image *image,
3691 const VkImageSubresourceRange *range,
3692 uint32_t clear_word)
3693 {
3694 assert(range->baseMipLevel == 0);
3695 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3696 unsigned layer_count = radv_get_layerCount(image, range);
3697 uint64_t size = image->surface.htile_slice_size * layer_count;
3698 uint64_t offset = image->offset + image->htile_offset +
3699 image->surface.htile_slice_size * range->baseArrayLayer;
3700 struct radv_cmd_state *state = &cmd_buffer->state;
3701
3702 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3703 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3704
3705 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3706 size, clear_word);
3707
3708 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3709 }
3710
3711 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3712 struct radv_image *image,
3713 VkImageLayout src_layout,
3714 VkImageLayout dst_layout,
3715 unsigned src_queue_mask,
3716 unsigned dst_queue_mask,
3717 const VkImageSubresourceRange *range,
3718 VkImageAspectFlags pending_clears)
3719 {
3720 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3721 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3722 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3723 cmd_buffer->state.render_area.extent.width == image->info.width &&
3724 cmd_buffer->state.render_area.extent.height == image->info.height) {
3725 /* The clear will initialize htile. */
3726 return;
3727 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3728 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3729 /* TODO: merge with the clear if applicable */
3730 radv_initialize_htile(cmd_buffer, image, range, 0);
3731 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3732 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3733 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3734 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3735 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3736 VkImageSubresourceRange local_range = *range;
3737 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3738 local_range.baseMipLevel = 0;
3739 local_range.levelCount = 1;
3740
3741 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3742 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3743
3744 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3745
3746 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3747 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3748 }
3749 }
3750
3751 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3752 struct radv_image *image, uint32_t value)
3753 {
3754 struct radv_cmd_state *state = &cmd_buffer->state;
3755
3756 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3757 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3758
3759 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3760 image->offset + image->cmask.offset,
3761 image->cmask.size, value);
3762
3763 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3764 }
3765
3766 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3767 struct radv_image *image,
3768 VkImageLayout src_layout,
3769 VkImageLayout dst_layout,
3770 unsigned src_queue_mask,
3771 unsigned dst_queue_mask,
3772 const VkImageSubresourceRange *range)
3773 {
3774 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3775 if (image->fmask.size)
3776 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3777 else
3778 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3779 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3780 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3781 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3782 }
3783 }
3784
3785 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3786 struct radv_image *image, uint32_t value)
3787 {
3788 struct radv_cmd_state *state = &cmd_buffer->state;
3789
3790 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3791 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3792
3793 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3794 image->offset + image->dcc_offset,
3795 image->surface.dcc_size, value);
3796
3797 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3798 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3799 }
3800
3801 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3802 struct radv_image *image,
3803 VkImageLayout src_layout,
3804 VkImageLayout dst_layout,
3805 unsigned src_queue_mask,
3806 unsigned dst_queue_mask,
3807 const VkImageSubresourceRange *range)
3808 {
3809 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3810 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3811 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3812 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3813 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3814 }
3815 }
3816
3817 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3818 struct radv_image *image,
3819 VkImageLayout src_layout,
3820 VkImageLayout dst_layout,
3821 uint32_t src_family,
3822 uint32_t dst_family,
3823 const VkImageSubresourceRange *range,
3824 VkImageAspectFlags pending_clears)
3825 {
3826 if (image->exclusive && src_family != dst_family) {
3827 /* This is an acquire or a release operation and there will be
3828 * a corresponding release/acquire. Do the transition in the
3829 * most flexible queue. */
3830
3831 assert(src_family == cmd_buffer->queue_family_index ||
3832 dst_family == cmd_buffer->queue_family_index);
3833
3834 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3835 return;
3836
3837 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3838 (src_family == RADV_QUEUE_GENERAL ||
3839 dst_family == RADV_QUEUE_GENERAL))
3840 return;
3841 }
3842
3843 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3844 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3845
3846 if (image->surface.htile_size)
3847 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3848 dst_layout, src_queue_mask,
3849 dst_queue_mask, range,
3850 pending_clears);
3851
3852 if (image->cmask.size || image->fmask.size)
3853 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3854 dst_layout, src_queue_mask,
3855 dst_queue_mask, range);
3856
3857 if (image->surface.dcc_size)
3858 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3859 dst_layout, src_queue_mask,
3860 dst_queue_mask, range);
3861 }
3862
3863 void radv_CmdPipelineBarrier(
3864 VkCommandBuffer commandBuffer,
3865 VkPipelineStageFlags srcStageMask,
3866 VkPipelineStageFlags destStageMask,
3867 VkBool32 byRegion,
3868 uint32_t memoryBarrierCount,
3869 const VkMemoryBarrier* pMemoryBarriers,
3870 uint32_t bufferMemoryBarrierCount,
3871 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3872 uint32_t imageMemoryBarrierCount,
3873 const VkImageMemoryBarrier* pImageMemoryBarriers)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 enum radv_cmd_flush_bits src_flush_bits = 0;
3877 enum radv_cmd_flush_bits dst_flush_bits = 0;
3878
3879 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3880 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3881 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3882 NULL);
3883 }
3884
3885 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3886 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3887 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3888 NULL);
3889 }
3890
3891 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3892 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3893 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3894 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3895 image);
3896 }
3897
3898 radv_stage_flush(cmd_buffer, srcStageMask);
3899 cmd_buffer->state.flush_bits |= src_flush_bits;
3900
3901 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3902 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3903 radv_handle_image_transition(cmd_buffer, image,
3904 pImageMemoryBarriers[i].oldLayout,
3905 pImageMemoryBarriers[i].newLayout,
3906 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3907 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3908 &pImageMemoryBarriers[i].subresourceRange,
3909 0);
3910 }
3911
3912 cmd_buffer->state.flush_bits |= dst_flush_bits;
3913 }
3914
3915
3916 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3917 struct radv_event *event,
3918 VkPipelineStageFlags stageMask,
3919 unsigned value)
3920 {
3921 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3922 uint64_t va = radv_buffer_get_va(event->bo);
3923
3924 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3925
3926 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3927
3928 /* TODO: this is overkill. Probably should figure something out from
3929 * the stage mask. */
3930
3931 si_cs_emit_write_event_eop(cs,
3932 cmd_buffer->state.predicating,
3933 cmd_buffer->device->physical_device->rad_info.chip_class,
3934 false,
3935 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3936 1, va, 2, value);
3937
3938 assert(cmd_buffer->cs->cdw <= cdw_max);
3939 }
3940
3941 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3942 VkEvent _event,
3943 VkPipelineStageFlags stageMask)
3944 {
3945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3946 RADV_FROM_HANDLE(radv_event, event, _event);
3947
3948 write_event(cmd_buffer, event, stageMask, 1);
3949 }
3950
3951 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3952 VkEvent _event,
3953 VkPipelineStageFlags stageMask)
3954 {
3955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3956 RADV_FROM_HANDLE(radv_event, event, _event);
3957
3958 write_event(cmd_buffer, event, stageMask, 0);
3959 }
3960
3961 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3962 uint32_t eventCount,
3963 const VkEvent* pEvents,
3964 VkPipelineStageFlags srcStageMask,
3965 VkPipelineStageFlags dstStageMask,
3966 uint32_t memoryBarrierCount,
3967 const VkMemoryBarrier* pMemoryBarriers,
3968 uint32_t bufferMemoryBarrierCount,
3969 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3970 uint32_t imageMemoryBarrierCount,
3971 const VkImageMemoryBarrier* pImageMemoryBarriers)
3972 {
3973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3974 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3975
3976 for (unsigned i = 0; i < eventCount; ++i) {
3977 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3978 uint64_t va = radv_buffer_get_va(event->bo);
3979
3980 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3981
3982 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3983
3984 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3985 assert(cmd_buffer->cs->cdw <= cdw_max);
3986 }
3987
3988
3989 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3990 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3991
3992 radv_handle_image_transition(cmd_buffer, image,
3993 pImageMemoryBarriers[i].oldLayout,
3994 pImageMemoryBarriers[i].newLayout,
3995 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3996 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3997 &pImageMemoryBarriers[i].subresourceRange,
3998 0);
3999 }
4000
4001 /* TODO: figure out how to do memory barriers without waiting */
4002 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4003 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4004 RADV_CMD_FLAG_INV_VMEM_L1 |
4005 RADV_CMD_FLAG_INV_SMEM_L1;
4006 }