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3f4940e9c668682d9de0ca7152959d575a50bb4c
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
368 /* Allocate a buffer for the EOP bug on GFX9. */
369 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
370 &eop_bug_offset, &fence_ptr);
371 cmd_buffer->gfx9_eop_bug_va =
372 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
373 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
374 }
375 }
376
377 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
378
379 return cmd_buffer->record_result;
380 }
381
382 static bool
383 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
384 uint64_t min_needed)
385 {
386 uint64_t new_size;
387 struct radeon_winsys_bo *bo;
388 struct radv_cmd_buffer_upload *upload;
389 struct radv_device *device = cmd_buffer->device;
390
391 new_size = MAX2(min_needed, 16 * 1024);
392 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
393
394 bo = device->ws->buffer_create(device->ws,
395 new_size, 4096,
396 RADEON_DOMAIN_GTT,
397 RADEON_FLAG_CPU_ACCESS|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING |
399 RADEON_FLAG_32BIT,
400 RADV_BO_PRIORITY_UPLOAD_BUFFER);
401
402 if (!bo) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
408 if (cmd_buffer->upload.upload_bo) {
409 upload = malloc(sizeof(*upload));
410
411 if (!upload) {
412 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
413 device->ws->buffer_destroy(bo);
414 return false;
415 }
416
417 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
418 list_add(&upload->list, &cmd_buffer->upload.list);
419 }
420
421 cmd_buffer->upload.upload_bo = bo;
422 cmd_buffer->upload.size = new_size;
423 cmd_buffer->upload.offset = 0;
424 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
425
426 if (!cmd_buffer->upload.map) {
427 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
428 return false;
429 }
430
431 return true;
432 }
433
434 bool
435 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
436 unsigned size,
437 unsigned alignment,
438 unsigned *out_offset,
439 void **ptr)
440 {
441 assert(util_is_power_of_two_nonzero(alignment));
442
443 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
444 if (offset + size > cmd_buffer->upload.size) {
445 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
446 return false;
447 offset = 0;
448 }
449
450 *out_offset = offset;
451 *ptr = cmd_buffer->upload.map + offset;
452
453 cmd_buffer->upload.offset = offset + size;
454 return true;
455 }
456
457 bool
458 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
459 unsigned size, unsigned alignment,
460 const void *data, unsigned *out_offset)
461 {
462 uint8_t *ptr;
463
464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
465 out_offset, (void **)&ptr))
466 return false;
467
468 if (ptr)
469 memcpy(ptr, data, size);
470
471 return true;
472 }
473
474 static void
475 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
476 unsigned count, const uint32_t *data)
477 {
478 struct radeon_cmdbuf *cs = cmd_buffer->cs;
479
480 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
481
482 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
483 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
484 S_370_WR_CONFIRM(1) |
485 S_370_ENGINE_SEL(V_370_ME));
486 radeon_emit(cs, va);
487 radeon_emit(cs, va >> 32);
488 radeon_emit_array(cs, data, count);
489 }
490
491 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
492 {
493 struct radv_device *device = cmd_buffer->device;
494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
495 uint64_t va;
496
497 va = radv_buffer_get_va(device->trace_bo);
498 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
499 va += 4;
500
501 ++cmd_buffer->state.trace_id;
502 radv_emit_write_data_packet(cmd_buffer, va, 1,
503 &cmd_buffer->state.trace_id);
504
505 radeon_check_space(cmd_buffer->device->ws, cs, 2);
506
507 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
508 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
509 }
510
511 static void
512 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
513 enum radv_cmd_flush_bits flags)
514 {
515 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
516 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
518
519 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
520
521 /* Force wait for graphics or compute engines to be idle. */
522 si_cs_emit_cache_flush(cmd_buffer->cs,
523 cmd_buffer->device->physical_device->rad_info.chip_class,
524 &cmd_buffer->gfx9_fence_idx,
525 cmd_buffer->gfx9_fence_va,
526 radv_cmd_buffer_uses_mec(cmd_buffer),
527 flags, cmd_buffer->gfx9_eop_bug_va);
528 }
529
530 if (unlikely(cmd_buffer->device->trace_bo))
531 radv_cmd_buffer_trace_emit(cmd_buffer);
532 }
533
534 static void
535 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline, enum ring_type ring)
537 {
538 struct radv_device *device = cmd_buffer->device;
539 uint32_t data[2];
540 uint64_t va;
541
542 va = radv_buffer_get_va(device->trace_bo);
543
544 switch (ring) {
545 case RING_GFX:
546 va += 8;
547 break;
548 case RING_COMPUTE:
549 va += 16;
550 break;
551 default:
552 assert(!"invalid ring type");
553 }
554
555 data[0] = (uintptr_t)pipeline;
556 data[1] = (uintptr_t)pipeline >> 32;
557
558 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
559 }
560
561 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
562 VkPipelineBindPoint bind_point,
563 struct radv_descriptor_set *set,
564 unsigned idx)
565 {
566 struct radv_descriptor_state *descriptors_state =
567 radv_get_descriptors_state(cmd_buffer, bind_point);
568
569 descriptors_state->sets[idx] = set;
570
571 descriptors_state->valid |= (1u << idx); /* active descriptors */
572 descriptors_state->dirty |= (1u << idx);
573 }
574
575 static void
576 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
577 VkPipelineBindPoint bind_point)
578 {
579 struct radv_descriptor_state *descriptors_state =
580 radv_get_descriptors_state(cmd_buffer, bind_point);
581 struct radv_device *device = cmd_buffer->device;
582 uint32_t data[MAX_SETS * 2] = {};
583 uint64_t va;
584 unsigned i;
585 va = radv_buffer_get_va(device->trace_bo) + 24;
586
587 for_each_bit(i, descriptors_state->valid) {
588 struct radv_descriptor_set *set = descriptors_state->sets[i];
589 data[i * 2] = (uint64_t)(uintptr_t)set;
590 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
591 }
592
593 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
594 }
595
596 struct radv_userdata_info *
597 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
598 gl_shader_stage stage,
599 int idx)
600 {
601 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
602 return &shader->info.user_sgprs_locs.shader_data[idx];
603 }
604
605 static void
606 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 gl_shader_stage stage,
609 int idx, uint64_t va)
610 {
611 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
612 uint32_t base_reg = pipeline->user_data_0[stage];
613 if (loc->sgpr_idx == -1)
614 return;
615
616 assert(loc->num_sgprs == 1);
617
618 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
619 base_reg + loc->sgpr_idx * 4, va, false);
620 }
621
622 static void
623 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
624 struct radv_pipeline *pipeline,
625 struct radv_descriptor_state *descriptors_state,
626 gl_shader_stage stage)
627 {
628 struct radv_device *device = cmd_buffer->device;
629 struct radeon_cmdbuf *cs = cmd_buffer->cs;
630 uint32_t sh_base = pipeline->user_data_0[stage];
631 struct radv_userdata_locations *locs =
632 &pipeline->shaders[stage]->info.user_sgprs_locs;
633 unsigned mask = locs->descriptor_sets_enabled;
634
635 mask &= descriptors_state->dirty & descriptors_state->valid;
636
637 while (mask) {
638 int start, count;
639
640 u_bit_scan_consecutive_range(&mask, &start, &count);
641
642 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
643 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
644
645 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
646 for (int i = 0; i < count; i++) {
647 struct radv_descriptor_set *set =
648 descriptors_state->sets[start + i];
649
650 radv_emit_shader_pointer_body(device, cs, set->va, true);
651 }
652 }
653 }
654
655 /**
656 * Convert the user sample locations to hardware sample locations (the values
657 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 */
659 static void
660 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
661 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
662 {
663 uint32_t x_offset = x % state->grid_size.width;
664 uint32_t y_offset = y % state->grid_size.height;
665 uint32_t num_samples = (uint32_t)state->per_pixel;
666 VkSampleLocationEXT *user_locs;
667 uint32_t pixel_offset;
668
669 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
670
671 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
672 user_locs = &state->locations[pixel_offset];
673
674 for (uint32_t i = 0; i < num_samples; i++) {
675 float shifted_pos_x = user_locs[i].x - 0.5;
676 float shifted_pos_y = user_locs[i].y - 0.5;
677
678 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
679 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
680
681 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
682 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
683 }
684 }
685
686 /**
687 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
688 * locations.
689 */
690 static void
691 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
692 uint32_t *sample_locs_pixel)
693 {
694 for (uint32_t i = 0; i < num_samples; i++) {
695 uint32_t sample_reg_idx = i / 4;
696 uint32_t sample_loc_idx = i % 4;
697 int32_t pos_x = sample_locs[i].x;
698 int32_t pos_y = sample_locs[i].y;
699
700 uint32_t shift_x = 8 * sample_loc_idx;
701 uint32_t shift_y = shift_x + 4;
702
703 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
704 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
705 }
706 }
707
708 /**
709 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
710 * sample locations.
711 */
712 static uint64_t
713 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
714 VkOffset2D *sample_locs,
715 uint32_t num_samples)
716 {
717 uint32_t centroid_priorities[num_samples];
718 uint32_t sample_mask = num_samples - 1;
719 uint32_t distances[num_samples];
720 uint64_t centroid_priority = 0;
721
722 /* Compute the distances from center for each sample. */
723 for (int i = 0; i < num_samples; i++) {
724 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
725 (sample_locs[i].y * sample_locs[i].y);
726 }
727
728 /* Compute the centroid priorities by looking at the distances array. */
729 for (int i = 0; i < num_samples; i++) {
730 uint32_t min_idx = 0;
731
732 for (int j = 1; j < num_samples; j++) {
733 if (distances[j] < distances[min_idx])
734 min_idx = j;
735 }
736
737 centroid_priorities[i] = min_idx;
738 distances[min_idx] = 0xffffffff;
739 }
740
741 /* Compute the final centroid priority. */
742 for (int i = 0; i < 8; i++) {
743 centroid_priority |=
744 centroid_priorities[i & sample_mask] << (i * 4);
745 }
746
747 return centroid_priority << 32 | centroid_priority;
748 }
749
750 /**
751 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 */
753 static void
754 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
755 {
756 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
757 struct radv_multisample_state *ms = &pipeline->graphics.ms;
758 struct radv_sample_locations_state *sample_location =
759 &cmd_buffer->state.dynamic.sample_location;
760 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
761 struct radeon_cmdbuf *cs = cmd_buffer->cs;
762 uint32_t sample_locs_pixel[4][2] = {};
763 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
764 uint32_t max_sample_dist = 0;
765 uint64_t centroid_priority;
766
767 if (!cmd_buffer->state.dynamic.sample_location.count)
768 return;
769
770 /* Convert the user sample locations to hardware sample locations. */
771 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
772 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
773 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
774 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
775
776 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
777 for (uint32_t i = 0; i < 4; i++) {
778 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
779 sample_locs_pixel[i]);
780 }
781
782 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
783 centroid_priority =
784 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
785 num_samples);
786
787 /* Compute the maximum sample distance from the specified locations. */
788 for (uint32_t i = 0; i < num_samples; i++) {
789 VkOffset2D offset = sample_locs[0][i];
790 max_sample_dist = MAX2(max_sample_dist,
791 MAX2(abs(offset.x), abs(offset.y)));
792 }
793
794 /* Emit the specified user sample locations. */
795 switch (num_samples) {
796 case 2:
797 case 4:
798 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
799 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
800 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
801 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
802 break;
803 case 8:
804 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
805 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
806 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
807 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
808 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
809 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
810 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
811 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
812 break;
813 default:
814 unreachable("invalid number of samples");
815 }
816
817 /* Emit the maximum sample distance and the centroid priority. */
818 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
819
820 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
821 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
822
823 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
824 radeon_emit(cs, pa_sc_aa_config);
825
826 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
827 radeon_emit(cs, centroid_priority);
828 radeon_emit(cs, centroid_priority >> 32);
829
830 /* GFX9: Flush DFSM when the AA mode changes. */
831 if (cmd_buffer->device->dfsm_allowed) {
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
833 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
834 }
835
836 cmd_buffer->state.context_roll_without_scissor_emitted = true;
837 }
838
839 static void
840 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_pipeline *pipeline,
842 gl_shader_stage stage,
843 int idx, int count, uint32_t *values)
844 {
845 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
846 uint32_t base_reg = pipeline->user_data_0[stage];
847 if (loc->sgpr_idx == -1)
848 return;
849
850 assert(loc->num_sgprs == count);
851
852 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
853 radeon_emit_array(cmd_buffer->cs, values, count);
854 }
855
856 static void
857 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
858 struct radv_pipeline *pipeline)
859 {
860 int num_samples = pipeline->graphics.ms.num_samples;
861 struct radv_multisample_state *ms = &pipeline->graphics.ms;
862 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
863
864 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
865 cmd_buffer->sample_positions_needed = true;
866
867 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
868 return;
869
870 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
871 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
872 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
873
874 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 /* GFX9: Flush DFSM when the AA mode changes. */
879 if (cmd_buffer->device->dfsm_allowed) {
880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
882 }
883
884 cmd_buffer->state.context_roll_without_scissor_emitted = true;
885 }
886
887 static void
888 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_pipeline *pipeline)
890 {
891 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
892
893
894 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
895 return;
896
897 if (old_pipeline &&
898 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
899 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
900 return;
901
902 bool binning_flush = false;
903 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
904 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
905 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
906 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
907 binning_flush = !old_pipeline ||
908 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
909 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
910 }
911
912 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
913 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
914 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
915
916 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
917 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
918 pipeline->graphics.binning.db_dfsm_control);
919 } else {
920 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 }
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = true;
925 }
926
927
928 static void
929 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_shader_variant *shader)
931 {
932 uint64_t va;
933
934 if (!shader)
935 return;
936
937 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
938
939 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
940 }
941
942 static void
943 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_pipeline *pipeline,
945 bool vertex_stage_only)
946 {
947 struct radv_cmd_state *state = &cmd_buffer->state;
948 uint32_t mask = state->prefetch_L2_mask;
949
950 if (vertex_stage_only) {
951 /* Fast prefetch path for starting draws as soon as possible.
952 */
953 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
954 RADV_PREFETCH_VBO_DESCRIPTORS);
955 }
956
957 if (mask & RADV_PREFETCH_VS)
958 radv_emit_shader_prefetch(cmd_buffer,
959 pipeline->shaders[MESA_SHADER_VERTEX]);
960
961 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
962 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
963
964 if (mask & RADV_PREFETCH_TCS)
965 radv_emit_shader_prefetch(cmd_buffer,
966 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
967
968 if (mask & RADV_PREFETCH_TES)
969 radv_emit_shader_prefetch(cmd_buffer,
970 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
971
972 if (mask & RADV_PREFETCH_GS) {
973 radv_emit_shader_prefetch(cmd_buffer,
974 pipeline->shaders[MESA_SHADER_GEOMETRY]);
975 if (radv_pipeline_has_gs_copy_shader(pipeline))
976 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
977 }
978
979 if (mask & RADV_PREFETCH_PS)
980 radv_emit_shader_prefetch(cmd_buffer,
981 pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 state->prefetch_L2_mask &= ~mask;
984 }
985
986 static void
987 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
988 {
989 if (!cmd_buffer->device->physical_device->rbplus_allowed)
990 return;
991
992 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
993 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
994 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
995
996 unsigned sx_ps_downconvert = 0;
997 unsigned sx_blend_opt_epsilon = 0;
998 unsigned sx_blend_opt_control = 0;
999
1000 for (unsigned i = 0; i < subpass->color_count; ++i) {
1001 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1002 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1003 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1004 continue;
1005 }
1006
1007 int idx = subpass->color_attachments[i].attachment;
1008 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
1009
1010 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1011 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1012 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1013 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1014
1015 bool has_alpha, has_rgb;
1016
1017 /* Set if RGB and A are present. */
1018 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1019
1020 if (format == V_028C70_COLOR_8 ||
1021 format == V_028C70_COLOR_16 ||
1022 format == V_028C70_COLOR_32)
1023 has_rgb = !has_alpha;
1024 else
1025 has_rgb = true;
1026
1027 /* Check the colormask and export format. */
1028 if (!(colormask & 0x7))
1029 has_rgb = false;
1030 if (!(colormask & 0x8))
1031 has_alpha = false;
1032
1033 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1034 has_rgb = false;
1035 has_alpha = false;
1036 }
1037
1038 /* Disable value checking for disabled channels. */
1039 if (!has_rgb)
1040 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1041 if (!has_alpha)
1042 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1043
1044 /* Enable down-conversion for 32bpp and smaller formats. */
1045 switch (format) {
1046 case V_028C70_COLOR_8:
1047 case V_028C70_COLOR_8_8:
1048 case V_028C70_COLOR_8_8_8_8:
1049 /* For 1 and 2-channel formats, use the superset thereof. */
1050 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1052 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1054 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1055 }
1056 break;
1057
1058 case V_028C70_COLOR_5_6_5:
1059 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1060 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1061 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1062 }
1063 break;
1064
1065 case V_028C70_COLOR_1_5_5_5:
1066 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1067 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1068 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1069 }
1070 break;
1071
1072 case V_028C70_COLOR_4_4_4_4:
1073 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1074 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1075 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1076 }
1077 break;
1078
1079 case V_028C70_COLOR_32:
1080 if (swap == V_028C70_SWAP_STD &&
1081 spi_format == V_028714_SPI_SHADER_32_R)
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1083 else if (swap == V_028C70_SWAP_ALT_REV &&
1084 spi_format == V_028714_SPI_SHADER_32_AR)
1085 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1086 break;
1087
1088 case V_028C70_COLOR_16:
1089 case V_028C70_COLOR_16_16:
1090 /* For 1-channel formats, use the superset thereof. */
1091 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1092 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1093 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1094 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1095 if (swap == V_028C70_SWAP_STD ||
1096 swap == V_028C70_SWAP_STD_REV)
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1098 else
1099 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1100 }
1101 break;
1102
1103 case V_028C70_COLOR_10_11_11:
1104 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1105 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1106 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1107 }
1108 break;
1109
1110 case V_028C70_COLOR_2_10_10_10:
1111 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1113 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1114 }
1115 break;
1116 }
1117 }
1118
1119 for (unsigned i = subpass->color_count; i < 8; ++i) {
1120 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1121 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1122 }
1123 /* TODO: avoid redundantly setting context registers */
1124 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1125 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1126 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1127 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1128
1129 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1130 }
1131
1132 static void
1133 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1136
1137 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1138 return;
1139
1140 radv_update_multisample_state(cmd_buffer, pipeline);
1141 radv_update_binning_state(cmd_buffer, pipeline);
1142
1143 cmd_buffer->scratch_size_needed =
1144 MAX2(cmd_buffer->scratch_size_needed,
1145 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1146
1147 if (!cmd_buffer->state.emitted_pipeline ||
1148 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1149 pipeline->graphics.can_use_guardband)
1150 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1151
1152 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1153
1154 if (!cmd_buffer->state.emitted_pipeline ||
1155 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1156 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1157 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1158 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1159 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1160 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1161 }
1162
1163 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1164 if (!pipeline->shaders[i])
1165 continue;
1166
1167 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1168 pipeline->shaders[i]->bo);
1169 }
1170
1171 if (radv_pipeline_has_gs_copy_shader(pipeline))
1172 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1173 pipeline->gs_copy_shader->bo);
1174
1175 if (unlikely(cmd_buffer->device->trace_bo))
1176 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1177
1178 cmd_buffer->state.emitted_pipeline = pipeline;
1179
1180 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1181 }
1182
1183 static void
1184 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1187 cmd_buffer->state.dynamic.viewport.viewports);
1188 }
1189
1190 static void
1191 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1192 {
1193 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1194
1195 si_write_scissors(cmd_buffer->cs, 0, count,
1196 cmd_buffer->state.dynamic.scissor.scissors,
1197 cmd_buffer->state.dynamic.viewport.viewports,
1198 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1199
1200 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1201 }
1202
1203 static void
1204 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1205 {
1206 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1207 return;
1208
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1210 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1211 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1212 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1213 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1214 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1215 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1216 }
1217 }
1218
1219 static void
1220 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1221 {
1222 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1223
1224 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1225 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1226 }
1227
1228 static void
1229 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1230 {
1231 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1232
1233 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1234 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1235 }
1236
1237 static void
1238 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1239 {
1240 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1241
1242 radeon_set_context_reg_seq(cmd_buffer->cs,
1243 R_028430_DB_STENCILREFMASK, 2);
1244 radeon_emit(cmd_buffer->cs,
1245 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1246 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1247 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1248 S_028430_STENCILOPVAL(1));
1249 radeon_emit(cmd_buffer->cs,
1250 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1251 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1252 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1253 S_028434_STENCILOPVAL_BF(1));
1254 }
1255
1256 static void
1257 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1260
1261 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1262 fui(d->depth_bounds.min));
1263 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1264 fui(d->depth_bounds.max));
1265 }
1266
1267 static void
1268 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1269 {
1270 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1271 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1272 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1273
1274
1275 radeon_set_context_reg_seq(cmd_buffer->cs,
1276 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1277 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1278 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1279 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1280 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1281 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1282 }
1283
1284 static void
1285 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1286 int index,
1287 struct radv_attachment_info *att,
1288 struct radv_image_view *iview,
1289 VkImageLayout layout)
1290 {
1291 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1292 struct radv_color_buffer_info *cb = &att->cb;
1293 uint32_t cb_color_info = cb->cb_color_info;
1294 struct radv_image *image = iview->image;
1295
1296 if (!radv_layout_dcc_compressed(image, layout,
1297 radv_image_queue_family_mask(image,
1298 cmd_buffer->queue_family_index,
1299 cmd_buffer->queue_family_index))) {
1300 cb_color_info &= C_028C70_DCC_ENABLE;
1301 }
1302
1303 if (radv_image_is_tc_compat_cmask(image) &&
1304 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1305 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1306 /* If this bit is set, the FMASK decompression operation
1307 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1308 */
1309 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1310 }
1311
1312 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1313 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1314 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1315 radeon_emit(cmd_buffer->cs, 0);
1316 radeon_emit(cmd_buffer->cs, 0);
1317 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1318 radeon_emit(cmd_buffer->cs, cb_color_info);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1320 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1322 radeon_emit(cmd_buffer->cs, 0);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1324 radeon_emit(cmd_buffer->cs, 0);
1325
1326 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1327 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1328
1329 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1330 cb->cb_color_base >> 32);
1331 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1332 cb->cb_color_cmask >> 32);
1333 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1334 cb->cb_color_fmask >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1336 cb->cb_dcc_base >> 32);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1338 cb->cb_color_attrib2);
1339 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1340 cb->cb_color_attrib3);
1341 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1342 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1343 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1344 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1347 radeon_emit(cmd_buffer->cs, cb_color_info);
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1349 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1351 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1353 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1354
1355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1356 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1357 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1358
1359 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1360 cb->cb_mrt_epitch);
1361 } else {
1362 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1363 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1364 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1367 radeon_emit(cmd_buffer->cs, cb_color_info);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1369 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1374
1375 if (is_vi) { /* DCC BASE */
1376 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1377 }
1378 }
1379
1380 if (radv_dcc_enabled(image, iview->base_mip)) {
1381 /* Drawing with DCC enabled also compresses colorbuffers. */
1382 VkImageSubresourceRange range = {
1383 .aspectMask = iview->aspect_mask,
1384 .baseMipLevel = iview->base_mip,
1385 .levelCount = iview->level_count,
1386 .baseArrayLayer = iview->base_layer,
1387 .layerCount = iview->layer_count,
1388 };
1389
1390 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1391 }
1392 }
1393
1394 static void
1395 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_ds_buffer_info *ds,
1397 struct radv_image *image, VkImageLayout layout,
1398 bool requires_cond_exec)
1399 {
1400 uint32_t db_z_info = ds->db_z_info;
1401 uint32_t db_z_info_reg;
1402
1403 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1404 !radv_image_is_tc_compat_htile(image))
1405 return;
1406
1407 if (!radv_layout_has_htile(image, layout,
1408 radv_image_queue_family_mask(image,
1409 cmd_buffer->queue_family_index,
1410 cmd_buffer->queue_family_index))) {
1411 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1412 }
1413
1414 db_z_info &= C_028040_ZRANGE_PRECISION;
1415
1416 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1417 db_z_info_reg = R_028038_DB_Z_INFO;
1418 } else {
1419 db_z_info_reg = R_028040_DB_Z_INFO;
1420 }
1421
1422 /* When we don't know the last fast clear value we need to emit a
1423 * conditional packet that will eventually skip the following
1424 * SET_CONTEXT_REG packet.
1425 */
1426 if (requires_cond_exec) {
1427 uint64_t va = radv_buffer_get_va(image->bo);
1428 va += image->offset + image->tc_compat_zrange_offset;
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1431 radeon_emit(cmd_buffer->cs, va);
1432 radeon_emit(cmd_buffer->cs, va >> 32);
1433 radeon_emit(cmd_buffer->cs, 0);
1434 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1435 }
1436
1437 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1438 }
1439
1440 static void
1441 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1442 struct radv_ds_buffer_info *ds,
1443 struct radv_image *image,
1444 VkImageLayout layout)
1445 {
1446 uint32_t db_z_info = ds->db_z_info;
1447 uint32_t db_stencil_info = ds->db_stencil_info;
1448
1449 if (!radv_layout_has_htile(image, layout,
1450 radv_image_queue_family_mask(image,
1451 cmd_buffer->queue_family_index,
1452 cmd_buffer->queue_family_index))) {
1453 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1454 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1458 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1459
1460 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1461 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1462 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1463
1464 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1465 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1466 radeon_emit(cmd_buffer->cs, db_z_info);
1467 radeon_emit(cmd_buffer->cs, db_stencil_info);
1468 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1469 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1470 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1471 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1472
1473 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1478 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1479 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1481 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1482 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1483 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1484
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1486 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1487 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1488 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1489 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1490 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1491 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1493 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1494 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1495 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1496
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1498 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1500 } else {
1501 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1504 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1505 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1506 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1509 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1512 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1513
1514 }
1515
1516 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1517 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1518
1519 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1520 ds->pa_su_poly_offset_db_fmt_cntl);
1521 }
1522
1523 /**
1524 * Update the fast clear depth/stencil values if the image is bound as a
1525 * depth/stencil buffer.
1526 */
1527 static void
1528 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1529 struct radv_image *image,
1530 VkClearDepthStencilValue ds_clear_value,
1531 VkImageAspectFlags aspects)
1532 {
1533 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1534 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1535 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1536 struct radv_attachment_info *att;
1537 uint32_t att_idx;
1538
1539 if (!framebuffer || !subpass)
1540 return;
1541
1542 if (!subpass->depth_stencil_attachment)
1543 return;
1544
1545 att_idx = subpass->depth_stencil_attachment->attachment;
1546 att = &framebuffer->attachments[att_idx];
1547 if (att->attachment->image != image)
1548 return;
1549
1550 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1551 radeon_emit(cs, ds_clear_value.stencil);
1552 radeon_emit(cs, fui(ds_clear_value.depth));
1553
1554 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1555 * only needed when clearing Z to 0.0.
1556 */
1557 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1558 ds_clear_value.depth == 0.0) {
1559 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1560
1561 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1562 layout, false);
1563 }
1564
1565 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1566 }
1567
1568 /**
1569 * Set the clear depth/stencil values to the image's metadata.
1570 */
1571 static void
1572 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1573 struct radv_image *image,
1574 VkClearDepthStencilValue ds_clear_value,
1575 VkImageAspectFlags aspects)
1576 {
1577 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1578 uint64_t va = radv_buffer_get_va(image->bo);
1579 unsigned reg_offset = 0, reg_count = 0;
1580
1581 va += image->offset + image->clear_value_offset;
1582
1583 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1584 ++reg_count;
1585 } else {
1586 ++reg_offset;
1587 va += 4;
1588 }
1589 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1590 ++reg_count;
1591
1592 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1593 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1594 S_370_WR_CONFIRM(1) |
1595 S_370_ENGINE_SEL(V_370_PFP));
1596 radeon_emit(cs, va);
1597 radeon_emit(cs, va >> 32);
1598 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1599 radeon_emit(cs, ds_clear_value.stencil);
1600 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1601 radeon_emit(cs, fui(ds_clear_value.depth));
1602 }
1603
1604 /**
1605 * Update the TC-compat metadata value for this image.
1606 */
1607 static void
1608 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_image *image,
1610 uint32_t value)
1611 {
1612 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1613 uint64_t va = radv_buffer_get_va(image->bo);
1614
1615 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1616 return;
1617
1618 va += image->offset + image->tc_compat_zrange_offset;
1619
1620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cs, va);
1625 radeon_emit(cs, va >> 32);
1626 radeon_emit(cs, value);
1627 }
1628
1629 static void
1630 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1631 struct radv_image *image,
1632 VkClearDepthStencilValue ds_clear_value)
1633 {
1634 uint32_t cond_val;
1635
1636 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1637 * depth clear value is 0.0f.
1638 */
1639 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1640
1641 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1642 }
1643
1644 /**
1645 * Update the clear depth/stencil values for this image.
1646 */
1647 void
1648 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image,
1650 VkClearDepthStencilValue ds_clear_value,
1651 VkImageAspectFlags aspects)
1652 {
1653 assert(radv_image_has_htile(image));
1654
1655 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1656
1657 if (radv_image_is_tc_compat_htile(image) &&
1658 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1659 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1660 ds_clear_value);
1661 }
1662
1663 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1664 aspects);
1665 }
1666
1667 /**
1668 * Load the clear depth/stencil values from the image's metadata.
1669 */
1670 static void
1671 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1672 struct radv_image *image)
1673 {
1674 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1675 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1676 uint64_t va = radv_buffer_get_va(image->bo);
1677 unsigned reg_offset = 0, reg_count = 0;
1678
1679 va += image->offset + image->clear_value_offset;
1680
1681 if (!radv_image_has_htile(image))
1682 return;
1683
1684 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1685 ++reg_count;
1686 } else {
1687 ++reg_offset;
1688 va += 4;
1689 }
1690 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1691 ++reg_count;
1692
1693 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1694
1695 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1696 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1697 radeon_emit(cs, va);
1698 radeon_emit(cs, va >> 32);
1699 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1700 radeon_emit(cs, reg_count);
1701 } else {
1702 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1703 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1704 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1705 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1706 radeon_emit(cs, va);
1707 radeon_emit(cs, va >> 32);
1708 radeon_emit(cs, reg >> 2);
1709 radeon_emit(cs, 0);
1710
1711 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1712 radeon_emit(cs, 0);
1713 }
1714 }
1715
1716 /*
1717 * With DCC some colors don't require CMASK elimination before being
1718 * used as a texture. This sets a predicate value to determine if the
1719 * cmask eliminate is required.
1720 */
1721 void
1722 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1723 struct radv_image *image,
1724 const VkImageSubresourceRange *range, bool value)
1725 {
1726 uint64_t pred_val = value;
1727 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1728 uint32_t level_count = radv_get_levelCount(image, range);
1729 uint32_t count = 2 * level_count;
1730
1731 assert(radv_dcc_enabled(image, range->baseMipLevel));
1732
1733 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1734 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1735 S_370_WR_CONFIRM(1) |
1736 S_370_ENGINE_SEL(V_370_PFP));
1737 radeon_emit(cmd_buffer->cs, va);
1738 radeon_emit(cmd_buffer->cs, va >> 32);
1739
1740 for (uint32_t l = 0; l < level_count; l++) {
1741 radeon_emit(cmd_buffer->cs, pred_val);
1742 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1743 }
1744 }
1745
1746 /**
1747 * Update the DCC predicate to reflect the compression state.
1748 */
1749 void
1750 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1751 struct radv_image *image,
1752 const VkImageSubresourceRange *range, bool value)
1753 {
1754 uint64_t pred_val = value;
1755 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1756 uint32_t level_count = radv_get_levelCount(image, range);
1757 uint32_t count = 2 * level_count;
1758
1759 assert(radv_dcc_enabled(image, range->baseMipLevel));
1760
1761 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1762 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1763 S_370_WR_CONFIRM(1) |
1764 S_370_ENGINE_SEL(V_370_PFP));
1765 radeon_emit(cmd_buffer->cs, va);
1766 radeon_emit(cmd_buffer->cs, va >> 32);
1767
1768 for (uint32_t l = 0; l < level_count; l++) {
1769 radeon_emit(cmd_buffer->cs, pred_val);
1770 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1771 }
1772 }
1773
1774 /**
1775 * Update the fast clear color values if the image is bound as a color buffer.
1776 */
1777 static void
1778 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1779 struct radv_image *image,
1780 int cb_idx,
1781 uint32_t color_values[2])
1782 {
1783 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1784 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1785 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1786 struct radv_attachment_info *att;
1787 uint32_t att_idx;
1788
1789 if (!framebuffer || !subpass)
1790 return;
1791
1792 att_idx = subpass->color_attachments[cb_idx].attachment;
1793 if (att_idx == VK_ATTACHMENT_UNUSED)
1794 return;
1795
1796 att = &framebuffer->attachments[att_idx];
1797 if (att->attachment->image != image)
1798 return;
1799
1800 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1801 radeon_emit(cs, color_values[0]);
1802 radeon_emit(cs, color_values[1]);
1803
1804 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1805 }
1806
1807 /**
1808 * Set the clear color values to the image's metadata.
1809 */
1810 static void
1811 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1812 struct radv_image *image,
1813 const VkImageSubresourceRange *range,
1814 uint32_t color_values[2])
1815 {
1816 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1817 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1818 uint32_t level_count = radv_get_levelCount(image, range);
1819 uint32_t count = 2 * level_count;
1820
1821 assert(radv_image_has_cmask(image) ||
1822 radv_dcc_enabled(image, range->baseMipLevel));
1823
1824 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1825 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1826 S_370_WR_CONFIRM(1) |
1827 S_370_ENGINE_SEL(V_370_PFP));
1828 radeon_emit(cs, va);
1829 radeon_emit(cs, va >> 32);
1830
1831 for (uint32_t l = 0; l < level_count; l++) {
1832 radeon_emit(cs, color_values[0]);
1833 radeon_emit(cs, color_values[1]);
1834 }
1835 }
1836
1837 /**
1838 * Update the clear color values for this image.
1839 */
1840 void
1841 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1842 const struct radv_image_view *iview,
1843 int cb_idx,
1844 uint32_t color_values[2])
1845 {
1846 struct radv_image *image = iview->image;
1847 VkImageSubresourceRange range = {
1848 .aspectMask = iview->aspect_mask,
1849 .baseMipLevel = iview->base_mip,
1850 .levelCount = iview->level_count,
1851 .baseArrayLayer = iview->base_layer,
1852 .layerCount = iview->layer_count,
1853 };
1854
1855 assert(radv_image_has_cmask(image) ||
1856 radv_dcc_enabled(image, iview->base_mip));
1857
1858 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1859
1860 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1861 color_values);
1862 }
1863
1864 /**
1865 * Load the clear color values from the image's metadata.
1866 */
1867 static void
1868 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1869 struct radv_image_view *iview,
1870 int cb_idx)
1871 {
1872 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1873 struct radv_image *image = iview->image;
1874 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1875
1876 if (!radv_image_has_cmask(image) &&
1877 !radv_dcc_enabled(image, iview->base_mip))
1878 return;
1879
1880 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1881
1882 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1883 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1884 radeon_emit(cs, va);
1885 radeon_emit(cs, va >> 32);
1886 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1887 radeon_emit(cs, 2);
1888 } else {
1889 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1890 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1891 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1892 COPY_DATA_COUNT_SEL);
1893 radeon_emit(cs, va);
1894 radeon_emit(cs, va >> 32);
1895 radeon_emit(cs, reg >> 2);
1896 radeon_emit(cs, 0);
1897
1898 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1899 radeon_emit(cs, 0);
1900 }
1901 }
1902
1903 static void
1904 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1905 {
1906 int i;
1907 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1908 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1909
1910 /* this may happen for inherited secondary recording */
1911 if (!framebuffer)
1912 return;
1913
1914 for (i = 0; i < 8; ++i) {
1915 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1916 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1917 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1918 continue;
1919 }
1920
1921 int idx = subpass->color_attachments[i].attachment;
1922 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1923 struct radv_image_view *iview = att->attachment;
1924 VkImageLayout layout = subpass->color_attachments[i].layout;
1925
1926 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1927
1928 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1929 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1930 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1931
1932 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1933 }
1934
1935 if (subpass->depth_stencil_attachment) {
1936 int idx = subpass->depth_stencil_attachment->attachment;
1937 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1938 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1939 struct radv_image *image = att->attachment->image;
1940 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1941 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1942 cmd_buffer->queue_family_index,
1943 cmd_buffer->queue_family_index);
1944 /* We currently don't support writing decompressed HTILE */
1945 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1946 radv_layout_is_htile_compressed(image, layout, queue_mask));
1947
1948 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1949
1950 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1951 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1952 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1953 }
1954 radv_load_ds_clear_metadata(cmd_buffer, image);
1955 } else {
1956 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1958 else
1959 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1960
1961 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1962 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1963 }
1964 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1965 S_028208_BR_X(framebuffer->width) |
1966 S_028208_BR_Y(framebuffer->height));
1967
1968 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1969 bool disable_constant_encode =
1970 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1971 enum chip_class chip_class =
1972 cmd_buffer->device->physical_device->rad_info.chip_class;
1973 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1974
1975 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1976 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1977 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1978 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1979 }
1980
1981 if (cmd_buffer->device->pbb_allowed) {
1982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1983 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1984 }
1985
1986 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1987 }
1988
1989 static void
1990 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1991 {
1992 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1993 struct radv_cmd_state *state = &cmd_buffer->state;
1994
1995 if (state->index_type != state->last_index_type) {
1996 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1997 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1998 cs, R_03090C_VGT_INDEX_TYPE,
1999 2, state->index_type);
2000 } else {
2001 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2002 radeon_emit(cs, state->index_type);
2003 }
2004
2005 state->last_index_type = state->index_type;
2006 }
2007
2008 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2009 radeon_emit(cs, state->index_va);
2010 radeon_emit(cs, state->index_va >> 32);
2011
2012 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2013 radeon_emit(cs, state->max_index_count);
2014
2015 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2016 }
2017
2018 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2019 {
2020 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2021 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2022 uint32_t pa_sc_mode_cntl_1 =
2023 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2024 uint32_t db_count_control;
2025
2026 if(!cmd_buffer->state.active_occlusion_queries) {
2027 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2028 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2029 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2030 has_perfect_queries) {
2031 /* Re-enable out-of-order rasterization if the
2032 * bound pipeline supports it and if it's has
2033 * been disabled before starting any perfect
2034 * occlusion queries.
2035 */
2036 radeon_set_context_reg(cmd_buffer->cs,
2037 R_028A4C_PA_SC_MODE_CNTL_1,
2038 pa_sc_mode_cntl_1);
2039 }
2040 }
2041 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2042 } else {
2043 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2044 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2045 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2046
2047 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2048 db_count_control =
2049 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2050 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2051 S_028004_SAMPLE_RATE(sample_rate) |
2052 S_028004_ZPASS_ENABLE(1) |
2053 S_028004_SLICE_EVEN_ENABLE(1) |
2054 S_028004_SLICE_ODD_ENABLE(1);
2055
2056 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2057 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2058 has_perfect_queries) {
2059 /* If the bound pipeline has enabled
2060 * out-of-order rasterization, we should
2061 * disable it before starting any perfect
2062 * occlusion queries.
2063 */
2064 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2065
2066 radeon_set_context_reg(cmd_buffer->cs,
2067 R_028A4C_PA_SC_MODE_CNTL_1,
2068 pa_sc_mode_cntl_1);
2069 }
2070 } else {
2071 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2072 S_028004_SAMPLE_RATE(sample_rate);
2073 }
2074 }
2075
2076 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2077
2078 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2079 }
2080
2081 static void
2082 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2083 {
2084 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2085
2086 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2087 radv_emit_viewport(cmd_buffer);
2088
2089 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2090 !cmd_buffer->device->physical_device->has_scissor_bug)
2091 radv_emit_scissor(cmd_buffer);
2092
2093 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2094 radv_emit_line_width(cmd_buffer);
2095
2096 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2097 radv_emit_blend_constants(cmd_buffer);
2098
2099 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2100 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2101 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2102 radv_emit_stencil(cmd_buffer);
2103
2104 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2105 radv_emit_depth_bounds(cmd_buffer);
2106
2107 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2108 radv_emit_depth_bias(cmd_buffer);
2109
2110 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2111 radv_emit_discard_rectangle(cmd_buffer);
2112
2113 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2114 radv_emit_sample_locations(cmd_buffer);
2115
2116 cmd_buffer->state.dirty &= ~states;
2117 }
2118
2119 static void
2120 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2121 VkPipelineBindPoint bind_point)
2122 {
2123 struct radv_descriptor_state *descriptors_state =
2124 radv_get_descriptors_state(cmd_buffer, bind_point);
2125 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2126 unsigned bo_offset;
2127
2128 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2129 set->mapped_ptr,
2130 &bo_offset))
2131 return;
2132
2133 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2134 set->va += bo_offset;
2135 }
2136
2137 static void
2138 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2139 VkPipelineBindPoint bind_point)
2140 {
2141 struct radv_descriptor_state *descriptors_state =
2142 radv_get_descriptors_state(cmd_buffer, bind_point);
2143 uint32_t size = MAX_SETS * 4;
2144 uint32_t offset;
2145 void *ptr;
2146
2147 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2148 256, &offset, &ptr))
2149 return;
2150
2151 for (unsigned i = 0; i < MAX_SETS; i++) {
2152 uint32_t *uptr = ((uint32_t *)ptr) + i;
2153 uint64_t set_va = 0;
2154 struct radv_descriptor_set *set = descriptors_state->sets[i];
2155 if (descriptors_state->valid & (1u << i))
2156 set_va = set->va;
2157 uptr[0] = set_va & 0xffffffff;
2158 }
2159
2160 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2161 va += offset;
2162
2163 if (cmd_buffer->state.pipeline) {
2164 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2165 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2166 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2167
2168 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2169 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2170 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2171
2172 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2173 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2174 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2175
2176 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2177 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2178 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2179
2180 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2181 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2182 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2183 }
2184
2185 if (cmd_buffer->state.compute_pipeline)
2186 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2187 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2188 }
2189
2190 static void
2191 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2192 VkShaderStageFlags stages)
2193 {
2194 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2195 VK_PIPELINE_BIND_POINT_COMPUTE :
2196 VK_PIPELINE_BIND_POINT_GRAPHICS;
2197 struct radv_descriptor_state *descriptors_state =
2198 radv_get_descriptors_state(cmd_buffer, bind_point);
2199 struct radv_cmd_state *state = &cmd_buffer->state;
2200 bool flush_indirect_descriptors;
2201
2202 if (!descriptors_state->dirty)
2203 return;
2204
2205 if (descriptors_state->push_dirty)
2206 radv_flush_push_descriptors(cmd_buffer, bind_point);
2207
2208 flush_indirect_descriptors =
2209 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2210 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2211 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2212 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2213
2214 if (flush_indirect_descriptors)
2215 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2216
2217 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2218 cmd_buffer->cs,
2219 MAX_SETS * MESA_SHADER_STAGES * 4);
2220
2221 if (cmd_buffer->state.pipeline) {
2222 radv_foreach_stage(stage, stages) {
2223 if (!cmd_buffer->state.pipeline->shaders[stage])
2224 continue;
2225
2226 radv_emit_descriptor_pointers(cmd_buffer,
2227 cmd_buffer->state.pipeline,
2228 descriptors_state, stage);
2229 }
2230 }
2231
2232 if (cmd_buffer->state.compute_pipeline &&
2233 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2234 radv_emit_descriptor_pointers(cmd_buffer,
2235 cmd_buffer->state.compute_pipeline,
2236 descriptors_state,
2237 MESA_SHADER_COMPUTE);
2238 }
2239
2240 descriptors_state->dirty = 0;
2241 descriptors_state->push_dirty = false;
2242
2243 assert(cmd_buffer->cs->cdw <= cdw_max);
2244
2245 if (unlikely(cmd_buffer->device->trace_bo))
2246 radv_save_descriptors(cmd_buffer, bind_point);
2247 }
2248
2249 static void
2250 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2251 VkShaderStageFlags stages)
2252 {
2253 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2254 ? cmd_buffer->state.compute_pipeline
2255 : cmd_buffer->state.pipeline;
2256 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2257 VK_PIPELINE_BIND_POINT_COMPUTE :
2258 VK_PIPELINE_BIND_POINT_GRAPHICS;
2259 struct radv_descriptor_state *descriptors_state =
2260 radv_get_descriptors_state(cmd_buffer, bind_point);
2261 struct radv_pipeline_layout *layout = pipeline->layout;
2262 struct radv_shader_variant *shader, *prev_shader;
2263 bool need_push_constants = false;
2264 unsigned offset;
2265 void *ptr;
2266 uint64_t va;
2267
2268 stages &= cmd_buffer->push_constant_stages;
2269 if (!stages ||
2270 (!layout->push_constant_size && !layout->dynamic_offset_count))
2271 return;
2272
2273 radv_foreach_stage(stage, stages) {
2274 if (!pipeline->shaders[stage])
2275 continue;
2276
2277 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2278 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2279
2280 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2281 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2282
2283 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2284 AC_UD_INLINE_PUSH_CONSTANTS,
2285 count,
2286 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2287 }
2288
2289 if (need_push_constants) {
2290 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2291 16 * layout->dynamic_offset_count,
2292 256, &offset, &ptr))
2293 return;
2294
2295 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2296 memcpy((char*)ptr + layout->push_constant_size,
2297 descriptors_state->dynamic_buffers,
2298 16 * layout->dynamic_offset_count);
2299
2300 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2301 va += offset;
2302
2303 MAYBE_UNUSED unsigned cdw_max =
2304 radeon_check_space(cmd_buffer->device->ws,
2305 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2306
2307 prev_shader = NULL;
2308 radv_foreach_stage(stage, stages) {
2309 shader = radv_get_shader(pipeline, stage);
2310
2311 /* Avoid redundantly emitting the address for merged stages. */
2312 if (shader && shader != prev_shader) {
2313 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2314 AC_UD_PUSH_CONSTANTS, va);
2315
2316 prev_shader = shader;
2317 }
2318 }
2319 assert(cmd_buffer->cs->cdw <= cdw_max);
2320 }
2321
2322 cmd_buffer->push_constant_stages &= ~stages;
2323 }
2324
2325 static void
2326 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2327 bool pipeline_is_dirty)
2328 {
2329 if ((pipeline_is_dirty ||
2330 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2331 cmd_buffer->state.pipeline->num_vertex_bindings &&
2332 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2333 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2334 unsigned vb_offset;
2335 void *vb_ptr;
2336 uint32_t i = 0;
2337 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2338 uint64_t va;
2339
2340 /* allocate some descriptor state for vertex buffers */
2341 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2342 &vb_offset, &vb_ptr))
2343 return;
2344
2345 for (i = 0; i < count; i++) {
2346 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2347 uint32_t offset;
2348 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2349 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2350
2351 if (!buffer)
2352 continue;
2353
2354 va = radv_buffer_get_va(buffer->bo);
2355
2356 offset = cmd_buffer->vertex_bindings[i].offset;
2357 va += offset + buffer->offset;
2358 desc[0] = va;
2359 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2360 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2361 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2362 else
2363 desc[2] = buffer->size - offset;
2364 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2365 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2366 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2367 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2368
2369 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2370 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2371 S_008F0C_OOB_SELECT(1) |
2372 S_008F0C_RESOURCE_LEVEL(1);
2373 } else {
2374 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2376 }
2377 }
2378
2379 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2380 va += vb_offset;
2381
2382 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2383 AC_UD_VS_VERTEX_BUFFERS, va);
2384
2385 cmd_buffer->state.vb_va = va;
2386 cmd_buffer->state.vb_size = count * 16;
2387 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2388 }
2389 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2390 }
2391
2392 static void
2393 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2394 {
2395 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2396 struct radv_userdata_info *loc;
2397 uint32_t base_reg;
2398
2399 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2400 if (!radv_get_shader(pipeline, stage))
2401 continue;
2402
2403 loc = radv_lookup_user_sgpr(pipeline, stage,
2404 AC_UD_STREAMOUT_BUFFERS);
2405 if (loc->sgpr_idx == -1)
2406 continue;
2407
2408 base_reg = pipeline->user_data_0[stage];
2409
2410 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2411 base_reg + loc->sgpr_idx * 4, va, false);
2412 }
2413
2414 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2415 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2416 if (loc->sgpr_idx != -1) {
2417 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2418
2419 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2420 base_reg + loc->sgpr_idx * 4, va, false);
2421 }
2422 }
2423 }
2424
2425 static void
2426 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2427 {
2428 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2429 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2430 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2431 unsigned so_offset;
2432 void *so_ptr;
2433 uint64_t va;
2434
2435 /* Allocate some descriptor state for streamout buffers. */
2436 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2437 MAX_SO_BUFFERS * 16, 256,
2438 &so_offset, &so_ptr))
2439 return;
2440
2441 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2442 struct radv_buffer *buffer = sb[i].buffer;
2443 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2444
2445 if (!(so->enabled_mask & (1 << i)))
2446 continue;
2447
2448 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2449
2450 va += sb[i].offset;
2451
2452 /* Set the descriptor.
2453 *
2454 * On GFX8, the format must be non-INVALID, otherwise
2455 * the buffer will be considered not bound and store
2456 * instructions will be no-ops.
2457 */
2458 desc[0] = va;
2459 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2460 desc[2] = 0xffffffff;
2461 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2465 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2466 }
2467
2468 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2469 va += so_offset;
2470
2471 radv_emit_streamout_buffers(cmd_buffer, va);
2472 }
2473
2474 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2475 }
2476
2477 static void
2478 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2479 {
2480 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2481 radv_flush_streamout_descriptors(cmd_buffer);
2482 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2483 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2484 }
2485
2486 struct radv_draw_info {
2487 /**
2488 * Number of vertices.
2489 */
2490 uint32_t count;
2491
2492 /**
2493 * Index of the first vertex.
2494 */
2495 int32_t vertex_offset;
2496
2497 /**
2498 * First instance id.
2499 */
2500 uint32_t first_instance;
2501
2502 /**
2503 * Number of instances.
2504 */
2505 uint32_t instance_count;
2506
2507 /**
2508 * First index (indexed draws only).
2509 */
2510 uint32_t first_index;
2511
2512 /**
2513 * Whether it's an indexed draw.
2514 */
2515 bool indexed;
2516
2517 /**
2518 * Indirect draw parameters resource.
2519 */
2520 struct radv_buffer *indirect;
2521 uint64_t indirect_offset;
2522 uint32_t stride;
2523
2524 /**
2525 * Draw count parameters resource.
2526 */
2527 struct radv_buffer *count_buffer;
2528 uint64_t count_buffer_offset;
2529
2530 /**
2531 * Stream output parameters resource.
2532 */
2533 struct radv_buffer *strmout_buffer;
2534 uint64_t strmout_buffer_offset;
2535 };
2536
2537 static void
2538 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2539 bool instanced_draw, bool indirect_draw,
2540 bool count_from_stream_output,
2541 uint32_t draw_vertex_count)
2542 {
2543 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2544 struct radv_cmd_state *state = &cmd_buffer->state;
2545 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2546 unsigned ia_multi_vgt_param;
2547
2548 ia_multi_vgt_param =
2549 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2550 indirect_draw,
2551 count_from_stream_output,
2552 draw_vertex_count);
2553
2554 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2555 if (info->chip_class == GFX9) {
2556 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2557 cs,
2558 R_030960_IA_MULTI_VGT_PARAM,
2559 4, ia_multi_vgt_param);
2560 } else if (info->chip_class >= GFX7) {
2561 radeon_set_context_reg_idx(cs,
2562 R_028AA8_IA_MULTI_VGT_PARAM,
2563 1, ia_multi_vgt_param);
2564 } else {
2565 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2566 ia_multi_vgt_param);
2567 }
2568 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2569 }
2570 }
2571
2572 static void
2573 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2574 const struct radv_draw_info *draw_info)
2575 {
2576 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2577 struct radv_cmd_state *state = &cmd_buffer->state;
2578 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2579 int32_t primitive_reset_en;
2580
2581 /* Draw state. */
2582 if (info->chip_class < GFX10) {
2583 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2584 draw_info->indirect,
2585 !!draw_info->strmout_buffer,
2586 draw_info->indirect ? 0 : draw_info->count);
2587 }
2588
2589 /* Primitive restart. */
2590 primitive_reset_en =
2591 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2592
2593 if (primitive_reset_en != state->last_primitive_reset_en) {
2594 state->last_primitive_reset_en = primitive_reset_en;
2595 if (info->chip_class >= GFX9) {
2596 radeon_set_uconfig_reg(cs,
2597 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2598 primitive_reset_en);
2599 } else {
2600 radeon_set_context_reg(cs,
2601 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2602 primitive_reset_en);
2603 }
2604 }
2605
2606 if (primitive_reset_en) {
2607 uint32_t primitive_reset_index =
2608 state->index_type ? 0xffffffffu : 0xffffu;
2609
2610 if (primitive_reset_index != state->last_primitive_reset_index) {
2611 radeon_set_context_reg(cs,
2612 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2613 primitive_reset_index);
2614 state->last_primitive_reset_index = primitive_reset_index;
2615 }
2616 }
2617
2618 if (draw_info->strmout_buffer) {
2619 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2620
2621 va += draw_info->strmout_buffer->offset +
2622 draw_info->strmout_buffer_offset;
2623
2624 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2625 draw_info->stride);
2626
2627 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2628 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2629 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2630 COPY_DATA_WR_CONFIRM);
2631 radeon_emit(cs, va);
2632 radeon_emit(cs, va >> 32);
2633 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2634 radeon_emit(cs, 0); /* unused */
2635
2636 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2637 }
2638 }
2639
2640 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2641 VkPipelineStageFlags src_stage_mask)
2642 {
2643 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2644 VK_PIPELINE_STAGE_TRANSFER_BIT |
2645 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2646 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2647 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2648 }
2649
2650 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2651 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2652 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2653 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2654 VK_PIPELINE_STAGE_TRANSFER_BIT |
2655 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2656 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2657 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2658 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2659 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2660 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2661 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2662 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2663 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2664 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2665 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2666 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2667 }
2668 }
2669
2670 static enum radv_cmd_flush_bits
2671 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2672 VkAccessFlags src_flags,
2673 struct radv_image *image)
2674 {
2675 bool flush_CB_meta = true, flush_DB_meta = true;
2676 enum radv_cmd_flush_bits flush_bits = 0;
2677 uint32_t b;
2678
2679 if (image) {
2680 if (!radv_image_has_CB_metadata(image))
2681 flush_CB_meta = false;
2682 if (!radv_image_has_htile(image))
2683 flush_DB_meta = false;
2684 }
2685
2686 for_each_bit(b, src_flags) {
2687 switch ((VkAccessFlagBits)(1 << b)) {
2688 case VK_ACCESS_SHADER_WRITE_BIT:
2689 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2690 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2691 flush_bits |= RADV_CMD_FLAG_WB_L2;
2692 break;
2693 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2694 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2695 if (flush_CB_meta)
2696 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2697 break;
2698 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2699 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2700 if (flush_DB_meta)
2701 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2702 break;
2703 case VK_ACCESS_TRANSFER_WRITE_BIT:
2704 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2705 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2706 RADV_CMD_FLAG_INV_L2;
2707
2708 if (flush_CB_meta)
2709 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2710 if (flush_DB_meta)
2711 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2712 break;
2713 default:
2714 break;
2715 }
2716 }
2717 return flush_bits;
2718 }
2719
2720 static enum radv_cmd_flush_bits
2721 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2722 VkAccessFlags dst_flags,
2723 struct radv_image *image)
2724 {
2725 bool flush_CB_meta = true, flush_DB_meta = true;
2726 enum radv_cmd_flush_bits flush_bits = 0;
2727 bool flush_CB = true, flush_DB = true;
2728 bool image_is_coherent = false;
2729 uint32_t b;
2730
2731 if (image) {
2732 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2733 flush_CB = false;
2734 flush_DB = false;
2735 }
2736
2737 if (!radv_image_has_CB_metadata(image))
2738 flush_CB_meta = false;
2739 if (!radv_image_has_htile(image))
2740 flush_DB_meta = false;
2741
2742 /* TODO: implement shader coherent for GFX10 */
2743
2744 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2745 if (image->info.samples == 1 &&
2746 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2747 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2748 !vk_format_is_stencil(image->vk_format)) {
2749 /* Single-sample color and single-sample depth
2750 * (not stencil) are coherent with shaders on
2751 * GFX9.
2752 */
2753 image_is_coherent = true;
2754 }
2755 }
2756 }
2757
2758 for_each_bit(b, dst_flags) {
2759 switch ((VkAccessFlagBits)(1 << b)) {
2760 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2761 case VK_ACCESS_INDEX_READ_BIT:
2762 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2763 break;
2764 case VK_ACCESS_UNIFORM_READ_BIT:
2765 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2766 break;
2767 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2768 case VK_ACCESS_TRANSFER_READ_BIT:
2769 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2770 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2771 RADV_CMD_FLAG_INV_L2;
2772 break;
2773 case VK_ACCESS_SHADER_READ_BIT:
2774 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2775
2776 if (!image_is_coherent)
2777 flush_bits |= RADV_CMD_FLAG_INV_L2;
2778 break;
2779 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2780 if (flush_CB)
2781 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2782 if (flush_CB_meta)
2783 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2784 break;
2785 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2786 if (flush_DB)
2787 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2788 if (flush_DB_meta)
2789 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2790 break;
2791 default:
2792 break;
2793 }
2794 }
2795 return flush_bits;
2796 }
2797
2798 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2799 const struct radv_subpass_barrier *barrier)
2800 {
2801 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2802 NULL);
2803 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2804 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2805 NULL);
2806 }
2807
2808 uint32_t
2809 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2810 {
2811 struct radv_cmd_state *state = &cmd_buffer->state;
2812 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2813
2814 /* The id of this subpass shouldn't exceed the number of subpasses in
2815 * this render pass minus 1.
2816 */
2817 assert(subpass_id < state->pass->subpass_count);
2818 return subpass_id;
2819 }
2820
2821 static struct radv_sample_locations_state *
2822 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2823 uint32_t att_idx,
2824 bool begin_subpass)
2825 {
2826 struct radv_cmd_state *state = &cmd_buffer->state;
2827 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2828 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2829
2830 if (view->image->info.samples == 1)
2831 return NULL;
2832
2833 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2834 /* Return the initial sample locations if this is the initial
2835 * layout transition of the given subpass attachemnt.
2836 */
2837 if (state->attachments[att_idx].sample_location.count > 0)
2838 return &state->attachments[att_idx].sample_location;
2839 } else {
2840 /* Otherwise return the subpass sample locations if defined. */
2841 if (state->subpass_sample_locs) {
2842 /* Because the driver sets the current subpass before
2843 * initial layout transitions, we should use the sample
2844 * locations from the previous subpass to avoid an
2845 * off-by-one problem. Otherwise, use the sample
2846 * locations for the current subpass for final layout
2847 * transitions.
2848 */
2849 if (begin_subpass)
2850 subpass_id--;
2851
2852 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2853 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2854 return &state->subpass_sample_locs[i].sample_location;
2855 }
2856 }
2857 }
2858
2859 return NULL;
2860 }
2861
2862 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2863 struct radv_subpass_attachment att,
2864 bool begin_subpass)
2865 {
2866 unsigned idx = att.attachment;
2867 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2868 struct radv_sample_locations_state *sample_locs;
2869 VkImageSubresourceRange range;
2870 range.aspectMask = 0;
2871 range.baseMipLevel = view->base_mip;
2872 range.levelCount = 1;
2873 range.baseArrayLayer = view->base_layer;
2874 range.layerCount = cmd_buffer->state.framebuffer->layers;
2875
2876 if (cmd_buffer->state.subpass->view_mask) {
2877 /* If the current subpass uses multiview, the driver might have
2878 * performed a fast color/depth clear to the whole image
2879 * (including all layers). To make sure the driver will
2880 * decompress the image correctly (if needed), we have to
2881 * account for the "real" number of layers. If the view mask is
2882 * sparse, this will decompress more layers than needed.
2883 */
2884 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2885 }
2886
2887 /* Get the subpass sample locations for the given attachment, if NULL
2888 * is returned the driver will use the default HW locations.
2889 */
2890 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2891 begin_subpass);
2892
2893 radv_handle_image_transition(cmd_buffer,
2894 view->image,
2895 cmd_buffer->state.attachments[idx].current_layout,
2896 att.layout, 0, 0, &range, sample_locs);
2897
2898 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2899
2900
2901 }
2902
2903 void
2904 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2905 const struct radv_subpass *subpass)
2906 {
2907 cmd_buffer->state.subpass = subpass;
2908
2909 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2910 }
2911
2912 static VkResult
2913 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2914 struct radv_render_pass *pass,
2915 const VkRenderPassBeginInfo *info)
2916 {
2917 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2918 vk_find_struct_const(info->pNext,
2919 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2920 struct radv_cmd_state *state = &cmd_buffer->state;
2921 struct radv_framebuffer *framebuffer = state->framebuffer;
2922
2923 if (!sample_locs) {
2924 state->subpass_sample_locs = NULL;
2925 return VK_SUCCESS;
2926 }
2927
2928 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2929 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2930 &sample_locs->pAttachmentInitialSampleLocations[i];
2931 uint32_t att_idx = att_sample_locs->attachmentIndex;
2932 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2933 struct radv_image *image = att->attachment->image;
2934
2935 assert(vk_format_is_depth_or_stencil(image->vk_format));
2936
2937 /* From the Vulkan spec 1.1.108:
2938 *
2939 * "If the image referenced by the framebuffer attachment at
2940 * index attachmentIndex was not created with
2941 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2942 * then the values specified in sampleLocationsInfo are
2943 * ignored."
2944 */
2945 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2946 continue;
2947
2948 const VkSampleLocationsInfoEXT *sample_locs_info =
2949 &att_sample_locs->sampleLocationsInfo;
2950
2951 state->attachments[att_idx].sample_location.per_pixel =
2952 sample_locs_info->sampleLocationsPerPixel;
2953 state->attachments[att_idx].sample_location.grid_size =
2954 sample_locs_info->sampleLocationGridSize;
2955 state->attachments[att_idx].sample_location.count =
2956 sample_locs_info->sampleLocationsCount;
2957 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2958 sample_locs_info->pSampleLocations,
2959 sample_locs_info->sampleLocationsCount);
2960 }
2961
2962 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2963 sample_locs->postSubpassSampleLocationsCount *
2964 sizeof(state->subpass_sample_locs[0]),
2965 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2966 if (state->subpass_sample_locs == NULL) {
2967 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2968 return cmd_buffer->record_result;
2969 }
2970
2971 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2972
2973 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2974 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2975 &sample_locs->pPostSubpassSampleLocations[i];
2976 const VkSampleLocationsInfoEXT *sample_locs_info =
2977 &subpass_sample_locs_info->sampleLocationsInfo;
2978
2979 state->subpass_sample_locs[i].subpass_idx =
2980 subpass_sample_locs_info->subpassIndex;
2981 state->subpass_sample_locs[i].sample_location.per_pixel =
2982 sample_locs_info->sampleLocationsPerPixel;
2983 state->subpass_sample_locs[i].sample_location.grid_size =
2984 sample_locs_info->sampleLocationGridSize;
2985 state->subpass_sample_locs[i].sample_location.count =
2986 sample_locs_info->sampleLocationsCount;
2987 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2988 sample_locs_info->pSampleLocations,
2989 sample_locs_info->sampleLocationsCount);
2990 }
2991
2992 return VK_SUCCESS;
2993 }
2994
2995 static VkResult
2996 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2997 struct radv_render_pass *pass,
2998 const VkRenderPassBeginInfo *info)
2999 {
3000 struct radv_cmd_state *state = &cmd_buffer->state;
3001
3002 if (pass->attachment_count == 0) {
3003 state->attachments = NULL;
3004 return VK_SUCCESS;
3005 }
3006
3007 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3008 pass->attachment_count *
3009 sizeof(state->attachments[0]),
3010 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3011 if (state->attachments == NULL) {
3012 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3013 return cmd_buffer->record_result;
3014 }
3015
3016 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3017 struct radv_render_pass_attachment *att = &pass->attachments[i];
3018 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3019 VkImageAspectFlags clear_aspects = 0;
3020
3021 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3022 /* color attachment */
3023 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3024 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3025 }
3026 } else {
3027 /* depthstencil attachment */
3028 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3029 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3030 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3031 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3032 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3033 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3034 }
3035 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3036 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3037 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3038 }
3039 }
3040
3041 state->attachments[i].pending_clear_aspects = clear_aspects;
3042 state->attachments[i].cleared_views = 0;
3043 if (clear_aspects && info) {
3044 assert(info->clearValueCount > i);
3045 state->attachments[i].clear_value = info->pClearValues[i];
3046 }
3047
3048 state->attachments[i].current_layout = att->initial_layout;
3049 state->attachments[i].sample_location.count = 0;
3050 }
3051
3052 return VK_SUCCESS;
3053 }
3054
3055 VkResult radv_AllocateCommandBuffers(
3056 VkDevice _device,
3057 const VkCommandBufferAllocateInfo *pAllocateInfo,
3058 VkCommandBuffer *pCommandBuffers)
3059 {
3060 RADV_FROM_HANDLE(radv_device, device, _device);
3061 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3062
3063 VkResult result = VK_SUCCESS;
3064 uint32_t i;
3065
3066 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3067
3068 if (!list_empty(&pool->free_cmd_buffers)) {
3069 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3070
3071 list_del(&cmd_buffer->pool_link);
3072 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3073
3074 result = radv_reset_cmd_buffer(cmd_buffer);
3075 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3076 cmd_buffer->level = pAllocateInfo->level;
3077
3078 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3079 } else {
3080 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3081 &pCommandBuffers[i]);
3082 }
3083 if (result != VK_SUCCESS)
3084 break;
3085 }
3086
3087 if (result != VK_SUCCESS) {
3088 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3089 i, pCommandBuffers);
3090
3091 /* From the Vulkan 1.0.66 spec:
3092 *
3093 * "vkAllocateCommandBuffers can be used to create multiple
3094 * command buffers. If the creation of any of those command
3095 * buffers fails, the implementation must destroy all
3096 * successfully created command buffer objects from this
3097 * command, set all entries of the pCommandBuffers array to
3098 * NULL and return the error."
3099 */
3100 memset(pCommandBuffers, 0,
3101 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3102 }
3103
3104 return result;
3105 }
3106
3107 void radv_FreeCommandBuffers(
3108 VkDevice device,
3109 VkCommandPool commandPool,
3110 uint32_t commandBufferCount,
3111 const VkCommandBuffer *pCommandBuffers)
3112 {
3113 for (uint32_t i = 0; i < commandBufferCount; i++) {
3114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3115
3116 if (cmd_buffer) {
3117 if (cmd_buffer->pool) {
3118 list_del(&cmd_buffer->pool_link);
3119 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3120 } else
3121 radv_cmd_buffer_destroy(cmd_buffer);
3122
3123 }
3124 }
3125 }
3126
3127 VkResult radv_ResetCommandBuffer(
3128 VkCommandBuffer commandBuffer,
3129 VkCommandBufferResetFlags flags)
3130 {
3131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3132 return radv_reset_cmd_buffer(cmd_buffer);
3133 }
3134
3135 VkResult radv_BeginCommandBuffer(
3136 VkCommandBuffer commandBuffer,
3137 const VkCommandBufferBeginInfo *pBeginInfo)
3138 {
3139 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3140 VkResult result = VK_SUCCESS;
3141
3142 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3143 /* If the command buffer has already been resetted with
3144 * vkResetCommandBuffer, no need to do it again.
3145 */
3146 result = radv_reset_cmd_buffer(cmd_buffer);
3147 if (result != VK_SUCCESS)
3148 return result;
3149 }
3150
3151 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3152 cmd_buffer->state.last_primitive_reset_en = -1;
3153 cmd_buffer->state.last_index_type = -1;
3154 cmd_buffer->state.last_num_instances = -1;
3155 cmd_buffer->state.last_vertex_offset = -1;
3156 cmd_buffer->state.last_first_instance = -1;
3157 cmd_buffer->state.predication_type = -1;
3158 cmd_buffer->usage_flags = pBeginInfo->flags;
3159
3160 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3161 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3162 assert(pBeginInfo->pInheritanceInfo);
3163 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3164 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3165
3166 struct radv_subpass *subpass =
3167 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3168
3169 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3170 if (result != VK_SUCCESS)
3171 return result;
3172
3173 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3174 }
3175
3176 if (unlikely(cmd_buffer->device->trace_bo)) {
3177 struct radv_device *device = cmd_buffer->device;
3178
3179 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3180 device->trace_bo);
3181
3182 radv_cmd_buffer_trace_emit(cmd_buffer);
3183 }
3184
3185 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3186
3187 return result;
3188 }
3189
3190 void radv_CmdBindVertexBuffers(
3191 VkCommandBuffer commandBuffer,
3192 uint32_t firstBinding,
3193 uint32_t bindingCount,
3194 const VkBuffer* pBuffers,
3195 const VkDeviceSize* pOffsets)
3196 {
3197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3198 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3199 bool changed = false;
3200
3201 /* We have to defer setting up vertex buffer since we need the buffer
3202 * stride from the pipeline. */
3203
3204 assert(firstBinding + bindingCount <= MAX_VBS);
3205 for (uint32_t i = 0; i < bindingCount; i++) {
3206 uint32_t idx = firstBinding + i;
3207
3208 if (!changed &&
3209 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3210 vb[idx].offset != pOffsets[i])) {
3211 changed = true;
3212 }
3213
3214 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3215 vb[idx].offset = pOffsets[i];
3216
3217 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3218 vb[idx].buffer->bo);
3219 }
3220
3221 if (!changed) {
3222 /* No state changes. */
3223 return;
3224 }
3225
3226 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3227 }
3228
3229 void radv_CmdBindIndexBuffer(
3230 VkCommandBuffer commandBuffer,
3231 VkBuffer buffer,
3232 VkDeviceSize offset,
3233 VkIndexType indexType)
3234 {
3235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3236 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3237
3238 if (cmd_buffer->state.index_buffer == index_buffer &&
3239 cmd_buffer->state.index_offset == offset &&
3240 cmd_buffer->state.index_type == indexType) {
3241 /* No state changes. */
3242 return;
3243 }
3244
3245 cmd_buffer->state.index_buffer = index_buffer;
3246 cmd_buffer->state.index_offset = offset;
3247 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3248 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3249 cmd_buffer->state.index_va += index_buffer->offset + offset;
3250
3251 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3252 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3253 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3254 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3255 }
3256
3257
3258 static void
3259 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3260 VkPipelineBindPoint bind_point,
3261 struct radv_descriptor_set *set, unsigned idx)
3262 {
3263 struct radeon_winsys *ws = cmd_buffer->device->ws;
3264
3265 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3266
3267 assert(set);
3268 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3269
3270 if (!cmd_buffer->device->use_global_bo_list) {
3271 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3272 if (set->descriptors[j])
3273 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3274 }
3275
3276 if(set->bo)
3277 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3278 }
3279
3280 void radv_CmdBindDescriptorSets(
3281 VkCommandBuffer commandBuffer,
3282 VkPipelineBindPoint pipelineBindPoint,
3283 VkPipelineLayout _layout,
3284 uint32_t firstSet,
3285 uint32_t descriptorSetCount,
3286 const VkDescriptorSet* pDescriptorSets,
3287 uint32_t dynamicOffsetCount,
3288 const uint32_t* pDynamicOffsets)
3289 {
3290 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3291 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3292 unsigned dyn_idx = 0;
3293
3294 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3295 struct radv_descriptor_state *descriptors_state =
3296 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3297
3298 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3299 unsigned idx = i + firstSet;
3300 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3301 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3302
3303 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3304 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3305 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3306 assert(dyn_idx < dynamicOffsetCount);
3307
3308 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3309 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3310 dst[0] = va;
3311 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3312 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3313 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3314 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3315 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3316 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3317
3318 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3319 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3320 S_008F0C_OOB_SELECT(3) |
3321 S_008F0C_RESOURCE_LEVEL(1);
3322 } else {
3323 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3325 }
3326
3327 cmd_buffer->push_constant_stages |=
3328 set->layout->dynamic_shader_stages;
3329 }
3330 }
3331 }
3332
3333 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3334 struct radv_descriptor_set *set,
3335 struct radv_descriptor_set_layout *layout,
3336 VkPipelineBindPoint bind_point)
3337 {
3338 struct radv_descriptor_state *descriptors_state =
3339 radv_get_descriptors_state(cmd_buffer, bind_point);
3340 set->size = layout->size;
3341 set->layout = layout;
3342
3343 if (descriptors_state->push_set.capacity < set->size) {
3344 size_t new_size = MAX2(set->size, 1024);
3345 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3346 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3347
3348 free(set->mapped_ptr);
3349 set->mapped_ptr = malloc(new_size);
3350
3351 if (!set->mapped_ptr) {
3352 descriptors_state->push_set.capacity = 0;
3353 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3354 return false;
3355 }
3356
3357 descriptors_state->push_set.capacity = new_size;
3358 }
3359
3360 return true;
3361 }
3362
3363 void radv_meta_push_descriptor_set(
3364 struct radv_cmd_buffer* cmd_buffer,
3365 VkPipelineBindPoint pipelineBindPoint,
3366 VkPipelineLayout _layout,
3367 uint32_t set,
3368 uint32_t descriptorWriteCount,
3369 const VkWriteDescriptorSet* pDescriptorWrites)
3370 {
3371 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3372 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3373 unsigned bo_offset;
3374
3375 assert(set == 0);
3376 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3377
3378 push_set->size = layout->set[set].layout->size;
3379 push_set->layout = layout->set[set].layout;
3380
3381 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3382 &bo_offset,
3383 (void**) &push_set->mapped_ptr))
3384 return;
3385
3386 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3387 push_set->va += bo_offset;
3388
3389 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3390 radv_descriptor_set_to_handle(push_set),
3391 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3392
3393 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3394 }
3395
3396 void radv_CmdPushDescriptorSetKHR(
3397 VkCommandBuffer commandBuffer,
3398 VkPipelineBindPoint pipelineBindPoint,
3399 VkPipelineLayout _layout,
3400 uint32_t set,
3401 uint32_t descriptorWriteCount,
3402 const VkWriteDescriptorSet* pDescriptorWrites)
3403 {
3404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3405 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3406 struct radv_descriptor_state *descriptors_state =
3407 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3408 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3409
3410 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3411
3412 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3413 layout->set[set].layout,
3414 pipelineBindPoint))
3415 return;
3416
3417 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3418 * because it is invalid, according to Vulkan spec.
3419 */
3420 for (int i = 0; i < descriptorWriteCount; i++) {
3421 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3422 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3423 }
3424
3425 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3426 radv_descriptor_set_to_handle(push_set),
3427 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3428
3429 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3430 descriptors_state->push_dirty = true;
3431 }
3432
3433 void radv_CmdPushDescriptorSetWithTemplateKHR(
3434 VkCommandBuffer commandBuffer,
3435 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3436 VkPipelineLayout _layout,
3437 uint32_t set,
3438 const void* pData)
3439 {
3440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3441 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3442 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3443 struct radv_descriptor_state *descriptors_state =
3444 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3445 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3446
3447 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3448
3449 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3450 layout->set[set].layout,
3451 templ->bind_point))
3452 return;
3453
3454 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3455 descriptorUpdateTemplate, pData);
3456
3457 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3458 descriptors_state->push_dirty = true;
3459 }
3460
3461 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3462 VkPipelineLayout layout,
3463 VkShaderStageFlags stageFlags,
3464 uint32_t offset,
3465 uint32_t size,
3466 const void* pValues)
3467 {
3468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3469 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3470 cmd_buffer->push_constant_stages |= stageFlags;
3471 }
3472
3473 VkResult radv_EndCommandBuffer(
3474 VkCommandBuffer commandBuffer)
3475 {
3476 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3477
3478 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3479 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3480 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3481
3482 /* Make sure to sync all pending active queries at the end of
3483 * command buffer.
3484 */
3485 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3486
3487 si_emit_cache_flush(cmd_buffer);
3488 }
3489
3490 /* Make sure CP DMA is idle at the end of IBs because the kernel
3491 * doesn't wait for it.
3492 */
3493 si_cp_dma_wait_for_idle(cmd_buffer);
3494
3495 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3496 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3497
3498 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3499 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3500
3501 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3502
3503 return cmd_buffer->record_result;
3504 }
3505
3506 static void
3507 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3508 {
3509 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3510
3511 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3512 return;
3513
3514 assert(!pipeline->ctx_cs.cdw);
3515
3516 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3517
3518 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3519 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3520
3521 cmd_buffer->compute_scratch_size_needed =
3522 MAX2(cmd_buffer->compute_scratch_size_needed,
3523 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3524
3525 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3526 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3527
3528 if (unlikely(cmd_buffer->device->trace_bo))
3529 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3530 }
3531
3532 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3533 VkPipelineBindPoint bind_point)
3534 {
3535 struct radv_descriptor_state *descriptors_state =
3536 radv_get_descriptors_state(cmd_buffer, bind_point);
3537
3538 descriptors_state->dirty |= descriptors_state->valid;
3539 }
3540
3541 void radv_CmdBindPipeline(
3542 VkCommandBuffer commandBuffer,
3543 VkPipelineBindPoint pipelineBindPoint,
3544 VkPipeline _pipeline)
3545 {
3546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3547 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3548
3549 switch (pipelineBindPoint) {
3550 case VK_PIPELINE_BIND_POINT_COMPUTE:
3551 if (cmd_buffer->state.compute_pipeline == pipeline)
3552 return;
3553 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3554
3555 cmd_buffer->state.compute_pipeline = pipeline;
3556 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3557 break;
3558 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3559 if (cmd_buffer->state.pipeline == pipeline)
3560 return;
3561 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3562
3563 cmd_buffer->state.pipeline = pipeline;
3564 if (!pipeline)
3565 break;
3566
3567 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3568 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3569
3570 /* the new vertex shader might not have the same user regs */
3571 cmd_buffer->state.last_first_instance = -1;
3572 cmd_buffer->state.last_vertex_offset = -1;
3573
3574 /* Prefetch all pipeline shaders at first draw time. */
3575 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3576
3577 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3578 radv_bind_streamout_state(cmd_buffer, pipeline);
3579
3580 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3581 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3582 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3583 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3584
3585 if (radv_pipeline_has_tess(pipeline))
3586 cmd_buffer->tess_rings_needed = true;
3587 break;
3588 default:
3589 assert(!"invalid bind point");
3590 break;
3591 }
3592 }
3593
3594 void radv_CmdSetViewport(
3595 VkCommandBuffer commandBuffer,
3596 uint32_t firstViewport,
3597 uint32_t viewportCount,
3598 const VkViewport* pViewports)
3599 {
3600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3601 struct radv_cmd_state *state = &cmd_buffer->state;
3602 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3603
3604 assert(firstViewport < MAX_VIEWPORTS);
3605 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3606
3607 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3608 pViewports, viewportCount * sizeof(*pViewports))) {
3609 return;
3610 }
3611
3612 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3613 viewportCount * sizeof(*pViewports));
3614
3615 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3616 }
3617
3618 void radv_CmdSetScissor(
3619 VkCommandBuffer commandBuffer,
3620 uint32_t firstScissor,
3621 uint32_t scissorCount,
3622 const VkRect2D* pScissors)
3623 {
3624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3625 struct radv_cmd_state *state = &cmd_buffer->state;
3626 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3627
3628 assert(firstScissor < MAX_SCISSORS);
3629 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3630
3631 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3632 scissorCount * sizeof(*pScissors))) {
3633 return;
3634 }
3635
3636 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3637 scissorCount * sizeof(*pScissors));
3638
3639 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3640 }
3641
3642 void radv_CmdSetLineWidth(
3643 VkCommandBuffer commandBuffer,
3644 float lineWidth)
3645 {
3646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3647
3648 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3649 return;
3650
3651 cmd_buffer->state.dynamic.line_width = lineWidth;
3652 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3653 }
3654
3655 void radv_CmdSetDepthBias(
3656 VkCommandBuffer commandBuffer,
3657 float depthBiasConstantFactor,
3658 float depthBiasClamp,
3659 float depthBiasSlopeFactor)
3660 {
3661 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3662 struct radv_cmd_state *state = &cmd_buffer->state;
3663
3664 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3665 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3666 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3667 return;
3668 }
3669
3670 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3671 state->dynamic.depth_bias.clamp = depthBiasClamp;
3672 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3673
3674 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3675 }
3676
3677 void radv_CmdSetBlendConstants(
3678 VkCommandBuffer commandBuffer,
3679 const float blendConstants[4])
3680 {
3681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3682 struct radv_cmd_state *state = &cmd_buffer->state;
3683
3684 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3685 return;
3686
3687 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3688
3689 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3690 }
3691
3692 void radv_CmdSetDepthBounds(
3693 VkCommandBuffer commandBuffer,
3694 float minDepthBounds,
3695 float maxDepthBounds)
3696 {
3697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3698 struct radv_cmd_state *state = &cmd_buffer->state;
3699
3700 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3701 state->dynamic.depth_bounds.max == maxDepthBounds) {
3702 return;
3703 }
3704
3705 state->dynamic.depth_bounds.min = minDepthBounds;
3706 state->dynamic.depth_bounds.max = maxDepthBounds;
3707
3708 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3709 }
3710
3711 void radv_CmdSetStencilCompareMask(
3712 VkCommandBuffer commandBuffer,
3713 VkStencilFaceFlags faceMask,
3714 uint32_t compareMask)
3715 {
3716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3717 struct radv_cmd_state *state = &cmd_buffer->state;
3718 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3719 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3720
3721 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3722 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3723 return;
3724 }
3725
3726 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3727 state->dynamic.stencil_compare_mask.front = compareMask;
3728 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3729 state->dynamic.stencil_compare_mask.back = compareMask;
3730
3731 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3732 }
3733
3734 void radv_CmdSetStencilWriteMask(
3735 VkCommandBuffer commandBuffer,
3736 VkStencilFaceFlags faceMask,
3737 uint32_t writeMask)
3738 {
3739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3740 struct radv_cmd_state *state = &cmd_buffer->state;
3741 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3742 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3743
3744 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3745 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3746 return;
3747 }
3748
3749 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3750 state->dynamic.stencil_write_mask.front = writeMask;
3751 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3752 state->dynamic.stencil_write_mask.back = writeMask;
3753
3754 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3755 }
3756
3757 void radv_CmdSetStencilReference(
3758 VkCommandBuffer commandBuffer,
3759 VkStencilFaceFlags faceMask,
3760 uint32_t reference)
3761 {
3762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3763 struct radv_cmd_state *state = &cmd_buffer->state;
3764 bool front_same = state->dynamic.stencil_reference.front == reference;
3765 bool back_same = state->dynamic.stencil_reference.back == reference;
3766
3767 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3768 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3769 return;
3770 }
3771
3772 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3773 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3774 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3775 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3776
3777 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3778 }
3779
3780 void radv_CmdSetDiscardRectangleEXT(
3781 VkCommandBuffer commandBuffer,
3782 uint32_t firstDiscardRectangle,
3783 uint32_t discardRectangleCount,
3784 const VkRect2D* pDiscardRectangles)
3785 {
3786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3787 struct radv_cmd_state *state = &cmd_buffer->state;
3788 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3789
3790 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3791 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3792
3793 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3794 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3795 return;
3796 }
3797
3798 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3799 pDiscardRectangles, discardRectangleCount);
3800
3801 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3802 }
3803
3804 void radv_CmdSetSampleLocationsEXT(
3805 VkCommandBuffer commandBuffer,
3806 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3807 {
3808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3809 struct radv_cmd_state *state = &cmd_buffer->state;
3810
3811 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3812
3813 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3814 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3815 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3816 typed_memcpy(&state->dynamic.sample_location.locations[0],
3817 pSampleLocationsInfo->pSampleLocations,
3818 pSampleLocationsInfo->sampleLocationsCount);
3819
3820 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3821 }
3822
3823 void radv_CmdExecuteCommands(
3824 VkCommandBuffer commandBuffer,
3825 uint32_t commandBufferCount,
3826 const VkCommandBuffer* pCmdBuffers)
3827 {
3828 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3829
3830 assert(commandBufferCount > 0);
3831
3832 /* Emit pending flushes on primary prior to executing secondary */
3833 si_emit_cache_flush(primary);
3834
3835 for (uint32_t i = 0; i < commandBufferCount; i++) {
3836 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3837
3838 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3839 secondary->scratch_size_needed);
3840 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3841 secondary->compute_scratch_size_needed);
3842
3843 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3844 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3845 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3846 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3847 if (secondary->tess_rings_needed)
3848 primary->tess_rings_needed = true;
3849 if (secondary->sample_positions_needed)
3850 primary->sample_positions_needed = true;
3851
3852 if (!secondary->state.framebuffer &&
3853 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3854 /* Emit the framebuffer state from primary if secondary
3855 * has been recorded without a framebuffer, otherwise
3856 * fast color/depth clears can't work.
3857 */
3858 radv_emit_framebuffer_state(primary);
3859 }
3860
3861 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3862
3863
3864 /* When the secondary command buffer is compute only we don't
3865 * need to re-emit the current graphics pipeline.
3866 */
3867 if (secondary->state.emitted_pipeline) {
3868 primary->state.emitted_pipeline =
3869 secondary->state.emitted_pipeline;
3870 }
3871
3872 /* When the secondary command buffer is graphics only we don't
3873 * need to re-emit the current compute pipeline.
3874 */
3875 if (secondary->state.emitted_compute_pipeline) {
3876 primary->state.emitted_compute_pipeline =
3877 secondary->state.emitted_compute_pipeline;
3878 }
3879
3880 /* Only re-emit the draw packets when needed. */
3881 if (secondary->state.last_primitive_reset_en != -1) {
3882 primary->state.last_primitive_reset_en =
3883 secondary->state.last_primitive_reset_en;
3884 }
3885
3886 if (secondary->state.last_primitive_reset_index) {
3887 primary->state.last_primitive_reset_index =
3888 secondary->state.last_primitive_reset_index;
3889 }
3890
3891 if (secondary->state.last_ia_multi_vgt_param) {
3892 primary->state.last_ia_multi_vgt_param =
3893 secondary->state.last_ia_multi_vgt_param;
3894 }
3895
3896 primary->state.last_first_instance = secondary->state.last_first_instance;
3897 primary->state.last_num_instances = secondary->state.last_num_instances;
3898 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3899
3900 if (secondary->state.last_index_type != -1) {
3901 primary->state.last_index_type =
3902 secondary->state.last_index_type;
3903 }
3904 }
3905
3906 /* After executing commands from secondary buffers we have to dirty
3907 * some states.
3908 */
3909 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3910 RADV_CMD_DIRTY_INDEX_BUFFER |
3911 RADV_CMD_DIRTY_DYNAMIC_ALL;
3912 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3913 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3914 }
3915
3916 VkResult radv_CreateCommandPool(
3917 VkDevice _device,
3918 const VkCommandPoolCreateInfo* pCreateInfo,
3919 const VkAllocationCallbacks* pAllocator,
3920 VkCommandPool* pCmdPool)
3921 {
3922 RADV_FROM_HANDLE(radv_device, device, _device);
3923 struct radv_cmd_pool *pool;
3924
3925 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3926 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3927 if (pool == NULL)
3928 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3929
3930 if (pAllocator)
3931 pool->alloc = *pAllocator;
3932 else
3933 pool->alloc = device->alloc;
3934
3935 list_inithead(&pool->cmd_buffers);
3936 list_inithead(&pool->free_cmd_buffers);
3937
3938 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3939
3940 *pCmdPool = radv_cmd_pool_to_handle(pool);
3941
3942 return VK_SUCCESS;
3943
3944 }
3945
3946 void radv_DestroyCommandPool(
3947 VkDevice _device,
3948 VkCommandPool commandPool,
3949 const VkAllocationCallbacks* pAllocator)
3950 {
3951 RADV_FROM_HANDLE(radv_device, device, _device);
3952 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3953
3954 if (!pool)
3955 return;
3956
3957 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3958 &pool->cmd_buffers, pool_link) {
3959 radv_cmd_buffer_destroy(cmd_buffer);
3960 }
3961
3962 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3963 &pool->free_cmd_buffers, pool_link) {
3964 radv_cmd_buffer_destroy(cmd_buffer);
3965 }
3966
3967 vk_free2(&device->alloc, pAllocator, pool);
3968 }
3969
3970 VkResult radv_ResetCommandPool(
3971 VkDevice device,
3972 VkCommandPool commandPool,
3973 VkCommandPoolResetFlags flags)
3974 {
3975 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3976 VkResult result;
3977
3978 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3979 &pool->cmd_buffers, pool_link) {
3980 result = radv_reset_cmd_buffer(cmd_buffer);
3981 if (result != VK_SUCCESS)
3982 return result;
3983 }
3984
3985 return VK_SUCCESS;
3986 }
3987
3988 void radv_TrimCommandPool(
3989 VkDevice device,
3990 VkCommandPool commandPool,
3991 VkCommandPoolTrimFlags flags)
3992 {
3993 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3994
3995 if (!pool)
3996 return;
3997
3998 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3999 &pool->free_cmd_buffers, pool_link) {
4000 radv_cmd_buffer_destroy(cmd_buffer);
4001 }
4002 }
4003
4004 static void
4005 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4006 uint32_t subpass_id)
4007 {
4008 struct radv_cmd_state *state = &cmd_buffer->state;
4009 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4010
4011 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4012 cmd_buffer->cs, 4096);
4013
4014 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4015
4016 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4017
4018 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4019 const uint32_t a = subpass->attachments[i].attachment;
4020 if (a == VK_ATTACHMENT_UNUSED)
4021 continue;
4022
4023 radv_handle_subpass_image_transition(cmd_buffer,
4024 subpass->attachments[i],
4025 true);
4026 }
4027
4028 radv_cmd_buffer_clear_subpass(cmd_buffer);
4029
4030 assert(cmd_buffer->cs->cdw <= cdw_max);
4031 }
4032
4033 static void
4034 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4035 {
4036 struct radv_cmd_state *state = &cmd_buffer->state;
4037 const struct radv_subpass *subpass = state->subpass;
4038 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4039
4040 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4041
4042 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4043 const uint32_t a = subpass->attachments[i].attachment;
4044 if (a == VK_ATTACHMENT_UNUSED)
4045 continue;
4046
4047 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4048 continue;
4049
4050 VkImageLayout layout = state->pass->attachments[a].final_layout;
4051 struct radv_subpass_attachment att = { a, layout };
4052 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4053 }
4054 }
4055
4056 void radv_CmdBeginRenderPass(
4057 VkCommandBuffer commandBuffer,
4058 const VkRenderPassBeginInfo* pRenderPassBegin,
4059 VkSubpassContents contents)
4060 {
4061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4062 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4063 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4064 VkResult result;
4065
4066 cmd_buffer->state.framebuffer = framebuffer;
4067 cmd_buffer->state.pass = pass;
4068 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4069
4070 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4071 if (result != VK_SUCCESS)
4072 return;
4073
4074 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4075 if (result != VK_SUCCESS)
4076 return;
4077
4078 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4079 }
4080
4081 void radv_CmdBeginRenderPass2KHR(
4082 VkCommandBuffer commandBuffer,
4083 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4084 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4085 {
4086 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4087 pSubpassBeginInfo->contents);
4088 }
4089
4090 void radv_CmdNextSubpass(
4091 VkCommandBuffer commandBuffer,
4092 VkSubpassContents contents)
4093 {
4094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4095
4096 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4097 radv_cmd_buffer_end_subpass(cmd_buffer);
4098 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4099 }
4100
4101 void radv_CmdNextSubpass2KHR(
4102 VkCommandBuffer commandBuffer,
4103 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4104 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4105 {
4106 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4107 }
4108
4109 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4110 {
4111 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4112 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4113 if (!radv_get_shader(pipeline, stage))
4114 continue;
4115
4116 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4117 if (loc->sgpr_idx == -1)
4118 continue;
4119 uint32_t base_reg = pipeline->user_data_0[stage];
4120 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4121
4122 }
4123 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4124 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4125 if (loc->sgpr_idx != -1) {
4126 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4127 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4128 }
4129 }
4130 }
4131
4132 static void
4133 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4134 uint32_t vertex_count,
4135 bool use_opaque)
4136 {
4137 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4138 radeon_emit(cmd_buffer->cs, vertex_count);
4139 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4140 S_0287F0_USE_OPAQUE(use_opaque));
4141 }
4142
4143 static void
4144 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4145 uint64_t index_va,
4146 uint32_t index_count)
4147 {
4148 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4149 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4150 radeon_emit(cmd_buffer->cs, index_va);
4151 radeon_emit(cmd_buffer->cs, index_va >> 32);
4152 radeon_emit(cmd_buffer->cs, index_count);
4153 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4154 }
4155
4156 static void
4157 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4158 bool indexed,
4159 uint32_t draw_count,
4160 uint64_t count_va,
4161 uint32_t stride)
4162 {
4163 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4164 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4165 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4166 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4167 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4168 bool predicating = cmd_buffer->state.predicating;
4169 assert(base_reg);
4170
4171 /* just reset draw state for vertex data */
4172 cmd_buffer->state.last_first_instance = -1;
4173 cmd_buffer->state.last_num_instances = -1;
4174 cmd_buffer->state.last_vertex_offset = -1;
4175
4176 if (draw_count == 1 && !count_va && !draw_id_enable) {
4177 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4178 PKT3_DRAW_INDIRECT, 3, predicating));
4179 radeon_emit(cs, 0);
4180 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4181 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4182 radeon_emit(cs, di_src_sel);
4183 } else {
4184 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4185 PKT3_DRAW_INDIRECT_MULTI,
4186 8, predicating));
4187 radeon_emit(cs, 0);
4188 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4189 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4190 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4191 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4192 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4193 radeon_emit(cs, draw_count); /* count */
4194 radeon_emit(cs, count_va); /* count_addr */
4195 radeon_emit(cs, count_va >> 32);
4196 radeon_emit(cs, stride); /* stride */
4197 radeon_emit(cs, di_src_sel);
4198 }
4199 }
4200
4201 static void
4202 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4203 const struct radv_draw_info *info)
4204 {
4205 struct radv_cmd_state *state = &cmd_buffer->state;
4206 struct radeon_winsys *ws = cmd_buffer->device->ws;
4207 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4208
4209 if (info->indirect) {
4210 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4211 uint64_t count_va = 0;
4212
4213 va += info->indirect->offset + info->indirect_offset;
4214
4215 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4216
4217 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4218 radeon_emit(cs, 1);
4219 radeon_emit(cs, va);
4220 radeon_emit(cs, va >> 32);
4221
4222 if (info->count_buffer) {
4223 count_va = radv_buffer_get_va(info->count_buffer->bo);
4224 count_va += info->count_buffer->offset +
4225 info->count_buffer_offset;
4226
4227 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4228 }
4229
4230 if (!state->subpass->view_mask) {
4231 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4232 info->indexed,
4233 info->count,
4234 count_va,
4235 info->stride);
4236 } else {
4237 unsigned i;
4238 for_each_bit(i, state->subpass->view_mask) {
4239 radv_emit_view_index(cmd_buffer, i);
4240
4241 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4242 info->indexed,
4243 info->count,
4244 count_va,
4245 info->stride);
4246 }
4247 }
4248 } else {
4249 assert(state->pipeline->graphics.vtx_base_sgpr);
4250
4251 if (info->vertex_offset != state->last_vertex_offset ||
4252 info->first_instance != state->last_first_instance) {
4253 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4254 state->pipeline->graphics.vtx_emit_num);
4255
4256 radeon_emit(cs, info->vertex_offset);
4257 radeon_emit(cs, info->first_instance);
4258 if (state->pipeline->graphics.vtx_emit_num == 3)
4259 radeon_emit(cs, 0);
4260 state->last_first_instance = info->first_instance;
4261 state->last_vertex_offset = info->vertex_offset;
4262 }
4263
4264 if (state->last_num_instances != info->instance_count) {
4265 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4266 radeon_emit(cs, info->instance_count);
4267 state->last_num_instances = info->instance_count;
4268 }
4269
4270 if (info->indexed) {
4271 int index_size = state->index_type ? 4 : 2;
4272 uint64_t index_va;
4273
4274 index_va = state->index_va;
4275 index_va += info->first_index * index_size;
4276
4277 if (!state->subpass->view_mask) {
4278 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4279 index_va,
4280 info->count);
4281 } else {
4282 unsigned i;
4283 for_each_bit(i, state->subpass->view_mask) {
4284 radv_emit_view_index(cmd_buffer, i);
4285
4286 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4287 index_va,
4288 info->count);
4289 }
4290 }
4291 } else {
4292 if (!state->subpass->view_mask) {
4293 radv_cs_emit_draw_packet(cmd_buffer,
4294 info->count,
4295 !!info->strmout_buffer);
4296 } else {
4297 unsigned i;
4298 for_each_bit(i, state->subpass->view_mask) {
4299 radv_emit_view_index(cmd_buffer, i);
4300
4301 radv_cs_emit_draw_packet(cmd_buffer,
4302 info->count,
4303 !!info->strmout_buffer);
4304 }
4305 }
4306 }
4307 }
4308 }
4309
4310 /*
4311 * Vega and raven have a bug which triggers if there are multiple context
4312 * register contexts active at the same time with different scissor values.
4313 *
4314 * There are two possible workarounds:
4315 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4316 * there is only ever 1 active set of scissor values at the same time.
4317 *
4318 * 2) Whenever the hardware switches contexts we have to set the scissor
4319 * registers again even if it is a noop. That way the new context gets
4320 * the correct scissor values.
4321 *
4322 * This implements option 2. radv_need_late_scissor_emission needs to
4323 * return true on affected HW if radv_emit_all_graphics_states sets
4324 * any context registers.
4325 */
4326 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4327 const struct radv_draw_info *info)
4328 {
4329 struct radv_cmd_state *state = &cmd_buffer->state;
4330
4331 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4332 return false;
4333
4334 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4335 return true;
4336
4337 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4338
4339 /* Index, vertex and streamout buffers don't change context regs, and
4340 * pipeline is already handled.
4341 */
4342 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4343 RADV_CMD_DIRTY_VERTEX_BUFFER |
4344 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4345 RADV_CMD_DIRTY_PIPELINE);
4346
4347 if (cmd_buffer->state.dirty & used_states)
4348 return true;
4349
4350 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4351 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4352 return true;
4353
4354 return false;
4355 }
4356
4357 static void
4358 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4359 const struct radv_draw_info *info)
4360 {
4361 bool late_scissor_emission;
4362
4363 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4364 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4365 radv_emit_rbplus_state(cmd_buffer);
4366
4367 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4368 radv_emit_graphics_pipeline(cmd_buffer);
4369
4370 /* This should be before the cmd_buffer->state.dirty is cleared
4371 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4372 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4373 late_scissor_emission =
4374 radv_need_late_scissor_emission(cmd_buffer, info);
4375
4376 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4377 radv_emit_framebuffer_state(cmd_buffer);
4378
4379 if (info->indexed) {
4380 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4381 radv_emit_index_buffer(cmd_buffer);
4382 } else {
4383 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4384 * so the state must be re-emitted before the next indexed
4385 * draw.
4386 */
4387 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4388 cmd_buffer->state.last_index_type = -1;
4389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4390 }
4391 }
4392
4393 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4394
4395 radv_emit_draw_registers(cmd_buffer, info);
4396
4397 if (late_scissor_emission)
4398 radv_emit_scissor(cmd_buffer);
4399 }
4400
4401 static void
4402 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4403 const struct radv_draw_info *info)
4404 {
4405 struct radeon_info *rad_info =
4406 &cmd_buffer->device->physical_device->rad_info;
4407 bool has_prefetch =
4408 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4409 bool pipeline_is_dirty =
4410 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4411 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4412
4413 MAYBE_UNUSED unsigned cdw_max =
4414 radeon_check_space(cmd_buffer->device->ws,
4415 cmd_buffer->cs, 4096);
4416
4417 if (likely(!info->indirect)) {
4418 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4419 * no workaround for indirect draws, but we can at least skip
4420 * direct draws.
4421 */
4422 if (unlikely(!info->instance_count))
4423 return;
4424
4425 /* Handle count == 0. */
4426 if (unlikely(!info->count && !info->strmout_buffer))
4427 return;
4428 }
4429
4430 /* Use optimal packet order based on whether we need to sync the
4431 * pipeline.
4432 */
4433 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4434 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4435 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4436 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4437 /* If we have to wait for idle, set all states first, so that
4438 * all SET packets are processed in parallel with previous draw
4439 * calls. Then upload descriptors, set shader pointers, and
4440 * draw, and prefetch at the end. This ensures that the time
4441 * the CUs are idle is very short. (there are only SET_SH
4442 * packets between the wait and the draw)
4443 */
4444 radv_emit_all_graphics_states(cmd_buffer, info);
4445 si_emit_cache_flush(cmd_buffer);
4446 /* <-- CUs are idle here --> */
4447
4448 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4449
4450 radv_emit_draw_packets(cmd_buffer, info);
4451 /* <-- CUs are busy here --> */
4452
4453 /* Start prefetches after the draw has been started. Both will
4454 * run in parallel, but starting the draw first is more
4455 * important.
4456 */
4457 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4458 radv_emit_prefetch_L2(cmd_buffer,
4459 cmd_buffer->state.pipeline, false);
4460 }
4461 } else {
4462 /* If we don't wait for idle, start prefetches first, then set
4463 * states, and draw at the end.
4464 */
4465 si_emit_cache_flush(cmd_buffer);
4466
4467 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4468 /* Only prefetch the vertex shader and VBO descriptors
4469 * in order to start the draw as soon as possible.
4470 */
4471 radv_emit_prefetch_L2(cmd_buffer,
4472 cmd_buffer->state.pipeline, true);
4473 }
4474
4475 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4476
4477 radv_emit_all_graphics_states(cmd_buffer, info);
4478 radv_emit_draw_packets(cmd_buffer, info);
4479
4480 /* Prefetch the remaining shaders after the draw has been
4481 * started.
4482 */
4483 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4484 radv_emit_prefetch_L2(cmd_buffer,
4485 cmd_buffer->state.pipeline, false);
4486 }
4487 }
4488
4489 /* Workaround for a VGT hang when streamout is enabled.
4490 * It must be done after drawing.
4491 */
4492 if (cmd_buffer->state.streamout.streamout_enabled &&
4493 (rad_info->family == CHIP_HAWAII ||
4494 rad_info->family == CHIP_TONGA ||
4495 rad_info->family == CHIP_FIJI)) {
4496 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4497 }
4498
4499 assert(cmd_buffer->cs->cdw <= cdw_max);
4500 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4501 }
4502
4503 void radv_CmdDraw(
4504 VkCommandBuffer commandBuffer,
4505 uint32_t vertexCount,
4506 uint32_t instanceCount,
4507 uint32_t firstVertex,
4508 uint32_t firstInstance)
4509 {
4510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4511 struct radv_draw_info info = {};
4512
4513 info.count = vertexCount;
4514 info.instance_count = instanceCount;
4515 info.first_instance = firstInstance;
4516 info.vertex_offset = firstVertex;
4517
4518 radv_draw(cmd_buffer, &info);
4519 }
4520
4521 void radv_CmdDrawIndexed(
4522 VkCommandBuffer commandBuffer,
4523 uint32_t indexCount,
4524 uint32_t instanceCount,
4525 uint32_t firstIndex,
4526 int32_t vertexOffset,
4527 uint32_t firstInstance)
4528 {
4529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4530 struct radv_draw_info info = {};
4531
4532 info.indexed = true;
4533 info.count = indexCount;
4534 info.instance_count = instanceCount;
4535 info.first_index = firstIndex;
4536 info.vertex_offset = vertexOffset;
4537 info.first_instance = firstInstance;
4538
4539 radv_draw(cmd_buffer, &info);
4540 }
4541
4542 void radv_CmdDrawIndirect(
4543 VkCommandBuffer commandBuffer,
4544 VkBuffer _buffer,
4545 VkDeviceSize offset,
4546 uint32_t drawCount,
4547 uint32_t stride)
4548 {
4549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4550 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4551 struct radv_draw_info info = {};
4552
4553 info.count = drawCount;
4554 info.indirect = buffer;
4555 info.indirect_offset = offset;
4556 info.stride = stride;
4557
4558 radv_draw(cmd_buffer, &info);
4559 }
4560
4561 void radv_CmdDrawIndexedIndirect(
4562 VkCommandBuffer commandBuffer,
4563 VkBuffer _buffer,
4564 VkDeviceSize offset,
4565 uint32_t drawCount,
4566 uint32_t stride)
4567 {
4568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4569 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4570 struct radv_draw_info info = {};
4571
4572 info.indexed = true;
4573 info.count = drawCount;
4574 info.indirect = buffer;
4575 info.indirect_offset = offset;
4576 info.stride = stride;
4577
4578 radv_draw(cmd_buffer, &info);
4579 }
4580
4581 void radv_CmdDrawIndirectCountKHR(
4582 VkCommandBuffer commandBuffer,
4583 VkBuffer _buffer,
4584 VkDeviceSize offset,
4585 VkBuffer _countBuffer,
4586 VkDeviceSize countBufferOffset,
4587 uint32_t maxDrawCount,
4588 uint32_t stride)
4589 {
4590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4591 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4592 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4593 struct radv_draw_info info = {};
4594
4595 info.count = maxDrawCount;
4596 info.indirect = buffer;
4597 info.indirect_offset = offset;
4598 info.count_buffer = count_buffer;
4599 info.count_buffer_offset = countBufferOffset;
4600 info.stride = stride;
4601
4602 radv_draw(cmd_buffer, &info);
4603 }
4604
4605 void radv_CmdDrawIndexedIndirectCountKHR(
4606 VkCommandBuffer commandBuffer,
4607 VkBuffer _buffer,
4608 VkDeviceSize offset,
4609 VkBuffer _countBuffer,
4610 VkDeviceSize countBufferOffset,
4611 uint32_t maxDrawCount,
4612 uint32_t stride)
4613 {
4614 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4615 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4616 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4617 struct radv_draw_info info = {};
4618
4619 info.indexed = true;
4620 info.count = maxDrawCount;
4621 info.indirect = buffer;
4622 info.indirect_offset = offset;
4623 info.count_buffer = count_buffer;
4624 info.count_buffer_offset = countBufferOffset;
4625 info.stride = stride;
4626
4627 radv_draw(cmd_buffer, &info);
4628 }
4629
4630 struct radv_dispatch_info {
4631 /**
4632 * Determine the layout of the grid (in block units) to be used.
4633 */
4634 uint32_t blocks[3];
4635
4636 /**
4637 * A starting offset for the grid. If unaligned is set, the offset
4638 * must still be aligned.
4639 */
4640 uint32_t offsets[3];
4641 /**
4642 * Whether it's an unaligned compute dispatch.
4643 */
4644 bool unaligned;
4645
4646 /**
4647 * Indirect compute parameters resource.
4648 */
4649 struct radv_buffer *indirect;
4650 uint64_t indirect_offset;
4651 };
4652
4653 static void
4654 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4655 const struct radv_dispatch_info *info)
4656 {
4657 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4658 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4659 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4660 struct radeon_winsys *ws = cmd_buffer->device->ws;
4661 bool predicating = cmd_buffer->state.predicating;
4662 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4663 struct radv_userdata_info *loc;
4664
4665 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4666 AC_UD_CS_GRID_SIZE);
4667
4668 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4669
4670 if (info->indirect) {
4671 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4672
4673 va += info->indirect->offset + info->indirect_offset;
4674
4675 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4676
4677 if (loc->sgpr_idx != -1) {
4678 for (unsigned i = 0; i < 3; ++i) {
4679 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4680 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4681 COPY_DATA_DST_SEL(COPY_DATA_REG));
4682 radeon_emit(cs, (va + 4 * i));
4683 radeon_emit(cs, (va + 4 * i) >> 32);
4684 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4685 + loc->sgpr_idx * 4) >> 2) + i);
4686 radeon_emit(cs, 0);
4687 }
4688 }
4689
4690 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4691 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4692 PKT3_SHADER_TYPE_S(1));
4693 radeon_emit(cs, va);
4694 radeon_emit(cs, va >> 32);
4695 radeon_emit(cs, dispatch_initiator);
4696 } else {
4697 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4698 PKT3_SHADER_TYPE_S(1));
4699 radeon_emit(cs, 1);
4700 radeon_emit(cs, va);
4701 radeon_emit(cs, va >> 32);
4702
4703 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4704 PKT3_SHADER_TYPE_S(1));
4705 radeon_emit(cs, 0);
4706 radeon_emit(cs, dispatch_initiator);
4707 }
4708 } else {
4709 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4710 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4711
4712 if (info->unaligned) {
4713 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4714 unsigned remainder[3];
4715
4716 /* If aligned, these should be an entire block size,
4717 * not 0.
4718 */
4719 remainder[0] = blocks[0] + cs_block_size[0] -
4720 align_u32_npot(blocks[0], cs_block_size[0]);
4721 remainder[1] = blocks[1] + cs_block_size[1] -
4722 align_u32_npot(blocks[1], cs_block_size[1]);
4723 remainder[2] = blocks[2] + cs_block_size[2] -
4724 align_u32_npot(blocks[2], cs_block_size[2]);
4725
4726 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4727 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4728 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4729
4730 for(unsigned i = 0; i < 3; ++i) {
4731 assert(offsets[i] % cs_block_size[i] == 0);
4732 offsets[i] /= cs_block_size[i];
4733 }
4734
4735 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4736 radeon_emit(cs,
4737 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4738 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4739 radeon_emit(cs,
4740 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4741 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4742 radeon_emit(cs,
4743 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4744 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4745
4746 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4747 }
4748
4749 if (loc->sgpr_idx != -1) {
4750 assert(loc->num_sgprs == 3);
4751
4752 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4753 loc->sgpr_idx * 4, 3);
4754 radeon_emit(cs, blocks[0]);
4755 radeon_emit(cs, blocks[1]);
4756 radeon_emit(cs, blocks[2]);
4757 }
4758
4759 if (offsets[0] || offsets[1] || offsets[2]) {
4760 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4761 radeon_emit(cs, offsets[0]);
4762 radeon_emit(cs, offsets[1]);
4763 radeon_emit(cs, offsets[2]);
4764
4765 /* The blocks in the packet are not counts but end values. */
4766 for (unsigned i = 0; i < 3; ++i)
4767 blocks[i] += offsets[i];
4768 } else {
4769 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4770 }
4771
4772 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4773 PKT3_SHADER_TYPE_S(1));
4774 radeon_emit(cs, blocks[0]);
4775 radeon_emit(cs, blocks[1]);
4776 radeon_emit(cs, blocks[2]);
4777 radeon_emit(cs, dispatch_initiator);
4778 }
4779
4780 assert(cmd_buffer->cs->cdw <= cdw_max);
4781 }
4782
4783 static void
4784 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4785 {
4786 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4787 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4788 }
4789
4790 static void
4791 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4792 const struct radv_dispatch_info *info)
4793 {
4794 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4795 bool has_prefetch =
4796 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4797 bool pipeline_is_dirty = pipeline &&
4798 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4799
4800 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4801 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4802 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4803 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4804 /* If we have to wait for idle, set all states first, so that
4805 * all SET packets are processed in parallel with previous draw
4806 * calls. Then upload descriptors, set shader pointers, and
4807 * dispatch, and prefetch at the end. This ensures that the
4808 * time the CUs are idle is very short. (there are only SET_SH
4809 * packets between the wait and the draw)
4810 */
4811 radv_emit_compute_pipeline(cmd_buffer);
4812 si_emit_cache_flush(cmd_buffer);
4813 /* <-- CUs are idle here --> */
4814
4815 radv_upload_compute_shader_descriptors(cmd_buffer);
4816
4817 radv_emit_dispatch_packets(cmd_buffer, info);
4818 /* <-- CUs are busy here --> */
4819
4820 /* Start prefetches after the dispatch has been started. Both
4821 * will run in parallel, but starting the dispatch first is
4822 * more important.
4823 */
4824 if (has_prefetch && pipeline_is_dirty) {
4825 radv_emit_shader_prefetch(cmd_buffer,
4826 pipeline->shaders[MESA_SHADER_COMPUTE]);
4827 }
4828 } else {
4829 /* If we don't wait for idle, start prefetches first, then set
4830 * states, and dispatch at the end.
4831 */
4832 si_emit_cache_flush(cmd_buffer);
4833
4834 if (has_prefetch && pipeline_is_dirty) {
4835 radv_emit_shader_prefetch(cmd_buffer,
4836 pipeline->shaders[MESA_SHADER_COMPUTE]);
4837 }
4838
4839 radv_upload_compute_shader_descriptors(cmd_buffer);
4840
4841 radv_emit_compute_pipeline(cmd_buffer);
4842 radv_emit_dispatch_packets(cmd_buffer, info);
4843 }
4844
4845 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4846 }
4847
4848 void radv_CmdDispatchBase(
4849 VkCommandBuffer commandBuffer,
4850 uint32_t base_x,
4851 uint32_t base_y,
4852 uint32_t base_z,
4853 uint32_t x,
4854 uint32_t y,
4855 uint32_t z)
4856 {
4857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4858 struct radv_dispatch_info info = {};
4859
4860 info.blocks[0] = x;
4861 info.blocks[1] = y;
4862 info.blocks[2] = z;
4863
4864 info.offsets[0] = base_x;
4865 info.offsets[1] = base_y;
4866 info.offsets[2] = base_z;
4867 radv_dispatch(cmd_buffer, &info);
4868 }
4869
4870 void radv_CmdDispatch(
4871 VkCommandBuffer commandBuffer,
4872 uint32_t x,
4873 uint32_t y,
4874 uint32_t z)
4875 {
4876 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4877 }
4878
4879 void radv_CmdDispatchIndirect(
4880 VkCommandBuffer commandBuffer,
4881 VkBuffer _buffer,
4882 VkDeviceSize offset)
4883 {
4884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4885 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4886 struct radv_dispatch_info info = {};
4887
4888 info.indirect = buffer;
4889 info.indirect_offset = offset;
4890
4891 radv_dispatch(cmd_buffer, &info);
4892 }
4893
4894 void radv_unaligned_dispatch(
4895 struct radv_cmd_buffer *cmd_buffer,
4896 uint32_t x,
4897 uint32_t y,
4898 uint32_t z)
4899 {
4900 struct radv_dispatch_info info = {};
4901
4902 info.blocks[0] = x;
4903 info.blocks[1] = y;
4904 info.blocks[2] = z;
4905 info.unaligned = 1;
4906
4907 radv_dispatch(cmd_buffer, &info);
4908 }
4909
4910 void radv_CmdEndRenderPass(
4911 VkCommandBuffer commandBuffer)
4912 {
4913 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4914
4915 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4916
4917 radv_cmd_buffer_end_subpass(cmd_buffer);
4918
4919 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4920 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4921
4922 cmd_buffer->state.pass = NULL;
4923 cmd_buffer->state.subpass = NULL;
4924 cmd_buffer->state.attachments = NULL;
4925 cmd_buffer->state.framebuffer = NULL;
4926 cmd_buffer->state.subpass_sample_locs = NULL;
4927 }
4928
4929 void radv_CmdEndRenderPass2KHR(
4930 VkCommandBuffer commandBuffer,
4931 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4932 {
4933 radv_CmdEndRenderPass(commandBuffer);
4934 }
4935
4936 /*
4937 * For HTILE we have the following interesting clear words:
4938 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4939 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4940 * 0xfffffff0: Clear depth to 1.0
4941 * 0x00000000: Clear depth to 0.0
4942 */
4943 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4944 struct radv_image *image,
4945 const VkImageSubresourceRange *range,
4946 uint32_t clear_word)
4947 {
4948 assert(range->baseMipLevel == 0);
4949 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4950 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4951 struct radv_cmd_state *state = &cmd_buffer->state;
4952 VkClearDepthStencilValue value = {};
4953
4954 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4955 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4956
4957 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4958
4959 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4960
4961 if (vk_format_is_stencil(image->vk_format))
4962 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4963
4964 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4965
4966 if (radv_image_is_tc_compat_htile(image)) {
4967 /* Initialize the TC-compat metada value to 0 because by
4968 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4969 * need have to conditionally update its value when performing
4970 * a fast depth clear.
4971 */
4972 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4973 }
4974 }
4975
4976 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4977 struct radv_image *image,
4978 VkImageLayout src_layout,
4979 VkImageLayout dst_layout,
4980 unsigned src_queue_mask,
4981 unsigned dst_queue_mask,
4982 const VkImageSubresourceRange *range,
4983 struct radv_sample_locations_state *sample_locs)
4984 {
4985 if (!radv_image_has_htile(image))
4986 return;
4987
4988 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4989 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4990
4991 if (radv_layout_is_htile_compressed(image, dst_layout,
4992 dst_queue_mask)) {
4993 clear_value = 0;
4994 }
4995
4996 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4997 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4998 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4999 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5000 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5001 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
5002 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
5003 VkImageSubresourceRange local_range = *range;
5004 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
5005 local_range.baseMipLevel = 0;
5006 local_range.levelCount = 1;
5007
5008 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5009 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5010
5011 radv_decompress_depth_image_inplace(cmd_buffer, image,
5012 &local_range, sample_locs);
5013
5014 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5015 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5016 }
5017 }
5018
5019 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5020 struct radv_image *image,
5021 const VkImageSubresourceRange *range,
5022 uint32_t value)
5023 {
5024 struct radv_cmd_state *state = &cmd_buffer->state;
5025
5026 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5027 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5028
5029 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5030
5031 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5032 }
5033
5034 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5035 struct radv_image *image,
5036 const VkImageSubresourceRange *range)
5037 {
5038 struct radv_cmd_state *state = &cmd_buffer->state;
5039 static const uint32_t fmask_clear_values[4] = {
5040 0x00000000,
5041 0x02020202,
5042 0xE4E4E4E4,
5043 0x76543210
5044 };
5045 uint32_t log2_samples = util_logbase2(image->info.samples);
5046 uint32_t value = fmask_clear_values[log2_samples];
5047
5048 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5049 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5050
5051 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5052
5053 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5054 }
5055
5056 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5057 struct radv_image *image,
5058 const VkImageSubresourceRange *range, uint32_t value)
5059 {
5060 struct radv_cmd_state *state = &cmd_buffer->state;
5061 unsigned size = 0;
5062
5063 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5064 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5065
5066 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5067
5068 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5069 /* When DCC is enabled with mipmaps, some levels might not
5070 * support fast clears and we have to initialize them as "fully
5071 * expanded".
5072 */
5073 /* Compute the size of all fast clearable DCC levels. */
5074 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5075 struct legacy_surf_level *surf_level =
5076 &image->planes[0].surface.u.legacy.level[i];
5077 unsigned dcc_fast_clear_size =
5078 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5079
5080 if (!dcc_fast_clear_size)
5081 break;
5082
5083 size = surf_level->dcc_offset + dcc_fast_clear_size;
5084 }
5085
5086 /* Initialize the mipmap levels without DCC. */
5087 if (size != image->planes[0].surface.dcc_size) {
5088 state->flush_bits |=
5089 radv_fill_buffer(cmd_buffer, image->bo,
5090 image->offset + image->dcc_offset + size,
5091 image->planes[0].surface.dcc_size - size,
5092 0xffffffff);
5093 }
5094 }
5095
5096 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5097 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5098 }
5099
5100 /**
5101 * Initialize DCC/FMASK/CMASK metadata for a color image.
5102 */
5103 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5104 struct radv_image *image,
5105 VkImageLayout src_layout,
5106 VkImageLayout dst_layout,
5107 unsigned src_queue_mask,
5108 unsigned dst_queue_mask,
5109 const VkImageSubresourceRange *range)
5110 {
5111 if (radv_image_has_cmask(image)) {
5112 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5113
5114 /* TODO: clarify this. */
5115 if (radv_image_has_fmask(image)) {
5116 value = 0xccccccccu;
5117 }
5118
5119 radv_initialise_cmask(cmd_buffer, image, range, value);
5120 }
5121
5122 if (radv_image_has_fmask(image)) {
5123 radv_initialize_fmask(cmd_buffer, image, range);
5124 }
5125
5126 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5127 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5128 bool need_decompress_pass = false;
5129
5130 if (radv_layout_dcc_compressed(image, dst_layout,
5131 dst_queue_mask)) {
5132 value = 0x20202020u;
5133 need_decompress_pass = true;
5134 }
5135
5136 radv_initialize_dcc(cmd_buffer, image, range, value);
5137
5138 radv_update_fce_metadata(cmd_buffer, image, range,
5139 need_decompress_pass);
5140 }
5141
5142 if (radv_image_has_cmask(image) ||
5143 radv_dcc_enabled(image, range->baseMipLevel)) {
5144 uint32_t color_values[2] = {};
5145 radv_set_color_clear_metadata(cmd_buffer, image, range,
5146 color_values);
5147 }
5148 }
5149
5150 /**
5151 * Handle color image transitions for DCC/FMASK/CMASK.
5152 */
5153 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5154 struct radv_image *image,
5155 VkImageLayout src_layout,
5156 VkImageLayout dst_layout,
5157 unsigned src_queue_mask,
5158 unsigned dst_queue_mask,
5159 const VkImageSubresourceRange *range)
5160 {
5161 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5162 radv_init_color_image_metadata(cmd_buffer, image,
5163 src_layout, dst_layout,
5164 src_queue_mask, dst_queue_mask,
5165 range);
5166 return;
5167 }
5168
5169 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5170 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5171 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5172 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5173 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5174 radv_decompress_dcc(cmd_buffer, image, range);
5175 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5176 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5177 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5178 }
5179 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5180 bool fce_eliminate = false, fmask_expand = false;
5181
5182 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5183 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5184 fce_eliminate = true;
5185 }
5186
5187 if (radv_image_has_fmask(image)) {
5188 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5189 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5190 /* A FMASK decompress is required before doing
5191 * a MSAA decompress using FMASK.
5192 */
5193 fmask_expand = true;
5194 }
5195 }
5196
5197 if (fce_eliminate || fmask_expand)
5198 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5199
5200 if (fmask_expand)
5201 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5202 }
5203 }
5204
5205 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5206 struct radv_image *image,
5207 VkImageLayout src_layout,
5208 VkImageLayout dst_layout,
5209 uint32_t src_family,
5210 uint32_t dst_family,
5211 const VkImageSubresourceRange *range,
5212 struct radv_sample_locations_state *sample_locs)
5213 {
5214 if (image->exclusive && src_family != dst_family) {
5215 /* This is an acquire or a release operation and there will be
5216 * a corresponding release/acquire. Do the transition in the
5217 * most flexible queue. */
5218
5219 assert(src_family == cmd_buffer->queue_family_index ||
5220 dst_family == cmd_buffer->queue_family_index);
5221
5222 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5223 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5224 return;
5225
5226 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5227 return;
5228
5229 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5230 (src_family == RADV_QUEUE_GENERAL ||
5231 dst_family == RADV_QUEUE_GENERAL))
5232 return;
5233 }
5234
5235 if (src_layout == dst_layout)
5236 return;
5237
5238 unsigned src_queue_mask =
5239 radv_image_queue_family_mask(image, src_family,
5240 cmd_buffer->queue_family_index);
5241 unsigned dst_queue_mask =
5242 radv_image_queue_family_mask(image, dst_family,
5243 cmd_buffer->queue_family_index);
5244
5245 if (vk_format_is_depth(image->vk_format)) {
5246 radv_handle_depth_image_transition(cmd_buffer, image,
5247 src_layout, dst_layout,
5248 src_queue_mask, dst_queue_mask,
5249 range, sample_locs);
5250 } else {
5251 radv_handle_color_image_transition(cmd_buffer, image,
5252 src_layout, dst_layout,
5253 src_queue_mask, dst_queue_mask,
5254 range);
5255 }
5256 }
5257
5258 struct radv_barrier_info {
5259 uint32_t eventCount;
5260 const VkEvent *pEvents;
5261 VkPipelineStageFlags srcStageMask;
5262 VkPipelineStageFlags dstStageMask;
5263 };
5264
5265 static void
5266 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5267 uint32_t memoryBarrierCount,
5268 const VkMemoryBarrier *pMemoryBarriers,
5269 uint32_t bufferMemoryBarrierCount,
5270 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5271 uint32_t imageMemoryBarrierCount,
5272 const VkImageMemoryBarrier *pImageMemoryBarriers,
5273 const struct radv_barrier_info *info)
5274 {
5275 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5276 enum radv_cmd_flush_bits src_flush_bits = 0;
5277 enum radv_cmd_flush_bits dst_flush_bits = 0;
5278
5279 for (unsigned i = 0; i < info->eventCount; ++i) {
5280 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5281 uint64_t va = radv_buffer_get_va(event->bo);
5282
5283 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5284
5285 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5286
5287 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5288 assert(cmd_buffer->cs->cdw <= cdw_max);
5289 }
5290
5291 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5292 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5293 NULL);
5294 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5295 NULL);
5296 }
5297
5298 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5299 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5300 NULL);
5301 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5302 NULL);
5303 }
5304
5305 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5306 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5307
5308 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5309 image);
5310 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5311 image);
5312 }
5313
5314 /* The Vulkan spec 1.1.98 says:
5315 *
5316 * "An execution dependency with only
5317 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5318 * will only prevent that stage from executing in subsequently
5319 * submitted commands. As this stage does not perform any actual
5320 * execution, this is not observable - in effect, it does not delay
5321 * processing of subsequent commands. Similarly an execution dependency
5322 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5323 * will effectively not wait for any prior commands to complete."
5324 */
5325 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5326 radv_stage_flush(cmd_buffer, info->srcStageMask);
5327 cmd_buffer->state.flush_bits |= src_flush_bits;
5328
5329 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5330 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5331
5332 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5333 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5334 SAMPLE_LOCATIONS_INFO_EXT);
5335 struct radv_sample_locations_state sample_locations = {};
5336
5337 if (sample_locs_info) {
5338 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5339 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5340 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5341 sample_locations.count = sample_locs_info->sampleLocationsCount;
5342 typed_memcpy(&sample_locations.locations[0],
5343 sample_locs_info->pSampleLocations,
5344 sample_locs_info->sampleLocationsCount);
5345 }
5346
5347 radv_handle_image_transition(cmd_buffer, image,
5348 pImageMemoryBarriers[i].oldLayout,
5349 pImageMemoryBarriers[i].newLayout,
5350 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5351 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5352 &pImageMemoryBarriers[i].subresourceRange,
5353 sample_locs_info ? &sample_locations : NULL);
5354 }
5355
5356 /* Make sure CP DMA is idle because the driver might have performed a
5357 * DMA operation for copying or filling buffers/images.
5358 */
5359 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5360 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5361 si_cp_dma_wait_for_idle(cmd_buffer);
5362
5363 cmd_buffer->state.flush_bits |= dst_flush_bits;
5364 }
5365
5366 void radv_CmdPipelineBarrier(
5367 VkCommandBuffer commandBuffer,
5368 VkPipelineStageFlags srcStageMask,
5369 VkPipelineStageFlags destStageMask,
5370 VkBool32 byRegion,
5371 uint32_t memoryBarrierCount,
5372 const VkMemoryBarrier* pMemoryBarriers,
5373 uint32_t bufferMemoryBarrierCount,
5374 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5375 uint32_t imageMemoryBarrierCount,
5376 const VkImageMemoryBarrier* pImageMemoryBarriers)
5377 {
5378 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5379 struct radv_barrier_info info;
5380
5381 info.eventCount = 0;
5382 info.pEvents = NULL;
5383 info.srcStageMask = srcStageMask;
5384 info.dstStageMask = destStageMask;
5385
5386 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5387 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5388 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5389 }
5390
5391
5392 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5393 struct radv_event *event,
5394 VkPipelineStageFlags stageMask,
5395 unsigned value)
5396 {
5397 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5398 uint64_t va = radv_buffer_get_va(event->bo);
5399
5400 si_emit_cache_flush(cmd_buffer);
5401
5402 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5403
5404 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5405
5406 /* Flags that only require a top-of-pipe event. */
5407 VkPipelineStageFlags top_of_pipe_flags =
5408 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5409
5410 /* Flags that only require a post-index-fetch event. */
5411 VkPipelineStageFlags post_index_fetch_flags =
5412 top_of_pipe_flags |
5413 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5414 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5415
5416 /* Make sure CP DMA is idle because the driver might have performed a
5417 * DMA operation for copying or filling buffers/images.
5418 */
5419 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5420 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5421 si_cp_dma_wait_for_idle(cmd_buffer);
5422
5423 /* TODO: Emit EOS events for syncing PS/CS stages. */
5424
5425 if (!(stageMask & ~top_of_pipe_flags)) {
5426 /* Just need to sync the PFP engine. */
5427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5429 S_370_WR_CONFIRM(1) |
5430 S_370_ENGINE_SEL(V_370_PFP));
5431 radeon_emit(cs, va);
5432 radeon_emit(cs, va >> 32);
5433 radeon_emit(cs, value);
5434 } else if (!(stageMask & ~post_index_fetch_flags)) {
5435 /* Sync ME because PFP reads index and indirect buffers. */
5436 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5437 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5438 S_370_WR_CONFIRM(1) |
5439 S_370_ENGINE_SEL(V_370_ME));
5440 radeon_emit(cs, va);
5441 radeon_emit(cs, va >> 32);
5442 radeon_emit(cs, value);
5443 } else {
5444 /* Otherwise, sync all prior GPU work using an EOP event. */
5445 si_cs_emit_write_event_eop(cs,
5446 cmd_buffer->device->physical_device->rad_info.chip_class,
5447 radv_cmd_buffer_uses_mec(cmd_buffer),
5448 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5449 EOP_DST_SEL_MEM,
5450 EOP_DATA_SEL_VALUE_32BIT, va, value,
5451 cmd_buffer->gfx9_eop_bug_va);
5452 }
5453
5454 assert(cmd_buffer->cs->cdw <= cdw_max);
5455 }
5456
5457 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5458 VkEvent _event,
5459 VkPipelineStageFlags stageMask)
5460 {
5461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5462 RADV_FROM_HANDLE(radv_event, event, _event);
5463
5464 write_event(cmd_buffer, event, stageMask, 1);
5465 }
5466
5467 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5468 VkEvent _event,
5469 VkPipelineStageFlags stageMask)
5470 {
5471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5472 RADV_FROM_HANDLE(radv_event, event, _event);
5473
5474 write_event(cmd_buffer, event, stageMask, 0);
5475 }
5476
5477 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5478 uint32_t eventCount,
5479 const VkEvent* pEvents,
5480 VkPipelineStageFlags srcStageMask,
5481 VkPipelineStageFlags dstStageMask,
5482 uint32_t memoryBarrierCount,
5483 const VkMemoryBarrier* pMemoryBarriers,
5484 uint32_t bufferMemoryBarrierCount,
5485 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5486 uint32_t imageMemoryBarrierCount,
5487 const VkImageMemoryBarrier* pImageMemoryBarriers)
5488 {
5489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5490 struct radv_barrier_info info;
5491
5492 info.eventCount = eventCount;
5493 info.pEvents = pEvents;
5494 info.srcStageMask = 0;
5495
5496 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5497 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5498 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5499 }
5500
5501
5502 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5503 uint32_t deviceMask)
5504 {
5505 /* No-op */
5506 }
5507
5508 /* VK_EXT_conditional_rendering */
5509 void radv_CmdBeginConditionalRenderingEXT(
5510 VkCommandBuffer commandBuffer,
5511 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5512 {
5513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5514 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5515 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5516 bool draw_visible = true;
5517 uint64_t pred_value = 0;
5518 uint64_t va, new_va;
5519 unsigned pred_offset;
5520
5521 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5522
5523 /* By default, if the 32-bit value at offset in buffer memory is zero,
5524 * then the rendering commands are discarded, otherwise they are
5525 * executed as normal. If the inverted flag is set, all commands are
5526 * discarded if the value is non zero.
5527 */
5528 if (pConditionalRenderingBegin->flags &
5529 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5530 draw_visible = false;
5531 }
5532
5533 si_emit_cache_flush(cmd_buffer);
5534
5535 /* From the Vulkan spec 1.1.107:
5536 *
5537 * "If the 32-bit value at offset in buffer memory is zero, then the
5538 * rendering commands are discarded, otherwise they are executed as
5539 * normal. If the value of the predicate in buffer memory changes while
5540 * conditional rendering is active, the rendering commands may be
5541 * discarded in an implementation-dependent way. Some implementations
5542 * may latch the value of the predicate upon beginning conditional
5543 * rendering while others may read it before every rendering command."
5544 *
5545 * But, the AMD hardware treats the predicate as a 64-bit value which
5546 * means we need a workaround in the driver. Luckily, it's not required
5547 * to support if the value changes when predication is active.
5548 *
5549 * The workaround is as follows:
5550 * 1) allocate a 64-value in the upload BO and initialize it to 0
5551 * 2) copy the 32-bit predicate value to the upload BO
5552 * 3) use the new allocated VA address for predication
5553 *
5554 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5555 * in ME (+ sync PFP) instead of PFP.
5556 */
5557 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5558
5559 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5560
5561 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5562 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5563 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5564 COPY_DATA_WR_CONFIRM);
5565 radeon_emit(cs, va);
5566 radeon_emit(cs, va >> 32);
5567 radeon_emit(cs, new_va);
5568 radeon_emit(cs, new_va >> 32);
5569
5570 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5571 radeon_emit(cs, 0);
5572
5573 /* Enable predication for this command buffer. */
5574 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5575 cmd_buffer->state.predicating = true;
5576
5577 /* Store conditional rendering user info. */
5578 cmd_buffer->state.predication_type = draw_visible;
5579 cmd_buffer->state.predication_va = new_va;
5580 }
5581
5582 void radv_CmdEndConditionalRenderingEXT(
5583 VkCommandBuffer commandBuffer)
5584 {
5585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5586
5587 /* Disable predication for this command buffer. */
5588 si_emit_set_predication_state(cmd_buffer, false, 0);
5589 cmd_buffer->state.predicating = false;
5590
5591 /* Reset conditional rendering user info. */
5592 cmd_buffer->state.predication_type = -1;
5593 cmd_buffer->state.predication_va = 0;
5594 }
5595
5596 /* VK_EXT_transform_feedback */
5597 void radv_CmdBindTransformFeedbackBuffersEXT(
5598 VkCommandBuffer commandBuffer,
5599 uint32_t firstBinding,
5600 uint32_t bindingCount,
5601 const VkBuffer* pBuffers,
5602 const VkDeviceSize* pOffsets,
5603 const VkDeviceSize* pSizes)
5604 {
5605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5606 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5607 uint8_t enabled_mask = 0;
5608
5609 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5610 for (uint32_t i = 0; i < bindingCount; i++) {
5611 uint32_t idx = firstBinding + i;
5612
5613 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5614 sb[idx].offset = pOffsets[i];
5615 sb[idx].size = pSizes[i];
5616
5617 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5618 sb[idx].buffer->bo);
5619
5620 enabled_mask |= 1 << idx;
5621 }
5622
5623 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5624
5625 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5626 }
5627
5628 static void
5629 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5630 {
5631 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5632 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5633
5634 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5635 radeon_emit(cs,
5636 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5637 S_028B94_RAST_STREAM(0) |
5638 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5639 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5640 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5641 radeon_emit(cs, so->hw_enabled_mask &
5642 so->enabled_stream_buffers_mask);
5643
5644 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5645 }
5646
5647 static void
5648 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5649 {
5650 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5651 bool old_streamout_enabled = so->streamout_enabled;
5652 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5653
5654 so->streamout_enabled = enable;
5655
5656 so->hw_enabled_mask = so->enabled_mask |
5657 (so->enabled_mask << 4) |
5658 (so->enabled_mask << 8) |
5659 (so->enabled_mask << 12);
5660
5661 if ((old_streamout_enabled != so->streamout_enabled) ||
5662 (old_hw_enabled_mask != so->hw_enabled_mask))
5663 radv_emit_streamout_enable(cmd_buffer);
5664 }
5665
5666 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5667 {
5668 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5669 unsigned reg_strmout_cntl;
5670
5671 /* The register is at different places on different ASICs. */
5672 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5673 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5674 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5675 } else {
5676 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5677 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5678 }
5679
5680 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5681 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5682
5683 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5684 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5685 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5686 radeon_emit(cs, 0);
5687 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5688 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5689 radeon_emit(cs, 4); /* poll interval */
5690 }
5691
5692 static void
5693 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5694 uint32_t firstCounterBuffer,
5695 uint32_t counterBufferCount,
5696 const VkBuffer *pCounterBuffers,
5697 const VkDeviceSize *pCounterBufferOffsets)
5698
5699 {
5700 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5701 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5702 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5703 uint32_t i;
5704
5705 radv_flush_vgt_streamout(cmd_buffer);
5706
5707 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5708 for_each_bit(i, so->enabled_mask) {
5709 int32_t counter_buffer_idx = i - firstCounterBuffer;
5710 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5711 counter_buffer_idx = -1;
5712
5713 /* AMD GCN binds streamout buffers as shader resources.
5714 * VGT only counts primitives and tells the shader through
5715 * SGPRs what to do.
5716 */
5717 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5718 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5719 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5720
5721 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5722
5723 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5724 /* The array of counter buffers is optional. */
5725 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5726 uint64_t va = radv_buffer_get_va(buffer->bo);
5727
5728 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5729
5730 /* Append */
5731 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5732 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5733 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5734 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5735 radeon_emit(cs, 0); /* unused */
5736 radeon_emit(cs, 0); /* unused */
5737 radeon_emit(cs, va); /* src address lo */
5738 radeon_emit(cs, va >> 32); /* src address hi */
5739
5740 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5741 } else {
5742 /* Start from the beginning. */
5743 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5744 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5745 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5746 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5747 radeon_emit(cs, 0); /* unused */
5748 radeon_emit(cs, 0); /* unused */
5749 radeon_emit(cs, 0); /* unused */
5750 radeon_emit(cs, 0); /* unused */
5751 }
5752 }
5753
5754 radv_set_streamout_enable(cmd_buffer, true);
5755 }
5756
5757 void radv_CmdBeginTransformFeedbackEXT(
5758 VkCommandBuffer commandBuffer,
5759 uint32_t firstCounterBuffer,
5760 uint32_t counterBufferCount,
5761 const VkBuffer* pCounterBuffers,
5762 const VkDeviceSize* pCounterBufferOffsets)
5763 {
5764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5765
5766 radv_emit_streamout_begin(cmd_buffer,
5767 firstCounterBuffer, counterBufferCount,
5768 pCounterBuffers, pCounterBufferOffsets);
5769 }
5770
5771 static void
5772 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5773 uint32_t firstCounterBuffer,
5774 uint32_t counterBufferCount,
5775 const VkBuffer *pCounterBuffers,
5776 const VkDeviceSize *pCounterBufferOffsets)
5777 {
5778 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5780 uint32_t i;
5781
5782 radv_flush_vgt_streamout(cmd_buffer);
5783
5784 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5785 for_each_bit(i, so->enabled_mask) {
5786 int32_t counter_buffer_idx = i - firstCounterBuffer;
5787 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5788 counter_buffer_idx = -1;
5789
5790 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5791 /* The array of counters buffer is optional. */
5792 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5793 uint64_t va = radv_buffer_get_va(buffer->bo);
5794
5795 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5796
5797 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5798 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5799 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5800 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5801 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5802 radeon_emit(cs, va); /* dst address lo */
5803 radeon_emit(cs, va >> 32); /* dst address hi */
5804 radeon_emit(cs, 0); /* unused */
5805 radeon_emit(cs, 0); /* unused */
5806
5807 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5808 }
5809
5810 /* Deactivate transform feedback by zeroing the buffer size.
5811 * The counters (primitives generated, primitives emitted) may
5812 * be enabled even if there is not buffer bound. This ensures
5813 * that the primitives-emitted query won't increment.
5814 */
5815 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5816
5817 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5818 }
5819
5820 radv_set_streamout_enable(cmd_buffer, false);
5821 }
5822
5823 void radv_CmdEndTransformFeedbackEXT(
5824 VkCommandBuffer commandBuffer,
5825 uint32_t firstCounterBuffer,
5826 uint32_t counterBufferCount,
5827 const VkBuffer* pCounterBuffers,
5828 const VkDeviceSize* pCounterBufferOffsets)
5829 {
5830 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5831
5832 radv_emit_streamout_end(cmd_buffer,
5833 firstCounterBuffer, counterBufferCount,
5834 pCounterBuffers, pCounterBufferOffsets);
5835 }
5836
5837 void radv_CmdDrawIndirectByteCountEXT(
5838 VkCommandBuffer commandBuffer,
5839 uint32_t instanceCount,
5840 uint32_t firstInstance,
5841 VkBuffer _counterBuffer,
5842 VkDeviceSize counterBufferOffset,
5843 uint32_t counterOffset,
5844 uint32_t vertexStride)
5845 {
5846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5847 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5848 struct radv_draw_info info = {};
5849
5850 info.instance_count = instanceCount;
5851 info.first_instance = firstInstance;
5852 info.strmout_buffer = counterBuffer;
5853 info.strmout_buffer_offset = counterBufferOffset;
5854 info.stride = vertexStride;
5855
5856 radv_draw(cmd_buffer, &info);
5857 }
5858
5859 /* VK_AMD_buffer_marker */
5860 void radv_CmdWriteBufferMarkerAMD(
5861 VkCommandBuffer commandBuffer,
5862 VkPipelineStageFlagBits pipelineStage,
5863 VkBuffer dstBuffer,
5864 VkDeviceSize dstOffset,
5865 uint32_t marker)
5866 {
5867 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5868 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5869 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5870 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5871
5872 si_emit_cache_flush(cmd_buffer);
5873
5874 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5875 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5876 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5877 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5878 COPY_DATA_WR_CONFIRM);
5879 radeon_emit(cs, marker);
5880 radeon_emit(cs, 0);
5881 radeon_emit(cs, va);
5882 radeon_emit(cs, va >> 32);
5883 } else {
5884 si_cs_emit_write_event_eop(cs,
5885 cmd_buffer->device->physical_device->rad_info.chip_class,
5886 radv_cmd_buffer_uses_mec(cmd_buffer),
5887 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5888 EOP_DST_SEL_MEM,
5889 EOP_DATA_SEL_VALUE_32BIT,
5890 va, marker,
5891 cmd_buffer->gfx9_eop_bug_va);
5892 }
5893 }