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41435d0649e28fc80966870f9c41994d31f532de
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
436 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
437 S_370_WR_CONFIRM(1) |
438 S_370_ENGINE_SEL(V_370_ME));
439 radeon_emit(cs, va);
440 radeon_emit(cs, va >> 32);
441 radeon_emit_array(cs, data, count);
442 }
443
444 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
445 {
446 struct radv_device *device = cmd_buffer->device;
447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
452 va += 4;
453
454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
455
456 ++cmd_buffer->state.trace_id;
457 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
458 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
459 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
460 }
461
462 static void
463 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
464 enum radv_cmd_flush_bits flags)
465 {
466 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
467 uint32_t *ptr = NULL;
468 uint64_t va = 0;
469
470 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
472
473 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
474 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
475 cmd_buffer->gfx9_fence_offset;
476 ptr = &cmd_buffer->gfx9_fence_idx;
477 }
478
479 /* Force wait for graphics or compute engines to be idle. */
480 si_cs_emit_cache_flush(cmd_buffer->cs,
481 cmd_buffer->device->physical_device->rad_info.chip_class,
482 ptr, va,
483 radv_cmd_buffer_uses_mec(cmd_buffer),
484 flags, cmd_buffer->gfx9_eop_bug_va);
485 }
486
487 if (unlikely(cmd_buffer->device->trace_bo))
488 radv_cmd_buffer_trace_emit(cmd_buffer);
489 }
490
491 static void
492 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_pipeline *pipeline, enum ring_type ring)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
497 uint32_t data[2];
498 uint64_t va;
499
500 va = radv_buffer_get_va(device->trace_bo);
501
502 switch (ring) {
503 case RING_GFX:
504 va += 8;
505 break;
506 case RING_COMPUTE:
507 va += 16;
508 break;
509 default:
510 assert(!"invalid ring type");
511 }
512
513 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
514 cmd_buffer->cs, 6);
515
516 data[0] = (uintptr_t)pipeline;
517 data[1] = (uintptr_t)pipeline >> 32;
518
519 radv_emit_write_data_packet(cs, va, 2, data);
520 }
521
522 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
523 VkPipelineBindPoint bind_point,
524 struct radv_descriptor_set *set,
525 unsigned idx)
526 {
527 struct radv_descriptor_state *descriptors_state =
528 radv_get_descriptors_state(cmd_buffer, bind_point);
529
530 descriptors_state->sets[idx] = set;
531 if (set)
532 descriptors_state->valid |= (1u << idx);
533 else
534 descriptors_state->valid &= ~(1u << idx);
535 descriptors_state->dirty |= (1u << idx);
536 }
537
538 static void
539 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
540 VkPipelineBindPoint bind_point)
541 {
542 struct radv_descriptor_state *descriptors_state =
543 radv_get_descriptors_state(cmd_buffer, bind_point);
544 struct radv_device *device = cmd_buffer->device;
545 struct radeon_cmdbuf *cs = cmd_buffer->cs;
546 uint32_t data[MAX_SETS * 2] = {};
547 uint64_t va;
548 unsigned i;
549 va = radv_buffer_get_va(device->trace_bo) + 24;
550
551 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
552 cmd_buffer->cs, 4 + MAX_SETS * 2);
553
554 for_each_bit(i, descriptors_state->valid) {
555 struct radv_descriptor_set *set = descriptors_state->sets[i];
556 data[i * 2] = (uintptr_t)set;
557 data[i * 2 + 1] = (uintptr_t)set >> 32;
558 }
559
560 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
561 }
562
563 struct radv_userdata_info *
564 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
565 gl_shader_stage stage,
566 int idx)
567 {
568 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
569 return &shader->info.user_sgprs_locs.shader_data[idx];
570 }
571
572 static void
573 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
574 struct radv_pipeline *pipeline,
575 gl_shader_stage stage,
576 int idx, uint64_t va)
577 {
578 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
579 uint32_t base_reg = pipeline->user_data_0[stage];
580 if (loc->sgpr_idx == -1)
581 return;
582
583 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
584 assert(!loc->indirect);
585
586 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
587 base_reg + loc->sgpr_idx * 4, va, false);
588 }
589
590 static void
591 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
592 struct radv_pipeline *pipeline,
593 struct radv_descriptor_state *descriptors_state,
594 gl_shader_stage stage)
595 {
596 struct radv_device *device = cmd_buffer->device;
597 struct radeon_cmdbuf *cs = cmd_buffer->cs;
598 uint32_t sh_base = pipeline->user_data_0[stage];
599 struct radv_userdata_locations *locs =
600 &pipeline->shaders[stage]->info.user_sgprs_locs;
601 unsigned mask = locs->descriptor_sets_enabled;
602
603 mask &= descriptors_state->dirty & descriptors_state->valid;
604
605 while (mask) {
606 int start, count;
607
608 u_bit_scan_consecutive_range(&mask, &start, &count);
609
610 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
611 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
612
613 radv_emit_shader_pointer_head(cs, sh_offset, count,
614 HAVE_32BIT_POINTERS);
615 for (int i = 0; i < count; i++) {
616 struct radv_descriptor_set *set =
617 descriptors_state->sets[start + i];
618
619 radv_emit_shader_pointer_body(device, cs, set->va,
620 HAVE_32BIT_POINTERS);
621 }
622 }
623 }
624
625 static void
626 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline)
628 {
629 int num_samples = pipeline->graphics.ms.num_samples;
630 struct radv_multisample_state *ms = &pipeline->graphics.ms;
631 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
632
633 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
634 cmd_buffer->sample_positions_needed = true;
635
636 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
637 return;
638
639 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
640 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
641 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
642
643 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
644
645 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
646
647 /* GFX9: Flush DFSM when the AA mode changes. */
648 if (cmd_buffer->device->dfsm_allowed) {
649 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
650 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
651 }
652 }
653
654 static void
655 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
656 struct radv_shader_variant *shader)
657 {
658 uint64_t va;
659
660 if (!shader)
661 return;
662
663 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
664
665 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
666 }
667
668 static void
669 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_pipeline *pipeline,
671 bool vertex_stage_only)
672 {
673 struct radv_cmd_state *state = &cmd_buffer->state;
674 uint32_t mask = state->prefetch_L2_mask;
675
676 if (vertex_stage_only) {
677 /* Fast prefetch path for starting draws as soon as possible.
678 */
679 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
680 RADV_PREFETCH_VBO_DESCRIPTORS);
681 }
682
683 if (mask & RADV_PREFETCH_VS)
684 radv_emit_shader_prefetch(cmd_buffer,
685 pipeline->shaders[MESA_SHADER_VERTEX]);
686
687 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
688 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
689
690 if (mask & RADV_PREFETCH_TCS)
691 radv_emit_shader_prefetch(cmd_buffer,
692 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
693
694 if (mask & RADV_PREFETCH_TES)
695 radv_emit_shader_prefetch(cmd_buffer,
696 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
697
698 if (mask & RADV_PREFETCH_GS) {
699 radv_emit_shader_prefetch(cmd_buffer,
700 pipeline->shaders[MESA_SHADER_GEOMETRY]);
701 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
702 }
703
704 if (mask & RADV_PREFETCH_PS)
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_FRAGMENT]);
707
708 state->prefetch_L2_mask &= ~mask;
709 }
710
711 static void
712 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
713 {
714 if (!cmd_buffer->device->physical_device->rbplus_allowed)
715 return;
716
717 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
718 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
719 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
720
721 unsigned sx_ps_downconvert = 0;
722 unsigned sx_blend_opt_epsilon = 0;
723 unsigned sx_blend_opt_control = 0;
724
725 for (unsigned i = 0; i < subpass->color_count; ++i) {
726 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
727 continue;
728
729 int idx = subpass->color_attachments[i].attachment;
730 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
731
732 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
733 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
734 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
735 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
736
737 bool has_alpha, has_rgb;
738
739 /* Set if RGB and A are present. */
740 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
741
742 if (format == V_028C70_COLOR_8 ||
743 format == V_028C70_COLOR_16 ||
744 format == V_028C70_COLOR_32)
745 has_rgb = !has_alpha;
746 else
747 has_rgb = true;
748
749 /* Check the colormask and export format. */
750 if (!(colormask & 0x7))
751 has_rgb = false;
752 if (!(colormask & 0x8))
753 has_alpha = false;
754
755 if (spi_format == V_028714_SPI_SHADER_ZERO) {
756 has_rgb = false;
757 has_alpha = false;
758 }
759
760 /* Disable value checking for disabled channels. */
761 if (!has_rgb)
762 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
763 if (!has_alpha)
764 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
765
766 /* Enable down-conversion for 32bpp and smaller formats. */
767 switch (format) {
768 case V_028C70_COLOR_8:
769 case V_028C70_COLOR_8_8:
770 case V_028C70_COLOR_8_8_8_8:
771 /* For 1 and 2-channel formats, use the superset thereof. */
772 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
773 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
774 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
775 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
776 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
777 }
778 break;
779
780 case V_028C70_COLOR_5_6_5:
781 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
782 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
783 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
784 }
785 break;
786
787 case V_028C70_COLOR_1_5_5_5:
788 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
789 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
790 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
791 }
792 break;
793
794 case V_028C70_COLOR_4_4_4_4:
795 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
796 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
797 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
798 }
799 break;
800
801 case V_028C70_COLOR_32:
802 if (swap == V_028C70_SWAP_STD &&
803 spi_format == V_028714_SPI_SHADER_32_R)
804 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
805 else if (swap == V_028C70_SWAP_ALT_REV &&
806 spi_format == V_028714_SPI_SHADER_32_AR)
807 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
808 break;
809
810 case V_028C70_COLOR_16:
811 case V_028C70_COLOR_16_16:
812 /* For 1-channel formats, use the superset thereof. */
813 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
814 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
815 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
817 if (swap == V_028C70_SWAP_STD ||
818 swap == V_028C70_SWAP_STD_REV)
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
820 else
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
822 }
823 break;
824
825 case V_028C70_COLOR_10_11_11:
826 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
828 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
829 }
830 break;
831
832 case V_028C70_COLOR_2_10_10_10:
833 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
834 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
835 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
836 }
837 break;
838 }
839 }
840
841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
842 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
843 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
844 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
845 }
846
847 static void
848 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
849 {
850 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
851
852 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
853 return;
854
855 radv_update_multisample_state(cmd_buffer, pipeline);
856
857 cmd_buffer->scratch_size_needed =
858 MAX2(cmd_buffer->scratch_size_needed,
859 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
860
861 if (!cmd_buffer->state.emitted_pipeline ||
862 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
863 pipeline->graphics.can_use_guardband)
864 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
865
866 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
867
868 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
869 if (!pipeline->shaders[i])
870 continue;
871
872 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
873 pipeline->shaders[i]->bo);
874 }
875
876 if (radv_pipeline_has_gs(pipeline))
877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
878 pipeline->gs_copy_shader->bo);
879
880 if (unlikely(cmd_buffer->device->trace_bo))
881 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
882
883 cmd_buffer->state.emitted_pipeline = pipeline;
884
885 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
886 }
887
888 static void
889 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
890 {
891 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
892 cmd_buffer->state.dynamic.viewport.viewports);
893 }
894
895 static void
896 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
897 {
898 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
899
900 si_write_scissors(cmd_buffer->cs, 0, count,
901 cmd_buffer->state.dynamic.scissor.scissors,
902 cmd_buffer->state.dynamic.viewport.viewports,
903 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
904 }
905
906 static void
907 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
908 {
909 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
910 return;
911
912 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
913 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
914 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
915 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
916 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
917 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
918 S_028214_BR_Y(rect.offset.y + rect.extent.height));
919 }
920 }
921
922 static void
923 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
924 {
925 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
926
927 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
928 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
929 }
930
931 static void
932 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
933 {
934 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
935
936 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
937 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
938 }
939
940 static void
941 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
942 {
943 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
944
945 radeon_set_context_reg_seq(cmd_buffer->cs,
946 R_028430_DB_STENCILREFMASK, 2);
947 radeon_emit(cmd_buffer->cs,
948 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
949 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
950 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
951 S_028430_STENCILOPVAL(1));
952 radeon_emit(cmd_buffer->cs,
953 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
954 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
955 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
956 S_028434_STENCILOPVAL_BF(1));
957 }
958
959 static void
960 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
961 {
962 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
963
964 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
965 fui(d->depth_bounds.min));
966 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
967 fui(d->depth_bounds.max));
968 }
969
970 static void
971 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
972 {
973 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
974 unsigned slope = fui(d->depth_bias.slope * 16.0f);
975 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
976
977
978 radeon_set_context_reg_seq(cmd_buffer->cs,
979 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
980 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
981 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
982 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
983 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
985 }
986
987 static void
988 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
989 int index,
990 struct radv_attachment_info *att,
991 struct radv_image *image,
992 VkImageLayout layout)
993 {
994 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
995 struct radv_color_buffer_info *cb = &att->cb;
996 uint32_t cb_color_info = cb->cb_color_info;
997
998 if (!radv_layout_dcc_compressed(image, layout,
999 radv_image_queue_family_mask(image,
1000 cmd_buffer->queue_family_index,
1001 cmd_buffer->queue_family_index))) {
1002 cb_color_info &= C_028C70_DCC_ENABLE;
1003 }
1004
1005 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1006 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1007 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1008 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1010 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1011 radeon_emit(cmd_buffer->cs, cb_color_info);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1013 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1015 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1017 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1018
1019 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1020 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1021 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1022
1023 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1024 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1025 } else {
1026 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1027 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1031 radeon_emit(cmd_buffer->cs, cb_color_info);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1033 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1038
1039 if (is_vi) { /* DCC BASE */
1040 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1041 }
1042 }
1043 }
1044
1045 static void
1046 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1047 struct radv_ds_buffer_info *ds,
1048 struct radv_image *image, VkImageLayout layout,
1049 bool requires_cond_write)
1050 {
1051 uint32_t db_z_info = ds->db_z_info;
1052 uint32_t db_z_info_reg;
1053
1054 if (!radv_image_is_tc_compat_htile(image))
1055 return;
1056
1057 if (!radv_layout_has_htile(image, layout,
1058 radv_image_queue_family_mask(image,
1059 cmd_buffer->queue_family_index,
1060 cmd_buffer->queue_family_index))) {
1061 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1062 }
1063
1064 db_z_info &= C_028040_ZRANGE_PRECISION;
1065
1066 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1067 db_z_info_reg = R_028038_DB_Z_INFO;
1068 } else {
1069 db_z_info_reg = R_028040_DB_Z_INFO;
1070 }
1071
1072 /* When we don't know the last fast clear value we need to emit a
1073 * conditional packet, otherwise we can update DB_Z_INFO directly.
1074 */
1075 if (requires_cond_write) {
1076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1077
1078 const uint32_t write_space = 0 << 8; /* register */
1079 const uint32_t poll_space = 1 << 4; /* memory */
1080 const uint32_t function = 3 << 0; /* equal to the reference */
1081 const uint32_t options = write_space | poll_space | function;
1082 radeon_emit(cmd_buffer->cs, options);
1083
1084 /* poll address - location of the depth clear value */
1085 uint64_t va = radv_buffer_get_va(image->bo);
1086 va += image->offset + image->clear_value_offset;
1087
1088 /* In presence of stencil format, we have to adjust the base
1089 * address because the first value is the stencil clear value.
1090 */
1091 if (vk_format_is_stencil(image->vk_format))
1092 va += 4;
1093
1094 radeon_emit(cmd_buffer->cs, va);
1095 radeon_emit(cmd_buffer->cs, va >> 32);
1096
1097 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1098 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1099 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1100 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1101 radeon_emit(cmd_buffer->cs, db_z_info);
1102 } else {
1103 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1104 }
1105 }
1106
1107 static void
1108 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1109 struct radv_ds_buffer_info *ds,
1110 struct radv_image *image,
1111 VkImageLayout layout)
1112 {
1113 uint32_t db_z_info = ds->db_z_info;
1114 uint32_t db_stencil_info = ds->db_stencil_info;
1115
1116 if (!radv_layout_has_htile(image, layout,
1117 radv_image_queue_family_mask(image,
1118 cmd_buffer->queue_family_index,
1119 cmd_buffer->queue_family_index))) {
1120 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1121 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1122 }
1123
1124 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1125 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1126
1127
1128 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1129 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1130 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1131 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1132 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1133
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1135 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1136 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1137 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1138 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1139 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1142 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1145
1146 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1147 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1149 } else {
1150 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1151
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1153 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1154 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1155 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1156 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1157 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1161 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1162
1163 }
1164
1165 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1166 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1167
1168 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1169 ds->pa_su_poly_offset_db_fmt_cntl);
1170 }
1171
1172 /**
1173 * Update the fast clear depth/stencil values if the image is bound as a
1174 * depth/stencil buffer.
1175 */
1176 static void
1177 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1178 struct radv_image *image,
1179 VkClearDepthStencilValue ds_clear_value,
1180 VkImageAspectFlags aspects)
1181 {
1182 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1183 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1184 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1185 struct radv_attachment_info *att;
1186 uint32_t att_idx;
1187
1188 if (!framebuffer || !subpass)
1189 return;
1190
1191 att_idx = subpass->depth_stencil_attachment.attachment;
1192 if (att_idx == VK_ATTACHMENT_UNUSED)
1193 return;
1194
1195 att = &framebuffer->attachments[att_idx];
1196 if (att->attachment->image != image)
1197 return;
1198
1199 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1200 radeon_emit(cs, ds_clear_value.stencil);
1201 radeon_emit(cs, fui(ds_clear_value.depth));
1202
1203 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1204 * only needed when clearing Z to 0.0.
1205 */
1206 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1207 ds_clear_value.depth == 0.0) {
1208 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1209
1210 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1211 layout, false);
1212 }
1213 }
1214
1215 /**
1216 * Set the clear depth/stencil values to the image's metadata.
1217 */
1218 static void
1219 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1220 struct radv_image *image,
1221 VkClearDepthStencilValue ds_clear_value,
1222 VkImageAspectFlags aspects)
1223 {
1224 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1225 uint64_t va = radv_buffer_get_va(image->bo);
1226 unsigned reg_offset = 0, reg_count = 0;
1227
1228 va += image->offset + image->clear_value_offset;
1229
1230 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1231 ++reg_count;
1232 } else {
1233 ++reg_offset;
1234 va += 4;
1235 }
1236 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1237 ++reg_count;
1238
1239 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1240 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1241 S_370_WR_CONFIRM(1) |
1242 S_370_ENGINE_SEL(V_370_PFP));
1243 radeon_emit(cs, va);
1244 radeon_emit(cs, va >> 32);
1245 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1246 radeon_emit(cs, ds_clear_value.stencil);
1247 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1248 radeon_emit(cs, fui(ds_clear_value.depth));
1249 }
1250
1251 /**
1252 * Update the clear depth/stencil values for this image.
1253 */
1254 void
1255 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1256 struct radv_image *image,
1257 VkClearDepthStencilValue ds_clear_value,
1258 VkImageAspectFlags aspects)
1259 {
1260 assert(radv_image_has_htile(image));
1261
1262 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1263
1264 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1265 aspects);
1266 }
1267
1268 /**
1269 * Load the clear depth/stencil values from the image's metadata.
1270 */
1271 static void
1272 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1273 struct radv_image *image)
1274 {
1275 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1276 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1277 uint64_t va = radv_buffer_get_va(image->bo);
1278 unsigned reg_offset = 0, reg_count = 0;
1279
1280 va += image->offset + image->clear_value_offset;
1281
1282 if (!radv_image_has_htile(image))
1283 return;
1284
1285 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1286 ++reg_count;
1287 } else {
1288 ++reg_offset;
1289 va += 4;
1290 }
1291 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1292 ++reg_count;
1293
1294 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1295 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1296 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1297 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1298 radeon_emit(cs, va);
1299 radeon_emit(cs, va >> 32);
1300 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1301 radeon_emit(cs, 0);
1302
1303 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1304 radeon_emit(cs, 0);
1305 }
1306
1307 /*
1308 * With DCC some colors don't require CMASK elimination before being
1309 * used as a texture. This sets a predicate value to determine if the
1310 * cmask eliminate is required.
1311 */
1312 void
1313 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1314 struct radv_image *image,
1315 bool value)
1316 {
1317 uint64_t pred_val = value;
1318 uint64_t va = radv_buffer_get_va(image->bo);
1319 va += image->offset + image->dcc_pred_offset;
1320
1321 assert(radv_image_has_dcc(image));
1322
1323 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1324 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1325 S_370_WR_CONFIRM(1) |
1326 S_370_ENGINE_SEL(V_370_PFP));
1327 radeon_emit(cmd_buffer->cs, va);
1328 radeon_emit(cmd_buffer->cs, va >> 32);
1329 radeon_emit(cmd_buffer->cs, pred_val);
1330 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1331 }
1332
1333 /**
1334 * Update the fast clear color values if the image is bound as a color buffer.
1335 */
1336 static void
1337 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1338 struct radv_image *image,
1339 int cb_idx,
1340 uint32_t color_values[2])
1341 {
1342 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1343 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1344 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1345 struct radv_attachment_info *att;
1346 uint32_t att_idx;
1347
1348 if (!framebuffer || !subpass)
1349 return;
1350
1351 att_idx = subpass->color_attachments[cb_idx].attachment;
1352 if (att_idx == VK_ATTACHMENT_UNUSED)
1353 return;
1354
1355 att = &framebuffer->attachments[att_idx];
1356 if (att->attachment->image != image)
1357 return;
1358
1359 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1360 radeon_emit(cs, color_values[0]);
1361 radeon_emit(cs, color_values[1]);
1362 }
1363
1364 /**
1365 * Set the clear color values to the image's metadata.
1366 */
1367 static void
1368 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1369 struct radv_image *image,
1370 uint32_t color_values[2])
1371 {
1372 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1373 uint64_t va = radv_buffer_get_va(image->bo);
1374
1375 va += image->offset + image->clear_value_offset;
1376
1377 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1378
1379 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1380 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1381 S_370_WR_CONFIRM(1) |
1382 S_370_ENGINE_SEL(V_370_PFP));
1383 radeon_emit(cs, va);
1384 radeon_emit(cs, va >> 32);
1385 radeon_emit(cs, color_values[0]);
1386 radeon_emit(cs, color_values[1]);
1387 }
1388
1389 /**
1390 * Update the clear color values for this image.
1391 */
1392 void
1393 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int cb_idx,
1396 uint32_t color_values[2])
1397 {
1398 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1399
1400 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1401
1402 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1403 color_values);
1404 }
1405
1406 /**
1407 * Load the clear color values from the image's metadata.
1408 */
1409 static void
1410 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1411 struct radv_image *image,
1412 int cb_idx)
1413 {
1414 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1415 uint64_t va = radv_buffer_get_va(image->bo);
1416
1417 va += image->offset + image->clear_value_offset;
1418
1419 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1420 return;
1421
1422 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1423
1424 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1425 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1426 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1427 COPY_DATA_COUNT_SEL);
1428 radeon_emit(cs, va);
1429 radeon_emit(cs, va >> 32);
1430 radeon_emit(cs, reg >> 2);
1431 radeon_emit(cs, 0);
1432
1433 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1434 radeon_emit(cs, 0);
1435 }
1436
1437 static void
1438 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1439 {
1440 int i;
1441 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1442 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1443
1444 /* this may happen for inherited secondary recording */
1445 if (!framebuffer)
1446 return;
1447
1448 for (i = 0; i < 8; ++i) {
1449 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1450 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1451 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1452 continue;
1453 }
1454
1455 int idx = subpass->color_attachments[i].attachment;
1456 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1457 struct radv_image *image = att->attachment->image;
1458 VkImageLayout layout = subpass->color_attachments[i].layout;
1459
1460 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1461
1462 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1463 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1464
1465 radv_load_color_clear_metadata(cmd_buffer, image, i);
1466 }
1467
1468 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1469 int idx = subpass->depth_stencil_attachment.attachment;
1470 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1471 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1472 struct radv_image *image = att->attachment->image;
1473 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1474 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1475 cmd_buffer->queue_family_index,
1476 cmd_buffer->queue_family_index);
1477 /* We currently don't support writing decompressed HTILE */
1478 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1479 radv_layout_is_htile_compressed(image, layout, queue_mask));
1480
1481 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1482
1483 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1484 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1485 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1486 }
1487 radv_load_ds_clear_metadata(cmd_buffer, image);
1488 } else {
1489 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1491 else
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1493
1494 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1495 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1496 }
1497 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1498 S_028208_BR_X(framebuffer->width) |
1499 S_028208_BR_Y(framebuffer->height));
1500
1501 if (cmd_buffer->device->dfsm_allowed) {
1502 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1503 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1504 }
1505
1506 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1507 }
1508
1509 static void
1510 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1511 {
1512 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1513 struct radv_cmd_state *state = &cmd_buffer->state;
1514
1515 if (state->index_type != state->last_index_type) {
1516 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1517 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1518 2, state->index_type);
1519 } else {
1520 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1521 radeon_emit(cs, state->index_type);
1522 }
1523
1524 state->last_index_type = state->index_type;
1525 }
1526
1527 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1528 radeon_emit(cs, state->index_va);
1529 radeon_emit(cs, state->index_va >> 32);
1530
1531 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1532 radeon_emit(cs, state->max_index_count);
1533
1534 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1535 }
1536
1537 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1538 {
1539 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1540 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1541 uint32_t pa_sc_mode_cntl_1 =
1542 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1543 uint32_t db_count_control;
1544
1545 if(!cmd_buffer->state.active_occlusion_queries) {
1546 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1547 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1548 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1549 has_perfect_queries) {
1550 /* Re-enable out-of-order rasterization if the
1551 * bound pipeline supports it and if it's has
1552 * been disabled before starting any perfect
1553 * occlusion queries.
1554 */
1555 radeon_set_context_reg(cmd_buffer->cs,
1556 R_028A4C_PA_SC_MODE_CNTL_1,
1557 pa_sc_mode_cntl_1);
1558 }
1559 db_count_control = 0;
1560 } else {
1561 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1562 }
1563 } else {
1564 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1565 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1566
1567 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1568 db_count_control =
1569 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1570 S_028004_SAMPLE_RATE(sample_rate) |
1571 S_028004_ZPASS_ENABLE(1) |
1572 S_028004_SLICE_EVEN_ENABLE(1) |
1573 S_028004_SLICE_ODD_ENABLE(1);
1574
1575 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1576 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1577 has_perfect_queries) {
1578 /* If the bound pipeline has enabled
1579 * out-of-order rasterization, we should
1580 * disable it before starting any perfect
1581 * occlusion queries.
1582 */
1583 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1584
1585 radeon_set_context_reg(cmd_buffer->cs,
1586 R_028A4C_PA_SC_MODE_CNTL_1,
1587 pa_sc_mode_cntl_1);
1588 }
1589 } else {
1590 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1591 S_028004_SAMPLE_RATE(sample_rate);
1592 }
1593 }
1594
1595 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1596 }
1597
1598 static void
1599 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1600 {
1601 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1602
1603 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1604 radv_emit_viewport(cmd_buffer);
1605
1606 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1607 !cmd_buffer->device->physical_device->has_scissor_bug)
1608 radv_emit_scissor(cmd_buffer);
1609
1610 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1611 radv_emit_line_width(cmd_buffer);
1612
1613 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1614 radv_emit_blend_constants(cmd_buffer);
1615
1616 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1617 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1618 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1619 radv_emit_stencil(cmd_buffer);
1620
1621 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1622 radv_emit_depth_bounds(cmd_buffer);
1623
1624 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1625 radv_emit_depth_bias(cmd_buffer);
1626
1627 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1628 radv_emit_discard_rectangle(cmd_buffer);
1629
1630 cmd_buffer->state.dirty &= ~states;
1631 }
1632
1633 static void
1634 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1635 VkPipelineBindPoint bind_point)
1636 {
1637 struct radv_descriptor_state *descriptors_state =
1638 radv_get_descriptors_state(cmd_buffer, bind_point);
1639 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1640 unsigned bo_offset;
1641
1642 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1643 set->mapped_ptr,
1644 &bo_offset))
1645 return;
1646
1647 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1648 set->va += bo_offset;
1649 }
1650
1651 static void
1652 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1653 VkPipelineBindPoint bind_point)
1654 {
1655 struct radv_descriptor_state *descriptors_state =
1656 radv_get_descriptors_state(cmd_buffer, bind_point);
1657 uint32_t size = MAX_SETS * 2 * 4;
1658 uint32_t offset;
1659 void *ptr;
1660
1661 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1662 256, &offset, &ptr))
1663 return;
1664
1665 for (unsigned i = 0; i < MAX_SETS; i++) {
1666 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1667 uint64_t set_va = 0;
1668 struct radv_descriptor_set *set = descriptors_state->sets[i];
1669 if (descriptors_state->valid & (1u << i))
1670 set_va = set->va;
1671 uptr[0] = set_va & 0xffffffff;
1672 uptr[1] = set_va >> 32;
1673 }
1674
1675 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1676 va += offset;
1677
1678 if (cmd_buffer->state.pipeline) {
1679 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1680 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1681 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1682
1683 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1684 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1685 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1686
1687 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1688 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1689 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1690
1691 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1692 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1693 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1694
1695 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1696 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1697 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1698 }
1699
1700 if (cmd_buffer->state.compute_pipeline)
1701 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1702 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1703 }
1704
1705 static void
1706 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1707 VkShaderStageFlags stages)
1708 {
1709 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1710 VK_PIPELINE_BIND_POINT_COMPUTE :
1711 VK_PIPELINE_BIND_POINT_GRAPHICS;
1712 struct radv_descriptor_state *descriptors_state =
1713 radv_get_descriptors_state(cmd_buffer, bind_point);
1714
1715 if (!descriptors_state->dirty)
1716 return;
1717
1718 if (descriptors_state->push_dirty)
1719 radv_flush_push_descriptors(cmd_buffer, bind_point);
1720
1721 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1722 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1723 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1724 }
1725
1726 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1727 cmd_buffer->cs,
1728 MAX_SETS * MESA_SHADER_STAGES * 4);
1729
1730 if (cmd_buffer->state.pipeline) {
1731 radv_foreach_stage(stage, stages) {
1732 if (!cmd_buffer->state.pipeline->shaders[stage])
1733 continue;
1734
1735 radv_emit_descriptor_pointers(cmd_buffer,
1736 cmd_buffer->state.pipeline,
1737 descriptors_state, stage);
1738 }
1739 }
1740
1741 if (cmd_buffer->state.compute_pipeline &&
1742 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1743 radv_emit_descriptor_pointers(cmd_buffer,
1744 cmd_buffer->state.compute_pipeline,
1745 descriptors_state,
1746 MESA_SHADER_COMPUTE);
1747 }
1748
1749 descriptors_state->dirty = 0;
1750 descriptors_state->push_dirty = false;
1751
1752 if (unlikely(cmd_buffer->device->trace_bo))
1753 radv_save_descriptors(cmd_buffer, bind_point);
1754
1755 assert(cmd_buffer->cs->cdw <= cdw_max);
1756 }
1757
1758 static void
1759 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1760 VkShaderStageFlags stages)
1761 {
1762 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1763 ? cmd_buffer->state.compute_pipeline
1764 : cmd_buffer->state.pipeline;
1765 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1766 VK_PIPELINE_BIND_POINT_COMPUTE :
1767 VK_PIPELINE_BIND_POINT_GRAPHICS;
1768 struct radv_descriptor_state *descriptors_state =
1769 radv_get_descriptors_state(cmd_buffer, bind_point);
1770 struct radv_pipeline_layout *layout = pipeline->layout;
1771 struct radv_shader_variant *shader, *prev_shader;
1772 unsigned offset;
1773 void *ptr;
1774 uint64_t va;
1775
1776 stages &= cmd_buffer->push_constant_stages;
1777 if (!stages ||
1778 (!layout->push_constant_size && !layout->dynamic_offset_count))
1779 return;
1780
1781 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1782 16 * layout->dynamic_offset_count,
1783 256, &offset, &ptr))
1784 return;
1785
1786 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1787 memcpy((char*)ptr + layout->push_constant_size,
1788 descriptors_state->dynamic_buffers,
1789 16 * layout->dynamic_offset_count);
1790
1791 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1792 va += offset;
1793
1794 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1795 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1796
1797 prev_shader = NULL;
1798 radv_foreach_stage(stage, stages) {
1799 shader = radv_get_shader(pipeline, stage);
1800
1801 /* Avoid redundantly emitting the address for merged stages. */
1802 if (shader && shader != prev_shader) {
1803 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1804 AC_UD_PUSH_CONSTANTS, va);
1805
1806 prev_shader = shader;
1807 }
1808 }
1809
1810 cmd_buffer->push_constant_stages &= ~stages;
1811 assert(cmd_buffer->cs->cdw <= cdw_max);
1812 }
1813
1814 static void
1815 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1816 bool pipeline_is_dirty)
1817 {
1818 if ((pipeline_is_dirty ||
1819 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1820 cmd_buffer->state.pipeline->vertex_elements.count &&
1821 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1822 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1823 unsigned vb_offset;
1824 void *vb_ptr;
1825 uint32_t i = 0;
1826 uint32_t count = velems->count;
1827 uint64_t va;
1828
1829 /* allocate some descriptor state for vertex buffers */
1830 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1831 &vb_offset, &vb_ptr))
1832 return;
1833
1834 for (i = 0; i < count; i++) {
1835 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1836 uint32_t offset;
1837 int vb = velems->binding[i];
1838 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1839 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1840
1841 va = radv_buffer_get_va(buffer->bo);
1842
1843 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1844 va += offset + buffer->offset;
1845 desc[0] = va;
1846 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1847 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1848 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1849 else
1850 desc[2] = buffer->size - offset;
1851 desc[3] = velems->rsrc_word3[i];
1852 }
1853
1854 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1855 va += vb_offset;
1856
1857 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1858 AC_UD_VS_VERTEX_BUFFERS, va);
1859
1860 cmd_buffer->state.vb_va = va;
1861 cmd_buffer->state.vb_size = count * 16;
1862 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1863 }
1864 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1865 }
1866
1867 static void
1868 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1869 {
1870 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1871 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1872 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1873 }
1874
1875 static void
1876 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1877 bool instanced_draw, bool indirect_draw,
1878 uint32_t draw_vertex_count)
1879 {
1880 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1881 struct radv_cmd_state *state = &cmd_buffer->state;
1882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1883 uint32_t ia_multi_vgt_param;
1884 int32_t primitive_reset_en;
1885
1886 /* Draw state. */
1887 ia_multi_vgt_param =
1888 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1889 indirect_draw, draw_vertex_count);
1890
1891 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1892 if (info->chip_class >= GFX9) {
1893 radeon_set_uconfig_reg_idx(cs,
1894 R_030960_IA_MULTI_VGT_PARAM,
1895 4, ia_multi_vgt_param);
1896 } else if (info->chip_class >= CIK) {
1897 radeon_set_context_reg_idx(cs,
1898 R_028AA8_IA_MULTI_VGT_PARAM,
1899 1, ia_multi_vgt_param);
1900 } else {
1901 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1902 ia_multi_vgt_param);
1903 }
1904 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1905 }
1906
1907 /* Primitive restart. */
1908 primitive_reset_en =
1909 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1910
1911 if (primitive_reset_en != state->last_primitive_reset_en) {
1912 state->last_primitive_reset_en = primitive_reset_en;
1913 if (info->chip_class >= GFX9) {
1914 radeon_set_uconfig_reg(cs,
1915 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1916 primitive_reset_en);
1917 } else {
1918 radeon_set_context_reg(cs,
1919 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1920 primitive_reset_en);
1921 }
1922 }
1923
1924 if (primitive_reset_en) {
1925 uint32_t primitive_reset_index =
1926 state->index_type ? 0xffffffffu : 0xffffu;
1927
1928 if (primitive_reset_index != state->last_primitive_reset_index) {
1929 radeon_set_context_reg(cs,
1930 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1931 primitive_reset_index);
1932 state->last_primitive_reset_index = primitive_reset_index;
1933 }
1934 }
1935 }
1936
1937 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1938 VkPipelineStageFlags src_stage_mask)
1939 {
1940 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1941 VK_PIPELINE_STAGE_TRANSFER_BIT |
1942 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1943 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1944 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1945 }
1946
1947 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1948 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1949 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1950 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1951 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1952 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1953 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1954 VK_PIPELINE_STAGE_TRANSFER_BIT |
1955 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1956 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1957 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1958 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1959 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1960 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1961 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1962 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1963 }
1964 }
1965
1966 static enum radv_cmd_flush_bits
1967 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1968 VkAccessFlags src_flags,
1969 struct radv_image *image)
1970 {
1971 enum radv_cmd_flush_bits flush_bits = 0;
1972 uint32_t b;
1973 for_each_bit(b, src_flags) {
1974 switch ((VkAccessFlagBits)(1 << b)) {
1975 case VK_ACCESS_SHADER_WRITE_BIT:
1976 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1977 break;
1978 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1979 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1980 if (!image || (image && radv_image_has_CB_metadata(image))) {
1981 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1982 }
1983 break;
1984 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1985 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1986 if (!image || (image && radv_image_has_htile(image))) {
1987 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1988 }
1989 break;
1990 case VK_ACCESS_TRANSFER_WRITE_BIT:
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1992 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1993 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1994 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1995 RADV_CMD_FLAG_INV_GLOBAL_L2;
1996 break;
1997 default:
1998 break;
1999 }
2000 }
2001 return flush_bits;
2002 }
2003
2004 static enum radv_cmd_flush_bits
2005 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2006 VkAccessFlags dst_flags,
2007 struct radv_image *image)
2008 {
2009 enum radv_cmd_flush_bits flush_bits = 0;
2010 uint32_t b;
2011 for_each_bit(b, dst_flags) {
2012 switch ((VkAccessFlagBits)(1 << b)) {
2013 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2014 case VK_ACCESS_INDEX_READ_BIT:
2015 break;
2016 case VK_ACCESS_UNIFORM_READ_BIT:
2017 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2018 break;
2019 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2020 case VK_ACCESS_SHADER_READ_BIT:
2021 case VK_ACCESS_TRANSFER_READ_BIT:
2022 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2023 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2024 RADV_CMD_FLAG_INV_GLOBAL_L2;
2025 break;
2026 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2027 /* TODO: change to image && when the image gets passed
2028 * through from the subpass. */
2029 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2030 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2032 break;
2033 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2034 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2035 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2036 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2037 break;
2038 default:
2039 break;
2040 }
2041 }
2042 return flush_bits;
2043 }
2044
2045 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2046 {
2047 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2048 NULL);
2049 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2050 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2051 NULL);
2052 }
2053
2054 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2055 struct radv_subpass_attachment att)
2056 {
2057 unsigned idx = att.attachment;
2058 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2059 VkImageSubresourceRange range;
2060 range.aspectMask = 0;
2061 range.baseMipLevel = view->base_mip;
2062 range.levelCount = 1;
2063 range.baseArrayLayer = view->base_layer;
2064 range.layerCount = cmd_buffer->state.framebuffer->layers;
2065
2066 radv_handle_image_transition(cmd_buffer,
2067 view->image,
2068 cmd_buffer->state.attachments[idx].current_layout,
2069 att.layout, 0, 0, &range,
2070 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2071
2072 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2073
2074
2075 }
2076
2077 void
2078 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2079 const struct radv_subpass *subpass, bool transitions)
2080 {
2081 if (transitions) {
2082 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2083
2084 for (unsigned i = 0; i < subpass->color_count; ++i) {
2085 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2086 radv_handle_subpass_image_transition(cmd_buffer,
2087 subpass->color_attachments[i]);
2088 }
2089
2090 for (unsigned i = 0; i < subpass->input_count; ++i) {
2091 radv_handle_subpass_image_transition(cmd_buffer,
2092 subpass->input_attachments[i]);
2093 }
2094
2095 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2096 radv_handle_subpass_image_transition(cmd_buffer,
2097 subpass->depth_stencil_attachment);
2098 }
2099 }
2100
2101 cmd_buffer->state.subpass = subpass;
2102
2103 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2104 }
2105
2106 static VkResult
2107 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2108 struct radv_render_pass *pass,
2109 const VkRenderPassBeginInfo *info)
2110 {
2111 struct radv_cmd_state *state = &cmd_buffer->state;
2112
2113 if (pass->attachment_count == 0) {
2114 state->attachments = NULL;
2115 return VK_SUCCESS;
2116 }
2117
2118 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2119 pass->attachment_count *
2120 sizeof(state->attachments[0]),
2121 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2122 if (state->attachments == NULL) {
2123 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2124 return cmd_buffer->record_result;
2125 }
2126
2127 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2128 struct radv_render_pass_attachment *att = &pass->attachments[i];
2129 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2130 VkImageAspectFlags clear_aspects = 0;
2131
2132 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2133 /* color attachment */
2134 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2135 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2136 }
2137 } else {
2138 /* depthstencil attachment */
2139 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2140 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2141 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2142 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2143 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2144 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2145 }
2146 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2147 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2148 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2149 }
2150 }
2151
2152 state->attachments[i].pending_clear_aspects = clear_aspects;
2153 state->attachments[i].cleared_views = 0;
2154 if (clear_aspects && info) {
2155 assert(info->clearValueCount > i);
2156 state->attachments[i].clear_value = info->pClearValues[i];
2157 }
2158
2159 state->attachments[i].current_layout = att->initial_layout;
2160 }
2161
2162 return VK_SUCCESS;
2163 }
2164
2165 VkResult radv_AllocateCommandBuffers(
2166 VkDevice _device,
2167 const VkCommandBufferAllocateInfo *pAllocateInfo,
2168 VkCommandBuffer *pCommandBuffers)
2169 {
2170 RADV_FROM_HANDLE(radv_device, device, _device);
2171 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2172
2173 VkResult result = VK_SUCCESS;
2174 uint32_t i;
2175
2176 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2177
2178 if (!list_empty(&pool->free_cmd_buffers)) {
2179 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2180
2181 list_del(&cmd_buffer->pool_link);
2182 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2183
2184 result = radv_reset_cmd_buffer(cmd_buffer);
2185 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2186 cmd_buffer->level = pAllocateInfo->level;
2187
2188 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2189 } else {
2190 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2191 &pCommandBuffers[i]);
2192 }
2193 if (result != VK_SUCCESS)
2194 break;
2195 }
2196
2197 if (result != VK_SUCCESS) {
2198 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2199 i, pCommandBuffers);
2200
2201 /* From the Vulkan 1.0.66 spec:
2202 *
2203 * "vkAllocateCommandBuffers can be used to create multiple
2204 * command buffers. If the creation of any of those command
2205 * buffers fails, the implementation must destroy all
2206 * successfully created command buffer objects from this
2207 * command, set all entries of the pCommandBuffers array to
2208 * NULL and return the error."
2209 */
2210 memset(pCommandBuffers, 0,
2211 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2212 }
2213
2214 return result;
2215 }
2216
2217 void radv_FreeCommandBuffers(
2218 VkDevice device,
2219 VkCommandPool commandPool,
2220 uint32_t commandBufferCount,
2221 const VkCommandBuffer *pCommandBuffers)
2222 {
2223 for (uint32_t i = 0; i < commandBufferCount; i++) {
2224 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2225
2226 if (cmd_buffer) {
2227 if (cmd_buffer->pool) {
2228 list_del(&cmd_buffer->pool_link);
2229 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2230 } else
2231 radv_cmd_buffer_destroy(cmd_buffer);
2232
2233 }
2234 }
2235 }
2236
2237 VkResult radv_ResetCommandBuffer(
2238 VkCommandBuffer commandBuffer,
2239 VkCommandBufferResetFlags flags)
2240 {
2241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2242 return radv_reset_cmd_buffer(cmd_buffer);
2243 }
2244
2245 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2246 {
2247 struct radv_device *device = cmd_buffer->device;
2248 if (device->gfx_init) {
2249 uint64_t va = radv_buffer_get_va(device->gfx_init);
2250 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2251 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2252 radeon_emit(cmd_buffer->cs, va);
2253 radeon_emit(cmd_buffer->cs, va >> 32);
2254 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2255 } else
2256 si_init_config(cmd_buffer);
2257 }
2258
2259 VkResult radv_BeginCommandBuffer(
2260 VkCommandBuffer commandBuffer,
2261 const VkCommandBufferBeginInfo *pBeginInfo)
2262 {
2263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2264 VkResult result = VK_SUCCESS;
2265
2266 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2267 /* If the command buffer has already been resetted with
2268 * vkResetCommandBuffer, no need to do it again.
2269 */
2270 result = radv_reset_cmd_buffer(cmd_buffer);
2271 if (result != VK_SUCCESS)
2272 return result;
2273 }
2274
2275 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2276 cmd_buffer->state.last_primitive_reset_en = -1;
2277 cmd_buffer->state.last_index_type = -1;
2278 cmd_buffer->state.last_num_instances = -1;
2279 cmd_buffer->state.last_vertex_offset = -1;
2280 cmd_buffer->state.last_first_instance = -1;
2281 cmd_buffer->usage_flags = pBeginInfo->flags;
2282
2283 /* setup initial configuration into command buffer */
2284 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2285 switch (cmd_buffer->queue_family_index) {
2286 case RADV_QUEUE_GENERAL:
2287 emit_gfx_buffer_state(cmd_buffer);
2288 break;
2289 case RADV_QUEUE_COMPUTE:
2290 si_init_compute(cmd_buffer);
2291 break;
2292 case RADV_QUEUE_TRANSFER:
2293 default:
2294 break;
2295 }
2296 }
2297
2298 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2299 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2300 assert(pBeginInfo->pInheritanceInfo);
2301 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2302 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2303
2304 struct radv_subpass *subpass =
2305 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2306
2307 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2308 if (result != VK_SUCCESS)
2309 return result;
2310
2311 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2312 }
2313
2314 if (unlikely(cmd_buffer->device->trace_bo)) {
2315 struct radv_device *device = cmd_buffer->device;
2316
2317 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2318 device->trace_bo);
2319
2320 radv_cmd_buffer_trace_emit(cmd_buffer);
2321 }
2322
2323 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2324
2325 return result;
2326 }
2327
2328 void radv_CmdBindVertexBuffers(
2329 VkCommandBuffer commandBuffer,
2330 uint32_t firstBinding,
2331 uint32_t bindingCount,
2332 const VkBuffer* pBuffers,
2333 const VkDeviceSize* pOffsets)
2334 {
2335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2337 bool changed = false;
2338
2339 /* We have to defer setting up vertex buffer since we need the buffer
2340 * stride from the pipeline. */
2341
2342 assert(firstBinding + bindingCount <= MAX_VBS);
2343 for (uint32_t i = 0; i < bindingCount; i++) {
2344 uint32_t idx = firstBinding + i;
2345
2346 if (!changed &&
2347 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2348 vb[idx].offset != pOffsets[i])) {
2349 changed = true;
2350 }
2351
2352 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2353 vb[idx].offset = pOffsets[i];
2354
2355 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2356 vb[idx].buffer->bo);
2357 }
2358
2359 if (!changed) {
2360 /* No state changes. */
2361 return;
2362 }
2363
2364 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2365 }
2366
2367 void radv_CmdBindIndexBuffer(
2368 VkCommandBuffer commandBuffer,
2369 VkBuffer buffer,
2370 VkDeviceSize offset,
2371 VkIndexType indexType)
2372 {
2373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2374 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2375
2376 if (cmd_buffer->state.index_buffer == index_buffer &&
2377 cmd_buffer->state.index_offset == offset &&
2378 cmd_buffer->state.index_type == indexType) {
2379 /* No state changes. */
2380 return;
2381 }
2382
2383 cmd_buffer->state.index_buffer = index_buffer;
2384 cmd_buffer->state.index_offset = offset;
2385 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2386 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2387 cmd_buffer->state.index_va += index_buffer->offset + offset;
2388
2389 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2390 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2391 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2392 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2393 }
2394
2395
2396 static void
2397 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2398 VkPipelineBindPoint bind_point,
2399 struct radv_descriptor_set *set, unsigned idx)
2400 {
2401 struct radeon_winsys *ws = cmd_buffer->device->ws;
2402
2403 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2404 if (!set)
2405 return;
2406
2407 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2408
2409 if (!cmd_buffer->device->use_global_bo_list) {
2410 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2411 if (set->descriptors[j])
2412 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2413 }
2414
2415 if(set->bo)
2416 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2417 }
2418
2419 void radv_CmdBindDescriptorSets(
2420 VkCommandBuffer commandBuffer,
2421 VkPipelineBindPoint pipelineBindPoint,
2422 VkPipelineLayout _layout,
2423 uint32_t firstSet,
2424 uint32_t descriptorSetCount,
2425 const VkDescriptorSet* pDescriptorSets,
2426 uint32_t dynamicOffsetCount,
2427 const uint32_t* pDynamicOffsets)
2428 {
2429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2430 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2431 unsigned dyn_idx = 0;
2432
2433 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2434 struct radv_descriptor_state *descriptors_state =
2435 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2436
2437 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2438 unsigned idx = i + firstSet;
2439 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2440 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2441
2442 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2443 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2444 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2445 assert(dyn_idx < dynamicOffsetCount);
2446
2447 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2448 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2449 dst[0] = va;
2450 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2451 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2452 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2453 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2454 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2455 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2456 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2457 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2458 cmd_buffer->push_constant_stages |=
2459 set->layout->dynamic_shader_stages;
2460 }
2461 }
2462 }
2463
2464 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2465 struct radv_descriptor_set *set,
2466 struct radv_descriptor_set_layout *layout,
2467 VkPipelineBindPoint bind_point)
2468 {
2469 struct radv_descriptor_state *descriptors_state =
2470 radv_get_descriptors_state(cmd_buffer, bind_point);
2471 set->size = layout->size;
2472 set->layout = layout;
2473
2474 if (descriptors_state->push_set.capacity < set->size) {
2475 size_t new_size = MAX2(set->size, 1024);
2476 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2477 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2478
2479 free(set->mapped_ptr);
2480 set->mapped_ptr = malloc(new_size);
2481
2482 if (!set->mapped_ptr) {
2483 descriptors_state->push_set.capacity = 0;
2484 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2485 return false;
2486 }
2487
2488 descriptors_state->push_set.capacity = new_size;
2489 }
2490
2491 return true;
2492 }
2493
2494 void radv_meta_push_descriptor_set(
2495 struct radv_cmd_buffer* cmd_buffer,
2496 VkPipelineBindPoint pipelineBindPoint,
2497 VkPipelineLayout _layout,
2498 uint32_t set,
2499 uint32_t descriptorWriteCount,
2500 const VkWriteDescriptorSet* pDescriptorWrites)
2501 {
2502 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2503 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2504 unsigned bo_offset;
2505
2506 assert(set == 0);
2507 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2508
2509 push_set->size = layout->set[set].layout->size;
2510 push_set->layout = layout->set[set].layout;
2511
2512 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2513 &bo_offset,
2514 (void**) &push_set->mapped_ptr))
2515 return;
2516
2517 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2518 push_set->va += bo_offset;
2519
2520 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2521 radv_descriptor_set_to_handle(push_set),
2522 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2523
2524 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2525 }
2526
2527 void radv_CmdPushDescriptorSetKHR(
2528 VkCommandBuffer commandBuffer,
2529 VkPipelineBindPoint pipelineBindPoint,
2530 VkPipelineLayout _layout,
2531 uint32_t set,
2532 uint32_t descriptorWriteCount,
2533 const VkWriteDescriptorSet* pDescriptorWrites)
2534 {
2535 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2536 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2537 struct radv_descriptor_state *descriptors_state =
2538 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2539 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2540
2541 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2542
2543 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2544 layout->set[set].layout,
2545 pipelineBindPoint))
2546 return;
2547
2548 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2549 radv_descriptor_set_to_handle(push_set),
2550 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2551
2552 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2553 descriptors_state->push_dirty = true;
2554 }
2555
2556 void radv_CmdPushDescriptorSetWithTemplateKHR(
2557 VkCommandBuffer commandBuffer,
2558 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2559 VkPipelineLayout _layout,
2560 uint32_t set,
2561 const void* pData)
2562 {
2563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2564 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2565 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2566 struct radv_descriptor_state *descriptors_state =
2567 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2568 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2569
2570 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2571
2572 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2573 layout->set[set].layout,
2574 templ->bind_point))
2575 return;
2576
2577 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2578 descriptorUpdateTemplate, pData);
2579
2580 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2581 descriptors_state->push_dirty = true;
2582 }
2583
2584 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2585 VkPipelineLayout layout,
2586 VkShaderStageFlags stageFlags,
2587 uint32_t offset,
2588 uint32_t size,
2589 const void* pValues)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2593 cmd_buffer->push_constant_stages |= stageFlags;
2594 }
2595
2596 VkResult radv_EndCommandBuffer(
2597 VkCommandBuffer commandBuffer)
2598 {
2599 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2600
2601 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2602 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2603 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2604 si_emit_cache_flush(cmd_buffer);
2605 }
2606
2607 /* Make sure CP DMA is idle at the end of IBs because the kernel
2608 * doesn't wait for it.
2609 */
2610 si_cp_dma_wait_for_idle(cmd_buffer);
2611
2612 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2613
2614 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2615 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2616
2617 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2618
2619 return cmd_buffer->record_result;
2620 }
2621
2622 static void
2623 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2624 {
2625 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2626
2627 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2628 return;
2629
2630 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2631
2632 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2633 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2634
2635 cmd_buffer->compute_scratch_size_needed =
2636 MAX2(cmd_buffer->compute_scratch_size_needed,
2637 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2638
2639 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2640 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2641
2642 if (unlikely(cmd_buffer->device->trace_bo))
2643 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2644 }
2645
2646 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2647 VkPipelineBindPoint bind_point)
2648 {
2649 struct radv_descriptor_state *descriptors_state =
2650 radv_get_descriptors_state(cmd_buffer, bind_point);
2651
2652 descriptors_state->dirty |= descriptors_state->valid;
2653 }
2654
2655 void radv_CmdBindPipeline(
2656 VkCommandBuffer commandBuffer,
2657 VkPipelineBindPoint pipelineBindPoint,
2658 VkPipeline _pipeline)
2659 {
2660 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2661 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2662
2663 switch (pipelineBindPoint) {
2664 case VK_PIPELINE_BIND_POINT_COMPUTE:
2665 if (cmd_buffer->state.compute_pipeline == pipeline)
2666 return;
2667 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2668
2669 cmd_buffer->state.compute_pipeline = pipeline;
2670 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2671 break;
2672 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2673 if (cmd_buffer->state.pipeline == pipeline)
2674 return;
2675 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2676
2677 cmd_buffer->state.pipeline = pipeline;
2678 if (!pipeline)
2679 break;
2680
2681 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2682 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2683
2684 /* the new vertex shader might not have the same user regs */
2685 cmd_buffer->state.last_first_instance = -1;
2686 cmd_buffer->state.last_vertex_offset = -1;
2687
2688 /* Prefetch all pipeline shaders at first draw time. */
2689 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2690
2691 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2692
2693 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2694 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2695 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2696 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2697
2698 if (radv_pipeline_has_tess(pipeline))
2699 cmd_buffer->tess_rings_needed = true;
2700 break;
2701 default:
2702 assert(!"invalid bind point");
2703 break;
2704 }
2705 }
2706
2707 void radv_CmdSetViewport(
2708 VkCommandBuffer commandBuffer,
2709 uint32_t firstViewport,
2710 uint32_t viewportCount,
2711 const VkViewport* pViewports)
2712 {
2713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2714 struct radv_cmd_state *state = &cmd_buffer->state;
2715 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2716
2717 assert(firstViewport < MAX_VIEWPORTS);
2718 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2719
2720 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2721 viewportCount * sizeof(*pViewports));
2722
2723 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2724 }
2725
2726 void radv_CmdSetScissor(
2727 VkCommandBuffer commandBuffer,
2728 uint32_t firstScissor,
2729 uint32_t scissorCount,
2730 const VkRect2D* pScissors)
2731 {
2732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2733 struct radv_cmd_state *state = &cmd_buffer->state;
2734 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2735
2736 assert(firstScissor < MAX_SCISSORS);
2737 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2738
2739 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2740 scissorCount * sizeof(*pScissors));
2741
2742 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2743 }
2744
2745 void radv_CmdSetLineWidth(
2746 VkCommandBuffer commandBuffer,
2747 float lineWidth)
2748 {
2749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2750 cmd_buffer->state.dynamic.line_width = lineWidth;
2751 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2752 }
2753
2754 void radv_CmdSetDepthBias(
2755 VkCommandBuffer commandBuffer,
2756 float depthBiasConstantFactor,
2757 float depthBiasClamp,
2758 float depthBiasSlopeFactor)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761
2762 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2763 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2764 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2765
2766 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2767 }
2768
2769 void radv_CmdSetBlendConstants(
2770 VkCommandBuffer commandBuffer,
2771 const float blendConstants[4])
2772 {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2774
2775 memcpy(cmd_buffer->state.dynamic.blend_constants,
2776 blendConstants, sizeof(float) * 4);
2777
2778 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2779 }
2780
2781 void radv_CmdSetDepthBounds(
2782 VkCommandBuffer commandBuffer,
2783 float minDepthBounds,
2784 float maxDepthBounds)
2785 {
2786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2787
2788 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2789 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2790
2791 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2792 }
2793
2794 void radv_CmdSetStencilCompareMask(
2795 VkCommandBuffer commandBuffer,
2796 VkStencilFaceFlags faceMask,
2797 uint32_t compareMask)
2798 {
2799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2800
2801 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2802 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2803 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2804 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2805
2806 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2807 }
2808
2809 void radv_CmdSetStencilWriteMask(
2810 VkCommandBuffer commandBuffer,
2811 VkStencilFaceFlags faceMask,
2812 uint32_t writeMask)
2813 {
2814 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2815
2816 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2817 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2818 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2819 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2820
2821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2822 }
2823
2824 void radv_CmdSetStencilReference(
2825 VkCommandBuffer commandBuffer,
2826 VkStencilFaceFlags faceMask,
2827 uint32_t reference)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2830
2831 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2832 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2833 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2834 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2835
2836 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2837 }
2838
2839 void radv_CmdSetDiscardRectangleEXT(
2840 VkCommandBuffer commandBuffer,
2841 uint32_t firstDiscardRectangle,
2842 uint32_t discardRectangleCount,
2843 const VkRect2D* pDiscardRectangles)
2844 {
2845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2846 struct radv_cmd_state *state = &cmd_buffer->state;
2847 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2848
2849 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2850 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2851
2852 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2853 pDiscardRectangles, discardRectangleCount);
2854
2855 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2856 }
2857
2858 void radv_CmdExecuteCommands(
2859 VkCommandBuffer commandBuffer,
2860 uint32_t commandBufferCount,
2861 const VkCommandBuffer* pCmdBuffers)
2862 {
2863 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2864
2865 assert(commandBufferCount > 0);
2866
2867 /* Emit pending flushes on primary prior to executing secondary */
2868 si_emit_cache_flush(primary);
2869
2870 for (uint32_t i = 0; i < commandBufferCount; i++) {
2871 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2872
2873 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2874 secondary->scratch_size_needed);
2875 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2876 secondary->compute_scratch_size_needed);
2877
2878 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2879 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2880 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2881 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2882 if (secondary->tess_rings_needed)
2883 primary->tess_rings_needed = true;
2884 if (secondary->sample_positions_needed)
2885 primary->sample_positions_needed = true;
2886
2887 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2888
2889
2890 /* When the secondary command buffer is compute only we don't
2891 * need to re-emit the current graphics pipeline.
2892 */
2893 if (secondary->state.emitted_pipeline) {
2894 primary->state.emitted_pipeline =
2895 secondary->state.emitted_pipeline;
2896 }
2897
2898 /* When the secondary command buffer is graphics only we don't
2899 * need to re-emit the current compute pipeline.
2900 */
2901 if (secondary->state.emitted_compute_pipeline) {
2902 primary->state.emitted_compute_pipeline =
2903 secondary->state.emitted_compute_pipeline;
2904 }
2905
2906 /* Only re-emit the draw packets when needed. */
2907 if (secondary->state.last_primitive_reset_en != -1) {
2908 primary->state.last_primitive_reset_en =
2909 secondary->state.last_primitive_reset_en;
2910 }
2911
2912 if (secondary->state.last_primitive_reset_index) {
2913 primary->state.last_primitive_reset_index =
2914 secondary->state.last_primitive_reset_index;
2915 }
2916
2917 if (secondary->state.last_ia_multi_vgt_param) {
2918 primary->state.last_ia_multi_vgt_param =
2919 secondary->state.last_ia_multi_vgt_param;
2920 }
2921
2922 primary->state.last_first_instance = secondary->state.last_first_instance;
2923 primary->state.last_num_instances = secondary->state.last_num_instances;
2924 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2925
2926 if (secondary->state.last_index_type != -1) {
2927 primary->state.last_index_type =
2928 secondary->state.last_index_type;
2929 }
2930 }
2931
2932 /* After executing commands from secondary buffers we have to dirty
2933 * some states.
2934 */
2935 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2936 RADV_CMD_DIRTY_INDEX_BUFFER |
2937 RADV_CMD_DIRTY_DYNAMIC_ALL;
2938 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2939 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2940 }
2941
2942 VkResult radv_CreateCommandPool(
2943 VkDevice _device,
2944 const VkCommandPoolCreateInfo* pCreateInfo,
2945 const VkAllocationCallbacks* pAllocator,
2946 VkCommandPool* pCmdPool)
2947 {
2948 RADV_FROM_HANDLE(radv_device, device, _device);
2949 struct radv_cmd_pool *pool;
2950
2951 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2952 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2953 if (pool == NULL)
2954 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2955
2956 if (pAllocator)
2957 pool->alloc = *pAllocator;
2958 else
2959 pool->alloc = device->alloc;
2960
2961 list_inithead(&pool->cmd_buffers);
2962 list_inithead(&pool->free_cmd_buffers);
2963
2964 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2965
2966 *pCmdPool = radv_cmd_pool_to_handle(pool);
2967
2968 return VK_SUCCESS;
2969
2970 }
2971
2972 void radv_DestroyCommandPool(
2973 VkDevice _device,
2974 VkCommandPool commandPool,
2975 const VkAllocationCallbacks* pAllocator)
2976 {
2977 RADV_FROM_HANDLE(radv_device, device, _device);
2978 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2979
2980 if (!pool)
2981 return;
2982
2983 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2984 &pool->cmd_buffers, pool_link) {
2985 radv_cmd_buffer_destroy(cmd_buffer);
2986 }
2987
2988 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2989 &pool->free_cmd_buffers, pool_link) {
2990 radv_cmd_buffer_destroy(cmd_buffer);
2991 }
2992
2993 vk_free2(&device->alloc, pAllocator, pool);
2994 }
2995
2996 VkResult radv_ResetCommandPool(
2997 VkDevice device,
2998 VkCommandPool commandPool,
2999 VkCommandPoolResetFlags flags)
3000 {
3001 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3002 VkResult result;
3003
3004 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3005 &pool->cmd_buffers, pool_link) {
3006 result = radv_reset_cmd_buffer(cmd_buffer);
3007 if (result != VK_SUCCESS)
3008 return result;
3009 }
3010
3011 return VK_SUCCESS;
3012 }
3013
3014 void radv_TrimCommandPool(
3015 VkDevice device,
3016 VkCommandPool commandPool,
3017 VkCommandPoolTrimFlagsKHR flags)
3018 {
3019 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3020
3021 if (!pool)
3022 return;
3023
3024 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3025 &pool->free_cmd_buffers, pool_link) {
3026 radv_cmd_buffer_destroy(cmd_buffer);
3027 }
3028 }
3029
3030 void radv_CmdBeginRenderPass(
3031 VkCommandBuffer commandBuffer,
3032 const VkRenderPassBeginInfo* pRenderPassBegin,
3033 VkSubpassContents contents)
3034 {
3035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3036 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3037 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3038
3039 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3040 cmd_buffer->cs, 2048);
3041 MAYBE_UNUSED VkResult result;
3042
3043 cmd_buffer->state.framebuffer = framebuffer;
3044 cmd_buffer->state.pass = pass;
3045 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3046
3047 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3048 if (result != VK_SUCCESS)
3049 return;
3050
3051 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3052 assert(cmd_buffer->cs->cdw <= cdw_max);
3053
3054 radv_cmd_buffer_clear_subpass(cmd_buffer);
3055 }
3056
3057 void radv_CmdBeginRenderPass2KHR(
3058 VkCommandBuffer commandBuffer,
3059 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3060 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3061 {
3062 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3063 pSubpassBeginInfo->contents);
3064 }
3065
3066 void radv_CmdNextSubpass(
3067 VkCommandBuffer commandBuffer,
3068 VkSubpassContents contents)
3069 {
3070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3071
3072 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3073
3074 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3075 2048);
3076
3077 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3078 radv_cmd_buffer_clear_subpass(cmd_buffer);
3079 }
3080
3081 void radv_CmdNextSubpass2KHR(
3082 VkCommandBuffer commandBuffer,
3083 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3084 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3085 {
3086 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3087 }
3088
3089 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3090 {
3091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3092 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3093 if (!radv_get_shader(pipeline, stage))
3094 continue;
3095
3096 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3097 if (loc->sgpr_idx == -1)
3098 continue;
3099 uint32_t base_reg = pipeline->user_data_0[stage];
3100 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3101
3102 }
3103 if (pipeline->gs_copy_shader) {
3104 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3105 if (loc->sgpr_idx != -1) {
3106 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3107 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3108 }
3109 }
3110 }
3111
3112 static void
3113 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3114 uint32_t vertex_count)
3115 {
3116 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3117 radeon_emit(cmd_buffer->cs, vertex_count);
3118 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3119 S_0287F0_USE_OPAQUE(0));
3120 }
3121
3122 static void
3123 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3124 uint64_t index_va,
3125 uint32_t index_count)
3126 {
3127 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3128 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3129 radeon_emit(cmd_buffer->cs, index_va);
3130 radeon_emit(cmd_buffer->cs, index_va >> 32);
3131 radeon_emit(cmd_buffer->cs, index_count);
3132 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3133 }
3134
3135 static void
3136 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3137 bool indexed,
3138 uint32_t draw_count,
3139 uint64_t count_va,
3140 uint32_t stride)
3141 {
3142 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3143 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3144 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3145 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3146 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3147 assert(base_reg);
3148
3149 /* just reset draw state for vertex data */
3150 cmd_buffer->state.last_first_instance = -1;
3151 cmd_buffer->state.last_num_instances = -1;
3152 cmd_buffer->state.last_vertex_offset = -1;
3153
3154 if (draw_count == 1 && !count_va && !draw_id_enable) {
3155 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3156 PKT3_DRAW_INDIRECT, 3, false));
3157 radeon_emit(cs, 0);
3158 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3159 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3160 radeon_emit(cs, di_src_sel);
3161 } else {
3162 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3163 PKT3_DRAW_INDIRECT_MULTI,
3164 8, false));
3165 radeon_emit(cs, 0);
3166 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3167 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3168 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3169 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3170 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3171 radeon_emit(cs, draw_count); /* count */
3172 radeon_emit(cs, count_va); /* count_addr */
3173 radeon_emit(cs, count_va >> 32);
3174 radeon_emit(cs, stride); /* stride */
3175 radeon_emit(cs, di_src_sel);
3176 }
3177 }
3178
3179 struct radv_draw_info {
3180 /**
3181 * Number of vertices.
3182 */
3183 uint32_t count;
3184
3185 /**
3186 * Index of the first vertex.
3187 */
3188 int32_t vertex_offset;
3189
3190 /**
3191 * First instance id.
3192 */
3193 uint32_t first_instance;
3194
3195 /**
3196 * Number of instances.
3197 */
3198 uint32_t instance_count;
3199
3200 /**
3201 * First index (indexed draws only).
3202 */
3203 uint32_t first_index;
3204
3205 /**
3206 * Whether it's an indexed draw.
3207 */
3208 bool indexed;
3209
3210 /**
3211 * Indirect draw parameters resource.
3212 */
3213 struct radv_buffer *indirect;
3214 uint64_t indirect_offset;
3215 uint32_t stride;
3216
3217 /**
3218 * Draw count parameters resource.
3219 */
3220 struct radv_buffer *count_buffer;
3221 uint64_t count_buffer_offset;
3222 };
3223
3224 static void
3225 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3226 const struct radv_draw_info *info)
3227 {
3228 struct radv_cmd_state *state = &cmd_buffer->state;
3229 struct radeon_winsys *ws = cmd_buffer->device->ws;
3230 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3231
3232 if (info->indirect) {
3233 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3234 uint64_t count_va = 0;
3235
3236 va += info->indirect->offset + info->indirect_offset;
3237
3238 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3239
3240 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3241 radeon_emit(cs, 1);
3242 radeon_emit(cs, va);
3243 radeon_emit(cs, va >> 32);
3244
3245 if (info->count_buffer) {
3246 count_va = radv_buffer_get_va(info->count_buffer->bo);
3247 count_va += info->count_buffer->offset +
3248 info->count_buffer_offset;
3249
3250 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3251 }
3252
3253 if (!state->subpass->view_mask) {
3254 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3255 info->indexed,
3256 info->count,
3257 count_va,
3258 info->stride);
3259 } else {
3260 unsigned i;
3261 for_each_bit(i, state->subpass->view_mask) {
3262 radv_emit_view_index(cmd_buffer, i);
3263
3264 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3265 info->indexed,
3266 info->count,
3267 count_va,
3268 info->stride);
3269 }
3270 }
3271 } else {
3272 assert(state->pipeline->graphics.vtx_base_sgpr);
3273
3274 if (info->vertex_offset != state->last_vertex_offset ||
3275 info->first_instance != state->last_first_instance) {
3276 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3277 state->pipeline->graphics.vtx_emit_num);
3278
3279 radeon_emit(cs, info->vertex_offset);
3280 radeon_emit(cs, info->first_instance);
3281 if (state->pipeline->graphics.vtx_emit_num == 3)
3282 radeon_emit(cs, 0);
3283 state->last_first_instance = info->first_instance;
3284 state->last_vertex_offset = info->vertex_offset;
3285 }
3286
3287 if (state->last_num_instances != info->instance_count) {
3288 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3289 radeon_emit(cs, info->instance_count);
3290 state->last_num_instances = info->instance_count;
3291 }
3292
3293 if (info->indexed) {
3294 int index_size = state->index_type ? 4 : 2;
3295 uint64_t index_va;
3296
3297 index_va = state->index_va;
3298 index_va += info->first_index * index_size;
3299
3300 if (!state->subpass->view_mask) {
3301 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3302 index_va,
3303 info->count);
3304 } else {
3305 unsigned i;
3306 for_each_bit(i, state->subpass->view_mask) {
3307 radv_emit_view_index(cmd_buffer, i);
3308
3309 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3310 index_va,
3311 info->count);
3312 }
3313 }
3314 } else {
3315 if (!state->subpass->view_mask) {
3316 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3317 } else {
3318 unsigned i;
3319 for_each_bit(i, state->subpass->view_mask) {
3320 radv_emit_view_index(cmd_buffer, i);
3321
3322 radv_cs_emit_draw_packet(cmd_buffer,
3323 info->count);
3324 }
3325 }
3326 }
3327 }
3328 }
3329
3330 /*
3331 * Vega and raven have a bug which triggers if there are multiple context
3332 * register contexts active at the same time with different scissor values.
3333 *
3334 * There are two possible workarounds:
3335 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3336 * there is only ever 1 active set of scissor values at the same time.
3337 *
3338 * 2) Whenever the hardware switches contexts we have to set the scissor
3339 * registers again even if it is a noop. That way the new context gets
3340 * the correct scissor values.
3341 *
3342 * This implements option 2. radv_need_late_scissor_emission needs to
3343 * return true on affected HW if radv_emit_all_graphics_states sets
3344 * any context registers.
3345 */
3346 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3347 bool indexed_draw)
3348 {
3349 struct radv_cmd_state *state = &cmd_buffer->state;
3350
3351 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3352 return false;
3353
3354 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3355
3356 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3357 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3358
3359 /* Assume all state changes except these two can imply context rolls. */
3360 if (cmd_buffer->state.dirty & used_states)
3361 return true;
3362
3363 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3364 return true;
3365
3366 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3367 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3368 return true;
3369
3370 return false;
3371 }
3372
3373 static void
3374 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3375 const struct radv_draw_info *info)
3376 {
3377 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3378
3379 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3380 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3381 radv_emit_rbplus_state(cmd_buffer);
3382
3383 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3384 radv_emit_graphics_pipeline(cmd_buffer);
3385
3386 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3387 radv_emit_framebuffer_state(cmd_buffer);
3388
3389 if (info->indexed) {
3390 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3391 radv_emit_index_buffer(cmd_buffer);
3392 } else {
3393 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3394 * so the state must be re-emitted before the next indexed
3395 * draw.
3396 */
3397 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3398 cmd_buffer->state.last_index_type = -1;
3399 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3400 }
3401 }
3402
3403 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3404
3405 radv_emit_draw_registers(cmd_buffer, info->indexed,
3406 info->instance_count > 1, info->indirect,
3407 info->indirect ? 0 : info->count);
3408
3409 if (late_scissor_emission)
3410 radv_emit_scissor(cmd_buffer);
3411 }
3412
3413 static void
3414 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3415 const struct radv_draw_info *info)
3416 {
3417 bool has_prefetch =
3418 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3419 bool pipeline_is_dirty =
3420 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3421 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3422
3423 MAYBE_UNUSED unsigned cdw_max =
3424 radeon_check_space(cmd_buffer->device->ws,
3425 cmd_buffer->cs, 4096);
3426
3427 /* Use optimal packet order based on whether we need to sync the
3428 * pipeline.
3429 */
3430 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3431 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3432 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3433 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3434 /* If we have to wait for idle, set all states first, so that
3435 * all SET packets are processed in parallel with previous draw
3436 * calls. Then upload descriptors, set shader pointers, and
3437 * draw, and prefetch at the end. This ensures that the time
3438 * the CUs are idle is very short. (there are only SET_SH
3439 * packets between the wait and the draw)
3440 */
3441 radv_emit_all_graphics_states(cmd_buffer, info);
3442 si_emit_cache_flush(cmd_buffer);
3443 /* <-- CUs are idle here --> */
3444
3445 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3446
3447 radv_emit_draw_packets(cmd_buffer, info);
3448 /* <-- CUs are busy here --> */
3449
3450 /* Start prefetches after the draw has been started. Both will
3451 * run in parallel, but starting the draw first is more
3452 * important.
3453 */
3454 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3455 radv_emit_prefetch_L2(cmd_buffer,
3456 cmd_buffer->state.pipeline, false);
3457 }
3458 } else {
3459 /* If we don't wait for idle, start prefetches first, then set
3460 * states, and draw at the end.
3461 */
3462 si_emit_cache_flush(cmd_buffer);
3463
3464 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3465 /* Only prefetch the vertex shader and VBO descriptors
3466 * in order to start the draw as soon as possible.
3467 */
3468 radv_emit_prefetch_L2(cmd_buffer,
3469 cmd_buffer->state.pipeline, true);
3470 }
3471
3472 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3473
3474 radv_emit_all_graphics_states(cmd_buffer, info);
3475 radv_emit_draw_packets(cmd_buffer, info);
3476
3477 /* Prefetch the remaining shaders after the draw has been
3478 * started.
3479 */
3480 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3481 radv_emit_prefetch_L2(cmd_buffer,
3482 cmd_buffer->state.pipeline, false);
3483 }
3484 }
3485
3486 assert(cmd_buffer->cs->cdw <= cdw_max);
3487 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3488 }
3489
3490 void radv_CmdDraw(
3491 VkCommandBuffer commandBuffer,
3492 uint32_t vertexCount,
3493 uint32_t instanceCount,
3494 uint32_t firstVertex,
3495 uint32_t firstInstance)
3496 {
3497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3498 struct radv_draw_info info = {};
3499
3500 info.count = vertexCount;
3501 info.instance_count = instanceCount;
3502 info.first_instance = firstInstance;
3503 info.vertex_offset = firstVertex;
3504
3505 radv_draw(cmd_buffer, &info);
3506 }
3507
3508 void radv_CmdDrawIndexed(
3509 VkCommandBuffer commandBuffer,
3510 uint32_t indexCount,
3511 uint32_t instanceCount,
3512 uint32_t firstIndex,
3513 int32_t vertexOffset,
3514 uint32_t firstInstance)
3515 {
3516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3517 struct radv_draw_info info = {};
3518
3519 info.indexed = true;
3520 info.count = indexCount;
3521 info.instance_count = instanceCount;
3522 info.first_index = firstIndex;
3523 info.vertex_offset = vertexOffset;
3524 info.first_instance = firstInstance;
3525
3526 radv_draw(cmd_buffer, &info);
3527 }
3528
3529 void radv_CmdDrawIndirect(
3530 VkCommandBuffer commandBuffer,
3531 VkBuffer _buffer,
3532 VkDeviceSize offset,
3533 uint32_t drawCount,
3534 uint32_t stride)
3535 {
3536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3537 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3538 struct radv_draw_info info = {};
3539
3540 info.count = drawCount;
3541 info.indirect = buffer;
3542 info.indirect_offset = offset;
3543 info.stride = stride;
3544
3545 radv_draw(cmd_buffer, &info);
3546 }
3547
3548 void radv_CmdDrawIndexedIndirect(
3549 VkCommandBuffer commandBuffer,
3550 VkBuffer _buffer,
3551 VkDeviceSize offset,
3552 uint32_t drawCount,
3553 uint32_t stride)
3554 {
3555 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3556 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3557 struct radv_draw_info info = {};
3558
3559 info.indexed = true;
3560 info.count = drawCount;
3561 info.indirect = buffer;
3562 info.indirect_offset = offset;
3563 info.stride = stride;
3564
3565 radv_draw(cmd_buffer, &info);
3566 }
3567
3568 void radv_CmdDrawIndirectCountAMD(
3569 VkCommandBuffer commandBuffer,
3570 VkBuffer _buffer,
3571 VkDeviceSize offset,
3572 VkBuffer _countBuffer,
3573 VkDeviceSize countBufferOffset,
3574 uint32_t maxDrawCount,
3575 uint32_t stride)
3576 {
3577 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3578 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3579 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3580 struct radv_draw_info info = {};
3581
3582 info.count = maxDrawCount;
3583 info.indirect = buffer;
3584 info.indirect_offset = offset;
3585 info.count_buffer = count_buffer;
3586 info.count_buffer_offset = countBufferOffset;
3587 info.stride = stride;
3588
3589 radv_draw(cmd_buffer, &info);
3590 }
3591
3592 void radv_CmdDrawIndexedIndirectCountAMD(
3593 VkCommandBuffer commandBuffer,
3594 VkBuffer _buffer,
3595 VkDeviceSize offset,
3596 VkBuffer _countBuffer,
3597 VkDeviceSize countBufferOffset,
3598 uint32_t maxDrawCount,
3599 uint32_t stride)
3600 {
3601 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3602 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3603 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3604 struct radv_draw_info info = {};
3605
3606 info.indexed = true;
3607 info.count = maxDrawCount;
3608 info.indirect = buffer;
3609 info.indirect_offset = offset;
3610 info.count_buffer = count_buffer;
3611 info.count_buffer_offset = countBufferOffset;
3612 info.stride = stride;
3613
3614 radv_draw(cmd_buffer, &info);
3615 }
3616
3617 void radv_CmdDrawIndirectCountKHR(
3618 VkCommandBuffer commandBuffer,
3619 VkBuffer _buffer,
3620 VkDeviceSize offset,
3621 VkBuffer _countBuffer,
3622 VkDeviceSize countBufferOffset,
3623 uint32_t maxDrawCount,
3624 uint32_t stride)
3625 {
3626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3627 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3628 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3629 struct radv_draw_info info = {};
3630
3631 info.count = maxDrawCount;
3632 info.indirect = buffer;
3633 info.indirect_offset = offset;
3634 info.count_buffer = count_buffer;
3635 info.count_buffer_offset = countBufferOffset;
3636 info.stride = stride;
3637
3638 radv_draw(cmd_buffer, &info);
3639 }
3640
3641 void radv_CmdDrawIndexedIndirectCountKHR(
3642 VkCommandBuffer commandBuffer,
3643 VkBuffer _buffer,
3644 VkDeviceSize offset,
3645 VkBuffer _countBuffer,
3646 VkDeviceSize countBufferOffset,
3647 uint32_t maxDrawCount,
3648 uint32_t stride)
3649 {
3650 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3651 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3652 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3653 struct radv_draw_info info = {};
3654
3655 info.indexed = true;
3656 info.count = maxDrawCount;
3657 info.indirect = buffer;
3658 info.indirect_offset = offset;
3659 info.count_buffer = count_buffer;
3660 info.count_buffer_offset = countBufferOffset;
3661 info.stride = stride;
3662
3663 radv_draw(cmd_buffer, &info);
3664 }
3665
3666 struct radv_dispatch_info {
3667 /**
3668 * Determine the layout of the grid (in block units) to be used.
3669 */
3670 uint32_t blocks[3];
3671
3672 /**
3673 * A starting offset for the grid. If unaligned is set, the offset
3674 * must still be aligned.
3675 */
3676 uint32_t offsets[3];
3677 /**
3678 * Whether it's an unaligned compute dispatch.
3679 */
3680 bool unaligned;
3681
3682 /**
3683 * Indirect compute parameters resource.
3684 */
3685 struct radv_buffer *indirect;
3686 uint64_t indirect_offset;
3687 };
3688
3689 static void
3690 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3691 const struct radv_dispatch_info *info)
3692 {
3693 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3694 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3695 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3696 struct radeon_winsys *ws = cmd_buffer->device->ws;
3697 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3698 struct radv_userdata_info *loc;
3699
3700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3701 AC_UD_CS_GRID_SIZE);
3702
3703 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3704
3705 if (info->indirect) {
3706 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3707
3708 va += info->indirect->offset + info->indirect_offset;
3709
3710 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3711
3712 if (loc->sgpr_idx != -1) {
3713 for (unsigned i = 0; i < 3; ++i) {
3714 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3715 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3716 COPY_DATA_DST_SEL(COPY_DATA_REG));
3717 radeon_emit(cs, (va + 4 * i));
3718 radeon_emit(cs, (va + 4 * i) >> 32);
3719 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3720 + loc->sgpr_idx * 4) >> 2) + i);
3721 radeon_emit(cs, 0);
3722 }
3723 }
3724
3725 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3726 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3727 PKT3_SHADER_TYPE_S(1));
3728 radeon_emit(cs, va);
3729 radeon_emit(cs, va >> 32);
3730 radeon_emit(cs, dispatch_initiator);
3731 } else {
3732 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3733 PKT3_SHADER_TYPE_S(1));
3734 radeon_emit(cs, 1);
3735 radeon_emit(cs, va);
3736 radeon_emit(cs, va >> 32);
3737
3738 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3739 PKT3_SHADER_TYPE_S(1));
3740 radeon_emit(cs, 0);
3741 radeon_emit(cs, dispatch_initiator);
3742 }
3743 } else {
3744 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3745 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3746
3747 if (info->unaligned) {
3748 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3749 unsigned remainder[3];
3750
3751 /* If aligned, these should be an entire block size,
3752 * not 0.
3753 */
3754 remainder[0] = blocks[0] + cs_block_size[0] -
3755 align_u32_npot(blocks[0], cs_block_size[0]);
3756 remainder[1] = blocks[1] + cs_block_size[1] -
3757 align_u32_npot(blocks[1], cs_block_size[1]);
3758 remainder[2] = blocks[2] + cs_block_size[2] -
3759 align_u32_npot(blocks[2], cs_block_size[2]);
3760
3761 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3762 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3763 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3764
3765 for(unsigned i = 0; i < 3; ++i) {
3766 assert(offsets[i] % cs_block_size[i] == 0);
3767 offsets[i] /= cs_block_size[i];
3768 }
3769
3770 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3771 radeon_emit(cs,
3772 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3773 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3774 radeon_emit(cs,
3775 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3776 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3777 radeon_emit(cs,
3778 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3779 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3780
3781 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3782 }
3783
3784 if (loc->sgpr_idx != -1) {
3785 assert(!loc->indirect);
3786 assert(loc->num_sgprs == 3);
3787
3788 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3789 loc->sgpr_idx * 4, 3);
3790 radeon_emit(cs, blocks[0]);
3791 radeon_emit(cs, blocks[1]);
3792 radeon_emit(cs, blocks[2]);
3793 }
3794
3795 if (offsets[0] || offsets[1] || offsets[2]) {
3796 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3797 radeon_emit(cs, offsets[0]);
3798 radeon_emit(cs, offsets[1]);
3799 radeon_emit(cs, offsets[2]);
3800
3801 /* The blocks in the packet are not counts but end values. */
3802 for (unsigned i = 0; i < 3; ++i)
3803 blocks[i] += offsets[i];
3804 } else {
3805 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3806 }
3807
3808 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3809 PKT3_SHADER_TYPE_S(1));
3810 radeon_emit(cs, blocks[0]);
3811 radeon_emit(cs, blocks[1]);
3812 radeon_emit(cs, blocks[2]);
3813 radeon_emit(cs, dispatch_initiator);
3814 }
3815
3816 assert(cmd_buffer->cs->cdw <= cdw_max);
3817 }
3818
3819 static void
3820 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3821 {
3822 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3823 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3824 }
3825
3826 static void
3827 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3828 const struct radv_dispatch_info *info)
3829 {
3830 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3831 bool has_prefetch =
3832 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3833 bool pipeline_is_dirty = pipeline &&
3834 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3835
3836 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3837 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3838 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3839 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3840 /* If we have to wait for idle, set all states first, so that
3841 * all SET packets are processed in parallel with previous draw
3842 * calls. Then upload descriptors, set shader pointers, and
3843 * dispatch, and prefetch at the end. This ensures that the
3844 * time the CUs are idle is very short. (there are only SET_SH
3845 * packets between the wait and the draw)
3846 */
3847 radv_emit_compute_pipeline(cmd_buffer);
3848 si_emit_cache_flush(cmd_buffer);
3849 /* <-- CUs are idle here --> */
3850
3851 radv_upload_compute_shader_descriptors(cmd_buffer);
3852
3853 radv_emit_dispatch_packets(cmd_buffer, info);
3854 /* <-- CUs are busy here --> */
3855
3856 /* Start prefetches after the dispatch has been started. Both
3857 * will run in parallel, but starting the dispatch first is
3858 * more important.
3859 */
3860 if (has_prefetch && pipeline_is_dirty) {
3861 radv_emit_shader_prefetch(cmd_buffer,
3862 pipeline->shaders[MESA_SHADER_COMPUTE]);
3863 }
3864 } else {
3865 /* If we don't wait for idle, start prefetches first, then set
3866 * states, and dispatch at the end.
3867 */
3868 si_emit_cache_flush(cmd_buffer);
3869
3870 if (has_prefetch && pipeline_is_dirty) {
3871 radv_emit_shader_prefetch(cmd_buffer,
3872 pipeline->shaders[MESA_SHADER_COMPUTE]);
3873 }
3874
3875 radv_upload_compute_shader_descriptors(cmd_buffer);
3876
3877 radv_emit_compute_pipeline(cmd_buffer);
3878 radv_emit_dispatch_packets(cmd_buffer, info);
3879 }
3880
3881 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3882 }
3883
3884 void radv_CmdDispatchBase(
3885 VkCommandBuffer commandBuffer,
3886 uint32_t base_x,
3887 uint32_t base_y,
3888 uint32_t base_z,
3889 uint32_t x,
3890 uint32_t y,
3891 uint32_t z)
3892 {
3893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3894 struct radv_dispatch_info info = {};
3895
3896 info.blocks[0] = x;
3897 info.blocks[1] = y;
3898 info.blocks[2] = z;
3899
3900 info.offsets[0] = base_x;
3901 info.offsets[1] = base_y;
3902 info.offsets[2] = base_z;
3903 radv_dispatch(cmd_buffer, &info);
3904 }
3905
3906 void radv_CmdDispatch(
3907 VkCommandBuffer commandBuffer,
3908 uint32_t x,
3909 uint32_t y,
3910 uint32_t z)
3911 {
3912 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3913 }
3914
3915 void radv_CmdDispatchIndirect(
3916 VkCommandBuffer commandBuffer,
3917 VkBuffer _buffer,
3918 VkDeviceSize offset)
3919 {
3920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3921 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3922 struct radv_dispatch_info info = {};
3923
3924 info.indirect = buffer;
3925 info.indirect_offset = offset;
3926
3927 radv_dispatch(cmd_buffer, &info);
3928 }
3929
3930 void radv_unaligned_dispatch(
3931 struct radv_cmd_buffer *cmd_buffer,
3932 uint32_t x,
3933 uint32_t y,
3934 uint32_t z)
3935 {
3936 struct radv_dispatch_info info = {};
3937
3938 info.blocks[0] = x;
3939 info.blocks[1] = y;
3940 info.blocks[2] = z;
3941 info.unaligned = 1;
3942
3943 radv_dispatch(cmd_buffer, &info);
3944 }
3945
3946 void radv_CmdEndRenderPass(
3947 VkCommandBuffer commandBuffer)
3948 {
3949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3950
3951 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3952
3953 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3954
3955 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3956 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3957 radv_handle_subpass_image_transition(cmd_buffer,
3958 (struct radv_subpass_attachment){i, layout});
3959 }
3960
3961 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3962
3963 cmd_buffer->state.pass = NULL;
3964 cmd_buffer->state.subpass = NULL;
3965 cmd_buffer->state.attachments = NULL;
3966 cmd_buffer->state.framebuffer = NULL;
3967 }
3968
3969 void radv_CmdEndRenderPass2KHR(
3970 VkCommandBuffer commandBuffer,
3971 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3972 {
3973 radv_CmdEndRenderPass(commandBuffer);
3974 }
3975
3976 /*
3977 * For HTILE we have the following interesting clear words:
3978 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3979 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3980 * 0xfffffff0: Clear depth to 1.0
3981 * 0x00000000: Clear depth to 0.0
3982 */
3983 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3984 struct radv_image *image,
3985 const VkImageSubresourceRange *range,
3986 uint32_t clear_word)
3987 {
3988 assert(range->baseMipLevel == 0);
3989 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3990 unsigned layer_count = radv_get_layerCount(image, range);
3991 uint64_t size = image->surface.htile_slice_size * layer_count;
3992 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3993 uint64_t offset = image->offset + image->htile_offset +
3994 image->surface.htile_slice_size * range->baseArrayLayer;
3995 struct radv_cmd_state *state = &cmd_buffer->state;
3996 VkClearDepthStencilValue value = {};
3997
3998 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3999 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4000
4001 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4002 size, clear_word);
4003
4004 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4005
4006 if (vk_format_is_stencil(image->vk_format))
4007 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4008
4009 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4010 }
4011
4012 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4013 struct radv_image *image,
4014 VkImageLayout src_layout,
4015 VkImageLayout dst_layout,
4016 unsigned src_queue_mask,
4017 unsigned dst_queue_mask,
4018 const VkImageSubresourceRange *range,
4019 VkImageAspectFlags pending_clears)
4020 {
4021 if (!radv_image_has_htile(image))
4022 return;
4023
4024 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4025 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4026 /* TODO: merge with the clear if applicable */
4027 radv_initialize_htile(cmd_buffer, image, range, 0);
4028 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4029 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4030 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4031 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4032 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4033 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4034 VkImageSubresourceRange local_range = *range;
4035 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4036 local_range.baseMipLevel = 0;
4037 local_range.levelCount = 1;
4038
4039 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4040 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4041
4042 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4043
4044 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4045 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4046 }
4047 }
4048
4049 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4050 struct radv_image *image, uint32_t value)
4051 {
4052 struct radv_cmd_state *state = &cmd_buffer->state;
4053
4054 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4055 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4056
4057 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4058
4059 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4060 }
4061
4062 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4063 struct radv_image *image, uint32_t value)
4064 {
4065 struct radv_cmd_state *state = &cmd_buffer->state;
4066
4067 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4068 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4069
4070 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4071
4072 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4073 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4074 }
4075
4076 /**
4077 * Initialize DCC/FMASK/CMASK metadata for a color image.
4078 */
4079 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4080 struct radv_image *image,
4081 VkImageLayout src_layout,
4082 VkImageLayout dst_layout,
4083 unsigned src_queue_mask,
4084 unsigned dst_queue_mask)
4085 {
4086 if (radv_image_has_cmask(image)) {
4087 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4088
4089 /* TODO: clarify this. */
4090 if (radv_image_has_fmask(image)) {
4091 value = 0xccccccccu;
4092 }
4093
4094 radv_initialise_cmask(cmd_buffer, image, value);
4095 }
4096
4097 if (radv_image_has_dcc(image)) {
4098 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4099
4100 if (radv_layout_dcc_compressed(image, dst_layout,
4101 dst_queue_mask)) {
4102 value = 0x20202020u;
4103 }
4104
4105 radv_initialize_dcc(cmd_buffer, image, value);
4106
4107 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4108 }
4109
4110 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4111 uint32_t color_values[2] = {};
4112 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4113 }
4114 }
4115
4116 /**
4117 * Handle color image transitions for DCC/FMASK/CMASK.
4118 */
4119 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4120 struct radv_image *image,
4121 VkImageLayout src_layout,
4122 VkImageLayout dst_layout,
4123 unsigned src_queue_mask,
4124 unsigned dst_queue_mask,
4125 const VkImageSubresourceRange *range)
4126 {
4127 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4128 radv_init_color_image_metadata(cmd_buffer, image,
4129 src_layout, dst_layout,
4130 src_queue_mask, dst_queue_mask);
4131 return;
4132 }
4133
4134 if (radv_image_has_dcc(image)) {
4135 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4136 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4137 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4138 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4139 radv_decompress_dcc(cmd_buffer, image, range);
4140 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4141 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4142 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4143 }
4144 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4145 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4146 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4147 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4148 }
4149 }
4150 }
4151
4152 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4153 struct radv_image *image,
4154 VkImageLayout src_layout,
4155 VkImageLayout dst_layout,
4156 uint32_t src_family,
4157 uint32_t dst_family,
4158 const VkImageSubresourceRange *range,
4159 VkImageAspectFlags pending_clears)
4160 {
4161 if (image->exclusive && src_family != dst_family) {
4162 /* This is an acquire or a release operation and there will be
4163 * a corresponding release/acquire. Do the transition in the
4164 * most flexible queue. */
4165
4166 assert(src_family == cmd_buffer->queue_family_index ||
4167 dst_family == cmd_buffer->queue_family_index);
4168
4169 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4170 return;
4171
4172 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4173 (src_family == RADV_QUEUE_GENERAL ||
4174 dst_family == RADV_QUEUE_GENERAL))
4175 return;
4176 }
4177
4178 unsigned src_queue_mask =
4179 radv_image_queue_family_mask(image, src_family,
4180 cmd_buffer->queue_family_index);
4181 unsigned dst_queue_mask =
4182 radv_image_queue_family_mask(image, dst_family,
4183 cmd_buffer->queue_family_index);
4184
4185 if (vk_format_is_depth(image->vk_format)) {
4186 radv_handle_depth_image_transition(cmd_buffer, image,
4187 src_layout, dst_layout,
4188 src_queue_mask, dst_queue_mask,
4189 range, pending_clears);
4190 } else {
4191 radv_handle_color_image_transition(cmd_buffer, image,
4192 src_layout, dst_layout,
4193 src_queue_mask, dst_queue_mask,
4194 range);
4195 }
4196 }
4197
4198 struct radv_barrier_info {
4199 uint32_t eventCount;
4200 const VkEvent *pEvents;
4201 VkPipelineStageFlags srcStageMask;
4202 };
4203
4204 static void
4205 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4206 uint32_t memoryBarrierCount,
4207 const VkMemoryBarrier *pMemoryBarriers,
4208 uint32_t bufferMemoryBarrierCount,
4209 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4210 uint32_t imageMemoryBarrierCount,
4211 const VkImageMemoryBarrier *pImageMemoryBarriers,
4212 const struct radv_barrier_info *info)
4213 {
4214 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4215 enum radv_cmd_flush_bits src_flush_bits = 0;
4216 enum radv_cmd_flush_bits dst_flush_bits = 0;
4217
4218 for (unsigned i = 0; i < info->eventCount; ++i) {
4219 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4220 uint64_t va = radv_buffer_get_va(event->bo);
4221
4222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4223
4224 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4225
4226 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4227 assert(cmd_buffer->cs->cdw <= cdw_max);
4228 }
4229
4230 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4231 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4232 NULL);
4233 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4234 NULL);
4235 }
4236
4237 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4238 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4239 NULL);
4240 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4241 NULL);
4242 }
4243
4244 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4245 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4246
4247 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4248 image);
4249 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4250 image);
4251 }
4252
4253 radv_stage_flush(cmd_buffer, info->srcStageMask);
4254 cmd_buffer->state.flush_bits |= src_flush_bits;
4255
4256 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4257 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4258 radv_handle_image_transition(cmd_buffer, image,
4259 pImageMemoryBarriers[i].oldLayout,
4260 pImageMemoryBarriers[i].newLayout,
4261 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4262 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4263 &pImageMemoryBarriers[i].subresourceRange,
4264 0);
4265 }
4266
4267 /* Make sure CP DMA is idle because the driver might have performed a
4268 * DMA operation for copying or filling buffers/images.
4269 */
4270 si_cp_dma_wait_for_idle(cmd_buffer);
4271
4272 cmd_buffer->state.flush_bits |= dst_flush_bits;
4273 }
4274
4275 void radv_CmdPipelineBarrier(
4276 VkCommandBuffer commandBuffer,
4277 VkPipelineStageFlags srcStageMask,
4278 VkPipelineStageFlags destStageMask,
4279 VkBool32 byRegion,
4280 uint32_t memoryBarrierCount,
4281 const VkMemoryBarrier* pMemoryBarriers,
4282 uint32_t bufferMemoryBarrierCount,
4283 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4284 uint32_t imageMemoryBarrierCount,
4285 const VkImageMemoryBarrier* pImageMemoryBarriers)
4286 {
4287 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4288 struct radv_barrier_info info;
4289
4290 info.eventCount = 0;
4291 info.pEvents = NULL;
4292 info.srcStageMask = srcStageMask;
4293
4294 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4295 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4296 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4297 }
4298
4299
4300 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4301 struct radv_event *event,
4302 VkPipelineStageFlags stageMask,
4303 unsigned value)
4304 {
4305 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4306 uint64_t va = radv_buffer_get_va(event->bo);
4307
4308 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4309
4310 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4311
4312 /* Flags that only require a top-of-pipe event. */
4313 VkPipelineStageFlags top_of_pipe_flags =
4314 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4315
4316 /* Flags that only require a post-index-fetch event. */
4317 VkPipelineStageFlags post_index_fetch_flags =
4318 top_of_pipe_flags |
4319 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4320 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4321
4322 /* Make sure CP DMA is idle because the driver might have performed a
4323 * DMA operation for copying or filling buffers/images.
4324 */
4325 si_cp_dma_wait_for_idle(cmd_buffer);
4326
4327 /* TODO: Emit EOS events for syncing PS/CS stages. */
4328
4329 if (!(stageMask & ~top_of_pipe_flags)) {
4330 /* Just need to sync the PFP engine. */
4331 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4332 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4333 S_370_WR_CONFIRM(1) |
4334 S_370_ENGINE_SEL(V_370_PFP));
4335 radeon_emit(cs, va);
4336 radeon_emit(cs, va >> 32);
4337 radeon_emit(cs, value);
4338 } else if (!(stageMask & ~post_index_fetch_flags)) {
4339 /* Sync ME because PFP reads index and indirect buffers. */
4340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4342 S_370_WR_CONFIRM(1) |
4343 S_370_ENGINE_SEL(V_370_ME));
4344 radeon_emit(cs, va);
4345 radeon_emit(cs, va >> 32);
4346 radeon_emit(cs, value);
4347 } else {
4348 /* Otherwise, sync all prior GPU work using an EOP event. */
4349 si_cs_emit_write_event_eop(cs,
4350 cmd_buffer->device->physical_device->rad_info.chip_class,
4351 radv_cmd_buffer_uses_mec(cmd_buffer),
4352 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4353 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4354 cmd_buffer->gfx9_eop_bug_va);
4355 }
4356
4357 assert(cmd_buffer->cs->cdw <= cdw_max);
4358 }
4359
4360 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4361 VkEvent _event,
4362 VkPipelineStageFlags stageMask)
4363 {
4364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4365 RADV_FROM_HANDLE(radv_event, event, _event);
4366
4367 write_event(cmd_buffer, event, stageMask, 1);
4368 }
4369
4370 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4371 VkEvent _event,
4372 VkPipelineStageFlags stageMask)
4373 {
4374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4375 RADV_FROM_HANDLE(radv_event, event, _event);
4376
4377 write_event(cmd_buffer, event, stageMask, 0);
4378 }
4379
4380 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4381 uint32_t eventCount,
4382 const VkEvent* pEvents,
4383 VkPipelineStageFlags srcStageMask,
4384 VkPipelineStageFlags dstStageMask,
4385 uint32_t memoryBarrierCount,
4386 const VkMemoryBarrier* pMemoryBarriers,
4387 uint32_t bufferMemoryBarrierCount,
4388 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4389 uint32_t imageMemoryBarrierCount,
4390 const VkImageMemoryBarrier* pImageMemoryBarriers)
4391 {
4392 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4393 struct radv_barrier_info info;
4394
4395 info.eventCount = eventCount;
4396 info.pEvents = pEvents;
4397 info.srcStageMask = 0;
4398
4399 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4400 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4401 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4402 }
4403
4404
4405 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4406 uint32_t deviceMask)
4407 {
4408 /* No-op */
4409 }