2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 VkImageAspectFlags pending_clears
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
110 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
111 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
112 src
->viewport
.count
* sizeof(VkViewport
))) {
113 typed_memcpy(dest
->viewport
.viewports
,
114 src
->viewport
.viewports
,
115 src
->viewport
.count
);
116 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
120 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
121 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
122 src
->scissor
.count
* sizeof(VkRect2D
))) {
123 typed_memcpy(dest
->scissor
.scissors
,
124 src
->scissor
.scissors
, src
->scissor
.count
);
125 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
129 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
130 if (dest
->line_width
!= src
->line_width
) {
131 dest
->line_width
= src
->line_width
;
132 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
136 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
137 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
138 sizeof(src
->depth_bias
))) {
139 dest
->depth_bias
= src
->depth_bias
;
140 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
144 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
145 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
146 sizeof(src
->blend_constants
))) {
147 typed_memcpy(dest
->blend_constants
,
148 src
->blend_constants
, 4);
149 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
153 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
154 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
155 sizeof(src
->depth_bounds
))) {
156 dest
->depth_bounds
= src
->depth_bounds
;
157 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
161 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
162 if (memcmp(&dest
->stencil_compare_mask
,
163 &src
->stencil_compare_mask
,
164 sizeof(src
->stencil_compare_mask
))) {
165 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
166 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
170 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
171 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
172 sizeof(src
->stencil_write_mask
))) {
173 dest
->stencil_write_mask
= src
->stencil_write_mask
;
174 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
178 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
179 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
180 sizeof(src
->stencil_reference
))) {
181 dest
->stencil_reference
= src
->stencil_reference
;
182 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
186 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
187 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
188 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
189 typed_memcpy(dest
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
);
192 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
196 cmd_buffer
->state
.dirty
|= dest_mask
;
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
201 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
202 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
205 enum ring_type
radv_queue_family_to_ring(int f
) {
207 case RADV_QUEUE_GENERAL
:
209 case RADV_QUEUE_COMPUTE
:
211 case RADV_QUEUE_TRANSFER
:
214 unreachable("Unknown queue family");
218 static VkResult
radv_create_cmd_buffer(
219 struct radv_device
* device
,
220 struct radv_cmd_pool
* pool
,
221 VkCommandBufferLevel level
,
222 VkCommandBuffer
* pCommandBuffer
)
224 struct radv_cmd_buffer
*cmd_buffer
;
226 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
228 if (cmd_buffer
== NULL
)
229 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
231 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
232 cmd_buffer
->device
= device
;
233 cmd_buffer
->pool
= pool
;
234 cmd_buffer
->level
= level
;
237 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
238 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
241 /* Init the pool_link so we can safely call list_del when we destroy
244 list_inithead(&cmd_buffer
->pool_link
);
245 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
248 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
250 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
251 if (!cmd_buffer
->cs
) {
252 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
253 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
256 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
258 list_inithead(&cmd_buffer
->upload
.list
);
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
266 list_del(&cmd_buffer
->pool_link
);
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
269 &cmd_buffer
->upload
.list
, list
) {
270 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
275 if (cmd_buffer
->upload
.upload_bo
)
276 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
277 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
279 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
280 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
282 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
286 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
289 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
292 &cmd_buffer
->upload
.list
, list
) {
293 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
298 cmd_buffer
->push_constant_stages
= 0;
299 cmd_buffer
->scratch_size_needed
= 0;
300 cmd_buffer
->compute_scratch_size_needed
= 0;
301 cmd_buffer
->esgs_ring_size_needed
= 0;
302 cmd_buffer
->gsvs_ring_size_needed
= 0;
303 cmd_buffer
->tess_rings_needed
= false;
304 cmd_buffer
->sample_positions_needed
= false;
306 if (cmd_buffer
->upload
.upload_bo
)
307 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
308 cmd_buffer
->upload
.upload_bo
, 8);
309 cmd_buffer
->upload
.offset
= 0;
311 cmd_buffer
->record_result
= VK_SUCCESS
;
313 cmd_buffer
->ring_offsets_idx
= -1;
315 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
316 cmd_buffer
->descriptors
[i
].dirty
= 0;
317 cmd_buffer
->descriptors
[i
].valid
= 0;
318 cmd_buffer
->descriptors
[i
].push_dirty
= false;
321 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
322 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
323 unsigned eop_bug_offset
;
326 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
327 &cmd_buffer
->gfx9_fence_offset
,
329 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
331 /* Allocate a buffer for the EOP bug on GFX9. */
332 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
333 &eop_bug_offset
, &fence_ptr
);
334 cmd_buffer
->gfx9_eop_bug_va
=
335 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
336 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
339 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
341 return cmd_buffer
->record_result
;
345 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
349 struct radeon_winsys_bo
*bo
;
350 struct radv_cmd_buffer_upload
*upload
;
351 struct radv_device
*device
= cmd_buffer
->device
;
353 new_size
= MAX2(min_needed
, 16 * 1024);
354 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
356 bo
= device
->ws
->buffer_create(device
->ws
,
359 RADEON_FLAG_CPU_ACCESS
|
360 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
364 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
368 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
, 8);
369 if (cmd_buffer
->upload
.upload_bo
) {
370 upload
= malloc(sizeof(*upload
));
373 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
374 device
->ws
->buffer_destroy(bo
);
378 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
379 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
382 cmd_buffer
->upload
.upload_bo
= bo
;
383 cmd_buffer
->upload
.size
= new_size
;
384 cmd_buffer
->upload
.offset
= 0;
385 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
387 if (!cmd_buffer
->upload
.map
) {
388 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
396 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
399 unsigned *out_offset
,
402 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
403 if (offset
+ size
> cmd_buffer
->upload
.size
) {
404 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
409 *out_offset
= offset
;
410 *ptr
= cmd_buffer
->upload
.map
+ offset
;
412 cmd_buffer
->upload
.offset
= offset
+ size
;
417 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
418 unsigned size
, unsigned alignment
,
419 const void *data
, unsigned *out_offset
)
423 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
424 out_offset
, (void **)&ptr
))
428 memcpy(ptr
, data
, size
);
434 radv_emit_write_data_packet(struct radeon_cmdbuf
*cs
, uint64_t va
,
435 unsigned count
, const uint32_t *data
)
437 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
438 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
439 S_370_WR_CONFIRM(1) |
440 S_370_ENGINE_SEL(V_370_ME
));
442 radeon_emit(cs
, va
>> 32);
443 radeon_emit_array(cs
, data
, count
);
446 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
448 struct radv_device
*device
= cmd_buffer
->device
;
449 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
452 va
= radv_buffer_get_va(device
->trace_bo
);
453 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
456 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
458 ++cmd_buffer
->state
.trace_id
;
459 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
460 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
461 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
465 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
466 enum radv_cmd_flush_bits flags
)
468 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
469 uint32_t *ptr
= NULL
;
472 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
473 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
475 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
476 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
477 cmd_buffer
->gfx9_fence_offset
;
478 ptr
= &cmd_buffer
->gfx9_fence_idx
;
481 /* Force wait for graphics or compute engines to be idle. */
482 si_cs_emit_cache_flush(cmd_buffer
->cs
,
483 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
485 radv_cmd_buffer_uses_mec(cmd_buffer
),
486 flags
, cmd_buffer
->gfx9_eop_bug_va
);
489 if (unlikely(cmd_buffer
->device
->trace_bo
))
490 radv_cmd_buffer_trace_emit(cmd_buffer
);
494 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
495 struct radv_pipeline
*pipeline
, enum ring_type ring
)
497 struct radv_device
*device
= cmd_buffer
->device
;
498 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
502 va
= radv_buffer_get_va(device
->trace_bo
);
512 assert(!"invalid ring type");
515 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
518 data
[0] = (uintptr_t)pipeline
;
519 data
[1] = (uintptr_t)pipeline
>> 32;
521 radv_emit_write_data_packet(cs
, va
, 2, data
);
524 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
525 VkPipelineBindPoint bind_point
,
526 struct radv_descriptor_set
*set
,
529 struct radv_descriptor_state
*descriptors_state
=
530 radv_get_descriptors_state(cmd_buffer
, bind_point
);
532 descriptors_state
->sets
[idx
] = set
;
534 descriptors_state
->valid
|= (1u << idx
);
536 descriptors_state
->valid
&= ~(1u << idx
);
537 descriptors_state
->dirty
|= (1u << idx
);
541 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
542 VkPipelineBindPoint bind_point
)
544 struct radv_descriptor_state
*descriptors_state
=
545 radv_get_descriptors_state(cmd_buffer
, bind_point
);
546 struct radv_device
*device
= cmd_buffer
->device
;
547 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
548 uint32_t data
[MAX_SETS
* 2] = {};
551 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
553 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
554 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
556 for_each_bit(i
, descriptors_state
->valid
) {
557 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
558 data
[i
* 2] = (uintptr_t)set
;
559 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
562 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
565 struct radv_userdata_info
*
566 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
567 gl_shader_stage stage
,
570 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
571 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
575 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
576 struct radv_pipeline
*pipeline
,
577 gl_shader_stage stage
,
578 int idx
, uint64_t va
)
580 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
581 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
582 if (loc
->sgpr_idx
== -1)
585 assert(loc
->num_sgprs
== (HAVE_32BIT_POINTERS
? 1 : 2));
586 assert(!loc
->indirect
);
588 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
589 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
593 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
594 struct radv_pipeline
*pipeline
,
595 struct radv_descriptor_state
*descriptors_state
,
596 gl_shader_stage stage
)
598 struct radv_device
*device
= cmd_buffer
->device
;
599 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
600 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
601 struct radv_userdata_locations
*locs
=
602 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
603 unsigned mask
= locs
->descriptor_sets_enabled
;
605 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
610 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
612 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
613 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
615 radv_emit_shader_pointer_head(cs
, sh_offset
, count
,
616 HAVE_32BIT_POINTERS
);
617 for (int i
= 0; i
< count
; i
++) {
618 struct radv_descriptor_set
*set
=
619 descriptors_state
->sets
[start
+ i
];
621 radv_emit_shader_pointer_body(device
, cs
, set
->va
,
622 HAVE_32BIT_POINTERS
);
628 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
629 struct radv_pipeline
*pipeline
)
631 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
632 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
633 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
635 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
636 cmd_buffer
->sample_positions_needed
= true;
638 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
641 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
642 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
643 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
645 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer
->device
->dfsm_allowed
) {
651 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
652 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
657 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
658 struct radv_shader_variant
*shader
)
665 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
667 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
671 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
672 struct radv_pipeline
*pipeline
,
673 bool vertex_stage_only
)
675 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
676 uint32_t mask
= state
->prefetch_L2_mask
;
678 if (vertex_stage_only
) {
679 /* Fast prefetch path for starting draws as soon as possible.
681 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
682 RADV_PREFETCH_VBO_DESCRIPTORS
);
685 if (mask
& RADV_PREFETCH_VS
)
686 radv_emit_shader_prefetch(cmd_buffer
,
687 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
689 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
690 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
692 if (mask
& RADV_PREFETCH_TCS
)
693 radv_emit_shader_prefetch(cmd_buffer
,
694 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
696 if (mask
& RADV_PREFETCH_TES
)
697 radv_emit_shader_prefetch(cmd_buffer
,
698 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
700 if (mask
& RADV_PREFETCH_GS
) {
701 radv_emit_shader_prefetch(cmd_buffer
,
702 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
703 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
706 if (mask
& RADV_PREFETCH_PS
)
707 radv_emit_shader_prefetch(cmd_buffer
,
708 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
710 state
->prefetch_L2_mask
&= ~mask
;
714 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
716 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
719 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
720 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
721 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
723 unsigned sx_ps_downconvert
= 0;
724 unsigned sx_blend_opt_epsilon
= 0;
725 unsigned sx_blend_opt_control
= 0;
727 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
728 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
731 int idx
= subpass
->color_attachments
[i
].attachment
;
732 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
734 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
735 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
736 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
737 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
739 bool has_alpha
, has_rgb
;
741 /* Set if RGB and A are present. */
742 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
744 if (format
== V_028C70_COLOR_8
||
745 format
== V_028C70_COLOR_16
||
746 format
== V_028C70_COLOR_32
)
747 has_rgb
= !has_alpha
;
751 /* Check the colormask and export format. */
752 if (!(colormask
& 0x7))
754 if (!(colormask
& 0x8))
757 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
762 /* Disable value checking for disabled channels. */
764 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
766 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
768 /* Enable down-conversion for 32bpp and smaller formats. */
770 case V_028C70_COLOR_8
:
771 case V_028C70_COLOR_8_8
:
772 case V_028C70_COLOR_8_8_8_8
:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
775 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
776 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
777 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
778 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
782 case V_028C70_COLOR_5_6_5
:
783 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
784 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
785 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
789 case V_028C70_COLOR_1_5_5_5
:
790 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
791 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
792 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
796 case V_028C70_COLOR_4_4_4_4
:
797 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
798 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
799 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
803 case V_028C70_COLOR_32
:
804 if (swap
== V_028C70_SWAP_STD
&&
805 spi_format
== V_028714_SPI_SHADER_32_R
)
806 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
807 else if (swap
== V_028C70_SWAP_ALT_REV
&&
808 spi_format
== V_028714_SPI_SHADER_32_AR
)
809 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
812 case V_028C70_COLOR_16
:
813 case V_028C70_COLOR_16_16
:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
816 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
817 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
818 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
819 if (swap
== V_028C70_SWAP_STD
||
820 swap
== V_028C70_SWAP_STD_REV
)
821 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
823 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
827 case V_028C70_COLOR_10_11_11
:
828 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
829 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
830 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
834 case V_028C70_COLOR_2_10_10_10
:
835 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
836 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
837 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
843 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
844 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
845 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
846 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
852 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
854 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
857 radv_update_multisample_state(cmd_buffer
, pipeline
);
859 cmd_buffer
->scratch_size_needed
=
860 MAX2(cmd_buffer
->scratch_size_needed
,
861 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
863 if (!cmd_buffer
->state
.emitted_pipeline
||
864 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
865 pipeline
->graphics
.can_use_guardband
)
866 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
868 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
870 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
871 if (!pipeline
->shaders
[i
])
874 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
875 pipeline
->shaders
[i
]->bo
, 8);
878 if (radv_pipeline_has_gs(pipeline
))
879 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
880 pipeline
->gs_copy_shader
->bo
, 8);
882 if (unlikely(cmd_buffer
->device
->trace_bo
))
883 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
885 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
887 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
891 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
893 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
894 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
898 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
900 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
902 si_write_scissors(cmd_buffer
->cs
, 0, count
,
903 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
904 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
905 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
909 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
911 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
914 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
915 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
916 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
917 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
918 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
919 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
920 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
925 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
927 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
929 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
930 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
934 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
936 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
938 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
939 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
943 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
945 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
947 radeon_set_context_reg_seq(cmd_buffer
->cs
,
948 R_028430_DB_STENCILREFMASK
, 2);
949 radeon_emit(cmd_buffer
->cs
,
950 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
951 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
952 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer
->cs
,
955 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
956 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
957 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
958 S_028434_STENCILOPVAL_BF(1));
962 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
964 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
966 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
967 fui(d
->depth_bounds
.min
));
968 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
969 fui(d
->depth_bounds
.max
));
973 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
975 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
976 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
977 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
980 radeon_set_context_reg_seq(cmd_buffer
->cs
,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
982 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
983 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
984 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
986 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
990 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
992 struct radv_attachment_info
*att
,
993 struct radv_image
*image
,
994 VkImageLayout layout
)
996 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
997 struct radv_color_buffer_info
*cb
= &att
->cb
;
998 uint32_t cb_color_info
= cb
->cb_color_info
;
1000 if (!radv_layout_dcc_compressed(image
, layout
,
1001 radv_image_queue_family_mask(image
,
1002 cmd_buffer
->queue_family_index
,
1003 cmd_buffer
->queue_family_index
))) {
1004 cb_color_info
&= C_028C70_DCC_ENABLE
;
1007 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1008 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1009 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1010 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1011 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1012 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1013 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1014 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1015 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1016 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1017 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1018 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1019 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1021 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1022 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1023 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1025 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1026 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1028 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1029 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1030 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1031 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1032 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1033 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1034 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1035 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1036 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1037 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1038 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1039 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1041 if (is_vi
) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1048 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1049 struct radv_ds_buffer_info
*ds
,
1050 struct radv_image
*image
, VkImageLayout layout
,
1051 bool requires_cond_write
)
1053 uint32_t db_z_info
= ds
->db_z_info
;
1054 uint32_t db_z_info_reg
;
1056 if (!radv_image_is_tc_compat_htile(image
))
1059 if (!radv_layout_has_htile(image
, layout
,
1060 radv_image_queue_family_mask(image
,
1061 cmd_buffer
->queue_family_index
,
1062 cmd_buffer
->queue_family_index
))) {
1063 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1066 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1068 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1069 db_z_info_reg
= R_028038_DB_Z_INFO
;
1071 db_z_info_reg
= R_028040_DB_Z_INFO
;
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1077 if (requires_cond_write
) {
1078 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_WRITE
, 7, 0));
1080 const uint32_t write_space
= 0 << 8; /* register */
1081 const uint32_t poll_space
= 1 << 4; /* memory */
1082 const uint32_t function
= 3 << 0; /* equal to the reference */
1083 const uint32_t options
= write_space
| poll_space
| function
;
1084 radeon_emit(cmd_buffer
->cs
, options
);
1086 /* poll address - location of the depth clear value */
1087 uint64_t va
= radv_buffer_get_va(image
->bo
);
1088 va
+= image
->offset
+ image
->clear_value_offset
;
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1093 if (vk_format_is_stencil(image
->vk_format
))
1096 radeon_emit(cmd_buffer
->cs
, va
);
1097 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1099 radeon_emit(cmd_buffer
->cs
, fui(0.0f
)); /* reference value */
1100 radeon_emit(cmd_buffer
->cs
, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer
->cs
, db_z_info_reg
>> 2); /* write address low */
1102 radeon_emit(cmd_buffer
->cs
, 0u); /* write address high */
1103 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1105 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1111 struct radv_ds_buffer_info
*ds
,
1112 struct radv_image
*image
,
1113 VkImageLayout layout
)
1115 uint32_t db_z_info
= ds
->db_z_info
;
1116 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1118 if (!radv_layout_has_htile(image
, layout
,
1119 radv_image_queue_family_mask(image
,
1120 cmd_buffer
->queue_family_index
,
1121 cmd_buffer
->queue_family_index
))) {
1122 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1123 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1126 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1127 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1130 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1131 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1132 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1133 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1134 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1136 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1137 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1148 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1149 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1150 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1152 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1154 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1170 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1171 ds
->pa_su_poly_offset_db_fmt_cntl
);
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1180 struct radv_image
*image
,
1181 VkClearDepthStencilValue ds_clear_value
,
1182 VkImageAspectFlags aspects
)
1184 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1185 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1186 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1187 struct radv_attachment_info
*att
;
1190 if (!framebuffer
|| !subpass
)
1193 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1194 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1197 att
= &framebuffer
->attachments
[att_idx
];
1198 if (att
->attachment
->image
!= image
)
1201 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1202 radeon_emit(cs
, ds_clear_value
.stencil
);
1203 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1205 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206 * only needed when clearing Z to 0.0.
1208 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1209 ds_clear_value
.depth
== 0.0) {
1210 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1212 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1218 * Set the clear depth/stencil values to the image's metadata.
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1222 struct radv_image
*image
,
1223 VkClearDepthStencilValue ds_clear_value
,
1224 VkImageAspectFlags aspects
)
1226 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1227 uint64_t va
= radv_buffer_get_va(image
->bo
);
1228 unsigned reg_offset
= 0, reg_count
= 0;
1230 va
+= image
->offset
+ image
->clear_value_offset
;
1232 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1238 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1241 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1242 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1243 S_370_WR_CONFIRM(1) |
1244 S_370_ENGINE_SEL(V_370_PFP
));
1245 radeon_emit(cs
, va
);
1246 radeon_emit(cs
, va
>> 32);
1247 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1248 radeon_emit(cs
, ds_clear_value
.stencil
);
1249 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1250 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1254 * Update the clear depth/stencil values for this image.
1257 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1258 struct radv_image
*image
,
1259 VkClearDepthStencilValue ds_clear_value
,
1260 VkImageAspectFlags aspects
)
1262 assert(radv_image_has_htile(image
));
1264 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1266 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1271 * Load the clear depth/stencil values from the image's metadata.
1274 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1275 struct radv_image
*image
)
1277 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1278 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1279 uint64_t va
= radv_buffer_get_va(image
->bo
);
1280 unsigned reg_offset
= 0, reg_count
= 0;
1282 va
+= image
->offset
+ image
->clear_value_offset
;
1284 if (!radv_image_has_htile(image
))
1287 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1293 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1296 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1297 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1298 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1299 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1300 radeon_emit(cs
, va
);
1301 radeon_emit(cs
, va
>> 32);
1302 radeon_emit(cs
, (R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
) >> 2);
1305 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1310 * With DCC some colors don't require CMASK elimination before being
1311 * used as a texture. This sets a predicate value to determine if the
1312 * cmask eliminate is required.
1315 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1316 struct radv_image
*image
,
1319 uint64_t pred_val
= value
;
1320 uint64_t va
= radv_buffer_get_va(image
->bo
);
1321 va
+= image
->offset
+ image
->dcc_pred_offset
;
1323 assert(radv_image_has_dcc(image
));
1325 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1326 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1327 S_370_WR_CONFIRM(1) |
1328 S_370_ENGINE_SEL(V_370_PFP
));
1329 radeon_emit(cmd_buffer
->cs
, va
);
1330 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1331 radeon_emit(cmd_buffer
->cs
, pred_val
);
1332 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1336 * Update the fast clear color values if the image is bound as a color buffer.
1339 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1340 struct radv_image
*image
,
1342 uint32_t color_values
[2])
1344 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1345 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1346 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1347 struct radv_attachment_info
*att
;
1350 if (!framebuffer
|| !subpass
)
1353 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1354 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1357 att
= &framebuffer
->attachments
[att_idx
];
1358 if (att
->attachment
->image
!= image
)
1361 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1362 radeon_emit(cs
, color_values
[0]);
1363 radeon_emit(cs
, color_values
[1]);
1367 * Set the clear color values to the image's metadata.
1370 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1371 struct radv_image
*image
,
1372 uint32_t color_values
[2])
1374 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1375 uint64_t va
= radv_buffer_get_va(image
->bo
);
1377 va
+= image
->offset
+ image
->clear_value_offset
;
1379 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1381 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1382 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1383 S_370_WR_CONFIRM(1) |
1384 S_370_ENGINE_SEL(V_370_PFP
));
1385 radeon_emit(cs
, va
);
1386 radeon_emit(cs
, va
>> 32);
1387 radeon_emit(cs
, color_values
[0]);
1388 radeon_emit(cs
, color_values
[1]);
1392 * Update the clear color values for this image.
1395 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1396 struct radv_image
*image
,
1398 uint32_t color_values
[2])
1400 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1402 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1404 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1409 * Load the clear color values from the image's metadata.
1412 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1413 struct radv_image
*image
,
1416 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1417 uint64_t va
= radv_buffer_get_va(image
->bo
);
1419 va
+= image
->offset
+ image
->clear_value_offset
;
1421 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1424 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1426 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1427 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1428 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1429 COPY_DATA_COUNT_SEL
);
1430 radeon_emit(cs
, va
);
1431 radeon_emit(cs
, va
>> 32);
1432 radeon_emit(cs
, reg
>> 2);
1435 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1440 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1443 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1444 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1446 /* this may happen for inherited secondary recording */
1450 for (i
= 0; i
< 8; ++i
) {
1451 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1452 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1453 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1457 int idx
= subpass
->color_attachments
[i
].attachment
;
1458 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1459 struct radv_image
*image
= att
->attachment
->image
;
1460 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1462 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1464 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1465 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1467 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1470 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1471 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1472 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1473 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1474 struct radv_image
*image
= att
->attachment
->image
;
1475 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1476 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1477 cmd_buffer
->queue_family_index
,
1478 cmd_buffer
->queue_family_index
);
1479 /* We currently don't support writing decompressed HTILE */
1480 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1481 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1483 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1485 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1486 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1487 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1489 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1491 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1492 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1494 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1496 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1497 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1499 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1500 S_028208_BR_X(framebuffer
->width
) |
1501 S_028208_BR_Y(framebuffer
->height
));
1503 if (cmd_buffer
->device
->dfsm_allowed
) {
1504 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1505 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1508 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1512 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1514 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1515 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1517 if (state
->index_type
!= state
->last_index_type
) {
1518 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1519 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1520 2, state
->index_type
);
1522 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1523 radeon_emit(cs
, state
->index_type
);
1526 state
->last_index_type
= state
->index_type
;
1529 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1530 radeon_emit(cs
, state
->index_va
);
1531 radeon_emit(cs
, state
->index_va
>> 32);
1533 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1534 radeon_emit(cs
, state
->max_index_count
);
1536 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1539 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1541 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1542 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1543 uint32_t pa_sc_mode_cntl_1
=
1544 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1545 uint32_t db_count_control
;
1547 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1548 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1549 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1550 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1551 has_perfect_queries
) {
1552 /* Re-enable out-of-order rasterization if the
1553 * bound pipeline supports it and if it's has
1554 * been disabled before starting any perfect
1555 * occlusion queries.
1557 radeon_set_context_reg(cmd_buffer
->cs
,
1558 R_028A4C_PA_SC_MODE_CNTL_1
,
1561 db_count_control
= 0;
1563 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1566 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1567 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1569 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1571 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1572 S_028004_SAMPLE_RATE(sample_rate
) |
1573 S_028004_ZPASS_ENABLE(1) |
1574 S_028004_SLICE_EVEN_ENABLE(1) |
1575 S_028004_SLICE_ODD_ENABLE(1);
1577 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1578 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1579 has_perfect_queries
) {
1580 /* If the bound pipeline has enabled
1581 * out-of-order rasterization, we should
1582 * disable it before starting any perfect
1583 * occlusion queries.
1585 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1587 radeon_set_context_reg(cmd_buffer
->cs
,
1588 R_028A4C_PA_SC_MODE_CNTL_1
,
1592 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1593 S_028004_SAMPLE_RATE(sample_rate
);
1597 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1601 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1603 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1605 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1606 radv_emit_viewport(cmd_buffer
);
1608 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1609 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1610 radv_emit_scissor(cmd_buffer
);
1612 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1613 radv_emit_line_width(cmd_buffer
);
1615 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1616 radv_emit_blend_constants(cmd_buffer
);
1618 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1619 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1621 radv_emit_stencil(cmd_buffer
);
1623 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1624 radv_emit_depth_bounds(cmd_buffer
);
1626 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1627 radv_emit_depth_bias(cmd_buffer
);
1629 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1630 radv_emit_discard_rectangle(cmd_buffer
);
1632 cmd_buffer
->state
.dirty
&= ~states
;
1636 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1637 VkPipelineBindPoint bind_point
)
1639 struct radv_descriptor_state
*descriptors_state
=
1640 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1641 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1644 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1649 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1650 set
->va
+= bo_offset
;
1654 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1655 VkPipelineBindPoint bind_point
)
1657 struct radv_descriptor_state
*descriptors_state
=
1658 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1659 uint32_t size
= MAX_SETS
* 2 * 4;
1663 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1664 256, &offset
, &ptr
))
1667 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1668 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1669 uint64_t set_va
= 0;
1670 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1671 if (descriptors_state
->valid
& (1u << i
))
1673 uptr
[0] = set_va
& 0xffffffff;
1674 uptr
[1] = set_va
>> 32;
1677 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1680 if (cmd_buffer
->state
.pipeline
) {
1681 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1682 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1685 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1686 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1689 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1690 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1693 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1694 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1697 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1698 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1699 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1702 if (cmd_buffer
->state
.compute_pipeline
)
1703 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1704 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1708 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1709 VkShaderStageFlags stages
)
1711 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1712 VK_PIPELINE_BIND_POINT_COMPUTE
:
1713 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1714 struct radv_descriptor_state
*descriptors_state
=
1715 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1717 if (!descriptors_state
->dirty
)
1720 if (descriptors_state
->push_dirty
)
1721 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1723 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1724 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1725 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1728 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1730 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1732 if (cmd_buffer
->state
.pipeline
) {
1733 radv_foreach_stage(stage
, stages
) {
1734 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1737 radv_emit_descriptor_pointers(cmd_buffer
,
1738 cmd_buffer
->state
.pipeline
,
1739 descriptors_state
, stage
);
1743 if (cmd_buffer
->state
.compute_pipeline
&&
1744 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1745 radv_emit_descriptor_pointers(cmd_buffer
,
1746 cmd_buffer
->state
.compute_pipeline
,
1748 MESA_SHADER_COMPUTE
);
1751 descriptors_state
->dirty
= 0;
1752 descriptors_state
->push_dirty
= false;
1754 if (unlikely(cmd_buffer
->device
->trace_bo
))
1755 radv_save_descriptors(cmd_buffer
, bind_point
);
1757 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1761 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1762 VkShaderStageFlags stages
)
1764 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1765 ? cmd_buffer
->state
.compute_pipeline
1766 : cmd_buffer
->state
.pipeline
;
1767 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1768 VK_PIPELINE_BIND_POINT_COMPUTE
:
1769 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1770 struct radv_descriptor_state
*descriptors_state
=
1771 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1772 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1773 struct radv_shader_variant
*shader
, *prev_shader
;
1778 stages
&= cmd_buffer
->push_constant_stages
;
1780 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1783 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1784 16 * layout
->dynamic_offset_count
,
1785 256, &offset
, &ptr
))
1788 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1789 memcpy((char*)ptr
+ layout
->push_constant_size
,
1790 descriptors_state
->dynamic_buffers
,
1791 16 * layout
->dynamic_offset_count
);
1793 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1796 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1797 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1800 radv_foreach_stage(stage
, stages
) {
1801 shader
= radv_get_shader(pipeline
, stage
);
1803 /* Avoid redundantly emitting the address for merged stages. */
1804 if (shader
&& shader
!= prev_shader
) {
1805 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1806 AC_UD_PUSH_CONSTANTS
, va
);
1808 prev_shader
= shader
;
1812 cmd_buffer
->push_constant_stages
&= ~stages
;
1813 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1817 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1818 bool pipeline_is_dirty
)
1820 if ((pipeline_is_dirty
||
1821 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1822 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1823 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1824 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1828 uint32_t count
= velems
->count
;
1831 /* allocate some descriptor state for vertex buffers */
1832 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1833 &vb_offset
, &vb_ptr
))
1836 for (i
= 0; i
< count
; i
++) {
1837 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1839 int vb
= velems
->binding
[i
];
1840 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1841 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1843 va
= radv_buffer_get_va(buffer
->bo
);
1845 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1846 va
+= offset
+ buffer
->offset
;
1848 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1849 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1850 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1852 desc
[2] = buffer
->size
- offset
;
1853 desc
[3] = velems
->rsrc_word3
[i
];
1856 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1859 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1860 AC_UD_VS_VERTEX_BUFFERS
, va
);
1862 cmd_buffer
->state
.vb_va
= va
;
1863 cmd_buffer
->state
.vb_size
= count
* 16;
1864 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
1866 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1870 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1872 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
1873 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1874 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1878 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1879 bool instanced_draw
, bool indirect_draw
,
1880 uint32_t draw_vertex_count
)
1882 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1883 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1884 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1885 uint32_t ia_multi_vgt_param
;
1886 int32_t primitive_reset_en
;
1889 ia_multi_vgt_param
=
1890 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1891 indirect_draw
, draw_vertex_count
);
1893 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1894 if (info
->chip_class
>= GFX9
) {
1895 radeon_set_uconfig_reg_idx(cs
,
1896 R_030960_IA_MULTI_VGT_PARAM
,
1897 4, ia_multi_vgt_param
);
1898 } else if (info
->chip_class
>= CIK
) {
1899 radeon_set_context_reg_idx(cs
,
1900 R_028AA8_IA_MULTI_VGT_PARAM
,
1901 1, ia_multi_vgt_param
);
1903 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1904 ia_multi_vgt_param
);
1906 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1909 /* Primitive restart. */
1910 primitive_reset_en
=
1911 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1913 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1914 state
->last_primitive_reset_en
= primitive_reset_en
;
1915 if (info
->chip_class
>= GFX9
) {
1916 radeon_set_uconfig_reg(cs
,
1917 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1918 primitive_reset_en
);
1920 radeon_set_context_reg(cs
,
1921 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1922 primitive_reset_en
);
1926 if (primitive_reset_en
) {
1927 uint32_t primitive_reset_index
=
1928 state
->index_type
? 0xffffffffu
: 0xffffu
;
1930 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1931 radeon_set_context_reg(cs
,
1932 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1933 primitive_reset_index
);
1934 state
->last_primitive_reset_index
= primitive_reset_index
;
1939 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1940 VkPipelineStageFlags src_stage_mask
)
1942 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1943 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1944 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1945 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1946 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1949 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1950 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1951 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1952 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1953 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1954 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1955 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1956 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1957 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1958 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1959 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1960 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1961 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1962 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1963 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1964 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1968 static enum radv_cmd_flush_bits
1969 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1970 VkAccessFlags src_flags
,
1971 struct radv_image
*image
)
1973 enum radv_cmd_flush_bits flush_bits
= 0;
1975 for_each_bit(b
, src_flags
) {
1976 switch ((VkAccessFlagBits
)(1 << b
)) {
1977 case VK_ACCESS_SHADER_WRITE_BIT
:
1978 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1980 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1981 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
1982 if (!image
|| (image
&& radv_image_has_CB_metadata(image
))) {
1983 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1986 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1987 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
1988 if (!image
|| (image
&& radv_image_has_htile(image
))) {
1989 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1992 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1993 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1994 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1995 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1996 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1997 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2006 static enum radv_cmd_flush_bits
2007 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2008 VkAccessFlags dst_flags
,
2009 struct radv_image
*image
)
2011 enum radv_cmd_flush_bits flush_bits
= 0;
2013 for_each_bit(b
, dst_flags
) {
2014 switch ((VkAccessFlagBits
)(1 << b
)) {
2015 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2016 case VK_ACCESS_INDEX_READ_BIT
:
2018 case VK_ACCESS_UNIFORM_READ_BIT
:
2019 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2021 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2022 case VK_ACCESS_SHADER_READ_BIT
:
2023 case VK_ACCESS_TRANSFER_READ_BIT
:
2024 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2025 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2026 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2028 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2029 /* TODO: change to image && when the image gets passed
2030 * through from the subpass. */
2031 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2032 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2033 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2035 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2036 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2037 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2038 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2047 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2049 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2051 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2052 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2056 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2057 struct radv_subpass_attachment att
)
2059 unsigned idx
= att
.attachment
;
2060 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2061 VkImageSubresourceRange range
;
2062 range
.aspectMask
= 0;
2063 range
.baseMipLevel
= view
->base_mip
;
2064 range
.levelCount
= 1;
2065 range
.baseArrayLayer
= view
->base_layer
;
2066 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2068 radv_handle_image_transition(cmd_buffer
,
2070 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2071 att
.layout
, 0, 0, &range
,
2072 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2074 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2080 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2081 const struct radv_subpass
*subpass
, bool transitions
)
2084 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2086 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2087 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2088 radv_handle_subpass_image_transition(cmd_buffer
,
2089 subpass
->color_attachments
[i
]);
2092 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2093 radv_handle_subpass_image_transition(cmd_buffer
,
2094 subpass
->input_attachments
[i
]);
2097 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2098 radv_handle_subpass_image_transition(cmd_buffer
,
2099 subpass
->depth_stencil_attachment
);
2103 cmd_buffer
->state
.subpass
= subpass
;
2105 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2109 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2110 struct radv_render_pass
*pass
,
2111 const VkRenderPassBeginInfo
*info
)
2113 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2115 if (pass
->attachment_count
== 0) {
2116 state
->attachments
= NULL
;
2120 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2121 pass
->attachment_count
*
2122 sizeof(state
->attachments
[0]),
2123 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2124 if (state
->attachments
== NULL
) {
2125 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2126 return cmd_buffer
->record_result
;
2129 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2130 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2131 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2132 VkImageAspectFlags clear_aspects
= 0;
2134 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2135 /* color attachment */
2136 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2137 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2140 /* depthstencil attachment */
2141 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2142 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2143 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2144 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2145 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2146 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2148 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2149 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2150 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2154 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2155 state
->attachments
[i
].cleared_views
= 0;
2156 if (clear_aspects
&& info
) {
2157 assert(info
->clearValueCount
> i
);
2158 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2161 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2167 VkResult
radv_AllocateCommandBuffers(
2169 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2170 VkCommandBuffer
*pCommandBuffers
)
2172 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2173 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2175 VkResult result
= VK_SUCCESS
;
2178 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2180 if (!list_empty(&pool
->free_cmd_buffers
)) {
2181 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2183 list_del(&cmd_buffer
->pool_link
);
2184 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2186 result
= radv_reset_cmd_buffer(cmd_buffer
);
2187 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2188 cmd_buffer
->level
= pAllocateInfo
->level
;
2190 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2192 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2193 &pCommandBuffers
[i
]);
2195 if (result
!= VK_SUCCESS
)
2199 if (result
!= VK_SUCCESS
) {
2200 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2201 i
, pCommandBuffers
);
2203 /* From the Vulkan 1.0.66 spec:
2205 * "vkAllocateCommandBuffers can be used to create multiple
2206 * command buffers. If the creation of any of those command
2207 * buffers fails, the implementation must destroy all
2208 * successfully created command buffer objects from this
2209 * command, set all entries of the pCommandBuffers array to
2210 * NULL and return the error."
2212 memset(pCommandBuffers
, 0,
2213 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2219 void radv_FreeCommandBuffers(
2221 VkCommandPool commandPool
,
2222 uint32_t commandBufferCount
,
2223 const VkCommandBuffer
*pCommandBuffers
)
2225 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2226 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2229 if (cmd_buffer
->pool
) {
2230 list_del(&cmd_buffer
->pool_link
);
2231 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2233 radv_cmd_buffer_destroy(cmd_buffer
);
2239 VkResult
radv_ResetCommandBuffer(
2240 VkCommandBuffer commandBuffer
,
2241 VkCommandBufferResetFlags flags
)
2243 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2244 return radv_reset_cmd_buffer(cmd_buffer
);
2247 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2249 struct radv_device
*device
= cmd_buffer
->device
;
2250 if (device
->gfx_init
) {
2251 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2252 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, device
->gfx_init
, 8);
2253 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2254 radeon_emit(cmd_buffer
->cs
, va
);
2255 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2256 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2258 si_init_config(cmd_buffer
);
2261 VkResult
radv_BeginCommandBuffer(
2262 VkCommandBuffer commandBuffer
,
2263 const VkCommandBufferBeginInfo
*pBeginInfo
)
2265 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2266 VkResult result
= VK_SUCCESS
;
2268 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2269 /* If the command buffer has already been resetted with
2270 * vkResetCommandBuffer, no need to do it again.
2272 result
= radv_reset_cmd_buffer(cmd_buffer
);
2273 if (result
!= VK_SUCCESS
)
2277 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2278 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2279 cmd_buffer
->state
.last_index_type
= -1;
2280 cmd_buffer
->state
.last_num_instances
= -1;
2281 cmd_buffer
->state
.last_vertex_offset
= -1;
2282 cmd_buffer
->state
.last_first_instance
= -1;
2283 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2285 /* setup initial configuration into command buffer */
2286 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2287 switch (cmd_buffer
->queue_family_index
) {
2288 case RADV_QUEUE_GENERAL
:
2289 emit_gfx_buffer_state(cmd_buffer
);
2291 case RADV_QUEUE_COMPUTE
:
2292 si_init_compute(cmd_buffer
);
2294 case RADV_QUEUE_TRANSFER
:
2300 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2301 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2302 assert(pBeginInfo
->pInheritanceInfo
);
2303 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2304 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2306 struct radv_subpass
*subpass
=
2307 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2309 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2310 if (result
!= VK_SUCCESS
)
2313 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2316 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2317 struct radv_device
*device
= cmd_buffer
->device
;
2319 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2320 device
->trace_bo
, 8);
2322 radv_cmd_buffer_trace_emit(cmd_buffer
);
2325 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2330 void radv_CmdBindVertexBuffers(
2331 VkCommandBuffer commandBuffer
,
2332 uint32_t firstBinding
,
2333 uint32_t bindingCount
,
2334 const VkBuffer
* pBuffers
,
2335 const VkDeviceSize
* pOffsets
)
2337 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2338 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2339 bool changed
= false;
2341 /* We have to defer setting up vertex buffer since we need the buffer
2342 * stride from the pipeline. */
2344 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2345 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2346 uint32_t idx
= firstBinding
+ i
;
2349 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2350 vb
[idx
].offset
!= pOffsets
[i
])) {
2354 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2355 vb
[idx
].offset
= pOffsets
[i
];
2357 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2358 vb
[idx
].buffer
->bo
, 8);
2362 /* No state changes. */
2366 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2369 void radv_CmdBindIndexBuffer(
2370 VkCommandBuffer commandBuffer
,
2372 VkDeviceSize offset
,
2373 VkIndexType indexType
)
2375 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2376 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2378 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2379 cmd_buffer
->state
.index_offset
== offset
&&
2380 cmd_buffer
->state
.index_type
== indexType
) {
2381 /* No state changes. */
2385 cmd_buffer
->state
.index_buffer
= index_buffer
;
2386 cmd_buffer
->state
.index_offset
= offset
;
2387 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2388 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2389 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2391 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2392 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2393 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2394 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
, 8);
2399 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2400 VkPipelineBindPoint bind_point
,
2401 struct radv_descriptor_set
*set
, unsigned idx
)
2403 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2405 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2409 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2411 if (!cmd_buffer
->device
->use_global_bo_list
) {
2412 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2413 if (set
->descriptors
[j
])
2414 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2418 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
, 8);
2421 void radv_CmdBindDescriptorSets(
2422 VkCommandBuffer commandBuffer
,
2423 VkPipelineBindPoint pipelineBindPoint
,
2424 VkPipelineLayout _layout
,
2426 uint32_t descriptorSetCount
,
2427 const VkDescriptorSet
* pDescriptorSets
,
2428 uint32_t dynamicOffsetCount
,
2429 const uint32_t* pDynamicOffsets
)
2431 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2432 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2433 unsigned dyn_idx
= 0;
2435 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2436 struct radv_descriptor_state
*descriptors_state
=
2437 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2439 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2440 unsigned idx
= i
+ firstSet
;
2441 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2442 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2444 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2445 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2446 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2447 assert(dyn_idx
< dynamicOffsetCount
);
2449 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2450 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2452 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2453 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2454 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2455 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2456 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2457 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2458 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2459 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2460 cmd_buffer
->push_constant_stages
|=
2461 set
->layout
->dynamic_shader_stages
;
2466 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2467 struct radv_descriptor_set
*set
,
2468 struct radv_descriptor_set_layout
*layout
,
2469 VkPipelineBindPoint bind_point
)
2471 struct radv_descriptor_state
*descriptors_state
=
2472 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2473 set
->size
= layout
->size
;
2474 set
->layout
= layout
;
2476 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2477 size_t new_size
= MAX2(set
->size
, 1024);
2478 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2479 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2481 free(set
->mapped_ptr
);
2482 set
->mapped_ptr
= malloc(new_size
);
2484 if (!set
->mapped_ptr
) {
2485 descriptors_state
->push_set
.capacity
= 0;
2486 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2490 descriptors_state
->push_set
.capacity
= new_size
;
2496 void radv_meta_push_descriptor_set(
2497 struct radv_cmd_buffer
* cmd_buffer
,
2498 VkPipelineBindPoint pipelineBindPoint
,
2499 VkPipelineLayout _layout
,
2501 uint32_t descriptorWriteCount
,
2502 const VkWriteDescriptorSet
* pDescriptorWrites
)
2504 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2505 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2509 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2511 push_set
->size
= layout
->set
[set
].layout
->size
;
2512 push_set
->layout
= layout
->set
[set
].layout
;
2514 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2516 (void**) &push_set
->mapped_ptr
))
2519 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2520 push_set
->va
+= bo_offset
;
2522 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2523 radv_descriptor_set_to_handle(push_set
),
2524 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2526 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2529 void radv_CmdPushDescriptorSetKHR(
2530 VkCommandBuffer commandBuffer
,
2531 VkPipelineBindPoint pipelineBindPoint
,
2532 VkPipelineLayout _layout
,
2534 uint32_t descriptorWriteCount
,
2535 const VkWriteDescriptorSet
* pDescriptorWrites
)
2537 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2538 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2539 struct radv_descriptor_state
*descriptors_state
=
2540 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2541 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2543 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2545 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2546 layout
->set
[set
].layout
,
2550 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2551 radv_descriptor_set_to_handle(push_set
),
2552 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2554 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2555 descriptors_state
->push_dirty
= true;
2558 void radv_CmdPushDescriptorSetWithTemplateKHR(
2559 VkCommandBuffer commandBuffer
,
2560 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2561 VkPipelineLayout _layout
,
2565 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2566 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2567 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2568 struct radv_descriptor_state
*descriptors_state
=
2569 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2570 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2572 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2574 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2575 layout
->set
[set
].layout
,
2579 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2580 descriptorUpdateTemplate
, pData
);
2582 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2583 descriptors_state
->push_dirty
= true;
2586 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2587 VkPipelineLayout layout
,
2588 VkShaderStageFlags stageFlags
,
2591 const void* pValues
)
2593 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2594 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2595 cmd_buffer
->push_constant_stages
|= stageFlags
;
2598 VkResult
radv_EndCommandBuffer(
2599 VkCommandBuffer commandBuffer
)
2601 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2603 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2604 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2605 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2606 si_emit_cache_flush(cmd_buffer
);
2609 /* Make sure CP DMA is idle at the end of IBs because the kernel
2610 * doesn't wait for it.
2612 si_cp_dma_wait_for_idle(cmd_buffer
);
2614 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2616 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2617 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2619 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2621 return cmd_buffer
->record_result
;
2625 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2627 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2629 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2632 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2634 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2635 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2637 cmd_buffer
->compute_scratch_size_needed
=
2638 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2639 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2641 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2642 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
, 8);
2644 if (unlikely(cmd_buffer
->device
->trace_bo
))
2645 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2648 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2649 VkPipelineBindPoint bind_point
)
2651 struct radv_descriptor_state
*descriptors_state
=
2652 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2654 descriptors_state
->dirty
|= descriptors_state
->valid
;
2657 void radv_CmdBindPipeline(
2658 VkCommandBuffer commandBuffer
,
2659 VkPipelineBindPoint pipelineBindPoint
,
2660 VkPipeline _pipeline
)
2662 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2663 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2665 switch (pipelineBindPoint
) {
2666 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2667 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2669 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2671 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2672 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2674 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2675 if (cmd_buffer
->state
.pipeline
== pipeline
)
2677 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2679 cmd_buffer
->state
.pipeline
= pipeline
;
2683 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2684 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2686 /* the new vertex shader might not have the same user regs */
2687 cmd_buffer
->state
.last_first_instance
= -1;
2688 cmd_buffer
->state
.last_vertex_offset
= -1;
2690 /* Prefetch all pipeline shaders at first draw time. */
2691 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
2693 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2695 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2696 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2697 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2698 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2700 if (radv_pipeline_has_tess(pipeline
))
2701 cmd_buffer
->tess_rings_needed
= true;
2703 if (radv_pipeline_has_gs(pipeline
)) {
2704 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2705 AC_UD_SCRATCH_RING_OFFSETS
);
2706 if (cmd_buffer
->ring_offsets_idx
== -1)
2707 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2708 else if (loc
->sgpr_idx
!= -1)
2709 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2713 assert(!"invalid bind point");
2718 void radv_CmdSetViewport(
2719 VkCommandBuffer commandBuffer
,
2720 uint32_t firstViewport
,
2721 uint32_t viewportCount
,
2722 const VkViewport
* pViewports
)
2724 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2725 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2726 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2728 assert(firstViewport
< MAX_VIEWPORTS
);
2729 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2731 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
2732 viewportCount
* sizeof(*pViewports
));
2734 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2737 void radv_CmdSetScissor(
2738 VkCommandBuffer commandBuffer
,
2739 uint32_t firstScissor
,
2740 uint32_t scissorCount
,
2741 const VkRect2D
* pScissors
)
2743 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2744 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2745 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2747 assert(firstScissor
< MAX_SCISSORS
);
2748 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2750 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
2751 scissorCount
* sizeof(*pScissors
));
2753 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2756 void radv_CmdSetLineWidth(
2757 VkCommandBuffer commandBuffer
,
2760 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2761 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2762 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2765 void radv_CmdSetDepthBias(
2766 VkCommandBuffer commandBuffer
,
2767 float depthBiasConstantFactor
,
2768 float depthBiasClamp
,
2769 float depthBiasSlopeFactor
)
2771 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2773 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2774 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2775 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2777 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2780 void radv_CmdSetBlendConstants(
2781 VkCommandBuffer commandBuffer
,
2782 const float blendConstants
[4])
2784 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2786 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2787 blendConstants
, sizeof(float) * 4);
2789 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2792 void radv_CmdSetDepthBounds(
2793 VkCommandBuffer commandBuffer
,
2794 float minDepthBounds
,
2795 float maxDepthBounds
)
2797 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2799 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2800 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2802 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2805 void radv_CmdSetStencilCompareMask(
2806 VkCommandBuffer commandBuffer
,
2807 VkStencilFaceFlags faceMask
,
2808 uint32_t compareMask
)
2810 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2812 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2813 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2814 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2815 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2817 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2820 void radv_CmdSetStencilWriteMask(
2821 VkCommandBuffer commandBuffer
,
2822 VkStencilFaceFlags faceMask
,
2825 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2827 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2828 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2829 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2830 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2832 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2835 void radv_CmdSetStencilReference(
2836 VkCommandBuffer commandBuffer
,
2837 VkStencilFaceFlags faceMask
,
2840 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2842 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2843 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2844 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2845 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2847 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2850 void radv_CmdSetDiscardRectangleEXT(
2851 VkCommandBuffer commandBuffer
,
2852 uint32_t firstDiscardRectangle
,
2853 uint32_t discardRectangleCount
,
2854 const VkRect2D
* pDiscardRectangles
)
2856 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2857 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2858 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
2860 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
2861 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
2863 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
2864 pDiscardRectangles
, discardRectangleCount
);
2866 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
2869 void radv_CmdExecuteCommands(
2870 VkCommandBuffer commandBuffer
,
2871 uint32_t commandBufferCount
,
2872 const VkCommandBuffer
* pCmdBuffers
)
2874 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2876 assert(commandBufferCount
> 0);
2878 /* Emit pending flushes on primary prior to executing secondary */
2879 si_emit_cache_flush(primary
);
2881 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2882 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2884 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2885 secondary
->scratch_size_needed
);
2886 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2887 secondary
->compute_scratch_size_needed
);
2889 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2890 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2891 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2892 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2893 if (secondary
->tess_rings_needed
)
2894 primary
->tess_rings_needed
= true;
2895 if (secondary
->sample_positions_needed
)
2896 primary
->sample_positions_needed
= true;
2898 if (secondary
->ring_offsets_idx
!= -1) {
2899 if (primary
->ring_offsets_idx
== -1)
2900 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2902 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2904 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2907 /* When the secondary command buffer is compute only we don't
2908 * need to re-emit the current graphics pipeline.
2910 if (secondary
->state
.emitted_pipeline
) {
2911 primary
->state
.emitted_pipeline
=
2912 secondary
->state
.emitted_pipeline
;
2915 /* When the secondary command buffer is graphics only we don't
2916 * need to re-emit the current compute pipeline.
2918 if (secondary
->state
.emitted_compute_pipeline
) {
2919 primary
->state
.emitted_compute_pipeline
=
2920 secondary
->state
.emitted_compute_pipeline
;
2923 /* Only re-emit the draw packets when needed. */
2924 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2925 primary
->state
.last_primitive_reset_en
=
2926 secondary
->state
.last_primitive_reset_en
;
2929 if (secondary
->state
.last_primitive_reset_index
) {
2930 primary
->state
.last_primitive_reset_index
=
2931 secondary
->state
.last_primitive_reset_index
;
2934 if (secondary
->state
.last_ia_multi_vgt_param
) {
2935 primary
->state
.last_ia_multi_vgt_param
=
2936 secondary
->state
.last_ia_multi_vgt_param
;
2939 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
2940 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
2941 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
2943 if (secondary
->state
.last_index_type
!= -1) {
2944 primary
->state
.last_index_type
=
2945 secondary
->state
.last_index_type
;
2949 /* After executing commands from secondary buffers we have to dirty
2952 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2953 RADV_CMD_DIRTY_INDEX_BUFFER
|
2954 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2955 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
2956 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
2959 VkResult
radv_CreateCommandPool(
2961 const VkCommandPoolCreateInfo
* pCreateInfo
,
2962 const VkAllocationCallbacks
* pAllocator
,
2963 VkCommandPool
* pCmdPool
)
2965 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2966 struct radv_cmd_pool
*pool
;
2968 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2969 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2971 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2974 pool
->alloc
= *pAllocator
;
2976 pool
->alloc
= device
->alloc
;
2978 list_inithead(&pool
->cmd_buffers
);
2979 list_inithead(&pool
->free_cmd_buffers
);
2981 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2983 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2989 void radv_DestroyCommandPool(
2991 VkCommandPool commandPool
,
2992 const VkAllocationCallbacks
* pAllocator
)
2994 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2995 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3000 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3001 &pool
->cmd_buffers
, pool_link
) {
3002 radv_cmd_buffer_destroy(cmd_buffer
);
3005 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3006 &pool
->free_cmd_buffers
, pool_link
) {
3007 radv_cmd_buffer_destroy(cmd_buffer
);
3010 vk_free2(&device
->alloc
, pAllocator
, pool
);
3013 VkResult
radv_ResetCommandPool(
3015 VkCommandPool commandPool
,
3016 VkCommandPoolResetFlags flags
)
3018 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3021 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3022 &pool
->cmd_buffers
, pool_link
) {
3023 result
= radv_reset_cmd_buffer(cmd_buffer
);
3024 if (result
!= VK_SUCCESS
)
3031 void radv_TrimCommandPool(
3033 VkCommandPool commandPool
,
3034 VkCommandPoolTrimFlagsKHR flags
)
3036 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3041 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3042 &pool
->free_cmd_buffers
, pool_link
) {
3043 radv_cmd_buffer_destroy(cmd_buffer
);
3047 void radv_CmdBeginRenderPass(
3048 VkCommandBuffer commandBuffer
,
3049 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3050 VkSubpassContents contents
)
3052 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3053 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3054 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3056 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3057 cmd_buffer
->cs
, 2048);
3058 MAYBE_UNUSED VkResult result
;
3060 cmd_buffer
->state
.framebuffer
= framebuffer
;
3061 cmd_buffer
->state
.pass
= pass
;
3062 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3064 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3065 if (result
!= VK_SUCCESS
)
3068 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3069 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3071 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3074 void radv_CmdBeginRenderPass2KHR(
3075 VkCommandBuffer commandBuffer
,
3076 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3077 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3079 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3080 pSubpassBeginInfo
->contents
);
3083 void radv_CmdNextSubpass(
3084 VkCommandBuffer commandBuffer
,
3085 VkSubpassContents contents
)
3087 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3089 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3091 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3094 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3095 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3098 void radv_CmdNextSubpass2KHR(
3099 VkCommandBuffer commandBuffer
,
3100 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3101 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3103 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3106 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3108 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3109 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3110 if (!radv_get_shader(pipeline
, stage
))
3113 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3114 if (loc
->sgpr_idx
== -1)
3116 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3117 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3120 if (pipeline
->gs_copy_shader
) {
3121 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3122 if (loc
->sgpr_idx
!= -1) {
3123 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3124 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3130 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3131 uint32_t vertex_count
)
3133 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3134 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3135 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3136 S_0287F0_USE_OPAQUE(0));
3140 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3142 uint32_t index_count
)
3144 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
3145 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3146 radeon_emit(cmd_buffer
->cs
, index_va
);
3147 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3148 radeon_emit(cmd_buffer
->cs
, index_count
);
3149 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3153 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3155 uint32_t draw_count
,
3159 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3160 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3161 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3162 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3163 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3166 /* just reset draw state for vertex data */
3167 cmd_buffer
->state
.last_first_instance
= -1;
3168 cmd_buffer
->state
.last_num_instances
= -1;
3169 cmd_buffer
->state
.last_vertex_offset
= -1;
3171 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3172 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3173 PKT3_DRAW_INDIRECT
, 3, false));
3175 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3176 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3177 radeon_emit(cs
, di_src_sel
);
3179 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3180 PKT3_DRAW_INDIRECT_MULTI
,
3183 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3184 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3185 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3186 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3187 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3188 radeon_emit(cs
, draw_count
); /* count */
3189 radeon_emit(cs
, count_va
); /* count_addr */
3190 radeon_emit(cs
, count_va
>> 32);
3191 radeon_emit(cs
, stride
); /* stride */
3192 radeon_emit(cs
, di_src_sel
);
3196 struct radv_draw_info
{
3198 * Number of vertices.
3203 * Index of the first vertex.
3205 int32_t vertex_offset
;
3208 * First instance id.
3210 uint32_t first_instance
;
3213 * Number of instances.
3215 uint32_t instance_count
;
3218 * First index (indexed draws only).
3220 uint32_t first_index
;
3223 * Whether it's an indexed draw.
3228 * Indirect draw parameters resource.
3230 struct radv_buffer
*indirect
;
3231 uint64_t indirect_offset
;
3235 * Draw count parameters resource.
3237 struct radv_buffer
*count_buffer
;
3238 uint64_t count_buffer_offset
;
3242 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3243 const struct radv_draw_info
*info
)
3245 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3246 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3247 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3249 if (info
->indirect
) {
3250 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3251 uint64_t count_va
= 0;
3253 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3255 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3257 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3259 radeon_emit(cs
, va
);
3260 radeon_emit(cs
, va
>> 32);
3262 if (info
->count_buffer
) {
3263 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3264 count_va
+= info
->count_buffer
->offset
+
3265 info
->count_buffer_offset
;
3267 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
, 8);
3270 if (!state
->subpass
->view_mask
) {
3271 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3278 for_each_bit(i
, state
->subpass
->view_mask
) {
3279 radv_emit_view_index(cmd_buffer
, i
);
3281 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3289 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3291 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3292 info
->first_instance
!= state
->last_first_instance
) {
3293 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3294 state
->pipeline
->graphics
.vtx_emit_num
);
3296 radeon_emit(cs
, info
->vertex_offset
);
3297 radeon_emit(cs
, info
->first_instance
);
3298 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3300 state
->last_first_instance
= info
->first_instance
;
3301 state
->last_vertex_offset
= info
->vertex_offset
;
3304 if (state
->last_num_instances
!= info
->instance_count
) {
3305 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3306 radeon_emit(cs
, info
->instance_count
);
3307 state
->last_num_instances
= info
->instance_count
;
3310 if (info
->indexed
) {
3311 int index_size
= state
->index_type
? 4 : 2;
3314 index_va
= state
->index_va
;
3315 index_va
+= info
->first_index
* index_size
;
3317 if (!state
->subpass
->view_mask
) {
3318 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3323 for_each_bit(i
, state
->subpass
->view_mask
) {
3324 radv_emit_view_index(cmd_buffer
, i
);
3326 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3332 if (!state
->subpass
->view_mask
) {
3333 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3336 for_each_bit(i
, state
->subpass
->view_mask
) {
3337 radv_emit_view_index(cmd_buffer
, i
);
3339 radv_cs_emit_draw_packet(cmd_buffer
,
3348 * Vega and raven have a bug which triggers if there are multiple context
3349 * register contexts active at the same time with different scissor values.
3351 * There are two possible workarounds:
3352 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3353 * there is only ever 1 active set of scissor values at the same time.
3355 * 2) Whenever the hardware switches contexts we have to set the scissor
3356 * registers again even if it is a noop. That way the new context gets
3357 * the correct scissor values.
3359 * This implements option 2. radv_need_late_scissor_emission needs to
3360 * return true on affected HW if radv_emit_all_graphics_states sets
3361 * any context registers.
3363 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3366 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3368 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3371 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3373 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3374 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
| RADV_CMD_DIRTY_VERTEX_BUFFER
| RADV_CMD_DIRTY_PIPELINE
);
3376 /* Assume all state changes except these two can imply context rolls. */
3377 if (cmd_buffer
->state
.dirty
& used_states
)
3380 if (cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3383 if (indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3384 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3391 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3392 const struct radv_draw_info
*info
)
3394 bool late_scissor_emission
= radv_need_late_scissor_emission(cmd_buffer
, info
->indexed
);
3396 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3397 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3398 radv_emit_rbplus_state(cmd_buffer
);
3400 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3401 radv_emit_graphics_pipeline(cmd_buffer
);
3403 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3404 radv_emit_framebuffer_state(cmd_buffer
);
3406 if (info
->indexed
) {
3407 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3408 radv_emit_index_buffer(cmd_buffer
);
3410 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3411 * so the state must be re-emitted before the next indexed
3414 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3415 cmd_buffer
->state
.last_index_type
= -1;
3416 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3420 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3422 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3423 info
->instance_count
> 1, info
->indirect
,
3424 info
->indirect
? 0 : info
->count
);
3426 if (late_scissor_emission
)
3427 radv_emit_scissor(cmd_buffer
);
3431 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3432 const struct radv_draw_info
*info
)
3435 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3436 bool pipeline_is_dirty
=
3437 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3438 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3440 MAYBE_UNUSED
unsigned cdw_max
=
3441 radeon_check_space(cmd_buffer
->device
->ws
,
3442 cmd_buffer
->cs
, 4096);
3444 /* Use optimal packet order based on whether we need to sync the
3447 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3448 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3449 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3450 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3451 /* If we have to wait for idle, set all states first, so that
3452 * all SET packets are processed in parallel with previous draw
3453 * calls. Then upload descriptors, set shader pointers, and
3454 * draw, and prefetch at the end. This ensures that the time
3455 * the CUs are idle is very short. (there are only SET_SH
3456 * packets between the wait and the draw)
3458 radv_emit_all_graphics_states(cmd_buffer
, info
);
3459 si_emit_cache_flush(cmd_buffer
);
3460 /* <-- CUs are idle here --> */
3462 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3464 radv_emit_draw_packets(cmd_buffer
, info
);
3465 /* <-- CUs are busy here --> */
3467 /* Start prefetches after the draw has been started. Both will
3468 * run in parallel, but starting the draw first is more
3471 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3472 radv_emit_prefetch_L2(cmd_buffer
,
3473 cmd_buffer
->state
.pipeline
, false);
3476 /* If we don't wait for idle, start prefetches first, then set
3477 * states, and draw at the end.
3479 si_emit_cache_flush(cmd_buffer
);
3481 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3482 /* Only prefetch the vertex shader and VBO descriptors
3483 * in order to start the draw as soon as possible.
3485 radv_emit_prefetch_L2(cmd_buffer
,
3486 cmd_buffer
->state
.pipeline
, true);
3489 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3491 radv_emit_all_graphics_states(cmd_buffer
, info
);
3492 radv_emit_draw_packets(cmd_buffer
, info
);
3494 /* Prefetch the remaining shaders after the draw has been
3497 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3498 radv_emit_prefetch_L2(cmd_buffer
,
3499 cmd_buffer
->state
.pipeline
, false);
3503 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3504 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3508 VkCommandBuffer commandBuffer
,
3509 uint32_t vertexCount
,
3510 uint32_t instanceCount
,
3511 uint32_t firstVertex
,
3512 uint32_t firstInstance
)
3514 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3515 struct radv_draw_info info
= {};
3517 info
.count
= vertexCount
;
3518 info
.instance_count
= instanceCount
;
3519 info
.first_instance
= firstInstance
;
3520 info
.vertex_offset
= firstVertex
;
3522 radv_draw(cmd_buffer
, &info
);
3525 void radv_CmdDrawIndexed(
3526 VkCommandBuffer commandBuffer
,
3527 uint32_t indexCount
,
3528 uint32_t instanceCount
,
3529 uint32_t firstIndex
,
3530 int32_t vertexOffset
,
3531 uint32_t firstInstance
)
3533 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3534 struct radv_draw_info info
= {};
3536 info
.indexed
= true;
3537 info
.count
= indexCount
;
3538 info
.instance_count
= instanceCount
;
3539 info
.first_index
= firstIndex
;
3540 info
.vertex_offset
= vertexOffset
;
3541 info
.first_instance
= firstInstance
;
3543 radv_draw(cmd_buffer
, &info
);
3546 void radv_CmdDrawIndirect(
3547 VkCommandBuffer commandBuffer
,
3549 VkDeviceSize offset
,
3553 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3554 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3555 struct radv_draw_info info
= {};
3557 info
.count
= drawCount
;
3558 info
.indirect
= buffer
;
3559 info
.indirect_offset
= offset
;
3560 info
.stride
= stride
;
3562 radv_draw(cmd_buffer
, &info
);
3565 void radv_CmdDrawIndexedIndirect(
3566 VkCommandBuffer commandBuffer
,
3568 VkDeviceSize offset
,
3572 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3573 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3574 struct radv_draw_info info
= {};
3576 info
.indexed
= true;
3577 info
.count
= drawCount
;
3578 info
.indirect
= buffer
;
3579 info
.indirect_offset
= offset
;
3580 info
.stride
= stride
;
3582 radv_draw(cmd_buffer
, &info
);
3585 void radv_CmdDrawIndirectCountAMD(
3586 VkCommandBuffer commandBuffer
,
3588 VkDeviceSize offset
,
3589 VkBuffer _countBuffer
,
3590 VkDeviceSize countBufferOffset
,
3591 uint32_t maxDrawCount
,
3594 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3595 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3596 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3597 struct radv_draw_info info
= {};
3599 info
.count
= maxDrawCount
;
3600 info
.indirect
= buffer
;
3601 info
.indirect_offset
= offset
;
3602 info
.count_buffer
= count_buffer
;
3603 info
.count_buffer_offset
= countBufferOffset
;
3604 info
.stride
= stride
;
3606 radv_draw(cmd_buffer
, &info
);
3609 void radv_CmdDrawIndexedIndirectCountAMD(
3610 VkCommandBuffer commandBuffer
,
3612 VkDeviceSize offset
,
3613 VkBuffer _countBuffer
,
3614 VkDeviceSize countBufferOffset
,
3615 uint32_t maxDrawCount
,
3618 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3619 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3620 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3621 struct radv_draw_info info
= {};
3623 info
.indexed
= true;
3624 info
.count
= maxDrawCount
;
3625 info
.indirect
= buffer
;
3626 info
.indirect_offset
= offset
;
3627 info
.count_buffer
= count_buffer
;
3628 info
.count_buffer_offset
= countBufferOffset
;
3629 info
.stride
= stride
;
3631 radv_draw(cmd_buffer
, &info
);
3634 void radv_CmdDrawIndirectCountKHR(
3635 VkCommandBuffer commandBuffer
,
3637 VkDeviceSize offset
,
3638 VkBuffer _countBuffer
,
3639 VkDeviceSize countBufferOffset
,
3640 uint32_t maxDrawCount
,
3643 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3644 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3645 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3646 struct radv_draw_info info
= {};
3648 info
.count
= maxDrawCount
;
3649 info
.indirect
= buffer
;
3650 info
.indirect_offset
= offset
;
3651 info
.count_buffer
= count_buffer
;
3652 info
.count_buffer_offset
= countBufferOffset
;
3653 info
.stride
= stride
;
3655 radv_draw(cmd_buffer
, &info
);
3658 void radv_CmdDrawIndexedIndirectCountKHR(
3659 VkCommandBuffer commandBuffer
,
3661 VkDeviceSize offset
,
3662 VkBuffer _countBuffer
,
3663 VkDeviceSize countBufferOffset
,
3664 uint32_t maxDrawCount
,
3667 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3668 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3669 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3670 struct radv_draw_info info
= {};
3672 info
.indexed
= true;
3673 info
.count
= maxDrawCount
;
3674 info
.indirect
= buffer
;
3675 info
.indirect_offset
= offset
;
3676 info
.count_buffer
= count_buffer
;
3677 info
.count_buffer_offset
= countBufferOffset
;
3678 info
.stride
= stride
;
3680 radv_draw(cmd_buffer
, &info
);
3683 struct radv_dispatch_info
{
3685 * Determine the layout of the grid (in block units) to be used.
3690 * A starting offset for the grid. If unaligned is set, the offset
3691 * must still be aligned.
3693 uint32_t offsets
[3];
3695 * Whether it's an unaligned compute dispatch.
3700 * Indirect compute parameters resource.
3702 struct radv_buffer
*indirect
;
3703 uint64_t indirect_offset
;
3707 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3708 const struct radv_dispatch_info
*info
)
3710 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3711 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3712 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3713 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3714 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3715 struct radv_userdata_info
*loc
;
3717 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3718 AC_UD_CS_GRID_SIZE
);
3720 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3722 if (info
->indirect
) {
3723 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3725 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3727 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3729 if (loc
->sgpr_idx
!= -1) {
3730 for (unsigned i
= 0; i
< 3; ++i
) {
3731 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3732 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3733 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3734 radeon_emit(cs
, (va
+ 4 * i
));
3735 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3736 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3737 + loc
->sgpr_idx
* 4) >> 2) + i
);
3742 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3743 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3744 PKT3_SHADER_TYPE_S(1));
3745 radeon_emit(cs
, va
);
3746 radeon_emit(cs
, va
>> 32);
3747 radeon_emit(cs
, dispatch_initiator
);
3749 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3750 PKT3_SHADER_TYPE_S(1));
3752 radeon_emit(cs
, va
);
3753 radeon_emit(cs
, va
>> 32);
3755 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3756 PKT3_SHADER_TYPE_S(1));
3758 radeon_emit(cs
, dispatch_initiator
);
3761 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3762 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
3764 if (info
->unaligned
) {
3765 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3766 unsigned remainder
[3];
3768 /* If aligned, these should be an entire block size,
3771 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3772 align_u32_npot(blocks
[0], cs_block_size
[0]);
3773 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3774 align_u32_npot(blocks
[1], cs_block_size
[1]);
3775 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3776 align_u32_npot(blocks
[2], cs_block_size
[2]);
3778 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3779 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3780 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3782 for(unsigned i
= 0; i
< 3; ++i
) {
3783 assert(offsets
[i
] % cs_block_size
[i
] == 0);
3784 offsets
[i
] /= cs_block_size
[i
];
3787 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3789 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3790 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3792 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3793 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3795 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3796 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3798 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3801 if (loc
->sgpr_idx
!= -1) {
3802 assert(!loc
->indirect
);
3803 assert(loc
->num_sgprs
== 3);
3805 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3806 loc
->sgpr_idx
* 4, 3);
3807 radeon_emit(cs
, blocks
[0]);
3808 radeon_emit(cs
, blocks
[1]);
3809 radeon_emit(cs
, blocks
[2]);
3812 if (offsets
[0] || offsets
[1] || offsets
[2]) {
3813 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
3814 radeon_emit(cs
, offsets
[0]);
3815 radeon_emit(cs
, offsets
[1]);
3816 radeon_emit(cs
, offsets
[2]);
3818 /* The blocks in the packet are not counts but end values. */
3819 for (unsigned i
= 0; i
< 3; ++i
)
3820 blocks
[i
] += offsets
[i
];
3822 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
3825 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3826 PKT3_SHADER_TYPE_S(1));
3827 radeon_emit(cs
, blocks
[0]);
3828 radeon_emit(cs
, blocks
[1]);
3829 radeon_emit(cs
, blocks
[2]);
3830 radeon_emit(cs
, dispatch_initiator
);
3833 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3837 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
3839 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3840 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3844 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3845 const struct radv_dispatch_info
*info
)
3847 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3849 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3850 bool pipeline_is_dirty
= pipeline
&&
3851 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
3853 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3854 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3855 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3856 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3857 /* If we have to wait for idle, set all states first, so that
3858 * all SET packets are processed in parallel with previous draw
3859 * calls. Then upload descriptors, set shader pointers, and
3860 * dispatch, and prefetch at the end. This ensures that the
3861 * time the CUs are idle is very short. (there are only SET_SH
3862 * packets between the wait and the draw)
3864 radv_emit_compute_pipeline(cmd_buffer
);
3865 si_emit_cache_flush(cmd_buffer
);
3866 /* <-- CUs are idle here --> */
3868 radv_upload_compute_shader_descriptors(cmd_buffer
);
3870 radv_emit_dispatch_packets(cmd_buffer
, info
);
3871 /* <-- CUs are busy here --> */
3873 /* Start prefetches after the dispatch has been started. Both
3874 * will run in parallel, but starting the dispatch first is
3877 if (has_prefetch
&& pipeline_is_dirty
) {
3878 radv_emit_shader_prefetch(cmd_buffer
,
3879 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3882 /* If we don't wait for idle, start prefetches first, then set
3883 * states, and dispatch at the end.
3885 si_emit_cache_flush(cmd_buffer
);
3887 if (has_prefetch
&& pipeline_is_dirty
) {
3888 radv_emit_shader_prefetch(cmd_buffer
,
3889 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3892 radv_upload_compute_shader_descriptors(cmd_buffer
);
3894 radv_emit_compute_pipeline(cmd_buffer
);
3895 radv_emit_dispatch_packets(cmd_buffer
, info
);
3898 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
3901 void radv_CmdDispatchBase(
3902 VkCommandBuffer commandBuffer
,
3910 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3911 struct radv_dispatch_info info
= {};
3917 info
.offsets
[0] = base_x
;
3918 info
.offsets
[1] = base_y
;
3919 info
.offsets
[2] = base_z
;
3920 radv_dispatch(cmd_buffer
, &info
);
3923 void radv_CmdDispatch(
3924 VkCommandBuffer commandBuffer
,
3929 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3932 void radv_CmdDispatchIndirect(
3933 VkCommandBuffer commandBuffer
,
3935 VkDeviceSize offset
)
3937 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3938 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3939 struct radv_dispatch_info info
= {};
3941 info
.indirect
= buffer
;
3942 info
.indirect_offset
= offset
;
3944 radv_dispatch(cmd_buffer
, &info
);
3947 void radv_unaligned_dispatch(
3948 struct radv_cmd_buffer
*cmd_buffer
,
3953 struct radv_dispatch_info info
= {};
3960 radv_dispatch(cmd_buffer
, &info
);
3963 void radv_CmdEndRenderPass(
3964 VkCommandBuffer commandBuffer
)
3966 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3968 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3970 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3972 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3973 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3974 radv_handle_subpass_image_transition(cmd_buffer
,
3975 (struct radv_subpass_attachment
){i
, layout
});
3978 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3980 cmd_buffer
->state
.pass
= NULL
;
3981 cmd_buffer
->state
.subpass
= NULL
;
3982 cmd_buffer
->state
.attachments
= NULL
;
3983 cmd_buffer
->state
.framebuffer
= NULL
;
3986 void radv_CmdEndRenderPass2KHR(
3987 VkCommandBuffer commandBuffer
,
3988 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3990 radv_CmdEndRenderPass(commandBuffer
);
3994 * For HTILE we have the following interesting clear words:
3995 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3996 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3997 * 0xfffffff0: Clear depth to 1.0
3998 * 0x00000000: Clear depth to 0.0
4000 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4001 struct radv_image
*image
,
4002 const VkImageSubresourceRange
*range
,
4003 uint32_t clear_word
)
4005 assert(range
->baseMipLevel
== 0);
4006 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4007 unsigned layer_count
= radv_get_layerCount(image
, range
);
4008 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
4009 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4010 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4011 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4012 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4013 VkClearDepthStencilValue value
= {};
4015 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4016 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4018 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4021 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4023 if (vk_format_is_stencil(image
->vk_format
))
4024 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4026 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4029 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4030 struct radv_image
*image
,
4031 VkImageLayout src_layout
,
4032 VkImageLayout dst_layout
,
4033 unsigned src_queue_mask
,
4034 unsigned dst_queue_mask
,
4035 const VkImageSubresourceRange
*range
,
4036 VkImageAspectFlags pending_clears
)
4038 if (!radv_image_has_htile(image
))
4041 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4042 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4043 /* TODO: merge with the clear if applicable */
4044 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4045 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4046 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4047 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4048 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4049 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4050 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4051 VkImageSubresourceRange local_range
= *range
;
4052 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4053 local_range
.baseMipLevel
= 0;
4054 local_range
.levelCount
= 1;
4056 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4057 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4059 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4061 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4062 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4066 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4067 struct radv_image
*image
, uint32_t value
)
4069 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4071 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4072 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4074 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4076 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4079 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4080 struct radv_image
*image
, uint32_t value
)
4082 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4084 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4085 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4087 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4089 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4090 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4094 * Initialize DCC/FMASK/CMASK metadata for a color image.
4096 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4097 struct radv_image
*image
,
4098 VkImageLayout src_layout
,
4099 VkImageLayout dst_layout
,
4100 unsigned src_queue_mask
,
4101 unsigned dst_queue_mask
)
4103 if (radv_image_has_cmask(image
)) {
4104 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4106 /* TODO: clarify this. */
4107 if (radv_image_has_fmask(image
)) {
4108 value
= 0xccccccccu
;
4111 radv_initialise_cmask(cmd_buffer
, image
, value
);
4114 if (radv_image_has_dcc(image
)) {
4115 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4117 if (radv_layout_dcc_compressed(image
, dst_layout
,
4119 value
= 0x20202020u
;
4122 radv_initialize_dcc(cmd_buffer
, image
, value
);
4124 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, image
, false);
4127 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4128 uint32_t color_values
[2] = {};
4129 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4134 * Handle color image transitions for DCC/FMASK/CMASK.
4136 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4137 struct radv_image
*image
,
4138 VkImageLayout src_layout
,
4139 VkImageLayout dst_layout
,
4140 unsigned src_queue_mask
,
4141 unsigned dst_queue_mask
,
4142 const VkImageSubresourceRange
*range
)
4144 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4145 radv_init_color_image_metadata(cmd_buffer
, image
,
4146 src_layout
, dst_layout
,
4147 src_queue_mask
, dst_queue_mask
);
4151 if (radv_image_has_dcc(image
)) {
4152 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4153 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4154 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4155 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4156 radv_decompress_dcc(cmd_buffer
, image
, range
);
4157 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4158 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4159 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4161 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4162 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4163 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4164 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4169 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4170 struct radv_image
*image
,
4171 VkImageLayout src_layout
,
4172 VkImageLayout dst_layout
,
4173 uint32_t src_family
,
4174 uint32_t dst_family
,
4175 const VkImageSubresourceRange
*range
,
4176 VkImageAspectFlags pending_clears
)
4178 if (image
->exclusive
&& src_family
!= dst_family
) {
4179 /* This is an acquire or a release operation and there will be
4180 * a corresponding release/acquire. Do the transition in the
4181 * most flexible queue. */
4183 assert(src_family
== cmd_buffer
->queue_family_index
||
4184 dst_family
== cmd_buffer
->queue_family_index
);
4186 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4189 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4190 (src_family
== RADV_QUEUE_GENERAL
||
4191 dst_family
== RADV_QUEUE_GENERAL
))
4195 unsigned src_queue_mask
=
4196 radv_image_queue_family_mask(image
, src_family
,
4197 cmd_buffer
->queue_family_index
);
4198 unsigned dst_queue_mask
=
4199 radv_image_queue_family_mask(image
, dst_family
,
4200 cmd_buffer
->queue_family_index
);
4202 if (vk_format_is_depth(image
->vk_format
)) {
4203 radv_handle_depth_image_transition(cmd_buffer
, image
,
4204 src_layout
, dst_layout
,
4205 src_queue_mask
, dst_queue_mask
,
4206 range
, pending_clears
);
4208 radv_handle_color_image_transition(cmd_buffer
, image
,
4209 src_layout
, dst_layout
,
4210 src_queue_mask
, dst_queue_mask
,
4215 struct radv_barrier_info
{
4216 uint32_t eventCount
;
4217 const VkEvent
*pEvents
;
4218 VkPipelineStageFlags srcStageMask
;
4222 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4223 uint32_t memoryBarrierCount
,
4224 const VkMemoryBarrier
*pMemoryBarriers
,
4225 uint32_t bufferMemoryBarrierCount
,
4226 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4227 uint32_t imageMemoryBarrierCount
,
4228 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4229 const struct radv_barrier_info
*info
)
4231 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4232 enum radv_cmd_flush_bits src_flush_bits
= 0;
4233 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4235 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4236 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4237 uint64_t va
= radv_buffer_get_va(event
->bo
);
4239 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
4241 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4243 si_emit_wait_fence(cs
, va
, 1, 0xffffffff);
4244 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4247 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4248 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4250 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4254 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4255 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4257 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4261 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4262 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4264 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4266 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4270 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4271 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4273 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4274 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4275 radv_handle_image_transition(cmd_buffer
, image
,
4276 pImageMemoryBarriers
[i
].oldLayout
,
4277 pImageMemoryBarriers
[i
].newLayout
,
4278 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4279 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4280 &pImageMemoryBarriers
[i
].subresourceRange
,
4284 /* Make sure CP DMA is idle because the driver might have performed a
4285 * DMA operation for copying or filling buffers/images.
4287 si_cp_dma_wait_for_idle(cmd_buffer
);
4289 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4292 void radv_CmdPipelineBarrier(
4293 VkCommandBuffer commandBuffer
,
4294 VkPipelineStageFlags srcStageMask
,
4295 VkPipelineStageFlags destStageMask
,
4297 uint32_t memoryBarrierCount
,
4298 const VkMemoryBarrier
* pMemoryBarriers
,
4299 uint32_t bufferMemoryBarrierCount
,
4300 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4301 uint32_t imageMemoryBarrierCount
,
4302 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4304 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4305 struct radv_barrier_info info
;
4307 info
.eventCount
= 0;
4308 info
.pEvents
= NULL
;
4309 info
.srcStageMask
= srcStageMask
;
4311 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4312 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4313 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4317 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4318 struct radv_event
*event
,
4319 VkPipelineStageFlags stageMask
,
4322 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4323 uint64_t va
= radv_buffer_get_va(event
->bo
);
4325 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
4327 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4329 /* Flags that only require a top-of-pipe event. */
4330 VkPipelineStageFlags top_of_pipe_flags
=
4331 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4333 /* Flags that only require a post-index-fetch event. */
4334 VkPipelineStageFlags post_index_fetch_flags
=
4336 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4337 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4339 /* Make sure CP DMA is idle because the driver might have performed a
4340 * DMA operation for copying or filling buffers/images.
4342 si_cp_dma_wait_for_idle(cmd_buffer
);
4344 /* TODO: Emit EOS events for syncing PS/CS stages. */
4346 if (!(stageMask
& ~top_of_pipe_flags
)) {
4347 /* Just need to sync the PFP engine. */
4348 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4349 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4350 S_370_WR_CONFIRM(1) |
4351 S_370_ENGINE_SEL(V_370_PFP
));
4352 radeon_emit(cs
, va
);
4353 radeon_emit(cs
, va
>> 32);
4354 radeon_emit(cs
, value
);
4355 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4356 /* Sync ME because PFP reads index and indirect buffers. */
4357 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4358 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4359 S_370_WR_CONFIRM(1) |
4360 S_370_ENGINE_SEL(V_370_ME
));
4361 radeon_emit(cs
, va
);
4362 radeon_emit(cs
, va
>> 32);
4363 radeon_emit(cs
, value
);
4365 /* Otherwise, sync all prior GPU work using an EOP event. */
4366 si_cs_emit_write_event_eop(cs
,
4367 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4368 radv_cmd_buffer_uses_mec(cmd_buffer
),
4369 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4370 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4371 cmd_buffer
->gfx9_eop_bug_va
);
4374 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4377 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4379 VkPipelineStageFlags stageMask
)
4381 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4382 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4384 write_event(cmd_buffer
, event
, stageMask
, 1);
4387 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4389 VkPipelineStageFlags stageMask
)
4391 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4392 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4394 write_event(cmd_buffer
, event
, stageMask
, 0);
4397 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4398 uint32_t eventCount
,
4399 const VkEvent
* pEvents
,
4400 VkPipelineStageFlags srcStageMask
,
4401 VkPipelineStageFlags dstStageMask
,
4402 uint32_t memoryBarrierCount
,
4403 const VkMemoryBarrier
* pMemoryBarriers
,
4404 uint32_t bufferMemoryBarrierCount
,
4405 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4406 uint32_t imageMemoryBarrierCount
,
4407 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4409 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4410 struct radv_barrier_info info
;
4412 info
.eventCount
= eventCount
;
4413 info
.pEvents
= pEvents
;
4414 info
.srcStageMask
= 0;
4416 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4417 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4418 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4422 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4423 uint32_t deviceMask
)