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radv: add assertions to make sure pipeline layout objects are valid
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
597 return;
598
599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
600 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
602
603 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
604
605 /* GFX9: Flush DFSM when the AA mode changes. */
606 if (cmd_buffer->device->dfsm_allowed) {
607 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
608 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
609 }
610 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
611 uint32_t offset;
612 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
613 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
614 if (loc->sgpr_idx == -1)
615 return;
616 assert(loc->num_sgprs == 1);
617 assert(!loc->indirect);
618 switch (num_samples) {
619 default:
620 offset = 0;
621 break;
622 case 2:
623 offset = 1;
624 break;
625 case 4:
626 offset = 3;
627 break;
628 case 8:
629 offset = 7;
630 break;
631 case 16:
632 offset = 15;
633 break;
634 }
635
636 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
637 cmd_buffer->sample_positions_needed = true;
638 }
639 }
640
641 static void
642 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline)
644 {
645 struct radv_raster_state *raster = &pipeline->graphics.raster;
646
647 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
648 raster->pa_cl_clip_cntl);
649 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
650 raster->spi_interp_control);
651 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
652 raster->pa_su_vtx_cntl);
653 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
654 raster->pa_su_sc_mode_cntl);
655 }
656
657 static inline void
658 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
659 unsigned size)
660 {
661 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
662 si_cp_dma_prefetch(cmd_buffer, va, size);
663 }
664
665 static void
666 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
667 {
668 if (cmd_buffer->state.vb_prefetch_dirty) {
669 radv_emit_prefetch_TC_L2_async(cmd_buffer,
670 cmd_buffer->state.vb_va,
671 cmd_buffer->state.vb_size);
672 cmd_buffer->state.vb_prefetch_dirty = false;
673 }
674 }
675
676 static void
677 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_shader_variant *shader)
679 {
680 struct radeon_winsys *ws = cmd_buffer->device->ws;
681 struct radeon_winsys_cs *cs = cmd_buffer->cs;
682 uint64_t va;
683
684 if (!shader)
685 return;
686
687 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
688
689 radv_cs_add_buffer(ws, cs, shader->bo, 8);
690 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
691 }
692
693 static void
694 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
695 struct radv_pipeline *pipeline)
696 {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_VERTEX]);
699 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
704 radv_emit_shader_prefetch(cmd_buffer,
705 pipeline->shaders[MESA_SHADER_GEOMETRY]);
706 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709 }
710
711 static void
712 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline,
714 struct radv_shader_variant *shader)
715 {
716 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
717
718 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
719 pipeline->graphics.vs.spi_vs_out_config);
720
721 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
722 pipeline->graphics.vs.spi_shader_pos_format);
723
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
725 radeon_emit(cmd_buffer->cs, va >> 8);
726 radeon_emit(cmd_buffer->cs, va >> 40);
727 radeon_emit(cmd_buffer->cs, shader->rsrc1);
728 radeon_emit(cmd_buffer->cs, shader->rsrc2);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
731 S_028818_VTX_W0_FMT(1) |
732 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
733 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
734 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
735
736
737 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
738 pipeline->graphics.vs.pa_cl_vs_out_cntl);
739
740 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
741 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
742 pipeline->graphics.vs.vgt_reuse_off);
743 }
744
745 static void
746 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
747 struct radv_pipeline *pipeline,
748 struct radv_shader_variant *shader)
749 {
750 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
751
752 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
753 radeon_emit(cmd_buffer->cs, va >> 8);
754 radeon_emit(cmd_buffer->cs, va >> 40);
755 radeon_emit(cmd_buffer->cs, shader->rsrc1);
756 radeon_emit(cmd_buffer->cs, shader->rsrc2);
757 }
758
759 static void
760 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_shader_variant *shader)
762 {
763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
764 uint32_t rsrc2 = shader->rsrc2;
765
766 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
767 radeon_emit(cmd_buffer->cs, va >> 8);
768 radeon_emit(cmd_buffer->cs, va >> 40);
769
770 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
771 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
772 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
773 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
774
775 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
776 radeon_emit(cmd_buffer->cs, shader->rsrc1);
777 radeon_emit(cmd_buffer->cs, rsrc2);
778 }
779
780 static void
781 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
782 struct radv_shader_variant *shader)
783 {
784 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
785
786 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
787 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
788 radeon_emit(cmd_buffer->cs, va >> 8);
789 radeon_emit(cmd_buffer->cs, va >> 40);
790
791 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
792 radeon_emit(cmd_buffer->cs, shader->rsrc1);
793 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
794 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
795 } else {
796 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
797 radeon_emit(cmd_buffer->cs, va >> 8);
798 radeon_emit(cmd_buffer->cs, va >> 40);
799 radeon_emit(cmd_buffer->cs, shader->rsrc1);
800 radeon_emit(cmd_buffer->cs, shader->rsrc2);
801 }
802 }
803
804 static void
805 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
806 struct radv_pipeline *pipeline)
807 {
808 struct radv_shader_variant *vs;
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
811
812 /* Skip shaders merged into HS/GS */
813 vs = pipeline->shaders[MESA_SHADER_VERTEX];
814 if (!vs)
815 return;
816
817 if (vs->info.vs.as_ls)
818 radv_emit_hw_ls(cmd_buffer, vs);
819 else if (vs->info.vs.as_es)
820 radv_emit_hw_es(cmd_buffer, pipeline, vs);
821 else
822 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
823 }
824
825
826 static void
827 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
828 struct radv_pipeline *pipeline)
829 {
830 if (!radv_pipeline_has_tess(pipeline))
831 return;
832
833 struct radv_shader_variant *tes, *tcs;
834
835 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
836 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
837
838 if (tes) {
839 if (tes->info.tes.as_es)
840 radv_emit_hw_es(cmd_buffer, pipeline, tes);
841 else
842 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
843 }
844
845 radv_emit_hw_hs(cmd_buffer, tcs);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
848 pipeline->graphics.tess.tf_param);
849
850 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
851 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
852 pipeline->graphics.tess.ls_hs_config);
853 else
854 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
855 pipeline->graphics.tess.ls_hs_config);
856
857 struct ac_userdata_info *loc;
858
859 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
860 if (loc->sgpr_idx != -1) {
861 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
862 assert(loc->num_sgprs == 4);
863 assert(!loc->indirect);
864 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
868 pipeline->graphics.tess.num_tcs_input_cp << 26);
869 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
870 }
871
872 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
873 if (loc->sgpr_idx != -1) {
874 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
875 assert(loc->num_sgprs == 1);
876 assert(!loc->indirect);
877
878 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
879 pipeline->graphics.tess.offchip_layout);
880 }
881
882 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
883 if (loc->sgpr_idx != -1) {
884 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
885 assert(loc->num_sgprs == 1);
886 assert(!loc->indirect);
887
888 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
889 pipeline->graphics.tess.tcs_in_layout);
890 }
891 }
892
893 static void
894 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
895 struct radv_pipeline *pipeline)
896 {
897 struct radv_shader_variant *gs;
898 uint64_t va;
899
900 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
901
902 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
903 if (!gs)
904 return;
905
906 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
907
908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
916
917 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
918 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
919 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
920 radeon_emit(cmd_buffer->cs, 0);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923
924 uint32_t gs_num_invocations = gs->info.gs.invocations;
925 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
926 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
927 S_028B90_ENABLE(gs_num_invocations > 0));
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
930 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
931
932 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
933
934 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
935 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
936 radeon_emit(cmd_buffer->cs, va >> 8);
937 radeon_emit(cmd_buffer->cs, va >> 40);
938
939 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
940 radeon_emit(cmd_buffer->cs, gs->rsrc1);
941 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
942 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
943
944 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
945 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
946 } else {
947 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
948 radeon_emit(cmd_buffer->cs, va >> 8);
949 radeon_emit(cmd_buffer->cs, va >> 40);
950 radeon_emit(cmd_buffer->cs, gs->rsrc1);
951 radeon_emit(cmd_buffer->cs, gs->rsrc2);
952 }
953
954 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
955
956 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
957 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
958 if (loc->sgpr_idx != -1) {
959 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
960 uint32_t num_entries = 64;
961 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
962
963 if (is_vi)
964 num_entries *= stride;
965
966 stride = S_008F04_STRIDE(stride);
967 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
968 radeon_emit(cmd_buffer->cs, stride);
969 radeon_emit(cmd_buffer->cs, num_entries);
970 }
971 }
972
973 static void
974 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_pipeline *pipeline)
976 {
977 struct radv_shader_variant *ps;
978 uint64_t va;
979 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
980 struct radv_blend_state *blend = &pipeline->graphics.blend;
981 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
984 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
985
986 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
987 radeon_emit(cmd_buffer->cs, va >> 8);
988 radeon_emit(cmd_buffer->cs, va >> 40);
989 radeon_emit(cmd_buffer->cs, ps->rsrc1);
990 radeon_emit(cmd_buffer->cs, ps->rsrc2);
991
992 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
993 pipeline->graphics.db_shader_control);
994
995 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
996 ps->config.spi_ps_input_ena);
997
998 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
999 ps->config.spi_ps_input_addr);
1000
1001 if (ps->info.info.ps.force_persample)
1002 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1005 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1008
1009 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1010 pipeline->graphics.shader_z_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1013
1014 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1015 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1016
1017 if (cmd_buffer->device->dfsm_allowed) {
1018 /* optimise this? */
1019 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1020 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1021 }
1022
1023 if (pipeline->graphics.ps_input_cntl_num) {
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1025 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1026 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1027 }
1028 }
1029 }
1030
1031 static void
1032 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_pipeline *pipeline)
1034 {
1035 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1036
1037 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1038 return;
1039
1040 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1041 pipeline->graphics.vtx_reuse_depth);
1042 }
1043
1044 static void
1045 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1046 {
1047 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1048
1049 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1050 return;
1051
1052 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1053 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1054 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1055 radv_update_multisample_state(cmd_buffer, pipeline);
1056 radv_emit_vertex_shader(cmd_buffer, pipeline);
1057 radv_emit_tess_shaders(cmd_buffer, pipeline);
1058 radv_emit_geometry_shader(cmd_buffer, pipeline);
1059 radv_emit_fragment_shader(cmd_buffer, pipeline);
1060 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1061
1062 cmd_buffer->scratch_size_needed =
1063 MAX2(cmd_buffer->scratch_size_needed,
1064 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1065
1066 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1067 S_0286E8_WAVES(pipeline->max_waves) |
1068 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1069
1070 if (!cmd_buffer->state.emitted_pipeline ||
1071 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1072 pipeline->graphics.can_use_guardband)
1073 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1074
1075 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1076
1077 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1078 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1079 } else {
1080 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1081 }
1082 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1083
1084 if (unlikely(cmd_buffer->device->trace_bo))
1085 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1086
1087 cmd_buffer->state.emitted_pipeline = pipeline;
1088
1089 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1090 }
1091
1092 static void
1093 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1094 {
1095 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1096 cmd_buffer->state.dynamic.viewport.viewports);
1097 }
1098
1099 static void
1100 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1101 {
1102 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1103
1104 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1105 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1106 si_emit_cache_flush(cmd_buffer);
1107 }
1108 si_write_scissors(cmd_buffer->cs, 0, count,
1109 cmd_buffer->state.dynamic.scissor.scissors,
1110 cmd_buffer->state.dynamic.viewport.viewports,
1111 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1112 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1113 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1114 }
1115
1116 static void
1117 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1120
1121 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1122 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1123 }
1124
1125 static void
1126 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1127 {
1128 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1129
1130 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1131 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1132 }
1133
1134 static void
1135 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1136 {
1137 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs,
1140 R_028430_DB_STENCILREFMASK, 2);
1141 radeon_emit(cmd_buffer->cs,
1142 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1143 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1144 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1145 S_028430_STENCILOPVAL(1));
1146 radeon_emit(cmd_buffer->cs,
1147 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1148 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1149 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1150 S_028434_STENCILOPVAL_BF(1));
1151 }
1152
1153 static void
1154 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1155 {
1156 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1157
1158 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1159 fui(d->depth_bounds.min));
1160 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1161 fui(d->depth_bounds.max));
1162 }
1163
1164 static void
1165 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1166 {
1167 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1168 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1169 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1170 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1171
1172 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1173 radeon_set_context_reg_seq(cmd_buffer->cs,
1174 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1175 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1176 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1178 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1179 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1180 }
1181 }
1182
1183 static void
1184 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1185 int index,
1186 struct radv_attachment_info *att)
1187 {
1188 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1189 struct radv_color_buffer_info *cb = &att->cb;
1190
1191 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1192 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1196 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1199 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1204
1205 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1206 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1207 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1208
1209 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1210 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1211 } else {
1212 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1216 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1219 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1223 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1224
1225 if (is_vi) { /* DCC BASE */
1226 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1227 }
1228 }
1229 }
1230
1231 static void
1232 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1233 struct radv_ds_buffer_info *ds,
1234 struct radv_image *image,
1235 VkImageLayout layout)
1236 {
1237 uint32_t db_z_info = ds->db_z_info;
1238 uint32_t db_stencil_info = ds->db_stencil_info;
1239
1240 if (!radv_layout_has_htile(image, layout,
1241 radv_image_queue_family_mask(image,
1242 cmd_buffer->queue_family_index,
1243 cmd_buffer->queue_family_index))) {
1244 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1245 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1246 }
1247
1248 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1249 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1250
1251
1252 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1254 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1255 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1256 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1257
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1259 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1260 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1261 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1263 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1265 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1267 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1269
1270 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1271 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1272 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1273 } else {
1274 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1275
1276 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1277 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1278 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1279 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1280 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1282 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1283 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1284 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1285 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1286
1287 }
1288
1289 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1290 ds->pa_su_poly_offset_db_fmt_cntl);
1291 }
1292
1293 void
1294 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 VkClearDepthStencilValue ds_clear_value,
1297 VkImageAspectFlags aspects)
1298 {
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->clear_value_offset;
1301 unsigned reg_offset = 0, reg_count = 0;
1302
1303 assert(image->surface.htile_size);
1304
1305 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1306 ++reg_count;
1307 } else {
1308 ++reg_offset;
1309 va += 4;
1310 }
1311 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1312 ++reg_count;
1313
1314 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1315 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP));
1318 radeon_emit(cmd_buffer->cs, va);
1319 radeon_emit(cmd_buffer->cs, va >> 32);
1320 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1321 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1322 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1323 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1324
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1326 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1327 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1328 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1329 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1330 }
1331
1332 static void
1333 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1334 struct radv_image *image)
1335 {
1336 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1337 uint64_t va = radv_buffer_get_va(image->bo);
1338 va += image->offset + image->clear_value_offset;
1339 unsigned reg_offset = 0, reg_count = 0;
1340
1341 if (!image->surface.htile_size)
1342 return;
1343
1344 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1345 ++reg_count;
1346 } else {
1347 ++reg_offset;
1348 va += 4;
1349 }
1350 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1351 ++reg_count;
1352
1353 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1354 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1355 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1356 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1357 radeon_emit(cmd_buffer->cs, va);
1358 radeon_emit(cmd_buffer->cs, va >> 32);
1359 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1360 radeon_emit(cmd_buffer->cs, 0);
1361
1362 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1363 radeon_emit(cmd_buffer->cs, 0);
1364 }
1365
1366 /*
1367 *with DCC some colors don't require CMASK elimiation before being
1368 * used as a texture. This sets a predicate value to determine if the
1369 * cmask eliminate is required.
1370 */
1371 void
1372 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1373 struct radv_image *image,
1374 bool value)
1375 {
1376 uint64_t pred_val = value;
1377 uint64_t va = radv_buffer_get_va(image->bo);
1378 va += image->offset + image->dcc_pred_offset;
1379
1380 assert(image->surface.dcc_size);
1381
1382 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1383 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1384 S_370_WR_CONFIRM(1) |
1385 S_370_ENGINE_SEL(V_370_PFP));
1386 radeon_emit(cmd_buffer->cs, va);
1387 radeon_emit(cmd_buffer->cs, va >> 32);
1388 radeon_emit(cmd_buffer->cs, pred_val);
1389 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1390 }
1391
1392 void
1393 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int idx,
1396 uint32_t color_values[2])
1397 {
1398 uint64_t va = radv_buffer_get_va(image->bo);
1399 va += image->offset + image->clear_value_offset;
1400
1401 assert(image->cmask.size || image->surface.dcc_size);
1402
1403 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1404 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1405 S_370_WR_CONFIRM(1) |
1406 S_370_ENGINE_SEL(V_370_PFP));
1407 radeon_emit(cmd_buffer->cs, va);
1408 radeon_emit(cmd_buffer->cs, va >> 32);
1409 radeon_emit(cmd_buffer->cs, color_values[0]);
1410 radeon_emit(cmd_buffer->cs, color_values[1]);
1411
1412 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1413 radeon_emit(cmd_buffer->cs, color_values[0]);
1414 radeon_emit(cmd_buffer->cs, color_values[1]);
1415 }
1416
1417 static void
1418 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1419 struct radv_image *image,
1420 int idx)
1421 {
1422 uint64_t va = radv_buffer_get_va(image->bo);
1423 va += image->offset + image->clear_value_offset;
1424
1425 if (!image->cmask.size && !image->surface.dcc_size)
1426 return;
1427
1428 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1431 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1432 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1433 COPY_DATA_COUNT_SEL);
1434 radeon_emit(cmd_buffer->cs, va);
1435 radeon_emit(cmd_buffer->cs, va >> 32);
1436 radeon_emit(cmd_buffer->cs, reg >> 2);
1437 radeon_emit(cmd_buffer->cs, 0);
1438
1439 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1440 radeon_emit(cmd_buffer->cs, 0);
1441 }
1442
1443 static void
1444 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1445 {
1446 int i;
1447 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1448 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1449
1450 /* this may happen for inherited secondary recording */
1451 if (!framebuffer)
1452 return;
1453
1454 for (i = 0; i < 8; ++i) {
1455 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1456 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1457 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1458 continue;
1459 }
1460
1461 int idx = subpass->color_attachments[i].attachment;
1462 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1463
1464 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1465
1466 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1467 radv_emit_fb_color_state(cmd_buffer, i, att);
1468
1469 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1470 }
1471
1472 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1473 int idx = subpass->depth_stencil_attachment.attachment;
1474 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1475 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1476 struct radv_image *image = att->attachment->image;
1477 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1478 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1479 cmd_buffer->queue_family_index,
1480 cmd_buffer->queue_family_index);
1481 /* We currently don't support writing decompressed HTILE */
1482 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1483 radv_layout_is_htile_compressed(image, layout, queue_mask));
1484
1485 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1486
1487 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1488 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1489 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1490 }
1491 radv_load_depth_clear_regs(cmd_buffer, image);
1492 } else {
1493 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1494 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1495 else
1496 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1497
1498 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1499 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1500 }
1501 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1502 S_028208_BR_X(framebuffer->width) |
1503 S_028208_BR_Y(framebuffer->height));
1504
1505 if (cmd_buffer->device->dfsm_allowed) {
1506 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1507 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1508 }
1509
1510 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1511 }
1512
1513 static void
1514 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1515 {
1516 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1517 struct radv_cmd_state *state = &cmd_buffer->state;
1518
1519 if (state->index_type != state->last_index_type) {
1520 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1521 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1522 2, state->index_type);
1523 } else {
1524 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1525 radeon_emit(cs, state->index_type);
1526 }
1527
1528 state->last_index_type = state->index_type;
1529 }
1530
1531 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1532 radeon_emit(cs, state->index_va);
1533 radeon_emit(cs, state->index_va >> 32);
1534
1535 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1536 radeon_emit(cs, state->max_index_count);
1537
1538 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1539 }
1540
1541 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1542 {
1543 uint32_t db_count_control;
1544
1545 if(!cmd_buffer->state.active_occlusion_queries) {
1546 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1547 db_count_control = 0;
1548 } else {
1549 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1550 }
1551 } else {
1552 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1553 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1554 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1555 S_028004_ZPASS_ENABLE(1) |
1556 S_028004_SLICE_EVEN_ENABLE(1) |
1557 S_028004_SLICE_ODD_ENABLE(1);
1558 } else {
1559 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1560 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1561 }
1562 }
1563
1564 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1565 }
1566
1567 static void
1568 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1569 {
1570 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1571 return;
1572
1573 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1574 radv_emit_viewport(cmd_buffer);
1575
1576 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1577 radv_emit_scissor(cmd_buffer);
1578
1579 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1580 radv_emit_line_width(cmd_buffer);
1581
1582 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1583 radv_emit_blend_constants(cmd_buffer);
1584
1585 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1586 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1587 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1588 radv_emit_stencil(cmd_buffer);
1589
1590 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1591 radv_emit_depth_bounds(cmd_buffer);
1592
1593 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1594 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1595 radv_emit_depth_biais(cmd_buffer);
1596
1597 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1598 }
1599
1600 static void
1601 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1602 struct radv_pipeline *pipeline,
1603 int idx,
1604 uint64_t va,
1605 gl_shader_stage stage)
1606 {
1607 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1608 uint32_t base_reg = pipeline->user_data_0[stage];
1609
1610 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1611 return;
1612
1613 assert(!desc_set_loc->indirect);
1614 assert(desc_set_loc->num_sgprs == 2);
1615 radeon_set_sh_reg_seq(cmd_buffer->cs,
1616 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1617 radeon_emit(cmd_buffer->cs, va);
1618 radeon_emit(cmd_buffer->cs, va >> 32);
1619 }
1620
1621 static void
1622 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1623 VkShaderStageFlags stages,
1624 struct radv_descriptor_set *set,
1625 unsigned idx)
1626 {
1627 if (cmd_buffer->state.pipeline) {
1628 radv_foreach_stage(stage, stages) {
1629 if (cmd_buffer->state.pipeline->shaders[stage])
1630 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1631 idx, set->va,
1632 stage);
1633 }
1634 }
1635
1636 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1637 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1638 idx, set->va,
1639 MESA_SHADER_COMPUTE);
1640 }
1641
1642 static void
1643 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1644 {
1645 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1646 unsigned bo_offset;
1647
1648 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1649 set->mapped_ptr,
1650 &bo_offset))
1651 return;
1652
1653 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1654 set->va += bo_offset;
1655 }
1656
1657 static void
1658 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1659 {
1660 uint32_t size = MAX_SETS * 2 * 4;
1661 uint32_t offset;
1662 void *ptr;
1663
1664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1665 256, &offset, &ptr))
1666 return;
1667
1668 for (unsigned i = 0; i < MAX_SETS; i++) {
1669 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1670 uint64_t set_va = 0;
1671 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1672 if (cmd_buffer->state.valid_descriptors & (1u << i))
1673 set_va = set->va;
1674 uptr[0] = set_va & 0xffffffff;
1675 uptr[1] = set_va >> 32;
1676 }
1677
1678 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1679 va += offset;
1680
1681 if (cmd_buffer->state.pipeline) {
1682 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685
1686 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1687 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1688 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1689
1690 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1691 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1693
1694 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1695 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1697
1698 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 if (cmd_buffer->state.compute_pipeline)
1704 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1705 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1706 }
1707
1708 static void
1709 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1710 VkShaderStageFlags stages)
1711 {
1712 unsigned i;
1713
1714 if (!cmd_buffer->state.descriptors_dirty)
1715 return;
1716
1717 if (cmd_buffer->state.push_descriptors_dirty)
1718 radv_flush_push_descriptors(cmd_buffer);
1719
1720 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1721 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1722 radv_flush_indirect_descriptor_sets(cmd_buffer);
1723 }
1724
1725 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1726 cmd_buffer->cs,
1727 MAX_SETS * MESA_SHADER_STAGES * 4);
1728
1729 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1730 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1731 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1732 continue;
1733
1734 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1735 }
1736 cmd_buffer->state.descriptors_dirty = 0;
1737 cmd_buffer->state.push_descriptors_dirty = false;
1738
1739 if (unlikely(cmd_buffer->device->trace_bo))
1740 radv_save_descriptors(cmd_buffer);
1741
1742 assert(cmd_buffer->cs->cdw <= cdw_max);
1743 }
1744
1745 static void
1746 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1747 struct radv_pipeline *pipeline,
1748 VkShaderStageFlags stages)
1749 {
1750 struct radv_pipeline_layout *layout = pipeline->layout;
1751 unsigned offset;
1752 void *ptr;
1753 uint64_t va;
1754
1755 stages &= cmd_buffer->push_constant_stages;
1756 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1757 return;
1758
1759 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1760 16 * layout->dynamic_offset_count,
1761 256, &offset, &ptr))
1762 return;
1763
1764 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1765 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1766 16 * layout->dynamic_offset_count);
1767
1768 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1769 va += offset;
1770
1771 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1772 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1773
1774 radv_foreach_stage(stage, stages) {
1775 if (pipeline->shaders[stage]) {
1776 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1777 AC_UD_PUSH_CONSTANTS, va);
1778 }
1779 }
1780
1781 cmd_buffer->push_constant_stages &= ~stages;
1782 assert(cmd_buffer->cs->cdw <= cdw_max);
1783 }
1784
1785 static bool
1786 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1787 {
1788 if ((pipeline_is_dirty ||
1789 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1790 cmd_buffer->state.pipeline->vertex_elements.count &&
1791 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1792 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1793 unsigned vb_offset;
1794 void *vb_ptr;
1795 uint32_t i = 0;
1796 uint32_t count = velems->count;
1797 uint64_t va;
1798
1799 /* allocate some descriptor state for vertex buffers */
1800 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1801 &vb_offset, &vb_ptr))
1802 return false;
1803
1804 for (i = 0; i < count; i++) {
1805 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1806 uint32_t offset;
1807 int vb = velems->binding[i];
1808 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1809 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1810
1811 va = radv_buffer_get_va(buffer->bo);
1812
1813 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1814 va += offset + buffer->offset;
1815 desc[0] = va;
1816 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1817 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1818 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1819 else
1820 desc[2] = buffer->size - offset;
1821 desc[3] = velems->rsrc_word3[i];
1822 }
1823
1824 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1825 va += vb_offset;
1826
1827 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1828 AC_UD_VS_VERTEX_BUFFERS, va);
1829
1830 cmd_buffer->state.vb_va = va;
1831 cmd_buffer->state.vb_size = count * 16;
1832 cmd_buffer->state.vb_prefetch_dirty = true;
1833 }
1834 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1835
1836 return true;
1837 }
1838
1839 static bool
1840 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1841 {
1842 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1843 return false;
1844
1845 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1846 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1847 VK_SHADER_STAGE_ALL_GRAPHICS);
1848
1849 return true;
1850 }
1851
1852 static void
1853 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1854 bool instanced_draw, bool indirect_draw,
1855 uint32_t draw_vertex_count)
1856 {
1857 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1858 struct radv_cmd_state *state = &cmd_buffer->state;
1859 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1860 uint32_t ia_multi_vgt_param;
1861 int32_t primitive_reset_en;
1862
1863 /* Draw state. */
1864 ia_multi_vgt_param =
1865 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1866 indirect_draw, draw_vertex_count);
1867
1868 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1869 if (info->chip_class >= GFX9) {
1870 radeon_set_uconfig_reg_idx(cs,
1871 R_030960_IA_MULTI_VGT_PARAM,
1872 4, ia_multi_vgt_param);
1873 } else if (info->chip_class >= CIK) {
1874 radeon_set_context_reg_idx(cs,
1875 R_028AA8_IA_MULTI_VGT_PARAM,
1876 1, ia_multi_vgt_param);
1877 } else {
1878 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1879 ia_multi_vgt_param);
1880 }
1881 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1882 }
1883
1884 /* Primitive restart. */
1885 primitive_reset_en =
1886 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1887
1888 if (primitive_reset_en != state->last_primitive_reset_en) {
1889 state->last_primitive_reset_en = primitive_reset_en;
1890 if (info->chip_class >= GFX9) {
1891 radeon_set_uconfig_reg(cs,
1892 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1893 primitive_reset_en);
1894 } else {
1895 radeon_set_context_reg(cs,
1896 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1897 primitive_reset_en);
1898 }
1899 }
1900
1901 if (primitive_reset_en) {
1902 uint32_t primitive_reset_index =
1903 state->index_type ? 0xffffffffu : 0xffffu;
1904
1905 if (primitive_reset_index != state->last_primitive_reset_index) {
1906 radeon_set_context_reg(cs,
1907 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1908 primitive_reset_index);
1909 state->last_primitive_reset_index = primitive_reset_index;
1910 }
1911 }
1912 }
1913
1914 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1915 VkPipelineStageFlags src_stage_mask)
1916 {
1917 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1918 VK_PIPELINE_STAGE_TRANSFER_BIT |
1919 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1920 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1921 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1922 }
1923
1924 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1925 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1926 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1927 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1928 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1929 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1930 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1931 VK_PIPELINE_STAGE_TRANSFER_BIT |
1932 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1933 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1934 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1936 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1937 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1938 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1939 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1940 }
1941 }
1942
1943 static enum radv_cmd_flush_bits
1944 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1945 VkAccessFlags src_flags)
1946 {
1947 enum radv_cmd_flush_bits flush_bits = 0;
1948 uint32_t b;
1949 for_each_bit(b, src_flags) {
1950 switch ((VkAccessFlagBits)(1 << b)) {
1951 case VK_ACCESS_SHADER_WRITE_BIT:
1952 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1953 break;
1954 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1955 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1957 break;
1958 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1959 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1960 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1961 break;
1962 case VK_ACCESS_TRANSFER_WRITE_BIT:
1963 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1964 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1965 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1967 RADV_CMD_FLAG_INV_GLOBAL_L2;
1968 break;
1969 default:
1970 break;
1971 }
1972 }
1973 return flush_bits;
1974 }
1975
1976 static enum radv_cmd_flush_bits
1977 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1978 VkAccessFlags dst_flags,
1979 struct radv_image *image)
1980 {
1981 enum radv_cmd_flush_bits flush_bits = 0;
1982 uint32_t b;
1983 for_each_bit(b, dst_flags) {
1984 switch ((VkAccessFlagBits)(1 << b)) {
1985 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1986 case VK_ACCESS_INDEX_READ_BIT:
1987 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1988 break;
1989 case VK_ACCESS_UNIFORM_READ_BIT:
1990 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1991 break;
1992 case VK_ACCESS_SHADER_READ_BIT:
1993 case VK_ACCESS_TRANSFER_READ_BIT:
1994 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1995 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1996 RADV_CMD_FLAG_INV_GLOBAL_L2;
1997 break;
1998 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1999 /* TODO: change to image && when the image gets passed
2000 * through from the subpass. */
2001 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2002 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2004 break;
2005 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2006 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2007 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2008 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2009 break;
2010 default:
2011 break;
2012 }
2013 }
2014 return flush_bits;
2015 }
2016
2017 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2018 {
2019 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2020 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2021 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2022 NULL);
2023 }
2024
2025 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2026 VkAttachmentReference att)
2027 {
2028 unsigned idx = att.attachment;
2029 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2030 VkImageSubresourceRange range;
2031 range.aspectMask = 0;
2032 range.baseMipLevel = view->base_mip;
2033 range.levelCount = 1;
2034 range.baseArrayLayer = view->base_layer;
2035 range.layerCount = cmd_buffer->state.framebuffer->layers;
2036
2037 radv_handle_image_transition(cmd_buffer,
2038 view->image,
2039 cmd_buffer->state.attachments[idx].current_layout,
2040 att.layout, 0, 0, &range,
2041 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2042
2043 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2044
2045
2046 }
2047
2048 void
2049 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2050 const struct radv_subpass *subpass, bool transitions)
2051 {
2052 if (transitions) {
2053 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2054
2055 for (unsigned i = 0; i < subpass->color_count; ++i) {
2056 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2057 radv_handle_subpass_image_transition(cmd_buffer,
2058 subpass->color_attachments[i]);
2059 }
2060
2061 for (unsigned i = 0; i < subpass->input_count; ++i) {
2062 radv_handle_subpass_image_transition(cmd_buffer,
2063 subpass->input_attachments[i]);
2064 }
2065
2066 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2067 radv_handle_subpass_image_transition(cmd_buffer,
2068 subpass->depth_stencil_attachment);
2069 }
2070 }
2071
2072 cmd_buffer->state.subpass = subpass;
2073
2074 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2075 }
2076
2077 static VkResult
2078 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2079 struct radv_render_pass *pass,
2080 const VkRenderPassBeginInfo *info)
2081 {
2082 struct radv_cmd_state *state = &cmd_buffer->state;
2083
2084 if (pass->attachment_count == 0) {
2085 state->attachments = NULL;
2086 return VK_SUCCESS;
2087 }
2088
2089 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2090 pass->attachment_count *
2091 sizeof(state->attachments[0]),
2092 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2093 if (state->attachments == NULL) {
2094 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2095 return cmd_buffer->record_result;
2096 }
2097
2098 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2099 struct radv_render_pass_attachment *att = &pass->attachments[i];
2100 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2101 VkImageAspectFlags clear_aspects = 0;
2102
2103 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2104 /* color attachment */
2105 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2106 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2107 }
2108 } else {
2109 /* depthstencil attachment */
2110 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2111 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2112 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2113 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2114 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2115 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2116 }
2117 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2118 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2119 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2120 }
2121 }
2122
2123 state->attachments[i].pending_clear_aspects = clear_aspects;
2124 state->attachments[i].cleared_views = 0;
2125 if (clear_aspects && info) {
2126 assert(info->clearValueCount > i);
2127 state->attachments[i].clear_value = info->pClearValues[i];
2128 }
2129
2130 state->attachments[i].current_layout = att->initial_layout;
2131 }
2132
2133 return VK_SUCCESS;
2134 }
2135
2136 VkResult radv_AllocateCommandBuffers(
2137 VkDevice _device,
2138 const VkCommandBufferAllocateInfo *pAllocateInfo,
2139 VkCommandBuffer *pCommandBuffers)
2140 {
2141 RADV_FROM_HANDLE(radv_device, device, _device);
2142 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2143
2144 VkResult result = VK_SUCCESS;
2145 uint32_t i;
2146
2147 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2148
2149 if (!list_empty(&pool->free_cmd_buffers)) {
2150 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2151
2152 list_del(&cmd_buffer->pool_link);
2153 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2154
2155 result = radv_reset_cmd_buffer(cmd_buffer);
2156 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2157 cmd_buffer->level = pAllocateInfo->level;
2158
2159 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2160 } else {
2161 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2162 &pCommandBuffers[i]);
2163 }
2164 if (result != VK_SUCCESS)
2165 break;
2166 }
2167
2168 if (result != VK_SUCCESS) {
2169 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2170 i, pCommandBuffers);
2171
2172 /* From the Vulkan 1.0.66 spec:
2173 *
2174 * "vkAllocateCommandBuffers can be used to create multiple
2175 * command buffers. If the creation of any of those command
2176 * buffers fails, the implementation must destroy all
2177 * successfully created command buffer objects from this
2178 * command, set all entries of the pCommandBuffers array to
2179 * NULL and return the error."
2180 */
2181 memset(pCommandBuffers, 0,
2182 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2183 }
2184
2185 return result;
2186 }
2187
2188 void radv_FreeCommandBuffers(
2189 VkDevice device,
2190 VkCommandPool commandPool,
2191 uint32_t commandBufferCount,
2192 const VkCommandBuffer *pCommandBuffers)
2193 {
2194 for (uint32_t i = 0; i < commandBufferCount; i++) {
2195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2196
2197 if (cmd_buffer) {
2198 if (cmd_buffer->pool) {
2199 list_del(&cmd_buffer->pool_link);
2200 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2201 } else
2202 radv_cmd_buffer_destroy(cmd_buffer);
2203
2204 }
2205 }
2206 }
2207
2208 VkResult radv_ResetCommandBuffer(
2209 VkCommandBuffer commandBuffer,
2210 VkCommandBufferResetFlags flags)
2211 {
2212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2213 return radv_reset_cmd_buffer(cmd_buffer);
2214 }
2215
2216 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2217 {
2218 struct radv_device *device = cmd_buffer->device;
2219 if (device->gfx_init) {
2220 uint64_t va = radv_buffer_get_va(device->gfx_init);
2221 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2222 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2223 radeon_emit(cmd_buffer->cs, va);
2224 radeon_emit(cmd_buffer->cs, va >> 32);
2225 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2226 } else
2227 si_init_config(cmd_buffer);
2228 }
2229
2230 VkResult radv_BeginCommandBuffer(
2231 VkCommandBuffer commandBuffer,
2232 const VkCommandBufferBeginInfo *pBeginInfo)
2233 {
2234 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2235 VkResult result = VK_SUCCESS;
2236
2237 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2238 /* If the command buffer has already been resetted with
2239 * vkResetCommandBuffer, no need to do it again.
2240 */
2241 result = radv_reset_cmd_buffer(cmd_buffer);
2242 if (result != VK_SUCCESS)
2243 return result;
2244 }
2245
2246 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2247 cmd_buffer->state.last_primitive_reset_en = -1;
2248 cmd_buffer->state.last_index_type = -1;
2249 cmd_buffer->usage_flags = pBeginInfo->flags;
2250
2251 /* setup initial configuration into command buffer */
2252 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2253 switch (cmd_buffer->queue_family_index) {
2254 case RADV_QUEUE_GENERAL:
2255 emit_gfx_buffer_state(cmd_buffer);
2256 break;
2257 case RADV_QUEUE_COMPUTE:
2258 si_init_compute(cmd_buffer);
2259 break;
2260 case RADV_QUEUE_TRANSFER:
2261 default:
2262 break;
2263 }
2264 }
2265
2266 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2267 assert(pBeginInfo->pInheritanceInfo);
2268 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2269 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2270
2271 struct radv_subpass *subpass =
2272 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2273
2274 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2275 if (result != VK_SUCCESS)
2276 return result;
2277
2278 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2279 }
2280
2281 if (unlikely(cmd_buffer->device->trace_bo))
2282 radv_cmd_buffer_trace_emit(cmd_buffer);
2283
2284 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2285
2286 return result;
2287 }
2288
2289 void radv_CmdBindVertexBuffers(
2290 VkCommandBuffer commandBuffer,
2291 uint32_t firstBinding,
2292 uint32_t bindingCount,
2293 const VkBuffer* pBuffers,
2294 const VkDeviceSize* pOffsets)
2295 {
2296 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2297 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2298 bool changed = false;
2299
2300 /* We have to defer setting up vertex buffer since we need the buffer
2301 * stride from the pipeline. */
2302
2303 assert(firstBinding + bindingCount <= MAX_VBS);
2304 for (uint32_t i = 0; i < bindingCount; i++) {
2305 uint32_t idx = firstBinding + i;
2306
2307 if (!changed &&
2308 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2309 vb[idx].offset != pOffsets[i])) {
2310 changed = true;
2311 }
2312
2313 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2314 vb[idx].offset = pOffsets[i];
2315
2316 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2317 vb[idx].buffer->bo, 8);
2318 }
2319
2320 if (!changed) {
2321 /* No state changes. */
2322 return;
2323 }
2324
2325 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2326 }
2327
2328 void radv_CmdBindIndexBuffer(
2329 VkCommandBuffer commandBuffer,
2330 VkBuffer buffer,
2331 VkDeviceSize offset,
2332 VkIndexType indexType)
2333 {
2334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2335 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2336
2337 if (cmd_buffer->state.index_buffer == index_buffer &&
2338 cmd_buffer->state.index_offset == offset &&
2339 cmd_buffer->state.index_type == indexType) {
2340 /* No state changes. */
2341 return;
2342 }
2343
2344 cmd_buffer->state.index_buffer = index_buffer;
2345 cmd_buffer->state.index_offset = offset;
2346 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2347 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2348 cmd_buffer->state.index_va += index_buffer->offset + offset;
2349
2350 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2351 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2352 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2353 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2354 }
2355
2356
2357 static void
2358 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2359 struct radv_descriptor_set *set, unsigned idx)
2360 {
2361 struct radeon_winsys *ws = cmd_buffer->device->ws;
2362
2363 radv_set_descriptor_set(cmd_buffer, set, idx);
2364 if (!set)
2365 return;
2366
2367 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2368
2369 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2370 if (set->descriptors[j])
2371 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2372
2373 if(set->bo)
2374 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2375 }
2376
2377 void radv_CmdBindDescriptorSets(
2378 VkCommandBuffer commandBuffer,
2379 VkPipelineBindPoint pipelineBindPoint,
2380 VkPipelineLayout _layout,
2381 uint32_t firstSet,
2382 uint32_t descriptorSetCount,
2383 const VkDescriptorSet* pDescriptorSets,
2384 uint32_t dynamicOffsetCount,
2385 const uint32_t* pDynamicOffsets)
2386 {
2387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2388 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2389 unsigned dyn_idx = 0;
2390
2391 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2392 unsigned idx = i + firstSet;
2393 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2394 radv_bind_descriptor_set(cmd_buffer, set, idx);
2395
2396 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2397 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2398 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2399 assert(dyn_idx < dynamicOffsetCount);
2400
2401 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2402 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2403 dst[0] = va;
2404 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2405 dst[2] = range->size;
2406 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2407 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2408 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2409 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2410 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2411 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2412 cmd_buffer->push_constant_stages |=
2413 set->layout->dynamic_shader_stages;
2414 }
2415 }
2416 }
2417
2418 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2419 struct radv_descriptor_set *set,
2420 struct radv_descriptor_set_layout *layout)
2421 {
2422 set->size = layout->size;
2423 set->layout = layout;
2424
2425 if (cmd_buffer->push_descriptors.capacity < set->size) {
2426 size_t new_size = MAX2(set->size, 1024);
2427 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2428 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2429
2430 free(set->mapped_ptr);
2431 set->mapped_ptr = malloc(new_size);
2432
2433 if (!set->mapped_ptr) {
2434 cmd_buffer->push_descriptors.capacity = 0;
2435 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2436 return false;
2437 }
2438
2439 cmd_buffer->push_descriptors.capacity = new_size;
2440 }
2441
2442 return true;
2443 }
2444
2445 void radv_meta_push_descriptor_set(
2446 struct radv_cmd_buffer* cmd_buffer,
2447 VkPipelineBindPoint pipelineBindPoint,
2448 VkPipelineLayout _layout,
2449 uint32_t set,
2450 uint32_t descriptorWriteCount,
2451 const VkWriteDescriptorSet* pDescriptorWrites)
2452 {
2453 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2454 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2455 unsigned bo_offset;
2456
2457 assert(set == 0);
2458 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2459
2460 push_set->size = layout->set[set].layout->size;
2461 push_set->layout = layout->set[set].layout;
2462
2463 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2464 &bo_offset,
2465 (void**) &push_set->mapped_ptr))
2466 return;
2467
2468 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2469 push_set->va += bo_offset;
2470
2471 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2472 radv_descriptor_set_to_handle(push_set),
2473 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2474
2475 radv_set_descriptor_set(cmd_buffer, push_set, set);
2476 }
2477
2478 void radv_CmdPushDescriptorSetKHR(
2479 VkCommandBuffer commandBuffer,
2480 VkPipelineBindPoint pipelineBindPoint,
2481 VkPipelineLayout _layout,
2482 uint32_t set,
2483 uint32_t descriptorWriteCount,
2484 const VkWriteDescriptorSet* pDescriptorWrites)
2485 {
2486 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2487 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2488 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2489
2490 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2491
2492 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2493 return;
2494
2495 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2496 radv_descriptor_set_to_handle(push_set),
2497 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2498
2499 radv_set_descriptor_set(cmd_buffer, push_set, set);
2500 cmd_buffer->state.push_descriptors_dirty = true;
2501 }
2502
2503 void radv_CmdPushDescriptorSetWithTemplateKHR(
2504 VkCommandBuffer commandBuffer,
2505 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2506 VkPipelineLayout _layout,
2507 uint32_t set,
2508 const void* pData)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2511 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2512 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2513
2514 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2515
2516 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2517 return;
2518
2519 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2520 descriptorUpdateTemplate, pData);
2521
2522 radv_set_descriptor_set(cmd_buffer, push_set, set);
2523 cmd_buffer->state.push_descriptors_dirty = true;
2524 }
2525
2526 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2527 VkPipelineLayout layout,
2528 VkShaderStageFlags stageFlags,
2529 uint32_t offset,
2530 uint32_t size,
2531 const void* pValues)
2532 {
2533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2534 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2535 cmd_buffer->push_constant_stages |= stageFlags;
2536 }
2537
2538 VkResult radv_EndCommandBuffer(
2539 VkCommandBuffer commandBuffer)
2540 {
2541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2542
2543 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2544 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2545 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2546 si_emit_cache_flush(cmd_buffer);
2547 }
2548
2549 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2550
2551 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2552 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2553
2554 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2555
2556 return cmd_buffer->record_result;
2557 }
2558
2559 static void
2560 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2561 {
2562 struct radv_shader_variant *compute_shader;
2563 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2564 struct radv_device *device = cmd_buffer->device;
2565 unsigned compute_resource_limits;
2566 unsigned waves_per_threadgroup;
2567 uint64_t va;
2568
2569 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2570 return;
2571
2572 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2573
2574 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2575 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2576
2577 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2578 cmd_buffer->cs, 19);
2579
2580 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2581 radeon_emit(cmd_buffer->cs, va >> 8);
2582 radeon_emit(cmd_buffer->cs, va >> 40);
2583
2584 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2585 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2586 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2587
2588
2589 cmd_buffer->compute_scratch_size_needed =
2590 MAX2(cmd_buffer->compute_scratch_size_needed,
2591 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2592
2593 /* change these once we have scratch support */
2594 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2595 S_00B860_WAVES(pipeline->max_waves) |
2596 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2597
2598 /* Calculate best compute resource limits. */
2599 waves_per_threadgroup =
2600 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2601 compute_shader->info.cs.block_size[1] *
2602 compute_shader->info.cs.block_size[2], 64);
2603 compute_resource_limits =
2604 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2605
2606 if (device->physical_device->rad_info.chip_class >= CIK) {
2607 unsigned num_cu_per_se =
2608 device->physical_device->rad_info.num_good_compute_units /
2609 device->physical_device->rad_info.max_se;
2610
2611 /* Force even distribution on all SIMDs in CU if the workgroup
2612 * size is 64. This has shown some good improvements if # of
2613 * CUs per SE is not a multiple of 4.
2614 */
2615 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2616 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2617 }
2618
2619 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2620 compute_resource_limits);
2621
2622 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2623 radeon_emit(cmd_buffer->cs,
2624 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2625 radeon_emit(cmd_buffer->cs,
2626 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2627 radeon_emit(cmd_buffer->cs,
2628 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2629
2630 assert(cmd_buffer->cs->cdw <= cdw_max);
2631
2632 if (unlikely(cmd_buffer->device->trace_bo))
2633 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2634 }
2635
2636 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2637 {
2638 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2639 }
2640
2641 void radv_CmdBindPipeline(
2642 VkCommandBuffer commandBuffer,
2643 VkPipelineBindPoint pipelineBindPoint,
2644 VkPipeline _pipeline)
2645 {
2646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2647 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2648
2649 switch (pipelineBindPoint) {
2650 case VK_PIPELINE_BIND_POINT_COMPUTE:
2651 if (cmd_buffer->state.compute_pipeline == pipeline)
2652 return;
2653 radv_mark_descriptor_sets_dirty(cmd_buffer);
2654
2655 cmd_buffer->state.compute_pipeline = pipeline;
2656 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2657 break;
2658 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2659 if (cmd_buffer->state.pipeline == pipeline)
2660 return;
2661 radv_mark_descriptor_sets_dirty(cmd_buffer);
2662
2663 cmd_buffer->state.pipeline = pipeline;
2664 if (!pipeline)
2665 break;
2666
2667 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2668 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2669
2670 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2671
2672 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2673 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2674 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2675 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2676
2677 if (radv_pipeline_has_tess(pipeline))
2678 cmd_buffer->tess_rings_needed = true;
2679
2680 if (radv_pipeline_has_gs(pipeline)) {
2681 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2682 AC_UD_SCRATCH_RING_OFFSETS);
2683 if (cmd_buffer->ring_offsets_idx == -1)
2684 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2685 else if (loc->sgpr_idx != -1)
2686 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2687 }
2688 break;
2689 default:
2690 assert(!"invalid bind point");
2691 break;
2692 }
2693 }
2694
2695 void radv_CmdSetViewport(
2696 VkCommandBuffer commandBuffer,
2697 uint32_t firstViewport,
2698 uint32_t viewportCount,
2699 const VkViewport* pViewports)
2700 {
2701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2702 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2703
2704 assert(firstViewport < MAX_VIEWPORTS);
2705 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2706
2707 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2708 pViewports, viewportCount * sizeof(*pViewports));
2709
2710 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2711 }
2712
2713 void radv_CmdSetScissor(
2714 VkCommandBuffer commandBuffer,
2715 uint32_t firstScissor,
2716 uint32_t scissorCount,
2717 const VkRect2D* pScissors)
2718 {
2719 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2720 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2721
2722 assert(firstScissor < MAX_SCISSORS);
2723 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2724
2725 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2726 pScissors, scissorCount * sizeof(*pScissors));
2727 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2728 }
2729
2730 void radv_CmdSetLineWidth(
2731 VkCommandBuffer commandBuffer,
2732 float lineWidth)
2733 {
2734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2735 cmd_buffer->state.dynamic.line_width = lineWidth;
2736 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2737 }
2738
2739 void radv_CmdSetDepthBias(
2740 VkCommandBuffer commandBuffer,
2741 float depthBiasConstantFactor,
2742 float depthBiasClamp,
2743 float depthBiasSlopeFactor)
2744 {
2745 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2746
2747 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2748 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2749 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2750
2751 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2752 }
2753
2754 void radv_CmdSetBlendConstants(
2755 VkCommandBuffer commandBuffer,
2756 const float blendConstants[4])
2757 {
2758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2759
2760 memcpy(cmd_buffer->state.dynamic.blend_constants,
2761 blendConstants, sizeof(float) * 4);
2762
2763 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2764 }
2765
2766 void radv_CmdSetDepthBounds(
2767 VkCommandBuffer commandBuffer,
2768 float minDepthBounds,
2769 float maxDepthBounds)
2770 {
2771 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2772
2773 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2774 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2775
2776 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2777 }
2778
2779 void radv_CmdSetStencilCompareMask(
2780 VkCommandBuffer commandBuffer,
2781 VkStencilFaceFlags faceMask,
2782 uint32_t compareMask)
2783 {
2784 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2785
2786 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2787 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2788 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2789 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2790
2791 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2792 }
2793
2794 void radv_CmdSetStencilWriteMask(
2795 VkCommandBuffer commandBuffer,
2796 VkStencilFaceFlags faceMask,
2797 uint32_t writeMask)
2798 {
2799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2800
2801 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2802 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2803 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2804 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2805
2806 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2807 }
2808
2809 void radv_CmdSetStencilReference(
2810 VkCommandBuffer commandBuffer,
2811 VkStencilFaceFlags faceMask,
2812 uint32_t reference)
2813 {
2814 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2815
2816 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2817 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2818 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2819 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2820
2821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2822 }
2823
2824 void radv_CmdExecuteCommands(
2825 VkCommandBuffer commandBuffer,
2826 uint32_t commandBufferCount,
2827 const VkCommandBuffer* pCmdBuffers)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2830
2831 assert(commandBufferCount > 0);
2832
2833 /* Emit pending flushes on primary prior to executing secondary */
2834 si_emit_cache_flush(primary);
2835
2836 for (uint32_t i = 0; i < commandBufferCount; i++) {
2837 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2838
2839 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2840 secondary->scratch_size_needed);
2841 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2842 secondary->compute_scratch_size_needed);
2843
2844 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2845 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2846 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2847 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2848 if (secondary->tess_rings_needed)
2849 primary->tess_rings_needed = true;
2850 if (secondary->sample_positions_needed)
2851 primary->sample_positions_needed = true;
2852
2853 if (secondary->ring_offsets_idx != -1) {
2854 if (primary->ring_offsets_idx == -1)
2855 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2856 else
2857 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2858 }
2859 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2860
2861
2862 /* When the secondary command buffer is compute only we don't
2863 * need to re-emit the current graphics pipeline.
2864 */
2865 if (secondary->state.emitted_pipeline) {
2866 primary->state.emitted_pipeline =
2867 secondary->state.emitted_pipeline;
2868 }
2869
2870 /* When the secondary command buffer is graphics only we don't
2871 * need to re-emit the current compute pipeline.
2872 */
2873 if (secondary->state.emitted_compute_pipeline) {
2874 primary->state.emitted_compute_pipeline =
2875 secondary->state.emitted_compute_pipeline;
2876 }
2877
2878 /* Only re-emit the draw packets when needed. */
2879 if (secondary->state.last_primitive_reset_en != -1) {
2880 primary->state.last_primitive_reset_en =
2881 secondary->state.last_primitive_reset_en;
2882 }
2883
2884 if (secondary->state.last_primitive_reset_index) {
2885 primary->state.last_primitive_reset_index =
2886 secondary->state.last_primitive_reset_index;
2887 }
2888
2889 if (secondary->state.last_ia_multi_vgt_param) {
2890 primary->state.last_ia_multi_vgt_param =
2891 secondary->state.last_ia_multi_vgt_param;
2892 }
2893
2894 if (secondary->state.last_index_type != -1) {
2895 primary->state.last_index_type =
2896 secondary->state.last_index_type;
2897 }
2898 }
2899
2900 /* After executing commands from secondary buffers we have to dirty
2901 * some states.
2902 */
2903 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2904 RADV_CMD_DIRTY_INDEX_BUFFER |
2905 RADV_CMD_DIRTY_DYNAMIC_ALL;
2906 radv_mark_descriptor_sets_dirty(primary);
2907 }
2908
2909 VkResult radv_CreateCommandPool(
2910 VkDevice _device,
2911 const VkCommandPoolCreateInfo* pCreateInfo,
2912 const VkAllocationCallbacks* pAllocator,
2913 VkCommandPool* pCmdPool)
2914 {
2915 RADV_FROM_HANDLE(radv_device, device, _device);
2916 struct radv_cmd_pool *pool;
2917
2918 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2919 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2920 if (pool == NULL)
2921 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2922
2923 if (pAllocator)
2924 pool->alloc = *pAllocator;
2925 else
2926 pool->alloc = device->alloc;
2927
2928 list_inithead(&pool->cmd_buffers);
2929 list_inithead(&pool->free_cmd_buffers);
2930
2931 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2932
2933 *pCmdPool = radv_cmd_pool_to_handle(pool);
2934
2935 return VK_SUCCESS;
2936
2937 }
2938
2939 void radv_DestroyCommandPool(
2940 VkDevice _device,
2941 VkCommandPool commandPool,
2942 const VkAllocationCallbacks* pAllocator)
2943 {
2944 RADV_FROM_HANDLE(radv_device, device, _device);
2945 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2946
2947 if (!pool)
2948 return;
2949
2950 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2951 &pool->cmd_buffers, pool_link) {
2952 radv_cmd_buffer_destroy(cmd_buffer);
2953 }
2954
2955 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2956 &pool->free_cmd_buffers, pool_link) {
2957 radv_cmd_buffer_destroy(cmd_buffer);
2958 }
2959
2960 vk_free2(&device->alloc, pAllocator, pool);
2961 }
2962
2963 VkResult radv_ResetCommandPool(
2964 VkDevice device,
2965 VkCommandPool commandPool,
2966 VkCommandPoolResetFlags flags)
2967 {
2968 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2969 VkResult result;
2970
2971 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2972 &pool->cmd_buffers, pool_link) {
2973 result = radv_reset_cmd_buffer(cmd_buffer);
2974 if (result != VK_SUCCESS)
2975 return result;
2976 }
2977
2978 return VK_SUCCESS;
2979 }
2980
2981 void radv_TrimCommandPoolKHR(
2982 VkDevice device,
2983 VkCommandPool commandPool,
2984 VkCommandPoolTrimFlagsKHR flags)
2985 {
2986 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2987
2988 if (!pool)
2989 return;
2990
2991 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2992 &pool->free_cmd_buffers, pool_link) {
2993 radv_cmd_buffer_destroy(cmd_buffer);
2994 }
2995 }
2996
2997 void radv_CmdBeginRenderPass(
2998 VkCommandBuffer commandBuffer,
2999 const VkRenderPassBeginInfo* pRenderPassBegin,
3000 VkSubpassContents contents)
3001 {
3002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3003 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3004 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3005
3006 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3007 cmd_buffer->cs, 2048);
3008 MAYBE_UNUSED VkResult result;
3009
3010 cmd_buffer->state.framebuffer = framebuffer;
3011 cmd_buffer->state.pass = pass;
3012 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3013
3014 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3015 if (result != VK_SUCCESS)
3016 return;
3017
3018 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3019 assert(cmd_buffer->cs->cdw <= cdw_max);
3020
3021 radv_cmd_buffer_clear_subpass(cmd_buffer);
3022 }
3023
3024 void radv_CmdNextSubpass(
3025 VkCommandBuffer commandBuffer,
3026 VkSubpassContents contents)
3027 {
3028 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3029
3030 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3031
3032 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3033 2048);
3034
3035 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3036 radv_cmd_buffer_clear_subpass(cmd_buffer);
3037 }
3038
3039 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3040 {
3041 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3042 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3043 if (!pipeline->shaders[stage])
3044 continue;
3045 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3046 if (loc->sgpr_idx == -1)
3047 continue;
3048 uint32_t base_reg = pipeline->user_data_0[stage];
3049 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3050
3051 }
3052 if (pipeline->gs_copy_shader) {
3053 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3054 if (loc->sgpr_idx != -1) {
3055 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3056 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3057 }
3058 }
3059 }
3060
3061 static void
3062 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3063 uint32_t vertex_count)
3064 {
3065 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3066 radeon_emit(cmd_buffer->cs, vertex_count);
3067 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3068 S_0287F0_USE_OPAQUE(0));
3069 }
3070
3071 static void
3072 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3073 uint64_t index_va,
3074 uint32_t index_count)
3075 {
3076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3077 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3078 radeon_emit(cmd_buffer->cs, index_va);
3079 radeon_emit(cmd_buffer->cs, index_va >> 32);
3080 radeon_emit(cmd_buffer->cs, index_count);
3081 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3082 }
3083
3084 static void
3085 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3086 bool indexed,
3087 uint32_t draw_count,
3088 uint64_t count_va,
3089 uint32_t stride)
3090 {
3091 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3092 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3093 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3094 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3095 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3096 assert(base_reg);
3097
3098 if (draw_count == 1 && !count_va && !draw_id_enable) {
3099 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3100 PKT3_DRAW_INDIRECT, 3, false));
3101 radeon_emit(cs, 0);
3102 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3103 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3104 radeon_emit(cs, di_src_sel);
3105 } else {
3106 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3107 PKT3_DRAW_INDIRECT_MULTI,
3108 8, false));
3109 radeon_emit(cs, 0);
3110 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3111 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3112 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3113 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3114 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3115 radeon_emit(cs, draw_count); /* count */
3116 radeon_emit(cs, count_va); /* count_addr */
3117 radeon_emit(cs, count_va >> 32);
3118 radeon_emit(cs, stride); /* stride */
3119 radeon_emit(cs, di_src_sel);
3120 }
3121 }
3122
3123 struct radv_draw_info {
3124 /**
3125 * Number of vertices.
3126 */
3127 uint32_t count;
3128
3129 /**
3130 * Index of the first vertex.
3131 */
3132 int32_t vertex_offset;
3133
3134 /**
3135 * First instance id.
3136 */
3137 uint32_t first_instance;
3138
3139 /**
3140 * Number of instances.
3141 */
3142 uint32_t instance_count;
3143
3144 /**
3145 * First index (indexed draws only).
3146 */
3147 uint32_t first_index;
3148
3149 /**
3150 * Whether it's an indexed draw.
3151 */
3152 bool indexed;
3153
3154 /**
3155 * Indirect draw parameters resource.
3156 */
3157 struct radv_buffer *indirect;
3158 uint64_t indirect_offset;
3159 uint32_t stride;
3160
3161 /**
3162 * Draw count parameters resource.
3163 */
3164 struct radv_buffer *count_buffer;
3165 uint64_t count_buffer_offset;
3166 };
3167
3168 static void
3169 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3170 const struct radv_draw_info *info)
3171 {
3172 struct radv_cmd_state *state = &cmd_buffer->state;
3173 struct radeon_winsys *ws = cmd_buffer->device->ws;
3174 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3175
3176 if (info->indirect) {
3177 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3178 uint64_t count_va = 0;
3179
3180 va += info->indirect->offset + info->indirect_offset;
3181
3182 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3183
3184 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3185 radeon_emit(cs, 1);
3186 radeon_emit(cs, va);
3187 radeon_emit(cs, va >> 32);
3188
3189 if (info->count_buffer) {
3190 count_va = radv_buffer_get_va(info->count_buffer->bo);
3191 count_va += info->count_buffer->offset +
3192 info->count_buffer_offset;
3193
3194 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3195 }
3196
3197 if (!state->subpass->view_mask) {
3198 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3199 info->indexed,
3200 info->count,
3201 count_va,
3202 info->stride);
3203 } else {
3204 unsigned i;
3205 for_each_bit(i, state->subpass->view_mask) {
3206 radv_emit_view_index(cmd_buffer, i);
3207
3208 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3209 info->indexed,
3210 info->count,
3211 count_va,
3212 info->stride);
3213 }
3214 }
3215 } else {
3216 assert(state->pipeline->graphics.vtx_base_sgpr);
3217 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3218 state->pipeline->graphics.vtx_emit_num);
3219 radeon_emit(cs, info->vertex_offset);
3220 radeon_emit(cs, info->first_instance);
3221 if (state->pipeline->graphics.vtx_emit_num == 3)
3222 radeon_emit(cs, 0);
3223
3224 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3225 radeon_emit(cs, info->instance_count);
3226
3227 if (info->indexed) {
3228 int index_size = state->index_type ? 4 : 2;
3229 uint64_t index_va;
3230
3231 index_va = state->index_va;
3232 index_va += info->first_index * index_size;
3233
3234 if (!state->subpass->view_mask) {
3235 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3236 index_va,
3237 info->count);
3238 } else {
3239 unsigned i;
3240 for_each_bit(i, state->subpass->view_mask) {
3241 radv_emit_view_index(cmd_buffer, i);
3242
3243 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3244 index_va,
3245 info->count);
3246 }
3247 }
3248 } else {
3249 if (!state->subpass->view_mask) {
3250 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3251 } else {
3252 unsigned i;
3253 for_each_bit(i, state->subpass->view_mask) {
3254 radv_emit_view_index(cmd_buffer, i);
3255
3256 radv_cs_emit_draw_packet(cmd_buffer,
3257 info->count);
3258 }
3259 }
3260 }
3261 }
3262 }
3263
3264 static void
3265 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3266 const struct radv_draw_info *info)
3267 {
3268 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3269 radv_emit_graphics_pipeline(cmd_buffer);
3270
3271 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3272 radv_emit_framebuffer_state(cmd_buffer);
3273
3274 if (info->indexed) {
3275 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3276 radv_emit_index_buffer(cmd_buffer);
3277 } else {
3278 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3279 * so the state must be re-emitted before the next indexed
3280 * draw.
3281 */
3282 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3283 cmd_buffer->state.last_index_type = -1;
3284 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3285 }
3286 }
3287
3288 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3289
3290 radv_emit_draw_registers(cmd_buffer, info->indexed,
3291 info->instance_count > 1, info->indirect,
3292 info->indirect ? 0 : info->count);
3293 }
3294
3295 static void
3296 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3297 const struct radv_draw_info *info)
3298 {
3299 bool pipeline_is_dirty =
3300 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3301 cmd_buffer->state.pipeline &&
3302 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3303
3304 MAYBE_UNUSED unsigned cdw_max =
3305 radeon_check_space(cmd_buffer->device->ws,
3306 cmd_buffer->cs, 4096);
3307
3308 /* Use optimal packet order based on whether we need to sync the
3309 * pipeline.
3310 */
3311 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3312 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3313 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3314 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3315 /* If we have to wait for idle, set all states first, so that
3316 * all SET packets are processed in parallel with previous draw
3317 * calls. Then upload descriptors, set shader pointers, and
3318 * draw, and prefetch at the end. This ensures that the time
3319 * the CUs are idle is very short. (there are only SET_SH
3320 * packets between the wait and the draw)
3321 */
3322 radv_emit_all_graphics_states(cmd_buffer, info);
3323 si_emit_cache_flush(cmd_buffer);
3324 /* <-- CUs are idle here --> */
3325
3326 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3327 return;
3328
3329 radv_emit_draw_packets(cmd_buffer, info);
3330 /* <-- CUs are busy here --> */
3331
3332 /* Start prefetches after the draw has been started. Both will
3333 * run in parallel, but starting the draw first is more
3334 * important.
3335 */
3336 if (pipeline_is_dirty) {
3337 radv_emit_prefetch(cmd_buffer,
3338 cmd_buffer->state.pipeline);
3339 }
3340 } else {
3341 /* If we don't wait for idle, start prefetches first, then set
3342 * states, and draw at the end.
3343 */
3344 si_emit_cache_flush(cmd_buffer);
3345
3346 if (pipeline_is_dirty) {
3347 radv_emit_prefetch(cmd_buffer,
3348 cmd_buffer->state.pipeline);
3349 }
3350
3351 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3352 return;
3353
3354 radv_emit_all_graphics_states(cmd_buffer, info);
3355 radv_emit_draw_packets(cmd_buffer, info);
3356 }
3357
3358 assert(cmd_buffer->cs->cdw <= cdw_max);
3359 radv_cmd_buffer_after_draw(cmd_buffer);
3360 }
3361
3362 void radv_CmdDraw(
3363 VkCommandBuffer commandBuffer,
3364 uint32_t vertexCount,
3365 uint32_t instanceCount,
3366 uint32_t firstVertex,
3367 uint32_t firstInstance)
3368 {
3369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3370 struct radv_draw_info info = {};
3371
3372 info.count = vertexCount;
3373 info.instance_count = instanceCount;
3374 info.first_instance = firstInstance;
3375 info.vertex_offset = firstVertex;
3376
3377 radv_draw(cmd_buffer, &info);
3378 }
3379
3380 void radv_CmdDrawIndexed(
3381 VkCommandBuffer commandBuffer,
3382 uint32_t indexCount,
3383 uint32_t instanceCount,
3384 uint32_t firstIndex,
3385 int32_t vertexOffset,
3386 uint32_t firstInstance)
3387 {
3388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3389 struct radv_draw_info info = {};
3390
3391 info.indexed = true;
3392 info.count = indexCount;
3393 info.instance_count = instanceCount;
3394 info.first_index = firstIndex;
3395 info.vertex_offset = vertexOffset;
3396 info.first_instance = firstInstance;
3397
3398 radv_draw(cmd_buffer, &info);
3399 }
3400
3401 void radv_CmdDrawIndirect(
3402 VkCommandBuffer commandBuffer,
3403 VkBuffer _buffer,
3404 VkDeviceSize offset,
3405 uint32_t drawCount,
3406 uint32_t stride)
3407 {
3408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3409 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3410 struct radv_draw_info info = {};
3411
3412 info.count = drawCount;
3413 info.indirect = buffer;
3414 info.indirect_offset = offset;
3415 info.stride = stride;
3416
3417 radv_draw(cmd_buffer, &info);
3418 }
3419
3420 void radv_CmdDrawIndexedIndirect(
3421 VkCommandBuffer commandBuffer,
3422 VkBuffer _buffer,
3423 VkDeviceSize offset,
3424 uint32_t drawCount,
3425 uint32_t stride)
3426 {
3427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3428 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3429 struct radv_draw_info info = {};
3430
3431 info.indexed = true;
3432 info.count = drawCount;
3433 info.indirect = buffer;
3434 info.indirect_offset = offset;
3435 info.stride = stride;
3436
3437 radv_draw(cmd_buffer, &info);
3438 }
3439
3440 void radv_CmdDrawIndirectCountAMD(
3441 VkCommandBuffer commandBuffer,
3442 VkBuffer _buffer,
3443 VkDeviceSize offset,
3444 VkBuffer _countBuffer,
3445 VkDeviceSize countBufferOffset,
3446 uint32_t maxDrawCount,
3447 uint32_t stride)
3448 {
3449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3450 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3451 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3452 struct radv_draw_info info = {};
3453
3454 info.count = maxDrawCount;
3455 info.indirect = buffer;
3456 info.indirect_offset = offset;
3457 info.count_buffer = count_buffer;
3458 info.count_buffer_offset = countBufferOffset;
3459 info.stride = stride;
3460
3461 radv_draw(cmd_buffer, &info);
3462 }
3463
3464 void radv_CmdDrawIndexedIndirectCountAMD(
3465 VkCommandBuffer commandBuffer,
3466 VkBuffer _buffer,
3467 VkDeviceSize offset,
3468 VkBuffer _countBuffer,
3469 VkDeviceSize countBufferOffset,
3470 uint32_t maxDrawCount,
3471 uint32_t stride)
3472 {
3473 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3474 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3475 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3476 struct radv_draw_info info = {};
3477
3478 info.indexed = true;
3479 info.count = maxDrawCount;
3480 info.indirect = buffer;
3481 info.indirect_offset = offset;
3482 info.count_buffer = count_buffer;
3483 info.count_buffer_offset = countBufferOffset;
3484 info.stride = stride;
3485
3486 radv_draw(cmd_buffer, &info);
3487 }
3488
3489 struct radv_dispatch_info {
3490 /**
3491 * Determine the layout of the grid (in block units) to be used.
3492 */
3493 uint32_t blocks[3];
3494
3495 /**
3496 * Whether it's an unaligned compute dispatch.
3497 */
3498 bool unaligned;
3499
3500 /**
3501 * Indirect compute parameters resource.
3502 */
3503 struct radv_buffer *indirect;
3504 uint64_t indirect_offset;
3505 };
3506
3507 static void
3508 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3509 const struct radv_dispatch_info *info)
3510 {
3511 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3512 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3513 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3514 struct radeon_winsys *ws = cmd_buffer->device->ws;
3515 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3516 struct ac_userdata_info *loc;
3517
3518 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3519 AC_UD_CS_GRID_SIZE);
3520
3521 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3522
3523 if (info->indirect) {
3524 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3525
3526 va += info->indirect->offset + info->indirect_offset;
3527
3528 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3529
3530 if (loc->sgpr_idx != -1) {
3531 for (unsigned i = 0; i < 3; ++i) {
3532 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3533 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3534 COPY_DATA_DST_SEL(COPY_DATA_REG));
3535 radeon_emit(cs, (va + 4 * i));
3536 radeon_emit(cs, (va + 4 * i) >> 32);
3537 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3538 + loc->sgpr_idx * 4) >> 2) + i);
3539 radeon_emit(cs, 0);
3540 }
3541 }
3542
3543 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3544 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3545 PKT3_SHADER_TYPE_S(1));
3546 radeon_emit(cs, va);
3547 radeon_emit(cs, va >> 32);
3548 radeon_emit(cs, dispatch_initiator);
3549 } else {
3550 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3551 PKT3_SHADER_TYPE_S(1));
3552 radeon_emit(cs, 1);
3553 radeon_emit(cs, va);
3554 radeon_emit(cs, va >> 32);
3555
3556 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3557 PKT3_SHADER_TYPE_S(1));
3558 radeon_emit(cs, 0);
3559 radeon_emit(cs, dispatch_initiator);
3560 }
3561 } else {
3562 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3563
3564 if (info->unaligned) {
3565 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3566 unsigned remainder[3];
3567
3568 /* If aligned, these should be an entire block size,
3569 * not 0.
3570 */
3571 remainder[0] = blocks[0] + cs_block_size[0] -
3572 align_u32_npot(blocks[0], cs_block_size[0]);
3573 remainder[1] = blocks[1] + cs_block_size[1] -
3574 align_u32_npot(blocks[1], cs_block_size[1]);
3575 remainder[2] = blocks[2] + cs_block_size[2] -
3576 align_u32_npot(blocks[2], cs_block_size[2]);
3577
3578 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3579 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3580 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3581
3582 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3583 radeon_emit(cs,
3584 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3585 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3586 radeon_emit(cs,
3587 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3588 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3589 radeon_emit(cs,
3590 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3591 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3592
3593 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3594 }
3595
3596 if (loc->sgpr_idx != -1) {
3597 assert(!loc->indirect);
3598 assert(loc->num_sgprs == 3);
3599
3600 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3601 loc->sgpr_idx * 4, 3);
3602 radeon_emit(cs, blocks[0]);
3603 radeon_emit(cs, blocks[1]);
3604 radeon_emit(cs, blocks[2]);
3605 }
3606
3607 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3608 PKT3_SHADER_TYPE_S(1));
3609 radeon_emit(cs, blocks[0]);
3610 radeon_emit(cs, blocks[1]);
3611 radeon_emit(cs, blocks[2]);
3612 radeon_emit(cs, dispatch_initiator);
3613 }
3614
3615 assert(cmd_buffer->cs->cdw <= cdw_max);
3616 }
3617
3618 static void
3619 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3620 {
3621 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3622 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3623 VK_SHADER_STAGE_COMPUTE_BIT);
3624 }
3625
3626 static void
3627 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3628 const struct radv_dispatch_info *info)
3629 {
3630 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3631 bool pipeline_is_dirty = pipeline &&
3632 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3633
3634 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3635 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3636 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3637 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3638 /* If we have to wait for idle, set all states first, so that
3639 * all SET packets are processed in parallel with previous draw
3640 * calls. Then upload descriptors, set shader pointers, and
3641 * dispatch, and prefetch at the end. This ensures that the
3642 * time the CUs are idle is very short. (there are only SET_SH
3643 * packets between the wait and the draw)
3644 */
3645 radv_emit_compute_pipeline(cmd_buffer);
3646 si_emit_cache_flush(cmd_buffer);
3647 /* <-- CUs are idle here --> */
3648
3649 radv_upload_compute_shader_descriptors(cmd_buffer);
3650
3651 radv_emit_dispatch_packets(cmd_buffer, info);
3652 /* <-- CUs are busy here --> */
3653
3654 /* Start prefetches after the dispatch has been started. Both
3655 * will run in parallel, but starting the dispatch first is
3656 * more important.
3657 */
3658 if (pipeline_is_dirty) {
3659 radv_emit_shader_prefetch(cmd_buffer,
3660 pipeline->shaders[MESA_SHADER_COMPUTE]);
3661 }
3662 } else {
3663 /* If we don't wait for idle, start prefetches first, then set
3664 * states, and dispatch at the end.
3665 */
3666 si_emit_cache_flush(cmd_buffer);
3667
3668 if (pipeline_is_dirty) {
3669 radv_emit_shader_prefetch(cmd_buffer,
3670 pipeline->shaders[MESA_SHADER_COMPUTE]);
3671 }
3672
3673 radv_upload_compute_shader_descriptors(cmd_buffer);
3674
3675 radv_emit_compute_pipeline(cmd_buffer);
3676 radv_emit_dispatch_packets(cmd_buffer, info);
3677 }
3678
3679 radv_cmd_buffer_after_draw(cmd_buffer);
3680 }
3681
3682 void radv_CmdDispatch(
3683 VkCommandBuffer commandBuffer,
3684 uint32_t x,
3685 uint32_t y,
3686 uint32_t z)
3687 {
3688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3689 struct radv_dispatch_info info = {};
3690
3691 info.blocks[0] = x;
3692 info.blocks[1] = y;
3693 info.blocks[2] = z;
3694
3695 radv_dispatch(cmd_buffer, &info);
3696 }
3697
3698 void radv_CmdDispatchIndirect(
3699 VkCommandBuffer commandBuffer,
3700 VkBuffer _buffer,
3701 VkDeviceSize offset)
3702 {
3703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3704 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3705 struct radv_dispatch_info info = {};
3706
3707 info.indirect = buffer;
3708 info.indirect_offset = offset;
3709
3710 radv_dispatch(cmd_buffer, &info);
3711 }
3712
3713 void radv_unaligned_dispatch(
3714 struct radv_cmd_buffer *cmd_buffer,
3715 uint32_t x,
3716 uint32_t y,
3717 uint32_t z)
3718 {
3719 struct radv_dispatch_info info = {};
3720
3721 info.blocks[0] = x;
3722 info.blocks[1] = y;
3723 info.blocks[2] = z;
3724 info.unaligned = 1;
3725
3726 radv_dispatch(cmd_buffer, &info);
3727 }
3728
3729 void radv_CmdEndRenderPass(
3730 VkCommandBuffer commandBuffer)
3731 {
3732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3733
3734 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3735
3736 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3737
3738 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3739 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3740 radv_handle_subpass_image_transition(cmd_buffer,
3741 (VkAttachmentReference){i, layout});
3742 }
3743
3744 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3745
3746 cmd_buffer->state.pass = NULL;
3747 cmd_buffer->state.subpass = NULL;
3748 cmd_buffer->state.attachments = NULL;
3749 cmd_buffer->state.framebuffer = NULL;
3750 }
3751
3752 /*
3753 * For HTILE we have the following interesting clear words:
3754 * 0x0000030f: Uncompressed.
3755 * 0xfffffff0: Clear depth to 1.0
3756 * 0x00000000: Clear depth to 0.0
3757 */
3758 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3759 struct radv_image *image,
3760 const VkImageSubresourceRange *range,
3761 uint32_t clear_word)
3762 {
3763 assert(range->baseMipLevel == 0);
3764 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3765 unsigned layer_count = radv_get_layerCount(image, range);
3766 uint64_t size = image->surface.htile_slice_size * layer_count;
3767 uint64_t offset = image->offset + image->htile_offset +
3768 image->surface.htile_slice_size * range->baseArrayLayer;
3769 struct radv_cmd_state *state = &cmd_buffer->state;
3770
3771 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3772 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3773
3774 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3775 size, clear_word);
3776
3777 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3778 }
3779
3780 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3781 struct radv_image *image,
3782 VkImageLayout src_layout,
3783 VkImageLayout dst_layout,
3784 unsigned src_queue_mask,
3785 unsigned dst_queue_mask,
3786 const VkImageSubresourceRange *range,
3787 VkImageAspectFlags pending_clears)
3788 {
3789 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3790 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3791 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3792 cmd_buffer->state.render_area.extent.width == image->info.width &&
3793 cmd_buffer->state.render_area.extent.height == image->info.height) {
3794 /* The clear will initialize htile. */
3795 return;
3796 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3797 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3798 /* TODO: merge with the clear if applicable */
3799 radv_initialize_htile(cmd_buffer, image, range, 0);
3800 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3801 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3802 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3803 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3804 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3805 VkImageSubresourceRange local_range = *range;
3806 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3807 local_range.baseMipLevel = 0;
3808 local_range.levelCount = 1;
3809
3810 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3811 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3812
3813 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3814
3815 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3816 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3817 }
3818 }
3819
3820 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3821 struct radv_image *image, uint32_t value)
3822 {
3823 struct radv_cmd_state *state = &cmd_buffer->state;
3824
3825 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3826 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3827
3828 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3829 image->offset + image->cmask.offset,
3830 image->cmask.size, value);
3831
3832 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3833 }
3834
3835 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3836 struct radv_image *image,
3837 VkImageLayout src_layout,
3838 VkImageLayout dst_layout,
3839 unsigned src_queue_mask,
3840 unsigned dst_queue_mask,
3841 const VkImageSubresourceRange *range)
3842 {
3843 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3844 if (image->fmask.size)
3845 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3846 else
3847 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3848 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3849 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3850 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3851 }
3852 }
3853
3854 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3855 struct radv_image *image, uint32_t value)
3856 {
3857 struct radv_cmd_state *state = &cmd_buffer->state;
3858
3859 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3860 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3861
3862 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3863 image->offset + image->dcc_offset,
3864 image->surface.dcc_size, value);
3865
3866 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3867 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3868 }
3869
3870 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3871 struct radv_image *image,
3872 VkImageLayout src_layout,
3873 VkImageLayout dst_layout,
3874 unsigned src_queue_mask,
3875 unsigned dst_queue_mask,
3876 const VkImageSubresourceRange *range)
3877 {
3878 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3879 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3880 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3881 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3882 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3883 }
3884 }
3885
3886 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3887 struct radv_image *image,
3888 VkImageLayout src_layout,
3889 VkImageLayout dst_layout,
3890 uint32_t src_family,
3891 uint32_t dst_family,
3892 const VkImageSubresourceRange *range,
3893 VkImageAspectFlags pending_clears)
3894 {
3895 if (image->exclusive && src_family != dst_family) {
3896 /* This is an acquire or a release operation and there will be
3897 * a corresponding release/acquire. Do the transition in the
3898 * most flexible queue. */
3899
3900 assert(src_family == cmd_buffer->queue_family_index ||
3901 dst_family == cmd_buffer->queue_family_index);
3902
3903 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3904 return;
3905
3906 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3907 (src_family == RADV_QUEUE_GENERAL ||
3908 dst_family == RADV_QUEUE_GENERAL))
3909 return;
3910 }
3911
3912 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3913 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3914
3915 if (image->surface.htile_size)
3916 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3917 dst_layout, src_queue_mask,
3918 dst_queue_mask, range,
3919 pending_clears);
3920
3921 if (image->cmask.size || image->fmask.size)
3922 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3923 dst_layout, src_queue_mask,
3924 dst_queue_mask, range);
3925
3926 if (image->surface.dcc_size)
3927 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3928 dst_layout, src_queue_mask,
3929 dst_queue_mask, range);
3930 }
3931
3932 void radv_CmdPipelineBarrier(
3933 VkCommandBuffer commandBuffer,
3934 VkPipelineStageFlags srcStageMask,
3935 VkPipelineStageFlags destStageMask,
3936 VkBool32 byRegion,
3937 uint32_t memoryBarrierCount,
3938 const VkMemoryBarrier* pMemoryBarriers,
3939 uint32_t bufferMemoryBarrierCount,
3940 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3941 uint32_t imageMemoryBarrierCount,
3942 const VkImageMemoryBarrier* pImageMemoryBarriers)
3943 {
3944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3945 enum radv_cmd_flush_bits src_flush_bits = 0;
3946 enum radv_cmd_flush_bits dst_flush_bits = 0;
3947
3948 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3949 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3950 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3951 NULL);
3952 }
3953
3954 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3955 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3956 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3957 NULL);
3958 }
3959
3960 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3961 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3962 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3963 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3964 image);
3965 }
3966
3967 radv_stage_flush(cmd_buffer, srcStageMask);
3968 cmd_buffer->state.flush_bits |= src_flush_bits;
3969
3970 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3971 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3972 radv_handle_image_transition(cmd_buffer, image,
3973 pImageMemoryBarriers[i].oldLayout,
3974 pImageMemoryBarriers[i].newLayout,
3975 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3976 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3977 &pImageMemoryBarriers[i].subresourceRange,
3978 0);
3979 }
3980
3981 cmd_buffer->state.flush_bits |= dst_flush_bits;
3982 }
3983
3984
3985 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3986 struct radv_event *event,
3987 VkPipelineStageFlags stageMask,
3988 unsigned value)
3989 {
3990 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3991 uint64_t va = radv_buffer_get_va(event->bo);
3992
3993 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3994
3995 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3996
3997 /* TODO: this is overkill. Probably should figure something out from
3998 * the stage mask. */
3999
4000 si_cs_emit_write_event_eop(cs,
4001 cmd_buffer->state.predicating,
4002 cmd_buffer->device->physical_device->rad_info.chip_class,
4003 false,
4004 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4005 1, va, 2, value);
4006
4007 assert(cmd_buffer->cs->cdw <= cdw_max);
4008 }
4009
4010 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4011 VkEvent _event,
4012 VkPipelineStageFlags stageMask)
4013 {
4014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4015 RADV_FROM_HANDLE(radv_event, event, _event);
4016
4017 write_event(cmd_buffer, event, stageMask, 1);
4018 }
4019
4020 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4021 VkEvent _event,
4022 VkPipelineStageFlags stageMask)
4023 {
4024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4025 RADV_FROM_HANDLE(radv_event, event, _event);
4026
4027 write_event(cmd_buffer, event, stageMask, 0);
4028 }
4029
4030 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4031 uint32_t eventCount,
4032 const VkEvent* pEvents,
4033 VkPipelineStageFlags srcStageMask,
4034 VkPipelineStageFlags dstStageMask,
4035 uint32_t memoryBarrierCount,
4036 const VkMemoryBarrier* pMemoryBarriers,
4037 uint32_t bufferMemoryBarrierCount,
4038 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4039 uint32_t imageMemoryBarrierCount,
4040 const VkImageMemoryBarrier* pImageMemoryBarriers)
4041 {
4042 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4043 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4044
4045 for (unsigned i = 0; i < eventCount; ++i) {
4046 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4047 uint64_t va = radv_buffer_get_va(event->bo);
4048
4049 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4050
4051 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4052
4053 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4054 assert(cmd_buffer->cs->cdw <= cdw_max);
4055 }
4056
4057
4058 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4059 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4060
4061 radv_handle_image_transition(cmd_buffer, image,
4062 pImageMemoryBarriers[i].oldLayout,
4063 pImageMemoryBarriers[i].newLayout,
4064 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4065 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4066 &pImageMemoryBarriers[i].subresourceRange,
4067 0);
4068 }
4069
4070 /* TODO: figure out how to do memory barriers without waiting */
4071 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4072 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4073 RADV_CMD_FLAG_INV_VMEM_L1 |
4074 RADV_CMD_FLAG_INV_SMEM_L1;
4075 }