2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
38 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
39 struct radv_image
*image
,
40 VkImageLayout src_layout
,
41 VkImageLayout dst_layout
,
44 const VkImageSubresourceRange
*range
,
45 VkImageAspectFlags pending_clears
);
47 const struct radv_dynamic_state default_dynamic_state
= {
60 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
65 .stencil_compare_mask
= {
69 .stencil_write_mask
= {
73 .stencil_reference
= {
80 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
81 const struct radv_dynamic_state
*src
,
84 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
85 dest
->viewport
.count
= src
->viewport
.count
;
86 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
90 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
91 dest
->scissor
.count
= src
->scissor
.count
;
92 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
96 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
97 dest
->line_width
= src
->line_width
;
99 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
100 dest
->depth_bias
= src
->depth_bias
;
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
103 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
106 dest
->depth_bounds
= src
->depth_bounds
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
109 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
112 dest
->stencil_write_mask
= src
->stencil_write_mask
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
115 dest
->stencil_reference
= src
->stencil_reference
;
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
120 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
121 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
124 enum ring_type
radv_queue_family_to_ring(int f
) {
126 case RADV_QUEUE_GENERAL
:
128 case RADV_QUEUE_COMPUTE
:
130 case RADV_QUEUE_TRANSFER
:
133 unreachable("Unknown queue family");
137 static VkResult
radv_create_cmd_buffer(
138 struct radv_device
* device
,
139 struct radv_cmd_pool
* pool
,
140 VkCommandBufferLevel level
,
141 VkCommandBuffer
* pCommandBuffer
)
143 struct radv_cmd_buffer
*cmd_buffer
;
146 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
148 if (cmd_buffer
== NULL
)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
151 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
152 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
153 cmd_buffer
->device
= device
;
154 cmd_buffer
->pool
= pool
;
155 cmd_buffer
->level
= level
;
158 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
159 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
162 /* Init the pool_link so we can safefly call list_del when we destroy
165 list_inithead(&cmd_buffer
->pool_link
);
166 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
169 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
171 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
172 if (!cmd_buffer
->cs
) {
173 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
177 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
179 cmd_buffer
->upload
.offset
= 0;
180 cmd_buffer
->upload
.size
= 0;
181 list_inithead(&cmd_buffer
->upload
.list
);
186 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
194 list_del(&cmd_buffer
->pool_link
);
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
197 &cmd_buffer
->upload
.list
, list
) {
198 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
203 if (cmd_buffer
->upload
.upload_bo
)
204 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
205 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
206 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
207 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
213 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
216 &cmd_buffer
->upload
.list
, list
) {
217 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
222 cmd_buffer
->scratch_size_needed
= 0;
223 cmd_buffer
->compute_scratch_size_needed
= 0;
224 cmd_buffer
->esgs_ring_size_needed
= 0;
225 cmd_buffer
->gsvs_ring_size_needed
= 0;
226 cmd_buffer
->tess_rings_needed
= false;
227 cmd_buffer
->sample_positions_needed
= false;
229 if (cmd_buffer
->upload
.upload_bo
)
230 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
231 cmd_buffer
->upload
.upload_bo
, 8);
232 cmd_buffer
->upload
.offset
= 0;
234 cmd_buffer
->record_fail
= false;
236 cmd_buffer
->ring_offsets_idx
= -1;
238 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
240 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
241 &cmd_buffer
->gfx9_fence_offset
,
243 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
252 struct radeon_winsys_bo
*bo
;
253 struct radv_cmd_buffer_upload
*upload
;
254 struct radv_device
*device
= cmd_buffer
->device
;
256 new_size
= MAX2(min_needed
, 16 * 1024);
257 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
259 bo
= device
->ws
->buffer_create(device
->ws
,
262 RADEON_FLAG_CPU_ACCESS
);
265 cmd_buffer
->record_fail
= true;
269 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
270 if (cmd_buffer
->upload
.upload_bo
) {
271 upload
= malloc(sizeof(*upload
));
274 cmd_buffer
->record_fail
= true;
275 device
->ws
->buffer_destroy(bo
);
279 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
280 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
283 cmd_buffer
->upload
.upload_bo
= bo
;
284 cmd_buffer
->upload
.size
= new_size
;
285 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
288 if (!cmd_buffer
->upload
.map
) {
289 cmd_buffer
->record_fail
= true;
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
300 unsigned *out_offset
,
303 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
304 if (offset
+ size
> cmd_buffer
->upload
.size
) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
310 *out_offset
= offset
;
311 *ptr
= cmd_buffer
->upload
.map
+ offset
;
313 cmd_buffer
->upload
.offset
= offset
+ size
;
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
319 unsigned size
, unsigned alignment
,
320 const void *data
, unsigned *out_offset
)
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
325 out_offset
, (void **)&ptr
))
329 memcpy(ptr
, data
, size
);
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
336 struct radv_device
*device
= cmd_buffer
->device
;
337 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
340 if (!device
->trace_bo
)
343 va
= device
->ws
->buffer_get_va(device
->trace_bo
);
345 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
347 ++cmd_buffer
->state
.trace_id
;
348 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
349 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
350 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME
));
354 radeon_emit(cs
, va
>> 32);
355 radeon_emit(cs
, cmd_buffer
->state
.trace_id
);
356 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
357 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
362 struct radv_pipeline
*pipeline
)
364 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
365 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
367 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
368 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
370 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
371 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
372 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
380 struct radv_pipeline
*pipeline
)
382 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
383 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
384 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
386 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
387 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x
)
394 x
>= 4096 ? 0xffff : x
* 16;
398 radv_shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
, bool has_tess
)
401 case MESA_SHADER_FRAGMENT
:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
403 case MESA_SHADER_VERTEX
:
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
407 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
408 case MESA_SHADER_GEOMETRY
:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
410 case MESA_SHADER_COMPUTE
:
411 return R_00B900_COMPUTE_USER_DATA_0
;
412 case MESA_SHADER_TESS_CTRL
:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
414 case MESA_SHADER_TESS_EVAL
:
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
420 unreachable("unknown shader");
424 struct ac_userdata_info
*
425 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
426 gl_shader_stage stage
,
429 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
433 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
434 struct radv_pipeline
*pipeline
,
435 gl_shader_stage stage
,
436 int idx
, uint64_t va
)
438 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
439 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
440 if (loc
->sgpr_idx
== -1)
442 assert(loc
->num_sgprs
== 2);
443 assert(!loc
->indirect
);
444 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
445 radeon_emit(cmd_buffer
->cs
, va
);
446 radeon_emit(cmd_buffer
->cs
, va
>> 32);
450 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
451 struct radv_pipeline
*pipeline
)
453 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
454 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
455 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
457 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
458 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
459 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
461 radeon_set_context_reg(cmd_buffer
->cs
, CM_R_028804_DB_EQAA
, ms
->db_eqaa
);
462 radeon_set_context_reg(cmd_buffer
->cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
464 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
467 radeon_set_context_reg_seq(cmd_buffer
->cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
468 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
469 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
475 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
476 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
478 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
480 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
481 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
482 if (loc
->sgpr_idx
== -1)
484 assert(loc
->num_sgprs
== 1);
485 assert(!loc
->indirect
);
486 switch (num_samples
) {
504 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
505 cmd_buffer
->sample_positions_needed
= true;
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
511 struct radv_pipeline
*pipeline
)
513 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
515 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
516 raster
->pa_cl_clip_cntl
);
518 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
519 raster
->spi_interp_control
);
521 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A00_PA_SU_POINT_SIZE
, 2);
522 unsigned tmp
= (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer
->cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
524 radeon_emit(cmd_buffer
->cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
527 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
528 raster
->pa_su_vtx_cntl
);
530 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
531 raster
->pa_su_sc_mode_cntl
);
535 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
538 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
539 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
543 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
544 struct radv_pipeline
*pipeline
,
545 struct radv_shader_variant
*shader
,
546 struct ac_vs_output_info
*outinfo
)
548 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
549 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
550 unsigned export_count
;
552 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
553 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
555 export_count
= MAX2(1, outinfo
->param_exports
);
556 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
557 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
559 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
560 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
561 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
562 V_02870C_SPI_SHADER_4COMP
:
563 V_02870C_SPI_SHADER_NONE
) |
564 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
565 V_02870C_SPI_SHADER_4COMP
:
566 V_02870C_SPI_SHADER_NONE
) |
567 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
568 V_02870C_SPI_SHADER_4COMP
:
569 V_02870C_SPI_SHADER_NONE
));
572 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
573 radeon_emit(cmd_buffer
->cs
, va
>> 8);
574 radeon_emit(cmd_buffer
->cs
, va
>> 40);
575 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
576 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
578 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
579 S_028818_VTX_W0_FMT(1) |
580 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
581 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
582 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
585 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
586 pipeline
->graphics
.pa_cl_vs_out_cntl
);
588 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
589 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
590 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
594 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
595 struct radv_shader_variant
*shader
,
596 struct ac_es_output_info
*outinfo
)
598 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
599 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
601 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
602 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
604 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
605 outinfo
->esgs_itemsize
/ 4);
606 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
607 radeon_emit(cmd_buffer
->cs
, va
>> 8);
608 radeon_emit(cmd_buffer
->cs
, va
>> 40);
609 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
610 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
614 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
615 struct radv_shader_variant
*shader
)
617 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
618 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
619 uint32_t rsrc2
= shader
->rsrc2
;
621 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
622 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
624 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
625 radeon_emit(cmd_buffer
->cs
, va
>> 8);
626 radeon_emit(cmd_buffer
->cs
, va
>> 40);
628 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
629 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
630 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
631 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
633 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
634 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
635 radeon_emit(cmd_buffer
->cs
, rsrc2
);
639 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
640 struct radv_shader_variant
*shader
)
642 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
643 uint64_t va
= ws
->buffer_get_va(shader
->bo
);
645 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
646 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
648 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
649 radeon_emit(cmd_buffer
->cs
, va
>> 8);
650 radeon_emit(cmd_buffer
->cs
, va
>> 40);
651 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
652 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
656 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
657 struct radv_pipeline
*pipeline
)
659 struct radv_shader_variant
*vs
;
661 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
663 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
665 if (vs
->info
.vs
.as_ls
)
666 radv_emit_hw_ls(cmd_buffer
, vs
);
667 else if (vs
->info
.vs
.as_es
)
668 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
670 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
672 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
677 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
678 struct radv_pipeline
*pipeline
)
680 if (!radv_pipeline_has_tess(pipeline
))
683 struct radv_shader_variant
*tes
, *tcs
;
685 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
686 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
688 if (tes
->info
.tes
.as_es
)
689 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
691 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
693 radv_emit_hw_hs(cmd_buffer
, tcs
);
695 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
696 pipeline
->graphics
.tess
.tf_param
);
698 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
699 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
700 pipeline
->graphics
.tess
.ls_hs_config
);
702 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
703 pipeline
->graphics
.tess
.ls_hs_config
);
705 struct ac_userdata_info
*loc
;
707 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
708 if (loc
->sgpr_idx
!= -1) {
709 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
710 assert(loc
->num_sgprs
== 4);
711 assert(!loc
->indirect
);
712 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
713 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
714 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
715 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
716 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
717 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
720 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
721 if (loc
->sgpr_idx
!= -1) {
722 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
723 assert(loc
->num_sgprs
== 1);
724 assert(!loc
->indirect
);
726 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
727 pipeline
->graphics
.tess
.offchip_layout
);
730 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
731 if (loc
->sgpr_idx
!= -1) {
732 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
733 assert(loc
->num_sgprs
== 1);
734 assert(!loc
->indirect
);
736 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
737 pipeline
->graphics
.tess
.tcs_in_layout
);
742 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
743 struct radv_pipeline
*pipeline
)
745 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
746 struct radv_shader_variant
*gs
;
749 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
751 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
755 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
757 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
758 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
759 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
760 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
762 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
764 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
766 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
767 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
768 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
769 radeon_emit(cmd_buffer
->cs
, 0);
770 radeon_emit(cmd_buffer
->cs
, 0);
771 radeon_emit(cmd_buffer
->cs
, 0);
773 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
774 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
775 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
776 S_028B90_ENABLE(gs_num_invocations
> 0));
778 va
= ws
->buffer_get_va(gs
->bo
);
779 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
780 radv_emit_prefetch(cmd_buffer
, va
, gs
->code_size
);
782 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
783 radeon_emit(cmd_buffer
->cs
, va
>> 8);
784 radeon_emit(cmd_buffer
->cs
, va
>> 40);
785 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
786 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
788 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
790 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
791 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
792 if (loc
->sgpr_idx
!= -1) {
793 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
794 uint32_t num_entries
= 64;
795 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
798 num_entries
*= stride
;
800 stride
= S_008F04_STRIDE(stride
);
801 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
802 radeon_emit(cmd_buffer
->cs
, stride
);
803 radeon_emit(cmd_buffer
->cs
, num_entries
);
808 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
809 struct radv_pipeline
*pipeline
)
811 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
812 struct radv_shader_variant
*ps
;
814 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
815 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
816 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
818 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
820 va
= ws
->buffer_get_va(ps
->bo
);
821 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
822 radv_emit_prefetch(cmd_buffer
, va
, ps
->code_size
);
824 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
825 radeon_emit(cmd_buffer
->cs
, va
>> 8);
826 radeon_emit(cmd_buffer
->cs
, va
>> 40);
827 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
828 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
830 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
831 pipeline
->graphics
.db_shader_control
);
833 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
834 ps
->config
.spi_ps_input_ena
);
836 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
837 ps
->config
.spi_ps_input_addr
);
839 if (ps
->info
.fs
.force_persample
)
840 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
842 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
843 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
845 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
847 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
848 pipeline
->graphics
.shader_z_format
);
850 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
852 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
853 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
855 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
857 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
858 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
861 if (pipeline
->graphics
.ps_input_cntl_num
) {
862 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
863 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
864 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
869 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
870 struct radv_pipeline
*pipeline
)
872 uint32_t vtx_reuse_depth
= 30;
873 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
876 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
877 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
)
878 vtx_reuse_depth
= 14;
880 radeon_set_context_reg(cmd_buffer
->cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
885 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
886 struct radv_pipeline
*pipeline
)
888 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
891 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
892 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
893 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
894 radv_update_multisample_state(cmd_buffer
, pipeline
);
895 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
896 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
897 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
898 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
899 polaris_set_vgt_vertex_reuse(cmd_buffer
, pipeline
);
901 cmd_buffer
->scratch_size_needed
=
902 MAX2(cmd_buffer
->scratch_size_needed
,
903 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
905 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
906 S_0286E8_WAVES(pipeline
->max_waves
) |
907 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
909 if (!cmd_buffer
->state
.emitted_pipeline
||
910 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
911 pipeline
->graphics
.can_use_guardband
)
912 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
914 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
916 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
917 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
919 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
921 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
923 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
927 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
929 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
930 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
934 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
936 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
937 si_write_scissors(cmd_buffer
->cs
, 0, count
,
938 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
939 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
940 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
941 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
942 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
946 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
948 struct radv_color_buffer_info
*cb
)
950 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
952 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
953 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
954 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
955 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
956 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
957 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
958 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
959 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
960 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
961 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
962 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
963 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
964 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
966 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
967 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
968 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
970 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
973 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
974 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
975 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
976 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
977 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
978 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
979 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
980 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
981 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
982 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
983 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
984 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
986 if (is_vi
) { /* DCC BASE */
987 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
993 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
994 struct radv_ds_buffer_info
*ds
,
995 struct radv_image
*image
,
996 VkImageLayout layout
)
998 uint32_t db_z_info
= ds
->db_z_info
;
999 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1001 if (!radv_layout_has_htile(image
, layout
,
1002 radv_image_queue_family_mask(image
,
1003 cmd_buffer
->queue_family_index
,
1004 cmd_buffer
->queue_family_index
))) {
1005 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1006 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1009 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1011 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1012 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1013 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1014 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1015 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1017 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1018 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1019 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1022 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1023 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1024 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1025 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1026 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1027 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1029 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1030 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1031 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1033 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1035 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1036 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1037 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1038 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1039 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1040 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1041 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1042 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1043 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1044 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1046 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1049 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1050 ds
->pa_su_poly_offset_db_fmt_cntl
);
1054 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1055 struct radv_image
*image
,
1056 VkClearDepthStencilValue ds_clear_value
,
1057 VkImageAspectFlags aspects
)
1059 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1060 va
+= image
->offset
+ image
->clear_value_offset
;
1061 unsigned reg_offset
= 0, reg_count
= 0;
1063 if (!image
->surface
.htile_size
|| !aspects
)
1066 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1072 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1075 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1077 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1078 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1079 S_370_WR_CONFIRM(1) |
1080 S_370_ENGINE_SEL(V_370_PFP
));
1081 radeon_emit(cmd_buffer
->cs
, va
);
1082 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1083 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1084 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1085 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1086 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1088 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1089 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1090 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1091 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1092 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1096 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1097 struct radv_image
*image
)
1099 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1100 va
+= image
->offset
+ image
->clear_value_offset
;
1102 if (!image
->surface
.htile_size
)
1105 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1107 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1108 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1109 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1110 COPY_DATA_COUNT_SEL
);
1111 radeon_emit(cmd_buffer
->cs
, va
);
1112 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1113 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1114 radeon_emit(cmd_buffer
->cs
, 0);
1116 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1117 radeon_emit(cmd_buffer
->cs
, 0);
1121 *with DCC some colors don't require CMASK elimiation before being
1122 * used as a texture. This sets a predicate value to determine if the
1123 * cmask eliminate is required.
1126 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1127 struct radv_image
*image
,
1130 uint64_t pred_val
= value
;
1131 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1132 va
+= image
->offset
+ image
->dcc_pred_offset
;
1134 if (!image
->surface
.dcc_size
)
1137 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1139 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1140 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1141 S_370_WR_CONFIRM(1) |
1142 S_370_ENGINE_SEL(V_370_PFP
));
1143 radeon_emit(cmd_buffer
->cs
, va
);
1144 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1145 radeon_emit(cmd_buffer
->cs
, pred_val
);
1146 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1150 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1151 struct radv_image
*image
,
1153 uint32_t color_values
[2])
1155 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1156 va
+= image
->offset
+ image
->clear_value_offset
;
1158 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1161 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1163 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1164 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1165 S_370_WR_CONFIRM(1) |
1166 S_370_ENGINE_SEL(V_370_PFP
));
1167 radeon_emit(cmd_buffer
->cs
, va
);
1168 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1169 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1170 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1172 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1173 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1174 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1178 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1179 struct radv_image
*image
,
1182 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1183 va
+= image
->offset
+ image
->clear_value_offset
;
1185 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1188 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1189 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1191 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1192 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1193 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1194 COPY_DATA_COUNT_SEL
);
1195 radeon_emit(cmd_buffer
->cs
, va
);
1196 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1197 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1198 radeon_emit(cmd_buffer
->cs
, 0);
1200 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1201 radeon_emit(cmd_buffer
->cs
, 0);
1205 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1208 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1209 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1211 for (i
= 0; i
< 8; ++i
) {
1212 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1213 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1214 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1218 int idx
= subpass
->color_attachments
[i
].attachment
;
1219 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1221 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1223 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1224 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1226 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1229 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1230 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1231 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1232 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1233 struct radv_image
*image
= att
->attachment
->image
;
1234 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1235 uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1236 cmd_buffer
->queue_family_index
,
1237 cmd_buffer
->queue_family_index
);
1238 /* We currently don't support writing decompressed HTILE */
1239 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1240 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1242 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1244 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1245 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1246 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1248 radv_load_depth_clear_regs(cmd_buffer
, image
);
1250 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1251 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1252 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1254 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1255 S_028208_BR_X(framebuffer
->width
) |
1256 S_028208_BR_Y(framebuffer
->height
));
1258 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1259 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1260 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1264 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1266 uint32_t db_count_control
;
1268 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1269 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1270 db_count_control
= 0;
1272 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1275 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1276 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1277 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1278 S_028004_ZPASS_ENABLE(1) |
1279 S_028004_SLICE_EVEN_ENABLE(1) |
1280 S_028004_SLICE_ODD_ENABLE(1);
1282 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1283 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1287 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1291 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1293 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1295 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1298 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1299 radv_emit_viewport(cmd_buffer
);
1301 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1302 radv_emit_scissor(cmd_buffer
);
1304 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1305 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1306 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1307 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1310 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
1311 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1312 radeon_emit_array(cmd_buffer
->cs
, (uint32_t*)d
->blend_constants
, 4);
1315 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1316 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1317 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1318 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028430_DB_STENCILREFMASK
, 2);
1319 radeon_emit(cmd_buffer
->cs
, S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1320 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1321 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1322 S_028430_STENCILOPVAL(1));
1323 radeon_emit(cmd_buffer
->cs
, S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1324 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1325 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1326 S_028434_STENCILOPVAL_BF(1));
1329 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1330 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)) {
1331 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(d
->depth_bounds
.min
));
1332 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(d
->depth_bounds
.max
));
1335 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1336 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)) {
1337 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1338 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1339 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1341 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1342 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1343 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1344 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1345 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1346 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1347 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1351 cmd_buffer
->state
.dirty
= 0;
1355 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1356 struct radv_pipeline
*pipeline
,
1359 gl_shader_stage stage
)
1361 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1362 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1364 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1367 assert(!desc_set_loc
->indirect
);
1368 assert(desc_set_loc
->num_sgprs
== 2);
1369 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1370 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1371 radeon_emit(cmd_buffer
->cs
, va
);
1372 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1376 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1377 VkShaderStageFlags stages
,
1378 struct radv_descriptor_set
*set
,
1381 if (cmd_buffer
->state
.pipeline
) {
1382 radv_foreach_stage(stage
, stages
) {
1383 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1384 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1390 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1391 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1393 MESA_SHADER_COMPUTE
);
1397 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1399 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1400 uint32_t *ptr
= NULL
;
1403 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, set
->size
, 32,
1408 set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1409 set
->va
+= bo_offset
;
1411 memcpy(ptr
, set
->mapped_ptr
, set
->size
);
1415 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1417 uint32_t size
= MAX_SETS
* 2 * 4;
1421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1422 256, &offset
, &ptr
))
1425 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1426 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1427 uint64_t set_va
= 0;
1428 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1431 uptr
[0] = set_va
& 0xffffffff;
1432 uptr
[1] = set_va
>> 32;
1435 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1438 if (cmd_buffer
->state
.pipeline
) {
1439 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1440 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1441 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1443 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1444 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1445 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1447 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1448 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1449 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1451 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1452 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1453 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1455 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1456 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1457 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1460 if (cmd_buffer
->state
.compute_pipeline
)
1461 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1462 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1466 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1467 VkShaderStageFlags stages
)
1471 if (!cmd_buffer
->state
.descriptors_dirty
)
1474 if (cmd_buffer
->state
.push_descriptors_dirty
)
1475 radv_flush_push_descriptors(cmd_buffer
);
1477 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1478 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1479 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1482 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1484 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1486 for (i
= 0; i
< MAX_SETS
; i
++) {
1487 if (!(cmd_buffer
->state
.descriptors_dirty
& (1u << i
)))
1489 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1493 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1495 cmd_buffer
->state
.descriptors_dirty
= 0;
1496 cmd_buffer
->state
.push_descriptors_dirty
= false;
1497 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1501 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1502 struct radv_pipeline
*pipeline
,
1503 VkShaderStageFlags stages
)
1505 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1510 stages
&= cmd_buffer
->push_constant_stages
;
1511 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1514 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1515 16 * layout
->dynamic_offset_count
,
1516 256, &offset
, &ptr
))
1519 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1520 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1521 16 * layout
->dynamic_offset_count
);
1523 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1526 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1527 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1529 radv_foreach_stage(stage
, stages
) {
1530 if (pipeline
->shaders
[stage
]) {
1531 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1532 AC_UD_PUSH_CONSTANTS
, va
);
1536 cmd_buffer
->push_constant_stages
&= ~stages
;
1537 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1540 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer
*cmd_buffer
,
1543 int32_t primitive_reset_en
= indexed_draw
&& cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
;
1545 if (primitive_reset_en
!= cmd_buffer
->state
.last_primitive_reset_en
) {
1546 cmd_buffer
->state
.last_primitive_reset_en
= primitive_reset_en
;
1547 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1548 radeon_set_uconfig_reg(cmd_buffer
->cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1549 primitive_reset_en
);
1551 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1552 primitive_reset_en
);
1556 if (primitive_reset_en
) {
1557 uint32_t primitive_reset_index
= cmd_buffer
->state
.index_type
? 0xffffffffu
: 0xffffu
;
1559 if (primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1560 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1561 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1562 primitive_reset_index
);
1568 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1570 struct radv_device
*device
= cmd_buffer
->device
;
1572 if ((cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
|| cmd_buffer
->state
.vb_dirty
) &&
1573 cmd_buffer
->state
.pipeline
->num_vertex_attribs
&&
1574 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.has_vertex_buffers
) {
1578 uint32_t num_attribs
= cmd_buffer
->state
.pipeline
->num_vertex_attribs
;
1581 /* allocate some descriptor state for vertex buffers */
1582 radv_cmd_buffer_upload_alloc(cmd_buffer
, num_attribs
* 16, 256,
1583 &vb_offset
, &vb_ptr
);
1585 for (i
= 0; i
< num_attribs
; i
++) {
1586 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1588 int vb
= cmd_buffer
->state
.pipeline
->va_binding
[i
];
1589 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1590 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1592 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1593 va
= device
->ws
->buffer_get_va(buffer
->bo
);
1595 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ cmd_buffer
->state
.pipeline
->va_offset
[i
];
1596 va
+= offset
+ buffer
->offset
;
1598 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1599 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1600 desc
[2] = (buffer
->size
- offset
- cmd_buffer
->state
.pipeline
->va_format_size
[i
]) / stride
+ 1;
1602 desc
[2] = buffer
->size
- offset
;
1603 desc
[3] = cmd_buffer
->state
.pipeline
->va_rsrc_word3
[i
];
1606 va
= device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1609 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1610 AC_UD_VS_VERTEX_BUFFERS
, va
);
1612 cmd_buffer
->state
.vb_dirty
= 0;
1616 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
,
1617 bool indexed_draw
, bool instanced_draw
,
1619 uint32_t draw_vertex_count
)
1621 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1622 uint32_t ia_multi_vgt_param
;
1624 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1625 cmd_buffer
->cs
, 4096);
1627 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
);
1629 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1630 radv_emit_graphics_pipeline(cmd_buffer
, pipeline
);
1632 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1633 radv_emit_framebuffer_state(cmd_buffer
);
1635 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
, indirect_draw
, draw_vertex_count
);
1636 if (cmd_buffer
->state
.last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1637 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1638 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
1639 else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
1640 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1642 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1643 cmd_buffer
->state
.last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1646 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1648 radv_emit_primitive_reset_state(cmd_buffer
, indexed_draw
);
1650 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1651 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1652 VK_SHADER_STAGE_ALL_GRAPHICS
);
1654 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1656 si_emit_cache_flush(cmd_buffer
);
1659 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1660 VkPipelineStageFlags src_stage_mask
)
1662 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1663 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1664 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1665 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1666 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1669 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1670 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1671 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1672 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1673 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1674 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1675 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1676 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1677 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1678 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1679 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1680 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1681 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1682 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1683 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1684 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1685 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1689 static enum radv_cmd_flush_bits
1690 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1691 VkAccessFlags src_flags
)
1693 enum radv_cmd_flush_bits flush_bits
= 0;
1695 for_each_bit(b
, src_flags
) {
1696 switch ((VkAccessFlagBits
)(1 << b
)) {
1697 case VK_ACCESS_SHADER_WRITE_BIT
:
1698 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1700 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1701 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1702 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1704 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1705 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1706 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1708 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1709 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1710 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1711 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1712 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1713 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1722 static enum radv_cmd_flush_bits
1723 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1724 VkAccessFlags dst_flags
,
1725 struct radv_image
*image
)
1727 enum radv_cmd_flush_bits flush_bits
= 0;
1729 for_each_bit(b
, dst_flags
) {
1730 switch ((VkAccessFlagBits
)(1 << b
)) {
1731 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1732 case VK_ACCESS_INDEX_READ_BIT
:
1733 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1735 case VK_ACCESS_UNIFORM_READ_BIT
:
1736 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1738 case VK_ACCESS_SHADER_READ_BIT
:
1739 case VK_ACCESS_TRANSFER_READ_BIT
:
1740 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1741 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1742 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1744 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1745 /* TODO: change to image && when the image gets passed
1746 * through from the subpass. */
1747 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1748 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1749 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1751 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1752 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1753 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1754 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1763 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1765 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1766 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1767 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1771 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1772 VkAttachmentReference att
)
1774 unsigned idx
= att
.attachment
;
1775 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1776 VkImageSubresourceRange range
;
1777 range
.aspectMask
= 0;
1778 range
.baseMipLevel
= view
->base_mip
;
1779 range
.levelCount
= 1;
1780 range
.baseArrayLayer
= view
->base_layer
;
1781 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1783 radv_handle_image_transition(cmd_buffer
,
1785 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1786 att
.layout
, 0, 0, &range
,
1787 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1789 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1795 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1796 const struct radv_subpass
*subpass
, bool transitions
)
1799 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1801 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1802 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1803 radv_handle_subpass_image_transition(cmd_buffer
,
1804 subpass
->color_attachments
[i
]);
1807 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1808 radv_handle_subpass_image_transition(cmd_buffer
,
1809 subpass
->input_attachments
[i
]);
1812 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1813 radv_handle_subpass_image_transition(cmd_buffer
,
1814 subpass
->depth_stencil_attachment
);
1818 cmd_buffer
->state
.subpass
= subpass
;
1820 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1824 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1825 struct radv_render_pass
*pass
,
1826 const VkRenderPassBeginInfo
*info
)
1828 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1830 if (pass
->attachment_count
== 0) {
1831 state
->attachments
= NULL
;
1835 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1836 pass
->attachment_count
*
1837 sizeof(state
->attachments
[0]),
1838 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1839 if (state
->attachments
== NULL
) {
1840 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1844 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1845 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1846 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1847 VkImageAspectFlags clear_aspects
= 0;
1849 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1850 /* color attachment */
1851 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1852 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1855 /* depthstencil attachment */
1856 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1857 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1858 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1859 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1860 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
1861 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1863 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1864 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1865 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1869 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1870 if (clear_aspects
&& info
) {
1871 assert(info
->clearValueCount
> i
);
1872 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1875 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1879 VkResult
radv_AllocateCommandBuffers(
1881 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1882 VkCommandBuffer
*pCommandBuffers
)
1884 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1885 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1887 VkResult result
= VK_SUCCESS
;
1890 memset(pCommandBuffers
, 0,
1891 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
1893 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1895 if (!list_empty(&pool
->free_cmd_buffers
)) {
1896 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
1898 list_del(&cmd_buffer
->pool_link
);
1899 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1901 radv_reset_cmd_buffer(cmd_buffer
);
1902 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1903 cmd_buffer
->level
= pAllocateInfo
->level
;
1905 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
1906 result
= VK_SUCCESS
;
1908 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1909 &pCommandBuffers
[i
]);
1911 if (result
!= VK_SUCCESS
)
1915 if (result
!= VK_SUCCESS
)
1916 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
1917 i
, pCommandBuffers
);
1922 void radv_FreeCommandBuffers(
1924 VkCommandPool commandPool
,
1925 uint32_t commandBufferCount
,
1926 const VkCommandBuffer
*pCommandBuffers
)
1928 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1929 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1932 if (cmd_buffer
->pool
) {
1933 list_del(&cmd_buffer
->pool_link
);
1934 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
1936 radv_cmd_buffer_destroy(cmd_buffer
);
1942 VkResult
radv_ResetCommandBuffer(
1943 VkCommandBuffer commandBuffer
,
1944 VkCommandBufferResetFlags flags
)
1946 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1947 radv_reset_cmd_buffer(cmd_buffer
);
1951 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1953 struct radv_device
*device
= cmd_buffer
->device
;
1954 if (device
->gfx_init
) {
1955 uint64_t va
= device
->ws
->buffer_get_va(device
->gfx_init
);
1956 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
1957 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1958 radeon_emit(cmd_buffer
->cs
, va
);
1959 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1960 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
1962 si_init_config(cmd_buffer
);
1965 VkResult
radv_BeginCommandBuffer(
1966 VkCommandBuffer commandBuffer
,
1967 const VkCommandBufferBeginInfo
*pBeginInfo
)
1969 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1970 radv_reset_cmd_buffer(cmd_buffer
);
1972 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1973 cmd_buffer
->state
.last_primitive_reset_en
= -1;
1975 /* setup initial configuration into command buffer */
1976 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1977 switch (cmd_buffer
->queue_family_index
) {
1978 case RADV_QUEUE_GENERAL
:
1979 emit_gfx_buffer_state(cmd_buffer
);
1980 radv_set_db_count_control(cmd_buffer
);
1982 case RADV_QUEUE_COMPUTE
:
1983 si_init_compute(cmd_buffer
);
1985 case RADV_QUEUE_TRANSFER
:
1991 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1992 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1993 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1995 struct radv_subpass
*subpass
=
1996 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1998 radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
1999 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2002 radv_cmd_buffer_trace_emit(cmd_buffer
);
2006 void radv_CmdBindVertexBuffers(
2007 VkCommandBuffer commandBuffer
,
2008 uint32_t firstBinding
,
2009 uint32_t bindingCount
,
2010 const VkBuffer
* pBuffers
,
2011 const VkDeviceSize
* pOffsets
)
2013 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2014 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2016 /* We have to defer setting up vertex buffer since we need the buffer
2017 * stride from the pipeline. */
2019 assert(firstBinding
+ bindingCount
< MAX_VBS
);
2020 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2021 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2022 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2023 cmd_buffer
->state
.vb_dirty
|= 1 << (firstBinding
+ i
);
2027 void radv_CmdBindIndexBuffer(
2028 VkCommandBuffer commandBuffer
,
2030 VkDeviceSize offset
,
2031 VkIndexType indexType
)
2033 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2034 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2036 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2037 cmd_buffer
->state
.index_va
= cmd_buffer
->device
->ws
->buffer_get_va(index_buffer
->bo
);
2038 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2040 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2041 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2042 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2043 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2047 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2048 struct radv_descriptor_set
*set
,
2051 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2053 cmd_buffer
->state
.descriptors
[idx
] = set
;
2054 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2058 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2060 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2061 if (set
->descriptors
[j
])
2062 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2065 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2068 void radv_CmdBindDescriptorSets(
2069 VkCommandBuffer commandBuffer
,
2070 VkPipelineBindPoint pipelineBindPoint
,
2071 VkPipelineLayout _layout
,
2073 uint32_t descriptorSetCount
,
2074 const VkDescriptorSet
* pDescriptorSets
,
2075 uint32_t dynamicOffsetCount
,
2076 const uint32_t* pDynamicOffsets
)
2078 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2079 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2080 unsigned dyn_idx
= 0;
2082 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2083 unsigned idx
= i
+ firstSet
;
2084 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2085 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2087 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2088 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2089 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2090 assert(dyn_idx
< dynamicOffsetCount
);
2092 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2093 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2095 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2096 dst
[2] = range
->size
;
2097 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2098 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2099 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2100 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2101 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2102 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2103 cmd_buffer
->push_constant_stages
|=
2104 set
->layout
->dynamic_shader_stages
;
2109 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2110 struct radv_descriptor_set
*set
,
2111 struct radv_descriptor_set_layout
*layout
)
2113 set
->size
= layout
->size
;
2114 set
->layout
= layout
;
2116 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2117 size_t new_size
= MAX2(set
->size
, 1024);
2118 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2119 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2121 free(set
->mapped_ptr
);
2122 set
->mapped_ptr
= malloc(new_size
);
2124 if (!set
->mapped_ptr
) {
2125 cmd_buffer
->push_descriptors
.capacity
= 0;
2126 cmd_buffer
->record_fail
= true;
2130 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2136 void radv_meta_push_descriptor_set(
2137 struct radv_cmd_buffer
* cmd_buffer
,
2138 VkPipelineBindPoint pipelineBindPoint
,
2139 VkPipelineLayout _layout
,
2141 uint32_t descriptorWriteCount
,
2142 const VkWriteDescriptorSet
* pDescriptorWrites
)
2144 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2145 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2148 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2150 push_set
->size
= layout
->set
[set
].layout
->size
;
2151 push_set
->layout
= layout
->set
[set
].layout
;
2153 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2155 (void**) &push_set
->mapped_ptr
))
2158 push_set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2159 push_set
->va
+= bo_offset
;
2161 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2162 radv_descriptor_set_to_handle(push_set
),
2163 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2165 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2166 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2169 void radv_CmdPushDescriptorSetKHR(
2170 VkCommandBuffer commandBuffer
,
2171 VkPipelineBindPoint pipelineBindPoint
,
2172 VkPipelineLayout _layout
,
2174 uint32_t descriptorWriteCount
,
2175 const VkWriteDescriptorSet
* pDescriptorWrites
)
2177 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2178 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2179 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2181 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2183 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2186 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2187 radv_descriptor_set_to_handle(push_set
),
2188 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2190 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2191 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2192 cmd_buffer
->state
.push_descriptors_dirty
= true;
2195 void radv_CmdPushDescriptorSetWithTemplateKHR(
2196 VkCommandBuffer commandBuffer
,
2197 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2198 VkPipelineLayout _layout
,
2202 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2203 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2204 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2206 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2208 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2211 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2212 descriptorUpdateTemplate
, pData
);
2214 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2215 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2216 cmd_buffer
->state
.push_descriptors_dirty
= true;
2219 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2220 VkPipelineLayout layout
,
2221 VkShaderStageFlags stageFlags
,
2224 const void* pValues
)
2226 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2227 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2228 cmd_buffer
->push_constant_stages
|= stageFlags
;
2231 VkResult
radv_EndCommandBuffer(
2232 VkCommandBuffer commandBuffer
)
2234 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2236 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
)
2237 si_emit_cache_flush(cmd_buffer
);
2239 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
) ||
2240 cmd_buffer
->record_fail
)
2241 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2246 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2248 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2249 struct radv_shader_variant
*compute_shader
;
2250 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2253 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2256 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2258 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2259 va
= ws
->buffer_get_va(compute_shader
->bo
);
2261 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2262 radv_emit_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2264 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2265 cmd_buffer
->cs
, 16);
2267 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2268 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2269 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2271 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2272 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2273 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2276 cmd_buffer
->compute_scratch_size_needed
=
2277 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2278 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2280 /* change these once we have scratch support */
2281 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2282 S_00B860_WAVES(pipeline
->max_waves
) |
2283 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2285 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2286 radeon_emit(cmd_buffer
->cs
,
2287 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2288 radeon_emit(cmd_buffer
->cs
,
2289 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2290 radeon_emit(cmd_buffer
->cs
,
2291 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2293 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2296 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2298 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2299 if (cmd_buffer
->state
.descriptors
[i
])
2300 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2304 void radv_CmdBindPipeline(
2305 VkCommandBuffer commandBuffer
,
2306 VkPipelineBindPoint pipelineBindPoint
,
2307 VkPipeline _pipeline
)
2309 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2310 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2312 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2314 switch (pipelineBindPoint
) {
2315 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2316 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2317 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2319 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2320 cmd_buffer
->state
.pipeline
= pipeline
;
2324 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2325 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2327 /* Apply the dynamic state from the pipeline */
2328 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2329 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2330 &pipeline
->dynamic_state
,
2331 pipeline
->dynamic_state_mask
);
2333 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2334 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2335 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2336 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2338 if (radv_pipeline_has_tess(pipeline
))
2339 cmd_buffer
->tess_rings_needed
= true;
2341 if (radv_pipeline_has_gs(pipeline
)) {
2342 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2343 AC_UD_SCRATCH_RING_OFFSETS
);
2344 if (cmd_buffer
->ring_offsets_idx
== -1)
2345 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2346 else if (loc
->sgpr_idx
!= -1)
2347 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2351 assert(!"invalid bind point");
2356 void radv_CmdSetViewport(
2357 VkCommandBuffer commandBuffer
,
2358 uint32_t firstViewport
,
2359 uint32_t viewportCount
,
2360 const VkViewport
* pViewports
)
2362 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2364 const uint32_t total_count
= firstViewport
+ viewportCount
;
2365 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
2366 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
2368 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2369 pViewports
, viewportCount
* sizeof(*pViewports
));
2371 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2374 void radv_CmdSetScissor(
2375 VkCommandBuffer commandBuffer
,
2376 uint32_t firstScissor
,
2377 uint32_t scissorCount
,
2378 const VkRect2D
* pScissors
)
2380 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2382 const uint32_t total_count
= firstScissor
+ scissorCount
;
2383 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
2384 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
2386 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2387 pScissors
, scissorCount
* sizeof(*pScissors
));
2388 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2391 void radv_CmdSetLineWidth(
2392 VkCommandBuffer commandBuffer
,
2395 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2396 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2397 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2400 void radv_CmdSetDepthBias(
2401 VkCommandBuffer commandBuffer
,
2402 float depthBiasConstantFactor
,
2403 float depthBiasClamp
,
2404 float depthBiasSlopeFactor
)
2406 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2408 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2409 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2410 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2412 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2415 void radv_CmdSetBlendConstants(
2416 VkCommandBuffer commandBuffer
,
2417 const float blendConstants
[4])
2419 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2421 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2422 blendConstants
, sizeof(float) * 4);
2424 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2427 void radv_CmdSetDepthBounds(
2428 VkCommandBuffer commandBuffer
,
2429 float minDepthBounds
,
2430 float maxDepthBounds
)
2432 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2434 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2435 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2437 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2440 void radv_CmdSetStencilCompareMask(
2441 VkCommandBuffer commandBuffer
,
2442 VkStencilFaceFlags faceMask
,
2443 uint32_t compareMask
)
2445 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2447 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2448 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2449 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2450 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2452 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2455 void radv_CmdSetStencilWriteMask(
2456 VkCommandBuffer commandBuffer
,
2457 VkStencilFaceFlags faceMask
,
2460 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2462 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2463 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2464 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2465 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2467 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2470 void radv_CmdSetStencilReference(
2471 VkCommandBuffer commandBuffer
,
2472 VkStencilFaceFlags faceMask
,
2475 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2477 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2478 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2479 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2480 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2482 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2485 void radv_CmdExecuteCommands(
2486 VkCommandBuffer commandBuffer
,
2487 uint32_t commandBufferCount
,
2488 const VkCommandBuffer
* pCmdBuffers
)
2490 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2492 /* Emit pending flushes on primary prior to executing secondary */
2493 si_emit_cache_flush(primary
);
2495 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2496 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2498 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2499 secondary
->scratch_size_needed
);
2500 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2501 secondary
->compute_scratch_size_needed
);
2503 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2504 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2505 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2506 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2507 if (secondary
->tess_rings_needed
)
2508 primary
->tess_rings_needed
= true;
2509 if (secondary
->sample_positions_needed
)
2510 primary
->sample_positions_needed
= true;
2512 if (secondary
->ring_offsets_idx
!= -1) {
2513 if (primary
->ring_offsets_idx
== -1)
2514 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2516 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2518 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2521 /* if we execute secondary we need to re-emit out pipelines */
2522 if (commandBufferCount
) {
2523 primary
->state
.emitted_pipeline
= NULL
;
2524 primary
->state
.emitted_compute_pipeline
= NULL
;
2525 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2526 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
2527 primary
->state
.last_primitive_reset_en
= -1;
2528 primary
->state
.last_primitive_reset_index
= 0;
2529 radv_mark_descriptor_sets_dirty(primary
);
2533 VkResult
radv_CreateCommandPool(
2535 const VkCommandPoolCreateInfo
* pCreateInfo
,
2536 const VkAllocationCallbacks
* pAllocator
,
2537 VkCommandPool
* pCmdPool
)
2539 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2540 struct radv_cmd_pool
*pool
;
2542 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2543 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2545 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2548 pool
->alloc
= *pAllocator
;
2550 pool
->alloc
= device
->alloc
;
2552 list_inithead(&pool
->cmd_buffers
);
2553 list_inithead(&pool
->free_cmd_buffers
);
2555 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2557 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2563 void radv_DestroyCommandPool(
2565 VkCommandPool commandPool
,
2566 const VkAllocationCallbacks
* pAllocator
)
2568 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2569 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2574 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2575 &pool
->cmd_buffers
, pool_link
) {
2576 radv_cmd_buffer_destroy(cmd_buffer
);
2579 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2580 &pool
->free_cmd_buffers
, pool_link
) {
2581 radv_cmd_buffer_destroy(cmd_buffer
);
2584 vk_free2(&device
->alloc
, pAllocator
, pool
);
2587 VkResult
radv_ResetCommandPool(
2589 VkCommandPool commandPool
,
2590 VkCommandPoolResetFlags flags
)
2592 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2594 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2595 &pool
->cmd_buffers
, pool_link
) {
2596 radv_reset_cmd_buffer(cmd_buffer
);
2602 void radv_TrimCommandPoolKHR(
2604 VkCommandPool commandPool
,
2605 VkCommandPoolTrimFlagsKHR flags
)
2607 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2612 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2613 &pool
->free_cmd_buffers
, pool_link
) {
2614 radv_cmd_buffer_destroy(cmd_buffer
);
2618 void radv_CmdBeginRenderPass(
2619 VkCommandBuffer commandBuffer
,
2620 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2621 VkSubpassContents contents
)
2623 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2624 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2625 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2627 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2628 cmd_buffer
->cs
, 2048);
2630 cmd_buffer
->state
.framebuffer
= framebuffer
;
2631 cmd_buffer
->state
.pass
= pass
;
2632 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2633 radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2635 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2636 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2638 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2641 void radv_CmdNextSubpass(
2642 VkCommandBuffer commandBuffer
,
2643 VkSubpassContents contents
)
2645 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2647 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2649 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2652 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2653 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2657 VkCommandBuffer commandBuffer
,
2658 uint32_t vertexCount
,
2659 uint32_t instanceCount
,
2660 uint32_t firstVertex
,
2661 uint32_t firstInstance
)
2663 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2665 radv_cmd_buffer_flush_state(cmd_buffer
, false, (instanceCount
> 1), false, vertexCount
);
2667 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
2669 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2670 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2671 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2672 radeon_emit(cmd_buffer
->cs
, firstVertex
);
2673 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2674 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2675 radeon_emit(cmd_buffer
->cs
, 0);
2677 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, cmd_buffer
->state
.predicating
));
2678 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2680 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2681 radeon_emit(cmd_buffer
->cs
, vertexCount
);
2682 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2683 S_0287F0_USE_OPAQUE(0));
2685 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2687 radv_cmd_buffer_trace_emit(cmd_buffer
);
2690 void radv_CmdDrawIndexed(
2691 VkCommandBuffer commandBuffer
,
2692 uint32_t indexCount
,
2693 uint32_t instanceCount
,
2694 uint32_t firstIndex
,
2695 int32_t vertexOffset
,
2696 uint32_t firstInstance
)
2698 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2699 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
2702 radv_cmd_buffer_flush_state(cmd_buffer
, true, (instanceCount
> 1), false, indexCount
);
2704 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
2706 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2707 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_03090C_VGT_INDEX_TYPE
,
2708 2, cmd_buffer
->state
.index_type
);
2710 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2711 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2714 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2715 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2716 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2717 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
2718 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2719 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2720 radeon_emit(cmd_buffer
->cs
, 0);
2722 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2723 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2725 index_va
= cmd_buffer
->state
.index_va
;
2726 index_va
+= firstIndex
* index_size
;
2727 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2728 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2729 radeon_emit(cmd_buffer
->cs
, index_va
);
2730 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
2731 radeon_emit(cmd_buffer
->cs
, indexCount
);
2732 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2734 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2735 radv_cmd_buffer_trace_emit(cmd_buffer
);
2739 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
2741 VkDeviceSize offset
,
2742 VkBuffer _count_buffer
,
2743 VkDeviceSize count_offset
,
2744 uint32_t draw_count
,
2748 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2749 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _count_buffer
);
2750 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2751 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2752 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2753 uint64_t indirect_va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2754 indirect_va
+= offset
+ buffer
->offset
;
2755 uint64_t count_va
= 0;
2758 count_va
= cmd_buffer
->device
->ws
->buffer_get_va(count_buffer
->bo
);
2759 count_va
+= count_offset
+ count_buffer
->offset
;
2765 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
2766 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2767 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
2770 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
2772 radeon_emit(cs
, indirect_va
);
2773 radeon_emit(cs
, indirect_va
>> 32);
2775 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2776 PKT3_DRAW_INDIRECT_MULTI
,
2779 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2780 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2781 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
2782 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2783 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2784 radeon_emit(cs
, draw_count
); /* count */
2785 radeon_emit(cs
, count_va
); /* count_addr */
2786 radeon_emit(cs
, count_va
>> 32);
2787 radeon_emit(cs
, stride
); /* stride */
2788 radeon_emit(cs
, di_src_sel
);
2789 radv_cmd_buffer_trace_emit(cmd_buffer
);
2793 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer
,
2795 VkDeviceSize offset
,
2796 VkBuffer countBuffer
,
2797 VkDeviceSize countBufferOffset
,
2798 uint32_t maxDrawCount
,
2801 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2802 radv_cmd_buffer_flush_state(cmd_buffer
, false, false, true, 0);
2804 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2805 cmd_buffer
->cs
, 14);
2807 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2808 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, false);
2810 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2814 radv_cmd_draw_indexed_indirect_count(
2815 VkCommandBuffer commandBuffer
,
2817 VkDeviceSize offset
,
2818 VkBuffer countBuffer
,
2819 VkDeviceSize countBufferOffset
,
2820 uint32_t maxDrawCount
,
2823 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2825 radv_cmd_buffer_flush_state(cmd_buffer
, true, false, true, 0);
2827 index_va
= cmd_buffer
->state
.index_va
;
2829 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 21);
2831 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2832 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2834 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2835 radeon_emit(cmd_buffer
->cs
, index_va
);
2836 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
2838 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2839 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2841 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2842 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, true);
2844 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2847 void radv_CmdDrawIndirect(
2848 VkCommandBuffer commandBuffer
,
2850 VkDeviceSize offset
,
2854 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2855 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2858 void radv_CmdDrawIndexedIndirect(
2859 VkCommandBuffer commandBuffer
,
2861 VkDeviceSize offset
,
2865 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
2866 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2869 void radv_CmdDrawIndirectCountAMD(
2870 VkCommandBuffer commandBuffer
,
2872 VkDeviceSize offset
,
2873 VkBuffer countBuffer
,
2874 VkDeviceSize countBufferOffset
,
2875 uint32_t maxDrawCount
,
2878 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2879 countBuffer
, countBufferOffset
,
2880 maxDrawCount
, stride
);
2883 void radv_CmdDrawIndexedIndirectCountAMD(
2884 VkCommandBuffer commandBuffer
,
2886 VkDeviceSize offset
,
2887 VkBuffer countBuffer
,
2888 VkDeviceSize countBufferOffset
,
2889 uint32_t maxDrawCount
,
2892 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
2893 countBuffer
, countBufferOffset
,
2894 maxDrawCount
, stride
);
2898 radv_flush_compute_state(struct radv_cmd_buffer
*cmd_buffer
)
2900 radv_emit_compute_pipeline(cmd_buffer
);
2901 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
2902 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
2903 VK_SHADER_STAGE_COMPUTE_BIT
);
2904 si_emit_cache_flush(cmd_buffer
);
2907 void radv_CmdDispatch(
2908 VkCommandBuffer commandBuffer
,
2913 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2915 radv_flush_compute_state(cmd_buffer
);
2917 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
2919 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
2920 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
2921 if (loc
->sgpr_idx
!= -1) {
2922 assert(!loc
->indirect
);
2923 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
2924 assert(loc
->num_sgprs
== grid_used
);
2925 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
2926 radeon_emit(cmd_buffer
->cs
, x
);
2928 radeon_emit(cmd_buffer
->cs
, y
);
2930 radeon_emit(cmd_buffer
->cs
, z
);
2933 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
2934 PKT3_SHADER_TYPE_S(1));
2935 radeon_emit(cmd_buffer
->cs
, x
);
2936 radeon_emit(cmd_buffer
->cs
, y
);
2937 radeon_emit(cmd_buffer
->cs
, z
);
2938 radeon_emit(cmd_buffer
->cs
, 1);
2940 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2941 radv_cmd_buffer_trace_emit(cmd_buffer
);
2944 void radv_CmdDispatchIndirect(
2945 VkCommandBuffer commandBuffer
,
2947 VkDeviceSize offset
)
2949 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2950 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2951 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2952 va
+= buffer
->offset
+ offset
;
2954 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
2956 radv_flush_compute_state(cmd_buffer
);
2958 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 25);
2959 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
2960 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
2961 if (loc
->sgpr_idx
!= -1) {
2962 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
2963 for (unsigned i
= 0; i
< grid_used
; ++i
) {
2964 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2965 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
2966 COPY_DATA_DST_SEL(COPY_DATA_REG
));
2967 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
));
2968 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
) >> 32);
2969 radeon_emit(cmd_buffer
->cs
, ((R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4) >> 2) + i
);
2970 radeon_emit(cmd_buffer
->cs
, 0);
2974 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
2975 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
2976 PKT3_SHADER_TYPE_S(1));
2977 radeon_emit(cmd_buffer
->cs
, va
);
2978 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2979 radeon_emit(cmd_buffer
->cs
, 1);
2981 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
2982 PKT3_SHADER_TYPE_S(1));
2983 radeon_emit(cmd_buffer
->cs
, 1);
2984 radeon_emit(cmd_buffer
->cs
, va
);
2985 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2987 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
2988 PKT3_SHADER_TYPE_S(1));
2989 radeon_emit(cmd_buffer
->cs
, 0);
2990 radeon_emit(cmd_buffer
->cs
, 1);
2993 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2994 radv_cmd_buffer_trace_emit(cmd_buffer
);
2997 void radv_unaligned_dispatch(
2998 struct radv_cmd_buffer
*cmd_buffer
,
3003 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3004 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3005 uint32_t blocks
[3], remainder
[3];
3007 blocks
[0] = round_up_u32(x
, compute_shader
->info
.cs
.block_size
[0]);
3008 blocks
[1] = round_up_u32(y
, compute_shader
->info
.cs
.block_size
[1]);
3009 blocks
[2] = round_up_u32(z
, compute_shader
->info
.cs
.block_size
[2]);
3011 /* If aligned, these should be an entire block size, not 0 */
3012 remainder
[0] = x
+ compute_shader
->info
.cs
.block_size
[0] - align_u32_npot(x
, compute_shader
->info
.cs
.block_size
[0]);
3013 remainder
[1] = y
+ compute_shader
->info
.cs
.block_size
[1] - align_u32_npot(y
, compute_shader
->info
.cs
.block_size
[1]);
3014 remainder
[2] = z
+ compute_shader
->info
.cs
.block_size
[2] - align_u32_npot(z
, compute_shader
->info
.cs
.block_size
[2]);
3016 radv_flush_compute_state(cmd_buffer
);
3018 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
3020 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3021 radeon_emit(cmd_buffer
->cs
,
3022 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]) |
3023 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3024 radeon_emit(cmd_buffer
->cs
,
3025 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]) |
3026 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3027 radeon_emit(cmd_buffer
->cs
,
3028 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]) |
3029 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3031 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
3032 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
3033 if (loc
->sgpr_idx
!= -1) {
3034 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
3035 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
3036 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3038 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3040 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3042 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3043 PKT3_SHADER_TYPE_S(1));
3044 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3045 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3046 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3047 radeon_emit(cmd_buffer
->cs
, S_00B800_COMPUTE_SHADER_EN(1) |
3048 S_00B800_PARTIAL_TG_EN(1));
3050 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3051 radv_cmd_buffer_trace_emit(cmd_buffer
);
3054 void radv_CmdEndRenderPass(
3055 VkCommandBuffer commandBuffer
)
3057 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3059 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3061 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3063 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3064 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3065 radv_handle_subpass_image_transition(cmd_buffer
,
3066 (VkAttachmentReference
){i
, layout
});
3069 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3071 cmd_buffer
->state
.pass
= NULL
;
3072 cmd_buffer
->state
.subpass
= NULL
;
3073 cmd_buffer
->state
.attachments
= NULL
;
3074 cmd_buffer
->state
.framebuffer
= NULL
;
3078 * For HTILE we have the following interesting clear words:
3079 * 0x0000030f: Uncompressed.
3080 * 0xfffffff0: Clear depth to 1.0
3081 * 0x00000000: Clear depth to 0.0
3083 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3084 struct radv_image
*image
,
3085 const VkImageSubresourceRange
*range
,
3086 uint32_t clear_word
)
3088 assert(range
->baseMipLevel
== 0);
3089 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3090 unsigned layer_count
= radv_get_layerCount(image
, range
);
3091 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3092 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3093 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3095 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3096 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3098 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3100 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3101 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3102 RADV_CMD_FLAG_INV_VMEM_L1
|
3103 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3106 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3107 struct radv_image
*image
,
3108 VkImageLayout src_layout
,
3109 VkImageLayout dst_layout
,
3110 unsigned src_queue_mask
,
3111 unsigned dst_queue_mask
,
3112 const VkImageSubresourceRange
*range
,
3113 VkImageAspectFlags pending_clears
)
3115 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3116 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3117 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3118 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3119 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3120 /* The clear will initialize htile. */
3122 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3123 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3124 /* TODO: merge with the clear if applicable */
3125 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3126 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3127 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3128 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3129 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3130 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3131 VkImageSubresourceRange local_range
= *range
;
3132 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3133 local_range
.baseMipLevel
= 0;
3134 local_range
.levelCount
= 1;
3136 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3137 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3139 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3141 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3142 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3146 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3147 struct radv_image
*image
, uint32_t value
)
3149 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3150 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3152 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3153 image
->cmask
.size
, value
);
3155 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3156 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3157 RADV_CMD_FLAG_INV_VMEM_L1
|
3158 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3161 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3162 struct radv_image
*image
,
3163 VkImageLayout src_layout
,
3164 VkImageLayout dst_layout
,
3165 unsigned src_queue_mask
,
3166 unsigned dst_queue_mask
,
3167 const VkImageSubresourceRange
*range
,
3168 VkImageAspectFlags pending_clears
)
3170 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3171 if (image
->fmask
.size
)
3172 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3174 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3175 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3176 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3177 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3181 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3182 struct radv_image
*image
, uint32_t value
)
3185 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3186 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3188 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3189 image
->surface
.dcc_size
, value
);
3191 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3192 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3193 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3194 RADV_CMD_FLAG_INV_VMEM_L1
|
3195 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3198 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3199 struct radv_image
*image
,
3200 VkImageLayout src_layout
,
3201 VkImageLayout dst_layout
,
3202 unsigned src_queue_mask
,
3203 unsigned dst_queue_mask
,
3204 const VkImageSubresourceRange
*range
,
3205 VkImageAspectFlags pending_clears
)
3207 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3208 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3209 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3210 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3211 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3215 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3216 struct radv_image
*image
,
3217 VkImageLayout src_layout
,
3218 VkImageLayout dst_layout
,
3219 uint32_t src_family
,
3220 uint32_t dst_family
,
3221 const VkImageSubresourceRange
*range
,
3222 VkImageAspectFlags pending_clears
)
3224 if (image
->exclusive
&& src_family
!= dst_family
) {
3225 /* This is an acquire or a release operation and there will be
3226 * a corresponding release/acquire. Do the transition in the
3227 * most flexible queue. */
3229 assert(src_family
== cmd_buffer
->queue_family_index
||
3230 dst_family
== cmd_buffer
->queue_family_index
);
3232 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3235 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3236 (src_family
== RADV_QUEUE_GENERAL
||
3237 dst_family
== RADV_QUEUE_GENERAL
))
3241 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3242 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3244 if (image
->surface
.htile_size
)
3245 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3246 dst_layout
, src_queue_mask
,
3247 dst_queue_mask
, range
,
3250 if (image
->cmask
.size
)
3251 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3252 dst_layout
, src_queue_mask
,
3253 dst_queue_mask
, range
,
3256 if (image
->surface
.dcc_size
)
3257 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3258 dst_layout
, src_queue_mask
,
3259 dst_queue_mask
, range
,
3263 void radv_CmdPipelineBarrier(
3264 VkCommandBuffer commandBuffer
,
3265 VkPipelineStageFlags srcStageMask
,
3266 VkPipelineStageFlags destStageMask
,
3268 uint32_t memoryBarrierCount
,
3269 const VkMemoryBarrier
* pMemoryBarriers
,
3270 uint32_t bufferMemoryBarrierCount
,
3271 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3272 uint32_t imageMemoryBarrierCount
,
3273 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3275 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3276 enum radv_cmd_flush_bits src_flush_bits
= 0;
3277 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3279 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3280 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3281 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3285 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3286 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3287 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3291 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3292 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3293 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3294 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3298 radv_stage_flush(cmd_buffer
, srcStageMask
);
3299 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3301 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3302 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3303 radv_handle_image_transition(cmd_buffer
, image
,
3304 pImageMemoryBarriers
[i
].oldLayout
,
3305 pImageMemoryBarriers
[i
].newLayout
,
3306 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3307 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3308 &pImageMemoryBarriers
[i
].subresourceRange
,
3312 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3316 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3317 struct radv_event
*event
,
3318 VkPipelineStageFlags stageMask
,
3321 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3322 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3324 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3326 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3328 /* TODO: this is overkill. Probably should figure something out from
3329 * the stage mask. */
3331 si_cs_emit_write_event_eop(cs
,
3332 cmd_buffer
->state
.predicating
,
3333 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3335 EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0,
3338 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3341 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3343 VkPipelineStageFlags stageMask
)
3345 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3346 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3348 write_event(cmd_buffer
, event
, stageMask
, 1);
3351 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3353 VkPipelineStageFlags stageMask
)
3355 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3356 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3358 write_event(cmd_buffer
, event
, stageMask
, 0);
3361 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3362 uint32_t eventCount
,
3363 const VkEvent
* pEvents
,
3364 VkPipelineStageFlags srcStageMask
,
3365 VkPipelineStageFlags dstStageMask
,
3366 uint32_t memoryBarrierCount
,
3367 const VkMemoryBarrier
* pMemoryBarriers
,
3368 uint32_t bufferMemoryBarrierCount
,
3369 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3370 uint32_t imageMemoryBarrierCount
,
3371 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3373 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3374 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3376 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3377 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3378 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3380 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3382 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3384 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3385 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3389 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3390 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3392 radv_handle_image_transition(cmd_buffer
, image
,
3393 pImageMemoryBarriers
[i
].oldLayout
,
3394 pImageMemoryBarriers
[i
].newLayout
,
3395 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3396 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3397 &pImageMemoryBarriers
[i
].subresourceRange
,
3401 /* TODO: figure out how to do memory barriers without waiting */
3402 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3403 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3404 RADV_CMD_FLAG_INV_VMEM_L1
|
3405 RADV_CMD_FLAG_INV_SMEM_L1
;