2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
38 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
39 struct radv_image
*image
,
40 VkImageLayout src_layout
,
41 VkImageLayout dst_layout
,
44 const VkImageSubresourceRange
*range
,
45 VkImageAspectFlags pending_clears
);
47 const struct radv_dynamic_state default_dynamic_state
= {
60 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
65 .stencil_compare_mask
= {
69 .stencil_write_mask
= {
73 .stencil_reference
= {
80 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
81 const struct radv_dynamic_state
*src
,
84 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
85 dest
->viewport
.count
= src
->viewport
.count
;
86 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
90 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
91 dest
->scissor
.count
= src
->scissor
.count
;
92 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
96 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
97 dest
->line_width
= src
->line_width
;
99 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
100 dest
->depth_bias
= src
->depth_bias
;
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
103 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
106 dest
->depth_bounds
= src
->depth_bounds
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
109 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
112 dest
->stencil_write_mask
= src
->stencil_write_mask
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
115 dest
->stencil_reference
= src
->stencil_reference
;
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
120 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
121 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
124 enum ring_type
radv_queue_family_to_ring(int f
) {
126 case RADV_QUEUE_GENERAL
:
128 case RADV_QUEUE_COMPUTE
:
130 case RADV_QUEUE_TRANSFER
:
133 unreachable("Unknown queue family");
137 static VkResult
radv_create_cmd_buffer(
138 struct radv_device
* device
,
139 struct radv_cmd_pool
* pool
,
140 VkCommandBufferLevel level
,
141 VkCommandBuffer
* pCommandBuffer
)
143 struct radv_cmd_buffer
*cmd_buffer
;
146 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
148 if (cmd_buffer
== NULL
)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
151 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
152 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
153 cmd_buffer
->device
= device
;
154 cmd_buffer
->pool
= pool
;
155 cmd_buffer
->level
= level
;
158 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
159 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
162 /* Init the pool_link so we can safefly call list_del when we destroy
165 list_inithead(&cmd_buffer
->pool_link
);
166 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
169 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
171 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
172 if (!cmd_buffer
->cs
) {
173 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
177 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
179 cmd_buffer
->upload
.offset
= 0;
180 cmd_buffer
->upload
.size
= 0;
181 list_inithead(&cmd_buffer
->upload
.list
);
186 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
194 list_del(&cmd_buffer
->pool_link
);
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
197 &cmd_buffer
->upload
.list
, list
) {
198 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
203 if (cmd_buffer
->upload
.upload_bo
)
204 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
205 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
206 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
207 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
213 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
216 &cmd_buffer
->upload
.list
, list
) {
217 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
222 cmd_buffer
->scratch_size_needed
= 0;
223 cmd_buffer
->compute_scratch_size_needed
= 0;
224 cmd_buffer
->esgs_ring_size_needed
= 0;
225 cmd_buffer
->gsvs_ring_size_needed
= 0;
226 cmd_buffer
->tess_rings_needed
= false;
227 cmd_buffer
->sample_positions_needed
= false;
229 if (cmd_buffer
->upload
.upload_bo
)
230 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
231 cmd_buffer
->upload
.upload_bo
, 8);
232 cmd_buffer
->upload
.offset
= 0;
234 cmd_buffer
->record_result
= VK_SUCCESS
;
236 cmd_buffer
->ring_offsets_idx
= -1;
238 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
240 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
241 &cmd_buffer
->gfx9_fence_offset
,
243 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
252 struct radeon_winsys_bo
*bo
;
253 struct radv_cmd_buffer_upload
*upload
;
254 struct radv_device
*device
= cmd_buffer
->device
;
256 new_size
= MAX2(min_needed
, 16 * 1024);
257 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
259 bo
= device
->ws
->buffer_create(device
->ws
,
262 RADEON_FLAG_CPU_ACCESS
);
265 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
269 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
270 if (cmd_buffer
->upload
.upload_bo
) {
271 upload
= malloc(sizeof(*upload
));
274 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
275 device
->ws
->buffer_destroy(bo
);
279 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
280 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
283 cmd_buffer
->upload
.upload_bo
= bo
;
284 cmd_buffer
->upload
.size
= new_size
;
285 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
288 if (!cmd_buffer
->upload
.map
) {
289 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
300 unsigned *out_offset
,
303 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
304 if (offset
+ size
> cmd_buffer
->upload
.size
) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
310 *out_offset
= offset
;
311 *ptr
= cmd_buffer
->upload
.map
+ offset
;
313 cmd_buffer
->upload
.offset
= offset
+ size
;
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
319 unsigned size
, unsigned alignment
,
320 const void *data
, unsigned *out_offset
)
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
325 out_offset
, (void **)&ptr
))
329 memcpy(ptr
, data
, size
);
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
336 struct radv_device
*device
= cmd_buffer
->device
;
337 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
340 if (!device
->trace_bo
)
343 va
= device
->ws
->buffer_get_va(device
->trace_bo
);
344 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
347 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
349 ++cmd_buffer
->state
.trace_id
;
350 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
351 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
352 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
353 S_370_WR_CONFIRM(1) |
354 S_370_ENGINE_SEL(V_370_ME
));
356 radeon_emit(cs
, va
>> 32);
357 radeon_emit(cs
, cmd_buffer
->state
.trace_id
);
358 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
359 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
363 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
364 struct radv_pipeline
*pipeline
)
366 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
367 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
369 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
370 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
372 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
374 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
375 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
377 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
378 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
379 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
380 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
385 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
386 struct radv_pipeline
*pipeline
)
388 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
389 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
390 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
392 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
393 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
396 /* 12.4 fixed-point */
397 static unsigned radv_pack_float_12p4(float x
)
400 x
>= 4096 ? 0xffff : x
* 16;
404 radv_shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
, bool has_tess
)
407 case MESA_SHADER_FRAGMENT
:
408 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
409 case MESA_SHADER_VERTEX
:
411 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
413 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
414 case MESA_SHADER_GEOMETRY
:
415 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
416 case MESA_SHADER_COMPUTE
:
417 return R_00B900_COMPUTE_USER_DATA_0
;
418 case MESA_SHADER_TESS_CTRL
:
419 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
420 case MESA_SHADER_TESS_EVAL
:
422 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
424 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
426 unreachable("unknown shader");
430 struct ac_userdata_info
*
431 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
432 gl_shader_stage stage
,
435 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
439 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
440 struct radv_pipeline
*pipeline
,
441 gl_shader_stage stage
,
442 int idx
, uint64_t va
)
444 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
445 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
446 if (loc
->sgpr_idx
== -1)
448 assert(loc
->num_sgprs
== 2);
449 assert(!loc
->indirect
);
450 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
451 radeon_emit(cmd_buffer
->cs
, va
);
452 radeon_emit(cmd_buffer
->cs
, va
>> 32);
456 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
457 struct radv_pipeline
*pipeline
)
459 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
460 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
461 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
463 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
464 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
465 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
467 radeon_set_context_reg(cmd_buffer
->cs
, CM_R_028804_DB_EQAA
, ms
->db_eqaa
);
468 radeon_set_context_reg(cmd_buffer
->cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
470 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
473 radeon_set_context_reg_seq(cmd_buffer
->cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
474 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
475 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
477 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
479 /* GFX9: Flush DFSM when the AA mode changes. */
480 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
481 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
482 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
484 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
486 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
487 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
488 if (loc
->sgpr_idx
== -1)
490 assert(loc
->num_sgprs
== 1);
491 assert(!loc
->indirect
);
492 switch (num_samples
) {
510 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
511 cmd_buffer
->sample_positions_needed
= true;
516 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
517 struct radv_pipeline
*pipeline
)
519 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
521 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
522 raster
->pa_cl_clip_cntl
);
524 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
525 raster
->spi_interp_control
);
527 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A00_PA_SU_POINT_SIZE
, 2);
528 unsigned tmp
= (unsigned)(1.0 * 8.0);
529 radeon_emit(cmd_buffer
->cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
530 radeon_emit(cmd_buffer
->cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
531 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
533 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
534 raster
->pa_su_vtx_cntl
);
536 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
537 raster
->pa_su_sc_mode_cntl
);
541 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
544 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
545 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
549 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
550 struct radv_pipeline
*pipeline
,
551 struct radv_shader_variant
*shader
,
552 struct ac_vs_output_info
*outinfo
)
554 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
555 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
556 unsigned export_count
;
558 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
559 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
561 export_count
= MAX2(1, outinfo
->param_exports
);
562 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
563 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
565 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
566 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
567 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
568 V_02870C_SPI_SHADER_4COMP
:
569 V_02870C_SPI_SHADER_NONE
) |
570 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
571 V_02870C_SPI_SHADER_4COMP
:
572 V_02870C_SPI_SHADER_NONE
) |
573 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
574 V_02870C_SPI_SHADER_4COMP
:
575 V_02870C_SPI_SHADER_NONE
));
578 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
579 radeon_emit(cmd_buffer
->cs
, va
>> 8);
580 radeon_emit(cmd_buffer
->cs
, va
>> 40);
581 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
582 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
584 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
585 S_028818_VTX_W0_FMT(1) |
586 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
587 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
588 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
591 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
592 pipeline
->graphics
.pa_cl_vs_out_cntl
);
594 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
595 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
596 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
600 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
601 struct radv_shader_variant
*shader
,
602 struct ac_es_output_info
*outinfo
)
604 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
605 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
607 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
608 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
610 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
611 outinfo
->esgs_itemsize
/ 4);
612 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
613 radeon_emit(cmd_buffer
->cs
, va
>> 8);
614 radeon_emit(cmd_buffer
->cs
, va
>> 40);
615 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
616 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
620 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
621 struct radv_shader_variant
*shader
)
623 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
624 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
625 uint32_t rsrc2
= shader
->rsrc2
;
627 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
628 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
630 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
631 radeon_emit(cmd_buffer
->cs
, va
>> 8);
632 radeon_emit(cmd_buffer
->cs
, va
>> 40);
634 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
635 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
636 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
637 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
639 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
640 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
641 radeon_emit(cmd_buffer
->cs
, rsrc2
);
645 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
646 struct radv_shader_variant
*shader
)
648 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
649 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
651 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
652 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
654 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
655 radeon_emit(cmd_buffer
->cs
, va
>> 8);
656 radeon_emit(cmd_buffer
->cs
, va
>> 40);
657 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
658 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
662 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
663 struct radv_pipeline
*pipeline
)
665 struct radv_shader_variant
*vs
;
667 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
669 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
671 if (vs
->info
.vs
.as_ls
)
672 radv_emit_hw_ls(cmd_buffer
, vs
);
673 else if (vs
->info
.vs
.as_es
)
674 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
676 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
678 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
683 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
684 struct radv_pipeline
*pipeline
)
686 if (!radv_pipeline_has_tess(pipeline
))
689 struct radv_shader_variant
*tes
, *tcs
;
691 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
692 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
694 if (tes
->info
.tes
.as_es
)
695 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
697 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
699 radv_emit_hw_hs(cmd_buffer
, tcs
);
701 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
702 pipeline
->graphics
.tess
.tf_param
);
704 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
705 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
706 pipeline
->graphics
.tess
.ls_hs_config
);
708 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
709 pipeline
->graphics
.tess
.ls_hs_config
);
711 struct ac_userdata_info
*loc
;
713 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
714 if (loc
->sgpr_idx
!= -1) {
715 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
716 assert(loc
->num_sgprs
== 4);
717 assert(!loc
->indirect
);
718 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
719 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
720 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
721 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
722 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
723 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
726 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
727 if (loc
->sgpr_idx
!= -1) {
728 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
729 assert(loc
->num_sgprs
== 1);
730 assert(!loc
->indirect
);
732 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
733 pipeline
->graphics
.tess
.offchip_layout
);
736 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
737 if (loc
->sgpr_idx
!= -1) {
738 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
739 assert(loc
->num_sgprs
== 1);
740 assert(!loc
->indirect
);
742 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
743 pipeline
->graphics
.tess
.tcs_in_layout
);
748 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
749 struct radv_pipeline
*pipeline
)
751 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
752 struct radv_shader_variant
*gs
;
755 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
757 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
761 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
763 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
764 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
765 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
766 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
768 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
770 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
772 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
773 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
774 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
775 radeon_emit(cmd_buffer
->cs
, 0);
776 radeon_emit(cmd_buffer
->cs
, 0);
777 radeon_emit(cmd_buffer
->cs
, 0);
779 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
780 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
781 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
782 S_028B90_ENABLE(gs_num_invocations
> 0));
784 va
= ws
->buffer_get_va(gs
->bo
) + gs
->bo_offset
;
785 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
786 radv_emit_prefetch(cmd_buffer
, va
, gs
->code_size
);
788 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
789 radeon_emit(cmd_buffer
->cs
, va
>> 8);
790 radeon_emit(cmd_buffer
->cs
, va
>> 40);
791 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
792 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
794 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
796 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
797 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
798 if (loc
->sgpr_idx
!= -1) {
799 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
800 uint32_t num_entries
= 64;
801 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
804 num_entries
*= stride
;
806 stride
= S_008F04_STRIDE(stride
);
807 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
808 radeon_emit(cmd_buffer
->cs
, stride
);
809 radeon_emit(cmd_buffer
->cs
, num_entries
);
814 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
815 struct radv_pipeline
*pipeline
)
817 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
818 struct radv_shader_variant
*ps
;
820 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
821 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
822 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
824 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
825 va
= ws
->buffer_get_va(ps
->bo
) + ps
->bo_offset
;
826 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
827 radv_emit_prefetch(cmd_buffer
, va
, ps
->code_size
);
829 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
830 radeon_emit(cmd_buffer
->cs
, va
>> 8);
831 radeon_emit(cmd_buffer
->cs
, va
>> 40);
832 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
833 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
835 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
836 pipeline
->graphics
.db_shader_control
);
838 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
839 ps
->config
.spi_ps_input_ena
);
841 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
842 ps
->config
.spi_ps_input_addr
);
844 if (ps
->info
.info
.ps
.force_persample
)
845 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
847 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
848 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
850 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
852 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
853 pipeline
->graphics
.shader_z_format
);
855 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
857 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
858 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
860 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
862 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
863 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
866 if (pipeline
->graphics
.ps_input_cntl_num
) {
867 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
868 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
869 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
874 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
875 struct radv_pipeline
*pipeline
)
877 uint32_t vtx_reuse_depth
= 30;
878 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
881 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
882 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
)
883 vtx_reuse_depth
= 14;
885 radeon_set_context_reg(cmd_buffer
->cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
890 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
891 struct radv_pipeline
*pipeline
)
893 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
896 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
897 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
898 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
899 radv_update_multisample_state(cmd_buffer
, pipeline
);
900 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
901 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
902 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
903 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
904 polaris_set_vgt_vertex_reuse(cmd_buffer
, pipeline
);
906 cmd_buffer
->scratch_size_needed
=
907 MAX2(cmd_buffer
->scratch_size_needed
,
908 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
910 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
911 S_0286E8_WAVES(pipeline
->max_waves
) |
912 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
914 if (!cmd_buffer
->state
.emitted_pipeline
||
915 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
916 pipeline
->graphics
.can_use_guardband
)
917 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
919 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
921 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
922 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
924 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
926 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
928 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
932 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
934 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
935 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
939 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
941 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
942 si_write_scissors(cmd_buffer
->cs
, 0, count
,
943 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
944 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
945 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
946 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
947 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
951 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
953 struct radv_color_buffer_info
*cb
)
955 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
957 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
958 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
959 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
960 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
961 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
962 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
963 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
964 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
965 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
966 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
967 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
968 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
969 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
971 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
972 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
973 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
975 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
978 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
979 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
980 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
981 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
982 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
983 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
984 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
985 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
986 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
987 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
988 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
989 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
991 if (is_vi
) { /* DCC BASE */
992 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
998 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
999 struct radv_ds_buffer_info
*ds
,
1000 struct radv_image
*image
,
1001 VkImageLayout layout
)
1003 uint32_t db_z_info
= ds
->db_z_info
;
1004 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1006 if (!radv_layout_has_htile(image
, layout
,
1007 radv_image_queue_family_mask(image
,
1008 cmd_buffer
->queue_family_index
,
1009 cmd_buffer
->queue_family_index
))) {
1010 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1011 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1014 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1015 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1018 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1019 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1020 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1021 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1022 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1024 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1025 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1026 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1027 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1028 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1029 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1030 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1031 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1032 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1033 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1034 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1036 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1037 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1038 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1040 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1042 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1043 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1044 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1045 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1046 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1047 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1048 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1049 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1050 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1051 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1055 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1056 ds
->pa_su_poly_offset_db_fmt_cntl
);
1060 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1061 struct radv_image
*image
,
1062 VkClearDepthStencilValue ds_clear_value
,
1063 VkImageAspectFlags aspects
)
1065 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1066 va
+= image
->offset
+ image
->clear_value_offset
;
1067 unsigned reg_offset
= 0, reg_count
= 0;
1069 if (!image
->surface
.htile_size
|| !aspects
)
1072 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1078 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1081 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1083 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1084 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1085 S_370_WR_CONFIRM(1) |
1086 S_370_ENGINE_SEL(V_370_PFP
));
1087 radeon_emit(cmd_buffer
->cs
, va
);
1088 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1089 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1090 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1091 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1092 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1094 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1095 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1096 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1097 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1098 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1102 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1103 struct radv_image
*image
)
1105 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1106 va
+= image
->offset
+ image
->clear_value_offset
;
1108 if (!image
->surface
.htile_size
)
1111 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1113 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1114 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1115 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1116 COPY_DATA_COUNT_SEL
);
1117 radeon_emit(cmd_buffer
->cs
, va
);
1118 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1119 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1120 radeon_emit(cmd_buffer
->cs
, 0);
1122 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1123 radeon_emit(cmd_buffer
->cs
, 0);
1127 *with DCC some colors don't require CMASK elimiation before being
1128 * used as a texture. This sets a predicate value to determine if the
1129 * cmask eliminate is required.
1132 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1133 struct radv_image
*image
,
1136 uint64_t pred_val
= value
;
1137 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1138 va
+= image
->offset
+ image
->dcc_pred_offset
;
1140 if (!image
->surface
.dcc_size
)
1143 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1145 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1146 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1147 S_370_WR_CONFIRM(1) |
1148 S_370_ENGINE_SEL(V_370_PFP
));
1149 radeon_emit(cmd_buffer
->cs
, va
);
1150 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1151 radeon_emit(cmd_buffer
->cs
, pred_val
);
1152 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1156 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1157 struct radv_image
*image
,
1159 uint32_t color_values
[2])
1161 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1162 va
+= image
->offset
+ image
->clear_value_offset
;
1164 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1167 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1169 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1170 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1171 S_370_WR_CONFIRM(1) |
1172 S_370_ENGINE_SEL(V_370_PFP
));
1173 radeon_emit(cmd_buffer
->cs
, va
);
1174 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1175 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1176 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1178 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1179 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1180 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1184 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1185 struct radv_image
*image
,
1188 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1189 va
+= image
->offset
+ image
->clear_value_offset
;
1191 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1194 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1195 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1197 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1198 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1199 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1200 COPY_DATA_COUNT_SEL
);
1201 radeon_emit(cmd_buffer
->cs
, va
);
1202 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1203 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1204 radeon_emit(cmd_buffer
->cs
, 0);
1206 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1207 radeon_emit(cmd_buffer
->cs
, 0);
1211 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1214 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1215 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1217 /* this may happen for inherited secondary recording */
1221 for (i
= 0; i
< 8; ++i
) {
1222 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1223 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1224 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1228 int idx
= subpass
->color_attachments
[i
].attachment
;
1229 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1231 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1233 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1234 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1236 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1239 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1240 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1241 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1242 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1243 struct radv_image
*image
= att
->attachment
->image
;
1244 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1245 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1246 cmd_buffer
->queue_family_index
,
1247 cmd_buffer
->queue_family_index
);
1248 /* We currently don't support writing decompressed HTILE */
1249 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1250 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1252 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1254 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1255 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1256 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1258 radv_load_depth_clear_regs(cmd_buffer
, image
);
1260 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1261 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1263 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1265 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1266 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1268 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1269 S_028208_BR_X(framebuffer
->width
) |
1270 S_028208_BR_Y(framebuffer
->height
));
1272 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1273 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1274 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1278 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1280 uint32_t db_count_control
;
1282 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1283 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1284 db_count_control
= 0;
1286 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1289 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1290 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1291 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1292 S_028004_ZPASS_ENABLE(1) |
1293 S_028004_SLICE_EVEN_ENABLE(1) |
1294 S_028004_SLICE_ODD_ENABLE(1);
1296 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1297 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1301 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1305 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1307 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1309 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1312 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1313 radv_emit_viewport(cmd_buffer
);
1315 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1316 radv_emit_scissor(cmd_buffer
);
1318 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1319 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1320 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1321 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1324 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
1325 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1326 radeon_emit_array(cmd_buffer
->cs
, (uint32_t*)d
->blend_constants
, 4);
1329 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1330 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1331 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1332 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028430_DB_STENCILREFMASK
, 2);
1333 radeon_emit(cmd_buffer
->cs
, S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1334 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1335 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1336 S_028430_STENCILOPVAL(1));
1337 radeon_emit(cmd_buffer
->cs
, S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1338 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1339 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1340 S_028434_STENCILOPVAL_BF(1));
1343 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1344 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)) {
1345 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(d
->depth_bounds
.min
));
1346 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(d
->depth_bounds
.max
));
1349 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1350 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)) {
1351 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1352 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1353 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1355 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1356 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1357 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1358 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1359 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1360 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1361 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1365 cmd_buffer
->state
.dirty
= 0;
1369 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1370 struct radv_pipeline
*pipeline
,
1373 gl_shader_stage stage
)
1375 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1376 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1378 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1381 assert(!desc_set_loc
->indirect
);
1382 assert(desc_set_loc
->num_sgprs
== 2);
1383 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1384 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1385 radeon_emit(cmd_buffer
->cs
, va
);
1386 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1390 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1391 VkShaderStageFlags stages
,
1392 struct radv_descriptor_set
*set
,
1395 if (cmd_buffer
->state
.pipeline
) {
1396 radv_foreach_stage(stage
, stages
) {
1397 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1398 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1404 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1405 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1407 MESA_SHADER_COMPUTE
);
1411 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1413 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1414 uint32_t *ptr
= NULL
;
1417 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, set
->size
, 32,
1422 set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1423 set
->va
+= bo_offset
;
1425 memcpy(ptr
, set
->mapped_ptr
, set
->size
);
1429 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1431 uint32_t size
= MAX_SETS
* 2 * 4;
1435 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1436 256, &offset
, &ptr
))
1439 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1440 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1441 uint64_t set_va
= 0;
1442 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1445 uptr
[0] = set_va
& 0xffffffff;
1446 uptr
[1] = set_va
>> 32;
1449 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1452 if (cmd_buffer
->state
.pipeline
) {
1453 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1454 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1455 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1457 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1458 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1459 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1461 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1462 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1463 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1465 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1466 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1467 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1469 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1470 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1471 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1474 if (cmd_buffer
->state
.compute_pipeline
)
1475 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1476 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1480 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1481 VkShaderStageFlags stages
)
1485 if (!cmd_buffer
->state
.descriptors_dirty
)
1488 if (cmd_buffer
->state
.push_descriptors_dirty
)
1489 radv_flush_push_descriptors(cmd_buffer
);
1491 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1492 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1493 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1496 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1498 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1500 for (i
= 0; i
< MAX_SETS
; i
++) {
1501 if (!(cmd_buffer
->state
.descriptors_dirty
& (1u << i
)))
1503 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1507 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1509 cmd_buffer
->state
.descriptors_dirty
= 0;
1510 cmd_buffer
->state
.push_descriptors_dirty
= false;
1511 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1515 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1516 struct radv_pipeline
*pipeline
,
1517 VkShaderStageFlags stages
)
1519 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1524 stages
&= cmd_buffer
->push_constant_stages
;
1525 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1528 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1529 16 * layout
->dynamic_offset_count
,
1530 256, &offset
, &ptr
))
1533 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1534 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1535 16 * layout
->dynamic_offset_count
);
1537 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1540 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1541 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1543 radv_foreach_stage(stage
, stages
) {
1544 if (pipeline
->shaders
[stage
]) {
1545 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1546 AC_UD_PUSH_CONSTANTS
, va
);
1550 cmd_buffer
->push_constant_stages
&= ~stages
;
1551 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1554 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer
*cmd_buffer
,
1557 int32_t primitive_reset_en
= indexed_draw
&& cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
;
1559 if (primitive_reset_en
!= cmd_buffer
->state
.last_primitive_reset_en
) {
1560 cmd_buffer
->state
.last_primitive_reset_en
= primitive_reset_en
;
1561 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1562 radeon_set_uconfig_reg(cmd_buffer
->cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1563 primitive_reset_en
);
1565 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1566 primitive_reset_en
);
1570 if (primitive_reset_en
) {
1571 uint32_t primitive_reset_index
= cmd_buffer
->state
.index_type
? 0xffffffffu
: 0xffffu
;
1573 if (primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1574 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1575 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1576 primitive_reset_index
);
1582 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1584 struct radv_device
*device
= cmd_buffer
->device
;
1586 if ((cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
|| cmd_buffer
->state
.vb_dirty
) &&
1587 cmd_buffer
->state
.pipeline
->num_vertex_attribs
&&
1588 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.has_vertex_buffers
) {
1592 uint32_t num_attribs
= cmd_buffer
->state
.pipeline
->num_vertex_attribs
;
1595 /* allocate some descriptor state for vertex buffers */
1596 radv_cmd_buffer_upload_alloc(cmd_buffer
, num_attribs
* 16, 256,
1597 &vb_offset
, &vb_ptr
);
1599 for (i
= 0; i
< num_attribs
; i
++) {
1600 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1602 int vb
= cmd_buffer
->state
.pipeline
->va_binding
[i
];
1603 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1604 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1606 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1607 va
= device
->ws
->buffer_get_va(buffer
->bo
);
1609 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ cmd_buffer
->state
.pipeline
->va_offset
[i
];
1610 va
+= offset
+ buffer
->offset
;
1612 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1613 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1614 desc
[2] = (buffer
->size
- offset
- cmd_buffer
->state
.pipeline
->va_format_size
[i
]) / stride
+ 1;
1616 desc
[2] = buffer
->size
- offset
;
1617 desc
[3] = cmd_buffer
->state
.pipeline
->va_rsrc_word3
[i
];
1620 va
= device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1623 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1624 AC_UD_VS_VERTEX_BUFFERS
, va
);
1626 cmd_buffer
->state
.vb_dirty
= false;
1630 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
,
1631 bool indexed_draw
, bool instanced_draw
,
1633 uint32_t draw_vertex_count
)
1635 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1636 uint32_t ia_multi_vgt_param
;
1638 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1639 cmd_buffer
->cs
, 4096);
1641 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
);
1643 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1644 radv_emit_graphics_pipeline(cmd_buffer
, pipeline
);
1646 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1647 radv_emit_framebuffer_state(cmd_buffer
);
1649 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
, indirect_draw
, draw_vertex_count
);
1650 if (cmd_buffer
->state
.last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1651 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1652 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
1653 else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
1654 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1656 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1657 cmd_buffer
->state
.last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1660 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1662 radv_emit_primitive_reset_state(cmd_buffer
, indexed_draw
);
1664 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1665 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1666 VK_SHADER_STAGE_ALL_GRAPHICS
);
1668 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1670 si_emit_cache_flush(cmd_buffer
);
1673 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1674 VkPipelineStageFlags src_stage_mask
)
1676 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1677 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1678 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1679 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1680 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1683 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1684 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1685 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1686 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1687 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1688 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1689 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1690 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1691 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1692 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1693 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1694 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1695 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1696 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1697 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1698 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1699 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1703 static enum radv_cmd_flush_bits
1704 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1705 VkAccessFlags src_flags
)
1707 enum radv_cmd_flush_bits flush_bits
= 0;
1709 for_each_bit(b
, src_flags
) {
1710 switch ((VkAccessFlagBits
)(1 << b
)) {
1711 case VK_ACCESS_SHADER_WRITE_BIT
:
1712 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1714 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1715 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1716 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1718 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1719 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1720 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1722 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1723 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1724 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1725 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1726 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1727 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1736 static enum radv_cmd_flush_bits
1737 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1738 VkAccessFlags dst_flags
,
1739 struct radv_image
*image
)
1741 enum radv_cmd_flush_bits flush_bits
= 0;
1743 for_each_bit(b
, dst_flags
) {
1744 switch ((VkAccessFlagBits
)(1 << b
)) {
1745 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1746 case VK_ACCESS_INDEX_READ_BIT
:
1747 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1749 case VK_ACCESS_UNIFORM_READ_BIT
:
1750 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1752 case VK_ACCESS_SHADER_READ_BIT
:
1753 case VK_ACCESS_TRANSFER_READ_BIT
:
1754 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1755 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1756 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1758 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1759 /* TODO: change to image && when the image gets passed
1760 * through from the subpass. */
1761 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1762 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1763 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1765 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1766 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1767 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1768 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1777 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1779 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1780 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1781 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1785 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1786 VkAttachmentReference att
)
1788 unsigned idx
= att
.attachment
;
1789 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1790 VkImageSubresourceRange range
;
1791 range
.aspectMask
= 0;
1792 range
.baseMipLevel
= view
->base_mip
;
1793 range
.levelCount
= 1;
1794 range
.baseArrayLayer
= view
->base_layer
;
1795 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1797 radv_handle_image_transition(cmd_buffer
,
1799 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1800 att
.layout
, 0, 0, &range
,
1801 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1803 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1809 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1810 const struct radv_subpass
*subpass
, bool transitions
)
1813 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1815 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1816 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1817 radv_handle_subpass_image_transition(cmd_buffer
,
1818 subpass
->color_attachments
[i
]);
1821 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1822 radv_handle_subpass_image_transition(cmd_buffer
,
1823 subpass
->input_attachments
[i
]);
1826 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1827 radv_handle_subpass_image_transition(cmd_buffer
,
1828 subpass
->depth_stencil_attachment
);
1832 cmd_buffer
->state
.subpass
= subpass
;
1834 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1838 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1839 struct radv_render_pass
*pass
,
1840 const VkRenderPassBeginInfo
*info
)
1842 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1844 if (pass
->attachment_count
== 0) {
1845 state
->attachments
= NULL
;
1849 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1850 pass
->attachment_count
*
1851 sizeof(state
->attachments
[0]),
1852 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1853 if (state
->attachments
== NULL
) {
1854 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1855 return cmd_buffer
->record_result
;
1858 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1859 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1860 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1861 VkImageAspectFlags clear_aspects
= 0;
1863 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1864 /* color attachment */
1865 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1866 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1869 /* depthstencil attachment */
1870 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1871 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1872 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1873 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1874 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
1875 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1877 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1878 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1879 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1883 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1884 state
->attachments
[i
].cleared_views
= 0;
1885 if (clear_aspects
&& info
) {
1886 assert(info
->clearValueCount
> i
);
1887 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1890 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1896 VkResult
radv_AllocateCommandBuffers(
1898 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1899 VkCommandBuffer
*pCommandBuffers
)
1901 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1902 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1904 VkResult result
= VK_SUCCESS
;
1907 memset(pCommandBuffers
, 0,
1908 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
1910 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1912 if (!list_empty(&pool
->free_cmd_buffers
)) {
1913 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
1915 list_del(&cmd_buffer
->pool_link
);
1916 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1918 radv_reset_cmd_buffer(cmd_buffer
);
1919 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1920 cmd_buffer
->level
= pAllocateInfo
->level
;
1922 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
1923 result
= VK_SUCCESS
;
1925 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1926 &pCommandBuffers
[i
]);
1928 if (result
!= VK_SUCCESS
)
1932 if (result
!= VK_SUCCESS
)
1933 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
1934 i
, pCommandBuffers
);
1939 void radv_FreeCommandBuffers(
1941 VkCommandPool commandPool
,
1942 uint32_t commandBufferCount
,
1943 const VkCommandBuffer
*pCommandBuffers
)
1945 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1946 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1949 if (cmd_buffer
->pool
) {
1950 list_del(&cmd_buffer
->pool_link
);
1951 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
1953 radv_cmd_buffer_destroy(cmd_buffer
);
1959 VkResult
radv_ResetCommandBuffer(
1960 VkCommandBuffer commandBuffer
,
1961 VkCommandBufferResetFlags flags
)
1963 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1964 radv_reset_cmd_buffer(cmd_buffer
);
1968 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1970 struct radv_device
*device
= cmd_buffer
->device
;
1971 if (device
->gfx_init
) {
1972 uint64_t va
= device
->ws
->buffer_get_va(device
->gfx_init
);
1973 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
1974 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1975 radeon_emit(cmd_buffer
->cs
, va
);
1976 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1977 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
1979 si_init_config(cmd_buffer
);
1982 VkResult
radv_BeginCommandBuffer(
1983 VkCommandBuffer commandBuffer
,
1984 const VkCommandBufferBeginInfo
*pBeginInfo
)
1986 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1987 VkResult result
= VK_SUCCESS
;
1989 radv_reset_cmd_buffer(cmd_buffer
);
1991 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1992 cmd_buffer
->state
.last_primitive_reset_en
= -1;
1993 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1995 /* setup initial configuration into command buffer */
1996 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1997 switch (cmd_buffer
->queue_family_index
) {
1998 case RADV_QUEUE_GENERAL
:
1999 emit_gfx_buffer_state(cmd_buffer
);
2000 radv_set_db_count_control(cmd_buffer
);
2002 case RADV_QUEUE_COMPUTE
:
2003 si_init_compute(cmd_buffer
);
2005 case RADV_QUEUE_TRANSFER
:
2011 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2012 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2013 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2015 struct radv_subpass
*subpass
=
2016 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2018 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2019 if (result
!= VK_SUCCESS
)
2022 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2025 radv_cmd_buffer_trace_emit(cmd_buffer
);
2029 void radv_CmdBindVertexBuffers(
2030 VkCommandBuffer commandBuffer
,
2031 uint32_t firstBinding
,
2032 uint32_t bindingCount
,
2033 const VkBuffer
* pBuffers
,
2034 const VkDeviceSize
* pOffsets
)
2036 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2037 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2039 /* We have to defer setting up vertex buffer since we need the buffer
2040 * stride from the pipeline. */
2042 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2043 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2044 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2045 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2048 cmd_buffer
->state
.vb_dirty
= true;
2051 void radv_CmdBindIndexBuffer(
2052 VkCommandBuffer commandBuffer
,
2054 VkDeviceSize offset
,
2055 VkIndexType indexType
)
2057 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2058 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2060 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2061 cmd_buffer
->state
.index_va
= cmd_buffer
->device
->ws
->buffer_get_va(index_buffer
->bo
);
2062 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2064 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2065 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2066 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2067 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2071 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2072 struct radv_descriptor_set
*set
,
2075 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2077 cmd_buffer
->state
.descriptors
[idx
] = set
;
2078 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2082 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2084 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2085 if (set
->descriptors
[j
])
2086 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2089 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2092 void radv_CmdBindDescriptorSets(
2093 VkCommandBuffer commandBuffer
,
2094 VkPipelineBindPoint pipelineBindPoint
,
2095 VkPipelineLayout _layout
,
2097 uint32_t descriptorSetCount
,
2098 const VkDescriptorSet
* pDescriptorSets
,
2099 uint32_t dynamicOffsetCount
,
2100 const uint32_t* pDynamicOffsets
)
2102 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2103 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2104 unsigned dyn_idx
= 0;
2106 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2107 unsigned idx
= i
+ firstSet
;
2108 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2109 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2111 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2112 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2113 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2114 assert(dyn_idx
< dynamicOffsetCount
);
2116 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2117 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2119 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2120 dst
[2] = range
->size
;
2121 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2122 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2123 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2124 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2125 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2126 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2127 cmd_buffer
->push_constant_stages
|=
2128 set
->layout
->dynamic_shader_stages
;
2133 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2134 struct radv_descriptor_set
*set
,
2135 struct radv_descriptor_set_layout
*layout
)
2137 set
->size
= layout
->size
;
2138 set
->layout
= layout
;
2140 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2141 size_t new_size
= MAX2(set
->size
, 1024);
2142 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2143 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2145 free(set
->mapped_ptr
);
2146 set
->mapped_ptr
= malloc(new_size
);
2148 if (!set
->mapped_ptr
) {
2149 cmd_buffer
->push_descriptors
.capacity
= 0;
2150 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2154 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2160 void radv_meta_push_descriptor_set(
2161 struct radv_cmd_buffer
* cmd_buffer
,
2162 VkPipelineBindPoint pipelineBindPoint
,
2163 VkPipelineLayout _layout
,
2165 uint32_t descriptorWriteCount
,
2166 const VkWriteDescriptorSet
* pDescriptorWrites
)
2168 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2169 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2173 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2175 push_set
->size
= layout
->set
[set
].layout
->size
;
2176 push_set
->layout
= layout
->set
[set
].layout
;
2178 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2180 (void**) &push_set
->mapped_ptr
))
2183 push_set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2184 push_set
->va
+= bo_offset
;
2186 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2187 radv_descriptor_set_to_handle(push_set
),
2188 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2190 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2191 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2194 void radv_CmdPushDescriptorSetKHR(
2195 VkCommandBuffer commandBuffer
,
2196 VkPipelineBindPoint pipelineBindPoint
,
2197 VkPipelineLayout _layout
,
2199 uint32_t descriptorWriteCount
,
2200 const VkWriteDescriptorSet
* pDescriptorWrites
)
2202 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2203 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2204 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2206 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2208 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2211 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2212 radv_descriptor_set_to_handle(push_set
),
2213 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2215 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2216 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2217 cmd_buffer
->state
.push_descriptors_dirty
= true;
2220 void radv_CmdPushDescriptorSetWithTemplateKHR(
2221 VkCommandBuffer commandBuffer
,
2222 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2223 VkPipelineLayout _layout
,
2227 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2228 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2229 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2231 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2233 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2236 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2237 descriptorUpdateTemplate
, pData
);
2239 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2240 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2241 cmd_buffer
->state
.push_descriptors_dirty
= true;
2244 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2245 VkPipelineLayout layout
,
2246 VkShaderStageFlags stageFlags
,
2249 const void* pValues
)
2251 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2252 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2253 cmd_buffer
->push_constant_stages
|= stageFlags
;
2256 VkResult
radv_EndCommandBuffer(
2257 VkCommandBuffer commandBuffer
)
2259 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2261 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2262 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2263 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2264 si_emit_cache_flush(cmd_buffer
);
2267 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2268 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2270 return cmd_buffer
->record_result
;
2274 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2276 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2277 struct radv_shader_variant
*compute_shader
;
2278 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2281 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2284 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2286 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2287 va
= ws
->buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2289 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2290 radv_emit_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2292 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2293 cmd_buffer
->cs
, 16);
2295 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2296 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2297 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2299 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2300 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2301 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2304 cmd_buffer
->compute_scratch_size_needed
=
2305 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2306 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2308 /* change these once we have scratch support */
2309 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2310 S_00B860_WAVES(pipeline
->max_waves
) |
2311 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2313 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2314 radeon_emit(cmd_buffer
->cs
,
2315 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2316 radeon_emit(cmd_buffer
->cs
,
2317 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2318 radeon_emit(cmd_buffer
->cs
,
2319 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2321 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2324 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2326 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2327 if (cmd_buffer
->state
.descriptors
[i
])
2328 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2332 void radv_CmdBindPipeline(
2333 VkCommandBuffer commandBuffer
,
2334 VkPipelineBindPoint pipelineBindPoint
,
2335 VkPipeline _pipeline
)
2337 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2338 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2340 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2342 switch (pipelineBindPoint
) {
2343 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2344 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2345 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2347 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2348 cmd_buffer
->state
.pipeline
= pipeline
;
2352 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2353 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2355 /* Apply the dynamic state from the pipeline */
2356 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2357 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2358 &pipeline
->dynamic_state
,
2359 pipeline
->dynamic_state_mask
);
2361 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2362 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2363 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2364 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2366 if (radv_pipeline_has_tess(pipeline
))
2367 cmd_buffer
->tess_rings_needed
= true;
2369 if (radv_pipeline_has_gs(pipeline
)) {
2370 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2371 AC_UD_SCRATCH_RING_OFFSETS
);
2372 if (cmd_buffer
->ring_offsets_idx
== -1)
2373 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2374 else if (loc
->sgpr_idx
!= -1)
2375 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2379 assert(!"invalid bind point");
2384 void radv_CmdSetViewport(
2385 VkCommandBuffer commandBuffer
,
2386 uint32_t firstViewport
,
2387 uint32_t viewportCount
,
2388 const VkViewport
* pViewports
)
2390 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2392 const uint32_t total_count
= firstViewport
+ viewportCount
;
2393 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
2394 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
2396 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2397 pViewports
, viewportCount
* sizeof(*pViewports
));
2399 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2402 void radv_CmdSetScissor(
2403 VkCommandBuffer commandBuffer
,
2404 uint32_t firstScissor
,
2405 uint32_t scissorCount
,
2406 const VkRect2D
* pScissors
)
2408 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2410 const uint32_t total_count
= firstScissor
+ scissorCount
;
2411 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
2412 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
2414 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2415 pScissors
, scissorCount
* sizeof(*pScissors
));
2416 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2419 void radv_CmdSetLineWidth(
2420 VkCommandBuffer commandBuffer
,
2423 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2424 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2425 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2428 void radv_CmdSetDepthBias(
2429 VkCommandBuffer commandBuffer
,
2430 float depthBiasConstantFactor
,
2431 float depthBiasClamp
,
2432 float depthBiasSlopeFactor
)
2434 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2436 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2437 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2438 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2440 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2443 void radv_CmdSetBlendConstants(
2444 VkCommandBuffer commandBuffer
,
2445 const float blendConstants
[4])
2447 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2449 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2450 blendConstants
, sizeof(float) * 4);
2452 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2455 void radv_CmdSetDepthBounds(
2456 VkCommandBuffer commandBuffer
,
2457 float minDepthBounds
,
2458 float maxDepthBounds
)
2460 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2462 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2463 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2465 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2468 void radv_CmdSetStencilCompareMask(
2469 VkCommandBuffer commandBuffer
,
2470 VkStencilFaceFlags faceMask
,
2471 uint32_t compareMask
)
2473 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2475 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2476 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2477 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2478 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2480 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2483 void radv_CmdSetStencilWriteMask(
2484 VkCommandBuffer commandBuffer
,
2485 VkStencilFaceFlags faceMask
,
2488 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2490 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2491 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2492 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2493 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2495 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2498 void radv_CmdSetStencilReference(
2499 VkCommandBuffer commandBuffer
,
2500 VkStencilFaceFlags faceMask
,
2503 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2505 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2506 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2507 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2508 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2510 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2513 void radv_CmdExecuteCommands(
2514 VkCommandBuffer commandBuffer
,
2515 uint32_t commandBufferCount
,
2516 const VkCommandBuffer
* pCmdBuffers
)
2518 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2520 /* Emit pending flushes on primary prior to executing secondary */
2521 si_emit_cache_flush(primary
);
2523 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2524 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2526 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2527 secondary
->scratch_size_needed
);
2528 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2529 secondary
->compute_scratch_size_needed
);
2531 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2532 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2533 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2534 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2535 if (secondary
->tess_rings_needed
)
2536 primary
->tess_rings_needed
= true;
2537 if (secondary
->sample_positions_needed
)
2538 primary
->sample_positions_needed
= true;
2540 if (secondary
->ring_offsets_idx
!= -1) {
2541 if (primary
->ring_offsets_idx
== -1)
2542 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2544 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2546 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2549 /* if we execute secondary we need to re-emit out pipelines */
2550 if (commandBufferCount
) {
2551 primary
->state
.emitted_pipeline
= NULL
;
2552 primary
->state
.emitted_compute_pipeline
= NULL
;
2553 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2554 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
2555 primary
->state
.last_primitive_reset_en
= -1;
2556 primary
->state
.last_primitive_reset_index
= 0;
2557 radv_mark_descriptor_sets_dirty(primary
);
2561 VkResult
radv_CreateCommandPool(
2563 const VkCommandPoolCreateInfo
* pCreateInfo
,
2564 const VkAllocationCallbacks
* pAllocator
,
2565 VkCommandPool
* pCmdPool
)
2567 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2568 struct radv_cmd_pool
*pool
;
2570 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2571 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2573 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2576 pool
->alloc
= *pAllocator
;
2578 pool
->alloc
= device
->alloc
;
2580 list_inithead(&pool
->cmd_buffers
);
2581 list_inithead(&pool
->free_cmd_buffers
);
2583 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2585 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2591 void radv_DestroyCommandPool(
2593 VkCommandPool commandPool
,
2594 const VkAllocationCallbacks
* pAllocator
)
2596 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2597 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2602 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2603 &pool
->cmd_buffers
, pool_link
) {
2604 radv_cmd_buffer_destroy(cmd_buffer
);
2607 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2608 &pool
->free_cmd_buffers
, pool_link
) {
2609 radv_cmd_buffer_destroy(cmd_buffer
);
2612 vk_free2(&device
->alloc
, pAllocator
, pool
);
2615 VkResult
radv_ResetCommandPool(
2617 VkCommandPool commandPool
,
2618 VkCommandPoolResetFlags flags
)
2620 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2622 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2623 &pool
->cmd_buffers
, pool_link
) {
2624 radv_reset_cmd_buffer(cmd_buffer
);
2630 void radv_TrimCommandPoolKHR(
2632 VkCommandPool commandPool
,
2633 VkCommandPoolTrimFlagsKHR flags
)
2635 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2640 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2641 &pool
->free_cmd_buffers
, pool_link
) {
2642 radv_cmd_buffer_destroy(cmd_buffer
);
2646 void radv_CmdBeginRenderPass(
2647 VkCommandBuffer commandBuffer
,
2648 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2649 VkSubpassContents contents
)
2651 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2652 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2653 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2655 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2656 cmd_buffer
->cs
, 2048);
2657 MAYBE_UNUSED VkResult result
;
2659 cmd_buffer
->state
.framebuffer
= framebuffer
;
2660 cmd_buffer
->state
.pass
= pass
;
2661 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2662 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2663 if (result
!= VK_SUCCESS
)
2664 cmd_buffer
->record_result
= result
;
2666 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2667 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2669 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2672 void radv_CmdNextSubpass(
2673 VkCommandBuffer commandBuffer
,
2674 VkSubpassContents contents
)
2676 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2678 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2680 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2683 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2684 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2687 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2689 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2690 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2691 if (!pipeline
->shaders
[stage
])
2693 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2694 if (loc
->sgpr_idx
== -1)
2696 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2697 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2700 if (pipeline
->gs_copy_shader
) {
2701 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2702 if (loc
->sgpr_idx
!= -1) {
2703 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2704 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2710 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2711 uint32_t vertex_count
)
2713 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2714 radeon_emit(cmd_buffer
->cs
, vertex_count
);
2715 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2716 S_0287F0_USE_OPAQUE(0));
2720 VkCommandBuffer commandBuffer
,
2721 uint32_t vertexCount
,
2722 uint32_t instanceCount
,
2723 uint32_t firstVertex
,
2724 uint32_t firstInstance
)
2726 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2728 radv_cmd_buffer_flush_state(cmd_buffer
, false, (instanceCount
> 1), false, vertexCount
);
2730 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 20 * MAX_VIEWS
);
2732 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2733 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2734 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2735 radeon_emit(cmd_buffer
->cs
, firstVertex
);
2736 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2737 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2738 radeon_emit(cmd_buffer
->cs
, 0);
2740 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, cmd_buffer
->state
.predicating
));
2741 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2743 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2744 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2747 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2748 radv_emit_view_index(cmd_buffer
, i
);
2750 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2754 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2756 radv_cmd_buffer_trace_emit(cmd_buffer
);
2761 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
2763 uint32_t index_count
)
2765 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2766 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2767 radeon_emit(cmd_buffer
->cs
, index_va
);
2768 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
2769 radeon_emit(cmd_buffer
->cs
, index_count
);
2770 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2773 void radv_CmdDrawIndexed(
2774 VkCommandBuffer commandBuffer
,
2775 uint32_t indexCount
,
2776 uint32_t instanceCount
,
2777 uint32_t firstIndex
,
2778 int32_t vertexOffset
,
2779 uint32_t firstInstance
)
2781 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2782 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
2785 radv_cmd_buffer_flush_state(cmd_buffer
, true, (instanceCount
> 1), false, indexCount
);
2787 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 26 * MAX_VIEWS
);
2789 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2790 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_03090C_VGT_INDEX_TYPE
,
2791 2, cmd_buffer
->state
.index_type
);
2793 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2794 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2797 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2798 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2799 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2800 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
2801 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2802 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2803 radeon_emit(cmd_buffer
->cs
, 0);
2805 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2806 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2808 index_va
= cmd_buffer
->state
.index_va
;
2809 index_va
+= firstIndex
* index_size
;
2810 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2811 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2814 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2815 radv_emit_view_index(cmd_buffer
, i
);
2817 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2821 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2822 radv_cmd_buffer_trace_emit(cmd_buffer
);
2826 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2828 uint32_t draw_count
,
2832 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2833 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2834 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2835 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2836 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
2839 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
2840 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
2841 PKT3_DRAW_INDIRECT
, 3, false));
2843 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2844 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2845 radeon_emit(cs
, di_src_sel
);
2847 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2848 PKT3_DRAW_INDIRECT_MULTI
,
2851 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2852 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2853 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
2854 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2855 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2856 radeon_emit(cs
, draw_count
); /* count */
2857 radeon_emit(cs
, count_va
); /* count_addr */
2858 radeon_emit(cs
, count_va
>> 32);
2859 radeon_emit(cs
, stride
); /* stride */
2860 radeon_emit(cs
, di_src_sel
);
2865 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
2867 VkDeviceSize offset
,
2868 VkBuffer _count_buffer
,
2869 VkDeviceSize count_offset
,
2870 uint32_t draw_count
,
2874 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2875 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _count_buffer
);
2876 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2878 uint64_t indirect_va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2879 indirect_va
+= offset
+ buffer
->offset
;
2880 uint64_t count_va
= 0;
2883 count_va
= cmd_buffer
->device
->ws
->buffer_get_va(count_buffer
->bo
);
2884 count_va
+= count_offset
+ count_buffer
->offset
;
2890 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
2892 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
2894 radeon_emit(cs
, indirect_va
);
2895 radeon_emit(cs
, indirect_va
>> 32);
2897 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2898 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
2901 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2902 radv_emit_view_index(cmd_buffer
, i
);
2904 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
2907 radv_cmd_buffer_trace_emit(cmd_buffer
);
2911 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer
,
2913 VkDeviceSize offset
,
2914 VkBuffer countBuffer
,
2915 VkDeviceSize countBufferOffset
,
2916 uint32_t maxDrawCount
,
2919 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2920 radv_cmd_buffer_flush_state(cmd_buffer
, false, false, true, 0);
2922 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2923 cmd_buffer
->cs
, 24 * MAX_VIEWS
);
2925 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2926 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, false);
2928 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2932 radv_cmd_draw_indexed_indirect_count(
2933 VkCommandBuffer commandBuffer
,
2935 VkDeviceSize offset
,
2936 VkBuffer countBuffer
,
2937 VkDeviceSize countBufferOffset
,
2938 uint32_t maxDrawCount
,
2941 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2943 radv_cmd_buffer_flush_state(cmd_buffer
, true, false, true, 0);
2945 index_va
= cmd_buffer
->state
.index_va
;
2947 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 31 * MAX_VIEWS
);
2949 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2950 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2952 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2953 radeon_emit(cmd_buffer
->cs
, index_va
);
2954 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
2956 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2957 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2959 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
2960 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, true);
2962 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2965 void radv_CmdDrawIndirect(
2966 VkCommandBuffer commandBuffer
,
2968 VkDeviceSize offset
,
2972 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2973 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2976 void radv_CmdDrawIndexedIndirect(
2977 VkCommandBuffer commandBuffer
,
2979 VkDeviceSize offset
,
2983 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
2984 VK_NULL_HANDLE
, 0, drawCount
, stride
);
2987 void radv_CmdDrawIndirectCountAMD(
2988 VkCommandBuffer commandBuffer
,
2990 VkDeviceSize offset
,
2991 VkBuffer countBuffer
,
2992 VkDeviceSize countBufferOffset
,
2993 uint32_t maxDrawCount
,
2996 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
2997 countBuffer
, countBufferOffset
,
2998 maxDrawCount
, stride
);
3001 void radv_CmdDrawIndexedIndirectCountAMD(
3002 VkCommandBuffer commandBuffer
,
3004 VkDeviceSize offset
,
3005 VkBuffer countBuffer
,
3006 VkDeviceSize countBufferOffset
,
3007 uint32_t maxDrawCount
,
3010 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
3011 countBuffer
, countBufferOffset
,
3012 maxDrawCount
, stride
);
3016 radv_flush_compute_state(struct radv_cmd_buffer
*cmd_buffer
)
3018 radv_emit_compute_pipeline(cmd_buffer
);
3019 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3020 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3021 VK_SHADER_STAGE_COMPUTE_BIT
);
3022 si_emit_cache_flush(cmd_buffer
);
3025 void radv_CmdDispatch(
3026 VkCommandBuffer commandBuffer
,
3031 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3033 radv_flush_compute_state(cmd_buffer
);
3035 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 10);
3037 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
3038 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
3039 if (loc
->sgpr_idx
!= -1) {
3040 assert(!loc
->indirect
);
3041 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
3042 assert(loc
->num_sgprs
== grid_used
);
3043 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
3044 radeon_emit(cmd_buffer
->cs
, x
);
3046 radeon_emit(cmd_buffer
->cs
, y
);
3048 radeon_emit(cmd_buffer
->cs
, z
);
3051 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3052 PKT3_SHADER_TYPE_S(1));
3053 radeon_emit(cmd_buffer
->cs
, x
);
3054 radeon_emit(cmd_buffer
->cs
, y
);
3055 radeon_emit(cmd_buffer
->cs
, z
);
3056 radeon_emit(cmd_buffer
->cs
, 1);
3058 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3059 radv_cmd_buffer_trace_emit(cmd_buffer
);
3062 void radv_CmdDispatchIndirect(
3063 VkCommandBuffer commandBuffer
,
3065 VkDeviceSize offset
)
3067 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3068 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3069 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
3070 va
+= buffer
->offset
+ offset
;
3072 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
3074 radv_flush_compute_state(cmd_buffer
);
3076 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 25);
3077 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
3078 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
3079 if (loc
->sgpr_idx
!= -1) {
3080 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
3081 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3082 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3083 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3084 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3085 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
));
3086 radeon_emit(cmd_buffer
->cs
, (va
+ 4 * i
) >> 32);
3087 radeon_emit(cmd_buffer
->cs
, ((R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4) >> 2) + i
);
3088 radeon_emit(cmd_buffer
->cs
, 0);
3092 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3093 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3094 PKT3_SHADER_TYPE_S(1));
3095 radeon_emit(cmd_buffer
->cs
, va
);
3096 radeon_emit(cmd_buffer
->cs
, va
>> 32);
3097 radeon_emit(cmd_buffer
->cs
, 1);
3099 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3100 PKT3_SHADER_TYPE_S(1));
3101 radeon_emit(cmd_buffer
->cs
, 1);
3102 radeon_emit(cmd_buffer
->cs
, va
);
3103 radeon_emit(cmd_buffer
->cs
, va
>> 32);
3105 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3106 PKT3_SHADER_TYPE_S(1));
3107 radeon_emit(cmd_buffer
->cs
, 0);
3108 radeon_emit(cmd_buffer
->cs
, 1);
3111 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3112 radv_cmd_buffer_trace_emit(cmd_buffer
);
3115 void radv_unaligned_dispatch(
3116 struct radv_cmd_buffer
*cmd_buffer
,
3121 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3122 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3123 uint32_t blocks
[3], remainder
[3];
3125 blocks
[0] = round_up_u32(x
, compute_shader
->info
.cs
.block_size
[0]);
3126 blocks
[1] = round_up_u32(y
, compute_shader
->info
.cs
.block_size
[1]);
3127 blocks
[2] = round_up_u32(z
, compute_shader
->info
.cs
.block_size
[2]);
3129 /* If aligned, these should be an entire block size, not 0 */
3130 remainder
[0] = x
+ compute_shader
->info
.cs
.block_size
[0] - align_u32_npot(x
, compute_shader
->info
.cs
.block_size
[0]);
3131 remainder
[1] = y
+ compute_shader
->info
.cs
.block_size
[1] - align_u32_npot(y
, compute_shader
->info
.cs
.block_size
[1]);
3132 remainder
[2] = z
+ compute_shader
->info
.cs
.block_size
[2] - align_u32_npot(z
, compute_shader
->info
.cs
.block_size
[2]);
3134 radv_flush_compute_state(cmd_buffer
);
3136 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 15);
3138 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3139 radeon_emit(cmd_buffer
->cs
,
3140 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]) |
3141 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3142 radeon_emit(cmd_buffer
->cs
,
3143 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]) |
3144 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3145 radeon_emit(cmd_buffer
->cs
,
3146 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]) |
3147 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3149 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.compute_pipeline
,
3150 MESA_SHADER_COMPUTE
, AC_UD_CS_GRID_SIZE
);
3151 if (loc
->sgpr_idx
!= -1) {
3152 uint8_t grid_used
= cmd_buffer
->state
.compute_pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.info
.cs
.grid_components_used
;
3153 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B900_COMPUTE_USER_DATA_0
+ loc
->sgpr_idx
* 4, grid_used
);
3154 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3156 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3158 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3160 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3161 PKT3_SHADER_TYPE_S(1));
3162 radeon_emit(cmd_buffer
->cs
, blocks
[0]);
3163 radeon_emit(cmd_buffer
->cs
, blocks
[1]);
3164 radeon_emit(cmd_buffer
->cs
, blocks
[2]);
3165 radeon_emit(cmd_buffer
->cs
, S_00B800_COMPUTE_SHADER_EN(1) |
3166 S_00B800_PARTIAL_TG_EN(1));
3168 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3169 radv_cmd_buffer_trace_emit(cmd_buffer
);
3172 void radv_CmdEndRenderPass(
3173 VkCommandBuffer commandBuffer
)
3175 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3177 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3179 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3181 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3182 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3183 radv_handle_subpass_image_transition(cmd_buffer
,
3184 (VkAttachmentReference
){i
, layout
});
3187 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3189 cmd_buffer
->state
.pass
= NULL
;
3190 cmd_buffer
->state
.subpass
= NULL
;
3191 cmd_buffer
->state
.attachments
= NULL
;
3192 cmd_buffer
->state
.framebuffer
= NULL
;
3196 * For HTILE we have the following interesting clear words:
3197 * 0x0000030f: Uncompressed.
3198 * 0xfffffff0: Clear depth to 1.0
3199 * 0x00000000: Clear depth to 0.0
3201 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3202 struct radv_image
*image
,
3203 const VkImageSubresourceRange
*range
,
3204 uint32_t clear_word
)
3206 assert(range
->baseMipLevel
== 0);
3207 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3208 unsigned layer_count
= radv_get_layerCount(image
, range
);
3209 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3210 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3211 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3213 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3214 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3216 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3218 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3219 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3220 RADV_CMD_FLAG_INV_VMEM_L1
|
3221 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3224 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3225 struct radv_image
*image
,
3226 VkImageLayout src_layout
,
3227 VkImageLayout dst_layout
,
3228 unsigned src_queue_mask
,
3229 unsigned dst_queue_mask
,
3230 const VkImageSubresourceRange
*range
,
3231 VkImageAspectFlags pending_clears
)
3233 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3234 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3235 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3236 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3237 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3238 /* The clear will initialize htile. */
3240 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3241 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3242 /* TODO: merge with the clear if applicable */
3243 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3244 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3245 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3246 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3247 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3248 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3249 VkImageSubresourceRange local_range
= *range
;
3250 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3251 local_range
.baseMipLevel
= 0;
3252 local_range
.levelCount
= 1;
3254 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3255 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3257 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3259 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3260 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3264 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3265 struct radv_image
*image
, uint32_t value
)
3267 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3268 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3270 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3271 image
->cmask
.size
, value
);
3273 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3274 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3275 RADV_CMD_FLAG_INV_VMEM_L1
|
3276 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3279 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3280 struct radv_image
*image
,
3281 VkImageLayout src_layout
,
3282 VkImageLayout dst_layout
,
3283 unsigned src_queue_mask
,
3284 unsigned dst_queue_mask
,
3285 const VkImageSubresourceRange
*range
,
3286 VkImageAspectFlags pending_clears
)
3288 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3289 if (image
->fmask
.size
)
3290 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3292 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3293 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3294 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3295 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3299 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3300 struct radv_image
*image
, uint32_t value
)
3303 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3304 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3306 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3307 image
->surface
.dcc_size
, value
);
3309 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3310 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3311 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3312 RADV_CMD_FLAG_INV_VMEM_L1
|
3313 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3316 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3317 struct radv_image
*image
,
3318 VkImageLayout src_layout
,
3319 VkImageLayout dst_layout
,
3320 unsigned src_queue_mask
,
3321 unsigned dst_queue_mask
,
3322 const VkImageSubresourceRange
*range
,
3323 VkImageAspectFlags pending_clears
)
3325 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3326 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3327 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3328 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3329 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3333 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3334 struct radv_image
*image
,
3335 VkImageLayout src_layout
,
3336 VkImageLayout dst_layout
,
3337 uint32_t src_family
,
3338 uint32_t dst_family
,
3339 const VkImageSubresourceRange
*range
,
3340 VkImageAspectFlags pending_clears
)
3342 if (image
->exclusive
&& src_family
!= dst_family
) {
3343 /* This is an acquire or a release operation and there will be
3344 * a corresponding release/acquire. Do the transition in the
3345 * most flexible queue. */
3347 assert(src_family
== cmd_buffer
->queue_family_index
||
3348 dst_family
== cmd_buffer
->queue_family_index
);
3350 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3353 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3354 (src_family
== RADV_QUEUE_GENERAL
||
3355 dst_family
== RADV_QUEUE_GENERAL
))
3359 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3360 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3362 if (image
->surface
.htile_size
)
3363 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3364 dst_layout
, src_queue_mask
,
3365 dst_queue_mask
, range
,
3368 if (image
->cmask
.size
)
3369 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3370 dst_layout
, src_queue_mask
,
3371 dst_queue_mask
, range
,
3374 if (image
->surface
.dcc_size
)
3375 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3376 dst_layout
, src_queue_mask
,
3377 dst_queue_mask
, range
,
3381 void radv_CmdPipelineBarrier(
3382 VkCommandBuffer commandBuffer
,
3383 VkPipelineStageFlags srcStageMask
,
3384 VkPipelineStageFlags destStageMask
,
3386 uint32_t memoryBarrierCount
,
3387 const VkMemoryBarrier
* pMemoryBarriers
,
3388 uint32_t bufferMemoryBarrierCount
,
3389 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3390 uint32_t imageMemoryBarrierCount
,
3391 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3393 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3394 enum radv_cmd_flush_bits src_flush_bits
= 0;
3395 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3397 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3398 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3399 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3403 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3404 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3405 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3409 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3410 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3411 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3412 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3416 radv_stage_flush(cmd_buffer
, srcStageMask
);
3417 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3419 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3420 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3421 radv_handle_image_transition(cmd_buffer
, image
,
3422 pImageMemoryBarriers
[i
].oldLayout
,
3423 pImageMemoryBarriers
[i
].newLayout
,
3424 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3425 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3426 &pImageMemoryBarriers
[i
].subresourceRange
,
3430 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3434 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3435 struct radv_event
*event
,
3436 VkPipelineStageFlags stageMask
,
3439 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3440 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3442 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3444 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3446 /* TODO: this is overkill. Probably should figure something out from
3447 * the stage mask. */
3449 si_cs_emit_write_event_eop(cs
,
3450 cmd_buffer
->state
.predicating
,
3451 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3453 EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0,
3456 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3459 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3461 VkPipelineStageFlags stageMask
)
3463 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3464 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3466 write_event(cmd_buffer
, event
, stageMask
, 1);
3469 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3471 VkPipelineStageFlags stageMask
)
3473 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3474 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3476 write_event(cmd_buffer
, event
, stageMask
, 0);
3479 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3480 uint32_t eventCount
,
3481 const VkEvent
* pEvents
,
3482 VkPipelineStageFlags srcStageMask
,
3483 VkPipelineStageFlags dstStageMask
,
3484 uint32_t memoryBarrierCount
,
3485 const VkMemoryBarrier
* pMemoryBarriers
,
3486 uint32_t bufferMemoryBarrierCount
,
3487 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3488 uint32_t imageMemoryBarrierCount
,
3489 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3491 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3492 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3494 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3495 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3496 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3498 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3500 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3502 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3503 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3507 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3508 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3510 radv_handle_image_transition(cmd_buffer
, image
,
3511 pImageMemoryBarriers
[i
].oldLayout
,
3512 pImageMemoryBarriers
[i
].newLayout
,
3513 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3514 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3515 &pImageMemoryBarriers
[i
].subresourceRange
,
3519 /* TODO: figure out how to do memory barriers without waiting */
3520 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3521 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3522 RADV_CMD_FLAG_INV_VMEM_L1
|
3523 RADV_CMD_FLAG_INV_SMEM_L1
;