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621f0bad0b11aa9b401557e12fbdb971c407e980
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
597 return;
598
599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
600 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
602
603 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
604
605 /* GFX9: Flush DFSM when the AA mode changes. */
606 if (cmd_buffer->device->dfsm_allowed) {
607 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
608 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
609 }
610 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
611 uint32_t offset;
612 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
613 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
614 if (loc->sgpr_idx == -1)
615 return;
616 assert(loc->num_sgprs == 1);
617 assert(!loc->indirect);
618 switch (num_samples) {
619 default:
620 offset = 0;
621 break;
622 case 2:
623 offset = 1;
624 break;
625 case 4:
626 offset = 3;
627 break;
628 case 8:
629 offset = 7;
630 break;
631 case 16:
632 offset = 15;
633 break;
634 }
635
636 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
637 cmd_buffer->sample_positions_needed = true;
638 }
639 }
640
641 static void
642 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline)
644 {
645 struct radv_raster_state *raster = &pipeline->graphics.raster;
646
647 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
648 raster->pa_cl_clip_cntl);
649 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
650 raster->spi_interp_control);
651 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
652 raster->pa_su_vtx_cntl);
653 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
654 raster->pa_su_sc_mode_cntl);
655 }
656
657 static inline void
658 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
659 unsigned size)
660 {
661 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
662 si_cp_dma_prefetch(cmd_buffer, va, size);
663 }
664
665 static void
666 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
667 {
668 if (cmd_buffer->state.vb_prefetch_dirty) {
669 radv_emit_prefetch_TC_L2_async(cmd_buffer,
670 cmd_buffer->state.vb_va,
671 cmd_buffer->state.vb_size);
672 cmd_buffer->state.vb_prefetch_dirty = false;
673 }
674 }
675
676 static void
677 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_shader_variant *shader)
679 {
680 struct radeon_winsys *ws = cmd_buffer->device->ws;
681 struct radeon_winsys_cs *cs = cmd_buffer->cs;
682 uint64_t va;
683
684 if (!shader)
685 return;
686
687 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
688
689 radv_cs_add_buffer(ws, cs, shader->bo, 8);
690 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
691 }
692
693 static void
694 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
695 struct radv_pipeline *pipeline)
696 {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_VERTEX]);
699 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
704 radv_emit_shader_prefetch(cmd_buffer,
705 pipeline->shaders[MESA_SHADER_GEOMETRY]);
706 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709 }
710
711 static void
712 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline,
714 struct radv_shader_variant *shader)
715 {
716 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
717
718 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
719 pipeline->graphics.vs.spi_vs_out_config);
720
721 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
722 pipeline->graphics.vs.spi_shader_pos_format);
723
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
725 radeon_emit(cmd_buffer->cs, va >> 8);
726 radeon_emit(cmd_buffer->cs, va >> 40);
727 radeon_emit(cmd_buffer->cs, shader->rsrc1);
728 radeon_emit(cmd_buffer->cs, shader->rsrc2);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
731 S_028818_VTX_W0_FMT(1) |
732 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
733 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
734 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
735
736
737 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
738 pipeline->graphics.vs.pa_cl_vs_out_cntl);
739
740 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
741 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
742 pipeline->graphics.vs.vgt_reuse_off);
743 }
744
745 static void
746 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
747 struct radv_pipeline *pipeline,
748 struct radv_shader_variant *shader)
749 {
750 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
751
752 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
753 radeon_emit(cmd_buffer->cs, va >> 8);
754 radeon_emit(cmd_buffer->cs, va >> 40);
755 radeon_emit(cmd_buffer->cs, shader->rsrc1);
756 radeon_emit(cmd_buffer->cs, shader->rsrc2);
757 }
758
759 static void
760 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_shader_variant *shader)
762 {
763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
764 uint32_t rsrc2 = shader->rsrc2;
765
766 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
767 radeon_emit(cmd_buffer->cs, va >> 8);
768 radeon_emit(cmd_buffer->cs, va >> 40);
769
770 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
771 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
772 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
773 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
774
775 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
776 radeon_emit(cmd_buffer->cs, shader->rsrc1);
777 radeon_emit(cmd_buffer->cs, rsrc2);
778 }
779
780 static void
781 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
782 struct radv_shader_variant *shader)
783 {
784 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
785
786 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
787 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
788 radeon_emit(cmd_buffer->cs, va >> 8);
789 radeon_emit(cmd_buffer->cs, va >> 40);
790
791 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
792 radeon_emit(cmd_buffer->cs, shader->rsrc1);
793 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
794 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
795 } else {
796 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
797 radeon_emit(cmd_buffer->cs, va >> 8);
798 radeon_emit(cmd_buffer->cs, va >> 40);
799 radeon_emit(cmd_buffer->cs, shader->rsrc1);
800 radeon_emit(cmd_buffer->cs, shader->rsrc2);
801 }
802 }
803
804 static void
805 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
806 struct radv_pipeline *pipeline)
807 {
808 struct radv_shader_variant *vs;
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
811
812 /* Skip shaders merged into HS/GS */
813 vs = pipeline->shaders[MESA_SHADER_VERTEX];
814 if (!vs)
815 return;
816
817 if (vs->info.vs.as_ls)
818 radv_emit_hw_ls(cmd_buffer, vs);
819 else if (vs->info.vs.as_es)
820 radv_emit_hw_es(cmd_buffer, pipeline, vs);
821 else
822 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
823 }
824
825
826 static void
827 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
828 struct radv_pipeline *pipeline)
829 {
830 if (!radv_pipeline_has_tess(pipeline))
831 return;
832
833 struct radv_shader_variant *tes, *tcs;
834
835 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
836 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
837
838 if (tes) {
839 if (tes->info.tes.as_es)
840 radv_emit_hw_es(cmd_buffer, pipeline, tes);
841 else
842 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
843 }
844
845 radv_emit_hw_hs(cmd_buffer, tcs);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
848 pipeline->graphics.tess.tf_param);
849
850 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
851 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
852 pipeline->graphics.tess.ls_hs_config);
853 else
854 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
855 pipeline->graphics.tess.ls_hs_config);
856
857 struct ac_userdata_info *loc;
858
859 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
860 if (loc->sgpr_idx != -1) {
861 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
862 assert(loc->num_sgprs == 4);
863 assert(!loc->indirect);
864 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
868 pipeline->graphics.tess.num_tcs_input_cp << 26);
869 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
870 }
871
872 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
873 if (loc->sgpr_idx != -1) {
874 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
875 assert(loc->num_sgprs == 1);
876 assert(!loc->indirect);
877
878 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
879 pipeline->graphics.tess.offchip_layout);
880 }
881
882 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
883 if (loc->sgpr_idx != -1) {
884 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
885 assert(loc->num_sgprs == 1);
886 assert(!loc->indirect);
887
888 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
889 pipeline->graphics.tess.tcs_in_layout);
890 }
891 }
892
893 static void
894 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
895 struct radv_pipeline *pipeline)
896 {
897 struct radv_shader_variant *gs;
898 uint64_t va;
899
900 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
901
902 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
903 if (!gs)
904 return;
905
906 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
907
908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
916
917 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
918 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
919 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
920 radeon_emit(cmd_buffer->cs, 0);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923
924 uint32_t gs_num_invocations = gs->info.gs.invocations;
925 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
926 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
927 S_028B90_ENABLE(gs_num_invocations > 0));
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
930 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
931
932 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
933
934 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
935 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
936 radeon_emit(cmd_buffer->cs, va >> 8);
937 radeon_emit(cmd_buffer->cs, va >> 40);
938
939 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
940 radeon_emit(cmd_buffer->cs, gs->rsrc1);
941 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
942 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
943
944 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
945 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
946 } else {
947 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
948 radeon_emit(cmd_buffer->cs, va >> 8);
949 radeon_emit(cmd_buffer->cs, va >> 40);
950 radeon_emit(cmd_buffer->cs, gs->rsrc1);
951 radeon_emit(cmd_buffer->cs, gs->rsrc2);
952 }
953
954 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
955
956 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
957 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
958 if (loc->sgpr_idx != -1) {
959 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
960 uint32_t num_entries = 64;
961 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
962
963 if (is_vi)
964 num_entries *= stride;
965
966 stride = S_008F04_STRIDE(stride);
967 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
968 radeon_emit(cmd_buffer->cs, stride);
969 radeon_emit(cmd_buffer->cs, num_entries);
970 }
971 }
972
973 static void
974 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_pipeline *pipeline)
976 {
977 struct radv_shader_variant *ps;
978 uint64_t va;
979 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
980 struct radv_blend_state *blend = &pipeline->graphics.blend;
981 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
984 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
985
986 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
987 radeon_emit(cmd_buffer->cs, va >> 8);
988 radeon_emit(cmd_buffer->cs, va >> 40);
989 radeon_emit(cmd_buffer->cs, ps->rsrc1);
990 radeon_emit(cmd_buffer->cs, ps->rsrc2);
991
992 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
993 pipeline->graphics.db_shader_control);
994
995 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
996 ps->config.spi_ps_input_ena);
997
998 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
999 ps->config.spi_ps_input_addr);
1000
1001 if (ps->info.info.ps.force_persample)
1002 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1005 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1008
1009 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1010 pipeline->graphics.shader_z_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1013
1014 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1015 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1016
1017 if (cmd_buffer->device->dfsm_allowed) {
1018 /* optimise this? */
1019 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1020 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1021 }
1022
1023 if (pipeline->graphics.ps_input_cntl_num) {
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1025 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1026 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1027 }
1028 }
1029 }
1030
1031 static void
1032 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_pipeline *pipeline)
1034 {
1035 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1036
1037 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1038 return;
1039
1040 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1041 pipeline->graphics.vtx_reuse_depth);
1042 }
1043
1044 static void
1045 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1046 {
1047 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1048
1049 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1050 return;
1051
1052 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1053 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1054 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1055 radv_update_multisample_state(cmd_buffer, pipeline);
1056 radv_emit_vertex_shader(cmd_buffer, pipeline);
1057 radv_emit_tess_shaders(cmd_buffer, pipeline);
1058 radv_emit_geometry_shader(cmd_buffer, pipeline);
1059 radv_emit_fragment_shader(cmd_buffer, pipeline);
1060 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1061
1062 cmd_buffer->scratch_size_needed =
1063 MAX2(cmd_buffer->scratch_size_needed,
1064 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1065
1066 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1067 S_0286E8_WAVES(pipeline->max_waves) |
1068 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1069
1070 if (!cmd_buffer->state.emitted_pipeline ||
1071 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1072 pipeline->graphics.can_use_guardband)
1073 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1074
1075 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1076
1077 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1078 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1079 } else {
1080 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1081 }
1082 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1083
1084 if (unlikely(cmd_buffer->device->trace_bo))
1085 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1086
1087 cmd_buffer->state.emitted_pipeline = pipeline;
1088
1089 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1090 }
1091
1092 static void
1093 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1094 {
1095 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1096 cmd_buffer->state.dynamic.viewport.viewports);
1097 }
1098
1099 static void
1100 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1101 {
1102 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1103
1104 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1105 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1106 si_emit_cache_flush(cmd_buffer);
1107 }
1108 si_write_scissors(cmd_buffer->cs, 0, count,
1109 cmd_buffer->state.dynamic.scissor.scissors,
1110 cmd_buffer->state.dynamic.viewport.viewports,
1111 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1112 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1113 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1114 }
1115
1116 static void
1117 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1120
1121 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1122 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1123 }
1124
1125 static void
1126 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1127 {
1128 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1129
1130 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1131 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1132 }
1133
1134 static void
1135 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1136 {
1137 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs,
1140 R_028430_DB_STENCILREFMASK, 2);
1141 radeon_emit(cmd_buffer->cs,
1142 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1143 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1144 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1145 S_028430_STENCILOPVAL(1));
1146 radeon_emit(cmd_buffer->cs,
1147 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1148 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1149 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1150 S_028434_STENCILOPVAL_BF(1));
1151 }
1152
1153 static void
1154 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1155 {
1156 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1157
1158 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1159 fui(d->depth_bounds.min));
1160 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1161 fui(d->depth_bounds.max));
1162 }
1163
1164 static void
1165 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1166 {
1167 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1168 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1169 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1170 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1171
1172 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1173 radeon_set_context_reg_seq(cmd_buffer->cs,
1174 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1175 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1176 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1178 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1179 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1180 }
1181 }
1182
1183 static void
1184 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1185 int index,
1186 struct radv_attachment_info *att)
1187 {
1188 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1189 struct radv_color_buffer_info *cb = &att->cb;
1190
1191 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1192 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1196 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1199 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1204
1205 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1206 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1207 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1208
1209 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1210 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1211 } else {
1212 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1216 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1219 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1223 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1224
1225 if (is_vi) { /* DCC BASE */
1226 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1227 }
1228 }
1229 }
1230
1231 static void
1232 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1233 struct radv_ds_buffer_info *ds,
1234 struct radv_image *image,
1235 VkImageLayout layout)
1236 {
1237 uint32_t db_z_info = ds->db_z_info;
1238 uint32_t db_stencil_info = ds->db_stencil_info;
1239
1240 if (!radv_layout_has_htile(image, layout,
1241 radv_image_queue_family_mask(image,
1242 cmd_buffer->queue_family_index,
1243 cmd_buffer->queue_family_index))) {
1244 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1245 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1246 }
1247
1248 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1249 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1250
1251
1252 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1254 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1255 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1256 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1257
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1259 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1260 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1261 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1263 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1265 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1267 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1269
1270 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1271 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1272 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1273 } else {
1274 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1275
1276 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1277 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1278 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1279 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1280 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1282 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1283 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1284 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1285 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1286
1287 }
1288
1289 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1290 ds->pa_su_poly_offset_db_fmt_cntl);
1291 }
1292
1293 void
1294 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 VkClearDepthStencilValue ds_clear_value,
1297 VkImageAspectFlags aspects)
1298 {
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->clear_value_offset;
1301 unsigned reg_offset = 0, reg_count = 0;
1302
1303 assert(image->surface.htile_size);
1304
1305 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1306 ++reg_count;
1307 } else {
1308 ++reg_offset;
1309 va += 4;
1310 }
1311 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1312 ++reg_count;
1313
1314 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1315 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP));
1318 radeon_emit(cmd_buffer->cs, va);
1319 radeon_emit(cmd_buffer->cs, va >> 32);
1320 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1321 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1322 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1323 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1324
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1326 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1327 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1328 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1329 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1330 }
1331
1332 static void
1333 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1334 struct radv_image *image)
1335 {
1336 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1337 uint64_t va = radv_buffer_get_va(image->bo);
1338 va += image->offset + image->clear_value_offset;
1339 unsigned reg_offset = 0, reg_count = 0;
1340
1341 if (!image->surface.htile_size)
1342 return;
1343
1344 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1345 ++reg_count;
1346 } else {
1347 ++reg_offset;
1348 va += 4;
1349 }
1350 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1351 ++reg_count;
1352
1353 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1354 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1355 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1356 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1357 radeon_emit(cmd_buffer->cs, va);
1358 radeon_emit(cmd_buffer->cs, va >> 32);
1359 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1360 radeon_emit(cmd_buffer->cs, 0);
1361
1362 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1363 radeon_emit(cmd_buffer->cs, 0);
1364 }
1365
1366 /*
1367 *with DCC some colors don't require CMASK elimiation before being
1368 * used as a texture. This sets a predicate value to determine if the
1369 * cmask eliminate is required.
1370 */
1371 void
1372 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1373 struct radv_image *image,
1374 bool value)
1375 {
1376 uint64_t pred_val = value;
1377 uint64_t va = radv_buffer_get_va(image->bo);
1378 va += image->offset + image->dcc_pred_offset;
1379
1380 if (!image->surface.dcc_size)
1381 return;
1382
1383 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1384 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1385 S_370_WR_CONFIRM(1) |
1386 S_370_ENGINE_SEL(V_370_PFP));
1387 radeon_emit(cmd_buffer->cs, va);
1388 radeon_emit(cmd_buffer->cs, va >> 32);
1389 radeon_emit(cmd_buffer->cs, pred_val);
1390 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1391 }
1392
1393 void
1394 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1395 struct radv_image *image,
1396 int idx,
1397 uint32_t color_values[2])
1398 {
1399 uint64_t va = radv_buffer_get_va(image->bo);
1400 va += image->offset + image->clear_value_offset;
1401
1402 assert(image->cmask.size || image->surface.dcc_size);
1403
1404 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1405 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1406 S_370_WR_CONFIRM(1) |
1407 S_370_ENGINE_SEL(V_370_PFP));
1408 radeon_emit(cmd_buffer->cs, va);
1409 radeon_emit(cmd_buffer->cs, va >> 32);
1410 radeon_emit(cmd_buffer->cs, color_values[0]);
1411 radeon_emit(cmd_buffer->cs, color_values[1]);
1412
1413 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1414 radeon_emit(cmd_buffer->cs, color_values[0]);
1415 radeon_emit(cmd_buffer->cs, color_values[1]);
1416 }
1417
1418 static void
1419 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1420 struct radv_image *image,
1421 int idx)
1422 {
1423 uint64_t va = radv_buffer_get_va(image->bo);
1424 va += image->offset + image->clear_value_offset;
1425
1426 if (!image->cmask.size && !image->surface.dcc_size)
1427 return;
1428
1429 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1430
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1432 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1433 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1434 COPY_DATA_COUNT_SEL);
1435 radeon_emit(cmd_buffer->cs, va);
1436 radeon_emit(cmd_buffer->cs, va >> 32);
1437 radeon_emit(cmd_buffer->cs, reg >> 2);
1438 radeon_emit(cmd_buffer->cs, 0);
1439
1440 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1441 radeon_emit(cmd_buffer->cs, 0);
1442 }
1443
1444 static void
1445 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1446 {
1447 int i;
1448 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1449 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1450
1451 /* this may happen for inherited secondary recording */
1452 if (!framebuffer)
1453 return;
1454
1455 for (i = 0; i < 8; ++i) {
1456 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1457 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1458 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1459 continue;
1460 }
1461
1462 int idx = subpass->color_attachments[i].attachment;
1463 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att);
1469
1470 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_depth_clear_regs(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 uint32_t db_count_control;
1545
1546 if(!cmd_buffer->state.active_occlusion_queries) {
1547 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1548 db_count_control = 0;
1549 } else {
1550 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1551 }
1552 } else {
1553 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1554 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1555 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1556 S_028004_ZPASS_ENABLE(1) |
1557 S_028004_SLICE_EVEN_ENABLE(1) |
1558 S_028004_SLICE_ODD_ENABLE(1);
1559 } else {
1560 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1561 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1562 }
1563 }
1564
1565 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1566 }
1567
1568 static void
1569 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1570 {
1571 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1572 return;
1573
1574 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1575 radv_emit_viewport(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1578 radv_emit_scissor(cmd_buffer);
1579
1580 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1581 radv_emit_line_width(cmd_buffer);
1582
1583 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1584 radv_emit_blend_constants(cmd_buffer);
1585
1586 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1587 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1588 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1589 radv_emit_stencil(cmd_buffer);
1590
1591 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1592 radv_emit_depth_bounds(cmd_buffer);
1593
1594 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1595 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1596 radv_emit_depth_biais(cmd_buffer);
1597
1598 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1599 }
1600
1601 static void
1602 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1603 struct radv_pipeline *pipeline,
1604 int idx,
1605 uint64_t va,
1606 gl_shader_stage stage)
1607 {
1608 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1609 uint32_t base_reg = pipeline->user_data_0[stage];
1610
1611 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1612 return;
1613
1614 assert(!desc_set_loc->indirect);
1615 assert(desc_set_loc->num_sgprs == 2);
1616 radeon_set_sh_reg_seq(cmd_buffer->cs,
1617 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1618 radeon_emit(cmd_buffer->cs, va);
1619 radeon_emit(cmd_buffer->cs, va >> 32);
1620 }
1621
1622 static void
1623 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1624 VkShaderStageFlags stages,
1625 struct radv_descriptor_set *set,
1626 unsigned idx)
1627 {
1628 if (cmd_buffer->state.pipeline) {
1629 radv_foreach_stage(stage, stages) {
1630 if (cmd_buffer->state.pipeline->shaders[stage])
1631 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1632 idx, set->va,
1633 stage);
1634 }
1635 }
1636
1637 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1638 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1639 idx, set->va,
1640 MESA_SHADER_COMPUTE);
1641 }
1642
1643 static void
1644 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1645 {
1646 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1647 unsigned bo_offset;
1648
1649 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1650 set->mapped_ptr,
1651 &bo_offset))
1652 return;
1653
1654 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1655 set->va += bo_offset;
1656 }
1657
1658 static void
1659 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1660 {
1661 uint32_t size = MAX_SETS * 2 * 4;
1662 uint32_t offset;
1663 void *ptr;
1664
1665 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1666 256, &offset, &ptr))
1667 return;
1668
1669 for (unsigned i = 0; i < MAX_SETS; i++) {
1670 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1671 uint64_t set_va = 0;
1672 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1673 if (cmd_buffer->state.valid_descriptors & (1u << i))
1674 set_va = set->va;
1675 uptr[0] = set_va & 0xffffffff;
1676 uptr[1] = set_va >> 32;
1677 }
1678
1679 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1680 va += offset;
1681
1682 if (cmd_buffer->state.pipeline) {
1683 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1684 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1685 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1686
1687 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1688 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1689 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1690
1691 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1692 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1693 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1694
1695 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1696 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1697 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1698
1699 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1700 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1701 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1702 }
1703
1704 if (cmd_buffer->state.compute_pipeline)
1705 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1706 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1707 }
1708
1709 static void
1710 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1711 VkShaderStageFlags stages)
1712 {
1713 unsigned i;
1714
1715 if (!cmd_buffer->state.descriptors_dirty)
1716 return;
1717
1718 if (cmd_buffer->state.push_descriptors_dirty)
1719 radv_flush_push_descriptors(cmd_buffer);
1720
1721 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1722 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1723 radv_flush_indirect_descriptor_sets(cmd_buffer);
1724 }
1725
1726 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1727 cmd_buffer->cs,
1728 MAX_SETS * MESA_SHADER_STAGES * 4);
1729
1730 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1731 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1732 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1733 continue;
1734
1735 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1736 }
1737 cmd_buffer->state.descriptors_dirty = 0;
1738 cmd_buffer->state.push_descriptors_dirty = false;
1739
1740 if (unlikely(cmd_buffer->device->trace_bo))
1741 radv_save_descriptors(cmd_buffer);
1742
1743 assert(cmd_buffer->cs->cdw <= cdw_max);
1744 }
1745
1746 static void
1747 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1748 struct radv_pipeline *pipeline,
1749 VkShaderStageFlags stages)
1750 {
1751 struct radv_pipeline_layout *layout = pipeline->layout;
1752 unsigned offset;
1753 void *ptr;
1754 uint64_t va;
1755
1756 stages &= cmd_buffer->push_constant_stages;
1757 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1758 return;
1759
1760 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1761 16 * layout->dynamic_offset_count,
1762 256, &offset, &ptr))
1763 return;
1764
1765 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1766 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1767 16 * layout->dynamic_offset_count);
1768
1769 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1770 va += offset;
1771
1772 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1773 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1774
1775 radv_foreach_stage(stage, stages) {
1776 if (pipeline->shaders[stage]) {
1777 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1778 AC_UD_PUSH_CONSTANTS, va);
1779 }
1780 }
1781
1782 cmd_buffer->push_constant_stages &= ~stages;
1783 assert(cmd_buffer->cs->cdw <= cdw_max);
1784 }
1785
1786 static bool
1787 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1788 {
1789 if ((pipeline_is_dirty ||
1790 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1791 cmd_buffer->state.pipeline->vertex_elements.count &&
1792 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1793 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1794 unsigned vb_offset;
1795 void *vb_ptr;
1796 uint32_t i = 0;
1797 uint32_t count = velems->count;
1798 uint64_t va;
1799
1800 /* allocate some descriptor state for vertex buffers */
1801 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1802 &vb_offset, &vb_ptr))
1803 return false;
1804
1805 for (i = 0; i < count; i++) {
1806 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1807 uint32_t offset;
1808 int vb = velems->binding[i];
1809 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1810 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1811
1812 va = radv_buffer_get_va(buffer->bo);
1813
1814 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1815 va += offset + buffer->offset;
1816 desc[0] = va;
1817 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1818 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1819 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1820 else
1821 desc[2] = buffer->size - offset;
1822 desc[3] = velems->rsrc_word3[i];
1823 }
1824
1825 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1826 va += vb_offset;
1827
1828 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1829 AC_UD_VS_VERTEX_BUFFERS, va);
1830
1831 cmd_buffer->state.vb_va = va;
1832 cmd_buffer->state.vb_size = count * 16;
1833 cmd_buffer->state.vb_prefetch_dirty = true;
1834 }
1835 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1836
1837 return true;
1838 }
1839
1840 static bool
1841 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1842 {
1843 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1844 return false;
1845
1846 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1847 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1848 VK_SHADER_STAGE_ALL_GRAPHICS);
1849
1850 return true;
1851 }
1852
1853 static void
1854 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1855 bool instanced_draw, bool indirect_draw,
1856 uint32_t draw_vertex_count)
1857 {
1858 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1859 struct radv_cmd_state *state = &cmd_buffer->state;
1860 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1861 uint32_t ia_multi_vgt_param;
1862 int32_t primitive_reset_en;
1863
1864 /* Draw state. */
1865 ia_multi_vgt_param =
1866 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1867 indirect_draw, draw_vertex_count);
1868
1869 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1870 if (info->chip_class >= GFX9) {
1871 radeon_set_uconfig_reg_idx(cs,
1872 R_030960_IA_MULTI_VGT_PARAM,
1873 4, ia_multi_vgt_param);
1874 } else if (info->chip_class >= CIK) {
1875 radeon_set_context_reg_idx(cs,
1876 R_028AA8_IA_MULTI_VGT_PARAM,
1877 1, ia_multi_vgt_param);
1878 } else {
1879 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1880 ia_multi_vgt_param);
1881 }
1882 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1883 }
1884
1885 /* Primitive restart. */
1886 primitive_reset_en =
1887 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1888
1889 if (primitive_reset_en != state->last_primitive_reset_en) {
1890 state->last_primitive_reset_en = primitive_reset_en;
1891 if (info->chip_class >= GFX9) {
1892 radeon_set_uconfig_reg(cs,
1893 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1894 primitive_reset_en);
1895 } else {
1896 radeon_set_context_reg(cs,
1897 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1898 primitive_reset_en);
1899 }
1900 }
1901
1902 if (primitive_reset_en) {
1903 uint32_t primitive_reset_index =
1904 state->index_type ? 0xffffffffu : 0xffffu;
1905
1906 if (primitive_reset_index != state->last_primitive_reset_index) {
1907 radeon_set_context_reg(cs,
1908 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1909 primitive_reset_index);
1910 state->last_primitive_reset_index = primitive_reset_index;
1911 }
1912 }
1913 }
1914
1915 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1916 VkPipelineStageFlags src_stage_mask)
1917 {
1918 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1919 VK_PIPELINE_STAGE_TRANSFER_BIT |
1920 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1921 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1922 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1923 }
1924
1925 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1926 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1927 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1928 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1929 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1930 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1931 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1932 VK_PIPELINE_STAGE_TRANSFER_BIT |
1933 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1934 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1935 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1936 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1937 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1938 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1939 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1940 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1941 }
1942 }
1943
1944 static enum radv_cmd_flush_bits
1945 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1946 VkAccessFlags src_flags)
1947 {
1948 enum radv_cmd_flush_bits flush_bits = 0;
1949 uint32_t b;
1950 for_each_bit(b, src_flags) {
1951 switch ((VkAccessFlagBits)(1 << b)) {
1952 case VK_ACCESS_SHADER_WRITE_BIT:
1953 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1954 break;
1955 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1956 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1957 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1958 break;
1959 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1960 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1961 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1962 break;
1963 case VK_ACCESS_TRANSFER_WRITE_BIT:
1964 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1965 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1966 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1967 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1968 RADV_CMD_FLAG_INV_GLOBAL_L2;
1969 break;
1970 default:
1971 break;
1972 }
1973 }
1974 return flush_bits;
1975 }
1976
1977 static enum radv_cmd_flush_bits
1978 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1979 VkAccessFlags dst_flags,
1980 struct radv_image *image)
1981 {
1982 enum radv_cmd_flush_bits flush_bits = 0;
1983 uint32_t b;
1984 for_each_bit(b, dst_flags) {
1985 switch ((VkAccessFlagBits)(1 << b)) {
1986 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1987 case VK_ACCESS_INDEX_READ_BIT:
1988 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1989 break;
1990 case VK_ACCESS_UNIFORM_READ_BIT:
1991 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1992 break;
1993 case VK_ACCESS_SHADER_READ_BIT:
1994 case VK_ACCESS_TRANSFER_READ_BIT:
1995 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1996 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1997 RADV_CMD_FLAG_INV_GLOBAL_L2;
1998 break;
1999 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2000 /* TODO: change to image && when the image gets passed
2001 * through from the subpass. */
2002 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2003 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2004 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2005 break;
2006 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2007 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2008 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2009 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2010 break;
2011 default:
2012 break;
2013 }
2014 }
2015 return flush_bits;
2016 }
2017
2018 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2019 {
2020 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2021 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2022 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2023 NULL);
2024 }
2025
2026 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2027 VkAttachmentReference att)
2028 {
2029 unsigned idx = att.attachment;
2030 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2031 VkImageSubresourceRange range;
2032 range.aspectMask = 0;
2033 range.baseMipLevel = view->base_mip;
2034 range.levelCount = 1;
2035 range.baseArrayLayer = view->base_layer;
2036 range.layerCount = cmd_buffer->state.framebuffer->layers;
2037
2038 radv_handle_image_transition(cmd_buffer,
2039 view->image,
2040 cmd_buffer->state.attachments[idx].current_layout,
2041 att.layout, 0, 0, &range,
2042 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2043
2044 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2045
2046
2047 }
2048
2049 void
2050 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2051 const struct radv_subpass *subpass, bool transitions)
2052 {
2053 if (transitions) {
2054 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2055
2056 for (unsigned i = 0; i < subpass->color_count; ++i) {
2057 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2058 radv_handle_subpass_image_transition(cmd_buffer,
2059 subpass->color_attachments[i]);
2060 }
2061
2062 for (unsigned i = 0; i < subpass->input_count; ++i) {
2063 radv_handle_subpass_image_transition(cmd_buffer,
2064 subpass->input_attachments[i]);
2065 }
2066
2067 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2068 radv_handle_subpass_image_transition(cmd_buffer,
2069 subpass->depth_stencil_attachment);
2070 }
2071 }
2072
2073 cmd_buffer->state.subpass = subpass;
2074
2075 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2076 }
2077
2078 static VkResult
2079 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2080 struct radv_render_pass *pass,
2081 const VkRenderPassBeginInfo *info)
2082 {
2083 struct radv_cmd_state *state = &cmd_buffer->state;
2084
2085 if (pass->attachment_count == 0) {
2086 state->attachments = NULL;
2087 return VK_SUCCESS;
2088 }
2089
2090 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2091 pass->attachment_count *
2092 sizeof(state->attachments[0]),
2093 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2094 if (state->attachments == NULL) {
2095 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2096 return cmd_buffer->record_result;
2097 }
2098
2099 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2100 struct radv_render_pass_attachment *att = &pass->attachments[i];
2101 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2102 VkImageAspectFlags clear_aspects = 0;
2103
2104 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2105 /* color attachment */
2106 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2107 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2108 }
2109 } else {
2110 /* depthstencil attachment */
2111 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2112 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2113 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2114 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2115 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2116 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2117 }
2118 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2119 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2120 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2121 }
2122 }
2123
2124 state->attachments[i].pending_clear_aspects = clear_aspects;
2125 state->attachments[i].cleared_views = 0;
2126 if (clear_aspects && info) {
2127 assert(info->clearValueCount > i);
2128 state->attachments[i].clear_value = info->pClearValues[i];
2129 }
2130
2131 state->attachments[i].current_layout = att->initial_layout;
2132 }
2133
2134 return VK_SUCCESS;
2135 }
2136
2137 VkResult radv_AllocateCommandBuffers(
2138 VkDevice _device,
2139 const VkCommandBufferAllocateInfo *pAllocateInfo,
2140 VkCommandBuffer *pCommandBuffers)
2141 {
2142 RADV_FROM_HANDLE(radv_device, device, _device);
2143 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2144
2145 VkResult result = VK_SUCCESS;
2146 uint32_t i;
2147
2148 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2149
2150 if (!list_empty(&pool->free_cmd_buffers)) {
2151 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2152
2153 list_del(&cmd_buffer->pool_link);
2154 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2155
2156 result = radv_reset_cmd_buffer(cmd_buffer);
2157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2158 cmd_buffer->level = pAllocateInfo->level;
2159
2160 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2161 } else {
2162 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2163 &pCommandBuffers[i]);
2164 }
2165 if (result != VK_SUCCESS)
2166 break;
2167 }
2168
2169 if (result != VK_SUCCESS) {
2170 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2171 i, pCommandBuffers);
2172
2173 /* From the Vulkan 1.0.66 spec:
2174 *
2175 * "vkAllocateCommandBuffers can be used to create multiple
2176 * command buffers. If the creation of any of those command
2177 * buffers fails, the implementation must destroy all
2178 * successfully created command buffer objects from this
2179 * command, set all entries of the pCommandBuffers array to
2180 * NULL and return the error."
2181 */
2182 memset(pCommandBuffers, 0,
2183 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2184 }
2185
2186 return result;
2187 }
2188
2189 void radv_FreeCommandBuffers(
2190 VkDevice device,
2191 VkCommandPool commandPool,
2192 uint32_t commandBufferCount,
2193 const VkCommandBuffer *pCommandBuffers)
2194 {
2195 for (uint32_t i = 0; i < commandBufferCount; i++) {
2196 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2197
2198 if (cmd_buffer) {
2199 if (cmd_buffer->pool) {
2200 list_del(&cmd_buffer->pool_link);
2201 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2202 } else
2203 radv_cmd_buffer_destroy(cmd_buffer);
2204
2205 }
2206 }
2207 }
2208
2209 VkResult radv_ResetCommandBuffer(
2210 VkCommandBuffer commandBuffer,
2211 VkCommandBufferResetFlags flags)
2212 {
2213 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2214 return radv_reset_cmd_buffer(cmd_buffer);
2215 }
2216
2217 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2218 {
2219 struct radv_device *device = cmd_buffer->device;
2220 if (device->gfx_init) {
2221 uint64_t va = radv_buffer_get_va(device->gfx_init);
2222 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2223 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2224 radeon_emit(cmd_buffer->cs, va);
2225 radeon_emit(cmd_buffer->cs, va >> 32);
2226 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2227 } else
2228 si_init_config(cmd_buffer);
2229 }
2230
2231 VkResult radv_BeginCommandBuffer(
2232 VkCommandBuffer commandBuffer,
2233 const VkCommandBufferBeginInfo *pBeginInfo)
2234 {
2235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236 VkResult result = VK_SUCCESS;
2237
2238 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2239 /* If the command buffer has already been resetted with
2240 * vkResetCommandBuffer, no need to do it again.
2241 */
2242 result = radv_reset_cmd_buffer(cmd_buffer);
2243 if (result != VK_SUCCESS)
2244 return result;
2245 }
2246
2247 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2248 cmd_buffer->state.last_primitive_reset_en = -1;
2249 cmd_buffer->state.last_index_type = -1;
2250 cmd_buffer->usage_flags = pBeginInfo->flags;
2251
2252 /* setup initial configuration into command buffer */
2253 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2254 switch (cmd_buffer->queue_family_index) {
2255 case RADV_QUEUE_GENERAL:
2256 emit_gfx_buffer_state(cmd_buffer);
2257 break;
2258 case RADV_QUEUE_COMPUTE:
2259 si_init_compute(cmd_buffer);
2260 break;
2261 case RADV_QUEUE_TRANSFER:
2262 default:
2263 break;
2264 }
2265 }
2266
2267 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2268 assert(pBeginInfo->pInheritanceInfo);
2269 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2270 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2271
2272 struct radv_subpass *subpass =
2273 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2274
2275 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2276 if (result != VK_SUCCESS)
2277 return result;
2278
2279 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2280 }
2281
2282 if (unlikely(cmd_buffer->device->trace_bo))
2283 radv_cmd_buffer_trace_emit(cmd_buffer);
2284
2285 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2286
2287 return result;
2288 }
2289
2290 void radv_CmdBindVertexBuffers(
2291 VkCommandBuffer commandBuffer,
2292 uint32_t firstBinding,
2293 uint32_t bindingCount,
2294 const VkBuffer* pBuffers,
2295 const VkDeviceSize* pOffsets)
2296 {
2297 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2298 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2299 bool changed = false;
2300
2301 /* We have to defer setting up vertex buffer since we need the buffer
2302 * stride from the pipeline. */
2303
2304 assert(firstBinding + bindingCount <= MAX_VBS);
2305 for (uint32_t i = 0; i < bindingCount; i++) {
2306 uint32_t idx = firstBinding + i;
2307
2308 if (!changed &&
2309 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2310 vb[idx].offset != pOffsets[i])) {
2311 changed = true;
2312 }
2313
2314 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2315 vb[idx].offset = pOffsets[i];
2316
2317 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2318 vb[idx].buffer->bo, 8);
2319 }
2320
2321 if (!changed) {
2322 /* No state changes. */
2323 return;
2324 }
2325
2326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2327 }
2328
2329 void radv_CmdBindIndexBuffer(
2330 VkCommandBuffer commandBuffer,
2331 VkBuffer buffer,
2332 VkDeviceSize offset,
2333 VkIndexType indexType)
2334 {
2335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2337
2338 if (cmd_buffer->state.index_buffer == index_buffer &&
2339 cmd_buffer->state.index_offset == offset &&
2340 cmd_buffer->state.index_type == indexType) {
2341 /* No state changes. */
2342 return;
2343 }
2344
2345 cmd_buffer->state.index_buffer = index_buffer;
2346 cmd_buffer->state.index_offset = offset;
2347 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2348 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2349 cmd_buffer->state.index_va += index_buffer->offset + offset;
2350
2351 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2352 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2353 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2354 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2355 }
2356
2357
2358 static void
2359 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2360 struct radv_descriptor_set *set, unsigned idx)
2361 {
2362 struct radeon_winsys *ws = cmd_buffer->device->ws;
2363
2364 radv_set_descriptor_set(cmd_buffer, set, idx);
2365 if (!set)
2366 return;
2367
2368 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2369
2370 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2371 if (set->descriptors[j])
2372 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2373
2374 if(set->bo)
2375 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2376 }
2377
2378 void radv_CmdBindDescriptorSets(
2379 VkCommandBuffer commandBuffer,
2380 VkPipelineBindPoint pipelineBindPoint,
2381 VkPipelineLayout _layout,
2382 uint32_t firstSet,
2383 uint32_t descriptorSetCount,
2384 const VkDescriptorSet* pDescriptorSets,
2385 uint32_t dynamicOffsetCount,
2386 const uint32_t* pDynamicOffsets)
2387 {
2388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2389 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2390 unsigned dyn_idx = 0;
2391
2392 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2393 unsigned idx = i + firstSet;
2394 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2395 radv_bind_descriptor_set(cmd_buffer, set, idx);
2396
2397 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2398 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2399 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2400 assert(dyn_idx < dynamicOffsetCount);
2401
2402 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2403 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2404 dst[0] = va;
2405 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2406 dst[2] = range->size;
2407 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2411 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2412 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2413 cmd_buffer->push_constant_stages |=
2414 set->layout->dynamic_shader_stages;
2415 }
2416 }
2417 }
2418
2419 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2420 struct radv_descriptor_set *set,
2421 struct radv_descriptor_set_layout *layout)
2422 {
2423 set->size = layout->size;
2424 set->layout = layout;
2425
2426 if (cmd_buffer->push_descriptors.capacity < set->size) {
2427 size_t new_size = MAX2(set->size, 1024);
2428 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2429 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2430
2431 free(set->mapped_ptr);
2432 set->mapped_ptr = malloc(new_size);
2433
2434 if (!set->mapped_ptr) {
2435 cmd_buffer->push_descriptors.capacity = 0;
2436 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2437 return false;
2438 }
2439
2440 cmd_buffer->push_descriptors.capacity = new_size;
2441 }
2442
2443 return true;
2444 }
2445
2446 void radv_meta_push_descriptor_set(
2447 struct radv_cmd_buffer* cmd_buffer,
2448 VkPipelineBindPoint pipelineBindPoint,
2449 VkPipelineLayout _layout,
2450 uint32_t set,
2451 uint32_t descriptorWriteCount,
2452 const VkWriteDescriptorSet* pDescriptorWrites)
2453 {
2454 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2455 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2456 unsigned bo_offset;
2457
2458 assert(set == 0);
2459 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2460
2461 push_set->size = layout->set[set].layout->size;
2462 push_set->layout = layout->set[set].layout;
2463
2464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2465 &bo_offset,
2466 (void**) &push_set->mapped_ptr))
2467 return;
2468
2469 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2470 push_set->va += bo_offset;
2471
2472 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2473 radv_descriptor_set_to_handle(push_set),
2474 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2475
2476 radv_set_descriptor_set(cmd_buffer, push_set, set);
2477 }
2478
2479 void radv_CmdPushDescriptorSetKHR(
2480 VkCommandBuffer commandBuffer,
2481 VkPipelineBindPoint pipelineBindPoint,
2482 VkPipelineLayout _layout,
2483 uint32_t set,
2484 uint32_t descriptorWriteCount,
2485 const VkWriteDescriptorSet* pDescriptorWrites)
2486 {
2487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2488 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2489 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2490
2491 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2492
2493 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2494 return;
2495
2496 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2497 radv_descriptor_set_to_handle(push_set),
2498 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2499
2500 radv_set_descriptor_set(cmd_buffer, push_set, set);
2501 cmd_buffer->state.push_descriptors_dirty = true;
2502 }
2503
2504 void radv_CmdPushDescriptorSetWithTemplateKHR(
2505 VkCommandBuffer commandBuffer,
2506 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2507 VkPipelineLayout _layout,
2508 uint32_t set,
2509 const void* pData)
2510 {
2511 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2512 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2513 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2514
2515 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2516
2517 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2518 return;
2519
2520 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2521 descriptorUpdateTemplate, pData);
2522
2523 radv_set_descriptor_set(cmd_buffer, push_set, set);
2524 cmd_buffer->state.push_descriptors_dirty = true;
2525 }
2526
2527 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2528 VkPipelineLayout layout,
2529 VkShaderStageFlags stageFlags,
2530 uint32_t offset,
2531 uint32_t size,
2532 const void* pValues)
2533 {
2534 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2535 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2536 cmd_buffer->push_constant_stages |= stageFlags;
2537 }
2538
2539 VkResult radv_EndCommandBuffer(
2540 VkCommandBuffer commandBuffer)
2541 {
2542 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2543
2544 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2545 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2546 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2547 si_emit_cache_flush(cmd_buffer);
2548 }
2549
2550 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2551
2552 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2553 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2554
2555 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2556
2557 return cmd_buffer->record_result;
2558 }
2559
2560 static void
2561 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2562 {
2563 struct radv_shader_variant *compute_shader;
2564 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2565 uint64_t va;
2566
2567 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2568 return;
2569
2570 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2571
2572 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2573 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2574
2575 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2576 cmd_buffer->cs, 16);
2577
2578 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2579 radeon_emit(cmd_buffer->cs, va >> 8);
2580 radeon_emit(cmd_buffer->cs, va >> 40);
2581
2582 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2583 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2584 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2585
2586
2587 cmd_buffer->compute_scratch_size_needed =
2588 MAX2(cmd_buffer->compute_scratch_size_needed,
2589 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2590
2591 /* change these once we have scratch support */
2592 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2593 S_00B860_WAVES(pipeline->max_waves) |
2594 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2595
2596 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2597 radeon_emit(cmd_buffer->cs,
2598 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2599 radeon_emit(cmd_buffer->cs,
2600 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2601 radeon_emit(cmd_buffer->cs,
2602 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2603
2604 assert(cmd_buffer->cs->cdw <= cdw_max);
2605
2606 if (unlikely(cmd_buffer->device->trace_bo))
2607 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2608 }
2609
2610 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2611 {
2612 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2613 }
2614
2615 void radv_CmdBindPipeline(
2616 VkCommandBuffer commandBuffer,
2617 VkPipelineBindPoint pipelineBindPoint,
2618 VkPipeline _pipeline)
2619 {
2620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2621 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2622
2623 switch (pipelineBindPoint) {
2624 case VK_PIPELINE_BIND_POINT_COMPUTE:
2625 if (cmd_buffer->state.compute_pipeline == pipeline)
2626 return;
2627 radv_mark_descriptor_sets_dirty(cmd_buffer);
2628
2629 cmd_buffer->state.compute_pipeline = pipeline;
2630 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2631 break;
2632 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2633 if (cmd_buffer->state.pipeline == pipeline)
2634 return;
2635 radv_mark_descriptor_sets_dirty(cmd_buffer);
2636
2637 cmd_buffer->state.pipeline = pipeline;
2638 if (!pipeline)
2639 break;
2640
2641 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2642 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2643
2644 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2645
2646 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2647 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2648 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2649 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2650
2651 if (radv_pipeline_has_tess(pipeline))
2652 cmd_buffer->tess_rings_needed = true;
2653
2654 if (radv_pipeline_has_gs(pipeline)) {
2655 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2656 AC_UD_SCRATCH_RING_OFFSETS);
2657 if (cmd_buffer->ring_offsets_idx == -1)
2658 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2659 else if (loc->sgpr_idx != -1)
2660 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2661 }
2662 break;
2663 default:
2664 assert(!"invalid bind point");
2665 break;
2666 }
2667 }
2668
2669 void radv_CmdSetViewport(
2670 VkCommandBuffer commandBuffer,
2671 uint32_t firstViewport,
2672 uint32_t viewportCount,
2673 const VkViewport* pViewports)
2674 {
2675 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2676 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2677
2678 assert(firstViewport < MAX_VIEWPORTS);
2679 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2680
2681 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2682 pViewports, viewportCount * sizeof(*pViewports));
2683
2684 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2685 }
2686
2687 void radv_CmdSetScissor(
2688 VkCommandBuffer commandBuffer,
2689 uint32_t firstScissor,
2690 uint32_t scissorCount,
2691 const VkRect2D* pScissors)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2694 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2695
2696 assert(firstScissor < MAX_SCISSORS);
2697 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2698
2699 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2700 pScissors, scissorCount * sizeof(*pScissors));
2701 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2702 }
2703
2704 void radv_CmdSetLineWidth(
2705 VkCommandBuffer commandBuffer,
2706 float lineWidth)
2707 {
2708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2709 cmd_buffer->state.dynamic.line_width = lineWidth;
2710 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2711 }
2712
2713 void radv_CmdSetDepthBias(
2714 VkCommandBuffer commandBuffer,
2715 float depthBiasConstantFactor,
2716 float depthBiasClamp,
2717 float depthBiasSlopeFactor)
2718 {
2719 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2720
2721 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2722 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2723 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2724
2725 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2726 }
2727
2728 void radv_CmdSetBlendConstants(
2729 VkCommandBuffer commandBuffer,
2730 const float blendConstants[4])
2731 {
2732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2733
2734 memcpy(cmd_buffer->state.dynamic.blend_constants,
2735 blendConstants, sizeof(float) * 4);
2736
2737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2738 }
2739
2740 void radv_CmdSetDepthBounds(
2741 VkCommandBuffer commandBuffer,
2742 float minDepthBounds,
2743 float maxDepthBounds)
2744 {
2745 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2746
2747 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2748 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2749
2750 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2751 }
2752
2753 void radv_CmdSetStencilCompareMask(
2754 VkCommandBuffer commandBuffer,
2755 VkStencilFaceFlags faceMask,
2756 uint32_t compareMask)
2757 {
2758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2759
2760 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2761 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2762 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2763 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2764
2765 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2766 }
2767
2768 void radv_CmdSetStencilWriteMask(
2769 VkCommandBuffer commandBuffer,
2770 VkStencilFaceFlags faceMask,
2771 uint32_t writeMask)
2772 {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2774
2775 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2776 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2777 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2778 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2779
2780 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2781 }
2782
2783 void radv_CmdSetStencilReference(
2784 VkCommandBuffer commandBuffer,
2785 VkStencilFaceFlags faceMask,
2786 uint32_t reference)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789
2790 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2791 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2792 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2793 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2794
2795 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2796 }
2797
2798 void radv_CmdExecuteCommands(
2799 VkCommandBuffer commandBuffer,
2800 uint32_t commandBufferCount,
2801 const VkCommandBuffer* pCmdBuffers)
2802 {
2803 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2804
2805 assert(commandBufferCount > 0);
2806
2807 /* Emit pending flushes on primary prior to executing secondary */
2808 si_emit_cache_flush(primary);
2809
2810 for (uint32_t i = 0; i < commandBufferCount; i++) {
2811 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2812
2813 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2814 secondary->scratch_size_needed);
2815 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2816 secondary->compute_scratch_size_needed);
2817
2818 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2819 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2820 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2821 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2822 if (secondary->tess_rings_needed)
2823 primary->tess_rings_needed = true;
2824 if (secondary->sample_positions_needed)
2825 primary->sample_positions_needed = true;
2826
2827 if (secondary->ring_offsets_idx != -1) {
2828 if (primary->ring_offsets_idx == -1)
2829 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2830 else
2831 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2832 }
2833 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2834
2835
2836 /* When the secondary command buffer is compute only we don't
2837 * need to re-emit the current graphics pipeline.
2838 */
2839 if (secondary->state.emitted_pipeline) {
2840 primary->state.emitted_pipeline =
2841 secondary->state.emitted_pipeline;
2842 }
2843
2844 /* When the secondary command buffer is graphics only we don't
2845 * need to re-emit the current compute pipeline.
2846 */
2847 if (secondary->state.emitted_compute_pipeline) {
2848 primary->state.emitted_compute_pipeline =
2849 secondary->state.emitted_compute_pipeline;
2850 }
2851
2852 /* Only re-emit the draw packets when needed. */
2853 if (secondary->state.last_primitive_reset_en != -1) {
2854 primary->state.last_primitive_reset_en =
2855 secondary->state.last_primitive_reset_en;
2856 }
2857
2858 if (secondary->state.last_primitive_reset_index) {
2859 primary->state.last_primitive_reset_index =
2860 secondary->state.last_primitive_reset_index;
2861 }
2862
2863 if (secondary->state.last_ia_multi_vgt_param) {
2864 primary->state.last_ia_multi_vgt_param =
2865 secondary->state.last_ia_multi_vgt_param;
2866 }
2867
2868 if (secondary->state.last_index_type != -1) {
2869 primary->state.last_index_type =
2870 secondary->state.last_index_type;
2871 }
2872 }
2873
2874 /* After executing commands from secondary buffers we have to dirty
2875 * some states.
2876 */
2877 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2878 RADV_CMD_DIRTY_INDEX_BUFFER |
2879 RADV_CMD_DIRTY_DYNAMIC_ALL;
2880 radv_mark_descriptor_sets_dirty(primary);
2881 }
2882
2883 VkResult radv_CreateCommandPool(
2884 VkDevice _device,
2885 const VkCommandPoolCreateInfo* pCreateInfo,
2886 const VkAllocationCallbacks* pAllocator,
2887 VkCommandPool* pCmdPool)
2888 {
2889 RADV_FROM_HANDLE(radv_device, device, _device);
2890 struct radv_cmd_pool *pool;
2891
2892 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2893 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2894 if (pool == NULL)
2895 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2896
2897 if (pAllocator)
2898 pool->alloc = *pAllocator;
2899 else
2900 pool->alloc = device->alloc;
2901
2902 list_inithead(&pool->cmd_buffers);
2903 list_inithead(&pool->free_cmd_buffers);
2904
2905 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2906
2907 *pCmdPool = radv_cmd_pool_to_handle(pool);
2908
2909 return VK_SUCCESS;
2910
2911 }
2912
2913 void radv_DestroyCommandPool(
2914 VkDevice _device,
2915 VkCommandPool commandPool,
2916 const VkAllocationCallbacks* pAllocator)
2917 {
2918 RADV_FROM_HANDLE(radv_device, device, _device);
2919 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2920
2921 if (!pool)
2922 return;
2923
2924 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2925 &pool->cmd_buffers, pool_link) {
2926 radv_cmd_buffer_destroy(cmd_buffer);
2927 }
2928
2929 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2930 &pool->free_cmd_buffers, pool_link) {
2931 radv_cmd_buffer_destroy(cmd_buffer);
2932 }
2933
2934 vk_free2(&device->alloc, pAllocator, pool);
2935 }
2936
2937 VkResult radv_ResetCommandPool(
2938 VkDevice device,
2939 VkCommandPool commandPool,
2940 VkCommandPoolResetFlags flags)
2941 {
2942 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2943 VkResult result;
2944
2945 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2946 &pool->cmd_buffers, pool_link) {
2947 result = radv_reset_cmd_buffer(cmd_buffer);
2948 if (result != VK_SUCCESS)
2949 return result;
2950 }
2951
2952 return VK_SUCCESS;
2953 }
2954
2955 void radv_TrimCommandPoolKHR(
2956 VkDevice device,
2957 VkCommandPool commandPool,
2958 VkCommandPoolTrimFlagsKHR flags)
2959 {
2960 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2961
2962 if (!pool)
2963 return;
2964
2965 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2966 &pool->free_cmd_buffers, pool_link) {
2967 radv_cmd_buffer_destroy(cmd_buffer);
2968 }
2969 }
2970
2971 void radv_CmdBeginRenderPass(
2972 VkCommandBuffer commandBuffer,
2973 const VkRenderPassBeginInfo* pRenderPassBegin,
2974 VkSubpassContents contents)
2975 {
2976 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2977 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2978 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2979
2980 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2981 cmd_buffer->cs, 2048);
2982 MAYBE_UNUSED VkResult result;
2983
2984 cmd_buffer->state.framebuffer = framebuffer;
2985 cmd_buffer->state.pass = pass;
2986 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2987
2988 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2989 if (result != VK_SUCCESS)
2990 return;
2991
2992 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2993 assert(cmd_buffer->cs->cdw <= cdw_max);
2994
2995 radv_cmd_buffer_clear_subpass(cmd_buffer);
2996 }
2997
2998 void radv_CmdNextSubpass(
2999 VkCommandBuffer commandBuffer,
3000 VkSubpassContents contents)
3001 {
3002 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3003
3004 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3005
3006 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3007 2048);
3008
3009 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3010 radv_cmd_buffer_clear_subpass(cmd_buffer);
3011 }
3012
3013 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3014 {
3015 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3016 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3017 if (!pipeline->shaders[stage])
3018 continue;
3019 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3020 if (loc->sgpr_idx == -1)
3021 continue;
3022 uint32_t base_reg = pipeline->user_data_0[stage];
3023 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3024
3025 }
3026 if (pipeline->gs_copy_shader) {
3027 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3028 if (loc->sgpr_idx != -1) {
3029 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3030 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3031 }
3032 }
3033 }
3034
3035 static void
3036 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3037 uint32_t vertex_count)
3038 {
3039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3040 radeon_emit(cmd_buffer->cs, vertex_count);
3041 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3042 S_0287F0_USE_OPAQUE(0));
3043 }
3044
3045 static void
3046 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3047 uint64_t index_va,
3048 uint32_t index_count)
3049 {
3050 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3051 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3052 radeon_emit(cmd_buffer->cs, index_va);
3053 radeon_emit(cmd_buffer->cs, index_va >> 32);
3054 radeon_emit(cmd_buffer->cs, index_count);
3055 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3056 }
3057
3058 static void
3059 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3060 bool indexed,
3061 uint32_t draw_count,
3062 uint64_t count_va,
3063 uint32_t stride)
3064 {
3065 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3066 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3067 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3068 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3069 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3070 assert(base_reg);
3071
3072 if (draw_count == 1 && !count_va && !draw_id_enable) {
3073 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3074 PKT3_DRAW_INDIRECT, 3, false));
3075 radeon_emit(cs, 0);
3076 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3077 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3078 radeon_emit(cs, di_src_sel);
3079 } else {
3080 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3081 PKT3_DRAW_INDIRECT_MULTI,
3082 8, false));
3083 radeon_emit(cs, 0);
3084 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3085 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3086 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3087 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3088 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3089 radeon_emit(cs, draw_count); /* count */
3090 radeon_emit(cs, count_va); /* count_addr */
3091 radeon_emit(cs, count_va >> 32);
3092 radeon_emit(cs, stride); /* stride */
3093 radeon_emit(cs, di_src_sel);
3094 }
3095 }
3096
3097 struct radv_draw_info {
3098 /**
3099 * Number of vertices.
3100 */
3101 uint32_t count;
3102
3103 /**
3104 * Index of the first vertex.
3105 */
3106 int32_t vertex_offset;
3107
3108 /**
3109 * First instance id.
3110 */
3111 uint32_t first_instance;
3112
3113 /**
3114 * Number of instances.
3115 */
3116 uint32_t instance_count;
3117
3118 /**
3119 * First index (indexed draws only).
3120 */
3121 uint32_t first_index;
3122
3123 /**
3124 * Whether it's an indexed draw.
3125 */
3126 bool indexed;
3127
3128 /**
3129 * Indirect draw parameters resource.
3130 */
3131 struct radv_buffer *indirect;
3132 uint64_t indirect_offset;
3133 uint32_t stride;
3134
3135 /**
3136 * Draw count parameters resource.
3137 */
3138 struct radv_buffer *count_buffer;
3139 uint64_t count_buffer_offset;
3140 };
3141
3142 static void
3143 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3144 const struct radv_draw_info *info)
3145 {
3146 struct radv_cmd_state *state = &cmd_buffer->state;
3147 struct radeon_winsys *ws = cmd_buffer->device->ws;
3148 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3149
3150 if (info->indirect) {
3151 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3152 uint64_t count_va = 0;
3153
3154 va += info->indirect->offset + info->indirect_offset;
3155
3156 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3157
3158 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3159 radeon_emit(cs, 1);
3160 radeon_emit(cs, va);
3161 radeon_emit(cs, va >> 32);
3162
3163 if (info->count_buffer) {
3164 count_va = radv_buffer_get_va(info->count_buffer->bo);
3165 count_va += info->count_buffer->offset +
3166 info->count_buffer_offset;
3167
3168 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3169 }
3170
3171 if (!state->subpass->view_mask) {
3172 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3173 info->indexed,
3174 info->count,
3175 count_va,
3176 info->stride);
3177 } else {
3178 unsigned i;
3179 for_each_bit(i, state->subpass->view_mask) {
3180 radv_emit_view_index(cmd_buffer, i);
3181
3182 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3183 info->indexed,
3184 info->count,
3185 count_va,
3186 info->stride);
3187 }
3188 }
3189 } else {
3190 assert(state->pipeline->graphics.vtx_base_sgpr);
3191 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3192 state->pipeline->graphics.vtx_emit_num);
3193 radeon_emit(cs, info->vertex_offset);
3194 radeon_emit(cs, info->first_instance);
3195 if (state->pipeline->graphics.vtx_emit_num == 3)
3196 radeon_emit(cs, 0);
3197
3198 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3199 radeon_emit(cs, info->instance_count);
3200
3201 if (info->indexed) {
3202 int index_size = state->index_type ? 4 : 2;
3203 uint64_t index_va;
3204
3205 index_va = state->index_va;
3206 index_va += info->first_index * index_size;
3207
3208 if (!state->subpass->view_mask) {
3209 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3210 index_va,
3211 info->count);
3212 } else {
3213 unsigned i;
3214 for_each_bit(i, state->subpass->view_mask) {
3215 radv_emit_view_index(cmd_buffer, i);
3216
3217 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3218 index_va,
3219 info->count);
3220 }
3221 }
3222 } else {
3223 if (!state->subpass->view_mask) {
3224 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3225 } else {
3226 unsigned i;
3227 for_each_bit(i, state->subpass->view_mask) {
3228 radv_emit_view_index(cmd_buffer, i);
3229
3230 radv_cs_emit_draw_packet(cmd_buffer,
3231 info->count);
3232 }
3233 }
3234 }
3235 }
3236 }
3237
3238 static void
3239 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3240 const struct radv_draw_info *info)
3241 {
3242 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3243 radv_emit_graphics_pipeline(cmd_buffer);
3244
3245 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3246 radv_emit_framebuffer_state(cmd_buffer);
3247
3248 if (info->indexed) {
3249 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3250 radv_emit_index_buffer(cmd_buffer);
3251 } else {
3252 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3253 * so the state must be re-emitted before the next indexed
3254 * draw.
3255 */
3256 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3257 cmd_buffer->state.last_index_type = -1;
3258 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3259 }
3260 }
3261
3262 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3263
3264 radv_emit_draw_registers(cmd_buffer, info->indexed,
3265 info->instance_count > 1, info->indirect,
3266 info->indirect ? 0 : info->count);
3267 }
3268
3269 static void
3270 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3271 const struct radv_draw_info *info)
3272 {
3273 bool pipeline_is_dirty =
3274 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3275 cmd_buffer->state.pipeline &&
3276 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3277
3278 MAYBE_UNUSED unsigned cdw_max =
3279 radeon_check_space(cmd_buffer->device->ws,
3280 cmd_buffer->cs, 4096);
3281
3282 /* Use optimal packet order based on whether we need to sync the
3283 * pipeline.
3284 */
3285 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3286 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3287 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3288 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3289 /* If we have to wait for idle, set all states first, so that
3290 * all SET packets are processed in parallel with previous draw
3291 * calls. Then upload descriptors, set shader pointers, and
3292 * draw, and prefetch at the end. This ensures that the time
3293 * the CUs are idle is very short. (there are only SET_SH
3294 * packets between the wait and the draw)
3295 */
3296 radv_emit_all_graphics_states(cmd_buffer, info);
3297 si_emit_cache_flush(cmd_buffer);
3298 /* <-- CUs are idle here --> */
3299
3300 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3301 return;
3302
3303 radv_emit_draw_packets(cmd_buffer, info);
3304 /* <-- CUs are busy here --> */
3305
3306 /* Start prefetches after the draw has been started. Both will
3307 * run in parallel, but starting the draw first is more
3308 * important.
3309 */
3310 if (pipeline_is_dirty) {
3311 radv_emit_prefetch(cmd_buffer,
3312 cmd_buffer->state.pipeline);
3313 }
3314 } else {
3315 /* If we don't wait for idle, start prefetches first, then set
3316 * states, and draw at the end.
3317 */
3318 si_emit_cache_flush(cmd_buffer);
3319
3320 if (pipeline_is_dirty) {
3321 radv_emit_prefetch(cmd_buffer,
3322 cmd_buffer->state.pipeline);
3323 }
3324
3325 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3326 return;
3327
3328 radv_emit_all_graphics_states(cmd_buffer, info);
3329 radv_emit_draw_packets(cmd_buffer, info);
3330 }
3331
3332 assert(cmd_buffer->cs->cdw <= cdw_max);
3333 radv_cmd_buffer_after_draw(cmd_buffer);
3334 }
3335
3336 void radv_CmdDraw(
3337 VkCommandBuffer commandBuffer,
3338 uint32_t vertexCount,
3339 uint32_t instanceCount,
3340 uint32_t firstVertex,
3341 uint32_t firstInstance)
3342 {
3343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3344 struct radv_draw_info info = {};
3345
3346 info.count = vertexCount;
3347 info.instance_count = instanceCount;
3348 info.first_instance = firstInstance;
3349 info.vertex_offset = firstVertex;
3350
3351 radv_draw(cmd_buffer, &info);
3352 }
3353
3354 void radv_CmdDrawIndexed(
3355 VkCommandBuffer commandBuffer,
3356 uint32_t indexCount,
3357 uint32_t instanceCount,
3358 uint32_t firstIndex,
3359 int32_t vertexOffset,
3360 uint32_t firstInstance)
3361 {
3362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3363 struct radv_draw_info info = {};
3364
3365 info.indexed = true;
3366 info.count = indexCount;
3367 info.instance_count = instanceCount;
3368 info.first_index = firstIndex;
3369 info.vertex_offset = vertexOffset;
3370 info.first_instance = firstInstance;
3371
3372 radv_draw(cmd_buffer, &info);
3373 }
3374
3375 void radv_CmdDrawIndirect(
3376 VkCommandBuffer commandBuffer,
3377 VkBuffer _buffer,
3378 VkDeviceSize offset,
3379 uint32_t drawCount,
3380 uint32_t stride)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3383 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3384 struct radv_draw_info info = {};
3385
3386 info.count = drawCount;
3387 info.indirect = buffer;
3388 info.indirect_offset = offset;
3389 info.stride = stride;
3390
3391 radv_draw(cmd_buffer, &info);
3392 }
3393
3394 void radv_CmdDrawIndexedIndirect(
3395 VkCommandBuffer commandBuffer,
3396 VkBuffer _buffer,
3397 VkDeviceSize offset,
3398 uint32_t drawCount,
3399 uint32_t stride)
3400 {
3401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3402 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3403 struct radv_draw_info info = {};
3404
3405 info.indexed = true;
3406 info.count = drawCount;
3407 info.indirect = buffer;
3408 info.indirect_offset = offset;
3409 info.stride = stride;
3410
3411 radv_draw(cmd_buffer, &info);
3412 }
3413
3414 void radv_CmdDrawIndirectCountAMD(
3415 VkCommandBuffer commandBuffer,
3416 VkBuffer _buffer,
3417 VkDeviceSize offset,
3418 VkBuffer _countBuffer,
3419 VkDeviceSize countBufferOffset,
3420 uint32_t maxDrawCount,
3421 uint32_t stride)
3422 {
3423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3424 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3425 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3426 struct radv_draw_info info = {};
3427
3428 info.count = maxDrawCount;
3429 info.indirect = buffer;
3430 info.indirect_offset = offset;
3431 info.count_buffer = count_buffer;
3432 info.count_buffer_offset = countBufferOffset;
3433 info.stride = stride;
3434
3435 radv_draw(cmd_buffer, &info);
3436 }
3437
3438 void radv_CmdDrawIndexedIndirectCountAMD(
3439 VkCommandBuffer commandBuffer,
3440 VkBuffer _buffer,
3441 VkDeviceSize offset,
3442 VkBuffer _countBuffer,
3443 VkDeviceSize countBufferOffset,
3444 uint32_t maxDrawCount,
3445 uint32_t stride)
3446 {
3447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3448 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3449 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3450 struct radv_draw_info info = {};
3451
3452 info.indexed = true;
3453 info.count = maxDrawCount;
3454 info.indirect = buffer;
3455 info.indirect_offset = offset;
3456 info.count_buffer = count_buffer;
3457 info.count_buffer_offset = countBufferOffset;
3458 info.stride = stride;
3459
3460 radv_draw(cmd_buffer, &info);
3461 }
3462
3463 struct radv_dispatch_info {
3464 /**
3465 * Determine the layout of the grid (in block units) to be used.
3466 */
3467 uint32_t blocks[3];
3468
3469 /**
3470 * Whether it's an unaligned compute dispatch.
3471 */
3472 bool unaligned;
3473
3474 /**
3475 * Indirect compute parameters resource.
3476 */
3477 struct radv_buffer *indirect;
3478 uint64_t indirect_offset;
3479 };
3480
3481 static void
3482 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3483 const struct radv_dispatch_info *info)
3484 {
3485 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3486 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3487 struct radeon_winsys *ws = cmd_buffer->device->ws;
3488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3489 struct ac_userdata_info *loc;
3490 unsigned dispatch_initiator;
3491 uint8_t grid_used;
3492
3493 grid_used = compute_shader->info.info.cs.grid_components_used;
3494
3495 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3496 AC_UD_CS_GRID_SIZE);
3497
3498 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3499
3500 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3501 S_00B800_FORCE_START_AT_000(1);
3502
3503 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3504 /* If the KMD allows it (there is a KMD hw register for it),
3505 * allow launching waves out-of-order.
3506 */
3507 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3508 }
3509
3510 if (info->indirect) {
3511 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3512
3513 va += info->indirect->offset + info->indirect_offset;
3514
3515 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3516
3517 if (loc->sgpr_idx != -1) {
3518 for (unsigned i = 0; i < grid_used; ++i) {
3519 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3520 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3521 COPY_DATA_DST_SEL(COPY_DATA_REG));
3522 radeon_emit(cs, (va + 4 * i));
3523 radeon_emit(cs, (va + 4 * i) >> 32);
3524 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3525 + loc->sgpr_idx * 4) >> 2) + i);
3526 radeon_emit(cs, 0);
3527 }
3528 }
3529
3530 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3531 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3532 PKT3_SHADER_TYPE_S(1));
3533 radeon_emit(cs, va);
3534 radeon_emit(cs, va >> 32);
3535 radeon_emit(cs, dispatch_initiator);
3536 } else {
3537 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3538 PKT3_SHADER_TYPE_S(1));
3539 radeon_emit(cs, 1);
3540 radeon_emit(cs, va);
3541 radeon_emit(cs, va >> 32);
3542
3543 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3544 PKT3_SHADER_TYPE_S(1));
3545 radeon_emit(cs, 0);
3546 radeon_emit(cs, dispatch_initiator);
3547 }
3548 } else {
3549 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3550
3551 if (info->unaligned) {
3552 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3553 unsigned remainder[3];
3554
3555 /* If aligned, these should be an entire block size,
3556 * not 0.
3557 */
3558 remainder[0] = blocks[0] + cs_block_size[0] -
3559 align_u32_npot(blocks[0], cs_block_size[0]);
3560 remainder[1] = blocks[1] + cs_block_size[1] -
3561 align_u32_npot(blocks[1], cs_block_size[1]);
3562 remainder[2] = blocks[2] + cs_block_size[2] -
3563 align_u32_npot(blocks[2], cs_block_size[2]);
3564
3565 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3566 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3567 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3568
3569 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3570 radeon_emit(cs,
3571 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3572 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3573 radeon_emit(cs,
3574 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3575 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3576 radeon_emit(cs,
3577 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3578 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3579
3580 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3581 }
3582
3583 if (loc->sgpr_idx != -1) {
3584 assert(!loc->indirect);
3585 assert(loc->num_sgprs == grid_used);
3586
3587 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3588 loc->sgpr_idx * 4, grid_used);
3589 radeon_emit(cs, blocks[0]);
3590 if (grid_used > 1)
3591 radeon_emit(cs, blocks[1]);
3592 if (grid_used > 2)
3593 radeon_emit(cs, blocks[2]);
3594 }
3595
3596 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3597 PKT3_SHADER_TYPE_S(1));
3598 radeon_emit(cs, blocks[0]);
3599 radeon_emit(cs, blocks[1]);
3600 radeon_emit(cs, blocks[2]);
3601 radeon_emit(cs, dispatch_initiator);
3602 }
3603
3604 assert(cmd_buffer->cs->cdw <= cdw_max);
3605 }
3606
3607 static void
3608 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3609 {
3610 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3611 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3612 VK_SHADER_STAGE_COMPUTE_BIT);
3613 }
3614
3615 static void
3616 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3617 const struct radv_dispatch_info *info)
3618 {
3619 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3620 bool pipeline_is_dirty = pipeline &&
3621 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3622
3623 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3624 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3625 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3626 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3627 /* If we have to wait for idle, set all states first, so that
3628 * all SET packets are processed in parallel with previous draw
3629 * calls. Then upload descriptors, set shader pointers, and
3630 * dispatch, and prefetch at the end. This ensures that the
3631 * time the CUs are idle is very short. (there are only SET_SH
3632 * packets between the wait and the draw)
3633 */
3634 radv_emit_compute_pipeline(cmd_buffer);
3635 si_emit_cache_flush(cmd_buffer);
3636 /* <-- CUs are idle here --> */
3637
3638 radv_upload_compute_shader_descriptors(cmd_buffer);
3639
3640 radv_emit_dispatch_packets(cmd_buffer, info);
3641 /* <-- CUs are busy here --> */
3642
3643 /* Start prefetches after the dispatch has been started. Both
3644 * will run in parallel, but starting the dispatch first is
3645 * more important.
3646 */
3647 if (pipeline_is_dirty) {
3648 radv_emit_shader_prefetch(cmd_buffer,
3649 pipeline->shaders[MESA_SHADER_COMPUTE]);
3650 }
3651 } else {
3652 /* If we don't wait for idle, start prefetches first, then set
3653 * states, and dispatch at the end.
3654 */
3655 si_emit_cache_flush(cmd_buffer);
3656
3657 if (pipeline_is_dirty) {
3658 radv_emit_shader_prefetch(cmd_buffer,
3659 pipeline->shaders[MESA_SHADER_COMPUTE]);
3660 }
3661
3662 radv_upload_compute_shader_descriptors(cmd_buffer);
3663
3664 radv_emit_compute_pipeline(cmd_buffer);
3665 radv_emit_dispatch_packets(cmd_buffer, info);
3666 }
3667
3668 radv_cmd_buffer_after_draw(cmd_buffer);
3669 }
3670
3671 void radv_CmdDispatch(
3672 VkCommandBuffer commandBuffer,
3673 uint32_t x,
3674 uint32_t y,
3675 uint32_t z)
3676 {
3677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3678 struct radv_dispatch_info info = {};
3679
3680 info.blocks[0] = x;
3681 info.blocks[1] = y;
3682 info.blocks[2] = z;
3683
3684 radv_dispatch(cmd_buffer, &info);
3685 }
3686
3687 void radv_CmdDispatchIndirect(
3688 VkCommandBuffer commandBuffer,
3689 VkBuffer _buffer,
3690 VkDeviceSize offset)
3691 {
3692 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3693 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3694 struct radv_dispatch_info info = {};
3695
3696 info.indirect = buffer;
3697 info.indirect_offset = offset;
3698
3699 radv_dispatch(cmd_buffer, &info);
3700 }
3701
3702 void radv_unaligned_dispatch(
3703 struct radv_cmd_buffer *cmd_buffer,
3704 uint32_t x,
3705 uint32_t y,
3706 uint32_t z)
3707 {
3708 struct radv_dispatch_info info = {};
3709
3710 info.blocks[0] = x;
3711 info.blocks[1] = y;
3712 info.blocks[2] = z;
3713 info.unaligned = 1;
3714
3715 radv_dispatch(cmd_buffer, &info);
3716 }
3717
3718 void radv_CmdEndRenderPass(
3719 VkCommandBuffer commandBuffer)
3720 {
3721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3722
3723 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3724
3725 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3726
3727 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3728 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3729 radv_handle_subpass_image_transition(cmd_buffer,
3730 (VkAttachmentReference){i, layout});
3731 }
3732
3733 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3734
3735 cmd_buffer->state.pass = NULL;
3736 cmd_buffer->state.subpass = NULL;
3737 cmd_buffer->state.attachments = NULL;
3738 cmd_buffer->state.framebuffer = NULL;
3739 }
3740
3741 /*
3742 * For HTILE we have the following interesting clear words:
3743 * 0x0000030f: Uncompressed.
3744 * 0xfffffff0: Clear depth to 1.0
3745 * 0x00000000: Clear depth to 0.0
3746 */
3747 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3748 struct radv_image *image,
3749 const VkImageSubresourceRange *range,
3750 uint32_t clear_word)
3751 {
3752 assert(range->baseMipLevel == 0);
3753 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3754 unsigned layer_count = radv_get_layerCount(image, range);
3755 uint64_t size = image->surface.htile_slice_size * layer_count;
3756 uint64_t offset = image->offset + image->htile_offset +
3757 image->surface.htile_slice_size * range->baseArrayLayer;
3758 struct radv_cmd_state *state = &cmd_buffer->state;
3759
3760 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3761 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3762
3763 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3764 size, clear_word);
3765
3766 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3767 }
3768
3769 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3770 struct radv_image *image,
3771 VkImageLayout src_layout,
3772 VkImageLayout dst_layout,
3773 unsigned src_queue_mask,
3774 unsigned dst_queue_mask,
3775 const VkImageSubresourceRange *range,
3776 VkImageAspectFlags pending_clears)
3777 {
3778 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3779 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3780 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3781 cmd_buffer->state.render_area.extent.width == image->info.width &&
3782 cmd_buffer->state.render_area.extent.height == image->info.height) {
3783 /* The clear will initialize htile. */
3784 return;
3785 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3786 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3787 /* TODO: merge with the clear if applicable */
3788 radv_initialize_htile(cmd_buffer, image, range, 0);
3789 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3790 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3791 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3792 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3793 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3794 VkImageSubresourceRange local_range = *range;
3795 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3796 local_range.baseMipLevel = 0;
3797 local_range.levelCount = 1;
3798
3799 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3800 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3801
3802 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3803
3804 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3805 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3806 }
3807 }
3808
3809 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3810 struct radv_image *image, uint32_t value)
3811 {
3812 struct radv_cmd_state *state = &cmd_buffer->state;
3813
3814 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3815 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3816
3817 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3818 image->offset + image->cmask.offset,
3819 image->cmask.size, value);
3820
3821 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3822 }
3823
3824 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3825 struct radv_image *image,
3826 VkImageLayout src_layout,
3827 VkImageLayout dst_layout,
3828 unsigned src_queue_mask,
3829 unsigned dst_queue_mask,
3830 const VkImageSubresourceRange *range)
3831 {
3832 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3833 if (image->fmask.size)
3834 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3835 else
3836 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3837 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3838 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3839 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3840 }
3841 }
3842
3843 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3844 struct radv_image *image, uint32_t value)
3845 {
3846 struct radv_cmd_state *state = &cmd_buffer->state;
3847
3848 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3849 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3850
3851 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3852 image->offset + image->dcc_offset,
3853 image->surface.dcc_size, value);
3854
3855 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3856 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3857 }
3858
3859 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3860 struct radv_image *image,
3861 VkImageLayout src_layout,
3862 VkImageLayout dst_layout,
3863 unsigned src_queue_mask,
3864 unsigned dst_queue_mask,
3865 const VkImageSubresourceRange *range)
3866 {
3867 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3868 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3869 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3870 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3871 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3872 }
3873 }
3874
3875 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3876 struct radv_image *image,
3877 VkImageLayout src_layout,
3878 VkImageLayout dst_layout,
3879 uint32_t src_family,
3880 uint32_t dst_family,
3881 const VkImageSubresourceRange *range,
3882 VkImageAspectFlags pending_clears)
3883 {
3884 if (image->exclusive && src_family != dst_family) {
3885 /* This is an acquire or a release operation and there will be
3886 * a corresponding release/acquire. Do the transition in the
3887 * most flexible queue. */
3888
3889 assert(src_family == cmd_buffer->queue_family_index ||
3890 dst_family == cmd_buffer->queue_family_index);
3891
3892 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3893 return;
3894
3895 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3896 (src_family == RADV_QUEUE_GENERAL ||
3897 dst_family == RADV_QUEUE_GENERAL))
3898 return;
3899 }
3900
3901 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3902 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3903
3904 if (image->surface.htile_size)
3905 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3906 dst_layout, src_queue_mask,
3907 dst_queue_mask, range,
3908 pending_clears);
3909
3910 if (image->cmask.size || image->fmask.size)
3911 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3912 dst_layout, src_queue_mask,
3913 dst_queue_mask, range);
3914
3915 if (image->surface.dcc_size)
3916 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3917 dst_layout, src_queue_mask,
3918 dst_queue_mask, range);
3919 }
3920
3921 void radv_CmdPipelineBarrier(
3922 VkCommandBuffer commandBuffer,
3923 VkPipelineStageFlags srcStageMask,
3924 VkPipelineStageFlags destStageMask,
3925 VkBool32 byRegion,
3926 uint32_t memoryBarrierCount,
3927 const VkMemoryBarrier* pMemoryBarriers,
3928 uint32_t bufferMemoryBarrierCount,
3929 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3930 uint32_t imageMemoryBarrierCount,
3931 const VkImageMemoryBarrier* pImageMemoryBarriers)
3932 {
3933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3934 enum radv_cmd_flush_bits src_flush_bits = 0;
3935 enum radv_cmd_flush_bits dst_flush_bits = 0;
3936
3937 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3938 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3939 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3940 NULL);
3941 }
3942
3943 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3944 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3945 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3946 NULL);
3947 }
3948
3949 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3950 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3951 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3952 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3953 image);
3954 }
3955
3956 radv_stage_flush(cmd_buffer, srcStageMask);
3957 cmd_buffer->state.flush_bits |= src_flush_bits;
3958
3959 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3960 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3961 radv_handle_image_transition(cmd_buffer, image,
3962 pImageMemoryBarriers[i].oldLayout,
3963 pImageMemoryBarriers[i].newLayout,
3964 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3965 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3966 &pImageMemoryBarriers[i].subresourceRange,
3967 0);
3968 }
3969
3970 cmd_buffer->state.flush_bits |= dst_flush_bits;
3971 }
3972
3973
3974 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3975 struct radv_event *event,
3976 VkPipelineStageFlags stageMask,
3977 unsigned value)
3978 {
3979 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3980 uint64_t va = radv_buffer_get_va(event->bo);
3981
3982 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3983
3984 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3985
3986 /* TODO: this is overkill. Probably should figure something out from
3987 * the stage mask. */
3988
3989 si_cs_emit_write_event_eop(cs,
3990 cmd_buffer->state.predicating,
3991 cmd_buffer->device->physical_device->rad_info.chip_class,
3992 false,
3993 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3994 1, va, 2, value);
3995
3996 assert(cmd_buffer->cs->cdw <= cdw_max);
3997 }
3998
3999 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4000 VkEvent _event,
4001 VkPipelineStageFlags stageMask)
4002 {
4003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4004 RADV_FROM_HANDLE(radv_event, event, _event);
4005
4006 write_event(cmd_buffer, event, stageMask, 1);
4007 }
4008
4009 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4010 VkEvent _event,
4011 VkPipelineStageFlags stageMask)
4012 {
4013 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4014 RADV_FROM_HANDLE(radv_event, event, _event);
4015
4016 write_event(cmd_buffer, event, stageMask, 0);
4017 }
4018
4019 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4020 uint32_t eventCount,
4021 const VkEvent* pEvents,
4022 VkPipelineStageFlags srcStageMask,
4023 VkPipelineStageFlags dstStageMask,
4024 uint32_t memoryBarrierCount,
4025 const VkMemoryBarrier* pMemoryBarriers,
4026 uint32_t bufferMemoryBarrierCount,
4027 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4028 uint32_t imageMemoryBarrierCount,
4029 const VkImageMemoryBarrier* pImageMemoryBarriers)
4030 {
4031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4032 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4033
4034 for (unsigned i = 0; i < eventCount; ++i) {
4035 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4036 uint64_t va = radv_buffer_get_va(event->bo);
4037
4038 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4039
4040 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4041
4042 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4043 assert(cmd_buffer->cs->cdw <= cdw_max);
4044 }
4045
4046
4047 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4048 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4049
4050 radv_handle_image_transition(cmd_buffer, image,
4051 pImageMemoryBarriers[i].oldLayout,
4052 pImageMemoryBarriers[i].newLayout,
4053 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4054 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4055 &pImageMemoryBarriers[i].subresourceRange,
4056 0);
4057 }
4058
4059 /* TODO: figure out how to do memory barriers without waiting */
4060 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4061 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4062 RADV_CMD_FLAG_INV_VMEM_L1 |
4063 RADV_CMD_FLAG_INV_SMEM_L1;
4064 }