2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
102 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
103 const struct radv_dynamic_state
*src
)
105 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
106 uint32_t copy_mask
= src
->mask
;
107 uint32_t dest_mask
= 0;
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
112 dest
->viewport
.count
= src
->viewport
.count
;
113 dest
->scissor
.count
= src
->scissor
.count
;
114 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
115 dest
->sample_location
.count
= src
->sample_location
.count
;
117 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
118 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
119 src
->viewport
.count
* sizeof(VkViewport
))) {
120 typed_memcpy(dest
->viewport
.viewports
,
121 src
->viewport
.viewports
,
122 src
->viewport
.count
);
123 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
127 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
128 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
129 src
->scissor
.count
* sizeof(VkRect2D
))) {
130 typed_memcpy(dest
->scissor
.scissors
,
131 src
->scissor
.scissors
, src
->scissor
.count
);
132 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
136 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
137 if (dest
->line_width
!= src
->line_width
) {
138 dest
->line_width
= src
->line_width
;
139 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
143 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
144 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
145 sizeof(src
->depth_bias
))) {
146 dest
->depth_bias
= src
->depth_bias
;
147 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
151 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
152 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
153 sizeof(src
->blend_constants
))) {
154 typed_memcpy(dest
->blend_constants
,
155 src
->blend_constants
, 4);
156 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
160 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
161 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
162 sizeof(src
->depth_bounds
))) {
163 dest
->depth_bounds
= src
->depth_bounds
;
164 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
168 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
169 if (memcmp(&dest
->stencil_compare_mask
,
170 &src
->stencil_compare_mask
,
171 sizeof(src
->stencil_compare_mask
))) {
172 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
178 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
179 sizeof(src
->stencil_write_mask
))) {
180 dest
->stencil_write_mask
= src
->stencil_write_mask
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
185 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
186 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
187 sizeof(src
->stencil_reference
))) {
188 dest
->stencil_reference
= src
->stencil_reference
;
189 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
193 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
194 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
195 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
196 typed_memcpy(dest
->discard_rectangle
.rectangles
,
197 src
->discard_rectangle
.rectangles
,
198 src
->discard_rectangle
.count
);
199 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
203 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
204 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
205 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
206 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
207 memcmp(&dest
->sample_location
.locations
,
208 &src
->sample_location
.locations
,
209 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
210 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
211 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
212 typed_memcpy(dest
->sample_location
.locations
,
213 src
->sample_location
.locations
,
214 src
->sample_location
.count
);
215 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
219 if (copy_mask
& RADV_DYNAMIC_LINE_STIPPLE
) {
220 if (memcmp(&dest
->line_stipple
, &src
->line_stipple
,
221 sizeof(src
->line_stipple
))) {
222 dest
->line_stipple
= src
->line_stipple
;
223 dest_mask
|= RADV_DYNAMIC_LINE_STIPPLE
;
227 cmd_buffer
->state
.dirty
|= dest_mask
;
231 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
232 struct radv_pipeline
*pipeline
)
234 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
235 struct radv_shader_info
*info
;
237 if (!pipeline
->streamout_shader
||
238 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
241 info
= &pipeline
->streamout_shader
->info
;
242 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
243 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
245 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
250 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
251 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
254 enum ring_type
radv_queue_family_to_ring(int f
) {
256 case RADV_QUEUE_GENERAL
:
258 case RADV_QUEUE_COMPUTE
:
260 case RADV_QUEUE_TRANSFER
:
263 unreachable("Unknown queue family");
267 static VkResult
radv_create_cmd_buffer(
268 struct radv_device
* device
,
269 struct radv_cmd_pool
* pool
,
270 VkCommandBufferLevel level
,
271 VkCommandBuffer
* pCommandBuffer
)
273 struct radv_cmd_buffer
*cmd_buffer
;
275 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
277 if (cmd_buffer
== NULL
)
278 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
280 vk_object_base_init(&device
->vk
, &cmd_buffer
->base
,
281 VK_OBJECT_TYPE_COMMAND_BUFFER
);
283 cmd_buffer
->device
= device
;
284 cmd_buffer
->pool
= pool
;
285 cmd_buffer
->level
= level
;
287 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
288 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
290 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
292 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
293 if (!cmd_buffer
->cs
) {
294 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
295 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
298 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
300 list_inithead(&cmd_buffer
->upload
.list
);
306 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
308 list_del(&cmd_buffer
->pool_link
);
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
311 &cmd_buffer
->upload
.list
, list
) {
312 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
317 if (cmd_buffer
->upload
.upload_bo
)
318 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
319 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
321 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
322 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
324 vk_object_base_finish(&cmd_buffer
->base
);
326 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
330 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
332 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
334 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
335 &cmd_buffer
->upload
.list
, list
) {
336 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
341 cmd_buffer
->push_constant_stages
= 0;
342 cmd_buffer
->scratch_size_per_wave_needed
= 0;
343 cmd_buffer
->scratch_waves_wanted
= 0;
344 cmd_buffer
->compute_scratch_size_per_wave_needed
= 0;
345 cmd_buffer
->compute_scratch_waves_wanted
= 0;
346 cmd_buffer
->esgs_ring_size_needed
= 0;
347 cmd_buffer
->gsvs_ring_size_needed
= 0;
348 cmd_buffer
->tess_rings_needed
= false;
349 cmd_buffer
->gds_needed
= false;
350 cmd_buffer
->gds_oa_needed
= false;
351 cmd_buffer
->sample_positions_needed
= false;
353 if (cmd_buffer
->upload
.upload_bo
)
354 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
355 cmd_buffer
->upload
.upload_bo
);
356 cmd_buffer
->upload
.offset
= 0;
358 cmd_buffer
->record_result
= VK_SUCCESS
;
360 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
362 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++) {
363 cmd_buffer
->descriptors
[i
].dirty
= 0;
364 cmd_buffer
->descriptors
[i
].valid
= 0;
365 cmd_buffer
->descriptors
[i
].push_dirty
= false;
368 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
369 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
370 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
371 unsigned fence_offset
, eop_bug_offset
;
374 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
377 cmd_buffer
->gfx9_fence_va
=
378 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
379 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
381 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
382 /* Allocate a buffer for the EOP bug on GFX9. */
383 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
384 &eop_bug_offset
, &fence_ptr
);
385 cmd_buffer
->gfx9_eop_bug_va
=
386 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
387 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
391 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
393 return cmd_buffer
->record_result
;
397 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
401 struct radeon_winsys_bo
*bo
;
402 struct radv_cmd_buffer_upload
*upload
;
403 struct radv_device
*device
= cmd_buffer
->device
;
405 new_size
= MAX2(min_needed
, 16 * 1024);
406 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
408 bo
= device
->ws
->buffer_create(device
->ws
,
411 RADEON_FLAG_CPU_ACCESS
|
412 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
414 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
417 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
421 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
422 if (cmd_buffer
->upload
.upload_bo
) {
423 upload
= malloc(sizeof(*upload
));
426 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
427 device
->ws
->buffer_destroy(bo
);
431 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
432 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
435 cmd_buffer
->upload
.upload_bo
= bo
;
436 cmd_buffer
->upload
.size
= new_size
;
437 cmd_buffer
->upload
.offset
= 0;
438 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
440 if (!cmd_buffer
->upload
.map
) {
441 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
449 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
452 unsigned *out_offset
,
455 assert(util_is_power_of_two_nonzero(alignment
));
457 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
458 if (offset
+ size
> cmd_buffer
->upload
.size
) {
459 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
464 *out_offset
= offset
;
465 *ptr
= cmd_buffer
->upload
.map
+ offset
;
467 cmd_buffer
->upload
.offset
= offset
+ size
;
472 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
473 unsigned size
, unsigned alignment
,
474 const void *data
, unsigned *out_offset
)
478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
479 out_offset
, (void **)&ptr
))
483 memcpy(ptr
, data
, size
);
489 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
490 unsigned count
, const uint32_t *data
)
492 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
494 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
496 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
497 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
498 S_370_WR_CONFIRM(1) |
499 S_370_ENGINE_SEL(V_370_ME
));
501 radeon_emit(cs
, va
>> 32);
502 radeon_emit_array(cs
, data
, count
);
505 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
507 struct radv_device
*device
= cmd_buffer
->device
;
508 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
511 va
= radv_buffer_get_va(device
->trace_bo
);
512 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
515 ++cmd_buffer
->state
.trace_id
;
516 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
517 &cmd_buffer
->state
.trace_id
);
519 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
521 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
522 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
526 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
527 enum radv_cmd_flush_bits flags
)
529 if (unlikely(cmd_buffer
->device
->thread_trace_bo
)) {
530 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
531 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER
) | EVENT_INDEX(0));
534 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
535 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
536 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
538 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
540 /* Force wait for graphics or compute engines to be idle. */
541 si_cs_emit_cache_flush(cmd_buffer
->cs
,
542 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
543 &cmd_buffer
->gfx9_fence_idx
,
544 cmd_buffer
->gfx9_fence_va
,
545 radv_cmd_buffer_uses_mec(cmd_buffer
),
546 flags
, cmd_buffer
->gfx9_eop_bug_va
);
549 if (unlikely(cmd_buffer
->device
->trace_bo
))
550 radv_cmd_buffer_trace_emit(cmd_buffer
);
554 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
555 struct radv_pipeline
*pipeline
, enum ring_type ring
)
557 struct radv_device
*device
= cmd_buffer
->device
;
561 va
= radv_buffer_get_va(device
->trace_bo
);
571 assert(!"invalid ring type");
574 uint64_t pipeline_address
= (uintptr_t)pipeline
;
575 data
[0] = pipeline_address
;
576 data
[1] = pipeline_address
>> 32;
578 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
581 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
582 VkPipelineBindPoint bind_point
,
583 struct radv_descriptor_set
*set
,
586 struct radv_descriptor_state
*descriptors_state
=
587 radv_get_descriptors_state(cmd_buffer
, bind_point
);
589 descriptors_state
->sets
[idx
] = set
;
591 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
592 descriptors_state
->dirty
|= (1u << idx
);
596 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
597 VkPipelineBindPoint bind_point
)
599 struct radv_descriptor_state
*descriptors_state
=
600 radv_get_descriptors_state(cmd_buffer
, bind_point
);
601 struct radv_device
*device
= cmd_buffer
->device
;
602 uint32_t data
[MAX_SETS
* 2] = {};
605 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
607 for_each_bit(i
, descriptors_state
->valid
) {
608 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
609 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
610 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
613 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
616 struct radv_userdata_info
*
617 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
618 gl_shader_stage stage
,
621 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
622 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
626 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
627 struct radv_pipeline
*pipeline
,
628 gl_shader_stage stage
,
629 int idx
, uint64_t va
)
631 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
632 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
633 if (loc
->sgpr_idx
== -1)
636 assert(loc
->num_sgprs
== 1);
638 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
639 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
643 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
644 struct radv_pipeline
*pipeline
,
645 struct radv_descriptor_state
*descriptors_state
,
646 gl_shader_stage stage
)
648 struct radv_device
*device
= cmd_buffer
->device
;
649 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
650 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
651 struct radv_userdata_locations
*locs
=
652 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
653 unsigned mask
= locs
->descriptor_sets_enabled
;
655 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
660 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
662 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
663 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
665 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
666 for (int i
= 0; i
< count
; i
++) {
667 struct radv_descriptor_set
*set
=
668 descriptors_state
->sets
[start
+ i
];
670 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
676 * Convert the user sample locations to hardware sample locations (the values
677 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
680 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
681 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
683 uint32_t x_offset
= x
% state
->grid_size
.width
;
684 uint32_t y_offset
= y
% state
->grid_size
.height
;
685 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
686 VkSampleLocationEXT
*user_locs
;
687 uint32_t pixel_offset
;
689 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
691 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
692 user_locs
= &state
->locations
[pixel_offset
];
694 for (uint32_t i
= 0; i
< num_samples
; i
++) {
695 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
696 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
698 int32_t scaled_pos_x
= floorf(shifted_pos_x
* 16);
699 int32_t scaled_pos_y
= floorf(shifted_pos_y
* 16);
701 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
702 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
707 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
711 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
712 uint32_t *sample_locs_pixel
)
714 for (uint32_t i
= 0; i
< num_samples
; i
++) {
715 uint32_t sample_reg_idx
= i
/ 4;
716 uint32_t sample_loc_idx
= i
% 4;
717 int32_t pos_x
= sample_locs
[i
].x
;
718 int32_t pos_y
= sample_locs
[i
].y
;
720 uint32_t shift_x
= 8 * sample_loc_idx
;
721 uint32_t shift_y
= shift_x
+ 4;
723 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
724 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
729 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
733 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
734 VkOffset2D
*sample_locs
,
735 uint32_t num_samples
)
737 uint32_t centroid_priorities
[num_samples
];
738 uint32_t sample_mask
= num_samples
- 1;
739 uint32_t distances
[num_samples
];
740 uint64_t centroid_priority
= 0;
742 /* Compute the distances from center for each sample. */
743 for (int i
= 0; i
< num_samples
; i
++) {
744 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
745 (sample_locs
[i
].y
* sample_locs
[i
].y
);
748 /* Compute the centroid priorities by looking at the distances array. */
749 for (int i
= 0; i
< num_samples
; i
++) {
750 uint32_t min_idx
= 0;
752 for (int j
= 1; j
< num_samples
; j
++) {
753 if (distances
[j
] < distances
[min_idx
])
757 centroid_priorities
[i
] = min_idx
;
758 distances
[min_idx
] = 0xffffffff;
761 /* Compute the final centroid priority. */
762 for (int i
= 0; i
< 8; i
++) {
764 centroid_priorities
[i
& sample_mask
] << (i
* 4);
767 return centroid_priority
<< 32 | centroid_priority
;
771 * Emit the sample locations that are specified with VK_EXT_sample_locations.
774 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
776 struct radv_sample_locations_state
*sample_location
=
777 &cmd_buffer
->state
.dynamic
.sample_location
;
778 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
779 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
780 uint32_t sample_locs_pixel
[4][2] = {};
781 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
782 uint32_t max_sample_dist
= 0;
783 uint64_t centroid_priority
;
785 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
788 /* Convert the user sample locations to hardware sample locations. */
789 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
790 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
791 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
792 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
794 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
795 for (uint32_t i
= 0; i
< 4; i
++) {
796 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
797 sample_locs_pixel
[i
]);
800 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
802 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
805 /* Compute the maximum sample distance from the specified locations. */
806 for (unsigned i
= 0; i
< 4; ++i
) {
807 for (uint32_t j
= 0; j
< num_samples
; j
++) {
808 VkOffset2D offset
= sample_locs
[i
][j
];
809 max_sample_dist
= MAX2(max_sample_dist
,
810 MAX2(abs(offset
.x
), abs(offset
.y
)));
814 /* Emit the specified user sample locations. */
815 switch (num_samples
) {
818 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
819 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
820 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
821 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
824 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
825 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
826 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
827 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
828 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
829 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
830 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
831 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
834 unreachable("invalid number of samples");
837 /* Emit the maximum sample distance and the centroid priority. */
838 radeon_set_context_reg_rmw(cs
, R_028BE0_PA_SC_AA_CONFIG
,
839 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
),
840 ~C_028BE0_MAX_SAMPLE_DIST
);
842 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
843 radeon_emit(cs
, centroid_priority
);
844 radeon_emit(cs
, centroid_priority
>> 32);
846 /* GFX9: Flush DFSM when the AA mode changes. */
847 if (cmd_buffer
->device
->dfsm_allowed
) {
848 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
849 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
852 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
856 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
857 struct radv_pipeline
*pipeline
,
858 gl_shader_stage stage
,
859 int idx
, int count
, uint32_t *values
)
861 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
862 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
863 if (loc
->sgpr_idx
== -1)
866 assert(loc
->num_sgprs
== count
);
868 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
869 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
873 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
874 struct radv_pipeline
*pipeline
)
876 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
877 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
879 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
880 cmd_buffer
->sample_positions_needed
= true;
882 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
885 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
887 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
891 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
892 struct radv_pipeline
*pipeline
)
894 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
897 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
901 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
902 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
905 bool binning_flush
= false;
906 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
907 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
908 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
909 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
910 binning_flush
= !old_pipeline
||
911 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
912 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
915 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
916 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
917 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
919 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
920 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
921 pipeline
->graphics
.binning
.db_dfsm_control
);
923 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
924 pipeline
->graphics
.binning
.db_dfsm_control
);
927 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
932 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
933 struct radv_shader_variant
*shader
)
940 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
942 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
946 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
947 struct radv_pipeline
*pipeline
,
948 bool vertex_stage_only
)
950 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
951 uint32_t mask
= state
->prefetch_L2_mask
;
953 if (vertex_stage_only
) {
954 /* Fast prefetch path for starting draws as soon as possible.
956 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
957 RADV_PREFETCH_VBO_DESCRIPTORS
);
960 if (mask
& RADV_PREFETCH_VS
)
961 radv_emit_shader_prefetch(cmd_buffer
,
962 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
964 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
965 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
967 if (mask
& RADV_PREFETCH_TCS
)
968 radv_emit_shader_prefetch(cmd_buffer
,
969 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
971 if (mask
& RADV_PREFETCH_TES
)
972 radv_emit_shader_prefetch(cmd_buffer
,
973 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
975 if (mask
& RADV_PREFETCH_GS
) {
976 radv_emit_shader_prefetch(cmd_buffer
,
977 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
978 if (radv_pipeline_has_gs_copy_shader(pipeline
))
979 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
982 if (mask
& RADV_PREFETCH_PS
)
983 radv_emit_shader_prefetch(cmd_buffer
,
984 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
986 state
->prefetch_L2_mask
&= ~mask
;
990 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
992 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
995 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
996 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
998 unsigned sx_ps_downconvert
= 0;
999 unsigned sx_blend_opt_epsilon
= 0;
1000 unsigned sx_blend_opt_control
= 0;
1002 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1005 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1006 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1007 /* We don't set the DISABLE bits, because the HW can't have holes,
1008 * so the SPI color format is set to 32-bit 1-component. */
1009 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1013 int idx
= subpass
->color_attachments
[i
].attachment
;
1014 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1016 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1017 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1018 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1019 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1021 bool has_alpha
, has_rgb
;
1023 /* Set if RGB and A are present. */
1024 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1026 if (format
== V_028C70_COLOR_8
||
1027 format
== V_028C70_COLOR_16
||
1028 format
== V_028C70_COLOR_32
)
1029 has_rgb
= !has_alpha
;
1033 /* Check the colormask and export format. */
1034 if (!(colormask
& 0x7))
1036 if (!(colormask
& 0x8))
1039 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1044 /* Disable value checking for disabled channels. */
1046 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1048 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1050 /* Enable down-conversion for 32bpp and smaller formats. */
1052 case V_028C70_COLOR_8
:
1053 case V_028C70_COLOR_8_8
:
1054 case V_028C70_COLOR_8_8_8_8
:
1055 /* For 1 and 2-channel formats, use the superset thereof. */
1056 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1057 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1058 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1059 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1060 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1064 case V_028C70_COLOR_5_6_5
:
1065 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1066 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1067 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1071 case V_028C70_COLOR_1_5_5_5
:
1072 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1073 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1074 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1078 case V_028C70_COLOR_4_4_4_4
:
1079 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1080 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1081 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1085 case V_028C70_COLOR_32
:
1086 if (swap
== V_028C70_SWAP_STD
&&
1087 spi_format
== V_028714_SPI_SHADER_32_R
)
1088 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1089 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1090 spi_format
== V_028714_SPI_SHADER_32_AR
)
1091 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1094 case V_028C70_COLOR_16
:
1095 case V_028C70_COLOR_16_16
:
1096 /* For 1-channel formats, use the superset thereof. */
1097 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1098 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1099 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1100 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1101 if (swap
== V_028C70_SWAP_STD
||
1102 swap
== V_028C70_SWAP_STD_REV
)
1103 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1105 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1109 case V_028C70_COLOR_10_11_11
:
1110 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1111 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1112 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1116 case V_028C70_COLOR_2_10_10_10
:
1117 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1118 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1119 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1125 /* Do not set the DISABLE bits for the unused attachments, as that
1126 * breaks dual source blending in SkQP and does not seem to improve
1129 if (sx_ps_downconvert
== cmd_buffer
->state
.last_sx_ps_downconvert
&&
1130 sx_blend_opt_epsilon
== cmd_buffer
->state
.last_sx_blend_opt_epsilon
&&
1131 sx_blend_opt_control
== cmd_buffer
->state
.last_sx_blend_opt_control
)
1134 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1135 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1136 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1137 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1139 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1141 cmd_buffer
->state
.last_sx_ps_downconvert
= sx_ps_downconvert
;
1142 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= sx_blend_opt_epsilon
;
1143 cmd_buffer
->state
.last_sx_blend_opt_control
= sx_blend_opt_control
;
1147 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer
*cmd_buffer
)
1149 if (!cmd_buffer
->device
->pbb_allowed
)
1152 struct radv_binning_settings settings
=
1153 radv_get_binning_settings(cmd_buffer
->device
->physical_device
);
1154 bool break_for_new_ps
=
1155 (!cmd_buffer
->state
.emitted_pipeline
||
1156 cmd_buffer
->state
.emitted_pipeline
->shaders
[MESA_SHADER_FRAGMENT
] !=
1157 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) &&
1158 (settings
.context_states_per_bin
> 1 ||
1159 settings
.persistent_states_per_bin
> 1);
1160 bool break_for_new_cb_target_mask
=
1161 (!cmd_buffer
->state
.emitted_pipeline
||
1162 cmd_buffer
->state
.emitted_pipeline
->graphics
.cb_target_mask
!=
1163 cmd_buffer
->state
.pipeline
->graphics
.cb_target_mask
) &&
1164 settings
.context_states_per_bin
> 1;
1166 if (!break_for_new_ps
&& !break_for_new_cb_target_mask
)
1169 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1170 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1174 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1176 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1178 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1181 radv_update_multisample_state(cmd_buffer
, pipeline
);
1182 radv_update_binning_state(cmd_buffer
, pipeline
);
1184 cmd_buffer
->scratch_size_per_wave_needed
= MAX2(cmd_buffer
->scratch_size_per_wave_needed
,
1185 pipeline
->scratch_bytes_per_wave
);
1186 cmd_buffer
->scratch_waves_wanted
= MAX2(cmd_buffer
->scratch_waves_wanted
,
1187 pipeline
->max_waves
);
1189 if (!cmd_buffer
->state
.emitted_pipeline
||
1190 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1191 pipeline
->graphics
.can_use_guardband
)
1192 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1194 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1196 if (!cmd_buffer
->state
.emitted_pipeline
||
1197 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1198 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1199 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1200 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1201 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1202 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1205 radv_emit_batch_break_on_new_ps(cmd_buffer
);
1207 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1208 if (!pipeline
->shaders
[i
])
1211 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1212 pipeline
->shaders
[i
]->bo
);
1215 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1216 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1217 pipeline
->gs_copy_shader
->bo
);
1219 if (unlikely(cmd_buffer
->device
->trace_bo
))
1220 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1222 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1224 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1228 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1230 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1231 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1235 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1237 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1239 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1240 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1241 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1242 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1244 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1248 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1250 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1253 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1254 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1255 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1256 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1257 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1258 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1259 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1264 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1266 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1268 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1269 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1273 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1275 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1277 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1278 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1282 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1284 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1286 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1287 R_028430_DB_STENCILREFMASK
, 2);
1288 radeon_emit(cmd_buffer
->cs
,
1289 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1290 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1291 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1292 S_028430_STENCILOPVAL(1));
1293 radeon_emit(cmd_buffer
->cs
,
1294 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1295 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1296 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1297 S_028434_STENCILOPVAL_BF(1));
1301 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1303 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1305 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1306 fui(d
->depth_bounds
.min
));
1307 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1308 fui(d
->depth_bounds
.max
));
1312 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1314 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1315 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1316 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1319 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1320 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1321 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1322 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1323 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1324 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1325 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1329 radv_emit_line_stipple(struct radv_cmd_buffer
*cmd_buffer
)
1331 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1332 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1333 uint32_t auto_reset_cntl
= 1;
1335 if (pipeline
->graphics
.topology
== VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
)
1336 auto_reset_cntl
= 2;
1338 radeon_set_context_reg(cmd_buffer
->cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1339 S_028A0C_LINE_PATTERN(d
->line_stipple
.pattern
) |
1340 S_028A0C_REPEAT_COUNT(d
->line_stipple
.factor
- 1) |
1341 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl
));
1345 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1347 struct radv_color_buffer_info
*cb
,
1348 struct radv_image_view
*iview
,
1349 VkImageLayout layout
,
1350 bool in_render_loop
)
1352 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1353 uint32_t cb_color_info
= cb
->cb_color_info
;
1354 struct radv_image
*image
= iview
->image
;
1356 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1357 radv_image_queue_family_mask(image
,
1358 cmd_buffer
->queue_family_index
,
1359 cmd_buffer
->queue_family_index
))) {
1360 cb_color_info
&= C_028C70_DCC_ENABLE
;
1363 if (radv_image_is_tc_compat_cmask(image
) &&
1364 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1365 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1366 /* If this bit is set, the FMASK decompression operation
1367 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1369 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1372 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1373 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1374 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1375 radeon_emit(cmd_buffer
->cs
, 0);
1376 radeon_emit(cmd_buffer
->cs
, 0);
1377 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1378 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1379 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1380 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1381 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1382 radeon_emit(cmd_buffer
->cs
, 0);
1383 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1384 radeon_emit(cmd_buffer
->cs
, 0);
1386 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1387 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1389 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1390 cb
->cb_color_base
>> 32);
1391 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1392 cb
->cb_color_cmask
>> 32);
1393 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1394 cb
->cb_color_fmask
>> 32);
1395 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1396 cb
->cb_dcc_base
>> 32);
1397 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1398 cb
->cb_color_attrib2
);
1399 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1400 cb
->cb_color_attrib3
);
1401 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1402 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1403 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1404 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1405 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1406 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1407 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1408 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1409 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1410 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1411 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1412 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1413 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1415 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1416 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1417 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1419 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1422 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1423 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1424 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1425 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1426 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1427 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1428 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1429 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1430 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1431 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1432 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1433 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1435 if (is_vi
) { /* DCC BASE */
1436 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1440 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1441 /* Drawing with DCC enabled also compresses colorbuffers. */
1442 VkImageSubresourceRange range
= {
1443 .aspectMask
= iview
->aspect_mask
,
1444 .baseMipLevel
= iview
->base_mip
,
1445 .levelCount
= iview
->level_count
,
1446 .baseArrayLayer
= iview
->base_layer
,
1447 .layerCount
= iview
->layer_count
,
1450 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1455 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1456 struct radv_ds_buffer_info
*ds
,
1457 const struct radv_image_view
*iview
,
1458 VkImageLayout layout
,
1459 bool in_render_loop
, bool requires_cond_exec
)
1461 const struct radv_image
*image
= iview
->image
;
1462 uint32_t db_z_info
= ds
->db_z_info
;
1463 uint32_t db_z_info_reg
;
1465 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1466 !radv_image_is_tc_compat_htile(image
))
1469 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1470 radv_image_queue_family_mask(image
,
1471 cmd_buffer
->queue_family_index
,
1472 cmd_buffer
->queue_family_index
))) {
1473 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1476 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1478 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1479 db_z_info_reg
= R_028038_DB_Z_INFO
;
1481 db_z_info_reg
= R_028040_DB_Z_INFO
;
1484 /* When we don't know the last fast clear value we need to emit a
1485 * conditional packet that will eventually skip the following
1486 * SET_CONTEXT_REG packet.
1488 if (requires_cond_exec
) {
1489 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1491 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1492 radeon_emit(cmd_buffer
->cs
, va
);
1493 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1494 radeon_emit(cmd_buffer
->cs
, 0);
1495 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1498 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1502 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1503 struct radv_ds_buffer_info
*ds
,
1504 struct radv_image_view
*iview
,
1505 VkImageLayout layout
,
1506 bool in_render_loop
)
1508 const struct radv_image
*image
= iview
->image
;
1509 uint32_t db_z_info
= ds
->db_z_info
;
1510 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1512 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1513 radv_image_queue_family_mask(image
,
1514 cmd_buffer
->queue_family_index
,
1515 cmd_buffer
->queue_family_index
))) {
1516 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1517 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1520 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1521 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1523 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1524 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1525 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1527 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1528 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1529 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1530 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1531 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1532 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1533 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1534 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1536 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1537 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1538 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1539 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1540 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1541 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1542 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1543 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1544 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1545 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1546 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1548 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1549 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1550 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1551 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1552 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1553 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1554 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1555 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1556 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1557 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1558 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1560 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1561 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1562 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1564 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1566 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1567 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1568 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1569 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1570 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1571 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1572 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1573 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1574 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1575 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1579 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1580 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1581 in_render_loop
, true);
1583 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1584 ds
->pa_su_poly_offset_db_fmt_cntl
);
1588 * Update the fast clear depth/stencil values if the image is bound as a
1589 * depth/stencil buffer.
1592 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1593 const struct radv_image_view
*iview
,
1594 VkClearDepthStencilValue ds_clear_value
,
1595 VkImageAspectFlags aspects
)
1597 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1598 const struct radv_image
*image
= iview
->image
;
1599 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1602 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1605 if (!subpass
->depth_stencil_attachment
)
1608 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1609 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1612 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1613 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1614 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1615 radeon_emit(cs
, ds_clear_value
.stencil
);
1616 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1617 } else if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1618 radeon_set_context_reg_seq(cs
, R_02802C_DB_DEPTH_CLEAR
, 1);
1619 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1621 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1622 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 1);
1623 radeon_emit(cs
, ds_clear_value
.stencil
);
1626 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1627 * only needed when clearing Z to 0.0.
1629 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1630 ds_clear_value
.depth
== 0.0) {
1631 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1632 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1634 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1635 iview
, layout
, in_render_loop
, false);
1638 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1642 * Set the clear depth/stencil values to the image's metadata.
1645 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1646 struct radv_image
*image
,
1647 const VkImageSubresourceRange
*range
,
1648 VkClearDepthStencilValue ds_clear_value
,
1649 VkImageAspectFlags aspects
)
1651 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1652 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1653 uint32_t level_count
= radv_get_levelCount(image
, range
);
1655 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1656 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1657 /* Use the fastest way when both aspects are used. */
1658 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1659 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1660 S_370_WR_CONFIRM(1) |
1661 S_370_ENGINE_SEL(V_370_PFP
));
1662 radeon_emit(cs
, va
);
1663 radeon_emit(cs
, va
>> 32);
1665 for (uint32_t l
= 0; l
< level_count
; l
++) {
1666 radeon_emit(cs
, ds_clear_value
.stencil
);
1667 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1670 /* Otherwise we need one WRITE_DATA packet per level. */
1671 for (uint32_t l
= 0; l
< level_count
; l
++) {
1672 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1675 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1676 value
= fui(ds_clear_value
.depth
);
1679 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1680 value
= ds_clear_value
.stencil
;
1683 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1684 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1685 S_370_WR_CONFIRM(1) |
1686 S_370_ENGINE_SEL(V_370_PFP
));
1687 radeon_emit(cs
, va
);
1688 radeon_emit(cs
, va
>> 32);
1689 radeon_emit(cs
, value
);
1695 * Update the TC-compat metadata value for this image.
1698 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1699 struct radv_image
*image
,
1700 const VkImageSubresourceRange
*range
,
1703 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1705 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1708 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1709 uint32_t level_count
= radv_get_levelCount(image
, range
);
1711 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1712 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1713 S_370_WR_CONFIRM(1) |
1714 S_370_ENGINE_SEL(V_370_PFP
));
1715 radeon_emit(cs
, va
);
1716 radeon_emit(cs
, va
>> 32);
1718 for (uint32_t l
= 0; l
< level_count
; l
++)
1719 radeon_emit(cs
, value
);
1723 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1724 const struct radv_image_view
*iview
,
1725 VkClearDepthStencilValue ds_clear_value
)
1727 VkImageSubresourceRange range
= {
1728 .aspectMask
= iview
->aspect_mask
,
1729 .baseMipLevel
= iview
->base_mip
,
1730 .levelCount
= iview
->level_count
,
1731 .baseArrayLayer
= iview
->base_layer
,
1732 .layerCount
= iview
->layer_count
,
1736 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1737 * depth clear value is 0.0f.
1739 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1741 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1746 * Update the clear depth/stencil values for this image.
1749 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1750 const struct radv_image_view
*iview
,
1751 VkClearDepthStencilValue ds_clear_value
,
1752 VkImageAspectFlags aspects
)
1754 VkImageSubresourceRange range
= {
1755 .aspectMask
= iview
->aspect_mask
,
1756 .baseMipLevel
= iview
->base_mip
,
1757 .levelCount
= iview
->level_count
,
1758 .baseArrayLayer
= iview
->base_layer
,
1759 .layerCount
= iview
->layer_count
,
1761 struct radv_image
*image
= iview
->image
;
1763 assert(radv_image_has_htile(image
));
1765 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1766 ds_clear_value
, aspects
);
1768 if (radv_image_is_tc_compat_htile(image
) &&
1769 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1770 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1774 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1779 * Load the clear depth/stencil values from the image's metadata.
1782 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1783 const struct radv_image_view
*iview
)
1785 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1786 const struct radv_image
*image
= iview
->image
;
1787 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1788 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
1789 unsigned reg_offset
= 0, reg_count
= 0;
1791 if (!radv_image_has_htile(image
))
1794 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1800 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1803 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1805 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1806 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX
, 3, 0));
1807 radeon_emit(cs
, va
);
1808 radeon_emit(cs
, va
>> 32);
1809 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1810 radeon_emit(cs
, reg_count
);
1812 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1813 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1814 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1815 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1816 radeon_emit(cs
, va
);
1817 radeon_emit(cs
, va
>> 32);
1818 radeon_emit(cs
, reg
>> 2);
1821 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1827 * With DCC some colors don't require CMASK elimination before being
1828 * used as a texture. This sets a predicate value to determine if the
1829 * cmask eliminate is required.
1832 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1833 struct radv_image
*image
,
1834 const VkImageSubresourceRange
*range
, bool value
)
1836 uint64_t pred_val
= value
;
1837 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1838 uint32_t level_count
= radv_get_levelCount(image
, range
);
1839 uint32_t count
= 2 * level_count
;
1841 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1843 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1844 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1845 S_370_WR_CONFIRM(1) |
1846 S_370_ENGINE_SEL(V_370_PFP
));
1847 radeon_emit(cmd_buffer
->cs
, va
);
1848 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1850 for (uint32_t l
= 0; l
< level_count
; l
++) {
1851 radeon_emit(cmd_buffer
->cs
, pred_val
);
1852 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1857 * Update the DCC predicate to reflect the compression state.
1860 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1861 struct radv_image
*image
,
1862 const VkImageSubresourceRange
*range
, bool value
)
1864 uint64_t pred_val
= value
;
1865 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1866 uint32_t level_count
= radv_get_levelCount(image
, range
);
1867 uint32_t count
= 2 * level_count
;
1869 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1871 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1872 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1873 S_370_WR_CONFIRM(1) |
1874 S_370_ENGINE_SEL(V_370_PFP
));
1875 radeon_emit(cmd_buffer
->cs
, va
);
1876 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1878 for (uint32_t l
= 0; l
< level_count
; l
++) {
1879 radeon_emit(cmd_buffer
->cs
, pred_val
);
1880 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1885 * Update the fast clear color values if the image is bound as a color buffer.
1888 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1889 struct radv_image
*image
,
1891 uint32_t color_values
[2])
1893 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1894 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1897 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1900 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1901 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1904 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1907 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1908 radeon_emit(cs
, color_values
[0]);
1909 radeon_emit(cs
, color_values
[1]);
1911 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1915 * Set the clear color values to the image's metadata.
1918 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1919 struct radv_image
*image
,
1920 const VkImageSubresourceRange
*range
,
1921 uint32_t color_values
[2])
1923 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1924 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1925 uint32_t level_count
= radv_get_levelCount(image
, range
);
1926 uint32_t count
= 2 * level_count
;
1928 assert(radv_image_has_cmask(image
) ||
1929 radv_dcc_enabled(image
, range
->baseMipLevel
));
1931 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1932 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1933 S_370_WR_CONFIRM(1) |
1934 S_370_ENGINE_SEL(V_370_PFP
));
1935 radeon_emit(cs
, va
);
1936 radeon_emit(cs
, va
>> 32);
1938 for (uint32_t l
= 0; l
< level_count
; l
++) {
1939 radeon_emit(cs
, color_values
[0]);
1940 radeon_emit(cs
, color_values
[1]);
1945 * Update the clear color values for this image.
1948 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1949 const struct radv_image_view
*iview
,
1951 uint32_t color_values
[2])
1953 struct radv_image
*image
= iview
->image
;
1954 VkImageSubresourceRange range
= {
1955 .aspectMask
= iview
->aspect_mask
,
1956 .baseMipLevel
= iview
->base_mip
,
1957 .levelCount
= iview
->level_count
,
1958 .baseArrayLayer
= iview
->base_layer
,
1959 .layerCount
= iview
->layer_count
,
1962 assert(radv_image_has_cmask(image
) ||
1963 radv_dcc_enabled(image
, iview
->base_mip
));
1965 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1967 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1972 * Load the clear color values from the image's metadata.
1975 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1976 struct radv_image_view
*iview
,
1979 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1980 struct radv_image
*image
= iview
->image
;
1981 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1983 if (!radv_image_has_cmask(image
) &&
1984 !radv_dcc_enabled(image
, iview
->base_mip
))
1987 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1989 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
1990 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX
, 3, cmd_buffer
->state
.predicating
));
1991 radeon_emit(cs
, va
);
1992 radeon_emit(cs
, va
>> 32);
1993 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1996 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1997 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1998 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1999 COPY_DATA_COUNT_SEL
);
2000 radeon_emit(cs
, va
);
2001 radeon_emit(cs
, va
>> 32);
2002 radeon_emit(cs
, reg
>> 2);
2005 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
2011 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2014 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
2015 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2017 /* this may happen for inherited secondary recording */
2021 for (i
= 0; i
< 8; ++i
) {
2022 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
2023 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2024 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2028 int idx
= subpass
->color_attachments
[i
].attachment
;
2029 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2030 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
2031 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
2033 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
2035 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
2036 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
2037 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
2039 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
2042 if (subpass
->depth_stencil_attachment
) {
2043 int idx
= subpass
->depth_stencil_attachment
->attachment
;
2044 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
2045 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
2046 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2047 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
2049 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
2051 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
2052 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2053 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
2055 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
2057 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
2058 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2060 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2062 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2063 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2065 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2066 S_028208_BR_X(framebuffer
->width
) |
2067 S_028208_BR_Y(framebuffer
->height
));
2069 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2070 bool disable_constant_encode
=
2071 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2072 enum chip_class chip_class
=
2073 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2074 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2076 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2077 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2078 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2079 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2082 if (cmd_buffer
->device
->dfsm_allowed
) {
2083 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2084 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2087 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2091 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
, bool indirect
)
2093 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2094 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2096 if (state
->index_type
!= state
->last_index_type
) {
2097 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2098 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2099 cs
, R_03090C_VGT_INDEX_TYPE
,
2100 2, state
->index_type
);
2102 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2103 radeon_emit(cs
, state
->index_type
);
2106 state
->last_index_type
= state
->index_type
;
2109 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2110 * the index_va and max_index_count already. */
2114 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2115 radeon_emit(cs
, state
->index_va
);
2116 radeon_emit(cs
, state
->index_va
>> 32);
2118 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2119 radeon_emit(cs
, state
->max_index_count
);
2121 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2124 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2126 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2127 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2128 uint32_t pa_sc_mode_cntl_1
=
2129 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2130 uint32_t db_count_control
;
2132 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2133 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2134 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2135 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2136 has_perfect_queries
) {
2137 /* Re-enable out-of-order rasterization if the
2138 * bound pipeline supports it and if it's has
2139 * been disabled before starting any perfect
2140 * occlusion queries.
2142 radeon_set_context_reg(cmd_buffer
->cs
,
2143 R_028A4C_PA_SC_MODE_CNTL_1
,
2147 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2149 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2150 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2151 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2153 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2155 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2156 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2157 S_028004_SAMPLE_RATE(sample_rate
) |
2158 S_028004_ZPASS_ENABLE(1) |
2159 S_028004_SLICE_EVEN_ENABLE(1) |
2160 S_028004_SLICE_ODD_ENABLE(1);
2162 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2163 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2164 has_perfect_queries
) {
2165 /* If the bound pipeline has enabled
2166 * out-of-order rasterization, we should
2167 * disable it before starting any perfect
2168 * occlusion queries.
2170 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2172 radeon_set_context_reg(cmd_buffer
->cs
,
2173 R_028A4C_PA_SC_MODE_CNTL_1
,
2177 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2178 S_028004_SAMPLE_RATE(sample_rate
);
2182 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2184 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2188 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2190 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2192 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2193 radv_emit_viewport(cmd_buffer
);
2195 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2196 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2197 radv_emit_scissor(cmd_buffer
);
2199 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2200 radv_emit_line_width(cmd_buffer
);
2202 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2203 radv_emit_blend_constants(cmd_buffer
);
2205 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2206 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2207 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2208 radv_emit_stencil(cmd_buffer
);
2210 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2211 radv_emit_depth_bounds(cmd_buffer
);
2213 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2214 radv_emit_depth_bias(cmd_buffer
);
2216 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2217 radv_emit_discard_rectangle(cmd_buffer
);
2219 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2220 radv_emit_sample_locations(cmd_buffer
);
2222 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
)
2223 radv_emit_line_stipple(cmd_buffer
);
2225 cmd_buffer
->state
.dirty
&= ~states
;
2229 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2230 VkPipelineBindPoint bind_point
)
2232 struct radv_descriptor_state
*descriptors_state
=
2233 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2234 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2237 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2242 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2243 set
->va
+= bo_offset
;
2247 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2248 VkPipelineBindPoint bind_point
)
2250 struct radv_descriptor_state
*descriptors_state
=
2251 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2252 uint32_t size
= MAX_SETS
* 4;
2256 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2257 256, &offset
, &ptr
))
2260 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2261 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2262 uint64_t set_va
= 0;
2263 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2264 if (descriptors_state
->valid
& (1u << i
))
2266 uptr
[0] = set_va
& 0xffffffff;
2269 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2272 if (cmd_buffer
->state
.pipeline
) {
2273 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2274 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2275 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2277 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2278 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2279 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2281 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2282 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2283 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2285 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2286 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2287 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2289 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2290 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2291 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2294 if (cmd_buffer
->state
.compute_pipeline
)
2295 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2296 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2300 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2301 VkShaderStageFlags stages
)
2303 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2304 VK_PIPELINE_BIND_POINT_COMPUTE
:
2305 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2306 struct radv_descriptor_state
*descriptors_state
=
2307 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2308 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2309 bool flush_indirect_descriptors
;
2311 if (!descriptors_state
->dirty
)
2314 if (descriptors_state
->push_dirty
)
2315 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2317 flush_indirect_descriptors
=
2318 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2319 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2320 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2321 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2323 if (flush_indirect_descriptors
)
2324 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2326 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2328 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2330 if (cmd_buffer
->state
.pipeline
) {
2331 radv_foreach_stage(stage
, stages
) {
2332 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2335 radv_emit_descriptor_pointers(cmd_buffer
,
2336 cmd_buffer
->state
.pipeline
,
2337 descriptors_state
, stage
);
2341 if (cmd_buffer
->state
.compute_pipeline
&&
2342 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2343 radv_emit_descriptor_pointers(cmd_buffer
,
2344 cmd_buffer
->state
.compute_pipeline
,
2346 MESA_SHADER_COMPUTE
);
2349 descriptors_state
->dirty
= 0;
2350 descriptors_state
->push_dirty
= false;
2352 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2354 if (unlikely(cmd_buffer
->device
->trace_bo
))
2355 radv_save_descriptors(cmd_buffer
, bind_point
);
2359 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2360 VkShaderStageFlags stages
)
2362 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2363 ? cmd_buffer
->state
.compute_pipeline
2364 : cmd_buffer
->state
.pipeline
;
2365 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2366 VK_PIPELINE_BIND_POINT_COMPUTE
:
2367 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2368 struct radv_descriptor_state
*descriptors_state
=
2369 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2370 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2371 struct radv_shader_variant
*shader
, *prev_shader
;
2372 bool need_push_constants
= false;
2377 stages
&= cmd_buffer
->push_constant_stages
;
2379 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2382 radv_foreach_stage(stage
, stages
) {
2383 shader
= radv_get_shader(pipeline
, stage
);
2387 need_push_constants
|= shader
->info
.loads_push_constants
;
2388 need_push_constants
|= shader
->info
.loads_dynamic_offsets
;
2390 uint8_t base
= shader
->info
.base_inline_push_consts
;
2391 uint8_t count
= shader
->info
.num_inline_push_consts
;
2393 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2394 AC_UD_INLINE_PUSH_CONSTANTS
,
2396 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2399 if (need_push_constants
) {
2400 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2401 16 * layout
->dynamic_offset_count
,
2402 256, &offset
, &ptr
))
2405 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2406 memcpy((char*)ptr
+ layout
->push_constant_size
,
2407 descriptors_state
->dynamic_buffers
,
2408 16 * layout
->dynamic_offset_count
);
2410 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2413 ASSERTED
unsigned cdw_max
=
2414 radeon_check_space(cmd_buffer
->device
->ws
,
2415 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2418 radv_foreach_stage(stage
, stages
) {
2419 shader
= radv_get_shader(pipeline
, stage
);
2421 /* Avoid redundantly emitting the address for merged stages. */
2422 if (shader
&& shader
!= prev_shader
) {
2423 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2424 AC_UD_PUSH_CONSTANTS
, va
);
2426 prev_shader
= shader
;
2429 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2432 cmd_buffer
->push_constant_stages
&= ~stages
;
2436 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2437 bool pipeline_is_dirty
)
2439 if ((pipeline_is_dirty
||
2440 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2441 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2442 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2446 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2449 /* allocate some descriptor state for vertex buffers */
2450 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2451 &vb_offset
, &vb_ptr
))
2454 for (i
= 0; i
< count
; i
++) {
2455 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2457 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2458 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2459 unsigned num_records
;
2464 va
= radv_buffer_get_va(buffer
->bo
);
2466 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2467 va
+= offset
+ buffer
->offset
;
2469 num_records
= buffer
->size
- offset
;
2470 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
)
2471 num_records
/= stride
;
2474 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2475 desc
[2] = num_records
;
2476 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2477 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2478 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2479 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2481 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2482 /* OOB_SELECT chooses the out-of-bounds check:
2483 * - 1: index >= NUM_RECORDS (Structured)
2484 * - 3: offset >= NUM_RECORDS (Raw)
2486 int oob_select
= stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
;
2488 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2489 S_008F0C_OOB_SELECT(oob_select
) |
2490 S_008F0C_RESOURCE_LEVEL(1);
2492 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2493 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2497 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2500 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2501 AC_UD_VS_VERTEX_BUFFERS
, va
);
2503 cmd_buffer
->state
.vb_va
= va
;
2504 cmd_buffer
->state
.vb_size
= count
* 16;
2505 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2507 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2511 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2513 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2514 struct radv_userdata_info
*loc
;
2517 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2518 if (!radv_get_shader(pipeline
, stage
))
2521 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2522 AC_UD_STREAMOUT_BUFFERS
);
2523 if (loc
->sgpr_idx
== -1)
2526 base_reg
= pipeline
->user_data_0
[stage
];
2528 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2529 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2532 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2533 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2534 if (loc
->sgpr_idx
!= -1) {
2535 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2537 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2538 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2544 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2546 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2547 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2548 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2553 /* Allocate some descriptor state for streamout buffers. */
2554 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2555 MAX_SO_BUFFERS
* 16, 256,
2556 &so_offset
, &so_ptr
))
2559 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2560 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2561 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2563 if (!(so
->enabled_mask
& (1 << i
)))
2566 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2570 /* Set the descriptor.
2572 * On GFX8, the format must be non-INVALID, otherwise
2573 * the buffer will be considered not bound and store
2574 * instructions will be no-ops.
2576 uint32_t size
= 0xffffffff;
2578 /* Compute the correct buffer size for NGG streamout
2579 * because it's used to determine the max emit per
2582 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2583 size
= buffer
->size
- sb
[i
].offset
;
2586 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2588 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2589 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2590 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2591 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2593 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2594 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2595 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
2596 S_008F0C_RESOURCE_LEVEL(1);
2598 desc
[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2602 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2605 radv_emit_streamout_buffers(cmd_buffer
, va
);
2608 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2612 radv_flush_ngg_gs_state(struct radv_cmd_buffer
*cmd_buffer
)
2614 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2615 struct radv_userdata_info
*loc
;
2616 uint32_t ngg_gs_state
= 0;
2619 if (!radv_pipeline_has_gs(pipeline
) ||
2620 !radv_pipeline_has_ngg(pipeline
))
2623 /* By default NGG GS queries are disabled but they are enabled if the
2624 * command buffer has active GDS queries or if it's a secondary command
2625 * buffer that inherits the number of generated primitives.
2627 if (cmd_buffer
->state
.active_pipeline_gds_queries
||
2628 (cmd_buffer
->state
.inherited_pipeline_statistics
& VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
))
2631 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_GEOMETRY
,
2632 AC_UD_NGG_GS_STATE
);
2633 base_reg
= pipeline
->user_data_0
[MESA_SHADER_GEOMETRY
];
2634 assert(loc
->sgpr_idx
!= -1);
2636 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
2641 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2643 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2644 radv_flush_streamout_descriptors(cmd_buffer
);
2645 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2646 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2647 radv_flush_ngg_gs_state(cmd_buffer
);
2650 struct radv_draw_info
{
2652 * Number of vertices.
2657 * Index of the first vertex.
2659 int32_t vertex_offset
;
2662 * First instance id.
2664 uint32_t first_instance
;
2667 * Number of instances.
2669 uint32_t instance_count
;
2672 * First index (indexed draws only).
2674 uint32_t first_index
;
2677 * Whether it's an indexed draw.
2682 * Indirect draw parameters resource.
2684 struct radv_buffer
*indirect
;
2685 uint64_t indirect_offset
;
2689 * Draw count parameters resource.
2691 struct radv_buffer
*count_buffer
;
2692 uint64_t count_buffer_offset
;
2695 * Stream output parameters resource.
2697 struct radv_buffer
*strmout_buffer
;
2698 uint64_t strmout_buffer_offset
;
2702 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2704 switch (cmd_buffer
->state
.index_type
) {
2705 case V_028A7C_VGT_INDEX_8
:
2707 case V_028A7C_VGT_INDEX_16
:
2709 case V_028A7C_VGT_INDEX_32
:
2712 unreachable("invalid index type");
2717 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2718 bool instanced_draw
, bool indirect_draw
,
2719 bool count_from_stream_output
,
2720 uint32_t draw_vertex_count
)
2722 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2723 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2724 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2725 unsigned ia_multi_vgt_param
;
2727 ia_multi_vgt_param
=
2728 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2730 count_from_stream_output
,
2733 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2734 if (info
->chip_class
== GFX9
) {
2735 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2737 R_030960_IA_MULTI_VGT_PARAM
,
2738 4, ia_multi_vgt_param
);
2739 } else if (info
->chip_class
>= GFX7
) {
2740 radeon_set_context_reg_idx(cs
,
2741 R_028AA8_IA_MULTI_VGT_PARAM
,
2742 1, ia_multi_vgt_param
);
2744 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2745 ia_multi_vgt_param
);
2747 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2752 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2753 const struct radv_draw_info
*draw_info
)
2755 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2756 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2757 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2758 int32_t primitive_reset_en
;
2761 if (info
->chip_class
< GFX10
) {
2762 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2763 draw_info
->indirect
,
2764 !!draw_info
->strmout_buffer
,
2765 draw_info
->indirect
? 0 : draw_info
->count
);
2768 /* Primitive restart. */
2769 primitive_reset_en
=
2770 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2772 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2773 state
->last_primitive_reset_en
= primitive_reset_en
;
2774 if (info
->chip_class
>= GFX9
) {
2775 radeon_set_uconfig_reg(cs
,
2776 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2777 primitive_reset_en
);
2779 radeon_set_context_reg(cs
,
2780 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2781 primitive_reset_en
);
2785 if (primitive_reset_en
) {
2786 uint32_t primitive_reset_index
=
2787 radv_get_primitive_reset_index(cmd_buffer
);
2789 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2790 radeon_set_context_reg(cs
,
2791 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2792 primitive_reset_index
);
2793 state
->last_primitive_reset_index
= primitive_reset_index
;
2797 if (draw_info
->strmout_buffer
) {
2798 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2800 va
+= draw_info
->strmout_buffer
->offset
+
2801 draw_info
->strmout_buffer_offset
;
2803 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2806 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2807 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2808 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2809 COPY_DATA_WR_CONFIRM
);
2810 radeon_emit(cs
, va
);
2811 radeon_emit(cs
, va
>> 32);
2812 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2813 radeon_emit(cs
, 0); /* unused */
2815 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2819 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2820 VkPipelineStageFlags src_stage_mask
)
2822 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2823 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2824 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2825 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2826 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2829 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2830 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2831 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2832 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2833 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2834 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2835 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2836 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2837 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2838 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2839 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2840 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2841 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2842 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2843 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2844 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2845 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2849 static enum radv_cmd_flush_bits
2850 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2851 VkAccessFlags src_flags
,
2852 struct radv_image
*image
)
2854 bool flush_CB_meta
= true, flush_DB_meta
= true;
2855 enum radv_cmd_flush_bits flush_bits
= 0;
2859 if (!radv_image_has_CB_metadata(image
))
2860 flush_CB_meta
= false;
2861 if (!radv_image_has_htile(image
))
2862 flush_DB_meta
= false;
2865 for_each_bit(b
, src_flags
) {
2866 switch ((VkAccessFlagBits
)(1 << b
)) {
2867 case VK_ACCESS_SHADER_WRITE_BIT
:
2868 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2869 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2870 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2872 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2873 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2875 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2877 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2878 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2880 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2882 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2883 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2884 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2885 RADV_CMD_FLAG_INV_L2
;
2888 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2890 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2899 static enum radv_cmd_flush_bits
2900 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2901 VkAccessFlags dst_flags
,
2902 struct radv_image
*image
)
2904 bool flush_CB_meta
= true, flush_DB_meta
= true;
2905 enum radv_cmd_flush_bits flush_bits
= 0;
2906 bool flush_CB
= true, flush_DB
= true;
2907 bool image_is_coherent
= false;
2911 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2916 if (!radv_image_has_CB_metadata(image
))
2917 flush_CB_meta
= false;
2918 if (!radv_image_has_htile(image
))
2919 flush_DB_meta
= false;
2921 /* TODO: implement shader coherent for GFX10 */
2923 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2924 if (image
->info
.samples
== 1 &&
2925 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2926 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2927 !vk_format_is_stencil(image
->vk_format
)) {
2928 /* Single-sample color and single-sample depth
2929 * (not stencil) are coherent with shaders on
2932 image_is_coherent
= true;
2937 for_each_bit(b
, dst_flags
) {
2938 switch ((VkAccessFlagBits
)(1 << b
)) {
2939 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2940 case VK_ACCESS_INDEX_READ_BIT
:
2941 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2943 case VK_ACCESS_UNIFORM_READ_BIT
:
2944 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2946 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2947 case VK_ACCESS_TRANSFER_READ_BIT
:
2948 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2949 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2950 RADV_CMD_FLAG_INV_L2
;
2952 case VK_ACCESS_SHADER_READ_BIT
:
2953 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2954 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2955 * invalidate the scalar cache. */
2956 if (cmd_buffer
->device
->physical_device
->use_aco
&&
2957 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2958 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
2960 if (!image_is_coherent
)
2961 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2963 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2965 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2967 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2969 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2971 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2973 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2982 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2983 const struct radv_subpass_barrier
*barrier
)
2985 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2987 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2988 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2993 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2995 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2996 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2998 /* The id of this subpass shouldn't exceed the number of subpasses in
2999 * this render pass minus 1.
3001 assert(subpass_id
< state
->pass
->subpass_count
);
3005 static struct radv_sample_locations_state
*
3006 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3010 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3011 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3012 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
3014 if (view
->image
->info
.samples
== 1)
3017 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
3018 /* Return the initial sample locations if this is the initial
3019 * layout transition of the given subpass attachemnt.
3021 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
3022 return &state
->attachments
[att_idx
].sample_location
;
3024 /* Otherwise return the subpass sample locations if defined. */
3025 if (state
->subpass_sample_locs
) {
3026 /* Because the driver sets the current subpass before
3027 * initial layout transitions, we should use the sample
3028 * locations from the previous subpass to avoid an
3029 * off-by-one problem. Otherwise, use the sample
3030 * locations for the current subpass for final layout
3036 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
3037 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
3038 return &state
->subpass_sample_locs
[i
].sample_location
;
3046 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3047 struct radv_subpass_attachment att
,
3050 unsigned idx
= att
.attachment
;
3051 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
3052 struct radv_sample_locations_state
*sample_locs
;
3053 VkImageSubresourceRange range
;
3054 range
.aspectMask
= view
->aspect_mask
;
3055 range
.baseMipLevel
= view
->base_mip
;
3056 range
.levelCount
= 1;
3057 range
.baseArrayLayer
= view
->base_layer
;
3058 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
3060 if (cmd_buffer
->state
.subpass
->view_mask
) {
3061 /* If the current subpass uses multiview, the driver might have
3062 * performed a fast color/depth clear to the whole image
3063 * (including all layers). To make sure the driver will
3064 * decompress the image correctly (if needed), we have to
3065 * account for the "real" number of layers. If the view mask is
3066 * sparse, this will decompress more layers than needed.
3068 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
3071 /* Get the subpass sample locations for the given attachment, if NULL
3072 * is returned the driver will use the default HW locations.
3074 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
3077 /* Determine if the subpass uses separate depth/stencil layouts. */
3078 bool uses_separate_depth_stencil_layouts
= false;
3079 if ((cmd_buffer
->state
.attachments
[idx
].current_layout
!=
3080 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
) ||
3081 (att
.layout
!= att
.stencil_layout
)) {
3082 uses_separate_depth_stencil_layouts
= true;
3085 /* For separate layouts, perform depth and stencil transitions
3088 if (uses_separate_depth_stencil_layouts
&&
3089 (range
.aspectMask
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
3090 VK_IMAGE_ASPECT_STENCIL_BIT
))) {
3091 /* Depth-only transitions. */
3092 range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3093 radv_handle_image_transition(cmd_buffer
,
3095 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3096 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3097 att
.layout
, att
.in_render_loop
,
3098 0, 0, &range
, sample_locs
);
3100 /* Stencil-only transitions. */
3101 range
.aspectMask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
3102 radv_handle_image_transition(cmd_buffer
,
3104 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
,
3105 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3106 att
.stencil_layout
, att
.in_render_loop
,
3107 0, 0, &range
, sample_locs
);
3109 radv_handle_image_transition(cmd_buffer
,
3111 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3112 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3113 att
.layout
, att
.in_render_loop
,
3114 0, 0, &range
, sample_locs
);
3117 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
3118 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
= att
.stencil_layout
;
3119 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
3125 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3126 const struct radv_subpass
*subpass
)
3128 cmd_buffer
->state
.subpass
= subpass
;
3130 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
3134 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3135 struct radv_render_pass
*pass
,
3136 const VkRenderPassBeginInfo
*info
)
3138 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
3139 vk_find_struct_const(info
->pNext
,
3140 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
3141 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3144 state
->subpass_sample_locs
= NULL
;
3148 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3149 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3150 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3151 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3152 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3154 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3156 /* From the Vulkan spec 1.1.108:
3158 * "If the image referenced by the framebuffer attachment at
3159 * index attachmentIndex was not created with
3160 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3161 * then the values specified in sampleLocationsInfo are
3164 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3167 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3168 &att_sample_locs
->sampleLocationsInfo
;
3170 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3171 sample_locs_info
->sampleLocationsPerPixel
;
3172 state
->attachments
[att_idx
].sample_location
.grid_size
=
3173 sample_locs_info
->sampleLocationGridSize
;
3174 state
->attachments
[att_idx
].sample_location
.count
=
3175 sample_locs_info
->sampleLocationsCount
;
3176 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3177 sample_locs_info
->pSampleLocations
,
3178 sample_locs_info
->sampleLocationsCount
);
3181 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3182 sample_locs
->postSubpassSampleLocationsCount
*
3183 sizeof(state
->subpass_sample_locs
[0]),
3184 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3185 if (state
->subpass_sample_locs
== NULL
) {
3186 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3187 return cmd_buffer
->record_result
;
3190 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3192 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3193 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3194 &sample_locs
->pPostSubpassSampleLocations
[i
];
3195 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3196 &subpass_sample_locs_info
->sampleLocationsInfo
;
3198 state
->subpass_sample_locs
[i
].subpass_idx
=
3199 subpass_sample_locs_info
->subpassIndex
;
3200 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3201 sample_locs_info
->sampleLocationsPerPixel
;
3202 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3203 sample_locs_info
->sampleLocationGridSize
;
3204 state
->subpass_sample_locs
[i
].sample_location
.count
=
3205 sample_locs_info
->sampleLocationsCount
;
3206 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3207 sample_locs_info
->pSampleLocations
,
3208 sample_locs_info
->sampleLocationsCount
);
3215 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3216 struct radv_render_pass
*pass
,
3217 const VkRenderPassBeginInfo
*info
)
3219 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3220 const struct VkRenderPassAttachmentBeginInfo
*attachment_info
= NULL
;
3223 attachment_info
= vk_find_struct_const(info
->pNext
,
3224 RENDER_PASS_ATTACHMENT_BEGIN_INFO
);
3228 if (pass
->attachment_count
== 0) {
3229 state
->attachments
= NULL
;
3233 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3234 pass
->attachment_count
*
3235 sizeof(state
->attachments
[0]),
3236 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3237 if (state
->attachments
== NULL
) {
3238 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3239 return cmd_buffer
->record_result
;
3242 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3243 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3244 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3245 VkImageAspectFlags clear_aspects
= 0;
3247 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3248 /* color attachment */
3249 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3250 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3253 /* depthstencil attachment */
3254 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3255 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3256 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3257 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3258 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3259 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3261 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3262 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3263 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3267 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3268 state
->attachments
[i
].cleared_views
= 0;
3269 if (clear_aspects
&& info
) {
3270 assert(info
->clearValueCount
> i
);
3271 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3274 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3275 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
3276 state
->attachments
[i
].sample_location
.count
= 0;
3278 struct radv_image_view
*iview
;
3279 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3280 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3282 iview
= state
->framebuffer
->attachments
[i
];
3285 state
->attachments
[i
].iview
= iview
;
3286 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3287 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3289 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3296 VkResult
radv_AllocateCommandBuffers(
3298 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3299 VkCommandBuffer
*pCommandBuffers
)
3301 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3302 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3304 VkResult result
= VK_SUCCESS
;
3307 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3309 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
3310 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3312 list_del(&cmd_buffer
->pool_link
);
3313 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3315 result
= radv_reset_cmd_buffer(cmd_buffer
);
3316 cmd_buffer
->level
= pAllocateInfo
->level
;
3318 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3320 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3321 &pCommandBuffers
[i
]);
3323 if (result
!= VK_SUCCESS
)
3327 if (result
!= VK_SUCCESS
) {
3328 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3329 i
, pCommandBuffers
);
3331 /* From the Vulkan 1.0.66 spec:
3333 * "vkAllocateCommandBuffers can be used to create multiple
3334 * command buffers. If the creation of any of those command
3335 * buffers fails, the implementation must destroy all
3336 * successfully created command buffer objects from this
3337 * command, set all entries of the pCommandBuffers array to
3338 * NULL and return the error."
3340 memset(pCommandBuffers
, 0,
3341 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3347 void radv_FreeCommandBuffers(
3349 VkCommandPool commandPool
,
3350 uint32_t commandBufferCount
,
3351 const VkCommandBuffer
*pCommandBuffers
)
3353 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3354 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3357 if (cmd_buffer
->pool
) {
3358 list_del(&cmd_buffer
->pool_link
);
3359 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3361 radv_cmd_buffer_destroy(cmd_buffer
);
3367 VkResult
radv_ResetCommandBuffer(
3368 VkCommandBuffer commandBuffer
,
3369 VkCommandBufferResetFlags flags
)
3371 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3372 return radv_reset_cmd_buffer(cmd_buffer
);
3375 VkResult
radv_BeginCommandBuffer(
3376 VkCommandBuffer commandBuffer
,
3377 const VkCommandBufferBeginInfo
*pBeginInfo
)
3379 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3380 VkResult result
= VK_SUCCESS
;
3382 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3383 /* If the command buffer has already been resetted with
3384 * vkResetCommandBuffer, no need to do it again.
3386 result
= radv_reset_cmd_buffer(cmd_buffer
);
3387 if (result
!= VK_SUCCESS
)
3391 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3392 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3393 cmd_buffer
->state
.last_index_type
= -1;
3394 cmd_buffer
->state
.last_num_instances
= -1;
3395 cmd_buffer
->state
.last_vertex_offset
= -1;
3396 cmd_buffer
->state
.last_first_instance
= -1;
3397 cmd_buffer
->state
.predication_type
= -1;
3398 cmd_buffer
->state
.last_sx_ps_downconvert
= -1;
3399 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= -1;
3400 cmd_buffer
->state
.last_sx_blend_opt_control
= -1;
3401 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3403 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3404 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3405 assert(pBeginInfo
->pInheritanceInfo
);
3406 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3407 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3409 struct radv_subpass
*subpass
=
3410 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3412 if (cmd_buffer
->state
.framebuffer
) {
3413 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3414 if (result
!= VK_SUCCESS
)
3418 cmd_buffer
->state
.inherited_pipeline_statistics
=
3419 pBeginInfo
->pInheritanceInfo
->pipelineStatistics
;
3421 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3424 if (unlikely(cmd_buffer
->device
->trace_bo
))
3425 radv_cmd_buffer_trace_emit(cmd_buffer
);
3427 radv_describe_begin_cmd_buffer(cmd_buffer
);
3429 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3434 void radv_CmdBindVertexBuffers(
3435 VkCommandBuffer commandBuffer
,
3436 uint32_t firstBinding
,
3437 uint32_t bindingCount
,
3438 const VkBuffer
* pBuffers
,
3439 const VkDeviceSize
* pOffsets
)
3441 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3442 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3443 bool changed
= false;
3445 /* We have to defer setting up vertex buffer since we need the buffer
3446 * stride from the pipeline. */
3448 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3449 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3450 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBuffers
[i
]);
3451 uint32_t idx
= firstBinding
+ i
;
3454 (vb
[idx
].buffer
!= buffer
||
3455 vb
[idx
].offset
!= pOffsets
[i
])) {
3459 vb
[idx
].buffer
= buffer
;
3460 vb
[idx
].offset
= pOffsets
[i
];
3463 radv_cs_add_buffer(cmd_buffer
->device
->ws
,
3464 cmd_buffer
->cs
, vb
[idx
].buffer
->bo
);
3469 /* No state changes. */
3473 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3477 vk_to_index_type(VkIndexType type
)
3480 case VK_INDEX_TYPE_UINT8_EXT
:
3481 return V_028A7C_VGT_INDEX_8
;
3482 case VK_INDEX_TYPE_UINT16
:
3483 return V_028A7C_VGT_INDEX_16
;
3484 case VK_INDEX_TYPE_UINT32
:
3485 return V_028A7C_VGT_INDEX_32
;
3487 unreachable("invalid index type");
3492 radv_get_vgt_index_size(uint32_t type
)
3495 case V_028A7C_VGT_INDEX_8
:
3497 case V_028A7C_VGT_INDEX_16
:
3499 case V_028A7C_VGT_INDEX_32
:
3502 unreachable("invalid index type");
3506 void radv_CmdBindIndexBuffer(
3507 VkCommandBuffer commandBuffer
,
3509 VkDeviceSize offset
,
3510 VkIndexType indexType
)
3512 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3513 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3515 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3516 cmd_buffer
->state
.index_offset
== offset
&&
3517 cmd_buffer
->state
.index_type
== indexType
) {
3518 /* No state changes. */
3522 cmd_buffer
->state
.index_buffer
= index_buffer
;
3523 cmd_buffer
->state
.index_offset
= offset
;
3524 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3525 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3526 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3528 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3529 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3530 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3531 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3536 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3537 VkPipelineBindPoint bind_point
,
3538 struct radv_descriptor_set
*set
, unsigned idx
)
3540 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3542 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3545 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3547 if (!cmd_buffer
->device
->use_global_bo_list
) {
3548 for (unsigned j
= 0; j
< set
->buffer_count
; ++j
)
3549 if (set
->descriptors
[j
])
3550 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3554 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3557 void radv_CmdBindDescriptorSets(
3558 VkCommandBuffer commandBuffer
,
3559 VkPipelineBindPoint pipelineBindPoint
,
3560 VkPipelineLayout _layout
,
3562 uint32_t descriptorSetCount
,
3563 const VkDescriptorSet
* pDescriptorSets
,
3564 uint32_t dynamicOffsetCount
,
3565 const uint32_t* pDynamicOffsets
)
3567 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3568 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3569 unsigned dyn_idx
= 0;
3571 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3572 struct radv_descriptor_state
*descriptors_state
=
3573 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3575 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3576 unsigned idx
= i
+ firstSet
;
3577 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3579 /* If the set is already bound we only need to update the
3580 * (potentially changed) dynamic offsets. */
3581 if (descriptors_state
->sets
[idx
] != set
||
3582 !(descriptors_state
->valid
& (1u << idx
))) {
3583 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3586 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3587 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3588 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3589 assert(dyn_idx
< dynamicOffsetCount
);
3591 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3592 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3594 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3595 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3596 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3597 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3598 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3599 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3601 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3602 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3603 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3604 S_008F0C_RESOURCE_LEVEL(1);
3606 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3607 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3610 cmd_buffer
->push_constant_stages
|=
3611 set
->layout
->dynamic_shader_stages
;
3616 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3617 struct radv_descriptor_set
*set
,
3618 struct radv_descriptor_set_layout
*layout
,
3619 VkPipelineBindPoint bind_point
)
3621 struct radv_descriptor_state
*descriptors_state
=
3622 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3623 set
->size
= layout
->size
;
3624 set
->layout
= layout
;
3626 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3627 size_t new_size
= MAX2(set
->size
, 1024);
3628 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3629 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3631 free(set
->mapped_ptr
);
3632 set
->mapped_ptr
= malloc(new_size
);
3634 if (!set
->mapped_ptr
) {
3635 descriptors_state
->push_set
.capacity
= 0;
3636 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3640 descriptors_state
->push_set
.capacity
= new_size
;
3646 void radv_meta_push_descriptor_set(
3647 struct radv_cmd_buffer
* cmd_buffer
,
3648 VkPipelineBindPoint pipelineBindPoint
,
3649 VkPipelineLayout _layout
,
3651 uint32_t descriptorWriteCount
,
3652 const VkWriteDescriptorSet
* pDescriptorWrites
)
3654 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3655 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3659 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3661 push_set
->size
= layout
->set
[set
].layout
->size
;
3662 push_set
->layout
= layout
->set
[set
].layout
;
3664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3666 (void**) &push_set
->mapped_ptr
))
3669 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3670 push_set
->va
+= bo_offset
;
3672 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3673 radv_descriptor_set_to_handle(push_set
),
3674 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3676 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3679 void radv_CmdPushDescriptorSetKHR(
3680 VkCommandBuffer commandBuffer
,
3681 VkPipelineBindPoint pipelineBindPoint
,
3682 VkPipelineLayout _layout
,
3684 uint32_t descriptorWriteCount
,
3685 const VkWriteDescriptorSet
* pDescriptorWrites
)
3687 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3688 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3689 struct radv_descriptor_state
*descriptors_state
=
3690 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3691 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3693 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3695 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3696 layout
->set
[set
].layout
,
3700 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3701 * because it is invalid, according to Vulkan spec.
3703 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3704 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3705 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3708 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3709 radv_descriptor_set_to_handle(push_set
),
3710 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3712 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3713 descriptors_state
->push_dirty
= true;
3716 void radv_CmdPushDescriptorSetWithTemplateKHR(
3717 VkCommandBuffer commandBuffer
,
3718 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3719 VkPipelineLayout _layout
,
3723 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3724 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3725 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3726 struct radv_descriptor_state
*descriptors_state
=
3727 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3728 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3730 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3732 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3733 layout
->set
[set
].layout
,
3737 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3738 descriptorUpdateTemplate
, pData
);
3740 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3741 descriptors_state
->push_dirty
= true;
3744 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3745 VkPipelineLayout layout
,
3746 VkShaderStageFlags stageFlags
,
3749 const void* pValues
)
3751 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3752 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3753 cmd_buffer
->push_constant_stages
|= stageFlags
;
3756 VkResult
radv_EndCommandBuffer(
3757 VkCommandBuffer commandBuffer
)
3759 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3761 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3762 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3763 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3765 /* Make sure to sync all pending active queries at the end of
3768 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3770 /* Since NGG streamout uses GDS, we need to make GDS idle when
3771 * we leave the IB, otherwise another process might overwrite
3772 * it while our shaders are busy.
3774 if (cmd_buffer
->gds_needed
)
3775 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3777 si_emit_cache_flush(cmd_buffer
);
3780 /* Make sure CP DMA is idle at the end of IBs because the kernel
3781 * doesn't wait for it.
3783 si_cp_dma_wait_for_idle(cmd_buffer
);
3785 radv_describe_end_cmd_buffer(cmd_buffer
);
3787 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3788 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3790 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3791 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3793 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3795 return cmd_buffer
->record_result
;
3799 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3801 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3803 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3806 assert(!pipeline
->ctx_cs
.cdw
);
3808 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3810 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3811 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3813 cmd_buffer
->compute_scratch_size_per_wave_needed
= MAX2(cmd_buffer
->compute_scratch_size_per_wave_needed
,
3814 pipeline
->scratch_bytes_per_wave
);
3815 cmd_buffer
->compute_scratch_waves_wanted
= MAX2(cmd_buffer
->compute_scratch_waves_wanted
,
3816 pipeline
->max_waves
);
3818 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3819 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3821 if (unlikely(cmd_buffer
->device
->trace_bo
))
3822 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3825 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3826 VkPipelineBindPoint bind_point
)
3828 struct radv_descriptor_state
*descriptors_state
=
3829 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3831 descriptors_state
->dirty
|= descriptors_state
->valid
;
3834 void radv_CmdBindPipeline(
3835 VkCommandBuffer commandBuffer
,
3836 VkPipelineBindPoint pipelineBindPoint
,
3837 VkPipeline _pipeline
)
3839 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3840 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3842 switch (pipelineBindPoint
) {
3843 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3844 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3846 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3848 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3849 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3851 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3852 if (cmd_buffer
->state
.pipeline
== pipeline
)
3854 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3856 cmd_buffer
->state
.pipeline
= pipeline
;
3860 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3861 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3863 /* the new vertex shader might not have the same user regs */
3864 cmd_buffer
->state
.last_first_instance
= -1;
3865 cmd_buffer
->state
.last_vertex_offset
= -1;
3867 /* Prefetch all pipeline shaders at first draw time. */
3868 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3870 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
3871 cmd_buffer
->state
.emitted_pipeline
&&
3872 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
3873 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
3874 /* Transitioning from NGG to legacy GS requires
3875 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3876 * at the beginning of IBs when legacy GS ring pointers
3879 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
3882 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3883 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3885 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3886 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3887 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3888 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3890 if (radv_pipeline_has_tess(pipeline
))
3891 cmd_buffer
->tess_rings_needed
= true;
3894 assert(!"invalid bind point");
3899 void radv_CmdSetViewport(
3900 VkCommandBuffer commandBuffer
,
3901 uint32_t firstViewport
,
3902 uint32_t viewportCount
,
3903 const VkViewport
* pViewports
)
3905 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3906 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3907 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3909 assert(firstViewport
< MAX_VIEWPORTS
);
3910 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3912 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3913 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3917 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3918 viewportCount
* sizeof(*pViewports
));
3920 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3923 void radv_CmdSetScissor(
3924 VkCommandBuffer commandBuffer
,
3925 uint32_t firstScissor
,
3926 uint32_t scissorCount
,
3927 const VkRect2D
* pScissors
)
3929 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3930 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3931 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3933 assert(firstScissor
< MAX_SCISSORS
);
3934 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3936 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3937 scissorCount
* sizeof(*pScissors
))) {
3941 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3942 scissorCount
* sizeof(*pScissors
));
3944 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3947 void radv_CmdSetLineWidth(
3948 VkCommandBuffer commandBuffer
,
3951 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3953 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3956 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3957 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3960 void radv_CmdSetDepthBias(
3961 VkCommandBuffer commandBuffer
,
3962 float depthBiasConstantFactor
,
3963 float depthBiasClamp
,
3964 float depthBiasSlopeFactor
)
3966 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3967 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3969 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3970 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3971 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3975 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3976 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3977 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3979 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3982 void radv_CmdSetBlendConstants(
3983 VkCommandBuffer commandBuffer
,
3984 const float blendConstants
[4])
3986 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3987 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3989 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3992 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3994 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3997 void radv_CmdSetDepthBounds(
3998 VkCommandBuffer commandBuffer
,
3999 float minDepthBounds
,
4000 float maxDepthBounds
)
4002 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4003 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4005 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
4006 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
4010 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
4011 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
4013 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
4016 void radv_CmdSetStencilCompareMask(
4017 VkCommandBuffer commandBuffer
,
4018 VkStencilFaceFlags faceMask
,
4019 uint32_t compareMask
)
4021 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4022 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4023 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
4024 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
4026 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4027 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4031 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4032 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
4033 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4034 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
4036 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
4039 void radv_CmdSetStencilWriteMask(
4040 VkCommandBuffer commandBuffer
,
4041 VkStencilFaceFlags faceMask
,
4044 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4045 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4046 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
4047 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
4049 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4050 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4054 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4055 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
4056 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4057 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
4059 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
4062 void radv_CmdSetStencilReference(
4063 VkCommandBuffer commandBuffer
,
4064 VkStencilFaceFlags faceMask
,
4067 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4068 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4069 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
4070 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
4072 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4073 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4077 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4078 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
4079 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4080 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
4082 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
4085 void radv_CmdSetDiscardRectangleEXT(
4086 VkCommandBuffer commandBuffer
,
4087 uint32_t firstDiscardRectangle
,
4088 uint32_t discardRectangleCount
,
4089 const VkRect2D
* pDiscardRectangles
)
4091 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4092 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4093 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
4095 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
4096 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
4098 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
4099 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
4103 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
4104 pDiscardRectangles
, discardRectangleCount
);
4106 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
4109 void radv_CmdSetSampleLocationsEXT(
4110 VkCommandBuffer commandBuffer
,
4111 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
4113 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4114 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4116 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
4118 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
4119 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
4120 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
4121 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
4122 pSampleLocationsInfo
->pSampleLocations
,
4123 pSampleLocationsInfo
->sampleLocationsCount
);
4125 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
4128 void radv_CmdSetLineStippleEXT(
4129 VkCommandBuffer commandBuffer
,
4130 uint32_t lineStippleFactor
,
4131 uint16_t lineStipplePattern
)
4133 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4134 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4136 state
->dynamic
.line_stipple
.factor
= lineStippleFactor
;
4137 state
->dynamic
.line_stipple
.pattern
= lineStipplePattern
;
4139 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
4142 void radv_CmdExecuteCommands(
4143 VkCommandBuffer commandBuffer
,
4144 uint32_t commandBufferCount
,
4145 const VkCommandBuffer
* pCmdBuffers
)
4147 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
4149 assert(commandBufferCount
> 0);
4151 /* Emit pending flushes on primary prior to executing secondary */
4152 si_emit_cache_flush(primary
);
4154 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
4155 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
4157 primary
->scratch_size_per_wave_needed
= MAX2(primary
->scratch_size_per_wave_needed
,
4158 secondary
->scratch_size_per_wave_needed
);
4159 primary
->scratch_waves_wanted
= MAX2(primary
->scratch_waves_wanted
,
4160 secondary
->scratch_waves_wanted
);
4161 primary
->compute_scratch_size_per_wave_needed
= MAX2(primary
->compute_scratch_size_per_wave_needed
,
4162 secondary
->compute_scratch_size_per_wave_needed
);
4163 primary
->compute_scratch_waves_wanted
= MAX2(primary
->compute_scratch_waves_wanted
,
4164 secondary
->compute_scratch_waves_wanted
);
4166 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4167 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4168 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4169 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4170 if (secondary
->tess_rings_needed
)
4171 primary
->tess_rings_needed
= true;
4172 if (secondary
->sample_positions_needed
)
4173 primary
->sample_positions_needed
= true;
4174 if (secondary
->gds_needed
)
4175 primary
->gds_needed
= true;
4177 if (!secondary
->state
.framebuffer
&&
4178 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4179 /* Emit the framebuffer state from primary if secondary
4180 * has been recorded without a framebuffer, otherwise
4181 * fast color/depth clears can't work.
4183 radv_emit_framebuffer_state(primary
);
4186 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4189 /* When the secondary command buffer is compute only we don't
4190 * need to re-emit the current graphics pipeline.
4192 if (secondary
->state
.emitted_pipeline
) {
4193 primary
->state
.emitted_pipeline
=
4194 secondary
->state
.emitted_pipeline
;
4197 /* When the secondary command buffer is graphics only we don't
4198 * need to re-emit the current compute pipeline.
4200 if (secondary
->state
.emitted_compute_pipeline
) {
4201 primary
->state
.emitted_compute_pipeline
=
4202 secondary
->state
.emitted_compute_pipeline
;
4205 /* Only re-emit the draw packets when needed. */
4206 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4207 primary
->state
.last_primitive_reset_en
=
4208 secondary
->state
.last_primitive_reset_en
;
4211 if (secondary
->state
.last_primitive_reset_index
) {
4212 primary
->state
.last_primitive_reset_index
=
4213 secondary
->state
.last_primitive_reset_index
;
4216 if (secondary
->state
.last_ia_multi_vgt_param
) {
4217 primary
->state
.last_ia_multi_vgt_param
=
4218 secondary
->state
.last_ia_multi_vgt_param
;
4221 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4222 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4223 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4224 primary
->state
.last_sx_ps_downconvert
= secondary
->state
.last_sx_ps_downconvert
;
4225 primary
->state
.last_sx_blend_opt_epsilon
= secondary
->state
.last_sx_blend_opt_epsilon
;
4226 primary
->state
.last_sx_blend_opt_control
= secondary
->state
.last_sx_blend_opt_control
;
4228 if (secondary
->state
.last_index_type
!= -1) {
4229 primary
->state
.last_index_type
=
4230 secondary
->state
.last_index_type
;
4234 /* After executing commands from secondary buffers we have to dirty
4237 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4238 RADV_CMD_DIRTY_INDEX_BUFFER
|
4239 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4240 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4241 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4244 VkResult
radv_CreateCommandPool(
4246 const VkCommandPoolCreateInfo
* pCreateInfo
,
4247 const VkAllocationCallbacks
* pAllocator
,
4248 VkCommandPool
* pCmdPool
)
4250 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4251 struct radv_cmd_pool
*pool
;
4253 pool
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pool
), 8,
4254 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4256 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4258 vk_object_base_init(&device
->vk
, &pool
->base
,
4259 VK_OBJECT_TYPE_COMMAND_POOL
);
4262 pool
->alloc
= *pAllocator
;
4264 pool
->alloc
= device
->vk
.alloc
;
4266 list_inithead(&pool
->cmd_buffers
);
4267 list_inithead(&pool
->free_cmd_buffers
);
4269 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4271 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4277 void radv_DestroyCommandPool(
4279 VkCommandPool commandPool
,
4280 const VkAllocationCallbacks
* pAllocator
)
4282 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4283 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4288 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4289 &pool
->cmd_buffers
, pool_link
) {
4290 radv_cmd_buffer_destroy(cmd_buffer
);
4293 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4294 &pool
->free_cmd_buffers
, pool_link
) {
4295 radv_cmd_buffer_destroy(cmd_buffer
);
4298 vk_object_base_finish(&pool
->base
);
4299 vk_free2(&device
->vk
.alloc
, pAllocator
, pool
);
4302 VkResult
radv_ResetCommandPool(
4304 VkCommandPool commandPool
,
4305 VkCommandPoolResetFlags flags
)
4307 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4310 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4311 &pool
->cmd_buffers
, pool_link
) {
4312 result
= radv_reset_cmd_buffer(cmd_buffer
);
4313 if (result
!= VK_SUCCESS
)
4320 void radv_TrimCommandPool(
4322 VkCommandPool commandPool
,
4323 VkCommandPoolTrimFlags flags
)
4325 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4330 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4331 &pool
->free_cmd_buffers
, pool_link
) {
4332 radv_cmd_buffer_destroy(cmd_buffer
);
4337 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4338 uint32_t subpass_id
)
4340 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4341 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4343 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4344 cmd_buffer
->cs
, 4096);
4346 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4348 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4350 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4352 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4353 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4354 if (a
== VK_ATTACHMENT_UNUSED
)
4357 radv_handle_subpass_image_transition(cmd_buffer
,
4358 subpass
->attachments
[i
],
4362 radv_describe_barrier_end(cmd_buffer
);
4364 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4366 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4370 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4372 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4373 const struct radv_subpass
*subpass
= state
->subpass
;
4374 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4376 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4378 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4380 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4381 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4382 if (a
== VK_ATTACHMENT_UNUSED
)
4385 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4388 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4389 VkImageLayout stencil_layout
= state
->pass
->attachments
[a
].stencil_final_layout
;
4390 struct radv_subpass_attachment att
= { a
, layout
, stencil_layout
};
4391 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4394 radv_describe_barrier_end(cmd_buffer
);
4398 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
4399 const VkRenderPassBeginInfo
*pRenderPassBegin
)
4401 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4402 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4405 cmd_buffer
->state
.framebuffer
= framebuffer
;
4406 cmd_buffer
->state
.pass
= pass
;
4407 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4409 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4410 if (result
!= VK_SUCCESS
)
4413 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4414 if (result
!= VK_SUCCESS
)
4418 void radv_CmdBeginRenderPass(
4419 VkCommandBuffer commandBuffer
,
4420 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4421 VkSubpassContents contents
)
4423 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4425 radv_cmd_buffer_begin_render_pass(cmd_buffer
, pRenderPassBegin
);
4427 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4430 void radv_CmdBeginRenderPass2(
4431 VkCommandBuffer commandBuffer
,
4432 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4433 const VkSubpassBeginInfo
* pSubpassBeginInfo
)
4435 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4436 pSubpassBeginInfo
->contents
);
4439 void radv_CmdNextSubpass(
4440 VkCommandBuffer commandBuffer
,
4441 VkSubpassContents contents
)
4443 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4445 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4446 radv_cmd_buffer_end_subpass(cmd_buffer
);
4447 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4450 void radv_CmdNextSubpass2(
4451 VkCommandBuffer commandBuffer
,
4452 const VkSubpassBeginInfo
* pSubpassBeginInfo
,
4453 const VkSubpassEndInfo
* pSubpassEndInfo
)
4455 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4458 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4460 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4461 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4462 if (!radv_get_shader(pipeline
, stage
))
4465 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4466 if (loc
->sgpr_idx
== -1)
4468 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4469 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4472 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4473 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4474 if (loc
->sgpr_idx
!= -1) {
4475 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4476 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4482 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4483 uint32_t vertex_count
,
4486 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4487 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4488 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4489 S_0287F0_USE_OPAQUE(use_opaque
));
4493 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4495 uint32_t index_count
)
4497 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4498 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4499 radeon_emit(cmd_buffer
->cs
, index_va
);
4500 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4501 radeon_emit(cmd_buffer
->cs
, index_count
);
4502 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4506 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4508 uint32_t draw_count
,
4512 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4513 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4514 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4515 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
4516 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4517 bool predicating
= cmd_buffer
->state
.predicating
;
4520 /* just reset draw state for vertex data */
4521 cmd_buffer
->state
.last_first_instance
= -1;
4522 cmd_buffer
->state
.last_num_instances
= -1;
4523 cmd_buffer
->state
.last_vertex_offset
= -1;
4525 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4526 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4527 PKT3_DRAW_INDIRECT
, 3, predicating
));
4529 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4530 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4531 radeon_emit(cs
, di_src_sel
);
4533 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4534 PKT3_DRAW_INDIRECT_MULTI
,
4537 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4538 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4539 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4540 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4541 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4542 radeon_emit(cs
, draw_count
); /* count */
4543 radeon_emit(cs
, count_va
); /* count_addr */
4544 radeon_emit(cs
, count_va
>> 32);
4545 radeon_emit(cs
, stride
); /* stride */
4546 radeon_emit(cs
, di_src_sel
);
4551 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4552 const struct radv_draw_info
*info
)
4554 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4555 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4556 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4558 if (info
->indirect
) {
4559 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4560 uint64_t count_va
= 0;
4562 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4564 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4566 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4568 radeon_emit(cs
, va
);
4569 radeon_emit(cs
, va
>> 32);
4571 if (info
->count_buffer
) {
4572 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4573 count_va
+= info
->count_buffer
->offset
+
4574 info
->count_buffer_offset
;
4576 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4579 if (!state
->subpass
->view_mask
) {
4580 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4587 for_each_bit(i
, state
->subpass
->view_mask
) {
4588 radv_emit_view_index(cmd_buffer
, i
);
4590 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4598 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4600 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4601 info
->first_instance
!= state
->last_first_instance
) {
4602 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4603 state
->pipeline
->graphics
.vtx_emit_num
);
4605 radeon_emit(cs
, info
->vertex_offset
);
4606 radeon_emit(cs
, info
->first_instance
);
4607 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4609 state
->last_first_instance
= info
->first_instance
;
4610 state
->last_vertex_offset
= info
->vertex_offset
;
4613 if (state
->last_num_instances
!= info
->instance_count
) {
4614 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4615 radeon_emit(cs
, info
->instance_count
);
4616 state
->last_num_instances
= info
->instance_count
;
4619 if (info
->indexed
) {
4620 int index_size
= radv_get_vgt_index_size(state
->index_type
);
4623 /* Skip draw calls with 0-sized index buffers. They
4624 * cause a hang on some chips, like Navi10-14.
4626 if (!cmd_buffer
->state
.max_index_count
)
4629 index_va
= state
->index_va
;
4630 index_va
+= info
->first_index
* index_size
;
4632 if (!state
->subpass
->view_mask
) {
4633 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4638 for_each_bit(i
, state
->subpass
->view_mask
) {
4639 radv_emit_view_index(cmd_buffer
, i
);
4641 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4647 if (!state
->subpass
->view_mask
) {
4648 radv_cs_emit_draw_packet(cmd_buffer
,
4650 !!info
->strmout_buffer
);
4653 for_each_bit(i
, state
->subpass
->view_mask
) {
4654 radv_emit_view_index(cmd_buffer
, i
);
4656 radv_cs_emit_draw_packet(cmd_buffer
,
4658 !!info
->strmout_buffer
);
4666 * Vega and raven have a bug which triggers if there are multiple context
4667 * register contexts active at the same time with different scissor values.
4669 * There are two possible workarounds:
4670 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4671 * there is only ever 1 active set of scissor values at the same time.
4673 * 2) Whenever the hardware switches contexts we have to set the scissor
4674 * registers again even if it is a noop. That way the new context gets
4675 * the correct scissor values.
4677 * This implements option 2. radv_need_late_scissor_emission needs to
4678 * return true on affected HW if radv_emit_all_graphics_states sets
4679 * any context registers.
4681 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4682 const struct radv_draw_info
*info
)
4684 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4686 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
4689 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4692 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4694 /* Index, vertex and streamout buffers don't change context regs, and
4695 * pipeline is already handled.
4697 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4698 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4699 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4700 RADV_CMD_DIRTY_PIPELINE
);
4702 if (cmd_buffer
->state
.dirty
& used_states
)
4705 uint32_t primitive_reset_index
=
4706 radv_get_primitive_reset_index(cmd_buffer
);
4708 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4709 primitive_reset_index
!= state
->last_primitive_reset_index
)
4716 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4717 const struct radv_draw_info
*info
)
4719 bool late_scissor_emission
;
4721 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4722 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4723 radv_emit_rbplus_state(cmd_buffer
);
4725 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4726 radv_emit_graphics_pipeline(cmd_buffer
);
4728 /* This should be before the cmd_buffer->state.dirty is cleared
4729 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4730 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4731 late_scissor_emission
=
4732 radv_need_late_scissor_emission(cmd_buffer
, info
);
4734 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4735 radv_emit_framebuffer_state(cmd_buffer
);
4737 if (info
->indexed
) {
4738 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4739 radv_emit_index_buffer(cmd_buffer
, info
->indirect
);
4741 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4742 * so the state must be re-emitted before the next indexed
4745 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4746 cmd_buffer
->state
.last_index_type
= -1;
4747 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4751 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4753 radv_emit_draw_registers(cmd_buffer
, info
);
4755 if (late_scissor_emission
)
4756 radv_emit_scissor(cmd_buffer
);
4760 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4761 const struct radv_draw_info
*info
)
4763 struct radeon_info
*rad_info
=
4764 &cmd_buffer
->device
->physical_device
->rad_info
;
4766 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4767 bool pipeline_is_dirty
=
4768 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4769 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4771 ASSERTED
unsigned cdw_max
=
4772 radeon_check_space(cmd_buffer
->device
->ws
,
4773 cmd_buffer
->cs
, 4096);
4775 if (likely(!info
->indirect
)) {
4776 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4777 * no workaround for indirect draws, but we can at least skip
4780 if (unlikely(!info
->instance_count
))
4783 /* Handle count == 0. */
4784 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4788 radv_describe_draw(cmd_buffer
);
4790 /* Use optimal packet order based on whether we need to sync the
4793 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4794 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4795 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4796 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4797 /* If we have to wait for idle, set all states first, so that
4798 * all SET packets are processed in parallel with previous draw
4799 * calls. Then upload descriptors, set shader pointers, and
4800 * draw, and prefetch at the end. This ensures that the time
4801 * the CUs are idle is very short. (there are only SET_SH
4802 * packets between the wait and the draw)
4804 radv_emit_all_graphics_states(cmd_buffer
, info
);
4805 si_emit_cache_flush(cmd_buffer
);
4806 /* <-- CUs are idle here --> */
4808 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4810 radv_emit_draw_packets(cmd_buffer
, info
);
4811 /* <-- CUs are busy here --> */
4813 /* Start prefetches after the draw has been started. Both will
4814 * run in parallel, but starting the draw first is more
4817 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4818 radv_emit_prefetch_L2(cmd_buffer
,
4819 cmd_buffer
->state
.pipeline
, false);
4822 /* If we don't wait for idle, start prefetches first, then set
4823 * states, and draw at the end.
4825 si_emit_cache_flush(cmd_buffer
);
4827 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4828 /* Only prefetch the vertex shader and VBO descriptors
4829 * in order to start the draw as soon as possible.
4831 radv_emit_prefetch_L2(cmd_buffer
,
4832 cmd_buffer
->state
.pipeline
, true);
4835 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4837 radv_emit_all_graphics_states(cmd_buffer
, info
);
4838 radv_emit_draw_packets(cmd_buffer
, info
);
4840 /* Prefetch the remaining shaders after the draw has been
4843 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4844 radv_emit_prefetch_L2(cmd_buffer
,
4845 cmd_buffer
->state
.pipeline
, false);
4849 /* Workaround for a VGT hang when streamout is enabled.
4850 * It must be done after drawing.
4852 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4853 (rad_info
->family
== CHIP_HAWAII
||
4854 rad_info
->family
== CHIP_TONGA
||
4855 rad_info
->family
== CHIP_FIJI
)) {
4856 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4859 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4860 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4864 VkCommandBuffer commandBuffer
,
4865 uint32_t vertexCount
,
4866 uint32_t instanceCount
,
4867 uint32_t firstVertex
,
4868 uint32_t firstInstance
)
4870 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4871 struct radv_draw_info info
= {};
4873 info
.count
= vertexCount
;
4874 info
.instance_count
= instanceCount
;
4875 info
.first_instance
= firstInstance
;
4876 info
.vertex_offset
= firstVertex
;
4878 radv_draw(cmd_buffer
, &info
);
4881 void radv_CmdDrawIndexed(
4882 VkCommandBuffer commandBuffer
,
4883 uint32_t indexCount
,
4884 uint32_t instanceCount
,
4885 uint32_t firstIndex
,
4886 int32_t vertexOffset
,
4887 uint32_t firstInstance
)
4889 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4890 struct radv_draw_info info
= {};
4892 info
.indexed
= true;
4893 info
.count
= indexCount
;
4894 info
.instance_count
= instanceCount
;
4895 info
.first_index
= firstIndex
;
4896 info
.vertex_offset
= vertexOffset
;
4897 info
.first_instance
= firstInstance
;
4899 radv_draw(cmd_buffer
, &info
);
4902 void radv_CmdDrawIndirect(
4903 VkCommandBuffer commandBuffer
,
4905 VkDeviceSize offset
,
4909 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4910 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4911 struct radv_draw_info info
= {};
4913 info
.count
= drawCount
;
4914 info
.indirect
= buffer
;
4915 info
.indirect_offset
= offset
;
4916 info
.stride
= stride
;
4918 radv_draw(cmd_buffer
, &info
);
4921 void radv_CmdDrawIndexedIndirect(
4922 VkCommandBuffer commandBuffer
,
4924 VkDeviceSize offset
,
4928 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4929 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4930 struct radv_draw_info info
= {};
4932 info
.indexed
= true;
4933 info
.count
= drawCount
;
4934 info
.indirect
= buffer
;
4935 info
.indirect_offset
= offset
;
4936 info
.stride
= stride
;
4938 radv_draw(cmd_buffer
, &info
);
4941 void radv_CmdDrawIndirectCount(
4942 VkCommandBuffer commandBuffer
,
4944 VkDeviceSize offset
,
4945 VkBuffer _countBuffer
,
4946 VkDeviceSize countBufferOffset
,
4947 uint32_t maxDrawCount
,
4950 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4951 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4952 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4953 struct radv_draw_info info
= {};
4955 info
.count
= maxDrawCount
;
4956 info
.indirect
= buffer
;
4957 info
.indirect_offset
= offset
;
4958 info
.count_buffer
= count_buffer
;
4959 info
.count_buffer_offset
= countBufferOffset
;
4960 info
.stride
= stride
;
4962 radv_draw(cmd_buffer
, &info
);
4965 void radv_CmdDrawIndexedIndirectCount(
4966 VkCommandBuffer commandBuffer
,
4968 VkDeviceSize offset
,
4969 VkBuffer _countBuffer
,
4970 VkDeviceSize countBufferOffset
,
4971 uint32_t maxDrawCount
,
4974 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4975 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4976 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4977 struct radv_draw_info info
= {};
4979 info
.indexed
= true;
4980 info
.count
= maxDrawCount
;
4981 info
.indirect
= buffer
;
4982 info
.indirect_offset
= offset
;
4983 info
.count_buffer
= count_buffer
;
4984 info
.count_buffer_offset
= countBufferOffset
;
4985 info
.stride
= stride
;
4987 radv_draw(cmd_buffer
, &info
);
4990 struct radv_dispatch_info
{
4992 * Determine the layout of the grid (in block units) to be used.
4997 * A starting offset for the grid. If unaligned is set, the offset
4998 * must still be aligned.
5000 uint32_t offsets
[3];
5002 * Whether it's an unaligned compute dispatch.
5007 * Indirect compute parameters resource.
5009 struct radv_buffer
*indirect
;
5010 uint64_t indirect_offset
;
5014 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
5015 const struct radv_dispatch_info
*info
)
5017 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5018 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5019 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
5020 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
5021 bool predicating
= cmd_buffer
->state
.predicating
;
5022 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5023 struct radv_userdata_info
*loc
;
5025 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
5026 AC_UD_CS_GRID_SIZE
);
5028 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
5030 if (compute_shader
->info
.wave_size
== 32) {
5031 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5032 dispatch_initiator
|= S_00B800_CS_W32_EN(1);
5035 if (info
->indirect
) {
5036 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
5038 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
5040 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
5042 if (loc
->sgpr_idx
!= -1) {
5043 for (unsigned i
= 0; i
< 3; ++i
) {
5044 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5045 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5046 COPY_DATA_DST_SEL(COPY_DATA_REG
));
5047 radeon_emit(cs
, (va
+ 4 * i
));
5048 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
5049 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
5050 + loc
->sgpr_idx
* 4) >> 2) + i
);
5055 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
5056 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
5057 PKT3_SHADER_TYPE_S(1));
5058 radeon_emit(cs
, va
);
5059 radeon_emit(cs
, va
>> 32);
5060 radeon_emit(cs
, dispatch_initiator
);
5062 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
5063 PKT3_SHADER_TYPE_S(1));
5065 radeon_emit(cs
, va
);
5066 radeon_emit(cs
, va
>> 32);
5068 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
5069 PKT3_SHADER_TYPE_S(1));
5071 radeon_emit(cs
, dispatch_initiator
);
5074 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
5075 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
5077 if (info
->unaligned
) {
5078 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
5079 unsigned remainder
[3];
5081 /* If aligned, these should be an entire block size,
5084 remainder
[0] = blocks
[0] + cs_block_size
[0] -
5085 align_u32_npot(blocks
[0], cs_block_size
[0]);
5086 remainder
[1] = blocks
[1] + cs_block_size
[1] -
5087 align_u32_npot(blocks
[1], cs_block_size
[1]);
5088 remainder
[2] = blocks
[2] + cs_block_size
[2] -
5089 align_u32_npot(blocks
[2], cs_block_size
[2]);
5091 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
5092 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
5093 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
5095 for(unsigned i
= 0; i
< 3; ++i
) {
5096 assert(offsets
[i
] % cs_block_size
[i
] == 0);
5097 offsets
[i
] /= cs_block_size
[i
];
5100 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5102 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
5103 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
5105 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
5106 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
5108 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
5109 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
5111 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
5114 if (loc
->sgpr_idx
!= -1) {
5115 assert(loc
->num_sgprs
== 3);
5117 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
5118 loc
->sgpr_idx
* 4, 3);
5119 radeon_emit(cs
, blocks
[0]);
5120 radeon_emit(cs
, blocks
[1]);
5121 radeon_emit(cs
, blocks
[2]);
5124 if (offsets
[0] || offsets
[1] || offsets
[2]) {
5125 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
5126 radeon_emit(cs
, offsets
[0]);
5127 radeon_emit(cs
, offsets
[1]);
5128 radeon_emit(cs
, offsets
[2]);
5130 /* The blocks in the packet are not counts but end values. */
5131 for (unsigned i
= 0; i
< 3; ++i
)
5132 blocks
[i
] += offsets
[i
];
5134 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
5137 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
5138 PKT3_SHADER_TYPE_S(1));
5139 radeon_emit(cs
, blocks
[0]);
5140 radeon_emit(cs
, blocks
[1]);
5141 radeon_emit(cs
, blocks
[2]);
5142 radeon_emit(cs
, dispatch_initiator
);
5145 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5149 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
5151 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5152 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5156 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
5157 const struct radv_dispatch_info
*info
)
5159 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5161 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
5162 bool pipeline_is_dirty
= pipeline
&&
5163 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
5165 radv_describe_dispatch(cmd_buffer
, 8, 8, 8);
5167 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5168 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5169 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5170 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5171 /* If we have to wait for idle, set all states first, so that
5172 * all SET packets are processed in parallel with previous draw
5173 * calls. Then upload descriptors, set shader pointers, and
5174 * dispatch, and prefetch at the end. This ensures that the
5175 * time the CUs are idle is very short. (there are only SET_SH
5176 * packets between the wait and the draw)
5178 radv_emit_compute_pipeline(cmd_buffer
);
5179 si_emit_cache_flush(cmd_buffer
);
5180 /* <-- CUs are idle here --> */
5182 radv_upload_compute_shader_descriptors(cmd_buffer
);
5184 radv_emit_dispatch_packets(cmd_buffer
, info
);
5185 /* <-- CUs are busy here --> */
5187 /* Start prefetches after the dispatch has been started. Both
5188 * will run in parallel, but starting the dispatch first is
5191 if (has_prefetch
&& pipeline_is_dirty
) {
5192 radv_emit_shader_prefetch(cmd_buffer
,
5193 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5196 /* If we don't wait for idle, start prefetches first, then set
5197 * states, and dispatch at the end.
5199 si_emit_cache_flush(cmd_buffer
);
5201 if (has_prefetch
&& pipeline_is_dirty
) {
5202 radv_emit_shader_prefetch(cmd_buffer
,
5203 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5206 radv_upload_compute_shader_descriptors(cmd_buffer
);
5208 radv_emit_compute_pipeline(cmd_buffer
);
5209 radv_emit_dispatch_packets(cmd_buffer
, info
);
5212 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5215 void radv_CmdDispatchBase(
5216 VkCommandBuffer commandBuffer
,
5224 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5225 struct radv_dispatch_info info
= {};
5231 info
.offsets
[0] = base_x
;
5232 info
.offsets
[1] = base_y
;
5233 info
.offsets
[2] = base_z
;
5234 radv_dispatch(cmd_buffer
, &info
);
5237 void radv_CmdDispatch(
5238 VkCommandBuffer commandBuffer
,
5243 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5246 void radv_CmdDispatchIndirect(
5247 VkCommandBuffer commandBuffer
,
5249 VkDeviceSize offset
)
5251 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5252 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5253 struct radv_dispatch_info info
= {};
5255 info
.indirect
= buffer
;
5256 info
.indirect_offset
= offset
;
5258 radv_dispatch(cmd_buffer
, &info
);
5261 void radv_unaligned_dispatch(
5262 struct radv_cmd_buffer
*cmd_buffer
,
5267 struct radv_dispatch_info info
= {};
5274 radv_dispatch(cmd_buffer
, &info
);
5278 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
)
5280 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5281 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5283 cmd_buffer
->state
.pass
= NULL
;
5284 cmd_buffer
->state
.subpass
= NULL
;
5285 cmd_buffer
->state
.attachments
= NULL
;
5286 cmd_buffer
->state
.framebuffer
= NULL
;
5287 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5290 void radv_CmdEndRenderPass(
5291 VkCommandBuffer commandBuffer
)
5293 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5295 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5297 radv_cmd_buffer_end_subpass(cmd_buffer
);
5299 radv_cmd_buffer_end_render_pass(cmd_buffer
);
5302 void radv_CmdEndRenderPass2(
5303 VkCommandBuffer commandBuffer
,
5304 const VkSubpassEndInfo
* pSubpassEndInfo
)
5306 radv_CmdEndRenderPass(commandBuffer
);
5310 * For HTILE we have the following interesting clear words:
5311 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5312 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5313 * 0xfffffff0: Clear depth to 1.0
5314 * 0x00000000: Clear depth to 0.0
5316 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5317 struct radv_image
*image
,
5318 const VkImageSubresourceRange
*range
)
5320 assert(range
->baseMipLevel
== 0);
5321 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5322 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5323 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5324 uint32_t htile_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5325 VkClearDepthStencilValue value
= {};
5326 struct radv_barrier_data barrier
= {};
5328 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5329 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5331 barrier
.layout_transitions
.init_mask_ram
= 1;
5332 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5334 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, htile_value
);
5336 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5338 if (vk_format_is_stencil(image
->vk_format
))
5339 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5341 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5343 if (radv_image_is_tc_compat_htile(image
)) {
5344 /* Initialize the TC-compat metada value to 0 because by
5345 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5346 * need have to conditionally update its value when performing
5347 * a fast depth clear.
5349 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5353 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5354 struct radv_image
*image
,
5355 VkImageLayout src_layout
,
5356 bool src_render_loop
,
5357 VkImageLayout dst_layout
,
5358 bool dst_render_loop
,
5359 unsigned src_queue_mask
,
5360 unsigned dst_queue_mask
,
5361 const VkImageSubresourceRange
*range
,
5362 struct radv_sample_locations_state
*sample_locs
)
5364 if (!radv_image_has_htile(image
))
5367 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5368 radv_initialize_htile(cmd_buffer
, image
, range
);
5369 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5370 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5371 radv_initialize_htile(cmd_buffer
, image
, range
);
5372 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5373 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5374 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5375 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5377 radv_decompress_depth_stencil(cmd_buffer
, image
, range
,
5380 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5381 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5385 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5386 struct radv_image
*image
,
5387 const VkImageSubresourceRange
*range
,
5390 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5391 struct radv_barrier_data barrier
= {};
5393 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5394 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5396 barrier
.layout_transitions
.init_mask_ram
= 1;
5397 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5399 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5401 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5404 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5405 struct radv_image
*image
,
5406 const VkImageSubresourceRange
*range
)
5408 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5409 static const uint32_t fmask_clear_values
[4] = {
5415 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5416 uint32_t value
= fmask_clear_values
[log2_samples
];
5417 struct radv_barrier_data barrier
= {};
5419 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5420 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5422 barrier
.layout_transitions
.init_mask_ram
= 1;
5423 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5425 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5427 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5430 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5431 struct radv_image
*image
,
5432 const VkImageSubresourceRange
*range
, uint32_t value
)
5434 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5435 struct radv_barrier_data barrier
= {};
5438 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5439 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5441 barrier
.layout_transitions
.init_mask_ram
= 1;
5442 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5444 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5446 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5447 /* When DCC is enabled with mipmaps, some levels might not
5448 * support fast clears and we have to initialize them as "fully
5451 /* Compute the size of all fast clearable DCC levels. */
5452 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5453 struct legacy_surf_level
*surf_level
=
5454 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5455 unsigned dcc_fast_clear_size
=
5456 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5458 if (!dcc_fast_clear_size
)
5461 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5464 /* Initialize the mipmap levels without DCC. */
5465 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5466 state
->flush_bits
|=
5467 radv_fill_buffer(cmd_buffer
, image
->bo
,
5468 image
->offset
+ image
->planes
[0].surface
.dcc_offset
+ size
,
5469 image
->planes
[0].surface
.dcc_size
- size
,
5474 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5475 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5479 * Initialize DCC/FMASK/CMASK metadata for a color image.
5481 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5482 struct radv_image
*image
,
5483 VkImageLayout src_layout
,
5484 bool src_render_loop
,
5485 VkImageLayout dst_layout
,
5486 bool dst_render_loop
,
5487 unsigned src_queue_mask
,
5488 unsigned dst_queue_mask
,
5489 const VkImageSubresourceRange
*range
)
5491 if (radv_image_has_cmask(image
)) {
5492 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5494 /* TODO: clarify this. */
5495 if (radv_image_has_fmask(image
)) {
5496 value
= 0xccccccccu
;
5499 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5502 if (radv_image_has_fmask(image
)) {
5503 radv_initialize_fmask(cmd_buffer
, image
, range
);
5506 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5507 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5508 bool need_decompress_pass
= false;
5510 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
5513 value
= 0x20202020u
;
5514 need_decompress_pass
= true;
5517 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5519 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5520 need_decompress_pass
);
5523 if (radv_image_has_cmask(image
) ||
5524 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5525 uint32_t color_values
[2] = {};
5526 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5532 * Handle color image transitions for DCC/FMASK/CMASK.
5534 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5535 struct radv_image
*image
,
5536 VkImageLayout src_layout
,
5537 bool src_render_loop
,
5538 VkImageLayout dst_layout
,
5539 bool dst_render_loop
,
5540 unsigned src_queue_mask
,
5541 unsigned dst_queue_mask
,
5542 const VkImageSubresourceRange
*range
)
5544 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5545 radv_init_color_image_metadata(cmd_buffer
, image
,
5546 src_layout
, src_render_loop
,
5547 dst_layout
, dst_render_loop
,
5548 src_queue_mask
, dst_queue_mask
,
5553 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5554 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5555 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5556 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5557 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5558 radv_decompress_dcc(cmd_buffer
, image
, range
);
5559 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5560 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5561 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5563 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5564 bool fce_eliminate
= false, fmask_expand
= false;
5566 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5567 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5568 fce_eliminate
= true;
5571 if (radv_image_has_fmask(image
)) {
5572 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5573 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5574 /* A FMASK decompress is required before doing
5575 * a MSAA decompress using FMASK.
5577 fmask_expand
= true;
5581 if (fce_eliminate
|| fmask_expand
)
5582 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5585 struct radv_barrier_data barrier
= {};
5586 barrier
.layout_transitions
.fmask_color_expand
= 1;
5587 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5589 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5594 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5595 struct radv_image
*image
,
5596 VkImageLayout src_layout
,
5597 bool src_render_loop
,
5598 VkImageLayout dst_layout
,
5599 bool dst_render_loop
,
5600 uint32_t src_family
,
5601 uint32_t dst_family
,
5602 const VkImageSubresourceRange
*range
,
5603 struct radv_sample_locations_state
*sample_locs
)
5605 if (image
->exclusive
&& src_family
!= dst_family
) {
5606 /* This is an acquire or a release operation and there will be
5607 * a corresponding release/acquire. Do the transition in the
5608 * most flexible queue. */
5610 assert(src_family
== cmd_buffer
->queue_family_index
||
5611 dst_family
== cmd_buffer
->queue_family_index
);
5613 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5614 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5617 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5620 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5621 (src_family
== RADV_QUEUE_GENERAL
||
5622 dst_family
== RADV_QUEUE_GENERAL
))
5626 if (src_layout
== dst_layout
)
5629 unsigned src_queue_mask
=
5630 radv_image_queue_family_mask(image
, src_family
,
5631 cmd_buffer
->queue_family_index
);
5632 unsigned dst_queue_mask
=
5633 radv_image_queue_family_mask(image
, dst_family
,
5634 cmd_buffer
->queue_family_index
);
5636 if (vk_format_is_depth(image
->vk_format
)) {
5637 radv_handle_depth_image_transition(cmd_buffer
, image
,
5638 src_layout
, src_render_loop
,
5639 dst_layout
, dst_render_loop
,
5640 src_queue_mask
, dst_queue_mask
,
5641 range
, sample_locs
);
5643 radv_handle_color_image_transition(cmd_buffer
, image
,
5644 src_layout
, src_render_loop
,
5645 dst_layout
, dst_render_loop
,
5646 src_queue_mask
, dst_queue_mask
,
5651 struct radv_barrier_info
{
5652 enum rgp_barrier_reason reason
;
5653 uint32_t eventCount
;
5654 const VkEvent
*pEvents
;
5655 VkPipelineStageFlags srcStageMask
;
5656 VkPipelineStageFlags dstStageMask
;
5660 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5661 uint32_t memoryBarrierCount
,
5662 const VkMemoryBarrier
*pMemoryBarriers
,
5663 uint32_t bufferMemoryBarrierCount
,
5664 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5665 uint32_t imageMemoryBarrierCount
,
5666 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5667 const struct radv_barrier_info
*info
)
5669 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5670 enum radv_cmd_flush_bits src_flush_bits
= 0;
5671 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5673 radv_describe_barrier_start(cmd_buffer
, info
->reason
);
5675 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5676 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5677 uint64_t va
= radv_buffer_get_va(event
->bo
);
5679 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5681 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5683 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5684 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5687 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5688 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5690 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5694 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5695 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5697 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5701 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5702 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5704 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5706 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5710 /* The Vulkan spec 1.1.98 says:
5712 * "An execution dependency with only
5713 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5714 * will only prevent that stage from executing in subsequently
5715 * submitted commands. As this stage does not perform any actual
5716 * execution, this is not observable - in effect, it does not delay
5717 * processing of subsequent commands. Similarly an execution dependency
5718 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5719 * will effectively not wait for any prior commands to complete."
5721 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5722 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5723 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5725 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5726 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5728 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5729 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5730 SAMPLE_LOCATIONS_INFO_EXT
);
5731 struct radv_sample_locations_state sample_locations
= {};
5733 if (sample_locs_info
) {
5734 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5735 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5736 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5737 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5738 typed_memcpy(&sample_locations
.locations
[0],
5739 sample_locs_info
->pSampleLocations
,
5740 sample_locs_info
->sampleLocationsCount
);
5743 radv_handle_image_transition(cmd_buffer
, image
,
5744 pImageMemoryBarriers
[i
].oldLayout
,
5745 false, /* Outside of a renderpass we are never in a renderloop */
5746 pImageMemoryBarriers
[i
].newLayout
,
5747 false, /* Outside of a renderpass we are never in a renderloop */
5748 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5749 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5750 &pImageMemoryBarriers
[i
].subresourceRange
,
5751 sample_locs_info
? &sample_locations
: NULL
);
5754 /* Make sure CP DMA is idle because the driver might have performed a
5755 * DMA operation for copying or filling buffers/images.
5757 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5758 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5759 si_cp_dma_wait_for_idle(cmd_buffer
);
5761 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5763 radv_describe_barrier_end(cmd_buffer
);
5766 void radv_CmdPipelineBarrier(
5767 VkCommandBuffer commandBuffer
,
5768 VkPipelineStageFlags srcStageMask
,
5769 VkPipelineStageFlags destStageMask
,
5771 uint32_t memoryBarrierCount
,
5772 const VkMemoryBarrier
* pMemoryBarriers
,
5773 uint32_t bufferMemoryBarrierCount
,
5774 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5775 uint32_t imageMemoryBarrierCount
,
5776 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5778 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5779 struct radv_barrier_info info
;
5781 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
;
5782 info
.eventCount
= 0;
5783 info
.pEvents
= NULL
;
5784 info
.srcStageMask
= srcStageMask
;
5785 info
.dstStageMask
= destStageMask
;
5787 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5788 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5789 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5793 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5794 struct radv_event
*event
,
5795 VkPipelineStageFlags stageMask
,
5798 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5799 uint64_t va
= radv_buffer_get_va(event
->bo
);
5801 si_emit_cache_flush(cmd_buffer
);
5803 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5805 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5807 /* Flags that only require a top-of-pipe event. */
5808 VkPipelineStageFlags top_of_pipe_flags
=
5809 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5811 /* Flags that only require a post-index-fetch event. */
5812 VkPipelineStageFlags post_index_fetch_flags
=
5814 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5815 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5817 /* Make sure CP DMA is idle because the driver might have performed a
5818 * DMA operation for copying or filling buffers/images.
5820 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5821 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5822 si_cp_dma_wait_for_idle(cmd_buffer
);
5824 /* TODO: Emit EOS events for syncing PS/CS stages. */
5826 if (!(stageMask
& ~top_of_pipe_flags
)) {
5827 /* Just need to sync the PFP engine. */
5828 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5829 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5830 S_370_WR_CONFIRM(1) |
5831 S_370_ENGINE_SEL(V_370_PFP
));
5832 radeon_emit(cs
, va
);
5833 radeon_emit(cs
, va
>> 32);
5834 radeon_emit(cs
, value
);
5835 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5836 /* Sync ME because PFP reads index and indirect buffers. */
5837 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5838 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5839 S_370_WR_CONFIRM(1) |
5840 S_370_ENGINE_SEL(V_370_ME
));
5841 radeon_emit(cs
, va
);
5842 radeon_emit(cs
, va
>> 32);
5843 radeon_emit(cs
, value
);
5845 /* Otherwise, sync all prior GPU work using an EOP event. */
5846 si_cs_emit_write_event_eop(cs
,
5847 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5848 radv_cmd_buffer_uses_mec(cmd_buffer
),
5849 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5851 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5852 cmd_buffer
->gfx9_eop_bug_va
);
5855 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5858 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5860 VkPipelineStageFlags stageMask
)
5862 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5863 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5865 write_event(cmd_buffer
, event
, stageMask
, 1);
5868 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5870 VkPipelineStageFlags stageMask
)
5872 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5873 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5875 write_event(cmd_buffer
, event
, stageMask
, 0);
5878 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5879 uint32_t eventCount
,
5880 const VkEvent
* pEvents
,
5881 VkPipelineStageFlags srcStageMask
,
5882 VkPipelineStageFlags dstStageMask
,
5883 uint32_t memoryBarrierCount
,
5884 const VkMemoryBarrier
* pMemoryBarriers
,
5885 uint32_t bufferMemoryBarrierCount
,
5886 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5887 uint32_t imageMemoryBarrierCount
,
5888 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5890 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5891 struct radv_barrier_info info
;
5893 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
;
5894 info
.eventCount
= eventCount
;
5895 info
.pEvents
= pEvents
;
5896 info
.srcStageMask
= 0;
5898 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5899 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5900 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5904 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5905 uint32_t deviceMask
)
5910 /* VK_EXT_conditional_rendering */
5911 void radv_CmdBeginConditionalRenderingEXT(
5912 VkCommandBuffer commandBuffer
,
5913 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5915 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5916 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5917 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5918 bool draw_visible
= true;
5919 uint64_t pred_value
= 0;
5920 uint64_t va
, new_va
;
5921 unsigned pred_offset
;
5923 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5925 /* By default, if the 32-bit value at offset in buffer memory is zero,
5926 * then the rendering commands are discarded, otherwise they are
5927 * executed as normal. If the inverted flag is set, all commands are
5928 * discarded if the value is non zero.
5930 if (pConditionalRenderingBegin
->flags
&
5931 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5932 draw_visible
= false;
5935 si_emit_cache_flush(cmd_buffer
);
5937 /* From the Vulkan spec 1.1.107:
5939 * "If the 32-bit value at offset in buffer memory is zero, then the
5940 * rendering commands are discarded, otherwise they are executed as
5941 * normal. If the value of the predicate in buffer memory changes while
5942 * conditional rendering is active, the rendering commands may be
5943 * discarded in an implementation-dependent way. Some implementations
5944 * may latch the value of the predicate upon beginning conditional
5945 * rendering while others may read it before every rendering command."
5947 * But, the AMD hardware treats the predicate as a 64-bit value which
5948 * means we need a workaround in the driver. Luckily, it's not required
5949 * to support if the value changes when predication is active.
5951 * The workaround is as follows:
5952 * 1) allocate a 64-value in the upload BO and initialize it to 0
5953 * 2) copy the 32-bit predicate value to the upload BO
5954 * 3) use the new allocated VA address for predication
5956 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5957 * in ME (+ sync PFP) instead of PFP.
5959 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5961 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5963 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5964 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5965 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5966 COPY_DATA_WR_CONFIRM
);
5967 radeon_emit(cs
, va
);
5968 radeon_emit(cs
, va
>> 32);
5969 radeon_emit(cs
, new_va
);
5970 radeon_emit(cs
, new_va
>> 32);
5972 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5975 /* Enable predication for this command buffer. */
5976 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5977 cmd_buffer
->state
.predicating
= true;
5979 /* Store conditional rendering user info. */
5980 cmd_buffer
->state
.predication_type
= draw_visible
;
5981 cmd_buffer
->state
.predication_va
= new_va
;
5984 void radv_CmdEndConditionalRenderingEXT(
5985 VkCommandBuffer commandBuffer
)
5987 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5989 /* Disable predication for this command buffer. */
5990 si_emit_set_predication_state(cmd_buffer
, false, 0);
5991 cmd_buffer
->state
.predicating
= false;
5993 /* Reset conditional rendering user info. */
5994 cmd_buffer
->state
.predication_type
= -1;
5995 cmd_buffer
->state
.predication_va
= 0;
5998 /* VK_EXT_transform_feedback */
5999 void radv_CmdBindTransformFeedbackBuffersEXT(
6000 VkCommandBuffer commandBuffer
,
6001 uint32_t firstBinding
,
6002 uint32_t bindingCount
,
6003 const VkBuffer
* pBuffers
,
6004 const VkDeviceSize
* pOffsets
,
6005 const VkDeviceSize
* pSizes
)
6007 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6008 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6009 uint8_t enabled_mask
= 0;
6011 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
6012 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
6013 uint32_t idx
= firstBinding
+ i
;
6015 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
6016 sb
[idx
].offset
= pOffsets
[i
];
6018 if (!pSizes
|| pSizes
[i
] == VK_WHOLE_SIZE
) {
6019 sb
[idx
].size
= sb
[idx
].buffer
->size
- sb
[idx
].offset
;
6021 sb
[idx
].size
= pSizes
[i
];
6024 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
6025 sb
[idx
].buffer
->bo
);
6027 enabled_mask
|= 1 << idx
;
6030 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
6032 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
6036 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
6038 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6039 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6041 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
6043 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
6044 S_028B94_RAST_STREAM(0) |
6045 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
6046 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
6047 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
6048 radeon_emit(cs
, so
->hw_enabled_mask
&
6049 so
->enabled_stream_buffers_mask
);
6051 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6055 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
6057 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6058 bool old_streamout_enabled
= so
->streamout_enabled
;
6059 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
6061 so
->streamout_enabled
= enable
;
6063 so
->hw_enabled_mask
= so
->enabled_mask
|
6064 (so
->enabled_mask
<< 4) |
6065 (so
->enabled_mask
<< 8) |
6066 (so
->enabled_mask
<< 12);
6068 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
6069 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
6070 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
6071 radv_emit_streamout_enable(cmd_buffer
);
6073 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6074 cmd_buffer
->gds_needed
= true;
6075 cmd_buffer
->gds_oa_needed
= true;
6079 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
6081 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6082 unsigned reg_strmout_cntl
;
6084 /* The register is at different places on different ASICs. */
6085 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6086 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
6087 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
6089 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
6090 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
6093 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
6094 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
6096 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
6097 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
6098 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
6100 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6101 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6102 radeon_emit(cs
, 4); /* poll interval */
6106 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6107 uint32_t firstCounterBuffer
,
6108 uint32_t counterBufferCount
,
6109 const VkBuffer
*pCounterBuffers
,
6110 const VkDeviceSize
*pCounterBufferOffsets
)
6113 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6114 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6115 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6118 radv_flush_vgt_streamout(cmd_buffer
);
6120 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6121 for_each_bit(i
, so
->enabled_mask
) {
6122 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6123 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6124 counter_buffer_idx
= -1;
6126 /* AMD GCN binds streamout buffers as shader resources.
6127 * VGT only counts primitives and tells the shader through
6130 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
6131 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
6132 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
6134 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6136 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6137 /* The array of counter buffers is optional. */
6138 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6139 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6141 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6144 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6145 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6146 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6147 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
6148 radeon_emit(cs
, 0); /* unused */
6149 radeon_emit(cs
, 0); /* unused */
6150 radeon_emit(cs
, va
); /* src address lo */
6151 radeon_emit(cs
, va
>> 32); /* src address hi */
6153 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6155 /* Start from the beginning. */
6156 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6157 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6158 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6159 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
6160 radeon_emit(cs
, 0); /* unused */
6161 radeon_emit(cs
, 0); /* unused */
6162 radeon_emit(cs
, 0); /* unused */
6163 radeon_emit(cs
, 0); /* unused */
6167 radv_set_streamout_enable(cmd_buffer
, true);
6171 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6172 uint32_t firstCounterBuffer
,
6173 uint32_t counterBufferCount
,
6174 const VkBuffer
*pCounterBuffers
,
6175 const VkDeviceSize
*pCounterBufferOffsets
)
6177 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6178 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
6179 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6182 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6183 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6185 /* Sync because the next streamout operation will overwrite GDS and we
6186 * have to make sure it's idle.
6187 * TODO: Improve by tracking if there is a streamout operation in
6190 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
6191 si_emit_cache_flush(cmd_buffer
);
6193 for_each_bit(i
, so
->enabled_mask
) {
6194 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6195 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6196 counter_buffer_idx
= -1;
6198 bool append
= counter_buffer_idx
>= 0 &&
6199 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
6203 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6205 va
+= radv_buffer_get_va(buffer
->bo
);
6206 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6208 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6211 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
6212 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
6213 S_411_DST_SEL(V_411_GDS
) |
6214 S_411_CP_SYNC(i
== last_target
));
6215 radeon_emit(cs
, va
);
6216 radeon_emit(cs
, va
>> 32);
6217 radeon_emit(cs
, 4 * i
); /* destination in GDS */
6219 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
6220 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
6223 radv_set_streamout_enable(cmd_buffer
, true);
6226 void radv_CmdBeginTransformFeedbackEXT(
6227 VkCommandBuffer commandBuffer
,
6228 uint32_t firstCounterBuffer
,
6229 uint32_t counterBufferCount
,
6230 const VkBuffer
* pCounterBuffers
,
6231 const VkDeviceSize
* pCounterBufferOffsets
)
6233 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6235 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6236 gfx10_emit_streamout_begin(cmd_buffer
,
6237 firstCounterBuffer
, counterBufferCount
,
6238 pCounterBuffers
, pCounterBufferOffsets
);
6240 radv_emit_streamout_begin(cmd_buffer
,
6241 firstCounterBuffer
, counterBufferCount
,
6242 pCounterBuffers
, pCounterBufferOffsets
);
6247 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6248 uint32_t firstCounterBuffer
,
6249 uint32_t counterBufferCount
,
6250 const VkBuffer
*pCounterBuffers
,
6251 const VkDeviceSize
*pCounterBufferOffsets
)
6253 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6254 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6257 radv_flush_vgt_streamout(cmd_buffer
);
6259 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6260 for_each_bit(i
, so
->enabled_mask
) {
6261 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6262 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6263 counter_buffer_idx
= -1;
6265 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6266 /* The array of counters buffer is optional. */
6267 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6268 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6270 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6272 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6273 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6274 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6275 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6276 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6277 radeon_emit(cs
, va
); /* dst address lo */
6278 radeon_emit(cs
, va
>> 32); /* dst address hi */
6279 radeon_emit(cs
, 0); /* unused */
6280 radeon_emit(cs
, 0); /* unused */
6282 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6285 /* Deactivate transform feedback by zeroing the buffer size.
6286 * The counters (primitives generated, primitives emitted) may
6287 * be enabled even if there is not buffer bound. This ensures
6288 * that the primitives-emitted query won't increment.
6290 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6292 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6295 radv_set_streamout_enable(cmd_buffer
, false);
6299 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6300 uint32_t firstCounterBuffer
,
6301 uint32_t counterBufferCount
,
6302 const VkBuffer
*pCounterBuffers
,
6303 const VkDeviceSize
*pCounterBufferOffsets
)
6305 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6306 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6309 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6310 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6312 for_each_bit(i
, so
->enabled_mask
) {
6313 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6314 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6315 counter_buffer_idx
= -1;
6317 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6318 /* The array of counters buffer is optional. */
6319 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6320 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6322 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6324 si_cs_emit_write_event_eop(cs
,
6325 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6326 radv_cmd_buffer_uses_mec(cmd_buffer
),
6327 V_028A90_PS_DONE
, 0,
6330 va
, EOP_DATA_GDS(i
, 1), 0);
6332 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6336 radv_set_streamout_enable(cmd_buffer
, false);
6339 void radv_CmdEndTransformFeedbackEXT(
6340 VkCommandBuffer commandBuffer
,
6341 uint32_t firstCounterBuffer
,
6342 uint32_t counterBufferCount
,
6343 const VkBuffer
* pCounterBuffers
,
6344 const VkDeviceSize
* pCounterBufferOffsets
)
6346 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6348 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6349 gfx10_emit_streamout_end(cmd_buffer
,
6350 firstCounterBuffer
, counterBufferCount
,
6351 pCounterBuffers
, pCounterBufferOffsets
);
6353 radv_emit_streamout_end(cmd_buffer
,
6354 firstCounterBuffer
, counterBufferCount
,
6355 pCounterBuffers
, pCounterBufferOffsets
);
6359 void radv_CmdDrawIndirectByteCountEXT(
6360 VkCommandBuffer commandBuffer
,
6361 uint32_t instanceCount
,
6362 uint32_t firstInstance
,
6363 VkBuffer _counterBuffer
,
6364 VkDeviceSize counterBufferOffset
,
6365 uint32_t counterOffset
,
6366 uint32_t vertexStride
)
6368 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6369 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6370 struct radv_draw_info info
= {};
6372 info
.instance_count
= instanceCount
;
6373 info
.first_instance
= firstInstance
;
6374 info
.strmout_buffer
= counterBuffer
;
6375 info
.strmout_buffer_offset
= counterBufferOffset
;
6376 info
.stride
= vertexStride
;
6378 radv_draw(cmd_buffer
, &info
);
6381 /* VK_AMD_buffer_marker */
6382 void radv_CmdWriteBufferMarkerAMD(
6383 VkCommandBuffer commandBuffer
,
6384 VkPipelineStageFlagBits pipelineStage
,
6386 VkDeviceSize dstOffset
,
6389 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6390 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6391 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6392 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6394 si_emit_cache_flush(cmd_buffer
);
6396 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 12);
6398 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6399 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6400 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6401 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6402 COPY_DATA_WR_CONFIRM
);
6403 radeon_emit(cs
, marker
);
6405 radeon_emit(cs
, va
);
6406 radeon_emit(cs
, va
>> 32);
6408 si_cs_emit_write_event_eop(cs
,
6409 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6410 radv_cmd_buffer_uses_mec(cmd_buffer
),
6411 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6413 EOP_DATA_SEL_VALUE_32BIT
,
6415 cmd_buffer
->gfx9_eop_bug_va
);
6418 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);