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6a0640e277672207e09c24aef15b2fe51d046ce2
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
497 }
498
499 static void
500 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
501 struct radv_pipeline *pipeline,
502 gl_shader_stage stage,
503 int idx, uint64_t va)
504 {
505 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
506 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
507 if (loc->sgpr_idx == -1)
508 return;
509 assert(loc->num_sgprs == 2);
510 assert(!loc->indirect);
511 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
512 radeon_emit(cmd_buffer->cs, va);
513 radeon_emit(cmd_buffer->cs, va >> 32);
514 }
515
516 static void
517 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
518 struct radv_pipeline *pipeline)
519 {
520 int num_samples = pipeline->graphics.ms.num_samples;
521 struct radv_multisample_state *ms = &pipeline->graphics.ms;
522 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
525 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
526 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
527
528 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
529 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
530
531 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
532 return;
533
534 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
535 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
536 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
537
538 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
539
540 /* GFX9: Flush DFSM when the AA mode changes. */
541 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
542 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
543 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
544 }
545 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
546 uint32_t offset;
547 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
548 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
549 if (loc->sgpr_idx == -1)
550 return;
551 assert(loc->num_sgprs == 1);
552 assert(!loc->indirect);
553 switch (num_samples) {
554 default:
555 offset = 0;
556 break;
557 case 2:
558 offset = 1;
559 break;
560 case 4:
561 offset = 3;
562 break;
563 case 8:
564 offset = 7;
565 break;
566 case 16:
567 offset = 15;
568 break;
569 }
570
571 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
572 cmd_buffer->sample_positions_needed = true;
573 }
574 }
575
576 static void
577 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
578 struct radv_pipeline *pipeline)
579 {
580 struct radv_raster_state *raster = &pipeline->graphics.raster;
581
582 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
583 raster->pa_cl_clip_cntl);
584 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
585 raster->spi_interp_control);
586 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
587 raster->pa_su_vtx_cntl);
588 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
589 raster->pa_su_sc_mode_cntl);
590 }
591
592 static inline void
593 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
594 unsigned size)
595 {
596 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
597 si_cp_dma_prefetch(cmd_buffer, va, size);
598 }
599
600 static void
601 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
602 struct radv_pipeline *pipeline,
603 struct radv_shader_variant *shader,
604 struct ac_vs_output_info *outinfo)
605 {
606 struct radeon_winsys *ws = cmd_buffer->device->ws;
607 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
608 unsigned export_count;
609
610 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
611 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
612
613 export_count = MAX2(1, outinfo->param_exports);
614 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
615 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
616
617 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
618 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
619 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
620 V_02870C_SPI_SHADER_4COMP :
621 V_02870C_SPI_SHADER_NONE) |
622 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
623 V_02870C_SPI_SHADER_4COMP :
624 V_02870C_SPI_SHADER_NONE) |
625 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
626 V_02870C_SPI_SHADER_4COMP :
627 V_02870C_SPI_SHADER_NONE));
628
629
630 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
631 radeon_emit(cmd_buffer->cs, va >> 8);
632 radeon_emit(cmd_buffer->cs, va >> 40);
633 radeon_emit(cmd_buffer->cs, shader->rsrc1);
634 radeon_emit(cmd_buffer->cs, shader->rsrc2);
635
636 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
637 S_028818_VTX_W0_FMT(1) |
638 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
639 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
640 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
641
642
643 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
644 pipeline->graphics.pa_cl_vs_out_cntl);
645
646 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
647 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
648 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
649 }
650
651 static void
652 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_shader_variant *shader,
654 struct ac_es_output_info *outinfo)
655 {
656 struct radeon_winsys *ws = cmd_buffer->device->ws;
657 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
658
659 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
660 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
661
662 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
663 outinfo->esgs_itemsize / 4);
664 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
665 radeon_emit(cmd_buffer->cs, va >> 8);
666 radeon_emit(cmd_buffer->cs, va >> 40);
667 radeon_emit(cmd_buffer->cs, shader->rsrc1);
668 radeon_emit(cmd_buffer->cs, shader->rsrc2);
669 }
670
671 static void
672 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 struct radeon_winsys *ws = cmd_buffer->device->ws;
676 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
677 uint32_t rsrc2 = shader->rsrc2;
678
679 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
680 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
681
682 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
683 radeon_emit(cmd_buffer->cs, va >> 8);
684 radeon_emit(cmd_buffer->cs, va >> 40);
685
686 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
687 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
688 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
689 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
690
691 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
692 radeon_emit(cmd_buffer->cs, shader->rsrc1);
693 radeon_emit(cmd_buffer->cs, rsrc2);
694 }
695
696 static void
697 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_shader_variant *shader)
699 {
700 struct radeon_winsys *ws = cmd_buffer->device->ws;
701 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
702
703 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
704 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
705
706 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
707 radeon_emit(cmd_buffer->cs, va >> 8);
708 radeon_emit(cmd_buffer->cs, va >> 40);
709 radeon_emit(cmd_buffer->cs, shader->rsrc1);
710 radeon_emit(cmd_buffer->cs, shader->rsrc2);
711 }
712
713 static void
714 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
715 struct radv_pipeline *pipeline)
716 {
717 struct radv_shader_variant *vs;
718
719 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
720
721 vs = pipeline->shaders[MESA_SHADER_VERTEX];
722
723 if (vs->info.vs.as_ls)
724 radv_emit_hw_ls(cmd_buffer, vs);
725 else if (vs->info.vs.as_es)
726 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
727 else
728 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
731 }
732
733
734 static void
735 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
736 struct radv_pipeline *pipeline)
737 {
738 if (!radv_pipeline_has_tess(pipeline))
739 return;
740
741 struct radv_shader_variant *tes, *tcs;
742
743 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
744 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
745
746 if (tes->info.tes.as_es)
747 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
748 else
749 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
750
751 radv_emit_hw_hs(cmd_buffer, tcs);
752
753 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
754 pipeline->graphics.tess.tf_param);
755
756 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
757 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
758 pipeline->graphics.tess.ls_hs_config);
759 else
760 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
761 pipeline->graphics.tess.ls_hs_config);
762
763 struct ac_userdata_info *loc;
764
765 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
766 if (loc->sgpr_idx != -1) {
767 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
768 assert(loc->num_sgprs == 4);
769 assert(!loc->indirect);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
771 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
772 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
773 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
774 pipeline->graphics.tess.num_tcs_input_cp << 26);
775 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
776 }
777
778 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
779 if (loc->sgpr_idx != -1) {
780 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
781 assert(loc->num_sgprs == 1);
782 assert(!loc->indirect);
783
784 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
785 pipeline->graphics.tess.offchip_layout);
786 }
787
788 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
789 if (loc->sgpr_idx != -1) {
790 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
791 assert(loc->num_sgprs == 1);
792 assert(!loc->indirect);
793
794 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
795 pipeline->graphics.tess.tcs_in_layout);
796 }
797 }
798
799 static void
800 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
801 struct radv_pipeline *pipeline)
802 {
803 struct radeon_winsys *ws = cmd_buffer->device->ws;
804 struct radv_shader_variant *gs;
805 uint64_t va;
806
807 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
808
809 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
810 if (!gs)
811 return;
812
813 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
814
815 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
816 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
817 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
818 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
819
820 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
821
822 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
823
824 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
826 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
827 radeon_emit(cmd_buffer->cs, 0);
828 radeon_emit(cmd_buffer->cs, 0);
829 radeon_emit(cmd_buffer->cs, 0);
830
831 uint32_t gs_num_invocations = gs->info.gs.invocations;
832 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
833 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
834 S_028B90_ENABLE(gs_num_invocations > 0));
835
836 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
837 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
838 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
839
840 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
841 radeon_emit(cmd_buffer->cs, va >> 8);
842 radeon_emit(cmd_buffer->cs, va >> 40);
843 radeon_emit(cmd_buffer->cs, gs->rsrc1);
844 radeon_emit(cmd_buffer->cs, gs->rsrc2);
845
846 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
847
848 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
849 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
850 if (loc->sgpr_idx != -1) {
851 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
852 uint32_t num_entries = 64;
853 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
854
855 if (is_vi)
856 num_entries *= stride;
857
858 stride = S_008F04_STRIDE(stride);
859 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
860 radeon_emit(cmd_buffer->cs, stride);
861 radeon_emit(cmd_buffer->cs, num_entries);
862 }
863 }
864
865 static void
866 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
867 struct radv_pipeline *pipeline)
868 {
869 struct radeon_winsys *ws = cmd_buffer->device->ws;
870 struct radv_shader_variant *ps;
871 uint64_t va;
872 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
873 struct radv_blend_state *blend = &pipeline->graphics.blend;
874 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
875
876 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
877 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
878 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
879 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
880
881 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
882 radeon_emit(cmd_buffer->cs, va >> 8);
883 radeon_emit(cmd_buffer->cs, va >> 40);
884 radeon_emit(cmd_buffer->cs, ps->rsrc1);
885 radeon_emit(cmd_buffer->cs, ps->rsrc2);
886
887 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
888 pipeline->graphics.db_shader_control);
889
890 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
891 ps->config.spi_ps_input_ena);
892
893 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
894 ps->config.spi_ps_input_addr);
895
896 if (ps->info.info.ps.force_persample)
897 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
898
899 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
900 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
901
902 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
903
904 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
905 pipeline->graphics.shader_z_format);
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
908
909 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
910 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
911
912 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
913 /* optimise this? */
914 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
916 }
917
918 if (pipeline->graphics.ps_input_cntl_num) {
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
920 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
921 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
922 }
923 }
924 }
925
926 static void
927 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
928 struct radv_pipeline *pipeline)
929 {
930 struct radeon_winsys_cs *cs = cmd_buffer->cs;
931
932 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
933 return;
934
935 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
936 pipeline->graphics.vtx_reuse_depth);
937 }
938
939 static void
940 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
941 {
942 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
943
944 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
945 return;
946
947 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
948 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
949 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
950 radv_update_multisample_state(cmd_buffer, pipeline);
951 radv_emit_vertex_shader(cmd_buffer, pipeline);
952 radv_emit_tess_shaders(cmd_buffer, pipeline);
953 radv_emit_geometry_shader(cmd_buffer, pipeline);
954 radv_emit_fragment_shader(cmd_buffer, pipeline);
955 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
956
957 cmd_buffer->scratch_size_needed =
958 MAX2(cmd_buffer->scratch_size_needed,
959 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
960
961 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
962 S_0286E8_WAVES(pipeline->max_waves) |
963 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
964
965 if (!cmd_buffer->state.emitted_pipeline ||
966 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
967 pipeline->graphics.can_use_guardband)
968 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
969
970 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
971
972 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
973 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
974 } else {
975 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
976 }
977 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
978
979 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
980
981 cmd_buffer->state.emitted_pipeline = pipeline;
982 }
983
984 static void
985 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
986 {
987 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
988 cmd_buffer->state.dynamic.viewport.viewports);
989 }
990
991 static void
992 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
993 {
994 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
995
996 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
997 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
998 si_emit_cache_flush(cmd_buffer);
999 }
1000 si_write_scissors(cmd_buffer->cs, 0, count,
1001 cmd_buffer->state.dynamic.scissor.scissors,
1002 cmd_buffer->state.dynamic.viewport.viewports,
1003 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1004 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1005 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1006 }
1007
1008 static void
1009 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1010 {
1011 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1014 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1015 }
1016
1017 static void
1018 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1019 {
1020 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1021
1022 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1023 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1024 }
1025
1026 static void
1027 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1028 {
1029 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1030
1031 radeon_set_context_reg_seq(cmd_buffer->cs,
1032 R_028430_DB_STENCILREFMASK, 2);
1033 radeon_emit(cmd_buffer->cs,
1034 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1035 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1036 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1037 S_028430_STENCILOPVAL(1));
1038 radeon_emit(cmd_buffer->cs,
1039 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1040 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1041 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1042 S_028434_STENCILOPVAL_BF(1));
1043 }
1044
1045 static void
1046 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1047 {
1048 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1049
1050 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1051 fui(d->depth_bounds.min));
1052 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1053 fui(d->depth_bounds.max));
1054 }
1055
1056 static void
1057 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1058 {
1059 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1060 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1061 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1062 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1063
1064 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1065 radeon_set_context_reg_seq(cmd_buffer->cs,
1066 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1067 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1068 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1069 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1070 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1071 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1072 }
1073 }
1074
1075 static void
1076 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1077 int index,
1078 struct radv_color_buffer_info *cb)
1079 {
1080 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1081
1082 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1083 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1084 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1085 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1087 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1088 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1089 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1090 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1091 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1092 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1093 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1094 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1095
1096 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1097 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1098 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1099
1100 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1101 cb->gfx9_epitch);
1102 } else {
1103 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1104 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1105 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1106 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1107 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1108 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1109 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1110 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1111 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1112 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1115
1116 if (is_vi) { /* DCC BASE */
1117 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1118 }
1119 }
1120 }
1121
1122 static void
1123 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1124 struct radv_ds_buffer_info *ds,
1125 struct radv_image *image,
1126 VkImageLayout layout)
1127 {
1128 uint32_t db_z_info = ds->db_z_info;
1129 uint32_t db_stencil_info = ds->db_stencil_info;
1130
1131 if (!radv_layout_has_htile(image, layout,
1132 radv_image_queue_family_mask(image,
1133 cmd_buffer->queue_family_index,
1134 cmd_buffer->queue_family_index))) {
1135 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1136 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1137 }
1138
1139 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1140 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1141
1142
1143 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1144 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1145 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1146 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1147 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1148
1149 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1150 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1151 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1152 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1153 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1154 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1155 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1156 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1157 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1158 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1160
1161 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1162 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1164 } else {
1165 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1166
1167 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1168 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1169 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1170 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1171 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1173 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1174 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1176 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1177
1178 }
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1181 ds->pa_su_poly_offset_db_fmt_cntl);
1182 }
1183
1184 void
1185 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1186 struct radv_image *image,
1187 VkClearDepthStencilValue ds_clear_value,
1188 VkImageAspectFlags aspects)
1189 {
1190 uint64_t va = radv_buffer_get_va(image->bo);
1191 va += image->offset + image->clear_value_offset;
1192 unsigned reg_offset = 0, reg_count = 0;
1193
1194 if (!image->surface.htile_size || !aspects)
1195 return;
1196
1197 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1198 ++reg_count;
1199 } else {
1200 ++reg_offset;
1201 va += 4;
1202 }
1203 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1204 ++reg_count;
1205
1206 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1207
1208 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1209 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1210 S_370_WR_CONFIRM(1) |
1211 S_370_ENGINE_SEL(V_370_PFP));
1212 radeon_emit(cmd_buffer->cs, va);
1213 radeon_emit(cmd_buffer->cs, va >> 32);
1214 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1215 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1216 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1217 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1218
1219 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1220 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1221 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1222 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1223 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1224 }
1225
1226 static void
1227 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1228 struct radv_image *image)
1229 {
1230 uint64_t va = radv_buffer_get_va(image->bo);
1231 va += image->offset + image->clear_value_offset;
1232
1233 if (!image->surface.htile_size)
1234 return;
1235
1236 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1237
1238 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1239 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1240 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1241 COPY_DATA_COUNT_SEL);
1242 radeon_emit(cmd_buffer->cs, va);
1243 radeon_emit(cmd_buffer->cs, va >> 32);
1244 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1245 radeon_emit(cmd_buffer->cs, 0);
1246
1247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1248 radeon_emit(cmd_buffer->cs, 0);
1249 }
1250
1251 /*
1252 *with DCC some colors don't require CMASK elimiation before being
1253 * used as a texture. This sets a predicate value to determine if the
1254 * cmask eliminate is required.
1255 */
1256 void
1257 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1258 struct radv_image *image,
1259 bool value)
1260 {
1261 uint64_t pred_val = value;
1262 uint64_t va = radv_buffer_get_va(image->bo);
1263 va += image->offset + image->dcc_pred_offset;
1264
1265 if (!image->surface.dcc_size)
1266 return;
1267
1268 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1269
1270 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1271 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1272 S_370_WR_CONFIRM(1) |
1273 S_370_ENGINE_SEL(V_370_PFP));
1274 radeon_emit(cmd_buffer->cs, va);
1275 radeon_emit(cmd_buffer->cs, va >> 32);
1276 radeon_emit(cmd_buffer->cs, pred_val);
1277 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1278 }
1279
1280 void
1281 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1282 struct radv_image *image,
1283 int idx,
1284 uint32_t color_values[2])
1285 {
1286 uint64_t va = radv_buffer_get_va(image->bo);
1287 va += image->offset + image->clear_value_offset;
1288
1289 if (!image->cmask.size && !image->surface.dcc_size)
1290 return;
1291
1292 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1293
1294 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1295 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1296 S_370_WR_CONFIRM(1) |
1297 S_370_ENGINE_SEL(V_370_PFP));
1298 radeon_emit(cmd_buffer->cs, va);
1299 radeon_emit(cmd_buffer->cs, va >> 32);
1300 radeon_emit(cmd_buffer->cs, color_values[0]);
1301 radeon_emit(cmd_buffer->cs, color_values[1]);
1302
1303 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1304 radeon_emit(cmd_buffer->cs, color_values[0]);
1305 radeon_emit(cmd_buffer->cs, color_values[1]);
1306 }
1307
1308 static void
1309 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1310 struct radv_image *image,
1311 int idx)
1312 {
1313 uint64_t va = radv_buffer_get_va(image->bo);
1314 va += image->offset + image->clear_value_offset;
1315
1316 if (!image->cmask.size && !image->surface.dcc_size)
1317 return;
1318
1319 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1320 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1321
1322 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1323 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1324 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1325 COPY_DATA_COUNT_SEL);
1326 radeon_emit(cmd_buffer->cs, va);
1327 radeon_emit(cmd_buffer->cs, va >> 32);
1328 radeon_emit(cmd_buffer->cs, reg >> 2);
1329 radeon_emit(cmd_buffer->cs, 0);
1330
1331 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1332 radeon_emit(cmd_buffer->cs, 0);
1333 }
1334
1335 void
1336 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1337 {
1338 int i;
1339 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1340 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1341
1342 /* this may happen for inherited secondary recording */
1343 if (!framebuffer)
1344 return;
1345
1346 for (i = 0; i < 8; ++i) {
1347 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1348 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1349 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1350 continue;
1351 }
1352
1353 int idx = subpass->color_attachments[i].attachment;
1354 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1355
1356 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1357
1358 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1359 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1360
1361 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1362 }
1363
1364 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1365 int idx = subpass->depth_stencil_attachment.attachment;
1366 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1367 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1368 struct radv_image *image = att->attachment->image;
1369 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1370 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1371 cmd_buffer->queue_family_index,
1372 cmd_buffer->queue_family_index);
1373 /* We currently don't support writing decompressed HTILE */
1374 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1375 radv_layout_is_htile_compressed(image, layout, queue_mask));
1376
1377 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1378
1379 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1380 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1381 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1382 }
1383 radv_load_depth_clear_regs(cmd_buffer, image);
1384 } else {
1385 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1386 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1387 else
1388 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1389
1390 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1391 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1392 }
1393 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1394 S_028208_BR_X(framebuffer->width) |
1395 S_028208_BR_Y(framebuffer->height));
1396
1397 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1398 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1399 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1400 }
1401 }
1402
1403 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1404 {
1405 uint32_t db_count_control;
1406
1407 if(!cmd_buffer->state.active_occlusion_queries) {
1408 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1409 db_count_control = 0;
1410 } else {
1411 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1412 }
1413 } else {
1414 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1415 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1416 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1417 S_028004_ZPASS_ENABLE(1) |
1418 S_028004_SLICE_EVEN_ENABLE(1) |
1419 S_028004_SLICE_ODD_ENABLE(1);
1420 } else {
1421 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1422 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1423 }
1424 }
1425
1426 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1427 }
1428
1429 static void
1430 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1431 {
1432 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1433 return;
1434
1435 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1436 radv_emit_viewport(cmd_buffer);
1437
1438 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1439 radv_emit_scissor(cmd_buffer);
1440
1441 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1442 radv_emit_line_width(cmd_buffer);
1443
1444 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1445 radv_emit_blend_constants(cmd_buffer);
1446
1447 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1448 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1449 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1450 radv_emit_stencil(cmd_buffer);
1451
1452 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1453 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1454 radv_emit_depth_bounds(cmd_buffer);
1455
1456 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1457 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1458 radv_emit_depth_biais(cmd_buffer);
1459
1460 cmd_buffer->state.dirty = 0;
1461 }
1462
1463 static void
1464 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_pipeline *pipeline,
1466 int idx,
1467 uint64_t va,
1468 gl_shader_stage stage)
1469 {
1470 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1471 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1472
1473 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1474 return;
1475
1476 assert(!desc_set_loc->indirect);
1477 assert(desc_set_loc->num_sgprs == 2);
1478 radeon_set_sh_reg_seq(cmd_buffer->cs,
1479 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1480 radeon_emit(cmd_buffer->cs, va);
1481 radeon_emit(cmd_buffer->cs, va >> 32);
1482 }
1483
1484 static void
1485 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1486 VkShaderStageFlags stages,
1487 struct radv_descriptor_set *set,
1488 unsigned idx)
1489 {
1490 if (cmd_buffer->state.pipeline) {
1491 radv_foreach_stage(stage, stages) {
1492 if (cmd_buffer->state.pipeline->shaders[stage])
1493 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1494 idx, set->va,
1495 stage);
1496 }
1497 }
1498
1499 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1500 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1501 idx, set->va,
1502 MESA_SHADER_COMPUTE);
1503 }
1504
1505 static void
1506 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1507 {
1508 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1509 unsigned bo_offset;
1510
1511 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1512 set->mapped_ptr,
1513 &bo_offset))
1514 return;
1515
1516 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1517 set->va += bo_offset;
1518 }
1519
1520 static void
1521 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1522 {
1523 uint32_t size = MAX_SETS * 2 * 4;
1524 uint32_t offset;
1525 void *ptr;
1526
1527 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1528 256, &offset, &ptr))
1529 return;
1530
1531 for (unsigned i = 0; i < MAX_SETS; i++) {
1532 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1533 uint64_t set_va = 0;
1534 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1535 if (set)
1536 set_va = set->va;
1537 uptr[0] = set_va & 0xffffffff;
1538 uptr[1] = set_va >> 32;
1539 }
1540
1541 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1542 va += offset;
1543
1544 if (cmd_buffer->state.pipeline) {
1545 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1546 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1547 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1548
1549 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1550 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1551 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1552
1553 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1554 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1555 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1556
1557 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1558 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1559 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1560
1561 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1562 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1563 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1564 }
1565
1566 if (cmd_buffer->state.compute_pipeline)
1567 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1568 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1569 }
1570
1571 static void
1572 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1573 VkShaderStageFlags stages)
1574 {
1575 unsigned i;
1576
1577 if (!cmd_buffer->state.descriptors_dirty)
1578 return;
1579
1580 if (cmd_buffer->state.push_descriptors_dirty)
1581 radv_flush_push_descriptors(cmd_buffer);
1582
1583 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1584 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1585 radv_flush_indirect_descriptor_sets(cmd_buffer);
1586 }
1587
1588 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1589 cmd_buffer->cs,
1590 MAX_SETS * MESA_SHADER_STAGES * 4);
1591
1592 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1593 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1594 if (!set)
1595 continue;
1596
1597 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1598 }
1599 cmd_buffer->state.descriptors_dirty = 0;
1600 cmd_buffer->state.push_descriptors_dirty = false;
1601
1602 radv_save_descriptors(cmd_buffer);
1603
1604 assert(cmd_buffer->cs->cdw <= cdw_max);
1605 }
1606
1607 static void
1608 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_pipeline *pipeline,
1610 VkShaderStageFlags stages)
1611 {
1612 struct radv_pipeline_layout *layout = pipeline->layout;
1613 unsigned offset;
1614 void *ptr;
1615 uint64_t va;
1616
1617 stages &= cmd_buffer->push_constant_stages;
1618 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1619 return;
1620
1621 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1622 16 * layout->dynamic_offset_count,
1623 256, &offset, &ptr))
1624 return;
1625
1626 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1627 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1628 16 * layout->dynamic_offset_count);
1629
1630 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1631 va += offset;
1632
1633 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1634 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1635
1636 radv_foreach_stage(stage, stages) {
1637 if (pipeline->shaders[stage]) {
1638 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1639 AC_UD_PUSH_CONSTANTS, va);
1640 }
1641 }
1642
1643 cmd_buffer->push_constant_stages &= ~stages;
1644 assert(cmd_buffer->cs->cdw <= cdw_max);
1645 }
1646
1647 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1648 bool indexed_draw)
1649 {
1650 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1651
1652 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1653 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1654 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1655 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1656 primitive_reset_en);
1657 } else {
1658 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1659 primitive_reset_en);
1660 }
1661 }
1662
1663 if (primitive_reset_en) {
1664 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1665
1666 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1667 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1668 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1669 primitive_reset_index);
1670 }
1671 }
1672 }
1673
1674 static bool
1675 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1676 {
1677 struct radv_device *device = cmd_buffer->device;
1678
1679 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1680 cmd_buffer->state.pipeline->vertex_elements.count &&
1681 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1682 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1683 unsigned vb_offset;
1684 void *vb_ptr;
1685 uint32_t i = 0;
1686 uint32_t count = velems->count;
1687 uint64_t va;
1688
1689 /* allocate some descriptor state for vertex buffers */
1690 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1691 &vb_offset, &vb_ptr))
1692 return false;
1693
1694 for (i = 0; i < count; i++) {
1695 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1696 uint32_t offset;
1697 int vb = velems->binding[i];
1698 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1699 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1700
1701 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1702 va = radv_buffer_get_va(buffer->bo);
1703
1704 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1705 va += offset + buffer->offset;
1706 desc[0] = va;
1707 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1708 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1709 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1710 else
1711 desc[2] = buffer->size - offset;
1712 desc[3] = velems->rsrc_word3[i];
1713 }
1714
1715 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1716 va += vb_offset;
1717
1718 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1719 AC_UD_VS_VERTEX_BUFFERS, va);
1720 }
1721 cmd_buffer->state.vb_dirty = false;
1722
1723 return true;
1724 }
1725
1726 static void
1727 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1728 bool indexed_draw, bool instanced_draw,
1729 bool indirect_draw,
1730 uint32_t draw_vertex_count)
1731 {
1732 uint32_t ia_multi_vgt_param;
1733
1734 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1735 cmd_buffer->cs, 4096);
1736
1737 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1738 return;
1739
1740 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1741 radv_emit_graphics_pipeline(cmd_buffer);
1742
1743 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1744 radv_emit_framebuffer_state(cmd_buffer);
1745
1746 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1747 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1748 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1749 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1750 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1751 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1752 else
1753 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1754 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1755 }
1756
1757 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1758
1759 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1760
1761 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1762 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1763 VK_SHADER_STAGE_ALL_GRAPHICS);
1764
1765 assert(cmd_buffer->cs->cdw <= cdw_max);
1766
1767 si_emit_cache_flush(cmd_buffer);
1768 }
1769
1770 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1771 VkPipelineStageFlags src_stage_mask)
1772 {
1773 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1774 VK_PIPELINE_STAGE_TRANSFER_BIT |
1775 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1776 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1777 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1778 }
1779
1780 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1781 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1782 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1783 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1784 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1785 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1786 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1787 VK_PIPELINE_STAGE_TRANSFER_BIT |
1788 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1789 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1790 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1791 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1792 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1793 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1794 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1795 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1796 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1797 }
1798 }
1799
1800 static enum radv_cmd_flush_bits
1801 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1802 VkAccessFlags src_flags)
1803 {
1804 enum radv_cmd_flush_bits flush_bits = 0;
1805 uint32_t b;
1806 for_each_bit(b, src_flags) {
1807 switch ((VkAccessFlagBits)(1 << b)) {
1808 case VK_ACCESS_SHADER_WRITE_BIT:
1809 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1810 break;
1811 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1812 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1813 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1814 break;
1815 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1816 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1817 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1818 break;
1819 case VK_ACCESS_TRANSFER_WRITE_BIT:
1820 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1822 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1823 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1824 RADV_CMD_FLAG_INV_GLOBAL_L2;
1825 break;
1826 default:
1827 break;
1828 }
1829 }
1830 return flush_bits;
1831 }
1832
1833 static enum radv_cmd_flush_bits
1834 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1835 VkAccessFlags dst_flags,
1836 struct radv_image *image)
1837 {
1838 enum radv_cmd_flush_bits flush_bits = 0;
1839 uint32_t b;
1840 for_each_bit(b, dst_flags) {
1841 switch ((VkAccessFlagBits)(1 << b)) {
1842 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1843 case VK_ACCESS_INDEX_READ_BIT:
1844 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1845 break;
1846 case VK_ACCESS_UNIFORM_READ_BIT:
1847 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1848 break;
1849 case VK_ACCESS_SHADER_READ_BIT:
1850 case VK_ACCESS_TRANSFER_READ_BIT:
1851 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1852 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1853 RADV_CMD_FLAG_INV_GLOBAL_L2;
1854 break;
1855 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1856 /* TODO: change to image && when the image gets passed
1857 * through from the subpass. */
1858 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1859 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1860 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1861 break;
1862 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1863 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1864 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1865 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1866 break;
1867 default:
1868 break;
1869 }
1870 }
1871 return flush_bits;
1872 }
1873
1874 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1875 {
1876 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1877 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1878 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1879 NULL);
1880 }
1881
1882 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1883 VkAttachmentReference att)
1884 {
1885 unsigned idx = att.attachment;
1886 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1887 VkImageSubresourceRange range;
1888 range.aspectMask = 0;
1889 range.baseMipLevel = view->base_mip;
1890 range.levelCount = 1;
1891 range.baseArrayLayer = view->base_layer;
1892 range.layerCount = cmd_buffer->state.framebuffer->layers;
1893
1894 radv_handle_image_transition(cmd_buffer,
1895 view->image,
1896 cmd_buffer->state.attachments[idx].current_layout,
1897 att.layout, 0, 0, &range,
1898 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1899
1900 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1901
1902
1903 }
1904
1905 void
1906 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1907 const struct radv_subpass *subpass, bool transitions)
1908 {
1909 if (transitions) {
1910 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1911
1912 for (unsigned i = 0; i < subpass->color_count; ++i) {
1913 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1914 radv_handle_subpass_image_transition(cmd_buffer,
1915 subpass->color_attachments[i]);
1916 }
1917
1918 for (unsigned i = 0; i < subpass->input_count; ++i) {
1919 radv_handle_subpass_image_transition(cmd_buffer,
1920 subpass->input_attachments[i]);
1921 }
1922
1923 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1924 radv_handle_subpass_image_transition(cmd_buffer,
1925 subpass->depth_stencil_attachment);
1926 }
1927 }
1928
1929 cmd_buffer->state.subpass = subpass;
1930
1931 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1932 }
1933
1934 static VkResult
1935 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1936 struct radv_render_pass *pass,
1937 const VkRenderPassBeginInfo *info)
1938 {
1939 struct radv_cmd_state *state = &cmd_buffer->state;
1940
1941 if (pass->attachment_count == 0) {
1942 state->attachments = NULL;
1943 return VK_SUCCESS;
1944 }
1945
1946 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1947 pass->attachment_count *
1948 sizeof(state->attachments[0]),
1949 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1950 if (state->attachments == NULL) {
1951 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1952 return cmd_buffer->record_result;
1953 }
1954
1955 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1956 struct radv_render_pass_attachment *att = &pass->attachments[i];
1957 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1958 VkImageAspectFlags clear_aspects = 0;
1959
1960 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1961 /* color attachment */
1962 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1963 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1964 }
1965 } else {
1966 /* depthstencil attachment */
1967 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1968 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1969 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1970 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1971 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1972 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1973 }
1974 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1975 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1976 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1977 }
1978 }
1979
1980 state->attachments[i].pending_clear_aspects = clear_aspects;
1981 state->attachments[i].cleared_views = 0;
1982 if (clear_aspects && info) {
1983 assert(info->clearValueCount > i);
1984 state->attachments[i].clear_value = info->pClearValues[i];
1985 }
1986
1987 state->attachments[i].current_layout = att->initial_layout;
1988 }
1989
1990 return VK_SUCCESS;
1991 }
1992
1993 VkResult radv_AllocateCommandBuffers(
1994 VkDevice _device,
1995 const VkCommandBufferAllocateInfo *pAllocateInfo,
1996 VkCommandBuffer *pCommandBuffers)
1997 {
1998 RADV_FROM_HANDLE(radv_device, device, _device);
1999 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2000
2001 VkResult result = VK_SUCCESS;
2002 uint32_t i;
2003
2004 memset(pCommandBuffers, 0,
2005 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2006
2007 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2008
2009 if (!list_empty(&pool->free_cmd_buffers)) {
2010 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2011
2012 list_del(&cmd_buffer->pool_link);
2013 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2014
2015 result = radv_reset_cmd_buffer(cmd_buffer);
2016 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2017 cmd_buffer->level = pAllocateInfo->level;
2018
2019 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2020 } else {
2021 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2022 &pCommandBuffers[i]);
2023 }
2024 if (result != VK_SUCCESS)
2025 break;
2026 }
2027
2028 if (result != VK_SUCCESS)
2029 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2030 i, pCommandBuffers);
2031
2032 return result;
2033 }
2034
2035 void radv_FreeCommandBuffers(
2036 VkDevice device,
2037 VkCommandPool commandPool,
2038 uint32_t commandBufferCount,
2039 const VkCommandBuffer *pCommandBuffers)
2040 {
2041 for (uint32_t i = 0; i < commandBufferCount; i++) {
2042 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2043
2044 if (cmd_buffer) {
2045 if (cmd_buffer->pool) {
2046 list_del(&cmd_buffer->pool_link);
2047 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2048 } else
2049 radv_cmd_buffer_destroy(cmd_buffer);
2050
2051 }
2052 }
2053 }
2054
2055 VkResult radv_ResetCommandBuffer(
2056 VkCommandBuffer commandBuffer,
2057 VkCommandBufferResetFlags flags)
2058 {
2059 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2060 return radv_reset_cmd_buffer(cmd_buffer);
2061 }
2062
2063 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2064 {
2065 struct radv_device *device = cmd_buffer->device;
2066 if (device->gfx_init) {
2067 uint64_t va = radv_buffer_get_va(device->gfx_init);
2068 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2069 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2070 radeon_emit(cmd_buffer->cs, va);
2071 radeon_emit(cmd_buffer->cs, va >> 32);
2072 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2073 } else
2074 si_init_config(cmd_buffer);
2075 }
2076
2077 VkResult radv_BeginCommandBuffer(
2078 VkCommandBuffer commandBuffer,
2079 const VkCommandBufferBeginInfo *pBeginInfo)
2080 {
2081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2082 VkResult result;
2083
2084 result = radv_reset_cmd_buffer(cmd_buffer);
2085 if (result != VK_SUCCESS)
2086 return result;
2087
2088 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2089 cmd_buffer->state.last_primitive_reset_en = -1;
2090 cmd_buffer->usage_flags = pBeginInfo->flags;
2091
2092 /* setup initial configuration into command buffer */
2093 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2094 switch (cmd_buffer->queue_family_index) {
2095 case RADV_QUEUE_GENERAL:
2096 emit_gfx_buffer_state(cmd_buffer);
2097 radv_set_db_count_control(cmd_buffer);
2098 break;
2099 case RADV_QUEUE_COMPUTE:
2100 si_init_compute(cmd_buffer);
2101 break;
2102 case RADV_QUEUE_TRANSFER:
2103 default:
2104 break;
2105 }
2106 }
2107
2108 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2109 assert(pBeginInfo->pInheritanceInfo);
2110 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2111 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2112
2113 struct radv_subpass *subpass =
2114 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2115
2116 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2117 if (result != VK_SUCCESS)
2118 return result;
2119
2120 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2121 }
2122
2123 radv_cmd_buffer_trace_emit(cmd_buffer);
2124 return result;
2125 }
2126
2127 void radv_CmdBindVertexBuffers(
2128 VkCommandBuffer commandBuffer,
2129 uint32_t firstBinding,
2130 uint32_t bindingCount,
2131 const VkBuffer* pBuffers,
2132 const VkDeviceSize* pOffsets)
2133 {
2134 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2135 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2136
2137 /* We have to defer setting up vertex buffer since we need the buffer
2138 * stride from the pipeline. */
2139
2140 assert(firstBinding + bindingCount <= MAX_VBS);
2141 for (uint32_t i = 0; i < bindingCount; i++) {
2142 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2143 vb[firstBinding + i].offset = pOffsets[i];
2144 }
2145
2146 cmd_buffer->state.vb_dirty = true;
2147 }
2148
2149 void radv_CmdBindIndexBuffer(
2150 VkCommandBuffer commandBuffer,
2151 VkBuffer buffer,
2152 VkDeviceSize offset,
2153 VkIndexType indexType)
2154 {
2155 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2156 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2157
2158 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2159 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2160 cmd_buffer->state.index_va += index_buffer->offset + offset;
2161
2162 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2163 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2164 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2165 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2166 }
2167
2168
2169 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2170 struct radv_descriptor_set *set,
2171 unsigned idx)
2172 {
2173 struct radeon_winsys *ws = cmd_buffer->device->ws;
2174
2175 cmd_buffer->state.descriptors[idx] = set;
2176 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2177 if (!set)
2178 return;
2179
2180 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2181
2182 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2183 if (set->descriptors[j])
2184 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2185
2186 if(set->bo)
2187 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2188 }
2189
2190 void radv_CmdBindDescriptorSets(
2191 VkCommandBuffer commandBuffer,
2192 VkPipelineBindPoint pipelineBindPoint,
2193 VkPipelineLayout _layout,
2194 uint32_t firstSet,
2195 uint32_t descriptorSetCount,
2196 const VkDescriptorSet* pDescriptorSets,
2197 uint32_t dynamicOffsetCount,
2198 const uint32_t* pDynamicOffsets)
2199 {
2200 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2201 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2202 unsigned dyn_idx = 0;
2203
2204 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2205 unsigned idx = i + firstSet;
2206 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2207 radv_bind_descriptor_set(cmd_buffer, set, idx);
2208
2209 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2210 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2211 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2212 assert(dyn_idx < dynamicOffsetCount);
2213
2214 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2215 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2216 dst[0] = va;
2217 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2218 dst[2] = range->size;
2219 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2220 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2222 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2223 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2224 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2225 cmd_buffer->push_constant_stages |=
2226 set->layout->dynamic_shader_stages;
2227 }
2228 }
2229 }
2230
2231 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2232 struct radv_descriptor_set *set,
2233 struct radv_descriptor_set_layout *layout)
2234 {
2235 set->size = layout->size;
2236 set->layout = layout;
2237
2238 if (cmd_buffer->push_descriptors.capacity < set->size) {
2239 size_t new_size = MAX2(set->size, 1024);
2240 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2241 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2242
2243 free(set->mapped_ptr);
2244 set->mapped_ptr = malloc(new_size);
2245
2246 if (!set->mapped_ptr) {
2247 cmd_buffer->push_descriptors.capacity = 0;
2248 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2249 return false;
2250 }
2251
2252 cmd_buffer->push_descriptors.capacity = new_size;
2253 }
2254
2255 return true;
2256 }
2257
2258 void radv_meta_push_descriptor_set(
2259 struct radv_cmd_buffer* cmd_buffer,
2260 VkPipelineBindPoint pipelineBindPoint,
2261 VkPipelineLayout _layout,
2262 uint32_t set,
2263 uint32_t descriptorWriteCount,
2264 const VkWriteDescriptorSet* pDescriptorWrites)
2265 {
2266 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2267 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2268 unsigned bo_offset;
2269
2270 assert(set == 0);
2271 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2272
2273 push_set->size = layout->set[set].layout->size;
2274 push_set->layout = layout->set[set].layout;
2275
2276 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2277 &bo_offset,
2278 (void**) &push_set->mapped_ptr))
2279 return;
2280
2281 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2282 push_set->va += bo_offset;
2283
2284 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2285 radv_descriptor_set_to_handle(push_set),
2286 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2287
2288 cmd_buffer->state.descriptors[set] = push_set;
2289 cmd_buffer->state.descriptors_dirty |= (1u << set);
2290 }
2291
2292 void radv_CmdPushDescriptorSetKHR(
2293 VkCommandBuffer commandBuffer,
2294 VkPipelineBindPoint pipelineBindPoint,
2295 VkPipelineLayout _layout,
2296 uint32_t set,
2297 uint32_t descriptorWriteCount,
2298 const VkWriteDescriptorSet* pDescriptorWrites)
2299 {
2300 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2301 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2302 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2303
2304 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2305
2306 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2307 return;
2308
2309 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2310 radv_descriptor_set_to_handle(push_set),
2311 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2312
2313 cmd_buffer->state.descriptors[set] = push_set;
2314 cmd_buffer->state.descriptors_dirty |= (1u << set);
2315 cmd_buffer->state.push_descriptors_dirty = true;
2316 }
2317
2318 void radv_CmdPushDescriptorSetWithTemplateKHR(
2319 VkCommandBuffer commandBuffer,
2320 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2321 VkPipelineLayout _layout,
2322 uint32_t set,
2323 const void* pData)
2324 {
2325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2326 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2327 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2328
2329 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2330
2331 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2332 return;
2333
2334 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2335 descriptorUpdateTemplate, pData);
2336
2337 cmd_buffer->state.descriptors[set] = push_set;
2338 cmd_buffer->state.descriptors_dirty |= (1u << set);
2339 cmd_buffer->state.push_descriptors_dirty = true;
2340 }
2341
2342 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2343 VkPipelineLayout layout,
2344 VkShaderStageFlags stageFlags,
2345 uint32_t offset,
2346 uint32_t size,
2347 const void* pValues)
2348 {
2349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2350 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2351 cmd_buffer->push_constant_stages |= stageFlags;
2352 }
2353
2354 VkResult radv_EndCommandBuffer(
2355 VkCommandBuffer commandBuffer)
2356 {
2357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358
2359 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2360 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2361 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2362 si_emit_cache_flush(cmd_buffer);
2363 }
2364
2365 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2366 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2367
2368 return cmd_buffer->record_result;
2369 }
2370
2371 static void
2372 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2373 {
2374 struct radeon_winsys *ws = cmd_buffer->device->ws;
2375 struct radv_shader_variant *compute_shader;
2376 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2377 uint64_t va;
2378
2379 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2380 return;
2381
2382 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2383
2384 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2385 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2386
2387 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2388 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2389
2390 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2391 cmd_buffer->cs, 16);
2392
2393 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2394 radeon_emit(cmd_buffer->cs, va >> 8);
2395 radeon_emit(cmd_buffer->cs, va >> 40);
2396
2397 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2398 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2399 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2400
2401
2402 cmd_buffer->compute_scratch_size_needed =
2403 MAX2(cmd_buffer->compute_scratch_size_needed,
2404 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2405
2406 /* change these once we have scratch support */
2407 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2408 S_00B860_WAVES(pipeline->max_waves) |
2409 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2410
2411 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2412 radeon_emit(cmd_buffer->cs,
2413 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2414 radeon_emit(cmd_buffer->cs,
2415 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2416 radeon_emit(cmd_buffer->cs,
2417 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2418
2419 assert(cmd_buffer->cs->cdw <= cdw_max);
2420 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2421 }
2422
2423 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2424 {
2425 for (unsigned i = 0; i < MAX_SETS; i++) {
2426 if (cmd_buffer->state.descriptors[i])
2427 cmd_buffer->state.descriptors_dirty |= (1u << i);
2428 }
2429 }
2430
2431 void radv_CmdBindPipeline(
2432 VkCommandBuffer commandBuffer,
2433 VkPipelineBindPoint pipelineBindPoint,
2434 VkPipeline _pipeline)
2435 {
2436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2437 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2438
2439 switch (pipelineBindPoint) {
2440 case VK_PIPELINE_BIND_POINT_COMPUTE:
2441 if (cmd_buffer->state.compute_pipeline == pipeline)
2442 return;
2443 radv_mark_descriptor_sets_dirty(cmd_buffer);
2444
2445 cmd_buffer->state.compute_pipeline = pipeline;
2446 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2447 break;
2448 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2449 if (cmd_buffer->state.pipeline == pipeline)
2450 return;
2451 radv_mark_descriptor_sets_dirty(cmd_buffer);
2452
2453 cmd_buffer->state.pipeline = pipeline;
2454 if (!pipeline)
2455 break;
2456
2457 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2458 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2459
2460 /* Apply the dynamic state from the pipeline */
2461 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2462 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2463 &pipeline->dynamic_state,
2464 pipeline->dynamic_state_mask);
2465
2466 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2467 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2468 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2469 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2470
2471 if (radv_pipeline_has_tess(pipeline))
2472 cmd_buffer->tess_rings_needed = true;
2473
2474 if (radv_pipeline_has_gs(pipeline)) {
2475 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2476 AC_UD_SCRATCH_RING_OFFSETS);
2477 if (cmd_buffer->ring_offsets_idx == -1)
2478 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2479 else if (loc->sgpr_idx != -1)
2480 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2481 }
2482 break;
2483 default:
2484 assert(!"invalid bind point");
2485 break;
2486 }
2487 }
2488
2489 void radv_CmdSetViewport(
2490 VkCommandBuffer commandBuffer,
2491 uint32_t firstViewport,
2492 uint32_t viewportCount,
2493 const VkViewport* pViewports)
2494 {
2495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2496 const uint32_t total_count = firstViewport + viewportCount;
2497
2498 assert(firstViewport < MAX_VIEWPORTS);
2499 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2500
2501 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2502 pViewports, viewportCount * sizeof(*pViewports));
2503
2504 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2505 }
2506
2507 void radv_CmdSetScissor(
2508 VkCommandBuffer commandBuffer,
2509 uint32_t firstScissor,
2510 uint32_t scissorCount,
2511 const VkRect2D* pScissors)
2512 {
2513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2514 const uint32_t total_count = firstScissor + scissorCount;
2515
2516 assert(firstScissor < MAX_SCISSORS);
2517 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2518
2519 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2520 pScissors, scissorCount * sizeof(*pScissors));
2521 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2522 }
2523
2524 void radv_CmdSetLineWidth(
2525 VkCommandBuffer commandBuffer,
2526 float lineWidth)
2527 {
2528 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2529 cmd_buffer->state.dynamic.line_width = lineWidth;
2530 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2531 }
2532
2533 void radv_CmdSetDepthBias(
2534 VkCommandBuffer commandBuffer,
2535 float depthBiasConstantFactor,
2536 float depthBiasClamp,
2537 float depthBiasSlopeFactor)
2538 {
2539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2540
2541 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2542 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2543 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2544
2545 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2546 }
2547
2548 void radv_CmdSetBlendConstants(
2549 VkCommandBuffer commandBuffer,
2550 const float blendConstants[4])
2551 {
2552 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2553
2554 memcpy(cmd_buffer->state.dynamic.blend_constants,
2555 blendConstants, sizeof(float) * 4);
2556
2557 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2558 }
2559
2560 void radv_CmdSetDepthBounds(
2561 VkCommandBuffer commandBuffer,
2562 float minDepthBounds,
2563 float maxDepthBounds)
2564 {
2565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2566
2567 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2568 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2569
2570 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2571 }
2572
2573 void radv_CmdSetStencilCompareMask(
2574 VkCommandBuffer commandBuffer,
2575 VkStencilFaceFlags faceMask,
2576 uint32_t compareMask)
2577 {
2578 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2579
2580 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2581 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2582 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2583 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2584
2585 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2586 }
2587
2588 void radv_CmdSetStencilWriteMask(
2589 VkCommandBuffer commandBuffer,
2590 VkStencilFaceFlags faceMask,
2591 uint32_t writeMask)
2592 {
2593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2594
2595 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2596 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2597 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2598 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2599
2600 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2601 }
2602
2603 void radv_CmdSetStencilReference(
2604 VkCommandBuffer commandBuffer,
2605 VkStencilFaceFlags faceMask,
2606 uint32_t reference)
2607 {
2608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2609
2610 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2611 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2612 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2613 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2614
2615 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2616 }
2617
2618 void radv_CmdExecuteCommands(
2619 VkCommandBuffer commandBuffer,
2620 uint32_t commandBufferCount,
2621 const VkCommandBuffer* pCmdBuffers)
2622 {
2623 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2624
2625 /* Emit pending flushes on primary prior to executing secondary */
2626 si_emit_cache_flush(primary);
2627
2628 for (uint32_t i = 0; i < commandBufferCount; i++) {
2629 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2630
2631 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2632 secondary->scratch_size_needed);
2633 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2634 secondary->compute_scratch_size_needed);
2635
2636 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2637 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2638 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2639 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2640 if (secondary->tess_rings_needed)
2641 primary->tess_rings_needed = true;
2642 if (secondary->sample_positions_needed)
2643 primary->sample_positions_needed = true;
2644
2645 if (secondary->ring_offsets_idx != -1) {
2646 if (primary->ring_offsets_idx == -1)
2647 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2648 else
2649 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2650 }
2651 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2652
2653 primary->state.emitted_pipeline = secondary->state.emitted_pipeline;
2654 primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
2655 primary->state.last_primitive_reset_en = secondary->state.last_primitive_reset_en;
2656 primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
2657 }
2658
2659 /* if we execute secondary we need to mark some stuff to reset dirty */
2660 if (commandBufferCount) {
2661 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2662 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2663 radv_mark_descriptor_sets_dirty(primary);
2664 }
2665 }
2666
2667 VkResult radv_CreateCommandPool(
2668 VkDevice _device,
2669 const VkCommandPoolCreateInfo* pCreateInfo,
2670 const VkAllocationCallbacks* pAllocator,
2671 VkCommandPool* pCmdPool)
2672 {
2673 RADV_FROM_HANDLE(radv_device, device, _device);
2674 struct radv_cmd_pool *pool;
2675
2676 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2677 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2678 if (pool == NULL)
2679 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2680
2681 if (pAllocator)
2682 pool->alloc = *pAllocator;
2683 else
2684 pool->alloc = device->alloc;
2685
2686 list_inithead(&pool->cmd_buffers);
2687 list_inithead(&pool->free_cmd_buffers);
2688
2689 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2690
2691 *pCmdPool = radv_cmd_pool_to_handle(pool);
2692
2693 return VK_SUCCESS;
2694
2695 }
2696
2697 void radv_DestroyCommandPool(
2698 VkDevice _device,
2699 VkCommandPool commandPool,
2700 const VkAllocationCallbacks* pAllocator)
2701 {
2702 RADV_FROM_HANDLE(radv_device, device, _device);
2703 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2704
2705 if (!pool)
2706 return;
2707
2708 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2709 &pool->cmd_buffers, pool_link) {
2710 radv_cmd_buffer_destroy(cmd_buffer);
2711 }
2712
2713 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2714 &pool->free_cmd_buffers, pool_link) {
2715 radv_cmd_buffer_destroy(cmd_buffer);
2716 }
2717
2718 vk_free2(&device->alloc, pAllocator, pool);
2719 }
2720
2721 VkResult radv_ResetCommandPool(
2722 VkDevice device,
2723 VkCommandPool commandPool,
2724 VkCommandPoolResetFlags flags)
2725 {
2726 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2727 VkResult result;
2728
2729 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2730 &pool->cmd_buffers, pool_link) {
2731 result = radv_reset_cmd_buffer(cmd_buffer);
2732 if (result != VK_SUCCESS)
2733 return result;
2734 }
2735
2736 return VK_SUCCESS;
2737 }
2738
2739 void radv_TrimCommandPoolKHR(
2740 VkDevice device,
2741 VkCommandPool commandPool,
2742 VkCommandPoolTrimFlagsKHR flags)
2743 {
2744 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2745
2746 if (!pool)
2747 return;
2748
2749 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2750 &pool->free_cmd_buffers, pool_link) {
2751 radv_cmd_buffer_destroy(cmd_buffer);
2752 }
2753 }
2754
2755 void radv_CmdBeginRenderPass(
2756 VkCommandBuffer commandBuffer,
2757 const VkRenderPassBeginInfo* pRenderPassBegin,
2758 VkSubpassContents contents)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2762 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2763
2764 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2765 cmd_buffer->cs, 2048);
2766 MAYBE_UNUSED VkResult result;
2767
2768 cmd_buffer->state.framebuffer = framebuffer;
2769 cmd_buffer->state.pass = pass;
2770 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2771
2772 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2773 if (result != VK_SUCCESS)
2774 return;
2775
2776 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2777 assert(cmd_buffer->cs->cdw <= cdw_max);
2778
2779 radv_cmd_buffer_clear_subpass(cmd_buffer);
2780 }
2781
2782 void radv_CmdNextSubpass(
2783 VkCommandBuffer commandBuffer,
2784 VkSubpassContents contents)
2785 {
2786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2787
2788 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2789
2790 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2791 2048);
2792
2793 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2794 radv_cmd_buffer_clear_subpass(cmd_buffer);
2795 }
2796
2797 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2798 {
2799 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2800 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2801 if (!pipeline->shaders[stage])
2802 continue;
2803 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2804 if (loc->sgpr_idx == -1)
2805 continue;
2806 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2807 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2808
2809 }
2810 if (pipeline->gs_copy_shader) {
2811 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2812 if (loc->sgpr_idx != -1) {
2813 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2814 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2815 }
2816 }
2817 }
2818
2819 static void
2820 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2821 uint32_t vertex_count)
2822 {
2823 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2824 radeon_emit(cmd_buffer->cs, vertex_count);
2825 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2826 S_0287F0_USE_OPAQUE(0));
2827 }
2828
2829 void radv_CmdDraw(
2830 VkCommandBuffer commandBuffer,
2831 uint32_t vertexCount,
2832 uint32_t instanceCount,
2833 uint32_t firstVertex,
2834 uint32_t firstInstance)
2835 {
2836 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2837
2838 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2839
2840 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2841
2842 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2843 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2844 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2845 radeon_emit(cmd_buffer->cs, firstVertex);
2846 radeon_emit(cmd_buffer->cs, firstInstance);
2847 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2848 radeon_emit(cmd_buffer->cs, 0);
2849
2850 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2851 radeon_emit(cmd_buffer->cs, instanceCount);
2852
2853 if (!cmd_buffer->state.subpass->view_mask) {
2854 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2855 } else {
2856 unsigned i;
2857 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2858 radv_emit_view_index(cmd_buffer, i);
2859
2860 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2861 }
2862 }
2863
2864 assert(cmd_buffer->cs->cdw <= cdw_max);
2865
2866 radv_cmd_buffer_after_draw(cmd_buffer);
2867 }
2868
2869
2870 static void
2871 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2872 uint64_t index_va,
2873 uint32_t index_count)
2874 {
2875 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2876 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2877 radeon_emit(cmd_buffer->cs, index_va);
2878 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2879 radeon_emit(cmd_buffer->cs, index_count);
2880 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2881 }
2882
2883 void radv_CmdDrawIndexed(
2884 VkCommandBuffer commandBuffer,
2885 uint32_t indexCount,
2886 uint32_t instanceCount,
2887 uint32_t firstIndex,
2888 int32_t vertexOffset,
2889 uint32_t firstInstance)
2890 {
2891 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2892 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2893 uint64_t index_va;
2894
2895 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2896
2897 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2898
2899 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2900 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2901 2, cmd_buffer->state.index_type);
2902 } else {
2903 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2904 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2905 }
2906
2907 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2908 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2909 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2910 radeon_emit(cmd_buffer->cs, vertexOffset);
2911 radeon_emit(cmd_buffer->cs, firstInstance);
2912 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2913 radeon_emit(cmd_buffer->cs, 0);
2914
2915 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2916 radeon_emit(cmd_buffer->cs, instanceCount);
2917
2918 index_va = cmd_buffer->state.index_va;
2919 index_va += firstIndex * index_size;
2920 if (!cmd_buffer->state.subpass->view_mask) {
2921 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2922 } else {
2923 unsigned i;
2924 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2925 radv_emit_view_index(cmd_buffer, i);
2926
2927 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2928 }
2929 }
2930
2931 assert(cmd_buffer->cs->cdw <= cdw_max);
2932 radv_cmd_buffer_after_draw(cmd_buffer);
2933 }
2934
2935 static void
2936 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2937 bool indexed,
2938 uint32_t draw_count,
2939 uint64_t count_va,
2940 uint32_t stride)
2941 {
2942 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2943 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2944 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2945 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2946 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2947 assert(base_reg);
2948
2949 if (draw_count == 1 && !count_va && !draw_id_enable) {
2950 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2951 PKT3_DRAW_INDIRECT, 3, false));
2952 radeon_emit(cs, 0);
2953 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2954 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2955 radeon_emit(cs, di_src_sel);
2956 } else {
2957 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2958 PKT3_DRAW_INDIRECT_MULTI,
2959 8, false));
2960 radeon_emit(cs, 0);
2961 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2962 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2963 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2964 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2965 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2966 radeon_emit(cs, draw_count); /* count */
2967 radeon_emit(cs, count_va); /* count_addr */
2968 radeon_emit(cs, count_va >> 32);
2969 radeon_emit(cs, stride); /* stride */
2970 radeon_emit(cs, di_src_sel);
2971 }
2972 }
2973
2974 static void
2975 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2976 VkBuffer _buffer,
2977 VkDeviceSize offset,
2978 VkBuffer _count_buffer,
2979 VkDeviceSize count_offset,
2980 uint32_t draw_count,
2981 uint32_t stride,
2982 bool indexed)
2983 {
2984 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2985 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2986 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2987
2988 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
2989 indirect_va += offset + buffer->offset;
2990 uint64_t count_va = 0;
2991
2992 if (count_buffer) {
2993 count_va = radv_buffer_get_va(count_buffer->bo);
2994 count_va += count_offset + count_buffer->offset;
2995 }
2996
2997 if (!draw_count)
2998 return;
2999
3000 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3001
3002 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3003 radeon_emit(cs, 1);
3004 radeon_emit(cs, indirect_va);
3005 radeon_emit(cs, indirect_va >> 32);
3006
3007 if (!cmd_buffer->state.subpass->view_mask) {
3008 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3009 } else {
3010 unsigned i;
3011 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3012 radv_emit_view_index(cmd_buffer, i);
3013
3014 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3015 }
3016 }
3017 radv_cmd_buffer_after_draw(cmd_buffer);
3018 }
3019
3020 static void
3021 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3022 VkBuffer buffer,
3023 VkDeviceSize offset,
3024 VkBuffer countBuffer,
3025 VkDeviceSize countBufferOffset,
3026 uint32_t maxDrawCount,
3027 uint32_t stride)
3028 {
3029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3030 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3031
3032 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3033 cmd_buffer->cs, 24 * MAX_VIEWS);
3034
3035 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3036 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3037
3038 assert(cmd_buffer->cs->cdw <= cdw_max);
3039 }
3040
3041 static void
3042 radv_cmd_draw_indexed_indirect_count(
3043 VkCommandBuffer commandBuffer,
3044 VkBuffer buffer,
3045 VkDeviceSize offset,
3046 VkBuffer countBuffer,
3047 VkDeviceSize countBufferOffset,
3048 uint32_t maxDrawCount,
3049 uint32_t stride)
3050 {
3051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3052 uint64_t index_va;
3053 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3054
3055 index_va = cmd_buffer->state.index_va;
3056
3057 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3058
3059 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
3060 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
3061
3062 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
3063 radeon_emit(cmd_buffer->cs, index_va);
3064 radeon_emit(cmd_buffer->cs, index_va >> 32);
3065
3066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
3067 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3068
3069 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3070 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3071
3072 assert(cmd_buffer->cs->cdw <= cdw_max);
3073 }
3074
3075 void radv_CmdDrawIndirect(
3076 VkCommandBuffer commandBuffer,
3077 VkBuffer buffer,
3078 VkDeviceSize offset,
3079 uint32_t drawCount,
3080 uint32_t stride)
3081 {
3082 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3083 VK_NULL_HANDLE, 0, drawCount, stride);
3084 }
3085
3086 void radv_CmdDrawIndexedIndirect(
3087 VkCommandBuffer commandBuffer,
3088 VkBuffer buffer,
3089 VkDeviceSize offset,
3090 uint32_t drawCount,
3091 uint32_t stride)
3092 {
3093 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3094 VK_NULL_HANDLE, 0, drawCount, stride);
3095 }
3096
3097 void radv_CmdDrawIndirectCountAMD(
3098 VkCommandBuffer commandBuffer,
3099 VkBuffer buffer,
3100 VkDeviceSize offset,
3101 VkBuffer countBuffer,
3102 VkDeviceSize countBufferOffset,
3103 uint32_t maxDrawCount,
3104 uint32_t stride)
3105 {
3106 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3107 countBuffer, countBufferOffset,
3108 maxDrawCount, stride);
3109 }
3110
3111 void radv_CmdDrawIndexedIndirectCountAMD(
3112 VkCommandBuffer commandBuffer,
3113 VkBuffer buffer,
3114 VkDeviceSize offset,
3115 VkBuffer countBuffer,
3116 VkDeviceSize countBufferOffset,
3117 uint32_t maxDrawCount,
3118 uint32_t stride)
3119 {
3120 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3121 countBuffer, countBufferOffset,
3122 maxDrawCount, stride);
3123 }
3124
3125 struct radv_dispatch_info {
3126 /**
3127 * Determine the layout of the grid (in block units) to be used.
3128 */
3129 uint32_t blocks[3];
3130
3131 /**
3132 * Whether it's an unaligned compute dispatch.
3133 */
3134 bool unaligned;
3135
3136 /**
3137 * Indirect compute parameters resource.
3138 */
3139 struct radv_buffer *indirect;
3140 uint64_t indirect_offset;
3141 };
3142
3143 static void
3144 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3145 const struct radv_dispatch_info *info)
3146 {
3147 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3148 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3149 struct radeon_winsys *ws = cmd_buffer->device->ws;
3150 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3151 struct ac_userdata_info *loc;
3152 uint8_t grid_used;
3153
3154 grid_used = compute_shader->info.info.cs.grid_components_used;
3155
3156 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3157 AC_UD_CS_GRID_SIZE);
3158
3159 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3160
3161 if (info->indirect) {
3162 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3163
3164 va += info->indirect->offset + info->indirect_offset;
3165
3166 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3167
3168 if (loc->sgpr_idx != -1) {
3169 for (unsigned i = 0; i < grid_used; ++i) {
3170 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3171 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3172 COPY_DATA_DST_SEL(COPY_DATA_REG));
3173 radeon_emit(cs, (va + 4 * i));
3174 radeon_emit(cs, (va + 4 * i) >> 32);
3175 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3176 + loc->sgpr_idx * 4) >> 2) + i);
3177 radeon_emit(cs, 0);
3178 }
3179 }
3180
3181 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3182 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3183 PKT3_SHADER_TYPE_S(1));
3184 radeon_emit(cs, va);
3185 radeon_emit(cs, va >> 32);
3186 radeon_emit(cs, 1);
3187 } else {
3188 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3189 PKT3_SHADER_TYPE_S(1));
3190 radeon_emit(cs, 1);
3191 radeon_emit(cs, va);
3192 radeon_emit(cs, va >> 32);
3193
3194 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3195 PKT3_SHADER_TYPE_S(1));
3196 radeon_emit(cs, 0);
3197 radeon_emit(cs, 1);
3198 }
3199 } else {
3200 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3201 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3202 S_00B800_FORCE_START_AT_000(1);
3203
3204 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3205 /* If the KMD allows it (there is a KMD hw register for
3206 * it), allow launching waves out-of-order.
3207 */
3208 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3209 }
3210
3211 if (info->unaligned) {
3212 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3213 unsigned remainder[3];
3214
3215 /* If aligned, these should be an entire block size,
3216 * not 0.
3217 */
3218 remainder[0] = blocks[0] + cs_block_size[0] -
3219 align_u32_npot(blocks[0], cs_block_size[0]);
3220 remainder[1] = blocks[1] + cs_block_size[1] -
3221 align_u32_npot(blocks[1], cs_block_size[1]);
3222 remainder[2] = blocks[2] + cs_block_size[2] -
3223 align_u32_npot(blocks[2], cs_block_size[2]);
3224
3225 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3226 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3227 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3228
3229 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3230 radeon_emit(cs,
3231 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3232 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3233 radeon_emit(cs,
3234 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3235 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3236 radeon_emit(cs,
3237 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3238 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3239
3240 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3241 }
3242
3243 if (loc->sgpr_idx != -1) {
3244 assert(!loc->indirect);
3245 assert(loc->num_sgprs == grid_used);
3246
3247 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3248 loc->sgpr_idx * 4, grid_used);
3249 radeon_emit(cs, blocks[0]);
3250 if (grid_used > 1)
3251 radeon_emit(cs, blocks[1]);
3252 if (grid_used > 2)
3253 radeon_emit(cs, blocks[2]);
3254 }
3255
3256 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3257 PKT3_SHADER_TYPE_S(1));
3258 radeon_emit(cs, blocks[0]);
3259 radeon_emit(cs, blocks[1]);
3260 radeon_emit(cs, blocks[2]);
3261 radeon_emit(cs, dispatch_initiator);
3262 }
3263
3264 assert(cmd_buffer->cs->cdw <= cdw_max);
3265 }
3266
3267 static void
3268 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3269 const struct radv_dispatch_info *info)
3270 {
3271 radv_emit_compute_pipeline(cmd_buffer);
3272
3273 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3274 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3275 VK_SHADER_STAGE_COMPUTE_BIT);
3276
3277 si_emit_cache_flush(cmd_buffer);
3278
3279 radv_emit_dispatch_packets(cmd_buffer, info);
3280
3281 radv_cmd_buffer_after_draw(cmd_buffer);
3282 }
3283
3284 void radv_CmdDispatch(
3285 VkCommandBuffer commandBuffer,
3286 uint32_t x,
3287 uint32_t y,
3288 uint32_t z)
3289 {
3290 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3291 struct radv_dispatch_info info = {};
3292
3293 info.blocks[0] = x;
3294 info.blocks[1] = y;
3295 info.blocks[2] = z;
3296
3297 radv_dispatch(cmd_buffer, &info);
3298 }
3299
3300 void radv_CmdDispatchIndirect(
3301 VkCommandBuffer commandBuffer,
3302 VkBuffer _buffer,
3303 VkDeviceSize offset)
3304 {
3305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3306 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3307 struct radv_dispatch_info info = {};
3308
3309 info.indirect = buffer;
3310 info.indirect_offset = offset;
3311
3312 radv_dispatch(cmd_buffer, &info);
3313 }
3314
3315 void radv_unaligned_dispatch(
3316 struct radv_cmd_buffer *cmd_buffer,
3317 uint32_t x,
3318 uint32_t y,
3319 uint32_t z)
3320 {
3321 struct radv_dispatch_info info = {};
3322
3323 info.blocks[0] = x;
3324 info.blocks[1] = y;
3325 info.blocks[2] = z;
3326 info.unaligned = 1;
3327
3328 radv_dispatch(cmd_buffer, &info);
3329 }
3330
3331 void radv_CmdEndRenderPass(
3332 VkCommandBuffer commandBuffer)
3333 {
3334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3335
3336 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3337
3338 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3339
3340 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3341 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3342 radv_handle_subpass_image_transition(cmd_buffer,
3343 (VkAttachmentReference){i, layout});
3344 }
3345
3346 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3347
3348 cmd_buffer->state.pass = NULL;
3349 cmd_buffer->state.subpass = NULL;
3350 cmd_buffer->state.attachments = NULL;
3351 cmd_buffer->state.framebuffer = NULL;
3352 }
3353
3354 /*
3355 * For HTILE we have the following interesting clear words:
3356 * 0x0000030f: Uncompressed.
3357 * 0xfffffff0: Clear depth to 1.0
3358 * 0x00000000: Clear depth to 0.0
3359 */
3360 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3361 struct radv_image *image,
3362 const VkImageSubresourceRange *range,
3363 uint32_t clear_word)
3364 {
3365 assert(range->baseMipLevel == 0);
3366 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3367 unsigned layer_count = radv_get_layerCount(image, range);
3368 uint64_t size = image->surface.htile_slice_size * layer_count;
3369 uint64_t offset = image->offset + image->htile_offset +
3370 image->surface.htile_slice_size * range->baseArrayLayer;
3371
3372 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3373 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3374
3375 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3376
3377 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3378 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3379 RADV_CMD_FLAG_INV_VMEM_L1 |
3380 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3381 }
3382
3383 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3384 struct radv_image *image,
3385 VkImageLayout src_layout,
3386 VkImageLayout dst_layout,
3387 unsigned src_queue_mask,
3388 unsigned dst_queue_mask,
3389 const VkImageSubresourceRange *range,
3390 VkImageAspectFlags pending_clears)
3391 {
3392 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3393 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3394 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3395 cmd_buffer->state.render_area.extent.width == image->info.width &&
3396 cmd_buffer->state.render_area.extent.height == image->info.height) {
3397 /* The clear will initialize htile. */
3398 return;
3399 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3400 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3401 /* TODO: merge with the clear if applicable */
3402 radv_initialize_htile(cmd_buffer, image, range, 0);
3403 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3404 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3405 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3406 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3407 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3408 VkImageSubresourceRange local_range = *range;
3409 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3410 local_range.baseMipLevel = 0;
3411 local_range.levelCount = 1;
3412
3413 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3414 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3415
3416 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3417
3418 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3419 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3420 }
3421 }
3422
3423 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3424 struct radv_image *image, uint32_t value)
3425 {
3426 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3427 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3428
3429 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3430 image->cmask.size, value);
3431
3432 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3433 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3434 RADV_CMD_FLAG_INV_VMEM_L1 |
3435 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3436 }
3437
3438 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3439 struct radv_image *image,
3440 VkImageLayout src_layout,
3441 VkImageLayout dst_layout,
3442 unsigned src_queue_mask,
3443 unsigned dst_queue_mask,
3444 const VkImageSubresourceRange *range)
3445 {
3446 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3447 if (image->fmask.size)
3448 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3449 else
3450 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3451 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3452 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3453 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3454 }
3455 }
3456
3457 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3458 struct radv_image *image, uint32_t value)
3459 {
3460
3461 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3462 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3463
3464 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3465 image->surface.dcc_size, value);
3466
3467 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3468 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3469 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3470 RADV_CMD_FLAG_INV_VMEM_L1 |
3471 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3472 }
3473
3474 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3475 struct radv_image *image,
3476 VkImageLayout src_layout,
3477 VkImageLayout dst_layout,
3478 unsigned src_queue_mask,
3479 unsigned dst_queue_mask,
3480 const VkImageSubresourceRange *range)
3481 {
3482 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3483 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3484 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3485 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3486 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3487 }
3488 }
3489
3490 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3491 struct radv_image *image,
3492 VkImageLayout src_layout,
3493 VkImageLayout dst_layout,
3494 uint32_t src_family,
3495 uint32_t dst_family,
3496 const VkImageSubresourceRange *range,
3497 VkImageAspectFlags pending_clears)
3498 {
3499 if (image->exclusive && src_family != dst_family) {
3500 /* This is an acquire or a release operation and there will be
3501 * a corresponding release/acquire. Do the transition in the
3502 * most flexible queue. */
3503
3504 assert(src_family == cmd_buffer->queue_family_index ||
3505 dst_family == cmd_buffer->queue_family_index);
3506
3507 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3508 return;
3509
3510 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3511 (src_family == RADV_QUEUE_GENERAL ||
3512 dst_family == RADV_QUEUE_GENERAL))
3513 return;
3514 }
3515
3516 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3517 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3518
3519 if (image->surface.htile_size)
3520 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3521 dst_layout, src_queue_mask,
3522 dst_queue_mask, range,
3523 pending_clears);
3524
3525 if (image->cmask.size)
3526 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3527 dst_layout, src_queue_mask,
3528 dst_queue_mask, range);
3529
3530 if (image->surface.dcc_size)
3531 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3532 dst_layout, src_queue_mask,
3533 dst_queue_mask, range);
3534 }
3535
3536 void radv_CmdPipelineBarrier(
3537 VkCommandBuffer commandBuffer,
3538 VkPipelineStageFlags srcStageMask,
3539 VkPipelineStageFlags destStageMask,
3540 VkBool32 byRegion,
3541 uint32_t memoryBarrierCount,
3542 const VkMemoryBarrier* pMemoryBarriers,
3543 uint32_t bufferMemoryBarrierCount,
3544 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3545 uint32_t imageMemoryBarrierCount,
3546 const VkImageMemoryBarrier* pImageMemoryBarriers)
3547 {
3548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3549 enum radv_cmd_flush_bits src_flush_bits = 0;
3550 enum radv_cmd_flush_bits dst_flush_bits = 0;
3551
3552 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3553 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3554 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3555 NULL);
3556 }
3557
3558 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3559 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3560 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3561 NULL);
3562 }
3563
3564 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3565 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3566 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3567 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3568 image);
3569 }
3570
3571 radv_stage_flush(cmd_buffer, srcStageMask);
3572 cmd_buffer->state.flush_bits |= src_flush_bits;
3573
3574 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3575 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3576 radv_handle_image_transition(cmd_buffer, image,
3577 pImageMemoryBarriers[i].oldLayout,
3578 pImageMemoryBarriers[i].newLayout,
3579 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3580 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3581 &pImageMemoryBarriers[i].subresourceRange,
3582 0);
3583 }
3584
3585 cmd_buffer->state.flush_bits |= dst_flush_bits;
3586 }
3587
3588
3589 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3590 struct radv_event *event,
3591 VkPipelineStageFlags stageMask,
3592 unsigned value)
3593 {
3594 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3595 uint64_t va = radv_buffer_get_va(event->bo);
3596
3597 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3598
3599 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3600
3601 /* TODO: this is overkill. Probably should figure something out from
3602 * the stage mask. */
3603
3604 si_cs_emit_write_event_eop(cs,
3605 cmd_buffer->state.predicating,
3606 cmd_buffer->device->physical_device->rad_info.chip_class,
3607 false,
3608 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3609 1, va, 2, value);
3610
3611 assert(cmd_buffer->cs->cdw <= cdw_max);
3612 }
3613
3614 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3615 VkEvent _event,
3616 VkPipelineStageFlags stageMask)
3617 {
3618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3619 RADV_FROM_HANDLE(radv_event, event, _event);
3620
3621 write_event(cmd_buffer, event, stageMask, 1);
3622 }
3623
3624 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3625 VkEvent _event,
3626 VkPipelineStageFlags stageMask)
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 RADV_FROM_HANDLE(radv_event, event, _event);
3630
3631 write_event(cmd_buffer, event, stageMask, 0);
3632 }
3633
3634 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3635 uint32_t eventCount,
3636 const VkEvent* pEvents,
3637 VkPipelineStageFlags srcStageMask,
3638 VkPipelineStageFlags dstStageMask,
3639 uint32_t memoryBarrierCount,
3640 const VkMemoryBarrier* pMemoryBarriers,
3641 uint32_t bufferMemoryBarrierCount,
3642 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3643 uint32_t imageMemoryBarrierCount,
3644 const VkImageMemoryBarrier* pImageMemoryBarriers)
3645 {
3646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3647 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3648
3649 for (unsigned i = 0; i < eventCount; ++i) {
3650 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3651 uint64_t va = radv_buffer_get_va(event->bo);
3652
3653 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3654
3655 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3656
3657 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3658 assert(cmd_buffer->cs->cdw <= cdw_max);
3659 }
3660
3661
3662 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3663 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3664
3665 radv_handle_image_transition(cmd_buffer, image,
3666 pImageMemoryBarriers[i].oldLayout,
3667 pImageMemoryBarriers[i].newLayout,
3668 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3669 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3670 &pImageMemoryBarriers[i].subresourceRange,
3671 0);
3672 }
3673
3674 /* TODO: figure out how to do memory barriers without waiting */
3675 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3676 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3677 RADV_CMD_FLAG_INV_VMEM_L1 |
3678 RADV_CMD_FLAG_INV_SMEM_L1;
3679 }