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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
597 old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
598 return;
599
600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
602 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
603
604 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
605
606 /* GFX9: Flush DFSM when the AA mode changes. */
607 if (cmd_buffer->device->dfsm_allowed) {
608 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
609 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
610 }
611 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
612 uint32_t offset;
613 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
614 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
615 if (loc->sgpr_idx == -1)
616 return;
617 assert(loc->num_sgprs == 1);
618 assert(!loc->indirect);
619 switch (num_samples) {
620 default:
621 offset = 0;
622 break;
623 case 2:
624 offset = 1;
625 break;
626 case 4:
627 offset = 3;
628 break;
629 case 8:
630 offset = 7;
631 break;
632 case 16:
633 offset = 15;
634 break;
635 }
636
637 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
638 cmd_buffer->sample_positions_needed = true;
639 }
640 }
641
642 static void
643 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 struct radv_raster_state *raster = &pipeline->graphics.raster;
647
648 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
649 raster->pa_cl_clip_cntl);
650 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
651 raster->spi_interp_control);
652 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
653 raster->pa_su_vtx_cntl);
654 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
655 raster->pa_su_sc_mode_cntl);
656 }
657
658 static inline void
659 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
660 unsigned size)
661 {
662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
663 si_cp_dma_prefetch(cmd_buffer, va, size);
664 }
665
666 static void
667 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
668 {
669 if (cmd_buffer->state.vb_prefetch_dirty) {
670 radv_emit_prefetch_TC_L2_async(cmd_buffer,
671 cmd_buffer->state.vb_va,
672 cmd_buffer->state.vb_size);
673 cmd_buffer->state.vb_prefetch_dirty = false;
674 }
675 }
676
677 static void
678 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
679 struct radv_shader_variant *shader)
680 {
681 struct radeon_winsys *ws = cmd_buffer->device->ws;
682 struct radeon_winsys_cs *cs = cmd_buffer->cs;
683 uint64_t va;
684
685 if (!shader)
686 return;
687
688 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
689
690 radv_cs_add_buffer(ws, cs, shader->bo, 8);
691 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
692 }
693
694 static void
695 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
696 struct radv_pipeline *pipeline)
697 {
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_GEOMETRY]);
707 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_FRAGMENT]);
710 }
711
712 static void
713 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
714 struct radv_pipeline *pipeline,
715 struct radv_shader_variant *shader)
716 {
717 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
720 pipeline->graphics.vs.spi_vs_out_config);
721
722 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
723 pipeline->graphics.vs.spi_shader_pos_format);
724
725 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
726 radeon_emit(cmd_buffer->cs, va >> 8);
727 radeon_emit(cmd_buffer->cs, va >> 40);
728 radeon_emit(cmd_buffer->cs, shader->rsrc1);
729 radeon_emit(cmd_buffer->cs, shader->rsrc2);
730
731 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
732 S_028818_VTX_W0_FMT(1) |
733 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
734 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
735 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
736
737
738 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
739 pipeline->graphics.vs.pa_cl_vs_out_cntl);
740
741 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
742 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
743 pipeline->graphics.vs.vgt_reuse_off);
744 }
745
746 static void
747 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_pipeline *pipeline,
749 struct radv_shader_variant *shader)
750 {
751 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
752
753 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
754 radeon_emit(cmd_buffer->cs, va >> 8);
755 radeon_emit(cmd_buffer->cs, va >> 40);
756 radeon_emit(cmd_buffer->cs, shader->rsrc1);
757 radeon_emit(cmd_buffer->cs, shader->rsrc2);
758 }
759
760 static void
761 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
762 struct radv_shader_variant *shader)
763 {
764 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
765 uint32_t rsrc2 = shader->rsrc2;
766
767 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
768 radeon_emit(cmd_buffer->cs, va >> 8);
769 radeon_emit(cmd_buffer->cs, va >> 40);
770
771 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
772 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
773 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
774 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
775
776 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
777 radeon_emit(cmd_buffer->cs, shader->rsrc1);
778 radeon_emit(cmd_buffer->cs, rsrc2);
779 }
780
781 static void
782 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
783 struct radv_shader_variant *shader)
784 {
785 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
786
787 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791
792 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
793 radeon_emit(cmd_buffer->cs, shader->rsrc1);
794 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
795 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
796 } else {
797 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
798 radeon_emit(cmd_buffer->cs, va >> 8);
799 radeon_emit(cmd_buffer->cs, va >> 40);
800 radeon_emit(cmd_buffer->cs, shader->rsrc1);
801 radeon_emit(cmd_buffer->cs, shader->rsrc2);
802 }
803 }
804
805 static void
806 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
807 struct radv_pipeline *pipeline)
808 {
809 struct radv_shader_variant *vs;
810
811 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
812
813 /* Skip shaders merged into HS/GS */
814 vs = pipeline->shaders[MESA_SHADER_VERTEX];
815 if (!vs)
816 return;
817
818 if (vs->info.vs.as_ls)
819 radv_emit_hw_ls(cmd_buffer, vs);
820 else if (vs->info.vs.as_es)
821 radv_emit_hw_es(cmd_buffer, pipeline, vs);
822 else
823 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
824 }
825
826
827 static void
828 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
829 struct radv_pipeline *pipeline)
830 {
831 if (!radv_pipeline_has_tess(pipeline))
832 return;
833
834 struct radv_shader_variant *tes, *tcs;
835
836 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
837 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
838
839 if (tes) {
840 if (tes->info.tes.as_es)
841 radv_emit_hw_es(cmd_buffer, pipeline, tes);
842 else
843 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
844 }
845
846 radv_emit_hw_hs(cmd_buffer, tcs);
847
848 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
849 pipeline->graphics.tess.tf_param);
850
851 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
852 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
853 pipeline->graphics.tess.ls_hs_config);
854 else
855 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
856 pipeline->graphics.tess.ls_hs_config);
857
858 struct ac_userdata_info *loc;
859
860 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
861 if (loc->sgpr_idx != -1) {
862 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
863 assert(loc->num_sgprs == 4);
864 assert(!loc->indirect);
865 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
868 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
869 pipeline->graphics.tess.num_tcs_input_cp << 26);
870 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
871 }
872
873 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
874 if (loc->sgpr_idx != -1) {
875 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
876 assert(loc->num_sgprs == 1);
877 assert(!loc->indirect);
878
879 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
880 pipeline->graphics.tess.offchip_layout);
881 }
882
883 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
884 if (loc->sgpr_idx != -1) {
885 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
886 assert(loc->num_sgprs == 1);
887 assert(!loc->indirect);
888
889 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
890 pipeline->graphics.tess.tcs_in_layout);
891 }
892 }
893
894 static void
895 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
896 struct radv_pipeline *pipeline)
897 {
898 struct radv_shader_variant *gs;
899 uint64_t va;
900
901 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
902
903 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
904 if (!gs)
905 return;
906
907 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
908
909 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
917
918 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
920 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923 radeon_emit(cmd_buffer->cs, 0);
924
925 uint32_t gs_num_invocations = gs->info.gs.invocations;
926 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
927 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
928 S_028B90_ENABLE(gs_num_invocations > 0));
929
930 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
931 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
932
933 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
934
935 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
936 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
937 radeon_emit(cmd_buffer->cs, va >> 8);
938 radeon_emit(cmd_buffer->cs, va >> 40);
939
940 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
941 radeon_emit(cmd_buffer->cs, gs->rsrc1);
942 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
943 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
944
945 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
946 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
947 } else {
948 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
949 radeon_emit(cmd_buffer->cs, va >> 8);
950 radeon_emit(cmd_buffer->cs, va >> 40);
951 radeon_emit(cmd_buffer->cs, gs->rsrc1);
952 radeon_emit(cmd_buffer->cs, gs->rsrc2);
953 }
954
955 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
956
957 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
958 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
959 if (loc->sgpr_idx != -1) {
960 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
961 uint32_t num_entries = 64;
962 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
963
964 if (is_vi)
965 num_entries *= stride;
966
967 stride = S_008F04_STRIDE(stride);
968 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
969 radeon_emit(cmd_buffer->cs, stride);
970 radeon_emit(cmd_buffer->cs, num_entries);
971 }
972 }
973
974 static void
975 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
976 struct radv_pipeline *pipeline)
977 {
978 struct radv_shader_variant *ps;
979 uint64_t va;
980 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
981 struct radv_blend_state *blend = &pipeline->graphics.blend;
982 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
983
984 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
985 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
986
987 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
988 radeon_emit(cmd_buffer->cs, va >> 8);
989 radeon_emit(cmd_buffer->cs, va >> 40);
990 radeon_emit(cmd_buffer->cs, ps->rsrc1);
991 radeon_emit(cmd_buffer->cs, ps->rsrc2);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
994 pipeline->graphics.db_shader_control);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
997 ps->config.spi_ps_input_ena);
998
999 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1000 ps->config.spi_ps_input_addr);
1001
1002 if (ps->info.info.ps.force_persample)
1003 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1006 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1011 pipeline->graphics.shader_z_format);
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1014
1015 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1016 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1017
1018 if (cmd_buffer->device->dfsm_allowed) {
1019 /* optimise this? */
1020 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1021 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1022 }
1023
1024 if (pipeline->graphics.ps_input_cntl_num) {
1025 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1026 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1027 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1028 }
1029 }
1030 }
1031
1032 static void
1033 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1034 struct radv_pipeline *pipeline)
1035 {
1036 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1037
1038 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1039 return;
1040
1041 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1042 pipeline->graphics.vtx_reuse_depth);
1043 }
1044
1045 static void
1046 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1047 {
1048 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1049
1050 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1051 return;
1052
1053 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1054 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1055 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1056 radv_update_multisample_state(cmd_buffer, pipeline);
1057 radv_emit_vertex_shader(cmd_buffer, pipeline);
1058 radv_emit_tess_shaders(cmd_buffer, pipeline);
1059 radv_emit_geometry_shader(cmd_buffer, pipeline);
1060 radv_emit_fragment_shader(cmd_buffer, pipeline);
1061 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1062
1063 cmd_buffer->scratch_size_needed =
1064 MAX2(cmd_buffer->scratch_size_needed,
1065 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1066
1067 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1068 S_0286E8_WAVES(pipeline->max_waves) |
1069 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1070
1071 if (!cmd_buffer->state.emitted_pipeline ||
1072 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1073 pipeline->graphics.can_use_guardband)
1074 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1075
1076 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1077
1078 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1079 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1080 } else {
1081 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1082 }
1083 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1084
1085 if (unlikely(cmd_buffer->device->trace_bo))
1086 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1087
1088 cmd_buffer->state.emitted_pipeline = pipeline;
1089
1090 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1091 }
1092
1093 static void
1094 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1095 {
1096 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1097 cmd_buffer->state.dynamic.viewport.viewports);
1098 }
1099
1100 static void
1101 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1102 {
1103 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1104
1105 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1106 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1107 si_emit_cache_flush(cmd_buffer);
1108 }
1109 si_write_scissors(cmd_buffer->cs, 0, count,
1110 cmd_buffer->state.dynamic.scissor.scissors,
1111 cmd_buffer->state.dynamic.viewport.viewports,
1112 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1113 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1114 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1115 }
1116
1117 static void
1118 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1119 {
1120 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1121
1122 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1123 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1124 }
1125
1126 static void
1127 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1128 {
1129 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1130
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1132 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1133 }
1134
1135 static void
1136 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1137 {
1138 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1139
1140 radeon_set_context_reg_seq(cmd_buffer->cs,
1141 R_028430_DB_STENCILREFMASK, 2);
1142 radeon_emit(cmd_buffer->cs,
1143 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1144 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1145 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1146 S_028430_STENCILOPVAL(1));
1147 radeon_emit(cmd_buffer->cs,
1148 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1149 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1150 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1151 S_028434_STENCILOPVAL_BF(1));
1152 }
1153
1154 static void
1155 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1156 {
1157 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1158
1159 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1160 fui(d->depth_bounds.min));
1161 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1162 fui(d->depth_bounds.max));
1163 }
1164
1165 static void
1166 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1167 {
1168 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1169 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1170 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1171 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1172
1173 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1174 radeon_set_context_reg_seq(cmd_buffer->cs,
1175 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1176 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1177 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1178 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1179 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1180 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1181 }
1182 }
1183
1184 static void
1185 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1186 int index,
1187 struct radv_attachment_info *att)
1188 {
1189 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1190 struct radv_color_buffer_info *cb = &att->cb;
1191
1192 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1193 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1196 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1200 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1204 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1207 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1208 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1209
1210 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1211 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1212 } else {
1213 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1216 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1219 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1220 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1223 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1224 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1225
1226 if (is_vi) { /* DCC BASE */
1227 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1228 }
1229 }
1230 }
1231
1232 static void
1233 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1234 struct radv_ds_buffer_info *ds,
1235 struct radv_image *image,
1236 VkImageLayout layout)
1237 {
1238 uint32_t db_z_info = ds->db_z_info;
1239 uint32_t db_stencil_info = ds->db_stencil_info;
1240
1241 if (!radv_layout_has_htile(image, layout,
1242 radv_image_queue_family_mask(image,
1243 cmd_buffer->queue_family_index,
1244 cmd_buffer->queue_family_index))) {
1245 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1246 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1247 }
1248
1249 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1250 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1251
1252
1253 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1254 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1255 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1256 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1257 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1258
1259 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1260 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1261 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1263 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1265 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1266 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1267 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1269 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1270
1271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1272 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1273 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1274 } else {
1275 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1276
1277 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1278 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1279 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1280 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1281 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1282 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1283 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1284 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1285 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1286 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1287
1288 }
1289
1290 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1291 ds->pa_su_poly_offset_db_fmt_cntl);
1292 }
1293
1294 void
1295 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1296 struct radv_image *image,
1297 VkClearDepthStencilValue ds_clear_value,
1298 VkImageAspectFlags aspects)
1299 {
1300 uint64_t va = radv_buffer_get_va(image->bo);
1301 va += image->offset + image->clear_value_offset;
1302 unsigned reg_offset = 0, reg_count = 0;
1303
1304 assert(image->surface.htile_size);
1305
1306 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1307 ++reg_count;
1308 } else {
1309 ++reg_offset;
1310 va += 4;
1311 }
1312 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1313 ++reg_count;
1314
1315 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1316 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1317 S_370_WR_CONFIRM(1) |
1318 S_370_ENGINE_SEL(V_370_PFP));
1319 radeon_emit(cmd_buffer->cs, va);
1320 radeon_emit(cmd_buffer->cs, va >> 32);
1321 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1322 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1323 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1324 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1325
1326 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1327 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1328 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1329 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1330 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1331 }
1332
1333 static void
1334 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1335 struct radv_image *image)
1336 {
1337 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1338 uint64_t va = radv_buffer_get_va(image->bo);
1339 va += image->offset + image->clear_value_offset;
1340 unsigned reg_offset = 0, reg_count = 0;
1341
1342 if (!image->surface.htile_size)
1343 return;
1344
1345 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1346 ++reg_count;
1347 } else {
1348 ++reg_offset;
1349 va += 4;
1350 }
1351 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1352 ++reg_count;
1353
1354 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1355 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1356 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1357 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1358 radeon_emit(cmd_buffer->cs, va);
1359 radeon_emit(cmd_buffer->cs, va >> 32);
1360 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1361 radeon_emit(cmd_buffer->cs, 0);
1362
1363 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1364 radeon_emit(cmd_buffer->cs, 0);
1365 }
1366
1367 /*
1368 *with DCC some colors don't require CMASK elimiation before being
1369 * used as a texture. This sets a predicate value to determine if the
1370 * cmask eliminate is required.
1371 */
1372 void
1373 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 bool value)
1376 {
1377 uint64_t pred_val = value;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379 va += image->offset + image->dcc_pred_offset;
1380
1381 assert(image->surface.dcc_size);
1382
1383 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1384 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1385 S_370_WR_CONFIRM(1) |
1386 S_370_ENGINE_SEL(V_370_PFP));
1387 radeon_emit(cmd_buffer->cs, va);
1388 radeon_emit(cmd_buffer->cs, va >> 32);
1389 radeon_emit(cmd_buffer->cs, pred_val);
1390 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1391 }
1392
1393 void
1394 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1395 struct radv_image *image,
1396 int idx,
1397 uint32_t color_values[2])
1398 {
1399 uint64_t va = radv_buffer_get_va(image->bo);
1400 va += image->offset + image->clear_value_offset;
1401
1402 assert(image->cmask.size || image->surface.dcc_size);
1403
1404 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1405 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1406 S_370_WR_CONFIRM(1) |
1407 S_370_ENGINE_SEL(V_370_PFP));
1408 radeon_emit(cmd_buffer->cs, va);
1409 radeon_emit(cmd_buffer->cs, va >> 32);
1410 radeon_emit(cmd_buffer->cs, color_values[0]);
1411 radeon_emit(cmd_buffer->cs, color_values[1]);
1412
1413 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1414 radeon_emit(cmd_buffer->cs, color_values[0]);
1415 radeon_emit(cmd_buffer->cs, color_values[1]);
1416 }
1417
1418 static void
1419 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1420 struct radv_image *image,
1421 int idx)
1422 {
1423 uint64_t va = radv_buffer_get_va(image->bo);
1424 va += image->offset + image->clear_value_offset;
1425
1426 if (!image->cmask.size && !image->surface.dcc_size)
1427 return;
1428
1429 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1430
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1432 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1433 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1434 COPY_DATA_COUNT_SEL);
1435 radeon_emit(cmd_buffer->cs, va);
1436 radeon_emit(cmd_buffer->cs, va >> 32);
1437 radeon_emit(cmd_buffer->cs, reg >> 2);
1438 radeon_emit(cmd_buffer->cs, 0);
1439
1440 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1441 radeon_emit(cmd_buffer->cs, 0);
1442 }
1443
1444 static void
1445 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1446 {
1447 int i;
1448 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1449 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1450
1451 /* this may happen for inherited secondary recording */
1452 if (!framebuffer)
1453 return;
1454
1455 for (i = 0; i < 8; ++i) {
1456 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1457 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1458 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1459 continue;
1460 }
1461
1462 int idx = subpass->color_attachments[i].attachment;
1463 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att);
1469
1470 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_depth_clear_regs(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 uint32_t db_count_control;
1545
1546 if(!cmd_buffer->state.active_occlusion_queries) {
1547 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1548 db_count_control = 0;
1549 } else {
1550 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1551 }
1552 } else {
1553 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1554 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1555 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1556 S_028004_ZPASS_ENABLE(1) |
1557 S_028004_SLICE_EVEN_ENABLE(1) |
1558 S_028004_SLICE_ODD_ENABLE(1);
1559 } else {
1560 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1561 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1562 }
1563 }
1564
1565 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1566 }
1567
1568 static void
1569 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1570 {
1571 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1572 return;
1573
1574 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1575 radv_emit_viewport(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1578 radv_emit_scissor(cmd_buffer);
1579
1580 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1581 radv_emit_line_width(cmd_buffer);
1582
1583 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1584 radv_emit_blend_constants(cmd_buffer);
1585
1586 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1587 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1588 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1589 radv_emit_stencil(cmd_buffer);
1590
1591 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1592 radv_emit_depth_bounds(cmd_buffer);
1593
1594 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1595 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1596 radv_emit_depth_biais(cmd_buffer);
1597
1598 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1599 }
1600
1601 static void
1602 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1603 struct radv_pipeline *pipeline,
1604 int idx,
1605 uint64_t va,
1606 gl_shader_stage stage)
1607 {
1608 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1609 uint32_t base_reg = pipeline->user_data_0[stage];
1610
1611 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1612 return;
1613
1614 assert(!desc_set_loc->indirect);
1615 assert(desc_set_loc->num_sgprs == 2);
1616 radeon_set_sh_reg_seq(cmd_buffer->cs,
1617 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1618 radeon_emit(cmd_buffer->cs, va);
1619 radeon_emit(cmd_buffer->cs, va >> 32);
1620 }
1621
1622 static void
1623 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1624 VkShaderStageFlags stages,
1625 struct radv_descriptor_set *set,
1626 unsigned idx)
1627 {
1628 if (cmd_buffer->state.pipeline) {
1629 radv_foreach_stage(stage, stages) {
1630 if (cmd_buffer->state.pipeline->shaders[stage])
1631 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1632 idx, set->va,
1633 stage);
1634 }
1635 }
1636
1637 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1638 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1639 idx, set->va,
1640 MESA_SHADER_COMPUTE);
1641 }
1642
1643 static void
1644 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1645 {
1646 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1647 unsigned bo_offset;
1648
1649 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1650 set->mapped_ptr,
1651 &bo_offset))
1652 return;
1653
1654 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1655 set->va += bo_offset;
1656 }
1657
1658 static void
1659 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1660 {
1661 uint32_t size = MAX_SETS * 2 * 4;
1662 uint32_t offset;
1663 void *ptr;
1664
1665 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1666 256, &offset, &ptr))
1667 return;
1668
1669 for (unsigned i = 0; i < MAX_SETS; i++) {
1670 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1671 uint64_t set_va = 0;
1672 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1673 if (cmd_buffer->state.valid_descriptors & (1u << i))
1674 set_va = set->va;
1675 uptr[0] = set_va & 0xffffffff;
1676 uptr[1] = set_va >> 32;
1677 }
1678
1679 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1680 va += offset;
1681
1682 if (cmd_buffer->state.pipeline) {
1683 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1684 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1685 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1686
1687 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1688 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1689 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1690
1691 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1692 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1693 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1694
1695 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1696 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1697 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1698
1699 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1700 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1701 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1702 }
1703
1704 if (cmd_buffer->state.compute_pipeline)
1705 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1706 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1707 }
1708
1709 static void
1710 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1711 VkShaderStageFlags stages)
1712 {
1713 unsigned i;
1714
1715 if (!cmd_buffer->state.descriptors_dirty)
1716 return;
1717
1718 if (cmd_buffer->state.push_descriptors_dirty)
1719 radv_flush_push_descriptors(cmd_buffer);
1720
1721 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1722 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1723 radv_flush_indirect_descriptor_sets(cmd_buffer);
1724 }
1725
1726 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1727 cmd_buffer->cs,
1728 MAX_SETS * MESA_SHADER_STAGES * 4);
1729
1730 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1731 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1732 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1733 continue;
1734
1735 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1736 }
1737 cmd_buffer->state.descriptors_dirty = 0;
1738 cmd_buffer->state.push_descriptors_dirty = false;
1739
1740 if (unlikely(cmd_buffer->device->trace_bo))
1741 radv_save_descriptors(cmd_buffer);
1742
1743 assert(cmd_buffer->cs->cdw <= cdw_max);
1744 }
1745
1746 static void
1747 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1748 struct radv_pipeline *pipeline,
1749 VkShaderStageFlags stages)
1750 {
1751 struct radv_pipeline_layout *layout = pipeline->layout;
1752 unsigned offset;
1753 void *ptr;
1754 uint64_t va;
1755
1756 stages &= cmd_buffer->push_constant_stages;
1757 if (!stages ||
1758 (!layout->push_constant_size && !layout->dynamic_offset_count))
1759 return;
1760
1761 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1762 16 * layout->dynamic_offset_count,
1763 256, &offset, &ptr))
1764 return;
1765
1766 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1767 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1768 16 * layout->dynamic_offset_count);
1769
1770 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1771 va += offset;
1772
1773 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1774 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1775
1776 radv_foreach_stage(stage, stages) {
1777 if (pipeline->shaders[stage]) {
1778 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1779 AC_UD_PUSH_CONSTANTS, va);
1780 }
1781 }
1782
1783 cmd_buffer->push_constant_stages &= ~stages;
1784 assert(cmd_buffer->cs->cdw <= cdw_max);
1785 }
1786
1787 static bool
1788 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1789 {
1790 if ((pipeline_is_dirty ||
1791 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1792 cmd_buffer->state.pipeline->vertex_elements.count &&
1793 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1794 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1795 unsigned vb_offset;
1796 void *vb_ptr;
1797 uint32_t i = 0;
1798 uint32_t count = velems->count;
1799 uint64_t va;
1800
1801 /* allocate some descriptor state for vertex buffers */
1802 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1803 &vb_offset, &vb_ptr))
1804 return false;
1805
1806 for (i = 0; i < count; i++) {
1807 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1808 uint32_t offset;
1809 int vb = velems->binding[i];
1810 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1811 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1812
1813 va = radv_buffer_get_va(buffer->bo);
1814
1815 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1816 va += offset + buffer->offset;
1817 desc[0] = va;
1818 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1819 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1820 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1821 else
1822 desc[2] = buffer->size - offset;
1823 desc[3] = velems->rsrc_word3[i];
1824 }
1825
1826 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1827 va += vb_offset;
1828
1829 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1830 AC_UD_VS_VERTEX_BUFFERS, va);
1831
1832 cmd_buffer->state.vb_va = va;
1833 cmd_buffer->state.vb_size = count * 16;
1834 cmd_buffer->state.vb_prefetch_dirty = true;
1835 }
1836 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1837
1838 return true;
1839 }
1840
1841 static bool
1842 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1843 {
1844 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1845 return false;
1846
1847 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1848 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1849 VK_SHADER_STAGE_ALL_GRAPHICS);
1850
1851 return true;
1852 }
1853
1854 static void
1855 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1856 bool instanced_draw, bool indirect_draw,
1857 uint32_t draw_vertex_count)
1858 {
1859 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1860 struct radv_cmd_state *state = &cmd_buffer->state;
1861 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1862 uint32_t ia_multi_vgt_param;
1863 int32_t primitive_reset_en;
1864
1865 /* Draw state. */
1866 ia_multi_vgt_param =
1867 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1868 indirect_draw, draw_vertex_count);
1869
1870 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1871 if (info->chip_class >= GFX9) {
1872 radeon_set_uconfig_reg_idx(cs,
1873 R_030960_IA_MULTI_VGT_PARAM,
1874 4, ia_multi_vgt_param);
1875 } else if (info->chip_class >= CIK) {
1876 radeon_set_context_reg_idx(cs,
1877 R_028AA8_IA_MULTI_VGT_PARAM,
1878 1, ia_multi_vgt_param);
1879 } else {
1880 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1881 ia_multi_vgt_param);
1882 }
1883 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1884 }
1885
1886 /* Primitive restart. */
1887 primitive_reset_en =
1888 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1889
1890 if (primitive_reset_en != state->last_primitive_reset_en) {
1891 state->last_primitive_reset_en = primitive_reset_en;
1892 if (info->chip_class >= GFX9) {
1893 radeon_set_uconfig_reg(cs,
1894 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1895 primitive_reset_en);
1896 } else {
1897 radeon_set_context_reg(cs,
1898 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1899 primitive_reset_en);
1900 }
1901 }
1902
1903 if (primitive_reset_en) {
1904 uint32_t primitive_reset_index =
1905 state->index_type ? 0xffffffffu : 0xffffu;
1906
1907 if (primitive_reset_index != state->last_primitive_reset_index) {
1908 radeon_set_context_reg(cs,
1909 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1910 primitive_reset_index);
1911 state->last_primitive_reset_index = primitive_reset_index;
1912 }
1913 }
1914 }
1915
1916 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1917 VkPipelineStageFlags src_stage_mask)
1918 {
1919 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1920 VK_PIPELINE_STAGE_TRANSFER_BIT |
1921 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1922 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1924 }
1925
1926 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1927 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1928 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1929 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1930 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1931 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1932 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1933 VK_PIPELINE_STAGE_TRANSFER_BIT |
1934 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1935 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1936 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1937 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1938 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1939 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1940 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1941 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1942 }
1943 }
1944
1945 static enum radv_cmd_flush_bits
1946 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1947 VkAccessFlags src_flags)
1948 {
1949 enum radv_cmd_flush_bits flush_bits = 0;
1950 uint32_t b;
1951 for_each_bit(b, src_flags) {
1952 switch ((VkAccessFlagBits)(1 << b)) {
1953 case VK_ACCESS_SHADER_WRITE_BIT:
1954 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1955 break;
1956 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1957 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1958 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1959 break;
1960 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1961 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1962 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1963 break;
1964 case VK_ACCESS_TRANSFER_WRITE_BIT:
1965 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1966 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1967 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1968 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1969 RADV_CMD_FLAG_INV_GLOBAL_L2;
1970 break;
1971 default:
1972 break;
1973 }
1974 }
1975 return flush_bits;
1976 }
1977
1978 static enum radv_cmd_flush_bits
1979 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1980 VkAccessFlags dst_flags,
1981 struct radv_image *image)
1982 {
1983 enum radv_cmd_flush_bits flush_bits = 0;
1984 uint32_t b;
1985 for_each_bit(b, dst_flags) {
1986 switch ((VkAccessFlagBits)(1 << b)) {
1987 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1988 case VK_ACCESS_INDEX_READ_BIT:
1989 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1990 break;
1991 case VK_ACCESS_UNIFORM_READ_BIT:
1992 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1993 break;
1994 case VK_ACCESS_SHADER_READ_BIT:
1995 case VK_ACCESS_TRANSFER_READ_BIT:
1996 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1997 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1998 RADV_CMD_FLAG_INV_GLOBAL_L2;
1999 break;
2000 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2001 /* TODO: change to image && when the image gets passed
2002 * through from the subpass. */
2003 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2004 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2005 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2006 break;
2007 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2008 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2009 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2010 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2011 break;
2012 default:
2013 break;
2014 }
2015 }
2016 return flush_bits;
2017 }
2018
2019 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2020 {
2021 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2022 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2023 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2024 NULL);
2025 }
2026
2027 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2028 VkAttachmentReference att)
2029 {
2030 unsigned idx = att.attachment;
2031 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2032 VkImageSubresourceRange range;
2033 range.aspectMask = 0;
2034 range.baseMipLevel = view->base_mip;
2035 range.levelCount = 1;
2036 range.baseArrayLayer = view->base_layer;
2037 range.layerCount = cmd_buffer->state.framebuffer->layers;
2038
2039 radv_handle_image_transition(cmd_buffer,
2040 view->image,
2041 cmd_buffer->state.attachments[idx].current_layout,
2042 att.layout, 0, 0, &range,
2043 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2044
2045 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2046
2047
2048 }
2049
2050 void
2051 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2052 const struct radv_subpass *subpass, bool transitions)
2053 {
2054 if (transitions) {
2055 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2056
2057 for (unsigned i = 0; i < subpass->color_count; ++i) {
2058 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2059 radv_handle_subpass_image_transition(cmd_buffer,
2060 subpass->color_attachments[i]);
2061 }
2062
2063 for (unsigned i = 0; i < subpass->input_count; ++i) {
2064 radv_handle_subpass_image_transition(cmd_buffer,
2065 subpass->input_attachments[i]);
2066 }
2067
2068 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2069 radv_handle_subpass_image_transition(cmd_buffer,
2070 subpass->depth_stencil_attachment);
2071 }
2072 }
2073
2074 cmd_buffer->state.subpass = subpass;
2075
2076 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2077 }
2078
2079 static VkResult
2080 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2081 struct radv_render_pass *pass,
2082 const VkRenderPassBeginInfo *info)
2083 {
2084 struct radv_cmd_state *state = &cmd_buffer->state;
2085
2086 if (pass->attachment_count == 0) {
2087 state->attachments = NULL;
2088 return VK_SUCCESS;
2089 }
2090
2091 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2092 pass->attachment_count *
2093 sizeof(state->attachments[0]),
2094 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2095 if (state->attachments == NULL) {
2096 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2097 return cmd_buffer->record_result;
2098 }
2099
2100 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2101 struct radv_render_pass_attachment *att = &pass->attachments[i];
2102 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2103 VkImageAspectFlags clear_aspects = 0;
2104
2105 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2106 /* color attachment */
2107 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2108 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2109 }
2110 } else {
2111 /* depthstencil attachment */
2112 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2113 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2114 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2115 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2116 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2117 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2118 }
2119 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2120 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2121 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2122 }
2123 }
2124
2125 state->attachments[i].pending_clear_aspects = clear_aspects;
2126 state->attachments[i].cleared_views = 0;
2127 if (clear_aspects && info) {
2128 assert(info->clearValueCount > i);
2129 state->attachments[i].clear_value = info->pClearValues[i];
2130 }
2131
2132 state->attachments[i].current_layout = att->initial_layout;
2133 }
2134
2135 return VK_SUCCESS;
2136 }
2137
2138 VkResult radv_AllocateCommandBuffers(
2139 VkDevice _device,
2140 const VkCommandBufferAllocateInfo *pAllocateInfo,
2141 VkCommandBuffer *pCommandBuffers)
2142 {
2143 RADV_FROM_HANDLE(radv_device, device, _device);
2144 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2145
2146 VkResult result = VK_SUCCESS;
2147 uint32_t i;
2148
2149 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2150
2151 if (!list_empty(&pool->free_cmd_buffers)) {
2152 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2153
2154 list_del(&cmd_buffer->pool_link);
2155 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2156
2157 result = radv_reset_cmd_buffer(cmd_buffer);
2158 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2159 cmd_buffer->level = pAllocateInfo->level;
2160
2161 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2162 } else {
2163 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2164 &pCommandBuffers[i]);
2165 }
2166 if (result != VK_SUCCESS)
2167 break;
2168 }
2169
2170 if (result != VK_SUCCESS) {
2171 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2172 i, pCommandBuffers);
2173
2174 /* From the Vulkan 1.0.66 spec:
2175 *
2176 * "vkAllocateCommandBuffers can be used to create multiple
2177 * command buffers. If the creation of any of those command
2178 * buffers fails, the implementation must destroy all
2179 * successfully created command buffer objects from this
2180 * command, set all entries of the pCommandBuffers array to
2181 * NULL and return the error."
2182 */
2183 memset(pCommandBuffers, 0,
2184 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2185 }
2186
2187 return result;
2188 }
2189
2190 void radv_FreeCommandBuffers(
2191 VkDevice device,
2192 VkCommandPool commandPool,
2193 uint32_t commandBufferCount,
2194 const VkCommandBuffer *pCommandBuffers)
2195 {
2196 for (uint32_t i = 0; i < commandBufferCount; i++) {
2197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2198
2199 if (cmd_buffer) {
2200 if (cmd_buffer->pool) {
2201 list_del(&cmd_buffer->pool_link);
2202 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2203 } else
2204 radv_cmd_buffer_destroy(cmd_buffer);
2205
2206 }
2207 }
2208 }
2209
2210 VkResult radv_ResetCommandBuffer(
2211 VkCommandBuffer commandBuffer,
2212 VkCommandBufferResetFlags flags)
2213 {
2214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2215 return radv_reset_cmd_buffer(cmd_buffer);
2216 }
2217
2218 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2219 {
2220 struct radv_device *device = cmd_buffer->device;
2221 if (device->gfx_init) {
2222 uint64_t va = radv_buffer_get_va(device->gfx_init);
2223 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2224 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2225 radeon_emit(cmd_buffer->cs, va);
2226 radeon_emit(cmd_buffer->cs, va >> 32);
2227 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2228 } else
2229 si_init_config(cmd_buffer);
2230 }
2231
2232 VkResult radv_BeginCommandBuffer(
2233 VkCommandBuffer commandBuffer,
2234 const VkCommandBufferBeginInfo *pBeginInfo)
2235 {
2236 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2237 VkResult result = VK_SUCCESS;
2238
2239 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2240 /* If the command buffer has already been resetted with
2241 * vkResetCommandBuffer, no need to do it again.
2242 */
2243 result = radv_reset_cmd_buffer(cmd_buffer);
2244 if (result != VK_SUCCESS)
2245 return result;
2246 }
2247
2248 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2249 cmd_buffer->state.last_primitive_reset_en = -1;
2250 cmd_buffer->state.last_index_type = -1;
2251 cmd_buffer->usage_flags = pBeginInfo->flags;
2252
2253 /* setup initial configuration into command buffer */
2254 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2255 switch (cmd_buffer->queue_family_index) {
2256 case RADV_QUEUE_GENERAL:
2257 emit_gfx_buffer_state(cmd_buffer);
2258 break;
2259 case RADV_QUEUE_COMPUTE:
2260 si_init_compute(cmd_buffer);
2261 break;
2262 case RADV_QUEUE_TRANSFER:
2263 default:
2264 break;
2265 }
2266 }
2267
2268 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2269 assert(pBeginInfo->pInheritanceInfo);
2270 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2271 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2272
2273 struct radv_subpass *subpass =
2274 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2275
2276 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2277 if (result != VK_SUCCESS)
2278 return result;
2279
2280 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2281 }
2282
2283 if (unlikely(cmd_buffer->device->trace_bo))
2284 radv_cmd_buffer_trace_emit(cmd_buffer);
2285
2286 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2287
2288 return result;
2289 }
2290
2291 void radv_CmdBindVertexBuffers(
2292 VkCommandBuffer commandBuffer,
2293 uint32_t firstBinding,
2294 uint32_t bindingCount,
2295 const VkBuffer* pBuffers,
2296 const VkDeviceSize* pOffsets)
2297 {
2298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2299 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2300 bool changed = false;
2301
2302 /* We have to defer setting up vertex buffer since we need the buffer
2303 * stride from the pipeline. */
2304
2305 assert(firstBinding + bindingCount <= MAX_VBS);
2306 for (uint32_t i = 0; i < bindingCount; i++) {
2307 uint32_t idx = firstBinding + i;
2308
2309 if (!changed &&
2310 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2311 vb[idx].offset != pOffsets[i])) {
2312 changed = true;
2313 }
2314
2315 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2316 vb[idx].offset = pOffsets[i];
2317
2318 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2319 vb[idx].buffer->bo, 8);
2320 }
2321
2322 if (!changed) {
2323 /* No state changes. */
2324 return;
2325 }
2326
2327 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2328 }
2329
2330 void radv_CmdBindIndexBuffer(
2331 VkCommandBuffer commandBuffer,
2332 VkBuffer buffer,
2333 VkDeviceSize offset,
2334 VkIndexType indexType)
2335 {
2336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2337 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2338
2339 if (cmd_buffer->state.index_buffer == index_buffer &&
2340 cmd_buffer->state.index_offset == offset &&
2341 cmd_buffer->state.index_type == indexType) {
2342 /* No state changes. */
2343 return;
2344 }
2345
2346 cmd_buffer->state.index_buffer = index_buffer;
2347 cmd_buffer->state.index_offset = offset;
2348 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2349 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2350 cmd_buffer->state.index_va += index_buffer->offset + offset;
2351
2352 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2353 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2354 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2355 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2356 }
2357
2358
2359 static void
2360 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2361 struct radv_descriptor_set *set, unsigned idx)
2362 {
2363 struct radeon_winsys *ws = cmd_buffer->device->ws;
2364
2365 radv_set_descriptor_set(cmd_buffer, set, idx);
2366 if (!set)
2367 return;
2368
2369 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2370
2371 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2372 if (set->descriptors[j])
2373 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2374
2375 if(set->bo)
2376 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2377 }
2378
2379 void radv_CmdBindDescriptorSets(
2380 VkCommandBuffer commandBuffer,
2381 VkPipelineBindPoint pipelineBindPoint,
2382 VkPipelineLayout _layout,
2383 uint32_t firstSet,
2384 uint32_t descriptorSetCount,
2385 const VkDescriptorSet* pDescriptorSets,
2386 uint32_t dynamicOffsetCount,
2387 const uint32_t* pDynamicOffsets)
2388 {
2389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2390 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2391 unsigned dyn_idx = 0;
2392
2393 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2394 unsigned idx = i + firstSet;
2395 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2396 radv_bind_descriptor_set(cmd_buffer, set, idx);
2397
2398 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2399 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2400 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2401 assert(dyn_idx < dynamicOffsetCount);
2402
2403 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2404 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2405 dst[0] = va;
2406 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2407 dst[2] = range->size;
2408 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2409 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2410 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2411 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2412 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2413 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2414 cmd_buffer->push_constant_stages |=
2415 set->layout->dynamic_shader_stages;
2416 }
2417 }
2418 }
2419
2420 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2421 struct radv_descriptor_set *set,
2422 struct radv_descriptor_set_layout *layout)
2423 {
2424 set->size = layout->size;
2425 set->layout = layout;
2426
2427 if (cmd_buffer->push_descriptors.capacity < set->size) {
2428 size_t new_size = MAX2(set->size, 1024);
2429 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2430 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2431
2432 free(set->mapped_ptr);
2433 set->mapped_ptr = malloc(new_size);
2434
2435 if (!set->mapped_ptr) {
2436 cmd_buffer->push_descriptors.capacity = 0;
2437 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2438 return false;
2439 }
2440
2441 cmd_buffer->push_descriptors.capacity = new_size;
2442 }
2443
2444 return true;
2445 }
2446
2447 void radv_meta_push_descriptor_set(
2448 struct radv_cmd_buffer* cmd_buffer,
2449 VkPipelineBindPoint pipelineBindPoint,
2450 VkPipelineLayout _layout,
2451 uint32_t set,
2452 uint32_t descriptorWriteCount,
2453 const VkWriteDescriptorSet* pDescriptorWrites)
2454 {
2455 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2456 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2457 unsigned bo_offset;
2458
2459 assert(set == 0);
2460 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2461
2462 push_set->size = layout->set[set].layout->size;
2463 push_set->layout = layout->set[set].layout;
2464
2465 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2466 &bo_offset,
2467 (void**) &push_set->mapped_ptr))
2468 return;
2469
2470 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2471 push_set->va += bo_offset;
2472
2473 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2474 radv_descriptor_set_to_handle(push_set),
2475 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2476
2477 radv_set_descriptor_set(cmd_buffer, push_set, set);
2478 }
2479
2480 void radv_CmdPushDescriptorSetKHR(
2481 VkCommandBuffer commandBuffer,
2482 VkPipelineBindPoint pipelineBindPoint,
2483 VkPipelineLayout _layout,
2484 uint32_t set,
2485 uint32_t descriptorWriteCount,
2486 const VkWriteDescriptorSet* pDescriptorWrites)
2487 {
2488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2489 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2490 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2491
2492 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2493
2494 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2495 return;
2496
2497 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2498 radv_descriptor_set_to_handle(push_set),
2499 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2500
2501 radv_set_descriptor_set(cmd_buffer, push_set, set);
2502 cmd_buffer->state.push_descriptors_dirty = true;
2503 }
2504
2505 void radv_CmdPushDescriptorSetWithTemplateKHR(
2506 VkCommandBuffer commandBuffer,
2507 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2508 VkPipelineLayout _layout,
2509 uint32_t set,
2510 const void* pData)
2511 {
2512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2513 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2514 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2515
2516 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2517
2518 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2519 return;
2520
2521 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2522 descriptorUpdateTemplate, pData);
2523
2524 radv_set_descriptor_set(cmd_buffer, push_set, set);
2525 cmd_buffer->state.push_descriptors_dirty = true;
2526 }
2527
2528 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2529 VkPipelineLayout layout,
2530 VkShaderStageFlags stageFlags,
2531 uint32_t offset,
2532 uint32_t size,
2533 const void* pValues)
2534 {
2535 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2536 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2537 cmd_buffer->push_constant_stages |= stageFlags;
2538 }
2539
2540 VkResult radv_EndCommandBuffer(
2541 VkCommandBuffer commandBuffer)
2542 {
2543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2544
2545 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2546 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2547 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2548 si_emit_cache_flush(cmd_buffer);
2549 }
2550
2551 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2552
2553 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2554 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2555
2556 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2557
2558 return cmd_buffer->record_result;
2559 }
2560
2561 static void
2562 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2563 {
2564 struct radv_shader_variant *compute_shader;
2565 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2566 struct radv_device *device = cmd_buffer->device;
2567 unsigned compute_resource_limits;
2568 unsigned waves_per_threadgroup;
2569 uint64_t va;
2570
2571 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2572 return;
2573
2574 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2575
2576 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2577 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2578
2579 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2580 cmd_buffer->cs, 19);
2581
2582 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2583 radeon_emit(cmd_buffer->cs, va >> 8);
2584 radeon_emit(cmd_buffer->cs, va >> 40);
2585
2586 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2587 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2588 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2589
2590
2591 cmd_buffer->compute_scratch_size_needed =
2592 MAX2(cmd_buffer->compute_scratch_size_needed,
2593 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2594
2595 /* change these once we have scratch support */
2596 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2597 S_00B860_WAVES(pipeline->max_waves) |
2598 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2599
2600 /* Calculate best compute resource limits. */
2601 waves_per_threadgroup =
2602 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2603 compute_shader->info.cs.block_size[1] *
2604 compute_shader->info.cs.block_size[2], 64);
2605 compute_resource_limits =
2606 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2607
2608 if (device->physical_device->rad_info.chip_class >= CIK) {
2609 unsigned num_cu_per_se =
2610 device->physical_device->rad_info.num_good_compute_units /
2611 device->physical_device->rad_info.max_se;
2612
2613 /* Force even distribution on all SIMDs in CU if the workgroup
2614 * size is 64. This has shown some good improvements if # of
2615 * CUs per SE is not a multiple of 4.
2616 */
2617 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2618 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2619 }
2620
2621 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2622 compute_resource_limits);
2623
2624 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2625 radeon_emit(cmd_buffer->cs,
2626 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2627 radeon_emit(cmd_buffer->cs,
2628 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2629 radeon_emit(cmd_buffer->cs,
2630 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2631
2632 assert(cmd_buffer->cs->cdw <= cdw_max);
2633
2634 if (unlikely(cmd_buffer->device->trace_bo))
2635 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2636 }
2637
2638 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2639 {
2640 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2641 }
2642
2643 void radv_CmdBindPipeline(
2644 VkCommandBuffer commandBuffer,
2645 VkPipelineBindPoint pipelineBindPoint,
2646 VkPipeline _pipeline)
2647 {
2648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2649 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2650
2651 switch (pipelineBindPoint) {
2652 case VK_PIPELINE_BIND_POINT_COMPUTE:
2653 if (cmd_buffer->state.compute_pipeline == pipeline)
2654 return;
2655 radv_mark_descriptor_sets_dirty(cmd_buffer);
2656
2657 cmd_buffer->state.compute_pipeline = pipeline;
2658 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2659 break;
2660 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2661 if (cmd_buffer->state.pipeline == pipeline)
2662 return;
2663 radv_mark_descriptor_sets_dirty(cmd_buffer);
2664
2665 cmd_buffer->state.pipeline = pipeline;
2666 if (!pipeline)
2667 break;
2668
2669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2670 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2671
2672 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2673
2674 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2675 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2676 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2677 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2678
2679 if (radv_pipeline_has_tess(pipeline))
2680 cmd_buffer->tess_rings_needed = true;
2681
2682 if (radv_pipeline_has_gs(pipeline)) {
2683 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2684 AC_UD_SCRATCH_RING_OFFSETS);
2685 if (cmd_buffer->ring_offsets_idx == -1)
2686 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2687 else if (loc->sgpr_idx != -1)
2688 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2689 }
2690 break;
2691 default:
2692 assert(!"invalid bind point");
2693 break;
2694 }
2695 }
2696
2697 void radv_CmdSetViewport(
2698 VkCommandBuffer commandBuffer,
2699 uint32_t firstViewport,
2700 uint32_t viewportCount,
2701 const VkViewport* pViewports)
2702 {
2703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2705
2706 assert(firstViewport < MAX_VIEWPORTS);
2707 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2708
2709 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2710 pViewports, viewportCount * sizeof(*pViewports));
2711
2712 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2713 }
2714
2715 void radv_CmdSetScissor(
2716 VkCommandBuffer commandBuffer,
2717 uint32_t firstScissor,
2718 uint32_t scissorCount,
2719 const VkRect2D* pScissors)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2723
2724 assert(firstScissor < MAX_SCISSORS);
2725 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2726
2727 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2728 pScissors, scissorCount * sizeof(*pScissors));
2729 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2730 }
2731
2732 void radv_CmdSetLineWidth(
2733 VkCommandBuffer commandBuffer,
2734 float lineWidth)
2735 {
2736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2737 cmd_buffer->state.dynamic.line_width = lineWidth;
2738 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2739 }
2740
2741 void radv_CmdSetDepthBias(
2742 VkCommandBuffer commandBuffer,
2743 float depthBiasConstantFactor,
2744 float depthBiasClamp,
2745 float depthBiasSlopeFactor)
2746 {
2747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2748
2749 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2750 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2751 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2752
2753 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2754 }
2755
2756 void radv_CmdSetBlendConstants(
2757 VkCommandBuffer commandBuffer,
2758 const float blendConstants[4])
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761
2762 memcpy(cmd_buffer->state.dynamic.blend_constants,
2763 blendConstants, sizeof(float) * 4);
2764
2765 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2766 }
2767
2768 void radv_CmdSetDepthBounds(
2769 VkCommandBuffer commandBuffer,
2770 float minDepthBounds,
2771 float maxDepthBounds)
2772 {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2774
2775 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2776 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2777
2778 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2779 }
2780
2781 void radv_CmdSetStencilCompareMask(
2782 VkCommandBuffer commandBuffer,
2783 VkStencilFaceFlags faceMask,
2784 uint32_t compareMask)
2785 {
2786 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2787
2788 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2789 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2790 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2791 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2792
2793 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2794 }
2795
2796 void radv_CmdSetStencilWriteMask(
2797 VkCommandBuffer commandBuffer,
2798 VkStencilFaceFlags faceMask,
2799 uint32_t writeMask)
2800 {
2801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2802
2803 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2804 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2805 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2806 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2807
2808 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2809 }
2810
2811 void radv_CmdSetStencilReference(
2812 VkCommandBuffer commandBuffer,
2813 VkStencilFaceFlags faceMask,
2814 uint32_t reference)
2815 {
2816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2817
2818 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2819 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2820 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2821 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2822
2823 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2824 }
2825
2826 void radv_CmdExecuteCommands(
2827 VkCommandBuffer commandBuffer,
2828 uint32_t commandBufferCount,
2829 const VkCommandBuffer* pCmdBuffers)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2832
2833 assert(commandBufferCount > 0);
2834
2835 /* Emit pending flushes on primary prior to executing secondary */
2836 si_emit_cache_flush(primary);
2837
2838 for (uint32_t i = 0; i < commandBufferCount; i++) {
2839 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2840
2841 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2842 secondary->scratch_size_needed);
2843 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2844 secondary->compute_scratch_size_needed);
2845
2846 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2847 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2848 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2849 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2850 if (secondary->tess_rings_needed)
2851 primary->tess_rings_needed = true;
2852 if (secondary->sample_positions_needed)
2853 primary->sample_positions_needed = true;
2854
2855 if (secondary->ring_offsets_idx != -1) {
2856 if (primary->ring_offsets_idx == -1)
2857 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2858 else
2859 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2860 }
2861 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2862
2863
2864 /* When the secondary command buffer is compute only we don't
2865 * need to re-emit the current graphics pipeline.
2866 */
2867 if (secondary->state.emitted_pipeline) {
2868 primary->state.emitted_pipeline =
2869 secondary->state.emitted_pipeline;
2870 }
2871
2872 /* When the secondary command buffer is graphics only we don't
2873 * need to re-emit the current compute pipeline.
2874 */
2875 if (secondary->state.emitted_compute_pipeline) {
2876 primary->state.emitted_compute_pipeline =
2877 secondary->state.emitted_compute_pipeline;
2878 }
2879
2880 /* Only re-emit the draw packets when needed. */
2881 if (secondary->state.last_primitive_reset_en != -1) {
2882 primary->state.last_primitive_reset_en =
2883 secondary->state.last_primitive_reset_en;
2884 }
2885
2886 if (secondary->state.last_primitive_reset_index) {
2887 primary->state.last_primitive_reset_index =
2888 secondary->state.last_primitive_reset_index;
2889 }
2890
2891 if (secondary->state.last_ia_multi_vgt_param) {
2892 primary->state.last_ia_multi_vgt_param =
2893 secondary->state.last_ia_multi_vgt_param;
2894 }
2895
2896 if (secondary->state.last_index_type != -1) {
2897 primary->state.last_index_type =
2898 secondary->state.last_index_type;
2899 }
2900 }
2901
2902 /* After executing commands from secondary buffers we have to dirty
2903 * some states.
2904 */
2905 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2906 RADV_CMD_DIRTY_INDEX_BUFFER |
2907 RADV_CMD_DIRTY_DYNAMIC_ALL;
2908 radv_mark_descriptor_sets_dirty(primary);
2909 }
2910
2911 VkResult radv_CreateCommandPool(
2912 VkDevice _device,
2913 const VkCommandPoolCreateInfo* pCreateInfo,
2914 const VkAllocationCallbacks* pAllocator,
2915 VkCommandPool* pCmdPool)
2916 {
2917 RADV_FROM_HANDLE(radv_device, device, _device);
2918 struct radv_cmd_pool *pool;
2919
2920 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2921 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2922 if (pool == NULL)
2923 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2924
2925 if (pAllocator)
2926 pool->alloc = *pAllocator;
2927 else
2928 pool->alloc = device->alloc;
2929
2930 list_inithead(&pool->cmd_buffers);
2931 list_inithead(&pool->free_cmd_buffers);
2932
2933 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2934
2935 *pCmdPool = radv_cmd_pool_to_handle(pool);
2936
2937 return VK_SUCCESS;
2938
2939 }
2940
2941 void radv_DestroyCommandPool(
2942 VkDevice _device,
2943 VkCommandPool commandPool,
2944 const VkAllocationCallbacks* pAllocator)
2945 {
2946 RADV_FROM_HANDLE(radv_device, device, _device);
2947 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2948
2949 if (!pool)
2950 return;
2951
2952 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2953 &pool->cmd_buffers, pool_link) {
2954 radv_cmd_buffer_destroy(cmd_buffer);
2955 }
2956
2957 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2958 &pool->free_cmd_buffers, pool_link) {
2959 radv_cmd_buffer_destroy(cmd_buffer);
2960 }
2961
2962 vk_free2(&device->alloc, pAllocator, pool);
2963 }
2964
2965 VkResult radv_ResetCommandPool(
2966 VkDevice device,
2967 VkCommandPool commandPool,
2968 VkCommandPoolResetFlags flags)
2969 {
2970 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2971 VkResult result;
2972
2973 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2974 &pool->cmd_buffers, pool_link) {
2975 result = radv_reset_cmd_buffer(cmd_buffer);
2976 if (result != VK_SUCCESS)
2977 return result;
2978 }
2979
2980 return VK_SUCCESS;
2981 }
2982
2983 void radv_TrimCommandPoolKHR(
2984 VkDevice device,
2985 VkCommandPool commandPool,
2986 VkCommandPoolTrimFlagsKHR flags)
2987 {
2988 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2989
2990 if (!pool)
2991 return;
2992
2993 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2994 &pool->free_cmd_buffers, pool_link) {
2995 radv_cmd_buffer_destroy(cmd_buffer);
2996 }
2997 }
2998
2999 void radv_CmdBeginRenderPass(
3000 VkCommandBuffer commandBuffer,
3001 const VkRenderPassBeginInfo* pRenderPassBegin,
3002 VkSubpassContents contents)
3003 {
3004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3005 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3006 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3007
3008 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3009 cmd_buffer->cs, 2048);
3010 MAYBE_UNUSED VkResult result;
3011
3012 cmd_buffer->state.framebuffer = framebuffer;
3013 cmd_buffer->state.pass = pass;
3014 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3015
3016 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3017 if (result != VK_SUCCESS)
3018 return;
3019
3020 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3021 assert(cmd_buffer->cs->cdw <= cdw_max);
3022
3023 radv_cmd_buffer_clear_subpass(cmd_buffer);
3024 }
3025
3026 void radv_CmdNextSubpass(
3027 VkCommandBuffer commandBuffer,
3028 VkSubpassContents contents)
3029 {
3030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3031
3032 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3033
3034 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3035 2048);
3036
3037 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3038 radv_cmd_buffer_clear_subpass(cmd_buffer);
3039 }
3040
3041 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3042 {
3043 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3044 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3045 if (!pipeline->shaders[stage])
3046 continue;
3047 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3048 if (loc->sgpr_idx == -1)
3049 continue;
3050 uint32_t base_reg = pipeline->user_data_0[stage];
3051 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3052
3053 }
3054 if (pipeline->gs_copy_shader) {
3055 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3056 if (loc->sgpr_idx != -1) {
3057 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3058 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3059 }
3060 }
3061 }
3062
3063 static void
3064 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3065 uint32_t vertex_count)
3066 {
3067 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3068 radeon_emit(cmd_buffer->cs, vertex_count);
3069 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3070 S_0287F0_USE_OPAQUE(0));
3071 }
3072
3073 static void
3074 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3075 uint64_t index_va,
3076 uint32_t index_count)
3077 {
3078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3079 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3080 radeon_emit(cmd_buffer->cs, index_va);
3081 radeon_emit(cmd_buffer->cs, index_va >> 32);
3082 radeon_emit(cmd_buffer->cs, index_count);
3083 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3084 }
3085
3086 static void
3087 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3088 bool indexed,
3089 uint32_t draw_count,
3090 uint64_t count_va,
3091 uint32_t stride)
3092 {
3093 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3094 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3095 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3096 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3097 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3098 assert(base_reg);
3099
3100 if (draw_count == 1 && !count_va && !draw_id_enable) {
3101 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3102 PKT3_DRAW_INDIRECT, 3, false));
3103 radeon_emit(cs, 0);
3104 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3105 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3106 radeon_emit(cs, di_src_sel);
3107 } else {
3108 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3109 PKT3_DRAW_INDIRECT_MULTI,
3110 8, false));
3111 radeon_emit(cs, 0);
3112 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3113 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3114 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3115 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3116 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3117 radeon_emit(cs, draw_count); /* count */
3118 radeon_emit(cs, count_va); /* count_addr */
3119 radeon_emit(cs, count_va >> 32);
3120 radeon_emit(cs, stride); /* stride */
3121 radeon_emit(cs, di_src_sel);
3122 }
3123 }
3124
3125 struct radv_draw_info {
3126 /**
3127 * Number of vertices.
3128 */
3129 uint32_t count;
3130
3131 /**
3132 * Index of the first vertex.
3133 */
3134 int32_t vertex_offset;
3135
3136 /**
3137 * First instance id.
3138 */
3139 uint32_t first_instance;
3140
3141 /**
3142 * Number of instances.
3143 */
3144 uint32_t instance_count;
3145
3146 /**
3147 * First index (indexed draws only).
3148 */
3149 uint32_t first_index;
3150
3151 /**
3152 * Whether it's an indexed draw.
3153 */
3154 bool indexed;
3155
3156 /**
3157 * Indirect draw parameters resource.
3158 */
3159 struct radv_buffer *indirect;
3160 uint64_t indirect_offset;
3161 uint32_t stride;
3162
3163 /**
3164 * Draw count parameters resource.
3165 */
3166 struct radv_buffer *count_buffer;
3167 uint64_t count_buffer_offset;
3168 };
3169
3170 static void
3171 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3172 const struct radv_draw_info *info)
3173 {
3174 struct radv_cmd_state *state = &cmd_buffer->state;
3175 struct radeon_winsys *ws = cmd_buffer->device->ws;
3176 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3177
3178 if (info->indirect) {
3179 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3180 uint64_t count_va = 0;
3181
3182 va += info->indirect->offset + info->indirect_offset;
3183
3184 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3185
3186 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3187 radeon_emit(cs, 1);
3188 radeon_emit(cs, va);
3189 radeon_emit(cs, va >> 32);
3190
3191 if (info->count_buffer) {
3192 count_va = radv_buffer_get_va(info->count_buffer->bo);
3193 count_va += info->count_buffer->offset +
3194 info->count_buffer_offset;
3195
3196 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3197 }
3198
3199 if (!state->subpass->view_mask) {
3200 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3201 info->indexed,
3202 info->count,
3203 count_va,
3204 info->stride);
3205 } else {
3206 unsigned i;
3207 for_each_bit(i, state->subpass->view_mask) {
3208 radv_emit_view_index(cmd_buffer, i);
3209
3210 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3211 info->indexed,
3212 info->count,
3213 count_va,
3214 info->stride);
3215 }
3216 }
3217 } else {
3218 assert(state->pipeline->graphics.vtx_base_sgpr);
3219 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3220 state->pipeline->graphics.vtx_emit_num);
3221 radeon_emit(cs, info->vertex_offset);
3222 radeon_emit(cs, info->first_instance);
3223 if (state->pipeline->graphics.vtx_emit_num == 3)
3224 radeon_emit(cs, 0);
3225
3226 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3227 radeon_emit(cs, info->instance_count);
3228
3229 if (info->indexed) {
3230 int index_size = state->index_type ? 4 : 2;
3231 uint64_t index_va;
3232
3233 index_va = state->index_va;
3234 index_va += info->first_index * index_size;
3235
3236 if (!state->subpass->view_mask) {
3237 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3238 index_va,
3239 info->count);
3240 } else {
3241 unsigned i;
3242 for_each_bit(i, state->subpass->view_mask) {
3243 radv_emit_view_index(cmd_buffer, i);
3244
3245 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3246 index_va,
3247 info->count);
3248 }
3249 }
3250 } else {
3251 if (!state->subpass->view_mask) {
3252 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3253 } else {
3254 unsigned i;
3255 for_each_bit(i, state->subpass->view_mask) {
3256 radv_emit_view_index(cmd_buffer, i);
3257
3258 radv_cs_emit_draw_packet(cmd_buffer,
3259 info->count);
3260 }
3261 }
3262 }
3263 }
3264 }
3265
3266 static void
3267 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3268 const struct radv_draw_info *info)
3269 {
3270 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3271 radv_emit_graphics_pipeline(cmd_buffer);
3272
3273 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3274 radv_emit_framebuffer_state(cmd_buffer);
3275
3276 if (info->indexed) {
3277 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3278 radv_emit_index_buffer(cmd_buffer);
3279 } else {
3280 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3281 * so the state must be re-emitted before the next indexed
3282 * draw.
3283 */
3284 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3285 cmd_buffer->state.last_index_type = -1;
3286 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3287 }
3288 }
3289
3290 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3291
3292 radv_emit_draw_registers(cmd_buffer, info->indexed,
3293 info->instance_count > 1, info->indirect,
3294 info->indirect ? 0 : info->count);
3295 }
3296
3297 static void
3298 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3299 const struct radv_draw_info *info)
3300 {
3301 bool pipeline_is_dirty =
3302 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3303 cmd_buffer->state.pipeline &&
3304 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3305
3306 MAYBE_UNUSED unsigned cdw_max =
3307 radeon_check_space(cmd_buffer->device->ws,
3308 cmd_buffer->cs, 4096);
3309
3310 /* Use optimal packet order based on whether we need to sync the
3311 * pipeline.
3312 */
3313 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3314 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3315 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3316 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3317 /* If we have to wait for idle, set all states first, so that
3318 * all SET packets are processed in parallel with previous draw
3319 * calls. Then upload descriptors, set shader pointers, and
3320 * draw, and prefetch at the end. This ensures that the time
3321 * the CUs are idle is very short. (there are only SET_SH
3322 * packets between the wait and the draw)
3323 */
3324 radv_emit_all_graphics_states(cmd_buffer, info);
3325 si_emit_cache_flush(cmd_buffer);
3326 /* <-- CUs are idle here --> */
3327
3328 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3329 return;
3330
3331 radv_emit_draw_packets(cmd_buffer, info);
3332 /* <-- CUs are busy here --> */
3333
3334 /* Start prefetches after the draw has been started. Both will
3335 * run in parallel, but starting the draw first is more
3336 * important.
3337 */
3338 if (pipeline_is_dirty) {
3339 radv_emit_prefetch(cmd_buffer,
3340 cmd_buffer->state.pipeline);
3341 }
3342 } else {
3343 /* If we don't wait for idle, start prefetches first, then set
3344 * states, and draw at the end.
3345 */
3346 si_emit_cache_flush(cmd_buffer);
3347
3348 if (pipeline_is_dirty) {
3349 radv_emit_prefetch(cmd_buffer,
3350 cmd_buffer->state.pipeline);
3351 }
3352
3353 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3354 return;
3355
3356 radv_emit_all_graphics_states(cmd_buffer, info);
3357 radv_emit_draw_packets(cmd_buffer, info);
3358 }
3359
3360 assert(cmd_buffer->cs->cdw <= cdw_max);
3361 radv_cmd_buffer_after_draw(cmd_buffer);
3362 }
3363
3364 void radv_CmdDraw(
3365 VkCommandBuffer commandBuffer,
3366 uint32_t vertexCount,
3367 uint32_t instanceCount,
3368 uint32_t firstVertex,
3369 uint32_t firstInstance)
3370 {
3371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3372 struct radv_draw_info info = {};
3373
3374 info.count = vertexCount;
3375 info.instance_count = instanceCount;
3376 info.first_instance = firstInstance;
3377 info.vertex_offset = firstVertex;
3378
3379 radv_draw(cmd_buffer, &info);
3380 }
3381
3382 void radv_CmdDrawIndexed(
3383 VkCommandBuffer commandBuffer,
3384 uint32_t indexCount,
3385 uint32_t instanceCount,
3386 uint32_t firstIndex,
3387 int32_t vertexOffset,
3388 uint32_t firstInstance)
3389 {
3390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3391 struct radv_draw_info info = {};
3392
3393 info.indexed = true;
3394 info.count = indexCount;
3395 info.instance_count = instanceCount;
3396 info.first_index = firstIndex;
3397 info.vertex_offset = vertexOffset;
3398 info.first_instance = firstInstance;
3399
3400 radv_draw(cmd_buffer, &info);
3401 }
3402
3403 void radv_CmdDrawIndirect(
3404 VkCommandBuffer commandBuffer,
3405 VkBuffer _buffer,
3406 VkDeviceSize offset,
3407 uint32_t drawCount,
3408 uint32_t stride)
3409 {
3410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3411 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3412 struct radv_draw_info info = {};
3413
3414 info.count = drawCount;
3415 info.indirect = buffer;
3416 info.indirect_offset = offset;
3417 info.stride = stride;
3418
3419 radv_draw(cmd_buffer, &info);
3420 }
3421
3422 void radv_CmdDrawIndexedIndirect(
3423 VkCommandBuffer commandBuffer,
3424 VkBuffer _buffer,
3425 VkDeviceSize offset,
3426 uint32_t drawCount,
3427 uint32_t stride)
3428 {
3429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3430 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3431 struct radv_draw_info info = {};
3432
3433 info.indexed = true;
3434 info.count = drawCount;
3435 info.indirect = buffer;
3436 info.indirect_offset = offset;
3437 info.stride = stride;
3438
3439 radv_draw(cmd_buffer, &info);
3440 }
3441
3442 void radv_CmdDrawIndirectCountAMD(
3443 VkCommandBuffer commandBuffer,
3444 VkBuffer _buffer,
3445 VkDeviceSize offset,
3446 VkBuffer _countBuffer,
3447 VkDeviceSize countBufferOffset,
3448 uint32_t maxDrawCount,
3449 uint32_t stride)
3450 {
3451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3452 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3453 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3454 struct radv_draw_info info = {};
3455
3456 info.count = maxDrawCount;
3457 info.indirect = buffer;
3458 info.indirect_offset = offset;
3459 info.count_buffer = count_buffer;
3460 info.count_buffer_offset = countBufferOffset;
3461 info.stride = stride;
3462
3463 radv_draw(cmd_buffer, &info);
3464 }
3465
3466 void radv_CmdDrawIndexedIndirectCountAMD(
3467 VkCommandBuffer commandBuffer,
3468 VkBuffer _buffer,
3469 VkDeviceSize offset,
3470 VkBuffer _countBuffer,
3471 VkDeviceSize countBufferOffset,
3472 uint32_t maxDrawCount,
3473 uint32_t stride)
3474 {
3475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3476 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3477 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3478 struct radv_draw_info info = {};
3479
3480 info.indexed = true;
3481 info.count = maxDrawCount;
3482 info.indirect = buffer;
3483 info.indirect_offset = offset;
3484 info.count_buffer = count_buffer;
3485 info.count_buffer_offset = countBufferOffset;
3486 info.stride = stride;
3487
3488 radv_draw(cmd_buffer, &info);
3489 }
3490
3491 struct radv_dispatch_info {
3492 /**
3493 * Determine the layout of the grid (in block units) to be used.
3494 */
3495 uint32_t blocks[3];
3496
3497 /**
3498 * Whether it's an unaligned compute dispatch.
3499 */
3500 bool unaligned;
3501
3502 /**
3503 * Indirect compute parameters resource.
3504 */
3505 struct radv_buffer *indirect;
3506 uint64_t indirect_offset;
3507 };
3508
3509 static void
3510 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3511 const struct radv_dispatch_info *info)
3512 {
3513 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3514 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3515 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3516 struct radeon_winsys *ws = cmd_buffer->device->ws;
3517 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3518 struct ac_userdata_info *loc;
3519
3520 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3521 AC_UD_CS_GRID_SIZE);
3522
3523 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3524
3525 if (info->indirect) {
3526 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3527
3528 va += info->indirect->offset + info->indirect_offset;
3529
3530 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3531
3532 if (loc->sgpr_idx != -1) {
3533 for (unsigned i = 0; i < 3; ++i) {
3534 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3535 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3536 COPY_DATA_DST_SEL(COPY_DATA_REG));
3537 radeon_emit(cs, (va + 4 * i));
3538 radeon_emit(cs, (va + 4 * i) >> 32);
3539 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3540 + loc->sgpr_idx * 4) >> 2) + i);
3541 radeon_emit(cs, 0);
3542 }
3543 }
3544
3545 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3546 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3547 PKT3_SHADER_TYPE_S(1));
3548 radeon_emit(cs, va);
3549 radeon_emit(cs, va >> 32);
3550 radeon_emit(cs, dispatch_initiator);
3551 } else {
3552 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3553 PKT3_SHADER_TYPE_S(1));
3554 radeon_emit(cs, 1);
3555 radeon_emit(cs, va);
3556 radeon_emit(cs, va >> 32);
3557
3558 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3559 PKT3_SHADER_TYPE_S(1));
3560 radeon_emit(cs, 0);
3561 radeon_emit(cs, dispatch_initiator);
3562 }
3563 } else {
3564 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3565
3566 if (info->unaligned) {
3567 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3568 unsigned remainder[3];
3569
3570 /* If aligned, these should be an entire block size,
3571 * not 0.
3572 */
3573 remainder[0] = blocks[0] + cs_block_size[0] -
3574 align_u32_npot(blocks[0], cs_block_size[0]);
3575 remainder[1] = blocks[1] + cs_block_size[1] -
3576 align_u32_npot(blocks[1], cs_block_size[1]);
3577 remainder[2] = blocks[2] + cs_block_size[2] -
3578 align_u32_npot(blocks[2], cs_block_size[2]);
3579
3580 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3581 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3582 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3583
3584 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3585 radeon_emit(cs,
3586 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3587 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3588 radeon_emit(cs,
3589 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3590 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3591 radeon_emit(cs,
3592 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3593 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3594
3595 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3596 }
3597
3598 if (loc->sgpr_idx != -1) {
3599 assert(!loc->indirect);
3600 assert(loc->num_sgprs == 3);
3601
3602 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3603 loc->sgpr_idx * 4, 3);
3604 radeon_emit(cs, blocks[0]);
3605 radeon_emit(cs, blocks[1]);
3606 radeon_emit(cs, blocks[2]);
3607 }
3608
3609 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3610 PKT3_SHADER_TYPE_S(1));
3611 radeon_emit(cs, blocks[0]);
3612 radeon_emit(cs, blocks[1]);
3613 radeon_emit(cs, blocks[2]);
3614 radeon_emit(cs, dispatch_initiator);
3615 }
3616
3617 assert(cmd_buffer->cs->cdw <= cdw_max);
3618 }
3619
3620 static void
3621 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3622 {
3623 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3624 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3625 VK_SHADER_STAGE_COMPUTE_BIT);
3626 }
3627
3628 static void
3629 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3630 const struct radv_dispatch_info *info)
3631 {
3632 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3633 bool pipeline_is_dirty = pipeline &&
3634 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3635
3636 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3637 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3638 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3639 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3640 /* If we have to wait for idle, set all states first, so that
3641 * all SET packets are processed in parallel with previous draw
3642 * calls. Then upload descriptors, set shader pointers, and
3643 * dispatch, and prefetch at the end. This ensures that the
3644 * time the CUs are idle is very short. (there are only SET_SH
3645 * packets between the wait and the draw)
3646 */
3647 radv_emit_compute_pipeline(cmd_buffer);
3648 si_emit_cache_flush(cmd_buffer);
3649 /* <-- CUs are idle here --> */
3650
3651 radv_upload_compute_shader_descriptors(cmd_buffer);
3652
3653 radv_emit_dispatch_packets(cmd_buffer, info);
3654 /* <-- CUs are busy here --> */
3655
3656 /* Start prefetches after the dispatch has been started. Both
3657 * will run in parallel, but starting the dispatch first is
3658 * more important.
3659 */
3660 if (pipeline_is_dirty) {
3661 radv_emit_shader_prefetch(cmd_buffer,
3662 pipeline->shaders[MESA_SHADER_COMPUTE]);
3663 }
3664 } else {
3665 /* If we don't wait for idle, start prefetches first, then set
3666 * states, and dispatch at the end.
3667 */
3668 si_emit_cache_flush(cmd_buffer);
3669
3670 if (pipeline_is_dirty) {
3671 radv_emit_shader_prefetch(cmd_buffer,
3672 pipeline->shaders[MESA_SHADER_COMPUTE]);
3673 }
3674
3675 radv_upload_compute_shader_descriptors(cmd_buffer);
3676
3677 radv_emit_compute_pipeline(cmd_buffer);
3678 radv_emit_dispatch_packets(cmd_buffer, info);
3679 }
3680
3681 radv_cmd_buffer_after_draw(cmd_buffer);
3682 }
3683
3684 void radv_CmdDispatch(
3685 VkCommandBuffer commandBuffer,
3686 uint32_t x,
3687 uint32_t y,
3688 uint32_t z)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 struct radv_dispatch_info info = {};
3692
3693 info.blocks[0] = x;
3694 info.blocks[1] = y;
3695 info.blocks[2] = z;
3696
3697 radv_dispatch(cmd_buffer, &info);
3698 }
3699
3700 void radv_CmdDispatchIndirect(
3701 VkCommandBuffer commandBuffer,
3702 VkBuffer _buffer,
3703 VkDeviceSize offset)
3704 {
3705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3706 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3707 struct radv_dispatch_info info = {};
3708
3709 info.indirect = buffer;
3710 info.indirect_offset = offset;
3711
3712 radv_dispatch(cmd_buffer, &info);
3713 }
3714
3715 void radv_unaligned_dispatch(
3716 struct radv_cmd_buffer *cmd_buffer,
3717 uint32_t x,
3718 uint32_t y,
3719 uint32_t z)
3720 {
3721 struct radv_dispatch_info info = {};
3722
3723 info.blocks[0] = x;
3724 info.blocks[1] = y;
3725 info.blocks[2] = z;
3726 info.unaligned = 1;
3727
3728 radv_dispatch(cmd_buffer, &info);
3729 }
3730
3731 void radv_CmdEndRenderPass(
3732 VkCommandBuffer commandBuffer)
3733 {
3734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3735
3736 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3737
3738 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3739
3740 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3741 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3742 radv_handle_subpass_image_transition(cmd_buffer,
3743 (VkAttachmentReference){i, layout});
3744 }
3745
3746 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3747
3748 cmd_buffer->state.pass = NULL;
3749 cmd_buffer->state.subpass = NULL;
3750 cmd_buffer->state.attachments = NULL;
3751 cmd_buffer->state.framebuffer = NULL;
3752 }
3753
3754 /*
3755 * For HTILE we have the following interesting clear words:
3756 * 0x0000030f: Uncompressed.
3757 * 0xfffffff0: Clear depth to 1.0
3758 * 0x00000000: Clear depth to 0.0
3759 */
3760 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3761 struct radv_image *image,
3762 const VkImageSubresourceRange *range,
3763 uint32_t clear_word)
3764 {
3765 assert(range->baseMipLevel == 0);
3766 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3767 unsigned layer_count = radv_get_layerCount(image, range);
3768 uint64_t size = image->surface.htile_slice_size * layer_count;
3769 uint64_t offset = image->offset + image->htile_offset +
3770 image->surface.htile_slice_size * range->baseArrayLayer;
3771 struct radv_cmd_state *state = &cmd_buffer->state;
3772
3773 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3774 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3775
3776 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3777 size, clear_word);
3778
3779 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3780 }
3781
3782 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3783 struct radv_image *image,
3784 VkImageLayout src_layout,
3785 VkImageLayout dst_layout,
3786 unsigned src_queue_mask,
3787 unsigned dst_queue_mask,
3788 const VkImageSubresourceRange *range,
3789 VkImageAspectFlags pending_clears)
3790 {
3791 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3792 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3793 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3794 cmd_buffer->state.render_area.extent.width == image->info.width &&
3795 cmd_buffer->state.render_area.extent.height == image->info.height) {
3796 /* The clear will initialize htile. */
3797 return;
3798 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3799 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3800 /* TODO: merge with the clear if applicable */
3801 radv_initialize_htile(cmd_buffer, image, range, 0);
3802 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3803 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3804 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3805 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3806 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3807 VkImageSubresourceRange local_range = *range;
3808 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3809 local_range.baseMipLevel = 0;
3810 local_range.levelCount = 1;
3811
3812 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3813 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3814
3815 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3816
3817 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3818 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3819 }
3820 }
3821
3822 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3823 struct radv_image *image, uint32_t value)
3824 {
3825 struct radv_cmd_state *state = &cmd_buffer->state;
3826
3827 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3828 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3829
3830 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3831 image->offset + image->cmask.offset,
3832 image->cmask.size, value);
3833
3834 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3835 }
3836
3837 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3838 struct radv_image *image,
3839 VkImageLayout src_layout,
3840 VkImageLayout dst_layout,
3841 unsigned src_queue_mask,
3842 unsigned dst_queue_mask,
3843 const VkImageSubresourceRange *range)
3844 {
3845 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3846 if (image->fmask.size)
3847 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3848 else
3849 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3850 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3851 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3852 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3853 }
3854 }
3855
3856 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3857 struct radv_image *image, uint32_t value)
3858 {
3859 struct radv_cmd_state *state = &cmd_buffer->state;
3860
3861 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3862 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3863
3864 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3865 image->offset + image->dcc_offset,
3866 image->surface.dcc_size, value);
3867
3868 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3869 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3870 }
3871
3872 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3873 struct radv_image *image,
3874 VkImageLayout src_layout,
3875 VkImageLayout dst_layout,
3876 unsigned src_queue_mask,
3877 unsigned dst_queue_mask,
3878 const VkImageSubresourceRange *range)
3879 {
3880 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3881 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3882 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3883 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3884 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3885 }
3886 }
3887
3888 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3889 struct radv_image *image,
3890 VkImageLayout src_layout,
3891 VkImageLayout dst_layout,
3892 uint32_t src_family,
3893 uint32_t dst_family,
3894 const VkImageSubresourceRange *range,
3895 VkImageAspectFlags pending_clears)
3896 {
3897 if (image->exclusive && src_family != dst_family) {
3898 /* This is an acquire or a release operation and there will be
3899 * a corresponding release/acquire. Do the transition in the
3900 * most flexible queue. */
3901
3902 assert(src_family == cmd_buffer->queue_family_index ||
3903 dst_family == cmd_buffer->queue_family_index);
3904
3905 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3906 return;
3907
3908 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3909 (src_family == RADV_QUEUE_GENERAL ||
3910 dst_family == RADV_QUEUE_GENERAL))
3911 return;
3912 }
3913
3914 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3915 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3916
3917 if (image->surface.htile_size)
3918 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3919 dst_layout, src_queue_mask,
3920 dst_queue_mask, range,
3921 pending_clears);
3922
3923 if (image->cmask.size || image->fmask.size)
3924 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3925 dst_layout, src_queue_mask,
3926 dst_queue_mask, range);
3927
3928 if (image->surface.dcc_size)
3929 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3930 dst_layout, src_queue_mask,
3931 dst_queue_mask, range);
3932 }
3933
3934 void radv_CmdPipelineBarrier(
3935 VkCommandBuffer commandBuffer,
3936 VkPipelineStageFlags srcStageMask,
3937 VkPipelineStageFlags destStageMask,
3938 VkBool32 byRegion,
3939 uint32_t memoryBarrierCount,
3940 const VkMemoryBarrier* pMemoryBarriers,
3941 uint32_t bufferMemoryBarrierCount,
3942 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3943 uint32_t imageMemoryBarrierCount,
3944 const VkImageMemoryBarrier* pImageMemoryBarriers)
3945 {
3946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3947 enum radv_cmd_flush_bits src_flush_bits = 0;
3948 enum radv_cmd_flush_bits dst_flush_bits = 0;
3949
3950 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3951 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3952 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3953 NULL);
3954 }
3955
3956 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3957 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3958 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3959 NULL);
3960 }
3961
3962 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3963 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3964 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3965 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3966 image);
3967 }
3968
3969 radv_stage_flush(cmd_buffer, srcStageMask);
3970 cmd_buffer->state.flush_bits |= src_flush_bits;
3971
3972 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3973 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3974 radv_handle_image_transition(cmd_buffer, image,
3975 pImageMemoryBarriers[i].oldLayout,
3976 pImageMemoryBarriers[i].newLayout,
3977 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3978 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3979 &pImageMemoryBarriers[i].subresourceRange,
3980 0);
3981 }
3982
3983 cmd_buffer->state.flush_bits |= dst_flush_bits;
3984 }
3985
3986
3987 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3988 struct radv_event *event,
3989 VkPipelineStageFlags stageMask,
3990 unsigned value)
3991 {
3992 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3993 uint64_t va = radv_buffer_get_va(event->bo);
3994
3995 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3996
3997 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3998
3999 /* TODO: this is overkill. Probably should figure something out from
4000 * the stage mask. */
4001
4002 si_cs_emit_write_event_eop(cs,
4003 cmd_buffer->state.predicating,
4004 cmd_buffer->device->physical_device->rad_info.chip_class,
4005 false,
4006 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4007 1, va, 2, value);
4008
4009 assert(cmd_buffer->cs->cdw <= cdw_max);
4010 }
4011
4012 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4013 VkEvent _event,
4014 VkPipelineStageFlags stageMask)
4015 {
4016 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4017 RADV_FROM_HANDLE(radv_event, event, _event);
4018
4019 write_event(cmd_buffer, event, stageMask, 1);
4020 }
4021
4022 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4023 VkEvent _event,
4024 VkPipelineStageFlags stageMask)
4025 {
4026 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4027 RADV_FROM_HANDLE(radv_event, event, _event);
4028
4029 write_event(cmd_buffer, event, stageMask, 0);
4030 }
4031
4032 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4033 uint32_t eventCount,
4034 const VkEvent* pEvents,
4035 VkPipelineStageFlags srcStageMask,
4036 VkPipelineStageFlags dstStageMask,
4037 uint32_t memoryBarrierCount,
4038 const VkMemoryBarrier* pMemoryBarriers,
4039 uint32_t bufferMemoryBarrierCount,
4040 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4041 uint32_t imageMemoryBarrierCount,
4042 const VkImageMemoryBarrier* pImageMemoryBarriers)
4043 {
4044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4045 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4046
4047 for (unsigned i = 0; i < eventCount; ++i) {
4048 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4049 uint64_t va = radv_buffer_get_va(event->bo);
4050
4051 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4052
4053 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4054
4055 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4056 assert(cmd_buffer->cs->cdw <= cdw_max);
4057 }
4058
4059
4060 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4061 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4062
4063 radv_handle_image_transition(cmd_buffer, image,
4064 pImageMemoryBarriers[i].oldLayout,
4065 pImageMemoryBarriers[i].newLayout,
4066 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4067 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4068 &pImageMemoryBarriers[i].subresourceRange,
4069 0);
4070 }
4071
4072 /* TODO: figure out how to do memory barriers without waiting */
4073 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4074 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4075 RADV_CMD_FLAG_INV_VMEM_L1 |
4076 RADV_CMD_FLAG_INV_SMEM_L1;
4077 }