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radv: Remove remaining hard coded references to VS.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 if (stage == MESA_SHADER_VERTEX) {
497 if (pipeline->shaders[MESA_SHADER_VERTEX])
498 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
499 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
500 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
501 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
502 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
503 }
504 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
505 }
506
507 static void
508 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
509 struct radv_pipeline *pipeline,
510 gl_shader_stage stage,
511 int idx, uint64_t va)
512 {
513 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
514 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
515 if (loc->sgpr_idx == -1)
516 return;
517 assert(loc->num_sgprs == 2);
518 assert(!loc->indirect);
519 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
520 radeon_emit(cmd_buffer->cs, va);
521 radeon_emit(cmd_buffer->cs, va >> 32);
522 }
523
524 static void
525 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
526 struct radv_pipeline *pipeline)
527 {
528 int num_samples = pipeline->graphics.ms.num_samples;
529 struct radv_multisample_state *ms = &pipeline->graphics.ms;
530 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
531
532 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
533 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
534 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
535
536 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
537 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
538
539 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
540 return;
541
542 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
543 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
544 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
545
546 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
547
548 /* GFX9: Flush DFSM when the AA mode changes. */
549 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
550 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
551 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
552 }
553 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
554 uint32_t offset;
555 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
556 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
557 if (loc->sgpr_idx == -1)
558 return;
559 assert(loc->num_sgprs == 1);
560 assert(!loc->indirect);
561 switch (num_samples) {
562 default:
563 offset = 0;
564 break;
565 case 2:
566 offset = 1;
567 break;
568 case 4:
569 offset = 3;
570 break;
571 case 8:
572 offset = 7;
573 break;
574 case 16:
575 offset = 15;
576 break;
577 }
578
579 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
580 cmd_buffer->sample_positions_needed = true;
581 }
582 }
583
584 static void
585 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline)
587 {
588 struct radv_raster_state *raster = &pipeline->graphics.raster;
589
590 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
591 raster->pa_cl_clip_cntl);
592 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
593 raster->spi_interp_control);
594 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
595 raster->pa_su_vtx_cntl);
596 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
597 raster->pa_su_sc_mode_cntl);
598 }
599
600 static inline void
601 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
602 unsigned size)
603 {
604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
605 si_cp_dma_prefetch(cmd_buffer, va, size);
606 }
607
608 static void
609 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_pipeline *pipeline,
611 struct radv_shader_variant *shader,
612 struct ac_vs_output_info *outinfo)
613 {
614 struct radeon_winsys *ws = cmd_buffer->device->ws;
615 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
616 unsigned export_count;
617
618 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
619 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
620
621 export_count = MAX2(1, outinfo->param_exports);
622 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
623 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
624
625 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
626 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
627 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
628 V_02870C_SPI_SHADER_4COMP :
629 V_02870C_SPI_SHADER_NONE) |
630 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
631 V_02870C_SPI_SHADER_4COMP :
632 V_02870C_SPI_SHADER_NONE) |
633 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
634 V_02870C_SPI_SHADER_4COMP :
635 V_02870C_SPI_SHADER_NONE));
636
637
638 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
639 radeon_emit(cmd_buffer->cs, va >> 8);
640 radeon_emit(cmd_buffer->cs, va >> 40);
641 radeon_emit(cmd_buffer->cs, shader->rsrc1);
642 radeon_emit(cmd_buffer->cs, shader->rsrc2);
643
644 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
645 S_028818_VTX_W0_FMT(1) |
646 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
647 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
648 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
649
650
651 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
652 pipeline->graphics.pa_cl_vs_out_cntl);
653
654 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
655 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
656 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
657 }
658
659 static void
660 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
661 struct radv_shader_variant *shader,
662 struct ac_es_output_info *outinfo)
663 {
664 struct radeon_winsys *ws = cmd_buffer->device->ws;
665 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
668 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
669
670 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
671 outinfo->esgs_itemsize / 4);
672 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
673 radeon_emit(cmd_buffer->cs, va >> 8);
674 radeon_emit(cmd_buffer->cs, va >> 40);
675 radeon_emit(cmd_buffer->cs, shader->rsrc1);
676 radeon_emit(cmd_buffer->cs, shader->rsrc2);
677 }
678
679 static void
680 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
681 struct radv_shader_variant *shader)
682 {
683 struct radeon_winsys *ws = cmd_buffer->device->ws;
684 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
685 uint32_t rsrc2 = shader->rsrc2;
686
687 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
688 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
689
690 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
691 radeon_emit(cmd_buffer->cs, va >> 8);
692 radeon_emit(cmd_buffer->cs, va >> 40);
693
694 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
695 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
696 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
697 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
698
699 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
700 radeon_emit(cmd_buffer->cs, shader->rsrc1);
701 radeon_emit(cmd_buffer->cs, rsrc2);
702 }
703
704 static void
705 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
706 struct radv_shader_variant *shader)
707 {
708 struct radeon_winsys *ws = cmd_buffer->device->ws;
709 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
710
711 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
712 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
713
714 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
715 radeon_emit(cmd_buffer->cs, va >> 8);
716 radeon_emit(cmd_buffer->cs, va >> 40);
717 radeon_emit(cmd_buffer->cs, shader->rsrc1);
718 radeon_emit(cmd_buffer->cs, shader->rsrc2);
719 }
720
721 static void
722 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
723 struct radv_pipeline *pipeline)
724 {
725 struct radv_shader_variant *vs;
726
727 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
728
729 /* Skip shaders merged into HS/GS */
730 vs = pipeline->shaders[MESA_SHADER_VERTEX];
731 if (!vs)
732 return;
733
734 if (vs->info.vs.as_ls)
735 radv_emit_hw_ls(cmd_buffer, vs);
736 else if (vs->info.vs.as_es)
737 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
738 else
739 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
740 }
741
742
743 static void
744 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_pipeline *pipeline)
746 {
747 if (!radv_pipeline_has_tess(pipeline))
748 return;
749
750 struct radv_shader_variant *tes, *tcs;
751
752 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
753 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
754
755 if (tes->info.tes.as_es)
756 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
757 else
758 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
759
760 radv_emit_hw_hs(cmd_buffer, tcs);
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
763 pipeline->graphics.tess.tf_param);
764
765 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
766 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
767 pipeline->graphics.tess.ls_hs_config);
768 else
769 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
770 pipeline->graphics.tess.ls_hs_config);
771
772 struct ac_userdata_info *loc;
773
774 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
775 if (loc->sgpr_idx != -1) {
776 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
777 assert(loc->num_sgprs == 4);
778 assert(!loc->indirect);
779 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
780 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
781 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
782 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
783 pipeline->graphics.tess.num_tcs_input_cp << 26);
784 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
785 }
786
787 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
788 if (loc->sgpr_idx != -1) {
789 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
790 assert(loc->num_sgprs == 1);
791 assert(!loc->indirect);
792
793 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
794 pipeline->graphics.tess.offchip_layout);
795 }
796
797 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
798 if (loc->sgpr_idx != -1) {
799 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
800 assert(loc->num_sgprs == 1);
801 assert(!loc->indirect);
802
803 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
804 pipeline->graphics.tess.tcs_in_layout);
805 }
806 }
807
808 static void
809 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
810 struct radv_pipeline *pipeline)
811 {
812 struct radeon_winsys *ws = cmd_buffer->device->ws;
813 struct radv_shader_variant *gs;
814 uint64_t va;
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
817
818 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
819 if (!gs)
820 return;
821
822 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
823
824 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
825 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
826 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
827 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
828
829 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
830
831 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
832
833 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
834 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
835 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
836 radeon_emit(cmd_buffer->cs, 0);
837 radeon_emit(cmd_buffer->cs, 0);
838 radeon_emit(cmd_buffer->cs, 0);
839
840 uint32_t gs_num_invocations = gs->info.gs.invocations;
841 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
842 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
843 S_028B90_ENABLE(gs_num_invocations > 0));
844
845 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
846 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
847 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
848
849 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
850 radeon_emit(cmd_buffer->cs, va >> 8);
851 radeon_emit(cmd_buffer->cs, va >> 40);
852 radeon_emit(cmd_buffer->cs, gs->rsrc1);
853 radeon_emit(cmd_buffer->cs, gs->rsrc2);
854
855 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
856
857 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
858 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
859 if (loc->sgpr_idx != -1) {
860 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
861 uint32_t num_entries = 64;
862 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
863
864 if (is_vi)
865 num_entries *= stride;
866
867 stride = S_008F04_STRIDE(stride);
868 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
869 radeon_emit(cmd_buffer->cs, stride);
870 radeon_emit(cmd_buffer->cs, num_entries);
871 }
872 }
873
874 static void
875 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
876 struct radv_pipeline *pipeline)
877 {
878 struct radeon_winsys *ws = cmd_buffer->device->ws;
879 struct radv_shader_variant *ps;
880 uint64_t va;
881 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
882 struct radv_blend_state *blend = &pipeline->graphics.blend;
883 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
884
885 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
886 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
887 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
888 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
889
890 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
891 radeon_emit(cmd_buffer->cs, va >> 8);
892 radeon_emit(cmd_buffer->cs, va >> 40);
893 radeon_emit(cmd_buffer->cs, ps->rsrc1);
894 radeon_emit(cmd_buffer->cs, ps->rsrc2);
895
896 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
897 pipeline->graphics.db_shader_control);
898
899 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
900 ps->config.spi_ps_input_ena);
901
902 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
903 ps->config.spi_ps_input_addr);
904
905 if (ps->info.info.ps.force_persample)
906 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
907
908 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
909 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
910
911 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
914 pipeline->graphics.shader_z_format);
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
917
918 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
919 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
922 /* optimise this? */
923 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
924 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
925 }
926
927 if (pipeline->graphics.ps_input_cntl_num) {
928 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
929 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
930 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
931 }
932 }
933 }
934
935 static void
936 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
937 struct radv_pipeline *pipeline)
938 {
939 struct radeon_winsys_cs *cs = cmd_buffer->cs;
940
941 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
942 return;
943
944 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
945 pipeline->graphics.vtx_reuse_depth);
946 }
947
948 static void
949 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
950 {
951 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
952
953 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
954 return;
955
956 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
957 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
958 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
959 radv_update_multisample_state(cmd_buffer, pipeline);
960 radv_emit_vertex_shader(cmd_buffer, pipeline);
961 radv_emit_tess_shaders(cmd_buffer, pipeline);
962 radv_emit_geometry_shader(cmd_buffer, pipeline);
963 radv_emit_fragment_shader(cmd_buffer, pipeline);
964 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
965
966 cmd_buffer->scratch_size_needed =
967 MAX2(cmd_buffer->scratch_size_needed,
968 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
969
970 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
971 S_0286E8_WAVES(pipeline->max_waves) |
972 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
973
974 if (!cmd_buffer->state.emitted_pipeline ||
975 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
976 pipeline->graphics.can_use_guardband)
977 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
978
979 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
980
981 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
982 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
983 } else {
984 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
985 }
986 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
987
988 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
989
990 cmd_buffer->state.emitted_pipeline = pipeline;
991 }
992
993 static void
994 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
995 {
996 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
997 cmd_buffer->state.dynamic.viewport.viewports);
998 }
999
1000 static void
1001 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1002 {
1003 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1004
1005 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1006 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1007 si_emit_cache_flush(cmd_buffer);
1008 }
1009 si_write_scissors(cmd_buffer->cs, 0, count,
1010 cmd_buffer->state.dynamic.scissor.scissors,
1011 cmd_buffer->state.dynamic.viewport.viewports,
1012 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1013 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1014 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1015 }
1016
1017 static void
1018 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1019 {
1020 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1021
1022 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1023 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1024 }
1025
1026 static void
1027 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1028 {
1029 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1030
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1032 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1033 }
1034
1035 static void
1036 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1037 {
1038 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs,
1041 R_028430_DB_STENCILREFMASK, 2);
1042 radeon_emit(cmd_buffer->cs,
1043 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1044 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1045 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1046 S_028430_STENCILOPVAL(1));
1047 radeon_emit(cmd_buffer->cs,
1048 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1049 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1050 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1051 S_028434_STENCILOPVAL_BF(1));
1052 }
1053
1054 static void
1055 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1056 {
1057 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1058
1059 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1060 fui(d->depth_bounds.min));
1061 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1062 fui(d->depth_bounds.max));
1063 }
1064
1065 static void
1066 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1067 {
1068 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1069 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1070 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1071 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1072
1073 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1074 radeon_set_context_reg_seq(cmd_buffer->cs,
1075 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1076 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1077 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1078 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1079 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1080 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1081 }
1082 }
1083
1084 static void
1085 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1086 int index,
1087 struct radv_color_buffer_info *cb)
1088 {
1089 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1090
1091 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1092 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1093 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1094 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1095 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1096 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1097 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1098 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1099 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1100 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1101 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1102 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1103 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1104
1105 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1106 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1107 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1108
1109 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1110 cb->gfx9_epitch);
1111 } else {
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1115 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1116 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1117 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1118 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1119 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1120 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1121 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1122 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1123 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1124
1125 if (is_vi) { /* DCC BASE */
1126 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1127 }
1128 }
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1190 ds->pa_su_poly_offset_db_fmt_cntl);
1191 }
1192
1193 void
1194 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1195 struct radv_image *image,
1196 VkClearDepthStencilValue ds_clear_value,
1197 VkImageAspectFlags aspects)
1198 {
1199 uint64_t va = radv_buffer_get_va(image->bo);
1200 va += image->offset + image->clear_value_offset;
1201 unsigned reg_offset = 0, reg_count = 0;
1202
1203 if (!image->surface.htile_size || !aspects)
1204 return;
1205
1206 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1207 ++reg_count;
1208 } else {
1209 ++reg_offset;
1210 va += 4;
1211 }
1212 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1213 ++reg_count;
1214
1215 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1216
1217 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1218 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1219 S_370_WR_CONFIRM(1) |
1220 S_370_ENGINE_SEL(V_370_PFP));
1221 radeon_emit(cmd_buffer->cs, va);
1222 radeon_emit(cmd_buffer->cs, va >> 32);
1223 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1224 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1225 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1226 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1227
1228 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1229 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1230 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1231 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1232 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1233 }
1234
1235 static void
1236 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1237 struct radv_image *image)
1238 {
1239 uint64_t va = radv_buffer_get_va(image->bo);
1240 va += image->offset + image->clear_value_offset;
1241
1242 if (!image->surface.htile_size)
1243 return;
1244
1245 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1246
1247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1248 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1249 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1250 COPY_DATA_COUNT_SEL);
1251 radeon_emit(cmd_buffer->cs, va);
1252 radeon_emit(cmd_buffer->cs, va >> 32);
1253 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1254 radeon_emit(cmd_buffer->cs, 0);
1255
1256 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1257 radeon_emit(cmd_buffer->cs, 0);
1258 }
1259
1260 /*
1261 *with DCC some colors don't require CMASK elimiation before being
1262 * used as a texture. This sets a predicate value to determine if the
1263 * cmask eliminate is required.
1264 */
1265 void
1266 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1267 struct radv_image *image,
1268 bool value)
1269 {
1270 uint64_t pred_val = value;
1271 uint64_t va = radv_buffer_get_va(image->bo);
1272 va += image->offset + image->dcc_pred_offset;
1273
1274 if (!image->surface.dcc_size)
1275 return;
1276
1277 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1278
1279 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1280 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1281 S_370_WR_CONFIRM(1) |
1282 S_370_ENGINE_SEL(V_370_PFP));
1283 radeon_emit(cmd_buffer->cs, va);
1284 radeon_emit(cmd_buffer->cs, va >> 32);
1285 radeon_emit(cmd_buffer->cs, pred_val);
1286 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1287 }
1288
1289 void
1290 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1291 struct radv_image *image,
1292 int idx,
1293 uint32_t color_values[2])
1294 {
1295 uint64_t va = radv_buffer_get_va(image->bo);
1296 va += image->offset + image->clear_value_offset;
1297
1298 if (!image->cmask.size && !image->surface.dcc_size)
1299 return;
1300
1301 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1302
1303 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1304 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1305 S_370_WR_CONFIRM(1) |
1306 S_370_ENGINE_SEL(V_370_PFP));
1307 radeon_emit(cmd_buffer->cs, va);
1308 radeon_emit(cmd_buffer->cs, va >> 32);
1309 radeon_emit(cmd_buffer->cs, color_values[0]);
1310 radeon_emit(cmd_buffer->cs, color_values[1]);
1311
1312 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1313 radeon_emit(cmd_buffer->cs, color_values[0]);
1314 radeon_emit(cmd_buffer->cs, color_values[1]);
1315 }
1316
1317 static void
1318 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 int idx)
1321 {
1322 uint64_t va = radv_buffer_get_va(image->bo);
1323 va += image->offset + image->clear_value_offset;
1324
1325 if (!image->cmask.size && !image->surface.dcc_size)
1326 return;
1327
1328 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1329 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1330
1331 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1332 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1333 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1334 COPY_DATA_COUNT_SEL);
1335 radeon_emit(cmd_buffer->cs, va);
1336 radeon_emit(cmd_buffer->cs, va >> 32);
1337 radeon_emit(cmd_buffer->cs, reg >> 2);
1338 radeon_emit(cmd_buffer->cs, 0);
1339
1340 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1341 radeon_emit(cmd_buffer->cs, 0);
1342 }
1343
1344 void
1345 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1346 {
1347 int i;
1348 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1349 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1350
1351 /* this may happen for inherited secondary recording */
1352 if (!framebuffer)
1353 return;
1354
1355 for (i = 0; i < 8; ++i) {
1356 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1357 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1358 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1359 continue;
1360 }
1361
1362 int idx = subpass->color_attachments[i].attachment;
1363 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1364
1365 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1366
1367 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1368 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1369
1370 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1371 }
1372
1373 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1374 int idx = subpass->depth_stencil_attachment.attachment;
1375 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1376 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1377 struct radv_image *image = att->attachment->image;
1378 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1379 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1380 cmd_buffer->queue_family_index,
1381 cmd_buffer->queue_family_index);
1382 /* We currently don't support writing decompressed HTILE */
1383 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1384 radv_layout_is_htile_compressed(image, layout, queue_mask));
1385
1386 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1387
1388 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1390 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1391 }
1392 radv_load_depth_clear_regs(cmd_buffer, image);
1393 } else {
1394 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1396 else
1397 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1398
1399 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1400 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1401 }
1402 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1403 S_028208_BR_X(framebuffer->width) |
1404 S_028208_BR_Y(framebuffer->height));
1405
1406 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1407 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1408 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1409 }
1410 }
1411
1412 static void
1413 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1414 {
1415 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1416
1417 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1418 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1419 2, cmd_buffer->state.index_type);
1420 } else {
1421 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1422 radeon_emit(cs, cmd_buffer->state.index_type);
1423 }
1424
1425 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1426 radeon_emit(cs, cmd_buffer->state.index_va);
1427 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1428
1429 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1430 radeon_emit(cs, cmd_buffer->state.max_index_count);
1431 }
1432
1433 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1434 {
1435 uint32_t db_count_control;
1436
1437 if(!cmd_buffer->state.active_occlusion_queries) {
1438 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1439 db_count_control = 0;
1440 } else {
1441 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1442 }
1443 } else {
1444 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1445 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1446 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1447 S_028004_ZPASS_ENABLE(1) |
1448 S_028004_SLICE_EVEN_ENABLE(1) |
1449 S_028004_SLICE_ODD_ENABLE(1);
1450 } else {
1451 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1452 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1453 }
1454 }
1455
1456 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1457 }
1458
1459 static void
1460 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1461 {
1462 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1463 return;
1464
1465 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1466 radv_emit_viewport(cmd_buffer);
1467
1468 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1469 radv_emit_scissor(cmd_buffer);
1470
1471 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1472 radv_emit_line_width(cmd_buffer);
1473
1474 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1475 radv_emit_blend_constants(cmd_buffer);
1476
1477 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1478 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1479 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1480 radv_emit_stencil(cmd_buffer);
1481
1482 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1483 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1484 radv_emit_depth_bounds(cmd_buffer);
1485
1486 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1487 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1488 radv_emit_depth_biais(cmd_buffer);
1489 }
1490
1491 static void
1492 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1493 struct radv_pipeline *pipeline,
1494 int idx,
1495 uint64_t va,
1496 gl_shader_stage stage)
1497 {
1498 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1499 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1500
1501 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1502 return;
1503
1504 assert(!desc_set_loc->indirect);
1505 assert(desc_set_loc->num_sgprs == 2);
1506 radeon_set_sh_reg_seq(cmd_buffer->cs,
1507 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1508 radeon_emit(cmd_buffer->cs, va);
1509 radeon_emit(cmd_buffer->cs, va >> 32);
1510 }
1511
1512 static void
1513 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1514 VkShaderStageFlags stages,
1515 struct radv_descriptor_set *set,
1516 unsigned idx)
1517 {
1518 if (cmd_buffer->state.pipeline) {
1519 radv_foreach_stage(stage, stages) {
1520 if (cmd_buffer->state.pipeline->shaders[stage])
1521 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1522 idx, set->va,
1523 stage);
1524 }
1525 }
1526
1527 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1528 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1529 idx, set->va,
1530 MESA_SHADER_COMPUTE);
1531 }
1532
1533 static void
1534 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1535 {
1536 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1537 unsigned bo_offset;
1538
1539 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1540 set->mapped_ptr,
1541 &bo_offset))
1542 return;
1543
1544 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1545 set->va += bo_offset;
1546 }
1547
1548 static void
1549 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1550 {
1551 uint32_t size = MAX_SETS * 2 * 4;
1552 uint32_t offset;
1553 void *ptr;
1554
1555 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1556 256, &offset, &ptr))
1557 return;
1558
1559 for (unsigned i = 0; i < MAX_SETS; i++) {
1560 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1561 uint64_t set_va = 0;
1562 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1563 if (set)
1564 set_va = set->va;
1565 uptr[0] = set_va & 0xffffffff;
1566 uptr[1] = set_va >> 32;
1567 }
1568
1569 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1570 va += offset;
1571
1572 if (cmd_buffer->state.pipeline) {
1573 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1574 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1575 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1576
1577 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1578 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1579 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1580
1581 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1582 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1583 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1584
1585 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1586 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1587 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1588
1589 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1590 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1591 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1592 }
1593
1594 if (cmd_buffer->state.compute_pipeline)
1595 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1596 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1597 }
1598
1599 static void
1600 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1601 VkShaderStageFlags stages)
1602 {
1603 unsigned i;
1604
1605 if (!cmd_buffer->state.descriptors_dirty)
1606 return;
1607
1608 if (cmd_buffer->state.push_descriptors_dirty)
1609 radv_flush_push_descriptors(cmd_buffer);
1610
1611 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1612 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1613 radv_flush_indirect_descriptor_sets(cmd_buffer);
1614 }
1615
1616 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1617 cmd_buffer->cs,
1618 MAX_SETS * MESA_SHADER_STAGES * 4);
1619
1620 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1621 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1622 if (!set)
1623 continue;
1624
1625 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1626 }
1627 cmd_buffer->state.descriptors_dirty = 0;
1628 cmd_buffer->state.push_descriptors_dirty = false;
1629
1630 radv_save_descriptors(cmd_buffer);
1631
1632 assert(cmd_buffer->cs->cdw <= cdw_max);
1633 }
1634
1635 static void
1636 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1637 struct radv_pipeline *pipeline,
1638 VkShaderStageFlags stages)
1639 {
1640 struct radv_pipeline_layout *layout = pipeline->layout;
1641 unsigned offset;
1642 void *ptr;
1643 uint64_t va;
1644
1645 stages &= cmd_buffer->push_constant_stages;
1646 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1647 return;
1648
1649 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1650 16 * layout->dynamic_offset_count,
1651 256, &offset, &ptr))
1652 return;
1653
1654 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1655 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1656 16 * layout->dynamic_offset_count);
1657
1658 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1659 va += offset;
1660
1661 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1662 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1663
1664 radv_foreach_stage(stage, stages) {
1665 if (pipeline->shaders[stage]) {
1666 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1667 AC_UD_PUSH_CONSTANTS, va);
1668 }
1669 }
1670
1671 cmd_buffer->push_constant_stages &= ~stages;
1672 assert(cmd_buffer->cs->cdw <= cdw_max);
1673 }
1674
1675 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1676 bool indexed_draw)
1677 {
1678 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1679
1680 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1681 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1682 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1683 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1684 primitive_reset_en);
1685 } else {
1686 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1687 primitive_reset_en);
1688 }
1689 }
1690
1691 if (primitive_reset_en) {
1692 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1693
1694 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1695 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1696 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1697 primitive_reset_index);
1698 }
1699 }
1700 }
1701
1702 static bool
1703 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1704 {
1705 struct radv_device *device = cmd_buffer->device;
1706
1707 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1708 cmd_buffer->state.pipeline->vertex_elements.count &&
1709 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1710 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1711 unsigned vb_offset;
1712 void *vb_ptr;
1713 uint32_t i = 0;
1714 uint32_t count = velems->count;
1715 uint64_t va;
1716
1717 /* allocate some descriptor state for vertex buffers */
1718 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1719 &vb_offset, &vb_ptr))
1720 return false;
1721
1722 for (i = 0; i < count; i++) {
1723 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1724 uint32_t offset;
1725 int vb = velems->binding[i];
1726 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1727 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1728
1729 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1730 va = radv_buffer_get_va(buffer->bo);
1731
1732 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1733 va += offset + buffer->offset;
1734 desc[0] = va;
1735 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1736 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1737 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1738 else
1739 desc[2] = buffer->size - offset;
1740 desc[3] = velems->rsrc_word3[i];
1741 }
1742
1743 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1744 va += vb_offset;
1745
1746 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1747 AC_UD_VS_VERTEX_BUFFERS, va);
1748 }
1749 cmd_buffer->state.vb_dirty = false;
1750
1751 return true;
1752 }
1753
1754 static void
1755 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1756 bool indexed_draw, bool instanced_draw,
1757 bool indirect_draw,
1758 uint32_t draw_vertex_count)
1759 {
1760 uint32_t ia_multi_vgt_param;
1761
1762 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1763 cmd_buffer->cs, 4096);
1764
1765 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1766 return;
1767
1768 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1769 radv_emit_graphics_pipeline(cmd_buffer);
1770
1771 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1772 radv_emit_framebuffer_state(cmd_buffer);
1773
1774 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
1775 radv_emit_index_buffer(cmd_buffer);
1776
1777 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1778 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1779 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1780 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1781 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1782 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1783 else
1784 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1785 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1786 }
1787
1788 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1789
1790 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1791
1792 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1793 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1794 VK_SHADER_STAGE_ALL_GRAPHICS);
1795
1796 assert(cmd_buffer->cs->cdw <= cdw_max);
1797
1798 si_emit_cache_flush(cmd_buffer);
1799
1800 cmd_buffer->state.dirty = 0;
1801 }
1802
1803 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1804 VkPipelineStageFlags src_stage_mask)
1805 {
1806 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1807 VK_PIPELINE_STAGE_TRANSFER_BIT |
1808 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1809 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1810 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1811 }
1812
1813 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1814 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1815 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1816 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1817 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1818 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1819 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1820 VK_PIPELINE_STAGE_TRANSFER_BIT |
1821 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1822 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1823 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1824 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1825 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1826 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1827 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1828 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1829 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1830 }
1831 }
1832
1833 static enum radv_cmd_flush_bits
1834 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1835 VkAccessFlags src_flags)
1836 {
1837 enum radv_cmd_flush_bits flush_bits = 0;
1838 uint32_t b;
1839 for_each_bit(b, src_flags) {
1840 switch ((VkAccessFlagBits)(1 << b)) {
1841 case VK_ACCESS_SHADER_WRITE_BIT:
1842 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1843 break;
1844 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1845 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1846 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1847 break;
1848 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1849 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1850 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1851 break;
1852 case VK_ACCESS_TRANSFER_WRITE_BIT:
1853 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1854 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1855 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1856 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1857 RADV_CMD_FLAG_INV_GLOBAL_L2;
1858 break;
1859 default:
1860 break;
1861 }
1862 }
1863 return flush_bits;
1864 }
1865
1866 static enum radv_cmd_flush_bits
1867 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1868 VkAccessFlags dst_flags,
1869 struct radv_image *image)
1870 {
1871 enum radv_cmd_flush_bits flush_bits = 0;
1872 uint32_t b;
1873 for_each_bit(b, dst_flags) {
1874 switch ((VkAccessFlagBits)(1 << b)) {
1875 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1876 case VK_ACCESS_INDEX_READ_BIT:
1877 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1878 break;
1879 case VK_ACCESS_UNIFORM_READ_BIT:
1880 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1881 break;
1882 case VK_ACCESS_SHADER_READ_BIT:
1883 case VK_ACCESS_TRANSFER_READ_BIT:
1884 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1885 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1886 RADV_CMD_FLAG_INV_GLOBAL_L2;
1887 break;
1888 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1889 /* TODO: change to image && when the image gets passed
1890 * through from the subpass. */
1891 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1892 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1893 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1894 break;
1895 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1896 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1897 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1898 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1899 break;
1900 default:
1901 break;
1902 }
1903 }
1904 return flush_bits;
1905 }
1906
1907 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1908 {
1909 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1910 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1911 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1912 NULL);
1913 }
1914
1915 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1916 VkAttachmentReference att)
1917 {
1918 unsigned idx = att.attachment;
1919 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1920 VkImageSubresourceRange range;
1921 range.aspectMask = 0;
1922 range.baseMipLevel = view->base_mip;
1923 range.levelCount = 1;
1924 range.baseArrayLayer = view->base_layer;
1925 range.layerCount = cmd_buffer->state.framebuffer->layers;
1926
1927 radv_handle_image_transition(cmd_buffer,
1928 view->image,
1929 cmd_buffer->state.attachments[idx].current_layout,
1930 att.layout, 0, 0, &range,
1931 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1932
1933 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1934
1935
1936 }
1937
1938 void
1939 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1940 const struct radv_subpass *subpass, bool transitions)
1941 {
1942 if (transitions) {
1943 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1944
1945 for (unsigned i = 0; i < subpass->color_count; ++i) {
1946 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1947 radv_handle_subpass_image_transition(cmd_buffer,
1948 subpass->color_attachments[i]);
1949 }
1950
1951 for (unsigned i = 0; i < subpass->input_count; ++i) {
1952 radv_handle_subpass_image_transition(cmd_buffer,
1953 subpass->input_attachments[i]);
1954 }
1955
1956 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1957 radv_handle_subpass_image_transition(cmd_buffer,
1958 subpass->depth_stencil_attachment);
1959 }
1960 }
1961
1962 cmd_buffer->state.subpass = subpass;
1963
1964 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1965 }
1966
1967 static VkResult
1968 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1969 struct radv_render_pass *pass,
1970 const VkRenderPassBeginInfo *info)
1971 {
1972 struct radv_cmd_state *state = &cmd_buffer->state;
1973
1974 if (pass->attachment_count == 0) {
1975 state->attachments = NULL;
1976 return VK_SUCCESS;
1977 }
1978
1979 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1980 pass->attachment_count *
1981 sizeof(state->attachments[0]),
1982 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1983 if (state->attachments == NULL) {
1984 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1985 return cmd_buffer->record_result;
1986 }
1987
1988 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1989 struct radv_render_pass_attachment *att = &pass->attachments[i];
1990 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1991 VkImageAspectFlags clear_aspects = 0;
1992
1993 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1994 /* color attachment */
1995 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1996 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1997 }
1998 } else {
1999 /* depthstencil attachment */
2000 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2001 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2002 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2003 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2004 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2005 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2006 }
2007 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2008 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2009 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2010 }
2011 }
2012
2013 state->attachments[i].pending_clear_aspects = clear_aspects;
2014 state->attachments[i].cleared_views = 0;
2015 if (clear_aspects && info) {
2016 assert(info->clearValueCount > i);
2017 state->attachments[i].clear_value = info->pClearValues[i];
2018 }
2019
2020 state->attachments[i].current_layout = att->initial_layout;
2021 }
2022
2023 return VK_SUCCESS;
2024 }
2025
2026 VkResult radv_AllocateCommandBuffers(
2027 VkDevice _device,
2028 const VkCommandBufferAllocateInfo *pAllocateInfo,
2029 VkCommandBuffer *pCommandBuffers)
2030 {
2031 RADV_FROM_HANDLE(radv_device, device, _device);
2032 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2033
2034 VkResult result = VK_SUCCESS;
2035 uint32_t i;
2036
2037 memset(pCommandBuffers, 0,
2038 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2039
2040 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2041
2042 if (!list_empty(&pool->free_cmd_buffers)) {
2043 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2044
2045 list_del(&cmd_buffer->pool_link);
2046 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2047
2048 result = radv_reset_cmd_buffer(cmd_buffer);
2049 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2050 cmd_buffer->level = pAllocateInfo->level;
2051
2052 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2053 } else {
2054 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2055 &pCommandBuffers[i]);
2056 }
2057 if (result != VK_SUCCESS)
2058 break;
2059 }
2060
2061 if (result != VK_SUCCESS)
2062 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2063 i, pCommandBuffers);
2064
2065 return result;
2066 }
2067
2068 void radv_FreeCommandBuffers(
2069 VkDevice device,
2070 VkCommandPool commandPool,
2071 uint32_t commandBufferCount,
2072 const VkCommandBuffer *pCommandBuffers)
2073 {
2074 for (uint32_t i = 0; i < commandBufferCount; i++) {
2075 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2076
2077 if (cmd_buffer) {
2078 if (cmd_buffer->pool) {
2079 list_del(&cmd_buffer->pool_link);
2080 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2081 } else
2082 radv_cmd_buffer_destroy(cmd_buffer);
2083
2084 }
2085 }
2086 }
2087
2088 VkResult radv_ResetCommandBuffer(
2089 VkCommandBuffer commandBuffer,
2090 VkCommandBufferResetFlags flags)
2091 {
2092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2093 return radv_reset_cmd_buffer(cmd_buffer);
2094 }
2095
2096 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2097 {
2098 struct radv_device *device = cmd_buffer->device;
2099 if (device->gfx_init) {
2100 uint64_t va = radv_buffer_get_va(device->gfx_init);
2101 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2102 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2103 radeon_emit(cmd_buffer->cs, va);
2104 radeon_emit(cmd_buffer->cs, va >> 32);
2105 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2106 } else
2107 si_init_config(cmd_buffer);
2108 }
2109
2110 VkResult radv_BeginCommandBuffer(
2111 VkCommandBuffer commandBuffer,
2112 const VkCommandBufferBeginInfo *pBeginInfo)
2113 {
2114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2115 VkResult result;
2116
2117 result = radv_reset_cmd_buffer(cmd_buffer);
2118 if (result != VK_SUCCESS)
2119 return result;
2120
2121 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2122 cmd_buffer->state.last_primitive_reset_en = -1;
2123 cmd_buffer->usage_flags = pBeginInfo->flags;
2124
2125 /* setup initial configuration into command buffer */
2126 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2127 switch (cmd_buffer->queue_family_index) {
2128 case RADV_QUEUE_GENERAL:
2129 emit_gfx_buffer_state(cmd_buffer);
2130 radv_set_db_count_control(cmd_buffer);
2131 break;
2132 case RADV_QUEUE_COMPUTE:
2133 si_init_compute(cmd_buffer);
2134 break;
2135 case RADV_QUEUE_TRANSFER:
2136 default:
2137 break;
2138 }
2139 }
2140
2141 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2142 assert(pBeginInfo->pInheritanceInfo);
2143 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2144 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2145
2146 struct radv_subpass *subpass =
2147 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2148
2149 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2150 if (result != VK_SUCCESS)
2151 return result;
2152
2153 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2154 }
2155
2156 radv_cmd_buffer_trace_emit(cmd_buffer);
2157 return result;
2158 }
2159
2160 void radv_CmdBindVertexBuffers(
2161 VkCommandBuffer commandBuffer,
2162 uint32_t firstBinding,
2163 uint32_t bindingCount,
2164 const VkBuffer* pBuffers,
2165 const VkDeviceSize* pOffsets)
2166 {
2167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2168 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2169
2170 /* We have to defer setting up vertex buffer since we need the buffer
2171 * stride from the pipeline. */
2172
2173 assert(firstBinding + bindingCount <= MAX_VBS);
2174 for (uint32_t i = 0; i < bindingCount; i++) {
2175 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2176 vb[firstBinding + i].offset = pOffsets[i];
2177 }
2178
2179 cmd_buffer->state.vb_dirty = true;
2180 }
2181
2182 void radv_CmdBindIndexBuffer(
2183 VkCommandBuffer commandBuffer,
2184 VkBuffer buffer,
2185 VkDeviceSize offset,
2186 VkIndexType indexType)
2187 {
2188 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2189 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2190
2191 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2192 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2193 cmd_buffer->state.index_va += index_buffer->offset + offset;
2194
2195 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2196 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2197 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2198 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2199 }
2200
2201
2202 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2203 struct radv_descriptor_set *set,
2204 unsigned idx)
2205 {
2206 struct radeon_winsys *ws = cmd_buffer->device->ws;
2207
2208 cmd_buffer->state.descriptors[idx] = set;
2209 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2210 if (!set)
2211 return;
2212
2213 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2214
2215 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2216 if (set->descriptors[j])
2217 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2218
2219 if(set->bo)
2220 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2221 }
2222
2223 void radv_CmdBindDescriptorSets(
2224 VkCommandBuffer commandBuffer,
2225 VkPipelineBindPoint pipelineBindPoint,
2226 VkPipelineLayout _layout,
2227 uint32_t firstSet,
2228 uint32_t descriptorSetCount,
2229 const VkDescriptorSet* pDescriptorSets,
2230 uint32_t dynamicOffsetCount,
2231 const uint32_t* pDynamicOffsets)
2232 {
2233 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2234 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2235 unsigned dyn_idx = 0;
2236
2237 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2238 unsigned idx = i + firstSet;
2239 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2240 radv_bind_descriptor_set(cmd_buffer, set, idx);
2241
2242 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2243 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2244 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2245 assert(dyn_idx < dynamicOffsetCount);
2246
2247 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2248 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2249 dst[0] = va;
2250 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2251 dst[2] = range->size;
2252 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2253 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2254 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2255 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2256 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2258 cmd_buffer->push_constant_stages |=
2259 set->layout->dynamic_shader_stages;
2260 }
2261 }
2262 }
2263
2264 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2265 struct radv_descriptor_set *set,
2266 struct radv_descriptor_set_layout *layout)
2267 {
2268 set->size = layout->size;
2269 set->layout = layout;
2270
2271 if (cmd_buffer->push_descriptors.capacity < set->size) {
2272 size_t new_size = MAX2(set->size, 1024);
2273 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2274 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2275
2276 free(set->mapped_ptr);
2277 set->mapped_ptr = malloc(new_size);
2278
2279 if (!set->mapped_ptr) {
2280 cmd_buffer->push_descriptors.capacity = 0;
2281 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2282 return false;
2283 }
2284
2285 cmd_buffer->push_descriptors.capacity = new_size;
2286 }
2287
2288 return true;
2289 }
2290
2291 void radv_meta_push_descriptor_set(
2292 struct radv_cmd_buffer* cmd_buffer,
2293 VkPipelineBindPoint pipelineBindPoint,
2294 VkPipelineLayout _layout,
2295 uint32_t set,
2296 uint32_t descriptorWriteCount,
2297 const VkWriteDescriptorSet* pDescriptorWrites)
2298 {
2299 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2300 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2301 unsigned bo_offset;
2302
2303 assert(set == 0);
2304 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2305
2306 push_set->size = layout->set[set].layout->size;
2307 push_set->layout = layout->set[set].layout;
2308
2309 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2310 &bo_offset,
2311 (void**) &push_set->mapped_ptr))
2312 return;
2313
2314 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2315 push_set->va += bo_offset;
2316
2317 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2318 radv_descriptor_set_to_handle(push_set),
2319 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2320
2321 cmd_buffer->state.descriptors[set] = push_set;
2322 cmd_buffer->state.descriptors_dirty |= (1u << set);
2323 }
2324
2325 void radv_CmdPushDescriptorSetKHR(
2326 VkCommandBuffer commandBuffer,
2327 VkPipelineBindPoint pipelineBindPoint,
2328 VkPipelineLayout _layout,
2329 uint32_t set,
2330 uint32_t descriptorWriteCount,
2331 const VkWriteDescriptorSet* pDescriptorWrites)
2332 {
2333 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2334 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2335 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2336
2337 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2338
2339 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2340 return;
2341
2342 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2343 radv_descriptor_set_to_handle(push_set),
2344 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2345
2346 cmd_buffer->state.descriptors[set] = push_set;
2347 cmd_buffer->state.descriptors_dirty |= (1u << set);
2348 cmd_buffer->state.push_descriptors_dirty = true;
2349 }
2350
2351 void radv_CmdPushDescriptorSetWithTemplateKHR(
2352 VkCommandBuffer commandBuffer,
2353 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2354 VkPipelineLayout _layout,
2355 uint32_t set,
2356 const void* pData)
2357 {
2358 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2359 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2360 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2361
2362 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2363
2364 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2365 return;
2366
2367 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2368 descriptorUpdateTemplate, pData);
2369
2370 cmd_buffer->state.descriptors[set] = push_set;
2371 cmd_buffer->state.descriptors_dirty |= (1u << set);
2372 cmd_buffer->state.push_descriptors_dirty = true;
2373 }
2374
2375 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2376 VkPipelineLayout layout,
2377 VkShaderStageFlags stageFlags,
2378 uint32_t offset,
2379 uint32_t size,
2380 const void* pValues)
2381 {
2382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2383 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2384 cmd_buffer->push_constant_stages |= stageFlags;
2385 }
2386
2387 VkResult radv_EndCommandBuffer(
2388 VkCommandBuffer commandBuffer)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391
2392 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2393 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2394 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2395 si_emit_cache_flush(cmd_buffer);
2396 }
2397
2398 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2399 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2400
2401 return cmd_buffer->record_result;
2402 }
2403
2404 static void
2405 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2406 {
2407 struct radeon_winsys *ws = cmd_buffer->device->ws;
2408 struct radv_shader_variant *compute_shader;
2409 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2410 uint64_t va;
2411
2412 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2413 return;
2414
2415 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2416
2417 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2418 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2419
2420 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2421 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2422
2423 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2424 cmd_buffer->cs, 16);
2425
2426 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2427 radeon_emit(cmd_buffer->cs, va >> 8);
2428 radeon_emit(cmd_buffer->cs, va >> 40);
2429
2430 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2431 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2432 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2433
2434
2435 cmd_buffer->compute_scratch_size_needed =
2436 MAX2(cmd_buffer->compute_scratch_size_needed,
2437 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2438
2439 /* change these once we have scratch support */
2440 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2441 S_00B860_WAVES(pipeline->max_waves) |
2442 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2443
2444 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2445 radeon_emit(cmd_buffer->cs,
2446 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2447 radeon_emit(cmd_buffer->cs,
2448 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2449 radeon_emit(cmd_buffer->cs,
2450 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2451
2452 assert(cmd_buffer->cs->cdw <= cdw_max);
2453 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2454 }
2455
2456 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2457 {
2458 for (unsigned i = 0; i < MAX_SETS; i++) {
2459 if (cmd_buffer->state.descriptors[i])
2460 cmd_buffer->state.descriptors_dirty |= (1u << i);
2461 }
2462 }
2463
2464 void radv_CmdBindPipeline(
2465 VkCommandBuffer commandBuffer,
2466 VkPipelineBindPoint pipelineBindPoint,
2467 VkPipeline _pipeline)
2468 {
2469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2470 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2471
2472 switch (pipelineBindPoint) {
2473 case VK_PIPELINE_BIND_POINT_COMPUTE:
2474 if (cmd_buffer->state.compute_pipeline == pipeline)
2475 return;
2476 radv_mark_descriptor_sets_dirty(cmd_buffer);
2477
2478 cmd_buffer->state.compute_pipeline = pipeline;
2479 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2480 break;
2481 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2482 if (cmd_buffer->state.pipeline == pipeline)
2483 return;
2484 radv_mark_descriptor_sets_dirty(cmd_buffer);
2485
2486 cmd_buffer->state.pipeline = pipeline;
2487 if (!pipeline)
2488 break;
2489
2490 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2491 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2492
2493 /* Apply the dynamic state from the pipeline */
2494 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2495 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2496 &pipeline->dynamic_state,
2497 pipeline->dynamic_state_mask);
2498
2499 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2500 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2501 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2502 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2503
2504 if (radv_pipeline_has_tess(pipeline))
2505 cmd_buffer->tess_rings_needed = true;
2506
2507 if (radv_pipeline_has_gs(pipeline)) {
2508 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2509 AC_UD_SCRATCH_RING_OFFSETS);
2510 if (cmd_buffer->ring_offsets_idx == -1)
2511 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2512 else if (loc->sgpr_idx != -1)
2513 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2514 }
2515 break;
2516 default:
2517 assert(!"invalid bind point");
2518 break;
2519 }
2520 }
2521
2522 void radv_CmdSetViewport(
2523 VkCommandBuffer commandBuffer,
2524 uint32_t firstViewport,
2525 uint32_t viewportCount,
2526 const VkViewport* pViewports)
2527 {
2528 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2529 const uint32_t total_count = firstViewport + viewportCount;
2530
2531 assert(firstViewport < MAX_VIEWPORTS);
2532 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2533
2534 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2535 pViewports, viewportCount * sizeof(*pViewports));
2536
2537 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2538 }
2539
2540 void radv_CmdSetScissor(
2541 VkCommandBuffer commandBuffer,
2542 uint32_t firstScissor,
2543 uint32_t scissorCount,
2544 const VkRect2D* pScissors)
2545 {
2546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2547 const uint32_t total_count = firstScissor + scissorCount;
2548
2549 assert(firstScissor < MAX_SCISSORS);
2550 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2551
2552 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2553 pScissors, scissorCount * sizeof(*pScissors));
2554 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2555 }
2556
2557 void radv_CmdSetLineWidth(
2558 VkCommandBuffer commandBuffer,
2559 float lineWidth)
2560 {
2561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2562 cmd_buffer->state.dynamic.line_width = lineWidth;
2563 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2564 }
2565
2566 void radv_CmdSetDepthBias(
2567 VkCommandBuffer commandBuffer,
2568 float depthBiasConstantFactor,
2569 float depthBiasClamp,
2570 float depthBiasSlopeFactor)
2571 {
2572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2573
2574 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2575 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2576 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2577
2578 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2579 }
2580
2581 void radv_CmdSetBlendConstants(
2582 VkCommandBuffer commandBuffer,
2583 const float blendConstants[4])
2584 {
2585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2586
2587 memcpy(cmd_buffer->state.dynamic.blend_constants,
2588 blendConstants, sizeof(float) * 4);
2589
2590 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2591 }
2592
2593 void radv_CmdSetDepthBounds(
2594 VkCommandBuffer commandBuffer,
2595 float minDepthBounds,
2596 float maxDepthBounds)
2597 {
2598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2599
2600 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2601 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2602
2603 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2604 }
2605
2606 void radv_CmdSetStencilCompareMask(
2607 VkCommandBuffer commandBuffer,
2608 VkStencilFaceFlags faceMask,
2609 uint32_t compareMask)
2610 {
2611 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2612
2613 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2614 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2615 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2616 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2617
2618 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2619 }
2620
2621 void radv_CmdSetStencilWriteMask(
2622 VkCommandBuffer commandBuffer,
2623 VkStencilFaceFlags faceMask,
2624 uint32_t writeMask)
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627
2628 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2629 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2630 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2631 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2632
2633 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2634 }
2635
2636 void radv_CmdSetStencilReference(
2637 VkCommandBuffer commandBuffer,
2638 VkStencilFaceFlags faceMask,
2639 uint32_t reference)
2640 {
2641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2642
2643 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2644 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2645 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2646 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2647
2648 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2649 }
2650
2651 void radv_CmdExecuteCommands(
2652 VkCommandBuffer commandBuffer,
2653 uint32_t commandBufferCount,
2654 const VkCommandBuffer* pCmdBuffers)
2655 {
2656 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2657
2658 assert(commandBufferCount > 0);
2659
2660 /* Emit pending flushes on primary prior to executing secondary */
2661 si_emit_cache_flush(primary);
2662
2663 for (uint32_t i = 0; i < commandBufferCount; i++) {
2664 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2665
2666 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2667 secondary->scratch_size_needed);
2668 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2669 secondary->compute_scratch_size_needed);
2670
2671 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2672 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2673 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2674 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2675 if (secondary->tess_rings_needed)
2676 primary->tess_rings_needed = true;
2677 if (secondary->sample_positions_needed)
2678 primary->sample_positions_needed = true;
2679
2680 if (secondary->ring_offsets_idx != -1) {
2681 if (primary->ring_offsets_idx == -1)
2682 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2683 else
2684 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2685 }
2686 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2687
2688
2689 /* When the secondary command buffer is compute only we don't
2690 * need to re-emit the current graphics pipeline.
2691 */
2692 if (secondary->state.emitted_pipeline) {
2693 primary->state.emitted_pipeline =
2694 secondary->state.emitted_pipeline;
2695 }
2696
2697 /* When the secondary command buffer is graphics only we don't
2698 * need to re-emit the current compute pipeline.
2699 */
2700 if (secondary->state.emitted_compute_pipeline) {
2701 primary->state.emitted_compute_pipeline =
2702 secondary->state.emitted_compute_pipeline;
2703 }
2704
2705 /* Only re-emit the draw packets when needed. */
2706 if (secondary->state.last_primitive_reset_en != -1) {
2707 primary->state.last_primitive_reset_en =
2708 secondary->state.last_primitive_reset_en;
2709 }
2710
2711 if (secondary->state.last_primitive_reset_index) {
2712 primary->state.last_primitive_reset_index =
2713 secondary->state.last_primitive_reset_index;
2714 }
2715
2716 if (secondary->state.last_ia_multi_vgt_param) {
2717 primary->state.last_ia_multi_vgt_param =
2718 secondary->state.last_ia_multi_vgt_param;
2719 }
2720 }
2721
2722 /* After executing commands from secondary buffers we have to dirty
2723 * some states.
2724 */
2725 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2726 RADV_CMD_DIRTY_INDEX_BUFFER |
2727 RADV_CMD_DIRTY_DYNAMIC_ALL;
2728 radv_mark_descriptor_sets_dirty(primary);
2729 }
2730
2731 VkResult radv_CreateCommandPool(
2732 VkDevice _device,
2733 const VkCommandPoolCreateInfo* pCreateInfo,
2734 const VkAllocationCallbacks* pAllocator,
2735 VkCommandPool* pCmdPool)
2736 {
2737 RADV_FROM_HANDLE(radv_device, device, _device);
2738 struct radv_cmd_pool *pool;
2739
2740 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2741 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2742 if (pool == NULL)
2743 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2744
2745 if (pAllocator)
2746 pool->alloc = *pAllocator;
2747 else
2748 pool->alloc = device->alloc;
2749
2750 list_inithead(&pool->cmd_buffers);
2751 list_inithead(&pool->free_cmd_buffers);
2752
2753 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2754
2755 *pCmdPool = radv_cmd_pool_to_handle(pool);
2756
2757 return VK_SUCCESS;
2758
2759 }
2760
2761 void radv_DestroyCommandPool(
2762 VkDevice _device,
2763 VkCommandPool commandPool,
2764 const VkAllocationCallbacks* pAllocator)
2765 {
2766 RADV_FROM_HANDLE(radv_device, device, _device);
2767 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2768
2769 if (!pool)
2770 return;
2771
2772 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2773 &pool->cmd_buffers, pool_link) {
2774 radv_cmd_buffer_destroy(cmd_buffer);
2775 }
2776
2777 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2778 &pool->free_cmd_buffers, pool_link) {
2779 radv_cmd_buffer_destroy(cmd_buffer);
2780 }
2781
2782 vk_free2(&device->alloc, pAllocator, pool);
2783 }
2784
2785 VkResult radv_ResetCommandPool(
2786 VkDevice device,
2787 VkCommandPool commandPool,
2788 VkCommandPoolResetFlags flags)
2789 {
2790 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2791 VkResult result;
2792
2793 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2794 &pool->cmd_buffers, pool_link) {
2795 result = radv_reset_cmd_buffer(cmd_buffer);
2796 if (result != VK_SUCCESS)
2797 return result;
2798 }
2799
2800 return VK_SUCCESS;
2801 }
2802
2803 void radv_TrimCommandPoolKHR(
2804 VkDevice device,
2805 VkCommandPool commandPool,
2806 VkCommandPoolTrimFlagsKHR flags)
2807 {
2808 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2809
2810 if (!pool)
2811 return;
2812
2813 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2814 &pool->free_cmd_buffers, pool_link) {
2815 radv_cmd_buffer_destroy(cmd_buffer);
2816 }
2817 }
2818
2819 void radv_CmdBeginRenderPass(
2820 VkCommandBuffer commandBuffer,
2821 const VkRenderPassBeginInfo* pRenderPassBegin,
2822 VkSubpassContents contents)
2823 {
2824 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2825 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2826 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2827
2828 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2829 cmd_buffer->cs, 2048);
2830 MAYBE_UNUSED VkResult result;
2831
2832 cmd_buffer->state.framebuffer = framebuffer;
2833 cmd_buffer->state.pass = pass;
2834 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2835
2836 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2837 if (result != VK_SUCCESS)
2838 return;
2839
2840 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2841 assert(cmd_buffer->cs->cdw <= cdw_max);
2842
2843 radv_cmd_buffer_clear_subpass(cmd_buffer);
2844 }
2845
2846 void radv_CmdNextSubpass(
2847 VkCommandBuffer commandBuffer,
2848 VkSubpassContents contents)
2849 {
2850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2851
2852 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2853
2854 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2855 2048);
2856
2857 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2858 radv_cmd_buffer_clear_subpass(cmd_buffer);
2859 }
2860
2861 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2862 {
2863 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2864 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2865 if (!pipeline->shaders[stage])
2866 continue;
2867 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2868 if (loc->sgpr_idx == -1)
2869 continue;
2870 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2871 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2872
2873 }
2874 if (pipeline->gs_copy_shader) {
2875 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2876 if (loc->sgpr_idx != -1) {
2877 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2878 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2879 }
2880 }
2881 }
2882
2883 static void
2884 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2885 uint32_t vertex_count)
2886 {
2887 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2888 radeon_emit(cmd_buffer->cs, vertex_count);
2889 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2890 S_0287F0_USE_OPAQUE(0));
2891 }
2892
2893 void radv_CmdDraw(
2894 VkCommandBuffer commandBuffer,
2895 uint32_t vertexCount,
2896 uint32_t instanceCount,
2897 uint32_t firstVertex,
2898 uint32_t firstInstance)
2899 {
2900 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2901
2902 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2903
2904 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2905
2906 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2907 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2908 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2909 radeon_emit(cmd_buffer->cs, firstVertex);
2910 radeon_emit(cmd_buffer->cs, firstInstance);
2911 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2912 radeon_emit(cmd_buffer->cs, 0);
2913
2914 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2915 radeon_emit(cmd_buffer->cs, instanceCount);
2916
2917 if (!cmd_buffer->state.subpass->view_mask) {
2918 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2919 } else {
2920 unsigned i;
2921 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2922 radv_emit_view_index(cmd_buffer, i);
2923
2924 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2925 }
2926 }
2927
2928 assert(cmd_buffer->cs->cdw <= cdw_max);
2929
2930 radv_cmd_buffer_after_draw(cmd_buffer);
2931 }
2932
2933
2934 static void
2935 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2936 uint64_t index_va,
2937 uint32_t index_count)
2938 {
2939 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2940 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2941 radeon_emit(cmd_buffer->cs, index_va);
2942 radeon_emit(cmd_buffer->cs, index_va >> 32);
2943 radeon_emit(cmd_buffer->cs, index_count);
2944 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2945 }
2946
2947 void radv_CmdDrawIndexed(
2948 VkCommandBuffer commandBuffer,
2949 uint32_t indexCount,
2950 uint32_t instanceCount,
2951 uint32_t firstIndex,
2952 int32_t vertexOffset,
2953 uint32_t firstInstance)
2954 {
2955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2956 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2957 uint64_t index_va;
2958
2959 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2960
2961 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2962
2963 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2964 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2965 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2966 radeon_emit(cmd_buffer->cs, vertexOffset);
2967 radeon_emit(cmd_buffer->cs, firstInstance);
2968 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2969 radeon_emit(cmd_buffer->cs, 0);
2970
2971 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2972 radeon_emit(cmd_buffer->cs, instanceCount);
2973
2974 index_va = cmd_buffer->state.index_va;
2975 index_va += firstIndex * index_size;
2976 if (!cmd_buffer->state.subpass->view_mask) {
2977 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2978 } else {
2979 unsigned i;
2980 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2981 radv_emit_view_index(cmd_buffer, i);
2982
2983 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2984 }
2985 }
2986
2987 assert(cmd_buffer->cs->cdw <= cdw_max);
2988 radv_cmd_buffer_after_draw(cmd_buffer);
2989 }
2990
2991 static void
2992 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2993 bool indexed,
2994 uint32_t draw_count,
2995 uint64_t count_va,
2996 uint32_t stride)
2997 {
2998 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2999 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3000 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3001 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3002 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3003 assert(base_reg);
3004
3005 if (draw_count == 1 && !count_va && !draw_id_enable) {
3006 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3007 PKT3_DRAW_INDIRECT, 3, false));
3008 radeon_emit(cs, 0);
3009 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3010 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3011 radeon_emit(cs, di_src_sel);
3012 } else {
3013 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3014 PKT3_DRAW_INDIRECT_MULTI,
3015 8, false));
3016 radeon_emit(cs, 0);
3017 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3018 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3019 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3020 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3021 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3022 radeon_emit(cs, draw_count); /* count */
3023 radeon_emit(cs, count_va); /* count_addr */
3024 radeon_emit(cs, count_va >> 32);
3025 radeon_emit(cs, stride); /* stride */
3026 radeon_emit(cs, di_src_sel);
3027 }
3028 }
3029
3030 static void
3031 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
3032 VkBuffer _buffer,
3033 VkDeviceSize offset,
3034 VkBuffer _count_buffer,
3035 VkDeviceSize count_offset,
3036 uint32_t draw_count,
3037 uint32_t stride,
3038 bool indexed)
3039 {
3040 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3041 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
3042 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3043
3044 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
3045 indirect_va += offset + buffer->offset;
3046 uint64_t count_va = 0;
3047
3048 if (count_buffer) {
3049 count_va = radv_buffer_get_va(count_buffer->bo);
3050 count_va += count_offset + count_buffer->offset;
3051
3052 cmd_buffer->device->ws->cs_add_buffer(cs, count_buffer->bo, 8);
3053 }
3054
3055 if (!draw_count)
3056 return;
3057
3058 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3059
3060 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3061 radeon_emit(cs, 1);
3062 radeon_emit(cs, indirect_va);
3063 radeon_emit(cs, indirect_va >> 32);
3064
3065 if (!cmd_buffer->state.subpass->view_mask) {
3066 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3067 } else {
3068 unsigned i;
3069 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3070 radv_emit_view_index(cmd_buffer, i);
3071
3072 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3073 }
3074 }
3075 radv_cmd_buffer_after_draw(cmd_buffer);
3076 }
3077
3078 static void
3079 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3080 VkBuffer buffer,
3081 VkDeviceSize offset,
3082 VkBuffer countBuffer,
3083 VkDeviceSize countBufferOffset,
3084 uint32_t maxDrawCount,
3085 uint32_t stride)
3086 {
3087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3088 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3089
3090 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3091 cmd_buffer->cs, 24 * MAX_VIEWS);
3092
3093 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3094 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3095
3096 assert(cmd_buffer->cs->cdw <= cdw_max);
3097 }
3098
3099 static void
3100 radv_cmd_draw_indexed_indirect_count(
3101 VkCommandBuffer commandBuffer,
3102 VkBuffer buffer,
3103 VkDeviceSize offset,
3104 VkBuffer countBuffer,
3105 VkDeviceSize countBufferOffset,
3106 uint32_t maxDrawCount,
3107 uint32_t stride)
3108 {
3109 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3110
3111 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3112
3113 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3114
3115 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3116 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3117
3118 assert(cmd_buffer->cs->cdw <= cdw_max);
3119 }
3120
3121 void radv_CmdDrawIndirect(
3122 VkCommandBuffer commandBuffer,
3123 VkBuffer buffer,
3124 VkDeviceSize offset,
3125 uint32_t drawCount,
3126 uint32_t stride)
3127 {
3128 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3129 VK_NULL_HANDLE, 0, drawCount, stride);
3130 }
3131
3132 void radv_CmdDrawIndexedIndirect(
3133 VkCommandBuffer commandBuffer,
3134 VkBuffer buffer,
3135 VkDeviceSize offset,
3136 uint32_t drawCount,
3137 uint32_t stride)
3138 {
3139 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3140 VK_NULL_HANDLE, 0, drawCount, stride);
3141 }
3142
3143 void radv_CmdDrawIndirectCountAMD(
3144 VkCommandBuffer commandBuffer,
3145 VkBuffer buffer,
3146 VkDeviceSize offset,
3147 VkBuffer countBuffer,
3148 VkDeviceSize countBufferOffset,
3149 uint32_t maxDrawCount,
3150 uint32_t stride)
3151 {
3152 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3153 countBuffer, countBufferOffset,
3154 maxDrawCount, stride);
3155 }
3156
3157 void radv_CmdDrawIndexedIndirectCountAMD(
3158 VkCommandBuffer commandBuffer,
3159 VkBuffer buffer,
3160 VkDeviceSize offset,
3161 VkBuffer countBuffer,
3162 VkDeviceSize countBufferOffset,
3163 uint32_t maxDrawCount,
3164 uint32_t stride)
3165 {
3166 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3167 countBuffer, countBufferOffset,
3168 maxDrawCount, stride);
3169 }
3170
3171 struct radv_dispatch_info {
3172 /**
3173 * Determine the layout of the grid (in block units) to be used.
3174 */
3175 uint32_t blocks[3];
3176
3177 /**
3178 * Whether it's an unaligned compute dispatch.
3179 */
3180 bool unaligned;
3181
3182 /**
3183 * Indirect compute parameters resource.
3184 */
3185 struct radv_buffer *indirect;
3186 uint64_t indirect_offset;
3187 };
3188
3189 static void
3190 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3191 const struct radv_dispatch_info *info)
3192 {
3193 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3194 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3195 struct radeon_winsys *ws = cmd_buffer->device->ws;
3196 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3197 struct ac_userdata_info *loc;
3198 unsigned dispatch_initiator;
3199 uint8_t grid_used;
3200
3201 grid_used = compute_shader->info.info.cs.grid_components_used;
3202
3203 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3204 AC_UD_CS_GRID_SIZE);
3205
3206 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3207
3208 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3209 S_00B800_FORCE_START_AT_000(1);
3210
3211 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3212 /* If the KMD allows it (there is a KMD hw register for it),
3213 * allow launching waves out-of-order.
3214 */
3215 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3216 }
3217
3218 if (info->indirect) {
3219 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3220
3221 va += info->indirect->offset + info->indirect_offset;
3222
3223 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3224
3225 if (loc->sgpr_idx != -1) {
3226 for (unsigned i = 0; i < grid_used; ++i) {
3227 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3228 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3229 COPY_DATA_DST_SEL(COPY_DATA_REG));
3230 radeon_emit(cs, (va + 4 * i));
3231 radeon_emit(cs, (va + 4 * i) >> 32);
3232 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3233 + loc->sgpr_idx * 4) >> 2) + i);
3234 radeon_emit(cs, 0);
3235 }
3236 }
3237
3238 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3239 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3240 PKT3_SHADER_TYPE_S(1));
3241 radeon_emit(cs, va);
3242 radeon_emit(cs, va >> 32);
3243 radeon_emit(cs, dispatch_initiator);
3244 } else {
3245 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3246 PKT3_SHADER_TYPE_S(1));
3247 radeon_emit(cs, 1);
3248 radeon_emit(cs, va);
3249 radeon_emit(cs, va >> 32);
3250
3251 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3252 PKT3_SHADER_TYPE_S(1));
3253 radeon_emit(cs, 0);
3254 radeon_emit(cs, dispatch_initiator);
3255 }
3256 } else {
3257 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3258
3259 if (info->unaligned) {
3260 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3261 unsigned remainder[3];
3262
3263 /* If aligned, these should be an entire block size,
3264 * not 0.
3265 */
3266 remainder[0] = blocks[0] + cs_block_size[0] -
3267 align_u32_npot(blocks[0], cs_block_size[0]);
3268 remainder[1] = blocks[1] + cs_block_size[1] -
3269 align_u32_npot(blocks[1], cs_block_size[1]);
3270 remainder[2] = blocks[2] + cs_block_size[2] -
3271 align_u32_npot(blocks[2], cs_block_size[2]);
3272
3273 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3274 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3275 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3276
3277 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3278 radeon_emit(cs,
3279 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3280 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3281 radeon_emit(cs,
3282 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3283 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3284 radeon_emit(cs,
3285 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3286 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3287
3288 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3289 }
3290
3291 if (loc->sgpr_idx != -1) {
3292 assert(!loc->indirect);
3293 assert(loc->num_sgprs == grid_used);
3294
3295 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3296 loc->sgpr_idx * 4, grid_used);
3297 radeon_emit(cs, blocks[0]);
3298 if (grid_used > 1)
3299 radeon_emit(cs, blocks[1]);
3300 if (grid_used > 2)
3301 radeon_emit(cs, blocks[2]);
3302 }
3303
3304 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3305 PKT3_SHADER_TYPE_S(1));
3306 radeon_emit(cs, blocks[0]);
3307 radeon_emit(cs, blocks[1]);
3308 radeon_emit(cs, blocks[2]);
3309 radeon_emit(cs, dispatch_initiator);
3310 }
3311
3312 assert(cmd_buffer->cs->cdw <= cdw_max);
3313 }
3314
3315 static void
3316 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3317 const struct radv_dispatch_info *info)
3318 {
3319 radv_emit_compute_pipeline(cmd_buffer);
3320
3321 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3322 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3323 VK_SHADER_STAGE_COMPUTE_BIT);
3324
3325 si_emit_cache_flush(cmd_buffer);
3326
3327 radv_emit_dispatch_packets(cmd_buffer, info);
3328
3329 radv_cmd_buffer_after_draw(cmd_buffer);
3330 }
3331
3332 void radv_CmdDispatch(
3333 VkCommandBuffer commandBuffer,
3334 uint32_t x,
3335 uint32_t y,
3336 uint32_t z)
3337 {
3338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3339 struct radv_dispatch_info info = {};
3340
3341 info.blocks[0] = x;
3342 info.blocks[1] = y;
3343 info.blocks[2] = z;
3344
3345 radv_dispatch(cmd_buffer, &info);
3346 }
3347
3348 void radv_CmdDispatchIndirect(
3349 VkCommandBuffer commandBuffer,
3350 VkBuffer _buffer,
3351 VkDeviceSize offset)
3352 {
3353 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3354 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3355 struct radv_dispatch_info info = {};
3356
3357 info.indirect = buffer;
3358 info.indirect_offset = offset;
3359
3360 radv_dispatch(cmd_buffer, &info);
3361 }
3362
3363 void radv_unaligned_dispatch(
3364 struct radv_cmd_buffer *cmd_buffer,
3365 uint32_t x,
3366 uint32_t y,
3367 uint32_t z)
3368 {
3369 struct radv_dispatch_info info = {};
3370
3371 info.blocks[0] = x;
3372 info.blocks[1] = y;
3373 info.blocks[2] = z;
3374 info.unaligned = 1;
3375
3376 radv_dispatch(cmd_buffer, &info);
3377 }
3378
3379 void radv_CmdEndRenderPass(
3380 VkCommandBuffer commandBuffer)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3383
3384 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3385
3386 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3387
3388 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3389 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3390 radv_handle_subpass_image_transition(cmd_buffer,
3391 (VkAttachmentReference){i, layout});
3392 }
3393
3394 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3395
3396 cmd_buffer->state.pass = NULL;
3397 cmd_buffer->state.subpass = NULL;
3398 cmd_buffer->state.attachments = NULL;
3399 cmd_buffer->state.framebuffer = NULL;
3400 }
3401
3402 /*
3403 * For HTILE we have the following interesting clear words:
3404 * 0x0000030f: Uncompressed.
3405 * 0xfffffff0: Clear depth to 1.0
3406 * 0x00000000: Clear depth to 0.0
3407 */
3408 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3409 struct radv_image *image,
3410 const VkImageSubresourceRange *range,
3411 uint32_t clear_word)
3412 {
3413 assert(range->baseMipLevel == 0);
3414 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3415 unsigned layer_count = radv_get_layerCount(image, range);
3416 uint64_t size = image->surface.htile_slice_size * layer_count;
3417 uint64_t offset = image->offset + image->htile_offset +
3418 image->surface.htile_slice_size * range->baseArrayLayer;
3419
3420 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3421 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3422
3423 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3424
3425 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3426 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3427 RADV_CMD_FLAG_INV_VMEM_L1 |
3428 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3429 }
3430
3431 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3432 struct radv_image *image,
3433 VkImageLayout src_layout,
3434 VkImageLayout dst_layout,
3435 unsigned src_queue_mask,
3436 unsigned dst_queue_mask,
3437 const VkImageSubresourceRange *range,
3438 VkImageAspectFlags pending_clears)
3439 {
3440 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3441 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3442 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3443 cmd_buffer->state.render_area.extent.width == image->info.width &&
3444 cmd_buffer->state.render_area.extent.height == image->info.height) {
3445 /* The clear will initialize htile. */
3446 return;
3447 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3448 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3449 /* TODO: merge with the clear if applicable */
3450 radv_initialize_htile(cmd_buffer, image, range, 0);
3451 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3452 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3453 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3454 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3455 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3456 VkImageSubresourceRange local_range = *range;
3457 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3458 local_range.baseMipLevel = 0;
3459 local_range.levelCount = 1;
3460
3461 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3462 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3463
3464 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3465
3466 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3467 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3468 }
3469 }
3470
3471 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3472 struct radv_image *image, uint32_t value)
3473 {
3474 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3475 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3476
3477 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3478 image->cmask.size, value);
3479
3480 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3481 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3482 RADV_CMD_FLAG_INV_VMEM_L1 |
3483 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3484 }
3485
3486 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3487 struct radv_image *image,
3488 VkImageLayout src_layout,
3489 VkImageLayout dst_layout,
3490 unsigned src_queue_mask,
3491 unsigned dst_queue_mask,
3492 const VkImageSubresourceRange *range)
3493 {
3494 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3495 if (image->fmask.size)
3496 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3497 else
3498 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3499 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3500 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3501 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3502 }
3503 }
3504
3505 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3506 struct radv_image *image, uint32_t value)
3507 {
3508
3509 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3510 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3511
3512 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3513 image->surface.dcc_size, value);
3514
3515 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3516 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3518 RADV_CMD_FLAG_INV_VMEM_L1 |
3519 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3520 }
3521
3522 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3523 struct radv_image *image,
3524 VkImageLayout src_layout,
3525 VkImageLayout dst_layout,
3526 unsigned src_queue_mask,
3527 unsigned dst_queue_mask,
3528 const VkImageSubresourceRange *range)
3529 {
3530 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3531 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3532 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3533 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3534 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3535 }
3536 }
3537
3538 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3539 struct radv_image *image,
3540 VkImageLayout src_layout,
3541 VkImageLayout dst_layout,
3542 uint32_t src_family,
3543 uint32_t dst_family,
3544 const VkImageSubresourceRange *range,
3545 VkImageAspectFlags pending_clears)
3546 {
3547 if (image->exclusive && src_family != dst_family) {
3548 /* This is an acquire or a release operation and there will be
3549 * a corresponding release/acquire. Do the transition in the
3550 * most flexible queue. */
3551
3552 assert(src_family == cmd_buffer->queue_family_index ||
3553 dst_family == cmd_buffer->queue_family_index);
3554
3555 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3556 return;
3557
3558 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3559 (src_family == RADV_QUEUE_GENERAL ||
3560 dst_family == RADV_QUEUE_GENERAL))
3561 return;
3562 }
3563
3564 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3565 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3566
3567 if (image->surface.htile_size)
3568 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3569 dst_layout, src_queue_mask,
3570 dst_queue_mask, range,
3571 pending_clears);
3572
3573 if (image->cmask.size || image->fmask.size)
3574 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3575 dst_layout, src_queue_mask,
3576 dst_queue_mask, range);
3577
3578 if (image->surface.dcc_size)
3579 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3580 dst_layout, src_queue_mask,
3581 dst_queue_mask, range);
3582 }
3583
3584 void radv_CmdPipelineBarrier(
3585 VkCommandBuffer commandBuffer,
3586 VkPipelineStageFlags srcStageMask,
3587 VkPipelineStageFlags destStageMask,
3588 VkBool32 byRegion,
3589 uint32_t memoryBarrierCount,
3590 const VkMemoryBarrier* pMemoryBarriers,
3591 uint32_t bufferMemoryBarrierCount,
3592 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3593 uint32_t imageMemoryBarrierCount,
3594 const VkImageMemoryBarrier* pImageMemoryBarriers)
3595 {
3596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3597 enum radv_cmd_flush_bits src_flush_bits = 0;
3598 enum radv_cmd_flush_bits dst_flush_bits = 0;
3599
3600 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3601 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3602 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3603 NULL);
3604 }
3605
3606 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3607 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3608 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3609 NULL);
3610 }
3611
3612 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3613 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3614 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3615 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3616 image);
3617 }
3618
3619 radv_stage_flush(cmd_buffer, srcStageMask);
3620 cmd_buffer->state.flush_bits |= src_flush_bits;
3621
3622 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3623 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3624 radv_handle_image_transition(cmd_buffer, image,
3625 pImageMemoryBarriers[i].oldLayout,
3626 pImageMemoryBarriers[i].newLayout,
3627 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3628 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3629 &pImageMemoryBarriers[i].subresourceRange,
3630 0);
3631 }
3632
3633 cmd_buffer->state.flush_bits |= dst_flush_bits;
3634 }
3635
3636
3637 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3638 struct radv_event *event,
3639 VkPipelineStageFlags stageMask,
3640 unsigned value)
3641 {
3642 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3643 uint64_t va = radv_buffer_get_va(event->bo);
3644
3645 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3646
3647 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3648
3649 /* TODO: this is overkill. Probably should figure something out from
3650 * the stage mask. */
3651
3652 si_cs_emit_write_event_eop(cs,
3653 cmd_buffer->state.predicating,
3654 cmd_buffer->device->physical_device->rad_info.chip_class,
3655 false,
3656 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3657 1, va, 2, value);
3658
3659 assert(cmd_buffer->cs->cdw <= cdw_max);
3660 }
3661
3662 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3663 VkEvent _event,
3664 VkPipelineStageFlags stageMask)
3665 {
3666 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3667 RADV_FROM_HANDLE(radv_event, event, _event);
3668
3669 write_event(cmd_buffer, event, stageMask, 1);
3670 }
3671
3672 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3673 VkEvent _event,
3674 VkPipelineStageFlags stageMask)
3675 {
3676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3677 RADV_FROM_HANDLE(radv_event, event, _event);
3678
3679 write_event(cmd_buffer, event, stageMask, 0);
3680 }
3681
3682 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3683 uint32_t eventCount,
3684 const VkEvent* pEvents,
3685 VkPipelineStageFlags srcStageMask,
3686 VkPipelineStageFlags dstStageMask,
3687 uint32_t memoryBarrierCount,
3688 const VkMemoryBarrier* pMemoryBarriers,
3689 uint32_t bufferMemoryBarrierCount,
3690 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3691 uint32_t imageMemoryBarrierCount,
3692 const VkImageMemoryBarrier* pImageMemoryBarriers)
3693 {
3694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3695 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3696
3697 for (unsigned i = 0; i < eventCount; ++i) {
3698 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3699 uint64_t va = radv_buffer_get_va(event->bo);
3700
3701 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3702
3703 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3704
3705 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3706 assert(cmd_buffer->cs->cdw <= cdw_max);
3707 }
3708
3709
3710 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3711 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3712
3713 radv_handle_image_transition(cmd_buffer, image,
3714 pImageMemoryBarriers[i].oldLayout,
3715 pImageMemoryBarriers[i].newLayout,
3716 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3717 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3718 &pImageMemoryBarriers[i].subresourceRange,
3719 0);
3720 }
3721
3722 /* TODO: figure out how to do memory barriers without waiting */
3723 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3724 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3725 RADV_CMD_FLAG_INV_VMEM_L1 |
3726 RADV_CMD_FLAG_INV_SMEM_L1;
3727 }