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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safefly call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING);
351
352 if (!bo) {
353 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
354 return false;
355 }
356
357 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
358 if (cmd_buffer->upload.upload_bo) {
359 upload = malloc(sizeof(*upload));
360
361 if (!upload) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
363 device->ws->buffer_destroy(bo);
364 return false;
365 }
366
367 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
368 list_add(&upload->list, &cmd_buffer->upload.list);
369 }
370
371 cmd_buffer->upload.upload_bo = bo;
372 cmd_buffer->upload.size = new_size;
373 cmd_buffer->upload.offset = 0;
374 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
375
376 if (!cmd_buffer->upload.map) {
377 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
378 return false;
379 }
380
381 return true;
382 }
383
384 bool
385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
386 unsigned size,
387 unsigned alignment,
388 unsigned *out_offset,
389 void **ptr)
390 {
391 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
392 if (offset + size > cmd_buffer->upload.size) {
393 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
394 return false;
395 offset = 0;
396 }
397
398 *out_offset = offset;
399 *ptr = cmd_buffer->upload.map + offset;
400
401 cmd_buffer->upload.offset = offset + size;
402 return true;
403 }
404
405 bool
406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
407 unsigned size, unsigned alignment,
408 const void *data, unsigned *out_offset)
409 {
410 uint8_t *ptr;
411
412 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
413 out_offset, (void **)&ptr))
414 return false;
415
416 if (ptr)
417 memcpy(ptr, data, size);
418
419 return true;
420 }
421
422 static void
423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
424 unsigned count, const uint32_t *data)
425 {
426 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
427 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
428 S_370_WR_CONFIRM(1) |
429 S_370_ENGINE_SEL(V_370_ME));
430 radeon_emit(cs, va);
431 radeon_emit(cs, va >> 32);
432 radeon_emit_array(cs, data, count);
433 }
434
435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
436 {
437 struct radv_device *device = cmd_buffer->device;
438 struct radeon_winsys_cs *cs = cmd_buffer->cs;
439 uint64_t va;
440
441 va = radv_buffer_get_va(device->trace_bo);
442 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
443 va += 4;
444
445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
446
447 ++cmd_buffer->state.trace_id;
448 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
449 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
451 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
452 }
453
454 static void
455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
456 enum radv_cmd_flush_bits flags)
457 {
458 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
459 uint32_t *ptr = NULL;
460 uint64_t va = 0;
461
462 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
464
465 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
466 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
467 cmd_buffer->gfx9_fence_offset;
468 ptr = &cmd_buffer->gfx9_fence_idx;
469 }
470
471 /* Force wait for graphics or compute engines to be idle. */
472 si_cs_emit_cache_flush(cmd_buffer->cs,
473 cmd_buffer->device->physical_device->rad_info.chip_class,
474 ptr, va,
475 radv_cmd_buffer_uses_mec(cmd_buffer),
476 flags);
477 }
478
479 if (unlikely(cmd_buffer->device->trace_bo))
480 radv_cmd_buffer_trace_emit(cmd_buffer);
481 }
482
483 static void
484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
485 struct radv_pipeline *pipeline, enum ring_type ring)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[2];
490 uint64_t va;
491
492 va = radv_buffer_get_va(device->trace_bo);
493
494 switch (ring) {
495 case RING_GFX:
496 va += 8;
497 break;
498 case RING_COMPUTE:
499 va += 16;
500 break;
501 default:
502 assert(!"invalid ring type");
503 }
504
505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
506 cmd_buffer->cs, 6);
507
508 data[0] = (uintptr_t)pipeline;
509 data[1] = (uintptr_t)pipeline >> 32;
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, 2, data);
513 }
514
515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
516 VkPipelineBindPoint bind_point,
517 struct radv_descriptor_set *set,
518 unsigned idx)
519 {
520 struct radv_descriptor_state *descriptors_state =
521 radv_get_descriptors_state(cmd_buffer, bind_point);
522
523 descriptors_state->sets[idx] = set;
524 if (set)
525 descriptors_state->valid |= (1u << idx);
526 else
527 descriptors_state->valid &= ~(1u << idx);
528 descriptors_state->dirty |= (1u << idx);
529 }
530
531 static void
532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
533 VkPipelineBindPoint bind_point)
534 {
535 struct radv_descriptor_state *descriptors_state =
536 radv_get_descriptors_state(cmd_buffer, bind_point);
537 struct radv_device *device = cmd_buffer->device;
538 struct radeon_winsys_cs *cs = cmd_buffer->cs;
539 uint32_t data[MAX_SETS * 2] = {};
540 uint64_t va;
541 unsigned i;
542 va = radv_buffer_get_va(device->trace_bo) + 24;
543
544 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
545 cmd_buffer->cs, 4 + MAX_SETS * 2);
546
547 for_each_bit(i, descriptors_state->valid) {
548 struct radv_descriptor_set *set = descriptors_state->sets[i];
549 data[i * 2] = (uintptr_t)set;
550 data[i * 2 + 1] = (uintptr_t)set >> 32;
551 }
552
553 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
554 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
555 }
556
557 struct radv_userdata_info *
558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
559 gl_shader_stage stage,
560 int idx)
561 {
562 if (stage == MESA_SHADER_VERTEX) {
563 if (pipeline->shaders[MESA_SHADER_VERTEX])
564 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
565 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
566 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
567 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
568 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
569 } else if (stage == MESA_SHADER_TESS_EVAL) {
570 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
571 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 }
575 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
576 }
577
578 static void
579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
580 struct radv_pipeline *pipeline,
581 gl_shader_stage stage,
582 int idx, uint64_t va)
583 {
584 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
585 uint32_t base_reg = pipeline->user_data_0[stage];
586 if (loc->sgpr_idx == -1)
587 return;
588 assert(loc->num_sgprs == 2);
589 assert(!loc->indirect);
590 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
591 radeon_emit(cmd_buffer->cs, va);
592 radeon_emit(cmd_buffer->cs, va >> 32);
593 }
594
595 static void
596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
597 struct radv_pipeline *pipeline)
598 {
599 int num_samples = pipeline->graphics.ms.num_samples;
600 struct radv_multisample_state *ms = &pipeline->graphics.ms;
601 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
602
603 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
604 cmd_buffer->sample_positions_needed = true;
605
606 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
607 return;
608
609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
611 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
614
615 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
616
617 /* GFX9: Flush DFSM when the AA mode changes. */
618 if (cmd_buffer->device->dfsm_allowed) {
619 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
620 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
621 }
622 }
623
624 static void
625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
626 struct radv_shader_variant *shader)
627 {
628 struct radeon_winsys *ws = cmd_buffer->device->ws;
629 struct radeon_winsys_cs *cs = cmd_buffer->cs;
630 uint64_t va;
631
632 if (!shader)
633 return;
634
635 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
636
637 radv_cs_add_buffer(ws, cs, shader->bo, 8);
638 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
639 }
640
641 static void
642 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline,
644 bool vertex_stage_only)
645 {
646 struct radv_cmd_state *state = &cmd_buffer->state;
647 uint32_t mask = state->prefetch_L2_mask;
648
649 if (vertex_stage_only) {
650 /* Fast prefetch path for starting draws as soon as possible.
651 */
652 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
653 RADV_PREFETCH_VBO_DESCRIPTORS);
654 }
655
656 if (mask & RADV_PREFETCH_VS)
657 radv_emit_shader_prefetch(cmd_buffer,
658 pipeline->shaders[MESA_SHADER_VERTEX]);
659
660 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
661 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
662
663 if (mask & RADV_PREFETCH_TCS)
664 radv_emit_shader_prefetch(cmd_buffer,
665 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
666
667 if (mask & RADV_PREFETCH_TES)
668 radv_emit_shader_prefetch(cmd_buffer,
669 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
670
671 if (mask & RADV_PREFETCH_GS) {
672 radv_emit_shader_prefetch(cmd_buffer,
673 pipeline->shaders[MESA_SHADER_GEOMETRY]);
674 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
675 }
676
677 if (mask & RADV_PREFETCH_PS)
678 radv_emit_shader_prefetch(cmd_buffer,
679 pipeline->shaders[MESA_SHADER_FRAGMENT]);
680
681 state->prefetch_L2_mask &= ~mask;
682 }
683
684 static void
685 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
686 {
687 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
688
689 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
690 return;
691
692 radv_update_multisample_state(cmd_buffer, pipeline);
693
694 cmd_buffer->scratch_size_needed =
695 MAX2(cmd_buffer->scratch_size_needed,
696 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
697
698 if (!cmd_buffer->state.emitted_pipeline ||
699 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
700 pipeline->graphics.can_use_guardband)
701 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
702
703 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
704
705 if (unlikely(cmd_buffer->device->trace_bo))
706 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
707
708 cmd_buffer->state.emitted_pipeline = pipeline;
709
710 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
711 }
712
713 static void
714 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
715 {
716 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
717 cmd_buffer->state.dynamic.viewport.viewports);
718 }
719
720 static void
721 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
722 {
723 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
724
725 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
726 * scissor registers are changed. There is also a more efficient but
727 * more involved alternative workaround.
728 */
729 if (cmd_buffer->device->physical_device->has_scissor_bug) {
730 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
731 si_emit_cache_flush(cmd_buffer);
732 }
733 si_write_scissors(cmd_buffer->cs, 0, count,
734 cmd_buffer->state.dynamic.scissor.scissors,
735 cmd_buffer->state.dynamic.viewport.viewports,
736 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
737 }
738
739 static void
740 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
741 {
742 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
743 return;
744
745 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
746 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
747 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
748 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
749 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
750 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
751 S_028214_BR_Y(rect.offset.y + rect.extent.height));
752 }
753 }
754
755 static void
756 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
757 {
758 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
759
760 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
761 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
762 }
763
764 static void
765 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
766 {
767 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
768
769 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
770 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
771 }
772
773 static void
774 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
777
778 radeon_set_context_reg_seq(cmd_buffer->cs,
779 R_028430_DB_STENCILREFMASK, 2);
780 radeon_emit(cmd_buffer->cs,
781 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
782 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
783 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
784 S_028430_STENCILOPVAL(1));
785 radeon_emit(cmd_buffer->cs,
786 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
787 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
788 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
789 S_028434_STENCILOPVAL_BF(1));
790 }
791
792 static void
793 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
794 {
795 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
796
797 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
798 fui(d->depth_bounds.min));
799 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
800 fui(d->depth_bounds.max));
801 }
802
803 static void
804 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
805 {
806 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
807 unsigned slope = fui(d->depth_bias.slope * 16.0f);
808 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
809
810
811 radeon_set_context_reg_seq(cmd_buffer->cs,
812 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
813 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
814 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
815 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
816 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
817 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
818 }
819
820 static void
821 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
822 int index,
823 struct radv_attachment_info *att,
824 struct radv_image *image,
825 VkImageLayout layout)
826 {
827 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
828 struct radv_color_buffer_info *cb = &att->cb;
829 uint32_t cb_color_info = cb->cb_color_info;
830
831 if (!radv_layout_dcc_compressed(image, layout,
832 radv_image_queue_family_mask(image,
833 cmd_buffer->queue_family_index,
834 cmd_buffer->queue_family_index))) {
835 cb_color_info &= C_028C70_DCC_ENABLE;
836 }
837
838 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
839 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
840 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
841 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
842 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
843 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
844 radeon_emit(cmd_buffer->cs, cb_color_info);
845 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
846 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
847 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
848 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
849 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
850 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
851
852 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
853 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
854 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
855
856 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
857 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
858 } else {
859 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
860 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
861 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
862 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
863 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
864 radeon_emit(cmd_buffer->cs, cb_color_info);
865 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
866 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
867 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
868 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
869 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
870 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
871
872 if (is_vi) { /* DCC BASE */
873 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
874 }
875 }
876 }
877
878 static void
879 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
880 struct radv_ds_buffer_info *ds,
881 struct radv_image *image,
882 VkImageLayout layout)
883 {
884 uint32_t db_z_info = ds->db_z_info;
885 uint32_t db_stencil_info = ds->db_stencil_info;
886
887 if (!radv_layout_has_htile(image, layout,
888 radv_image_queue_family_mask(image,
889 cmd_buffer->queue_family_index,
890 cmd_buffer->queue_family_index))) {
891 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
892 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
893 }
894
895 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
896 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
897
898
899 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
900 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
901 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
902 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
903 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
904
905 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
906 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
907 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
908 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
909 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
910 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
911 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
912 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
913 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
914 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
915 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
918 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
919 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
920 } else {
921 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
922
923 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
924 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
925 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
926 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
927 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
928 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
929 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
930 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
931 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
932 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
933
934 }
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
937 ds->pa_su_poly_offset_db_fmt_cntl);
938 }
939
940 void
941 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
942 struct radv_image *image,
943 VkClearDepthStencilValue ds_clear_value,
944 VkImageAspectFlags aspects)
945 {
946 uint64_t va = radv_buffer_get_va(image->bo);
947 va += image->offset + image->clear_value_offset;
948 unsigned reg_offset = 0, reg_count = 0;
949
950 assert(radv_image_has_htile(image));
951
952 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
953 ++reg_count;
954 } else {
955 ++reg_offset;
956 va += 4;
957 }
958 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
959 ++reg_count;
960
961 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
962 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
963 S_370_WR_CONFIRM(1) |
964 S_370_ENGINE_SEL(V_370_PFP));
965 radeon_emit(cmd_buffer->cs, va);
966 radeon_emit(cmd_buffer->cs, va >> 32);
967 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
968 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
969 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
970 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
971
972 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
973 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
974 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
975 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
976 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
977 }
978
979 static void
980 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
981 struct radv_image *image)
982 {
983 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
984 uint64_t va = radv_buffer_get_va(image->bo);
985 va += image->offset + image->clear_value_offset;
986 unsigned reg_offset = 0, reg_count = 0;
987
988 if (!radv_image_has_htile(image))
989 return;
990
991 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
992 ++reg_count;
993 } else {
994 ++reg_offset;
995 va += 4;
996 }
997 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
998 ++reg_count;
999
1000 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1001 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1002 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1003 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1004 radeon_emit(cmd_buffer->cs, va);
1005 radeon_emit(cmd_buffer->cs, va >> 32);
1006 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1007 radeon_emit(cmd_buffer->cs, 0);
1008
1009 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1010 radeon_emit(cmd_buffer->cs, 0);
1011 }
1012
1013 /*
1014 *with DCC some colors don't require CMASK elimiation before being
1015 * used as a texture. This sets a predicate value to determine if the
1016 * cmask eliminate is required.
1017 */
1018 void
1019 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1020 struct radv_image *image,
1021 bool value)
1022 {
1023 uint64_t pred_val = value;
1024 uint64_t va = radv_buffer_get_va(image->bo);
1025 va += image->offset + image->dcc_pred_offset;
1026
1027 assert(radv_image_has_dcc(image));
1028
1029 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1030 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1031 S_370_WR_CONFIRM(1) |
1032 S_370_ENGINE_SEL(V_370_PFP));
1033 radeon_emit(cmd_buffer->cs, va);
1034 radeon_emit(cmd_buffer->cs, va >> 32);
1035 radeon_emit(cmd_buffer->cs, pred_val);
1036 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1037 }
1038
1039 void
1040 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1041 struct radv_image *image,
1042 int idx,
1043 uint32_t color_values[2])
1044 {
1045 uint64_t va = radv_buffer_get_va(image->bo);
1046 va += image->offset + image->clear_value_offset;
1047
1048 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1049
1050 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1051 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1052 S_370_WR_CONFIRM(1) |
1053 S_370_ENGINE_SEL(V_370_PFP));
1054 radeon_emit(cmd_buffer->cs, va);
1055 radeon_emit(cmd_buffer->cs, va >> 32);
1056 radeon_emit(cmd_buffer->cs, color_values[0]);
1057 radeon_emit(cmd_buffer->cs, color_values[1]);
1058
1059 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1060 radeon_emit(cmd_buffer->cs, color_values[0]);
1061 radeon_emit(cmd_buffer->cs, color_values[1]);
1062 }
1063
1064 static void
1065 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1066 struct radv_image *image,
1067 int idx)
1068 {
1069 uint64_t va = radv_buffer_get_va(image->bo);
1070 va += image->offset + image->clear_value_offset;
1071
1072 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1073 return;
1074
1075 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1076
1077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1078 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1079 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1080 COPY_DATA_COUNT_SEL);
1081 radeon_emit(cmd_buffer->cs, va);
1082 radeon_emit(cmd_buffer->cs, va >> 32);
1083 radeon_emit(cmd_buffer->cs, reg >> 2);
1084 radeon_emit(cmd_buffer->cs, 0);
1085
1086 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1087 radeon_emit(cmd_buffer->cs, 0);
1088 }
1089
1090 static void
1091 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1092 {
1093 int i;
1094 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1095 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1096
1097 /* this may happen for inherited secondary recording */
1098 if (!framebuffer)
1099 return;
1100
1101 for (i = 0; i < 8; ++i) {
1102 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1103 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1104 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1105 continue;
1106 }
1107
1108 int idx = subpass->color_attachments[i].attachment;
1109 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1110 struct radv_image *image = att->attachment->image;
1111 VkImageLayout layout = subpass->color_attachments[i].layout;
1112
1113 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1114
1115 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1116 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1117
1118 radv_load_color_clear_regs(cmd_buffer, image, i);
1119 }
1120
1121 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1122 int idx = subpass->depth_stencil_attachment.attachment;
1123 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1124 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1125 struct radv_image *image = att->attachment->image;
1126 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1127 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1128 cmd_buffer->queue_family_index,
1129 cmd_buffer->queue_family_index);
1130 /* We currently don't support writing decompressed HTILE */
1131 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1132 radv_layout_is_htile_compressed(image, layout, queue_mask));
1133
1134 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1135
1136 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1137 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1138 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1139 }
1140 radv_load_depth_clear_regs(cmd_buffer, image);
1141 } else {
1142 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1144 else
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1146
1147 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1148 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1149 }
1150 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1151 S_028208_BR_X(framebuffer->width) |
1152 S_028208_BR_Y(framebuffer->height));
1153
1154 if (cmd_buffer->device->dfsm_allowed) {
1155 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1156 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1157 }
1158
1159 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1160 }
1161
1162 static void
1163 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1164 {
1165 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1166 struct radv_cmd_state *state = &cmd_buffer->state;
1167
1168 if (state->index_type != state->last_index_type) {
1169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1170 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1171 2, state->index_type);
1172 } else {
1173 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1174 radeon_emit(cs, state->index_type);
1175 }
1176
1177 state->last_index_type = state->index_type;
1178 }
1179
1180 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1181 radeon_emit(cs, state->index_va);
1182 radeon_emit(cs, state->index_va >> 32);
1183
1184 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1185 radeon_emit(cs, state->max_index_count);
1186
1187 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1188 }
1189
1190 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1191 {
1192 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1193 uint32_t pa_sc_mode_cntl_1 =
1194 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1195 uint32_t db_count_control;
1196
1197 if(!cmd_buffer->state.active_occlusion_queries) {
1198 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1199 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1200 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1201 /* Re-enable out-of-order rasterization if the
1202 * bound pipeline supports it and if it's has
1203 * been disabled before starting occlusion
1204 * queries.
1205 */
1206 radeon_set_context_reg(cmd_buffer->cs,
1207 R_028A4C_PA_SC_MODE_CNTL_1,
1208 pa_sc_mode_cntl_1);
1209 }
1210 db_count_control = 0;
1211 } else {
1212 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1213 }
1214 } else {
1215 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1216 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1217 bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled;
1218
1219 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1220 db_count_control =
1221 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1222 S_028004_SAMPLE_RATE(sample_rate) |
1223 S_028004_ZPASS_ENABLE(1) |
1224 S_028004_SLICE_EVEN_ENABLE(1) |
1225 S_028004_SLICE_ODD_ENABLE(1);
1226
1227 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1228 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1229 /* If the bound pipeline has enabled
1230 * out-of-order rasterization, we should
1231 * disable it before starting occlusion
1232 * queries.
1233 */
1234 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1235
1236 radeon_set_context_reg(cmd_buffer->cs,
1237 R_028A4C_PA_SC_MODE_CNTL_1,
1238 pa_sc_mode_cntl_1);
1239 }
1240 } else {
1241 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1242 S_028004_SAMPLE_RATE(sample_rate);
1243 }
1244 }
1245
1246 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1247 }
1248
1249 static void
1250 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1251 {
1252 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1253
1254 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1255 radv_emit_viewport(cmd_buffer);
1256
1257 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1258 radv_emit_scissor(cmd_buffer);
1259
1260 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1261 radv_emit_line_width(cmd_buffer);
1262
1263 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1264 radv_emit_blend_constants(cmd_buffer);
1265
1266 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1267 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1268 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1269 radv_emit_stencil(cmd_buffer);
1270
1271 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1272 radv_emit_depth_bounds(cmd_buffer);
1273
1274 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1275 radv_emit_depth_bias(cmd_buffer);
1276
1277 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1278 radv_emit_discard_rectangle(cmd_buffer);
1279
1280 cmd_buffer->state.dirty &= ~states;
1281 }
1282
1283 static void
1284 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1285 struct radv_pipeline *pipeline,
1286 int idx,
1287 uint64_t va,
1288 gl_shader_stage stage)
1289 {
1290 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1291 uint32_t base_reg = pipeline->user_data_0[stage];
1292
1293 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1294 return;
1295
1296 assert(!desc_set_loc->indirect);
1297 assert(desc_set_loc->num_sgprs == 2);
1298 radeon_set_sh_reg_seq(cmd_buffer->cs,
1299 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1300 radeon_emit(cmd_buffer->cs, va);
1301 radeon_emit(cmd_buffer->cs, va >> 32);
1302 }
1303
1304 static void
1305 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1306 VkShaderStageFlags stages,
1307 struct radv_descriptor_set *set,
1308 unsigned idx)
1309 {
1310 if (cmd_buffer->state.pipeline) {
1311 radv_foreach_stage(stage, stages) {
1312 if (cmd_buffer->state.pipeline->shaders[stage])
1313 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1314 idx, set->va,
1315 stage);
1316 }
1317 }
1318
1319 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1320 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1321 idx, set->va,
1322 MESA_SHADER_COMPUTE);
1323 }
1324
1325 static void
1326 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1327 VkPipelineBindPoint bind_point)
1328 {
1329 struct radv_descriptor_state *descriptors_state =
1330 radv_get_descriptors_state(cmd_buffer, bind_point);
1331 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1332 unsigned bo_offset;
1333
1334 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1335 set->mapped_ptr,
1336 &bo_offset))
1337 return;
1338
1339 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1340 set->va += bo_offset;
1341 }
1342
1343 static void
1344 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1345 VkPipelineBindPoint bind_point)
1346 {
1347 struct radv_descriptor_state *descriptors_state =
1348 radv_get_descriptors_state(cmd_buffer, bind_point);
1349 uint32_t size = MAX_SETS * 2 * 4;
1350 uint32_t offset;
1351 void *ptr;
1352
1353 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1354 256, &offset, &ptr))
1355 return;
1356
1357 for (unsigned i = 0; i < MAX_SETS; i++) {
1358 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1359 uint64_t set_va = 0;
1360 struct radv_descriptor_set *set = descriptors_state->sets[i];
1361 if (descriptors_state->valid & (1u << i))
1362 set_va = set->va;
1363 uptr[0] = set_va & 0xffffffff;
1364 uptr[1] = set_va >> 32;
1365 }
1366
1367 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1368 va += offset;
1369
1370 if (cmd_buffer->state.pipeline) {
1371 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1372 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1373 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1374
1375 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1376 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1377 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1378
1379 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1380 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1381 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1382
1383 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1384 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1385 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1386
1387 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1388 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1389 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1390 }
1391
1392 if (cmd_buffer->state.compute_pipeline)
1393 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1394 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1395 }
1396
1397 static void
1398 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1399 VkShaderStageFlags stages)
1400 {
1401 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1402 VK_PIPELINE_BIND_POINT_COMPUTE :
1403 VK_PIPELINE_BIND_POINT_GRAPHICS;
1404 struct radv_descriptor_state *descriptors_state =
1405 radv_get_descriptors_state(cmd_buffer, bind_point);
1406 unsigned i;
1407
1408 if (!descriptors_state->dirty)
1409 return;
1410
1411 if (descriptors_state->push_dirty)
1412 radv_flush_push_descriptors(cmd_buffer, bind_point);
1413
1414 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1415 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1416 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1417 }
1418
1419 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1420 cmd_buffer->cs,
1421 MAX_SETS * MESA_SHADER_STAGES * 4);
1422
1423 for_each_bit(i, descriptors_state->dirty) {
1424 struct radv_descriptor_set *set = descriptors_state->sets[i];
1425 if (!(descriptors_state->valid & (1u << i)))
1426 continue;
1427
1428 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1429 }
1430 descriptors_state->dirty = 0;
1431 descriptors_state->push_dirty = false;
1432
1433 if (unlikely(cmd_buffer->device->trace_bo))
1434 radv_save_descriptors(cmd_buffer, bind_point);
1435
1436 assert(cmd_buffer->cs->cdw <= cdw_max);
1437 }
1438
1439 static void
1440 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1441 VkShaderStageFlags stages)
1442 {
1443 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1444 ? cmd_buffer->state.compute_pipeline
1445 : cmd_buffer->state.pipeline;
1446 struct radv_pipeline_layout *layout = pipeline->layout;
1447 unsigned offset;
1448 void *ptr;
1449 uint64_t va;
1450
1451 stages &= cmd_buffer->push_constant_stages;
1452 if (!stages ||
1453 (!layout->push_constant_size && !layout->dynamic_offset_count))
1454 return;
1455
1456 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1457 16 * layout->dynamic_offset_count,
1458 256, &offset, &ptr))
1459 return;
1460
1461 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1462 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1463 16 * layout->dynamic_offset_count);
1464
1465 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1466 va += offset;
1467
1468 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1469 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1470
1471 radv_foreach_stage(stage, stages) {
1472 if (pipeline->shaders[stage]) {
1473 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1474 AC_UD_PUSH_CONSTANTS, va);
1475 }
1476 }
1477
1478 cmd_buffer->push_constant_stages &= ~stages;
1479 assert(cmd_buffer->cs->cdw <= cdw_max);
1480 }
1481
1482 static void
1483 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1484 bool pipeline_is_dirty)
1485 {
1486 if ((pipeline_is_dirty ||
1487 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1488 cmd_buffer->state.pipeline->vertex_elements.count &&
1489 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1490 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1491 unsigned vb_offset;
1492 void *vb_ptr;
1493 uint32_t i = 0;
1494 uint32_t count = velems->count;
1495 uint64_t va;
1496
1497 /* allocate some descriptor state for vertex buffers */
1498 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1499 &vb_offset, &vb_ptr))
1500 return;
1501
1502 for (i = 0; i < count; i++) {
1503 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1504 uint32_t offset;
1505 int vb = velems->binding[i];
1506 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1507 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1508
1509 va = radv_buffer_get_va(buffer->bo);
1510
1511 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1512 va += offset + buffer->offset;
1513 desc[0] = va;
1514 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1515 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1516 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1517 else
1518 desc[2] = buffer->size - offset;
1519 desc[3] = velems->rsrc_word3[i];
1520 }
1521
1522 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1523 va += vb_offset;
1524
1525 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1526 AC_UD_VS_VERTEX_BUFFERS, va);
1527
1528 cmd_buffer->state.vb_va = va;
1529 cmd_buffer->state.vb_size = count * 16;
1530 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1531 }
1532 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1533 }
1534
1535 static void
1536 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1537 {
1538 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1539 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1540 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1541 }
1542
1543 static void
1544 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1545 bool instanced_draw, bool indirect_draw,
1546 uint32_t draw_vertex_count)
1547 {
1548 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1549 struct radv_cmd_state *state = &cmd_buffer->state;
1550 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1551 uint32_t ia_multi_vgt_param;
1552 int32_t primitive_reset_en;
1553
1554 /* Draw state. */
1555 ia_multi_vgt_param =
1556 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1557 indirect_draw, draw_vertex_count);
1558
1559 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1560 if (info->chip_class >= GFX9) {
1561 radeon_set_uconfig_reg_idx(cs,
1562 R_030960_IA_MULTI_VGT_PARAM,
1563 4, ia_multi_vgt_param);
1564 } else if (info->chip_class >= CIK) {
1565 radeon_set_context_reg_idx(cs,
1566 R_028AA8_IA_MULTI_VGT_PARAM,
1567 1, ia_multi_vgt_param);
1568 } else {
1569 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1570 ia_multi_vgt_param);
1571 }
1572 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1573 }
1574
1575 /* Primitive restart. */
1576 primitive_reset_en =
1577 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1578
1579 if (primitive_reset_en != state->last_primitive_reset_en) {
1580 state->last_primitive_reset_en = primitive_reset_en;
1581 if (info->chip_class >= GFX9) {
1582 radeon_set_uconfig_reg(cs,
1583 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1584 primitive_reset_en);
1585 } else {
1586 radeon_set_context_reg(cs,
1587 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1588 primitive_reset_en);
1589 }
1590 }
1591
1592 if (primitive_reset_en) {
1593 uint32_t primitive_reset_index =
1594 state->index_type ? 0xffffffffu : 0xffffu;
1595
1596 if (primitive_reset_index != state->last_primitive_reset_index) {
1597 radeon_set_context_reg(cs,
1598 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1599 primitive_reset_index);
1600 state->last_primitive_reset_index = primitive_reset_index;
1601 }
1602 }
1603 }
1604
1605 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1606 VkPipelineStageFlags src_stage_mask)
1607 {
1608 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1609 VK_PIPELINE_STAGE_TRANSFER_BIT |
1610 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1611 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1612 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1613 }
1614
1615 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1616 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1617 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1618 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1619 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1620 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1621 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1622 VK_PIPELINE_STAGE_TRANSFER_BIT |
1623 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1624 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1625 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1626 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1627 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1628 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1629 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1630 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1631 }
1632 }
1633
1634 static enum radv_cmd_flush_bits
1635 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1636 VkAccessFlags src_flags)
1637 {
1638 enum radv_cmd_flush_bits flush_bits = 0;
1639 uint32_t b;
1640 for_each_bit(b, src_flags) {
1641 switch ((VkAccessFlagBits)(1 << b)) {
1642 case VK_ACCESS_SHADER_WRITE_BIT:
1643 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1644 break;
1645 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1646 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1647 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1648 break;
1649 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1651 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1652 break;
1653 case VK_ACCESS_TRANSFER_WRITE_BIT:
1654 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1655 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1656 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1657 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1658 RADV_CMD_FLAG_INV_GLOBAL_L2;
1659 break;
1660 default:
1661 break;
1662 }
1663 }
1664 return flush_bits;
1665 }
1666
1667 static enum radv_cmd_flush_bits
1668 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1669 VkAccessFlags dst_flags,
1670 struct radv_image *image)
1671 {
1672 enum radv_cmd_flush_bits flush_bits = 0;
1673 uint32_t b;
1674 for_each_bit(b, dst_flags) {
1675 switch ((VkAccessFlagBits)(1 << b)) {
1676 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1677 case VK_ACCESS_INDEX_READ_BIT:
1678 break;
1679 case VK_ACCESS_UNIFORM_READ_BIT:
1680 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1681 break;
1682 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1683 case VK_ACCESS_SHADER_READ_BIT:
1684 case VK_ACCESS_TRANSFER_READ_BIT:
1685 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1686 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1687 RADV_CMD_FLAG_INV_GLOBAL_L2;
1688 break;
1689 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1690 /* TODO: change to image && when the image gets passed
1691 * through from the subpass. */
1692 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1693 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1694 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1695 break;
1696 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1697 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1698 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1699 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1700 break;
1701 default:
1702 break;
1703 }
1704 }
1705 return flush_bits;
1706 }
1707
1708 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1709 {
1710 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1711 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1712 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1713 NULL);
1714 }
1715
1716 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1717 VkAttachmentReference att)
1718 {
1719 unsigned idx = att.attachment;
1720 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1721 VkImageSubresourceRange range;
1722 range.aspectMask = 0;
1723 range.baseMipLevel = view->base_mip;
1724 range.levelCount = 1;
1725 range.baseArrayLayer = view->base_layer;
1726 range.layerCount = cmd_buffer->state.framebuffer->layers;
1727
1728 radv_handle_image_transition(cmd_buffer,
1729 view->image,
1730 cmd_buffer->state.attachments[idx].current_layout,
1731 att.layout, 0, 0, &range,
1732 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1733
1734 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1735
1736
1737 }
1738
1739 void
1740 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1741 const struct radv_subpass *subpass, bool transitions)
1742 {
1743 if (transitions) {
1744 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1745
1746 for (unsigned i = 0; i < subpass->color_count; ++i) {
1747 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1748 radv_handle_subpass_image_transition(cmd_buffer,
1749 subpass->color_attachments[i]);
1750 }
1751
1752 for (unsigned i = 0; i < subpass->input_count; ++i) {
1753 radv_handle_subpass_image_transition(cmd_buffer,
1754 subpass->input_attachments[i]);
1755 }
1756
1757 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1758 radv_handle_subpass_image_transition(cmd_buffer,
1759 subpass->depth_stencil_attachment);
1760 }
1761 }
1762
1763 cmd_buffer->state.subpass = subpass;
1764
1765 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1766 }
1767
1768 static VkResult
1769 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1770 struct radv_render_pass *pass,
1771 const VkRenderPassBeginInfo *info)
1772 {
1773 struct radv_cmd_state *state = &cmd_buffer->state;
1774
1775 if (pass->attachment_count == 0) {
1776 state->attachments = NULL;
1777 return VK_SUCCESS;
1778 }
1779
1780 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1781 pass->attachment_count *
1782 sizeof(state->attachments[0]),
1783 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1784 if (state->attachments == NULL) {
1785 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1786 return cmd_buffer->record_result;
1787 }
1788
1789 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1790 struct radv_render_pass_attachment *att = &pass->attachments[i];
1791 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1792 VkImageAspectFlags clear_aspects = 0;
1793
1794 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1795 /* color attachment */
1796 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1797 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1798 }
1799 } else {
1800 /* depthstencil attachment */
1801 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1802 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1803 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1804 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1805 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1806 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1807 }
1808 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1809 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1810 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1811 }
1812 }
1813
1814 state->attachments[i].pending_clear_aspects = clear_aspects;
1815 state->attachments[i].cleared_views = 0;
1816 if (clear_aspects && info) {
1817 assert(info->clearValueCount > i);
1818 state->attachments[i].clear_value = info->pClearValues[i];
1819 }
1820
1821 state->attachments[i].current_layout = att->initial_layout;
1822 }
1823
1824 return VK_SUCCESS;
1825 }
1826
1827 VkResult radv_AllocateCommandBuffers(
1828 VkDevice _device,
1829 const VkCommandBufferAllocateInfo *pAllocateInfo,
1830 VkCommandBuffer *pCommandBuffers)
1831 {
1832 RADV_FROM_HANDLE(radv_device, device, _device);
1833 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1834
1835 VkResult result = VK_SUCCESS;
1836 uint32_t i;
1837
1838 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1839
1840 if (!list_empty(&pool->free_cmd_buffers)) {
1841 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1842
1843 list_del(&cmd_buffer->pool_link);
1844 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1845
1846 result = radv_reset_cmd_buffer(cmd_buffer);
1847 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1848 cmd_buffer->level = pAllocateInfo->level;
1849
1850 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1851 } else {
1852 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1853 &pCommandBuffers[i]);
1854 }
1855 if (result != VK_SUCCESS)
1856 break;
1857 }
1858
1859 if (result != VK_SUCCESS) {
1860 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1861 i, pCommandBuffers);
1862
1863 /* From the Vulkan 1.0.66 spec:
1864 *
1865 * "vkAllocateCommandBuffers can be used to create multiple
1866 * command buffers. If the creation of any of those command
1867 * buffers fails, the implementation must destroy all
1868 * successfully created command buffer objects from this
1869 * command, set all entries of the pCommandBuffers array to
1870 * NULL and return the error."
1871 */
1872 memset(pCommandBuffers, 0,
1873 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1874 }
1875
1876 return result;
1877 }
1878
1879 void radv_FreeCommandBuffers(
1880 VkDevice device,
1881 VkCommandPool commandPool,
1882 uint32_t commandBufferCount,
1883 const VkCommandBuffer *pCommandBuffers)
1884 {
1885 for (uint32_t i = 0; i < commandBufferCount; i++) {
1886 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1887
1888 if (cmd_buffer) {
1889 if (cmd_buffer->pool) {
1890 list_del(&cmd_buffer->pool_link);
1891 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1892 } else
1893 radv_cmd_buffer_destroy(cmd_buffer);
1894
1895 }
1896 }
1897 }
1898
1899 VkResult radv_ResetCommandBuffer(
1900 VkCommandBuffer commandBuffer,
1901 VkCommandBufferResetFlags flags)
1902 {
1903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1904 return radv_reset_cmd_buffer(cmd_buffer);
1905 }
1906
1907 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1908 {
1909 struct radv_device *device = cmd_buffer->device;
1910 if (device->gfx_init) {
1911 uint64_t va = radv_buffer_get_va(device->gfx_init);
1912 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1913 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1914 radeon_emit(cmd_buffer->cs, va);
1915 radeon_emit(cmd_buffer->cs, va >> 32);
1916 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1917 } else
1918 si_init_config(cmd_buffer);
1919 }
1920
1921 VkResult radv_BeginCommandBuffer(
1922 VkCommandBuffer commandBuffer,
1923 const VkCommandBufferBeginInfo *pBeginInfo)
1924 {
1925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1926 VkResult result = VK_SUCCESS;
1927
1928 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1929 /* If the command buffer has already been resetted with
1930 * vkResetCommandBuffer, no need to do it again.
1931 */
1932 result = radv_reset_cmd_buffer(cmd_buffer);
1933 if (result != VK_SUCCESS)
1934 return result;
1935 }
1936
1937 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1938 cmd_buffer->state.last_primitive_reset_en = -1;
1939 cmd_buffer->state.last_index_type = -1;
1940 cmd_buffer->state.last_num_instances = -1;
1941 cmd_buffer->state.last_vertex_offset = -1;
1942 cmd_buffer->state.last_first_instance = -1;
1943 cmd_buffer->usage_flags = pBeginInfo->flags;
1944
1945 /* setup initial configuration into command buffer */
1946 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1947 switch (cmd_buffer->queue_family_index) {
1948 case RADV_QUEUE_GENERAL:
1949 emit_gfx_buffer_state(cmd_buffer);
1950 break;
1951 case RADV_QUEUE_COMPUTE:
1952 si_init_compute(cmd_buffer);
1953 break;
1954 case RADV_QUEUE_TRANSFER:
1955 default:
1956 break;
1957 }
1958 }
1959
1960 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1961 assert(pBeginInfo->pInheritanceInfo);
1962 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1963 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1964
1965 struct radv_subpass *subpass =
1966 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1967
1968 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1969 if (result != VK_SUCCESS)
1970 return result;
1971
1972 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1973 }
1974
1975 if (unlikely(cmd_buffer->device->trace_bo))
1976 radv_cmd_buffer_trace_emit(cmd_buffer);
1977
1978 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1979
1980 return result;
1981 }
1982
1983 void radv_CmdBindVertexBuffers(
1984 VkCommandBuffer commandBuffer,
1985 uint32_t firstBinding,
1986 uint32_t bindingCount,
1987 const VkBuffer* pBuffers,
1988 const VkDeviceSize* pOffsets)
1989 {
1990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1991 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1992 bool changed = false;
1993
1994 /* We have to defer setting up vertex buffer since we need the buffer
1995 * stride from the pipeline. */
1996
1997 assert(firstBinding + bindingCount <= MAX_VBS);
1998 for (uint32_t i = 0; i < bindingCount; i++) {
1999 uint32_t idx = firstBinding + i;
2000
2001 if (!changed &&
2002 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2003 vb[idx].offset != pOffsets[i])) {
2004 changed = true;
2005 }
2006
2007 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2008 vb[idx].offset = pOffsets[i];
2009
2010 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2011 vb[idx].buffer->bo, 8);
2012 }
2013
2014 if (!changed) {
2015 /* No state changes. */
2016 return;
2017 }
2018
2019 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2020 }
2021
2022 void radv_CmdBindIndexBuffer(
2023 VkCommandBuffer commandBuffer,
2024 VkBuffer buffer,
2025 VkDeviceSize offset,
2026 VkIndexType indexType)
2027 {
2028 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2029 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2030
2031 if (cmd_buffer->state.index_buffer == index_buffer &&
2032 cmd_buffer->state.index_offset == offset &&
2033 cmd_buffer->state.index_type == indexType) {
2034 /* No state changes. */
2035 return;
2036 }
2037
2038 cmd_buffer->state.index_buffer = index_buffer;
2039 cmd_buffer->state.index_offset = offset;
2040 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2041 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2042 cmd_buffer->state.index_va += index_buffer->offset + offset;
2043
2044 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2045 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2046 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2047 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2048 }
2049
2050
2051 static void
2052 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2053 VkPipelineBindPoint bind_point,
2054 struct radv_descriptor_set *set, unsigned idx)
2055 {
2056 struct radeon_winsys *ws = cmd_buffer->device->ws;
2057
2058 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2059 if (!set)
2060 return;
2061
2062 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2063
2064 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2065 if (set->descriptors[j])
2066 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2067
2068 if(set->bo)
2069 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2070 }
2071
2072 void radv_CmdBindDescriptorSets(
2073 VkCommandBuffer commandBuffer,
2074 VkPipelineBindPoint pipelineBindPoint,
2075 VkPipelineLayout _layout,
2076 uint32_t firstSet,
2077 uint32_t descriptorSetCount,
2078 const VkDescriptorSet* pDescriptorSets,
2079 uint32_t dynamicOffsetCount,
2080 const uint32_t* pDynamicOffsets)
2081 {
2082 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2083 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2084 unsigned dyn_idx = 0;
2085
2086 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2087 unsigned idx = i + firstSet;
2088 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2089 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2090
2091 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2092 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2093 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2094 assert(dyn_idx < dynamicOffsetCount);
2095
2096 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2097 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2098 dst[0] = va;
2099 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2100 dst[2] = range->size;
2101 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2102 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2103 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2104 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2105 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2107 cmd_buffer->push_constant_stages |=
2108 set->layout->dynamic_shader_stages;
2109 }
2110 }
2111 }
2112
2113 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2114 struct radv_descriptor_set *set,
2115 struct radv_descriptor_set_layout *layout,
2116 VkPipelineBindPoint bind_point)
2117 {
2118 struct radv_descriptor_state *descriptors_state =
2119 radv_get_descriptors_state(cmd_buffer, bind_point);
2120 set->size = layout->size;
2121 set->layout = layout;
2122
2123 if (descriptors_state->push_set.capacity < set->size) {
2124 size_t new_size = MAX2(set->size, 1024);
2125 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2126 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2127
2128 free(set->mapped_ptr);
2129 set->mapped_ptr = malloc(new_size);
2130
2131 if (!set->mapped_ptr) {
2132 descriptors_state->push_set.capacity = 0;
2133 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2134 return false;
2135 }
2136
2137 descriptors_state->push_set.capacity = new_size;
2138 }
2139
2140 return true;
2141 }
2142
2143 void radv_meta_push_descriptor_set(
2144 struct radv_cmd_buffer* cmd_buffer,
2145 VkPipelineBindPoint pipelineBindPoint,
2146 VkPipelineLayout _layout,
2147 uint32_t set,
2148 uint32_t descriptorWriteCount,
2149 const VkWriteDescriptorSet* pDescriptorWrites)
2150 {
2151 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2152 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2153 unsigned bo_offset;
2154
2155 assert(set == 0);
2156 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2157
2158 push_set->size = layout->set[set].layout->size;
2159 push_set->layout = layout->set[set].layout;
2160
2161 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2162 &bo_offset,
2163 (void**) &push_set->mapped_ptr))
2164 return;
2165
2166 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2167 push_set->va += bo_offset;
2168
2169 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2170 radv_descriptor_set_to_handle(push_set),
2171 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2172
2173 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2174 }
2175
2176 void radv_CmdPushDescriptorSetKHR(
2177 VkCommandBuffer commandBuffer,
2178 VkPipelineBindPoint pipelineBindPoint,
2179 VkPipelineLayout _layout,
2180 uint32_t set,
2181 uint32_t descriptorWriteCount,
2182 const VkWriteDescriptorSet* pDescriptorWrites)
2183 {
2184 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2185 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2186 struct radv_descriptor_state *descriptors_state =
2187 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2188 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2189
2190 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2191
2192 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2193 layout->set[set].layout,
2194 pipelineBindPoint))
2195 return;
2196
2197 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2198 radv_descriptor_set_to_handle(push_set),
2199 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2200
2201 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2202 descriptors_state->push_dirty = true;
2203 }
2204
2205 void radv_CmdPushDescriptorSetWithTemplateKHR(
2206 VkCommandBuffer commandBuffer,
2207 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2208 VkPipelineLayout _layout,
2209 uint32_t set,
2210 const void* pData)
2211 {
2212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2213 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2214 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2215 struct radv_descriptor_state *descriptors_state =
2216 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2217 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2218
2219 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2220
2221 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2222 layout->set[set].layout,
2223 templ->bind_point))
2224 return;
2225
2226 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2227 descriptorUpdateTemplate, pData);
2228
2229 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2230 descriptors_state->push_dirty = true;
2231 }
2232
2233 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2234 VkPipelineLayout layout,
2235 VkShaderStageFlags stageFlags,
2236 uint32_t offset,
2237 uint32_t size,
2238 const void* pValues)
2239 {
2240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2241 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2242 cmd_buffer->push_constant_stages |= stageFlags;
2243 }
2244
2245 VkResult radv_EndCommandBuffer(
2246 VkCommandBuffer commandBuffer)
2247 {
2248 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2249
2250 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2251 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2253 si_emit_cache_flush(cmd_buffer);
2254 }
2255
2256 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2257
2258 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2259 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2260
2261 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2262
2263 return cmd_buffer->record_result;
2264 }
2265
2266 static void
2267 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2268 {
2269 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2270
2271 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2272 return;
2273
2274 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2275
2276 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2277 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2278
2279 cmd_buffer->compute_scratch_size_needed =
2280 MAX2(cmd_buffer->compute_scratch_size_needed,
2281 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2282
2283 if (unlikely(cmd_buffer->device->trace_bo))
2284 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2285 }
2286
2287 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2288 VkPipelineBindPoint bind_point)
2289 {
2290 struct radv_descriptor_state *descriptors_state =
2291 radv_get_descriptors_state(cmd_buffer, bind_point);
2292
2293 descriptors_state->dirty |= descriptors_state->valid;
2294 }
2295
2296 void radv_CmdBindPipeline(
2297 VkCommandBuffer commandBuffer,
2298 VkPipelineBindPoint pipelineBindPoint,
2299 VkPipeline _pipeline)
2300 {
2301 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2302 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2303
2304 switch (pipelineBindPoint) {
2305 case VK_PIPELINE_BIND_POINT_COMPUTE:
2306 if (cmd_buffer->state.compute_pipeline == pipeline)
2307 return;
2308 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2309
2310 cmd_buffer->state.compute_pipeline = pipeline;
2311 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2312 break;
2313 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2314 if (cmd_buffer->state.pipeline == pipeline)
2315 return;
2316 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2317
2318 cmd_buffer->state.pipeline = pipeline;
2319 if (!pipeline)
2320 break;
2321
2322 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2323 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2324
2325 /* the new vertex shader might not have the same user regs */
2326 cmd_buffer->state.last_first_instance = -1;
2327 cmd_buffer->state.last_vertex_offset = -1;
2328
2329 /* Prefetch all pipeline shaders at first draw time. */
2330 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2331
2332 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2333
2334 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2335 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2336 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2337 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2338
2339 if (radv_pipeline_has_tess(pipeline))
2340 cmd_buffer->tess_rings_needed = true;
2341
2342 if (radv_pipeline_has_gs(pipeline)) {
2343 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2344 AC_UD_SCRATCH_RING_OFFSETS);
2345 if (cmd_buffer->ring_offsets_idx == -1)
2346 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2347 else if (loc->sgpr_idx != -1)
2348 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2349 }
2350 break;
2351 default:
2352 assert(!"invalid bind point");
2353 break;
2354 }
2355 }
2356
2357 void radv_CmdSetViewport(
2358 VkCommandBuffer commandBuffer,
2359 uint32_t firstViewport,
2360 uint32_t viewportCount,
2361 const VkViewport* pViewports)
2362 {
2363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2364 struct radv_cmd_state *state = &cmd_buffer->state;
2365 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2366
2367 assert(firstViewport < MAX_VIEWPORTS);
2368 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2369
2370 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2371 /* Try to skip unnecessary PS partial flushes when the viewports
2372 * don't change.
2373 */
2374 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2375 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2376 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2377 pViewports, viewportCount * sizeof(*pViewports))) {
2378 return;
2379 }
2380 }
2381
2382 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2383 viewportCount * sizeof(*pViewports));
2384
2385 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2386 }
2387
2388 void radv_CmdSetScissor(
2389 VkCommandBuffer commandBuffer,
2390 uint32_t firstScissor,
2391 uint32_t scissorCount,
2392 const VkRect2D* pScissors)
2393 {
2394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2395 struct radv_cmd_state *state = &cmd_buffer->state;
2396 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2397
2398 assert(firstScissor < MAX_SCISSORS);
2399 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2400
2401 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2402 /* Try to skip unnecessary PS partial flushes when the scissors
2403 * don't change.
2404 */
2405 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2406 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2407 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2408 pScissors, scissorCount * sizeof(*pScissors))) {
2409 return;
2410 }
2411 }
2412
2413 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2414 scissorCount * sizeof(*pScissors));
2415
2416 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2417 }
2418
2419 void radv_CmdSetLineWidth(
2420 VkCommandBuffer commandBuffer,
2421 float lineWidth)
2422 {
2423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2424 cmd_buffer->state.dynamic.line_width = lineWidth;
2425 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2426 }
2427
2428 void radv_CmdSetDepthBias(
2429 VkCommandBuffer commandBuffer,
2430 float depthBiasConstantFactor,
2431 float depthBiasClamp,
2432 float depthBiasSlopeFactor)
2433 {
2434 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2435
2436 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2437 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2438 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2439
2440 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2441 }
2442
2443 void radv_CmdSetBlendConstants(
2444 VkCommandBuffer commandBuffer,
2445 const float blendConstants[4])
2446 {
2447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2448
2449 memcpy(cmd_buffer->state.dynamic.blend_constants,
2450 blendConstants, sizeof(float) * 4);
2451
2452 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2453 }
2454
2455 void radv_CmdSetDepthBounds(
2456 VkCommandBuffer commandBuffer,
2457 float minDepthBounds,
2458 float maxDepthBounds)
2459 {
2460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2461
2462 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2463 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2464
2465 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2466 }
2467
2468 void radv_CmdSetStencilCompareMask(
2469 VkCommandBuffer commandBuffer,
2470 VkStencilFaceFlags faceMask,
2471 uint32_t compareMask)
2472 {
2473 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2474
2475 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2476 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2477 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2478 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2479
2480 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2481 }
2482
2483 void radv_CmdSetStencilWriteMask(
2484 VkCommandBuffer commandBuffer,
2485 VkStencilFaceFlags faceMask,
2486 uint32_t writeMask)
2487 {
2488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2489
2490 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2491 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2492 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2493 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2494
2495 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2496 }
2497
2498 void radv_CmdSetStencilReference(
2499 VkCommandBuffer commandBuffer,
2500 VkStencilFaceFlags faceMask,
2501 uint32_t reference)
2502 {
2503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2504
2505 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2506 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2507 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2508 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2509
2510 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2511 }
2512
2513 void radv_CmdSetDiscardRectangleEXT(
2514 VkCommandBuffer commandBuffer,
2515 uint32_t firstDiscardRectangle,
2516 uint32_t discardRectangleCount,
2517 const VkRect2D* pDiscardRectangles)
2518 {
2519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2520 struct radv_cmd_state *state = &cmd_buffer->state;
2521 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2522
2523 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2524 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2525
2526 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2527 pDiscardRectangles, discardRectangleCount);
2528
2529 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2530 }
2531
2532 void radv_CmdExecuteCommands(
2533 VkCommandBuffer commandBuffer,
2534 uint32_t commandBufferCount,
2535 const VkCommandBuffer* pCmdBuffers)
2536 {
2537 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2538
2539 assert(commandBufferCount > 0);
2540
2541 /* Emit pending flushes on primary prior to executing secondary */
2542 si_emit_cache_flush(primary);
2543
2544 for (uint32_t i = 0; i < commandBufferCount; i++) {
2545 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2546
2547 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2548 secondary->scratch_size_needed);
2549 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2550 secondary->compute_scratch_size_needed);
2551
2552 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2553 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2554 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2555 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2556 if (secondary->tess_rings_needed)
2557 primary->tess_rings_needed = true;
2558 if (secondary->sample_positions_needed)
2559 primary->sample_positions_needed = true;
2560
2561 if (secondary->ring_offsets_idx != -1) {
2562 if (primary->ring_offsets_idx == -1)
2563 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2564 else
2565 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2566 }
2567 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2568
2569
2570 /* When the secondary command buffer is compute only we don't
2571 * need to re-emit the current graphics pipeline.
2572 */
2573 if (secondary->state.emitted_pipeline) {
2574 primary->state.emitted_pipeline =
2575 secondary->state.emitted_pipeline;
2576 }
2577
2578 /* When the secondary command buffer is graphics only we don't
2579 * need to re-emit the current compute pipeline.
2580 */
2581 if (secondary->state.emitted_compute_pipeline) {
2582 primary->state.emitted_compute_pipeline =
2583 secondary->state.emitted_compute_pipeline;
2584 }
2585
2586 /* Only re-emit the draw packets when needed. */
2587 if (secondary->state.last_primitive_reset_en != -1) {
2588 primary->state.last_primitive_reset_en =
2589 secondary->state.last_primitive_reset_en;
2590 }
2591
2592 if (secondary->state.last_primitive_reset_index) {
2593 primary->state.last_primitive_reset_index =
2594 secondary->state.last_primitive_reset_index;
2595 }
2596
2597 if (secondary->state.last_ia_multi_vgt_param) {
2598 primary->state.last_ia_multi_vgt_param =
2599 secondary->state.last_ia_multi_vgt_param;
2600 }
2601
2602 if (secondary->state.last_first_instance != -1) {
2603 primary->state.last_first_instance =
2604 secondary->state.last_first_instance;
2605 }
2606
2607 if (secondary->state.last_num_instances != -1) {
2608 primary->state.last_num_instances =
2609 secondary->state.last_num_instances;
2610 }
2611
2612 if (secondary->state.last_vertex_offset != -1) {
2613 primary->state.last_vertex_offset =
2614 secondary->state.last_vertex_offset;
2615 }
2616
2617 if (secondary->state.last_index_type != -1) {
2618 primary->state.last_index_type =
2619 secondary->state.last_index_type;
2620 }
2621 }
2622
2623 /* After executing commands from secondary buffers we have to dirty
2624 * some states.
2625 */
2626 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2627 RADV_CMD_DIRTY_INDEX_BUFFER |
2628 RADV_CMD_DIRTY_DYNAMIC_ALL;
2629 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2630 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2631 }
2632
2633 VkResult radv_CreateCommandPool(
2634 VkDevice _device,
2635 const VkCommandPoolCreateInfo* pCreateInfo,
2636 const VkAllocationCallbacks* pAllocator,
2637 VkCommandPool* pCmdPool)
2638 {
2639 RADV_FROM_HANDLE(radv_device, device, _device);
2640 struct radv_cmd_pool *pool;
2641
2642 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2643 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2644 if (pool == NULL)
2645 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2646
2647 if (pAllocator)
2648 pool->alloc = *pAllocator;
2649 else
2650 pool->alloc = device->alloc;
2651
2652 list_inithead(&pool->cmd_buffers);
2653 list_inithead(&pool->free_cmd_buffers);
2654
2655 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2656
2657 *pCmdPool = radv_cmd_pool_to_handle(pool);
2658
2659 return VK_SUCCESS;
2660
2661 }
2662
2663 void radv_DestroyCommandPool(
2664 VkDevice _device,
2665 VkCommandPool commandPool,
2666 const VkAllocationCallbacks* pAllocator)
2667 {
2668 RADV_FROM_HANDLE(radv_device, device, _device);
2669 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2670
2671 if (!pool)
2672 return;
2673
2674 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2675 &pool->cmd_buffers, pool_link) {
2676 radv_cmd_buffer_destroy(cmd_buffer);
2677 }
2678
2679 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2680 &pool->free_cmd_buffers, pool_link) {
2681 radv_cmd_buffer_destroy(cmd_buffer);
2682 }
2683
2684 vk_free2(&device->alloc, pAllocator, pool);
2685 }
2686
2687 VkResult radv_ResetCommandPool(
2688 VkDevice device,
2689 VkCommandPool commandPool,
2690 VkCommandPoolResetFlags flags)
2691 {
2692 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2693 VkResult result;
2694
2695 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2696 &pool->cmd_buffers, pool_link) {
2697 result = radv_reset_cmd_buffer(cmd_buffer);
2698 if (result != VK_SUCCESS)
2699 return result;
2700 }
2701
2702 return VK_SUCCESS;
2703 }
2704
2705 void radv_TrimCommandPool(
2706 VkDevice device,
2707 VkCommandPool commandPool,
2708 VkCommandPoolTrimFlagsKHR flags)
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2711
2712 if (!pool)
2713 return;
2714
2715 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2716 &pool->free_cmd_buffers, pool_link) {
2717 radv_cmd_buffer_destroy(cmd_buffer);
2718 }
2719 }
2720
2721 void radv_CmdBeginRenderPass(
2722 VkCommandBuffer commandBuffer,
2723 const VkRenderPassBeginInfo* pRenderPassBegin,
2724 VkSubpassContents contents)
2725 {
2726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2727 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2728 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2729
2730 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2731 cmd_buffer->cs, 2048);
2732 MAYBE_UNUSED VkResult result;
2733
2734 cmd_buffer->state.framebuffer = framebuffer;
2735 cmd_buffer->state.pass = pass;
2736 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2737
2738 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2739 if (result != VK_SUCCESS)
2740 return;
2741
2742 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2743 assert(cmd_buffer->cs->cdw <= cdw_max);
2744
2745 radv_cmd_buffer_clear_subpass(cmd_buffer);
2746 }
2747
2748 void radv_CmdNextSubpass(
2749 VkCommandBuffer commandBuffer,
2750 VkSubpassContents contents)
2751 {
2752 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2753
2754 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2755
2756 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2757 2048);
2758
2759 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2760 radv_cmd_buffer_clear_subpass(cmd_buffer);
2761 }
2762
2763 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2764 {
2765 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2766 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2767 if (!pipeline->shaders[stage])
2768 continue;
2769 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2770 if (loc->sgpr_idx == -1)
2771 continue;
2772 uint32_t base_reg = pipeline->user_data_0[stage];
2773 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2774
2775 }
2776 if (pipeline->gs_copy_shader) {
2777 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2778 if (loc->sgpr_idx != -1) {
2779 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2780 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2781 }
2782 }
2783 }
2784
2785 static void
2786 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2787 uint32_t vertex_count)
2788 {
2789 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2790 radeon_emit(cmd_buffer->cs, vertex_count);
2791 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2792 S_0287F0_USE_OPAQUE(0));
2793 }
2794
2795 static void
2796 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2797 uint64_t index_va,
2798 uint32_t index_count)
2799 {
2800 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2801 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2802 radeon_emit(cmd_buffer->cs, index_va);
2803 radeon_emit(cmd_buffer->cs, index_va >> 32);
2804 radeon_emit(cmd_buffer->cs, index_count);
2805 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2806 }
2807
2808 static void
2809 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2810 bool indexed,
2811 uint32_t draw_count,
2812 uint64_t count_va,
2813 uint32_t stride)
2814 {
2815 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2816 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2817 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2818 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2819 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2820 assert(base_reg);
2821
2822 /* just reset draw state for vertex data */
2823 cmd_buffer->state.last_first_instance = -1;
2824 cmd_buffer->state.last_num_instances = -1;
2825 cmd_buffer->state.last_vertex_offset = -1;
2826
2827 if (draw_count == 1 && !count_va && !draw_id_enable) {
2828 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2829 PKT3_DRAW_INDIRECT, 3, false));
2830 radeon_emit(cs, 0);
2831 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2832 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2833 radeon_emit(cs, di_src_sel);
2834 } else {
2835 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2836 PKT3_DRAW_INDIRECT_MULTI,
2837 8, false));
2838 radeon_emit(cs, 0);
2839 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2840 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2841 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2842 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2843 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2844 radeon_emit(cs, draw_count); /* count */
2845 radeon_emit(cs, count_va); /* count_addr */
2846 radeon_emit(cs, count_va >> 32);
2847 radeon_emit(cs, stride); /* stride */
2848 radeon_emit(cs, di_src_sel);
2849 }
2850 }
2851
2852 struct radv_draw_info {
2853 /**
2854 * Number of vertices.
2855 */
2856 uint32_t count;
2857
2858 /**
2859 * Index of the first vertex.
2860 */
2861 int32_t vertex_offset;
2862
2863 /**
2864 * First instance id.
2865 */
2866 uint32_t first_instance;
2867
2868 /**
2869 * Number of instances.
2870 */
2871 uint32_t instance_count;
2872
2873 /**
2874 * First index (indexed draws only).
2875 */
2876 uint32_t first_index;
2877
2878 /**
2879 * Whether it's an indexed draw.
2880 */
2881 bool indexed;
2882
2883 /**
2884 * Indirect draw parameters resource.
2885 */
2886 struct radv_buffer *indirect;
2887 uint64_t indirect_offset;
2888 uint32_t stride;
2889
2890 /**
2891 * Draw count parameters resource.
2892 */
2893 struct radv_buffer *count_buffer;
2894 uint64_t count_buffer_offset;
2895 };
2896
2897 static void
2898 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2899 const struct radv_draw_info *info)
2900 {
2901 struct radv_cmd_state *state = &cmd_buffer->state;
2902 struct radeon_winsys *ws = cmd_buffer->device->ws;
2903 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2904
2905 if (info->indirect) {
2906 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2907 uint64_t count_va = 0;
2908
2909 va += info->indirect->offset + info->indirect_offset;
2910
2911 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2912
2913 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2914 radeon_emit(cs, 1);
2915 radeon_emit(cs, va);
2916 radeon_emit(cs, va >> 32);
2917
2918 if (info->count_buffer) {
2919 count_va = radv_buffer_get_va(info->count_buffer->bo);
2920 count_va += info->count_buffer->offset +
2921 info->count_buffer_offset;
2922
2923 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2924 }
2925
2926 if (!state->subpass->view_mask) {
2927 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2928 info->indexed,
2929 info->count,
2930 count_va,
2931 info->stride);
2932 } else {
2933 unsigned i;
2934 for_each_bit(i, state->subpass->view_mask) {
2935 radv_emit_view_index(cmd_buffer, i);
2936
2937 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2938 info->indexed,
2939 info->count,
2940 count_va,
2941 info->stride);
2942 }
2943 }
2944 } else {
2945 assert(state->pipeline->graphics.vtx_base_sgpr);
2946
2947 if (info->vertex_offset != state->last_vertex_offset ||
2948 info->first_instance != state->last_first_instance) {
2949 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2950 state->pipeline->graphics.vtx_emit_num);
2951
2952 radeon_emit(cs, info->vertex_offset);
2953 radeon_emit(cs, info->first_instance);
2954 if (state->pipeline->graphics.vtx_emit_num == 3)
2955 radeon_emit(cs, 0);
2956 state->last_first_instance = info->first_instance;
2957 state->last_vertex_offset = info->vertex_offset;
2958 }
2959
2960 if (state->last_num_instances != info->instance_count) {
2961 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2962 radeon_emit(cs, info->instance_count);
2963 state->last_num_instances = info->instance_count;
2964 }
2965
2966 if (info->indexed) {
2967 int index_size = state->index_type ? 4 : 2;
2968 uint64_t index_va;
2969
2970 index_va = state->index_va;
2971 index_va += info->first_index * index_size;
2972
2973 if (!state->subpass->view_mask) {
2974 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2975 index_va,
2976 info->count);
2977 } else {
2978 unsigned i;
2979 for_each_bit(i, state->subpass->view_mask) {
2980 radv_emit_view_index(cmd_buffer, i);
2981
2982 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2983 index_va,
2984 info->count);
2985 }
2986 }
2987 } else {
2988 if (!state->subpass->view_mask) {
2989 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2990 } else {
2991 unsigned i;
2992 for_each_bit(i, state->subpass->view_mask) {
2993 radv_emit_view_index(cmd_buffer, i);
2994
2995 radv_cs_emit_draw_packet(cmd_buffer,
2996 info->count);
2997 }
2998 }
2999 }
3000 }
3001 }
3002
3003 static void
3004 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3005 const struct radv_draw_info *info)
3006 {
3007 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3008 radv_emit_graphics_pipeline(cmd_buffer);
3009
3010 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3011 radv_emit_framebuffer_state(cmd_buffer);
3012
3013 if (info->indexed) {
3014 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3015 radv_emit_index_buffer(cmd_buffer);
3016 } else {
3017 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3018 * so the state must be re-emitted before the next indexed
3019 * draw.
3020 */
3021 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3022 cmd_buffer->state.last_index_type = -1;
3023 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3024 }
3025 }
3026
3027 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3028
3029 radv_emit_draw_registers(cmd_buffer, info->indexed,
3030 info->instance_count > 1, info->indirect,
3031 info->indirect ? 0 : info->count);
3032 }
3033
3034 static void
3035 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3036 const struct radv_draw_info *info)
3037 {
3038 bool has_prefetch =
3039 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3040 bool pipeline_is_dirty =
3041 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3042 cmd_buffer->state.pipeline &&
3043 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3044
3045 MAYBE_UNUSED unsigned cdw_max =
3046 radeon_check_space(cmd_buffer->device->ws,
3047 cmd_buffer->cs, 4096);
3048
3049 /* Use optimal packet order based on whether we need to sync the
3050 * pipeline.
3051 */
3052 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3053 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3054 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3055 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3056 /* If we have to wait for idle, set all states first, so that
3057 * all SET packets are processed in parallel with previous draw
3058 * calls. Then upload descriptors, set shader pointers, and
3059 * draw, and prefetch at the end. This ensures that the time
3060 * the CUs are idle is very short. (there are only SET_SH
3061 * packets between the wait and the draw)
3062 */
3063 radv_emit_all_graphics_states(cmd_buffer, info);
3064 si_emit_cache_flush(cmd_buffer);
3065 /* <-- CUs are idle here --> */
3066
3067 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3068
3069 radv_emit_draw_packets(cmd_buffer, info);
3070 /* <-- CUs are busy here --> */
3071
3072 /* Start prefetches after the draw has been started. Both will
3073 * run in parallel, but starting the draw first is more
3074 * important.
3075 */
3076 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3077 radv_emit_prefetch_L2(cmd_buffer,
3078 cmd_buffer->state.pipeline, false);
3079 }
3080 } else {
3081 /* If we don't wait for idle, start prefetches first, then set
3082 * states, and draw at the end.
3083 */
3084 si_emit_cache_flush(cmd_buffer);
3085
3086 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3087 /* Only prefetch the vertex shader and VBO descriptors
3088 * in order to start the draw as soon as possible.
3089 */
3090 radv_emit_prefetch_L2(cmd_buffer,
3091 cmd_buffer->state.pipeline, true);
3092 }
3093
3094 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3095
3096 radv_emit_all_graphics_states(cmd_buffer, info);
3097 radv_emit_draw_packets(cmd_buffer, info);
3098
3099 /* Prefetch the remaining shaders after the draw has been
3100 * started.
3101 */
3102 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3103 radv_emit_prefetch_L2(cmd_buffer,
3104 cmd_buffer->state.pipeline, false);
3105 }
3106 }
3107
3108 assert(cmd_buffer->cs->cdw <= cdw_max);
3109 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3110 }
3111
3112 void radv_CmdDraw(
3113 VkCommandBuffer commandBuffer,
3114 uint32_t vertexCount,
3115 uint32_t instanceCount,
3116 uint32_t firstVertex,
3117 uint32_t firstInstance)
3118 {
3119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3120 struct radv_draw_info info = {};
3121
3122 info.count = vertexCount;
3123 info.instance_count = instanceCount;
3124 info.first_instance = firstInstance;
3125 info.vertex_offset = firstVertex;
3126
3127 radv_draw(cmd_buffer, &info);
3128 }
3129
3130 void radv_CmdDrawIndexed(
3131 VkCommandBuffer commandBuffer,
3132 uint32_t indexCount,
3133 uint32_t instanceCount,
3134 uint32_t firstIndex,
3135 int32_t vertexOffset,
3136 uint32_t firstInstance)
3137 {
3138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3139 struct radv_draw_info info = {};
3140
3141 info.indexed = true;
3142 info.count = indexCount;
3143 info.instance_count = instanceCount;
3144 info.first_index = firstIndex;
3145 info.vertex_offset = vertexOffset;
3146 info.first_instance = firstInstance;
3147
3148 radv_draw(cmd_buffer, &info);
3149 }
3150
3151 void radv_CmdDrawIndirect(
3152 VkCommandBuffer commandBuffer,
3153 VkBuffer _buffer,
3154 VkDeviceSize offset,
3155 uint32_t drawCount,
3156 uint32_t stride)
3157 {
3158 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3159 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3160 struct radv_draw_info info = {};
3161
3162 info.count = drawCount;
3163 info.indirect = buffer;
3164 info.indirect_offset = offset;
3165 info.stride = stride;
3166
3167 radv_draw(cmd_buffer, &info);
3168 }
3169
3170 void radv_CmdDrawIndexedIndirect(
3171 VkCommandBuffer commandBuffer,
3172 VkBuffer _buffer,
3173 VkDeviceSize offset,
3174 uint32_t drawCount,
3175 uint32_t stride)
3176 {
3177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3178 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3179 struct radv_draw_info info = {};
3180
3181 info.indexed = true;
3182 info.count = drawCount;
3183 info.indirect = buffer;
3184 info.indirect_offset = offset;
3185 info.stride = stride;
3186
3187 radv_draw(cmd_buffer, &info);
3188 }
3189
3190 void radv_CmdDrawIndirectCountAMD(
3191 VkCommandBuffer commandBuffer,
3192 VkBuffer _buffer,
3193 VkDeviceSize offset,
3194 VkBuffer _countBuffer,
3195 VkDeviceSize countBufferOffset,
3196 uint32_t maxDrawCount,
3197 uint32_t stride)
3198 {
3199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3200 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3201 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3202 struct radv_draw_info info = {};
3203
3204 info.count = maxDrawCount;
3205 info.indirect = buffer;
3206 info.indirect_offset = offset;
3207 info.count_buffer = count_buffer;
3208 info.count_buffer_offset = countBufferOffset;
3209 info.stride = stride;
3210
3211 radv_draw(cmd_buffer, &info);
3212 }
3213
3214 void radv_CmdDrawIndexedIndirectCountAMD(
3215 VkCommandBuffer commandBuffer,
3216 VkBuffer _buffer,
3217 VkDeviceSize offset,
3218 VkBuffer _countBuffer,
3219 VkDeviceSize countBufferOffset,
3220 uint32_t maxDrawCount,
3221 uint32_t stride)
3222 {
3223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3224 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3225 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3226 struct radv_draw_info info = {};
3227
3228 info.indexed = true;
3229 info.count = maxDrawCount;
3230 info.indirect = buffer;
3231 info.indirect_offset = offset;
3232 info.count_buffer = count_buffer;
3233 info.count_buffer_offset = countBufferOffset;
3234 info.stride = stride;
3235
3236 radv_draw(cmd_buffer, &info);
3237 }
3238
3239 struct radv_dispatch_info {
3240 /**
3241 * Determine the layout of the grid (in block units) to be used.
3242 */
3243 uint32_t blocks[3];
3244
3245 /**
3246 * A starting offset for the grid. If unaligned is set, the offset
3247 * must still be aligned.
3248 */
3249 uint32_t offsets[3];
3250 /**
3251 * Whether it's an unaligned compute dispatch.
3252 */
3253 bool unaligned;
3254
3255 /**
3256 * Indirect compute parameters resource.
3257 */
3258 struct radv_buffer *indirect;
3259 uint64_t indirect_offset;
3260 };
3261
3262 static void
3263 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3264 const struct radv_dispatch_info *info)
3265 {
3266 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3267 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3268 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3269 struct radeon_winsys *ws = cmd_buffer->device->ws;
3270 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3271 struct radv_userdata_info *loc;
3272
3273 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3274 AC_UD_CS_GRID_SIZE);
3275
3276 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3277
3278 if (info->indirect) {
3279 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3280
3281 va += info->indirect->offset + info->indirect_offset;
3282
3283 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3284
3285 if (loc->sgpr_idx != -1) {
3286 for (unsigned i = 0; i < 3; ++i) {
3287 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3288 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3289 COPY_DATA_DST_SEL(COPY_DATA_REG));
3290 radeon_emit(cs, (va + 4 * i));
3291 radeon_emit(cs, (va + 4 * i) >> 32);
3292 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3293 + loc->sgpr_idx * 4) >> 2) + i);
3294 radeon_emit(cs, 0);
3295 }
3296 }
3297
3298 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3299 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3300 PKT3_SHADER_TYPE_S(1));
3301 radeon_emit(cs, va);
3302 radeon_emit(cs, va >> 32);
3303 radeon_emit(cs, dispatch_initiator);
3304 } else {
3305 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3306 PKT3_SHADER_TYPE_S(1));
3307 radeon_emit(cs, 1);
3308 radeon_emit(cs, va);
3309 radeon_emit(cs, va >> 32);
3310
3311 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3312 PKT3_SHADER_TYPE_S(1));
3313 radeon_emit(cs, 0);
3314 radeon_emit(cs, dispatch_initiator);
3315 }
3316 } else {
3317 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3318 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3319
3320 if (info->unaligned) {
3321 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3322 unsigned remainder[3];
3323
3324 /* If aligned, these should be an entire block size,
3325 * not 0.
3326 */
3327 remainder[0] = blocks[0] + cs_block_size[0] -
3328 align_u32_npot(blocks[0], cs_block_size[0]);
3329 remainder[1] = blocks[1] + cs_block_size[1] -
3330 align_u32_npot(blocks[1], cs_block_size[1]);
3331 remainder[2] = blocks[2] + cs_block_size[2] -
3332 align_u32_npot(blocks[2], cs_block_size[2]);
3333
3334 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3335 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3336 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3337
3338 for(unsigned i = 0; i < 3; ++i) {
3339 assert(offsets[i] % cs_block_size[i] == 0);
3340 offsets[i] /= cs_block_size[i];
3341 }
3342
3343 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3344 radeon_emit(cs,
3345 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3346 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3347 radeon_emit(cs,
3348 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3349 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3350 radeon_emit(cs,
3351 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3352 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3353
3354 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3355 }
3356
3357 if (loc->sgpr_idx != -1) {
3358 assert(!loc->indirect);
3359 assert(loc->num_sgprs == 3);
3360
3361 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3362 loc->sgpr_idx * 4, 3);
3363 radeon_emit(cs, blocks[0]);
3364 radeon_emit(cs, blocks[1]);
3365 radeon_emit(cs, blocks[2]);
3366 }
3367
3368 if (offsets[0] || offsets[1] || offsets[2]) {
3369 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3370 radeon_emit(cs, offsets[0]);
3371 radeon_emit(cs, offsets[1]);
3372 radeon_emit(cs, offsets[2]);
3373
3374 /* The blocks in the packet are not counts but end values. */
3375 for (unsigned i = 0; i < 3; ++i)
3376 blocks[i] += offsets[i];
3377 } else {
3378 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3379 }
3380
3381 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3382 PKT3_SHADER_TYPE_S(1));
3383 radeon_emit(cs, blocks[0]);
3384 radeon_emit(cs, blocks[1]);
3385 radeon_emit(cs, blocks[2]);
3386 radeon_emit(cs, dispatch_initiator);
3387 }
3388
3389 assert(cmd_buffer->cs->cdw <= cdw_max);
3390 }
3391
3392 static void
3393 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3394 {
3395 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3396 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3397 }
3398
3399 static void
3400 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3401 const struct radv_dispatch_info *info)
3402 {
3403 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3404 bool has_prefetch =
3405 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3406 bool pipeline_is_dirty = pipeline &&
3407 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3408
3409 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3410 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3411 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3412 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3413 /* If we have to wait for idle, set all states first, so that
3414 * all SET packets are processed in parallel with previous draw
3415 * calls. Then upload descriptors, set shader pointers, and
3416 * dispatch, and prefetch at the end. This ensures that the
3417 * time the CUs are idle is very short. (there are only SET_SH
3418 * packets between the wait and the draw)
3419 */
3420 radv_emit_compute_pipeline(cmd_buffer);
3421 si_emit_cache_flush(cmd_buffer);
3422 /* <-- CUs are idle here --> */
3423
3424 radv_upload_compute_shader_descriptors(cmd_buffer);
3425
3426 radv_emit_dispatch_packets(cmd_buffer, info);
3427 /* <-- CUs are busy here --> */
3428
3429 /* Start prefetches after the dispatch has been started. Both
3430 * will run in parallel, but starting the dispatch first is
3431 * more important.
3432 */
3433 if (has_prefetch && pipeline_is_dirty) {
3434 radv_emit_shader_prefetch(cmd_buffer,
3435 pipeline->shaders[MESA_SHADER_COMPUTE]);
3436 }
3437 } else {
3438 /* If we don't wait for idle, start prefetches first, then set
3439 * states, and dispatch at the end.
3440 */
3441 si_emit_cache_flush(cmd_buffer);
3442
3443 if (has_prefetch && pipeline_is_dirty) {
3444 radv_emit_shader_prefetch(cmd_buffer,
3445 pipeline->shaders[MESA_SHADER_COMPUTE]);
3446 }
3447
3448 radv_upload_compute_shader_descriptors(cmd_buffer);
3449
3450 radv_emit_compute_pipeline(cmd_buffer);
3451 radv_emit_dispatch_packets(cmd_buffer, info);
3452 }
3453
3454 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3455 }
3456
3457 void radv_CmdDispatchBase(
3458 VkCommandBuffer commandBuffer,
3459 uint32_t base_x,
3460 uint32_t base_y,
3461 uint32_t base_z,
3462 uint32_t x,
3463 uint32_t y,
3464 uint32_t z)
3465 {
3466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3467 struct radv_dispatch_info info = {};
3468
3469 info.blocks[0] = x;
3470 info.blocks[1] = y;
3471 info.blocks[2] = z;
3472
3473 info.offsets[0] = base_x;
3474 info.offsets[1] = base_y;
3475 info.offsets[2] = base_z;
3476 radv_dispatch(cmd_buffer, &info);
3477 }
3478
3479 void radv_CmdDispatch(
3480 VkCommandBuffer commandBuffer,
3481 uint32_t x,
3482 uint32_t y,
3483 uint32_t z)
3484 {
3485 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3486 }
3487
3488 void radv_CmdDispatchIndirect(
3489 VkCommandBuffer commandBuffer,
3490 VkBuffer _buffer,
3491 VkDeviceSize offset)
3492 {
3493 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3494 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3495 struct radv_dispatch_info info = {};
3496
3497 info.indirect = buffer;
3498 info.indirect_offset = offset;
3499
3500 radv_dispatch(cmd_buffer, &info);
3501 }
3502
3503 void radv_unaligned_dispatch(
3504 struct radv_cmd_buffer *cmd_buffer,
3505 uint32_t x,
3506 uint32_t y,
3507 uint32_t z)
3508 {
3509 struct radv_dispatch_info info = {};
3510
3511 info.blocks[0] = x;
3512 info.blocks[1] = y;
3513 info.blocks[2] = z;
3514 info.unaligned = 1;
3515
3516 radv_dispatch(cmd_buffer, &info);
3517 }
3518
3519 void radv_CmdEndRenderPass(
3520 VkCommandBuffer commandBuffer)
3521 {
3522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3523
3524 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3525
3526 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3527
3528 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3529 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3530 radv_handle_subpass_image_transition(cmd_buffer,
3531 (VkAttachmentReference){i, layout});
3532 }
3533
3534 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3535
3536 cmd_buffer->state.pass = NULL;
3537 cmd_buffer->state.subpass = NULL;
3538 cmd_buffer->state.attachments = NULL;
3539 cmd_buffer->state.framebuffer = NULL;
3540 }
3541
3542 /*
3543 * For HTILE we have the following interesting clear words:
3544 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3545 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3546 * 0xfffffff0: Clear depth to 1.0
3547 * 0x00000000: Clear depth to 0.0
3548 */
3549 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3550 struct radv_image *image,
3551 const VkImageSubresourceRange *range,
3552 uint32_t clear_word)
3553 {
3554 assert(range->baseMipLevel == 0);
3555 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3556 unsigned layer_count = radv_get_layerCount(image, range);
3557 uint64_t size = image->surface.htile_slice_size * layer_count;
3558 uint64_t offset = image->offset + image->htile_offset +
3559 image->surface.htile_slice_size * range->baseArrayLayer;
3560 struct radv_cmd_state *state = &cmd_buffer->state;
3561
3562 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3563 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3564
3565 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3566 size, clear_word);
3567
3568 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3569 }
3570
3571 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3572 struct radv_image *image,
3573 VkImageLayout src_layout,
3574 VkImageLayout dst_layout,
3575 unsigned src_queue_mask,
3576 unsigned dst_queue_mask,
3577 const VkImageSubresourceRange *range,
3578 VkImageAspectFlags pending_clears)
3579 {
3580 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3581 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3582 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3583 cmd_buffer->state.render_area.extent.width == image->info.width &&
3584 cmd_buffer->state.render_area.extent.height == image->info.height) {
3585 /* The clear will initialize htile. */
3586 return;
3587 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3588 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3589 /* TODO: merge with the clear if applicable */
3590 radv_initialize_htile(cmd_buffer, image, range, 0);
3591 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3592 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3593 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3594 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3595 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3596 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3597 VkImageSubresourceRange local_range = *range;
3598 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3599 local_range.baseMipLevel = 0;
3600 local_range.levelCount = 1;
3601
3602 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3603 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3604
3605 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3606
3607 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3608 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3609 }
3610 }
3611
3612 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3613 struct radv_image *image, uint32_t value)
3614 {
3615 struct radv_cmd_state *state = &cmd_buffer->state;
3616
3617 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3618 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3619
3620 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3621
3622 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3623 }
3624
3625 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3626 struct radv_image *image,
3627 VkImageLayout src_layout,
3628 VkImageLayout dst_layout,
3629 unsigned src_queue_mask,
3630 unsigned dst_queue_mask,
3631 const VkImageSubresourceRange *range)
3632 {
3633 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3634 if (radv_image_has_fmask(image))
3635 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3636 else
3637 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3638 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3639 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3640 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3641 }
3642 }
3643
3644 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3645 struct radv_image *image, uint32_t value)
3646 {
3647 struct radv_cmd_state *state = &cmd_buffer->state;
3648
3649 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3650 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3651
3652 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3653
3654 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3655 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3656 }
3657
3658 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3659 struct radv_image *image,
3660 VkImageLayout src_layout,
3661 VkImageLayout dst_layout,
3662 unsigned src_queue_mask,
3663 unsigned dst_queue_mask,
3664 const VkImageSubresourceRange *range)
3665 {
3666 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3667 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3668 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3669 radv_initialize_dcc(cmd_buffer, image,
3670 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3671 0x20202020u : 0xffffffffu);
3672 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3673 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3674 radv_decompress_dcc(cmd_buffer, image, range);
3675 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3676 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3677 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3678 }
3679 }
3680
3681 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3682 struct radv_image *image,
3683 VkImageLayout src_layout,
3684 VkImageLayout dst_layout,
3685 uint32_t src_family,
3686 uint32_t dst_family,
3687 const VkImageSubresourceRange *range,
3688 VkImageAspectFlags pending_clears)
3689 {
3690 if (image->exclusive && src_family != dst_family) {
3691 /* This is an acquire or a release operation and there will be
3692 * a corresponding release/acquire. Do the transition in the
3693 * most flexible queue. */
3694
3695 assert(src_family == cmd_buffer->queue_family_index ||
3696 dst_family == cmd_buffer->queue_family_index);
3697
3698 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3699 return;
3700
3701 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3702 (src_family == RADV_QUEUE_GENERAL ||
3703 dst_family == RADV_QUEUE_GENERAL))
3704 return;
3705 }
3706
3707 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3708 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3709
3710 if (radv_image_has_htile(image))
3711 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3712 dst_layout, src_queue_mask,
3713 dst_queue_mask, range,
3714 pending_clears);
3715
3716 if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
3717 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3718 dst_layout, src_queue_mask,
3719 dst_queue_mask, range);
3720
3721 if (radv_image_has_dcc(image))
3722 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3723 dst_layout, src_queue_mask,
3724 dst_queue_mask, range);
3725 }
3726
3727 void radv_CmdPipelineBarrier(
3728 VkCommandBuffer commandBuffer,
3729 VkPipelineStageFlags srcStageMask,
3730 VkPipelineStageFlags destStageMask,
3731 VkBool32 byRegion,
3732 uint32_t memoryBarrierCount,
3733 const VkMemoryBarrier* pMemoryBarriers,
3734 uint32_t bufferMemoryBarrierCount,
3735 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3736 uint32_t imageMemoryBarrierCount,
3737 const VkImageMemoryBarrier* pImageMemoryBarriers)
3738 {
3739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3740 enum radv_cmd_flush_bits src_flush_bits = 0;
3741 enum radv_cmd_flush_bits dst_flush_bits = 0;
3742
3743 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3744 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3745 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3746 NULL);
3747 }
3748
3749 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3750 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3751 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3752 NULL);
3753 }
3754
3755 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3756 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3757 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3758 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3759 image);
3760 }
3761
3762 radv_stage_flush(cmd_buffer, srcStageMask);
3763 cmd_buffer->state.flush_bits |= src_flush_bits;
3764
3765 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3766 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3767 radv_handle_image_transition(cmd_buffer, image,
3768 pImageMemoryBarriers[i].oldLayout,
3769 pImageMemoryBarriers[i].newLayout,
3770 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3771 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3772 &pImageMemoryBarriers[i].subresourceRange,
3773 0);
3774 }
3775
3776 cmd_buffer->state.flush_bits |= dst_flush_bits;
3777 }
3778
3779
3780 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3781 struct radv_event *event,
3782 VkPipelineStageFlags stageMask,
3783 unsigned value)
3784 {
3785 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3786 uint64_t va = radv_buffer_get_va(event->bo);
3787
3788 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3789
3790 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3791
3792 /* TODO: this is overkill. Probably should figure something out from
3793 * the stage mask. */
3794
3795 si_cs_emit_write_event_eop(cs,
3796 cmd_buffer->state.predicating,
3797 cmd_buffer->device->physical_device->rad_info.chip_class,
3798 radv_cmd_buffer_uses_mec(cmd_buffer),
3799 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3800 1, va, 2, value);
3801
3802 assert(cmd_buffer->cs->cdw <= cdw_max);
3803 }
3804
3805 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3806 VkEvent _event,
3807 VkPipelineStageFlags stageMask)
3808 {
3809 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3810 RADV_FROM_HANDLE(radv_event, event, _event);
3811
3812 write_event(cmd_buffer, event, stageMask, 1);
3813 }
3814
3815 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3816 VkEvent _event,
3817 VkPipelineStageFlags stageMask)
3818 {
3819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3820 RADV_FROM_HANDLE(radv_event, event, _event);
3821
3822 write_event(cmd_buffer, event, stageMask, 0);
3823 }
3824
3825 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3826 uint32_t eventCount,
3827 const VkEvent* pEvents,
3828 VkPipelineStageFlags srcStageMask,
3829 VkPipelineStageFlags dstStageMask,
3830 uint32_t memoryBarrierCount,
3831 const VkMemoryBarrier* pMemoryBarriers,
3832 uint32_t bufferMemoryBarrierCount,
3833 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3834 uint32_t imageMemoryBarrierCount,
3835 const VkImageMemoryBarrier* pImageMemoryBarriers)
3836 {
3837 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3838 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3839
3840 for (unsigned i = 0; i < eventCount; ++i) {
3841 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3842 uint64_t va = radv_buffer_get_va(event->bo);
3843
3844 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3845
3846 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3847
3848 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3849 assert(cmd_buffer->cs->cdw <= cdw_max);
3850 }
3851
3852
3853 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3854 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3855
3856 radv_handle_image_transition(cmd_buffer, image,
3857 pImageMemoryBarriers[i].oldLayout,
3858 pImageMemoryBarriers[i].newLayout,
3859 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3860 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3861 &pImageMemoryBarriers[i].subresourceRange,
3862 0);
3863 }
3864
3865 /* TODO: figure out how to do memory barriers without waiting */
3866 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3867 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3868 RADV_CMD_FLAG_INV_VMEM_L1 |
3869 RADV_CMD_FLAG_INV_SMEM_L1;
3870 }
3871
3872
3873 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3874 uint32_t deviceMask)
3875 {
3876 /* No-op */
3877 }