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6dc80acef079e16f2a6f1d6e64642b8b7ec988fc
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
597 old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
598 return;
599
600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
602 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
603
604 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
605
606 /* GFX9: Flush DFSM when the AA mode changes. */
607 if (cmd_buffer->device->dfsm_allowed) {
608 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
609 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
610 }
611 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
612 uint32_t offset;
613 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
614 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
615 if (loc->sgpr_idx == -1)
616 return;
617 assert(loc->num_sgprs == 1);
618 assert(!loc->indirect);
619 switch (num_samples) {
620 default:
621 offset = 0;
622 break;
623 case 2:
624 offset = 1;
625 break;
626 case 4:
627 offset = 3;
628 break;
629 case 8:
630 offset = 7;
631 break;
632 case 16:
633 offset = 15;
634 break;
635 }
636
637 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
638 cmd_buffer->sample_positions_needed = true;
639 }
640 }
641
642 static void
643 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 struct radv_raster_state *raster = &pipeline->graphics.raster;
647
648 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
649 raster->pa_cl_clip_cntl);
650 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
651 raster->spi_interp_control);
652 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
653 raster->pa_su_vtx_cntl);
654 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
655 raster->pa_su_sc_mode_cntl);
656 }
657
658 static inline void
659 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
660 unsigned size)
661 {
662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
663 si_cp_dma_prefetch(cmd_buffer, va, size);
664 }
665
666 static void
667 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
668 {
669 if (cmd_buffer->state.vb_prefetch_dirty) {
670 radv_emit_prefetch_TC_L2_async(cmd_buffer,
671 cmd_buffer->state.vb_va,
672 cmd_buffer->state.vb_size);
673 cmd_buffer->state.vb_prefetch_dirty = false;
674 }
675 }
676
677 static void
678 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
679 struct radv_shader_variant *shader)
680 {
681 struct radeon_winsys *ws = cmd_buffer->device->ws;
682 struct radeon_winsys_cs *cs = cmd_buffer->cs;
683 uint64_t va;
684
685 if (!shader)
686 return;
687
688 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
689
690 radv_cs_add_buffer(ws, cs, shader->bo, 8);
691 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
692 }
693
694 static void
695 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
696 struct radv_pipeline *pipeline)
697 {
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_GEOMETRY]);
707 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_FRAGMENT]);
710 }
711
712 static void
713 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
714 struct radv_pipeline *pipeline,
715 struct radv_shader_variant *shader)
716 {
717 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
720 pipeline->graphics.vs.spi_vs_out_config);
721
722 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
723 pipeline->graphics.vs.spi_shader_pos_format);
724
725 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
726 radeon_emit(cmd_buffer->cs, va >> 8);
727 radeon_emit(cmd_buffer->cs, va >> 40);
728 radeon_emit(cmd_buffer->cs, shader->rsrc1);
729 radeon_emit(cmd_buffer->cs, shader->rsrc2);
730
731 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
732 S_028818_VTX_W0_FMT(1) |
733 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
734 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
735 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
736
737
738 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
739 pipeline->graphics.vs.pa_cl_vs_out_cntl);
740
741 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
742 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
743 pipeline->graphics.vs.vgt_reuse_off);
744 }
745
746 static void
747 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_pipeline *pipeline,
749 struct radv_shader_variant *shader)
750 {
751 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
752
753 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
754 radeon_emit(cmd_buffer->cs, va >> 8);
755 radeon_emit(cmd_buffer->cs, va >> 40);
756 radeon_emit(cmd_buffer->cs, shader->rsrc1);
757 radeon_emit(cmd_buffer->cs, shader->rsrc2);
758 }
759
760 static void
761 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
762 struct radv_shader_variant *shader)
763 {
764 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
765 uint32_t rsrc2 = shader->rsrc2;
766
767 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
768 radeon_emit(cmd_buffer->cs, va >> 8);
769 radeon_emit(cmd_buffer->cs, va >> 40);
770
771 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
772 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
773 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
774 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
775
776 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
777 radeon_emit(cmd_buffer->cs, shader->rsrc1);
778 radeon_emit(cmd_buffer->cs, rsrc2);
779 }
780
781 static void
782 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
783 struct radv_shader_variant *shader)
784 {
785 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
786
787 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791
792 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
793 radeon_emit(cmd_buffer->cs, shader->rsrc1);
794 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
795 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
796 } else {
797 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
798 radeon_emit(cmd_buffer->cs, va >> 8);
799 radeon_emit(cmd_buffer->cs, va >> 40);
800 radeon_emit(cmd_buffer->cs, shader->rsrc1);
801 radeon_emit(cmd_buffer->cs, shader->rsrc2);
802 }
803 }
804
805 static void
806 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
807 struct radv_pipeline *pipeline)
808 {
809 struct radv_shader_variant *vs;
810
811 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
812
813 /* Skip shaders merged into HS/GS */
814 vs = pipeline->shaders[MESA_SHADER_VERTEX];
815 if (!vs)
816 return;
817
818 if (vs->info.vs.as_ls)
819 radv_emit_hw_ls(cmd_buffer, vs);
820 else if (vs->info.vs.as_es)
821 radv_emit_hw_es(cmd_buffer, pipeline, vs);
822 else
823 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
824 }
825
826
827 static void
828 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
829 struct radv_pipeline *pipeline)
830 {
831 if (!radv_pipeline_has_tess(pipeline))
832 return;
833
834 struct radv_shader_variant *tes, *tcs;
835
836 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
837 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
838
839 if (tes) {
840 if (tes->info.tes.as_es)
841 radv_emit_hw_es(cmd_buffer, pipeline, tes);
842 else
843 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
844 }
845
846 radv_emit_hw_hs(cmd_buffer, tcs);
847
848 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
849 pipeline->graphics.tess.tf_param);
850
851 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
852 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
853 pipeline->graphics.tess.ls_hs_config);
854 else
855 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
856 pipeline->graphics.tess.ls_hs_config);
857
858 struct ac_userdata_info *loc;
859
860 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
861 if (loc->sgpr_idx != -1) {
862 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
863 assert(loc->num_sgprs == 4);
864 assert(!loc->indirect);
865 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
868 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
869 pipeline->graphics.tess.num_tcs_input_cp << 26);
870 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
871 }
872
873 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
874 if (loc->sgpr_idx != -1) {
875 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
876 assert(loc->num_sgprs == 1);
877 assert(!loc->indirect);
878
879 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
880 pipeline->graphics.tess.offchip_layout);
881 }
882
883 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
884 if (loc->sgpr_idx != -1) {
885 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
886 assert(loc->num_sgprs == 1);
887 assert(!loc->indirect);
888
889 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
890 pipeline->graphics.tess.tcs_in_layout);
891 }
892 }
893
894 static void
895 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
896 struct radv_pipeline *pipeline)
897 {
898 struct radv_shader_variant *gs;
899 uint64_t va;
900
901 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
902
903 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
904 if (!gs)
905 return;
906
907 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
908
909 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
917
918 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
920 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923 radeon_emit(cmd_buffer->cs, 0);
924
925 uint32_t gs_num_invocations = gs->info.gs.invocations;
926 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
927 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
928 S_028B90_ENABLE(gs_num_invocations > 0));
929
930 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
931 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
932
933 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
934
935 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
936 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
937 radeon_emit(cmd_buffer->cs, va >> 8);
938 radeon_emit(cmd_buffer->cs, va >> 40);
939
940 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
941 radeon_emit(cmd_buffer->cs, gs->rsrc1);
942 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
943 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
944
945 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
946 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
947 } else {
948 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
949 radeon_emit(cmd_buffer->cs, va >> 8);
950 radeon_emit(cmd_buffer->cs, va >> 40);
951 radeon_emit(cmd_buffer->cs, gs->rsrc1);
952 radeon_emit(cmd_buffer->cs, gs->rsrc2);
953 }
954
955 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
956
957 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
958 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
959 if (loc->sgpr_idx != -1) {
960 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
961 uint32_t num_entries = 64;
962 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
963
964 if (is_vi)
965 num_entries *= stride;
966
967 stride = S_008F04_STRIDE(stride);
968 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
969 radeon_emit(cmd_buffer->cs, stride);
970 radeon_emit(cmd_buffer->cs, num_entries);
971 }
972 }
973
974 static void
975 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
976 struct radv_pipeline *pipeline)
977 {
978 struct radv_shader_variant *ps;
979 uint64_t va;
980 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
981 struct radv_blend_state *blend = &pipeline->graphics.blend;
982 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
983
984 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
985 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
986
987 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
988 radeon_emit(cmd_buffer->cs, va >> 8);
989 radeon_emit(cmd_buffer->cs, va >> 40);
990 radeon_emit(cmd_buffer->cs, ps->rsrc1);
991 radeon_emit(cmd_buffer->cs, ps->rsrc2);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
994 pipeline->graphics.db_shader_control);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
997 ps->config.spi_ps_input_ena);
998
999 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1000 ps->config.spi_ps_input_addr);
1001
1002 if (ps->info.info.ps.force_persample)
1003 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1006 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1011 pipeline->graphics.shader_z_format);
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1014
1015 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1016 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1017
1018 if (cmd_buffer->device->dfsm_allowed) {
1019 /* optimise this? */
1020 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1021 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1022 }
1023
1024 if (pipeline->graphics.ps_input_cntl_num) {
1025 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1026 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1027 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1028 }
1029 }
1030 }
1031
1032 static void
1033 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1034 struct radv_pipeline *pipeline)
1035 {
1036 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1037
1038 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1039 return;
1040
1041 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1042 pipeline->graphics.vtx_reuse_depth);
1043 }
1044
1045 static void
1046 radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
1047 struct radv_pipeline *pipeline)
1048 {
1049 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1050
1051 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
1052 return;
1053
1054 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
1055 pipeline->graphics.bin.pa_sc_binner_cntl_0);
1056 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
1057 pipeline->graphics.bin.db_dfsm_control);
1058 }
1059
1060 static void
1061 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1062 {
1063 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1064
1065 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1066 return;
1067
1068 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1069 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1070 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1071 radv_update_multisample_state(cmd_buffer, pipeline);
1072 radv_emit_vertex_shader(cmd_buffer, pipeline);
1073 radv_emit_tess_shaders(cmd_buffer, pipeline);
1074 radv_emit_geometry_shader(cmd_buffer, pipeline);
1075 radv_emit_fragment_shader(cmd_buffer, pipeline);
1076 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1077 radv_emit_binning_state(cmd_buffer, pipeline);
1078
1079 cmd_buffer->scratch_size_needed =
1080 MAX2(cmd_buffer->scratch_size_needed,
1081 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1082
1083 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1084 S_0286E8_WAVES(pipeline->max_waves) |
1085 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1086
1087 if (!cmd_buffer->state.emitted_pipeline ||
1088 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1089 pipeline->graphics.can_use_guardband)
1090 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1091
1092 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1093
1094 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1095 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1096 } else {
1097 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1098 }
1099 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1100
1101 if (unlikely(cmd_buffer->device->trace_bo))
1102 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1103
1104 cmd_buffer->state.emitted_pipeline = pipeline;
1105
1106 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1107 }
1108
1109 static void
1110 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1111 {
1112 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1113 cmd_buffer->state.dynamic.viewport.viewports);
1114 }
1115
1116 static void
1117 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1120
1121 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1122 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1123 si_emit_cache_flush(cmd_buffer);
1124 }
1125 si_write_scissors(cmd_buffer->cs, 0, count,
1126 cmd_buffer->state.dynamic.scissor.scissors,
1127 cmd_buffer->state.dynamic.viewport.viewports,
1128 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1129 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1130 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1131 }
1132
1133 static void
1134 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1135 {
1136 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1137
1138 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1139 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1140 }
1141
1142 static void
1143 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1144 {
1145 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1146
1147 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1148 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1149 }
1150
1151 static void
1152 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1153 {
1154 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1155
1156 radeon_set_context_reg_seq(cmd_buffer->cs,
1157 R_028430_DB_STENCILREFMASK, 2);
1158 radeon_emit(cmd_buffer->cs,
1159 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1160 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1161 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1162 S_028430_STENCILOPVAL(1));
1163 radeon_emit(cmd_buffer->cs,
1164 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1165 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1166 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1167 S_028434_STENCILOPVAL_BF(1));
1168 }
1169
1170 static void
1171 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1172 {
1173 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1174
1175 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1176 fui(d->depth_bounds.min));
1177 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1178 fui(d->depth_bounds.max));
1179 }
1180
1181 static void
1182 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1183 {
1184 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1185 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1186 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1187 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1188
1189 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1190 radeon_set_context_reg_seq(cmd_buffer->cs,
1191 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1192 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1193 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1194 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1195 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1196 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1197 }
1198 }
1199
1200 static void
1201 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1202 int index,
1203 struct radv_attachment_info *att,
1204 struct radv_image *image,
1205 VkImageLayout layout)
1206 {
1207 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1208 struct radv_color_buffer_info *cb = &att->cb;
1209 uint32_t cb_color_info = cb->cb_color_info;
1210
1211 if (!radv_layout_dcc_compressed(image, layout,
1212 radv_image_queue_family_mask(image,
1213 cmd_buffer->queue_family_index,
1214 cmd_buffer->queue_family_index))) {
1215 cb_color_info &= C_028C70_DCC_ENABLE;
1216 }
1217
1218 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1219 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1223 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1224 radeon_emit(cmd_buffer->cs, cb_color_info);
1225 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1226 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1227 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1228 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1229 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1230 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1231
1232 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1233 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1234 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1235
1236 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1237 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1238 } else {
1239 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1240 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1241 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1242 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1243 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1244 radeon_emit(cmd_buffer->cs, cb_color_info);
1245 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1246 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1247 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1248 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1249 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1250 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1251
1252 if (is_vi) { /* DCC BASE */
1253 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1254 }
1255 }
1256 }
1257
1258 static void
1259 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1260 struct radv_ds_buffer_info *ds,
1261 struct radv_image *image,
1262 VkImageLayout layout)
1263 {
1264 uint32_t db_z_info = ds->db_z_info;
1265 uint32_t db_stencil_info = ds->db_stencil_info;
1266
1267 if (!radv_layout_has_htile(image, layout,
1268 radv_image_queue_family_mask(image,
1269 cmd_buffer->queue_family_index,
1270 cmd_buffer->queue_family_index))) {
1271 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1272 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1273 }
1274
1275 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1276 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1277
1278
1279 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1280 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1281 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1282 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1283 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1284
1285 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1286 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1287 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1288 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1289 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1290 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1291 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1292 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1293 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1294 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1295 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1296
1297 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1298 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1299 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1300 } else {
1301 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1302
1303 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1304 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1305 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1306 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1307 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1308 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1309 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1310 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1311 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1312 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1313
1314 }
1315
1316 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1317 ds->pa_su_poly_offset_db_fmt_cntl);
1318 }
1319
1320 void
1321 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1322 struct radv_image *image,
1323 VkClearDepthStencilValue ds_clear_value,
1324 VkImageAspectFlags aspects)
1325 {
1326 uint64_t va = radv_buffer_get_va(image->bo);
1327 va += image->offset + image->clear_value_offset;
1328 unsigned reg_offset = 0, reg_count = 0;
1329
1330 assert(image->surface.htile_size);
1331
1332 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1333 ++reg_count;
1334 } else {
1335 ++reg_offset;
1336 va += 4;
1337 }
1338 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1339 ++reg_count;
1340
1341 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1342 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1343 S_370_WR_CONFIRM(1) |
1344 S_370_ENGINE_SEL(V_370_PFP));
1345 radeon_emit(cmd_buffer->cs, va);
1346 radeon_emit(cmd_buffer->cs, va >> 32);
1347 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1348 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1349 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1350 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1351
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1353 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1354 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1355 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1356 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1357 }
1358
1359 static void
1360 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1361 struct radv_image *image)
1362 {
1363 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1364 uint64_t va = radv_buffer_get_va(image->bo);
1365 va += image->offset + image->clear_value_offset;
1366 unsigned reg_offset = 0, reg_count = 0;
1367
1368 if (!image->surface.htile_size)
1369 return;
1370
1371 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1372 ++reg_count;
1373 } else {
1374 ++reg_offset;
1375 va += 4;
1376 }
1377 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1378 ++reg_count;
1379
1380 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1381 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1382 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1383 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1384 radeon_emit(cmd_buffer->cs, va);
1385 radeon_emit(cmd_buffer->cs, va >> 32);
1386 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1387 radeon_emit(cmd_buffer->cs, 0);
1388
1389 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1390 radeon_emit(cmd_buffer->cs, 0);
1391 }
1392
1393 /*
1394 *with DCC some colors don't require CMASK elimiation before being
1395 * used as a texture. This sets a predicate value to determine if the
1396 * cmask eliminate is required.
1397 */
1398 void
1399 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1400 struct radv_image *image,
1401 bool value)
1402 {
1403 uint64_t pred_val = value;
1404 uint64_t va = radv_buffer_get_va(image->bo);
1405 va += image->offset + image->dcc_pred_offset;
1406
1407 assert(image->surface.dcc_size);
1408
1409 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1410 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1411 S_370_WR_CONFIRM(1) |
1412 S_370_ENGINE_SEL(V_370_PFP));
1413 radeon_emit(cmd_buffer->cs, va);
1414 radeon_emit(cmd_buffer->cs, va >> 32);
1415 radeon_emit(cmd_buffer->cs, pred_val);
1416 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1417 }
1418
1419 void
1420 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1421 struct radv_image *image,
1422 int idx,
1423 uint32_t color_values[2])
1424 {
1425 uint64_t va = radv_buffer_get_va(image->bo);
1426 va += image->offset + image->clear_value_offset;
1427
1428 assert(image->cmask.size || image->surface.dcc_size);
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1431 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1432 S_370_WR_CONFIRM(1) |
1433 S_370_ENGINE_SEL(V_370_PFP));
1434 radeon_emit(cmd_buffer->cs, va);
1435 radeon_emit(cmd_buffer->cs, va >> 32);
1436 radeon_emit(cmd_buffer->cs, color_values[0]);
1437 radeon_emit(cmd_buffer->cs, color_values[1]);
1438
1439 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1440 radeon_emit(cmd_buffer->cs, color_values[0]);
1441 radeon_emit(cmd_buffer->cs, color_values[1]);
1442 }
1443
1444 static void
1445 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1446 struct radv_image *image,
1447 int idx)
1448 {
1449 uint64_t va = radv_buffer_get_va(image->bo);
1450 va += image->offset + image->clear_value_offset;
1451
1452 if (!image->cmask.size && !image->surface.dcc_size)
1453 return;
1454
1455 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1456
1457 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1458 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1459 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1460 COPY_DATA_COUNT_SEL);
1461 radeon_emit(cmd_buffer->cs, va);
1462 radeon_emit(cmd_buffer->cs, va >> 32);
1463 radeon_emit(cmd_buffer->cs, reg >> 2);
1464 radeon_emit(cmd_buffer->cs, 0);
1465
1466 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1467 radeon_emit(cmd_buffer->cs, 0);
1468 }
1469
1470 static void
1471 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1472 {
1473 int i;
1474 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1475 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1476
1477 /* this may happen for inherited secondary recording */
1478 if (!framebuffer)
1479 return;
1480
1481 for (i = 0; i < 8; ++i) {
1482 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1483 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1484 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1485 continue;
1486 }
1487
1488 int idx = subpass->color_attachments[i].attachment;
1489 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1490 struct radv_image *image = att->attachment->image;
1491 VkImageLayout layout = subpass->color_attachments[i].layout;
1492
1493 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1494
1495 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1496 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1497
1498 radv_load_color_clear_regs(cmd_buffer, image, i);
1499 }
1500
1501 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1502 int idx = subpass->depth_stencil_attachment.attachment;
1503 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1504 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1505 struct radv_image *image = att->attachment->image;
1506 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1507 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1508 cmd_buffer->queue_family_index,
1509 cmd_buffer->queue_family_index);
1510 /* We currently don't support writing decompressed HTILE */
1511 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1512 radv_layout_is_htile_compressed(image, layout, queue_mask));
1513
1514 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1515
1516 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1517 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1518 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1519 }
1520 radv_load_depth_clear_regs(cmd_buffer, image);
1521 } else {
1522 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1523 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1524 else
1525 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1526
1527 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1528 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1529 }
1530 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1531 S_028208_BR_X(framebuffer->width) |
1532 S_028208_BR_Y(framebuffer->height));
1533
1534 if (cmd_buffer->device->dfsm_allowed) {
1535 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1536 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1537 }
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1540 }
1541
1542 static void
1543 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1544 {
1545 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1546 struct radv_cmd_state *state = &cmd_buffer->state;
1547
1548 if (state->index_type != state->last_index_type) {
1549 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1550 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1551 2, state->index_type);
1552 } else {
1553 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1554 radeon_emit(cs, state->index_type);
1555 }
1556
1557 state->last_index_type = state->index_type;
1558 }
1559
1560 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1561 radeon_emit(cs, state->index_va);
1562 radeon_emit(cs, state->index_va >> 32);
1563
1564 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1565 radeon_emit(cs, state->max_index_count);
1566
1567 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1568 }
1569
1570 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1571 {
1572 uint32_t db_count_control;
1573
1574 if(!cmd_buffer->state.active_occlusion_queries) {
1575 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1576 db_count_control = 0;
1577 } else {
1578 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1579 }
1580 } else {
1581 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1582 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1583 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1584 S_028004_ZPASS_ENABLE(1) |
1585 S_028004_SLICE_EVEN_ENABLE(1) |
1586 S_028004_SLICE_ODD_ENABLE(1);
1587 } else {
1588 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1589 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1590 }
1591 }
1592
1593 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1594 }
1595
1596 static void
1597 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1598 {
1599 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1600 return;
1601
1602 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1603 radv_emit_viewport(cmd_buffer);
1604
1605 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1606 radv_emit_scissor(cmd_buffer);
1607
1608 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1609 radv_emit_line_width(cmd_buffer);
1610
1611 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1612 radv_emit_blend_constants(cmd_buffer);
1613
1614 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1615 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1616 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1617 radv_emit_stencil(cmd_buffer);
1618
1619 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1620 radv_emit_depth_bounds(cmd_buffer);
1621
1622 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1623 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1624 radv_emit_depth_biais(cmd_buffer);
1625
1626 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1627 }
1628
1629 static void
1630 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1631 struct radv_pipeline *pipeline,
1632 int idx,
1633 uint64_t va,
1634 gl_shader_stage stage)
1635 {
1636 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1637 uint32_t base_reg = pipeline->user_data_0[stage];
1638
1639 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1640 return;
1641
1642 assert(!desc_set_loc->indirect);
1643 assert(desc_set_loc->num_sgprs == 2);
1644 radeon_set_sh_reg_seq(cmd_buffer->cs,
1645 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1646 radeon_emit(cmd_buffer->cs, va);
1647 radeon_emit(cmd_buffer->cs, va >> 32);
1648 }
1649
1650 static void
1651 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1652 VkShaderStageFlags stages,
1653 struct radv_descriptor_set *set,
1654 unsigned idx)
1655 {
1656 if (cmd_buffer->state.pipeline) {
1657 radv_foreach_stage(stage, stages) {
1658 if (cmd_buffer->state.pipeline->shaders[stage])
1659 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1660 idx, set->va,
1661 stage);
1662 }
1663 }
1664
1665 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1666 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1667 idx, set->va,
1668 MESA_SHADER_COMPUTE);
1669 }
1670
1671 static void
1672 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1673 {
1674 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1675 unsigned bo_offset;
1676
1677 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1678 set->mapped_ptr,
1679 &bo_offset))
1680 return;
1681
1682 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1683 set->va += bo_offset;
1684 }
1685
1686 static void
1687 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1688 {
1689 uint32_t size = MAX_SETS * 2 * 4;
1690 uint32_t offset;
1691 void *ptr;
1692
1693 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1694 256, &offset, &ptr))
1695 return;
1696
1697 for (unsigned i = 0; i < MAX_SETS; i++) {
1698 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1699 uint64_t set_va = 0;
1700 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1701 if (cmd_buffer->state.valid_descriptors & (1u << i))
1702 set_va = set->va;
1703 uptr[0] = set_va & 0xffffffff;
1704 uptr[1] = set_va >> 32;
1705 }
1706
1707 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1708 va += offset;
1709
1710 if (cmd_buffer->state.pipeline) {
1711 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1712 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1713 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1714
1715 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1716 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1717 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1718
1719 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1720 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1721 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1722
1723 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1724 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1725 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1726
1727 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1728 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1729 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1730 }
1731
1732 if (cmd_buffer->state.compute_pipeline)
1733 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1734 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1735 }
1736
1737 static void
1738 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1739 VkShaderStageFlags stages)
1740 {
1741 unsigned i;
1742
1743 if (!cmd_buffer->state.descriptors_dirty)
1744 return;
1745
1746 if (cmd_buffer->state.push_descriptors_dirty)
1747 radv_flush_push_descriptors(cmd_buffer);
1748
1749 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1750 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1751 radv_flush_indirect_descriptor_sets(cmd_buffer);
1752 }
1753
1754 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1755 cmd_buffer->cs,
1756 MAX_SETS * MESA_SHADER_STAGES * 4);
1757
1758 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1759 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1760 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1761 continue;
1762
1763 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1764 }
1765 cmd_buffer->state.descriptors_dirty = 0;
1766 cmd_buffer->state.push_descriptors_dirty = false;
1767
1768 if (unlikely(cmd_buffer->device->trace_bo))
1769 radv_save_descriptors(cmd_buffer);
1770
1771 assert(cmd_buffer->cs->cdw <= cdw_max);
1772 }
1773
1774 static void
1775 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1776 struct radv_pipeline *pipeline,
1777 VkShaderStageFlags stages)
1778 {
1779 struct radv_pipeline_layout *layout = pipeline->layout;
1780 unsigned offset;
1781 void *ptr;
1782 uint64_t va;
1783
1784 stages &= cmd_buffer->push_constant_stages;
1785 if (!stages ||
1786 (!layout->push_constant_size && !layout->dynamic_offset_count))
1787 return;
1788
1789 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1790 16 * layout->dynamic_offset_count,
1791 256, &offset, &ptr))
1792 return;
1793
1794 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1795 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1796 16 * layout->dynamic_offset_count);
1797
1798 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1799 va += offset;
1800
1801 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1802 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1803
1804 radv_foreach_stage(stage, stages) {
1805 if (pipeline->shaders[stage]) {
1806 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1807 AC_UD_PUSH_CONSTANTS, va);
1808 }
1809 }
1810
1811 cmd_buffer->push_constant_stages &= ~stages;
1812 assert(cmd_buffer->cs->cdw <= cdw_max);
1813 }
1814
1815 static bool
1816 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1817 {
1818 if ((pipeline_is_dirty ||
1819 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1820 cmd_buffer->state.pipeline->vertex_elements.count &&
1821 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1822 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1823 unsigned vb_offset;
1824 void *vb_ptr;
1825 uint32_t i = 0;
1826 uint32_t count = velems->count;
1827 uint64_t va;
1828
1829 /* allocate some descriptor state for vertex buffers */
1830 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1831 &vb_offset, &vb_ptr))
1832 return false;
1833
1834 for (i = 0; i < count; i++) {
1835 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1836 uint32_t offset;
1837 int vb = velems->binding[i];
1838 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1839 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1840
1841 va = radv_buffer_get_va(buffer->bo);
1842
1843 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1844 va += offset + buffer->offset;
1845 desc[0] = va;
1846 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1847 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1848 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1849 else
1850 desc[2] = buffer->size - offset;
1851 desc[3] = velems->rsrc_word3[i];
1852 }
1853
1854 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1855 va += vb_offset;
1856
1857 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1858 AC_UD_VS_VERTEX_BUFFERS, va);
1859
1860 cmd_buffer->state.vb_va = va;
1861 cmd_buffer->state.vb_size = count * 16;
1862 cmd_buffer->state.vb_prefetch_dirty = true;
1863 }
1864 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1865
1866 return true;
1867 }
1868
1869 static bool
1870 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1871 {
1872 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1873 return false;
1874
1875 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1876 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1877 VK_SHADER_STAGE_ALL_GRAPHICS);
1878
1879 return true;
1880 }
1881
1882 static void
1883 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1884 bool instanced_draw, bool indirect_draw,
1885 uint32_t draw_vertex_count)
1886 {
1887 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1888 struct radv_cmd_state *state = &cmd_buffer->state;
1889 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1890 uint32_t ia_multi_vgt_param;
1891 int32_t primitive_reset_en;
1892
1893 /* Draw state. */
1894 ia_multi_vgt_param =
1895 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1896 indirect_draw, draw_vertex_count);
1897
1898 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1899 if (info->chip_class >= GFX9) {
1900 radeon_set_uconfig_reg_idx(cs,
1901 R_030960_IA_MULTI_VGT_PARAM,
1902 4, ia_multi_vgt_param);
1903 } else if (info->chip_class >= CIK) {
1904 radeon_set_context_reg_idx(cs,
1905 R_028AA8_IA_MULTI_VGT_PARAM,
1906 1, ia_multi_vgt_param);
1907 } else {
1908 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1909 ia_multi_vgt_param);
1910 }
1911 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1912 }
1913
1914 /* Primitive restart. */
1915 primitive_reset_en =
1916 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1917
1918 if (primitive_reset_en != state->last_primitive_reset_en) {
1919 state->last_primitive_reset_en = primitive_reset_en;
1920 if (info->chip_class >= GFX9) {
1921 radeon_set_uconfig_reg(cs,
1922 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1923 primitive_reset_en);
1924 } else {
1925 radeon_set_context_reg(cs,
1926 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1927 primitive_reset_en);
1928 }
1929 }
1930
1931 if (primitive_reset_en) {
1932 uint32_t primitive_reset_index =
1933 state->index_type ? 0xffffffffu : 0xffffu;
1934
1935 if (primitive_reset_index != state->last_primitive_reset_index) {
1936 radeon_set_context_reg(cs,
1937 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1938 primitive_reset_index);
1939 state->last_primitive_reset_index = primitive_reset_index;
1940 }
1941 }
1942 }
1943
1944 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1945 VkPipelineStageFlags src_stage_mask)
1946 {
1947 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1948 VK_PIPELINE_STAGE_TRANSFER_BIT |
1949 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1950 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1951 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1952 }
1953
1954 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1955 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1956 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1957 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1958 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1959 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1960 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1961 VK_PIPELINE_STAGE_TRANSFER_BIT |
1962 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1963 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1964 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1965 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1966 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1967 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1968 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1969 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1970 }
1971 }
1972
1973 static enum radv_cmd_flush_bits
1974 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1975 VkAccessFlags src_flags)
1976 {
1977 enum radv_cmd_flush_bits flush_bits = 0;
1978 uint32_t b;
1979 for_each_bit(b, src_flags) {
1980 switch ((VkAccessFlagBits)(1 << b)) {
1981 case VK_ACCESS_SHADER_WRITE_BIT:
1982 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1983 break;
1984 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1985 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1986 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1987 break;
1988 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1990 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1991 break;
1992 case VK_ACCESS_TRANSFER_WRITE_BIT:
1993 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1994 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1995 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1996 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1997 RADV_CMD_FLAG_INV_GLOBAL_L2;
1998 break;
1999 default:
2000 break;
2001 }
2002 }
2003 return flush_bits;
2004 }
2005
2006 static enum radv_cmd_flush_bits
2007 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2008 VkAccessFlags dst_flags,
2009 struct radv_image *image)
2010 {
2011 enum radv_cmd_flush_bits flush_bits = 0;
2012 uint32_t b;
2013 for_each_bit(b, dst_flags) {
2014 switch ((VkAccessFlagBits)(1 << b)) {
2015 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2016 case VK_ACCESS_INDEX_READ_BIT:
2017 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2018 break;
2019 case VK_ACCESS_UNIFORM_READ_BIT:
2020 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2021 break;
2022 case VK_ACCESS_SHADER_READ_BIT:
2023 case VK_ACCESS_TRANSFER_READ_BIT:
2024 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2025 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2026 RADV_CMD_FLAG_INV_GLOBAL_L2;
2027 break;
2028 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2029 /* TODO: change to image && when the image gets passed
2030 * through from the subpass. */
2031 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2032 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2033 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2034 break;
2035 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2036 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2037 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2038 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2039 break;
2040 default:
2041 break;
2042 }
2043 }
2044 return flush_bits;
2045 }
2046
2047 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2048 {
2049 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2050 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2051 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2052 NULL);
2053 }
2054
2055 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2056 VkAttachmentReference att)
2057 {
2058 unsigned idx = att.attachment;
2059 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2060 VkImageSubresourceRange range;
2061 range.aspectMask = 0;
2062 range.baseMipLevel = view->base_mip;
2063 range.levelCount = 1;
2064 range.baseArrayLayer = view->base_layer;
2065 range.layerCount = cmd_buffer->state.framebuffer->layers;
2066
2067 radv_handle_image_transition(cmd_buffer,
2068 view->image,
2069 cmd_buffer->state.attachments[idx].current_layout,
2070 att.layout, 0, 0, &range,
2071 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2072
2073 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2074
2075
2076 }
2077
2078 void
2079 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2080 const struct radv_subpass *subpass, bool transitions)
2081 {
2082 if (transitions) {
2083 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2084
2085 for (unsigned i = 0; i < subpass->color_count; ++i) {
2086 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2087 radv_handle_subpass_image_transition(cmd_buffer,
2088 subpass->color_attachments[i]);
2089 }
2090
2091 for (unsigned i = 0; i < subpass->input_count; ++i) {
2092 radv_handle_subpass_image_transition(cmd_buffer,
2093 subpass->input_attachments[i]);
2094 }
2095
2096 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2097 radv_handle_subpass_image_transition(cmd_buffer,
2098 subpass->depth_stencil_attachment);
2099 }
2100 }
2101
2102 cmd_buffer->state.subpass = subpass;
2103
2104 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2105 }
2106
2107 static VkResult
2108 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2109 struct radv_render_pass *pass,
2110 const VkRenderPassBeginInfo *info)
2111 {
2112 struct radv_cmd_state *state = &cmd_buffer->state;
2113
2114 if (pass->attachment_count == 0) {
2115 state->attachments = NULL;
2116 return VK_SUCCESS;
2117 }
2118
2119 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2120 pass->attachment_count *
2121 sizeof(state->attachments[0]),
2122 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2123 if (state->attachments == NULL) {
2124 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2125 return cmd_buffer->record_result;
2126 }
2127
2128 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2129 struct radv_render_pass_attachment *att = &pass->attachments[i];
2130 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2131 VkImageAspectFlags clear_aspects = 0;
2132
2133 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2134 /* color attachment */
2135 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2136 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2137 }
2138 } else {
2139 /* depthstencil attachment */
2140 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2141 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2142 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2143 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2144 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2145 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2146 }
2147 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2148 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2149 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2150 }
2151 }
2152
2153 state->attachments[i].pending_clear_aspects = clear_aspects;
2154 state->attachments[i].cleared_views = 0;
2155 if (clear_aspects && info) {
2156 assert(info->clearValueCount > i);
2157 state->attachments[i].clear_value = info->pClearValues[i];
2158 }
2159
2160 state->attachments[i].current_layout = att->initial_layout;
2161 }
2162
2163 return VK_SUCCESS;
2164 }
2165
2166 VkResult radv_AllocateCommandBuffers(
2167 VkDevice _device,
2168 const VkCommandBufferAllocateInfo *pAllocateInfo,
2169 VkCommandBuffer *pCommandBuffers)
2170 {
2171 RADV_FROM_HANDLE(radv_device, device, _device);
2172 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2173
2174 VkResult result = VK_SUCCESS;
2175 uint32_t i;
2176
2177 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2178
2179 if (!list_empty(&pool->free_cmd_buffers)) {
2180 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2181
2182 list_del(&cmd_buffer->pool_link);
2183 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2184
2185 result = radv_reset_cmd_buffer(cmd_buffer);
2186 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2187 cmd_buffer->level = pAllocateInfo->level;
2188
2189 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2190 } else {
2191 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2192 &pCommandBuffers[i]);
2193 }
2194 if (result != VK_SUCCESS)
2195 break;
2196 }
2197
2198 if (result != VK_SUCCESS) {
2199 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2200 i, pCommandBuffers);
2201
2202 /* From the Vulkan 1.0.66 spec:
2203 *
2204 * "vkAllocateCommandBuffers can be used to create multiple
2205 * command buffers. If the creation of any of those command
2206 * buffers fails, the implementation must destroy all
2207 * successfully created command buffer objects from this
2208 * command, set all entries of the pCommandBuffers array to
2209 * NULL and return the error."
2210 */
2211 memset(pCommandBuffers, 0,
2212 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2213 }
2214
2215 return result;
2216 }
2217
2218 void radv_FreeCommandBuffers(
2219 VkDevice device,
2220 VkCommandPool commandPool,
2221 uint32_t commandBufferCount,
2222 const VkCommandBuffer *pCommandBuffers)
2223 {
2224 for (uint32_t i = 0; i < commandBufferCount; i++) {
2225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2226
2227 if (cmd_buffer) {
2228 if (cmd_buffer->pool) {
2229 list_del(&cmd_buffer->pool_link);
2230 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2231 } else
2232 radv_cmd_buffer_destroy(cmd_buffer);
2233
2234 }
2235 }
2236 }
2237
2238 VkResult radv_ResetCommandBuffer(
2239 VkCommandBuffer commandBuffer,
2240 VkCommandBufferResetFlags flags)
2241 {
2242 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2243 return radv_reset_cmd_buffer(cmd_buffer);
2244 }
2245
2246 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2247 {
2248 struct radv_device *device = cmd_buffer->device;
2249 if (device->gfx_init) {
2250 uint64_t va = radv_buffer_get_va(device->gfx_init);
2251 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2252 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2253 radeon_emit(cmd_buffer->cs, va);
2254 radeon_emit(cmd_buffer->cs, va >> 32);
2255 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2256 } else
2257 si_init_config(cmd_buffer);
2258 }
2259
2260 VkResult radv_BeginCommandBuffer(
2261 VkCommandBuffer commandBuffer,
2262 const VkCommandBufferBeginInfo *pBeginInfo)
2263 {
2264 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2265 VkResult result = VK_SUCCESS;
2266
2267 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2268 /* If the command buffer has already been resetted with
2269 * vkResetCommandBuffer, no need to do it again.
2270 */
2271 result = radv_reset_cmd_buffer(cmd_buffer);
2272 if (result != VK_SUCCESS)
2273 return result;
2274 }
2275
2276 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2277 cmd_buffer->state.last_primitive_reset_en = -1;
2278 cmd_buffer->state.last_index_type = -1;
2279 cmd_buffer->usage_flags = pBeginInfo->flags;
2280
2281 /* setup initial configuration into command buffer */
2282 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2283 switch (cmd_buffer->queue_family_index) {
2284 case RADV_QUEUE_GENERAL:
2285 emit_gfx_buffer_state(cmd_buffer);
2286 break;
2287 case RADV_QUEUE_COMPUTE:
2288 si_init_compute(cmd_buffer);
2289 break;
2290 case RADV_QUEUE_TRANSFER:
2291 default:
2292 break;
2293 }
2294 }
2295
2296 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2297 assert(pBeginInfo->pInheritanceInfo);
2298 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2299 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2300
2301 struct radv_subpass *subpass =
2302 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2303
2304 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2305 if (result != VK_SUCCESS)
2306 return result;
2307
2308 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2309 }
2310
2311 if (unlikely(cmd_buffer->device->trace_bo))
2312 radv_cmd_buffer_trace_emit(cmd_buffer);
2313
2314 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2315
2316 return result;
2317 }
2318
2319 void radv_CmdBindVertexBuffers(
2320 VkCommandBuffer commandBuffer,
2321 uint32_t firstBinding,
2322 uint32_t bindingCount,
2323 const VkBuffer* pBuffers,
2324 const VkDeviceSize* pOffsets)
2325 {
2326 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2327 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2328 bool changed = false;
2329
2330 /* We have to defer setting up vertex buffer since we need the buffer
2331 * stride from the pipeline. */
2332
2333 assert(firstBinding + bindingCount <= MAX_VBS);
2334 for (uint32_t i = 0; i < bindingCount; i++) {
2335 uint32_t idx = firstBinding + i;
2336
2337 if (!changed &&
2338 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2339 vb[idx].offset != pOffsets[i])) {
2340 changed = true;
2341 }
2342
2343 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2344 vb[idx].offset = pOffsets[i];
2345
2346 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2347 vb[idx].buffer->bo, 8);
2348 }
2349
2350 if (!changed) {
2351 /* No state changes. */
2352 return;
2353 }
2354
2355 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2356 }
2357
2358 void radv_CmdBindIndexBuffer(
2359 VkCommandBuffer commandBuffer,
2360 VkBuffer buffer,
2361 VkDeviceSize offset,
2362 VkIndexType indexType)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2366
2367 if (cmd_buffer->state.index_buffer == index_buffer &&
2368 cmd_buffer->state.index_offset == offset &&
2369 cmd_buffer->state.index_type == indexType) {
2370 /* No state changes. */
2371 return;
2372 }
2373
2374 cmd_buffer->state.index_buffer = index_buffer;
2375 cmd_buffer->state.index_offset = offset;
2376 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2377 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2378 cmd_buffer->state.index_va += index_buffer->offset + offset;
2379
2380 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2381 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2382 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2383 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2384 }
2385
2386
2387 static void
2388 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2389 struct radv_descriptor_set *set, unsigned idx)
2390 {
2391 struct radeon_winsys *ws = cmd_buffer->device->ws;
2392
2393 radv_set_descriptor_set(cmd_buffer, set, idx);
2394 if (!set)
2395 return;
2396
2397 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2398
2399 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2400 if (set->descriptors[j])
2401 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2402
2403 if(set->bo)
2404 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2405 }
2406
2407 void radv_CmdBindDescriptorSets(
2408 VkCommandBuffer commandBuffer,
2409 VkPipelineBindPoint pipelineBindPoint,
2410 VkPipelineLayout _layout,
2411 uint32_t firstSet,
2412 uint32_t descriptorSetCount,
2413 const VkDescriptorSet* pDescriptorSets,
2414 uint32_t dynamicOffsetCount,
2415 const uint32_t* pDynamicOffsets)
2416 {
2417 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2418 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2419 unsigned dyn_idx = 0;
2420
2421 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2422 unsigned idx = i + firstSet;
2423 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2424 radv_bind_descriptor_set(cmd_buffer, set, idx);
2425
2426 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2427 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2428 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2429 assert(dyn_idx < dynamicOffsetCount);
2430
2431 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2432 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2433 dst[0] = va;
2434 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2435 dst[2] = range->size;
2436 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2437 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2438 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2439 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2440 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2441 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2442 cmd_buffer->push_constant_stages |=
2443 set->layout->dynamic_shader_stages;
2444 }
2445 }
2446 }
2447
2448 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2449 struct radv_descriptor_set *set,
2450 struct radv_descriptor_set_layout *layout)
2451 {
2452 set->size = layout->size;
2453 set->layout = layout;
2454
2455 if (cmd_buffer->push_descriptors.capacity < set->size) {
2456 size_t new_size = MAX2(set->size, 1024);
2457 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2458 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2459
2460 free(set->mapped_ptr);
2461 set->mapped_ptr = malloc(new_size);
2462
2463 if (!set->mapped_ptr) {
2464 cmd_buffer->push_descriptors.capacity = 0;
2465 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2466 return false;
2467 }
2468
2469 cmd_buffer->push_descriptors.capacity = new_size;
2470 }
2471
2472 return true;
2473 }
2474
2475 void radv_meta_push_descriptor_set(
2476 struct radv_cmd_buffer* cmd_buffer,
2477 VkPipelineBindPoint pipelineBindPoint,
2478 VkPipelineLayout _layout,
2479 uint32_t set,
2480 uint32_t descriptorWriteCount,
2481 const VkWriteDescriptorSet* pDescriptorWrites)
2482 {
2483 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2484 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2485 unsigned bo_offset;
2486
2487 assert(set == 0);
2488 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2489
2490 push_set->size = layout->set[set].layout->size;
2491 push_set->layout = layout->set[set].layout;
2492
2493 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2494 &bo_offset,
2495 (void**) &push_set->mapped_ptr))
2496 return;
2497
2498 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2499 push_set->va += bo_offset;
2500
2501 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2502 radv_descriptor_set_to_handle(push_set),
2503 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2504
2505 radv_set_descriptor_set(cmd_buffer, push_set, set);
2506 }
2507
2508 void radv_CmdPushDescriptorSetKHR(
2509 VkCommandBuffer commandBuffer,
2510 VkPipelineBindPoint pipelineBindPoint,
2511 VkPipelineLayout _layout,
2512 uint32_t set,
2513 uint32_t descriptorWriteCount,
2514 const VkWriteDescriptorSet* pDescriptorWrites)
2515 {
2516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2517 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2518 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2519
2520 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2521
2522 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2523 return;
2524
2525 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2526 radv_descriptor_set_to_handle(push_set),
2527 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2528
2529 radv_set_descriptor_set(cmd_buffer, push_set, set);
2530 cmd_buffer->state.push_descriptors_dirty = true;
2531 }
2532
2533 void radv_CmdPushDescriptorSetWithTemplateKHR(
2534 VkCommandBuffer commandBuffer,
2535 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2536 VkPipelineLayout _layout,
2537 uint32_t set,
2538 const void* pData)
2539 {
2540 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2541 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2542 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2543
2544 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2545
2546 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2547 return;
2548
2549 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2550 descriptorUpdateTemplate, pData);
2551
2552 radv_set_descriptor_set(cmd_buffer, push_set, set);
2553 cmd_buffer->state.push_descriptors_dirty = true;
2554 }
2555
2556 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2557 VkPipelineLayout layout,
2558 VkShaderStageFlags stageFlags,
2559 uint32_t offset,
2560 uint32_t size,
2561 const void* pValues)
2562 {
2563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2564 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2565 cmd_buffer->push_constant_stages |= stageFlags;
2566 }
2567
2568 VkResult radv_EndCommandBuffer(
2569 VkCommandBuffer commandBuffer)
2570 {
2571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2572
2573 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2574 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2575 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2576 si_emit_cache_flush(cmd_buffer);
2577 }
2578
2579 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2580
2581 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2582 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2583
2584 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2585
2586 return cmd_buffer->record_result;
2587 }
2588
2589 static void
2590 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2591 {
2592 struct radv_shader_variant *compute_shader;
2593 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2594 struct radv_device *device = cmd_buffer->device;
2595 unsigned compute_resource_limits;
2596 unsigned waves_per_threadgroup;
2597 uint64_t va;
2598
2599 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2600 return;
2601
2602 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2603
2604 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2605 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2606
2607 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2608 cmd_buffer->cs, 19);
2609
2610 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2611 radeon_emit(cmd_buffer->cs, va >> 8);
2612 radeon_emit(cmd_buffer->cs, va >> 40);
2613
2614 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2615 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2616 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2617
2618
2619 cmd_buffer->compute_scratch_size_needed =
2620 MAX2(cmd_buffer->compute_scratch_size_needed,
2621 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2622
2623 /* change these once we have scratch support */
2624 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2625 S_00B860_WAVES(pipeline->max_waves) |
2626 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2627
2628 /* Calculate best compute resource limits. */
2629 waves_per_threadgroup =
2630 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2631 compute_shader->info.cs.block_size[1] *
2632 compute_shader->info.cs.block_size[2], 64);
2633 compute_resource_limits =
2634 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2635
2636 if (device->physical_device->rad_info.chip_class >= CIK) {
2637 unsigned num_cu_per_se =
2638 device->physical_device->rad_info.num_good_compute_units /
2639 device->physical_device->rad_info.max_se;
2640
2641 /* Force even distribution on all SIMDs in CU if the workgroup
2642 * size is 64. This has shown some good improvements if # of
2643 * CUs per SE is not a multiple of 4.
2644 */
2645 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2646 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2647 }
2648
2649 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2650 compute_resource_limits);
2651
2652 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2653 radeon_emit(cmd_buffer->cs,
2654 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2655 radeon_emit(cmd_buffer->cs,
2656 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2657 radeon_emit(cmd_buffer->cs,
2658 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2659
2660 assert(cmd_buffer->cs->cdw <= cdw_max);
2661
2662 if (unlikely(cmd_buffer->device->trace_bo))
2663 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2664 }
2665
2666 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2667 {
2668 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2669 }
2670
2671 void radv_CmdBindPipeline(
2672 VkCommandBuffer commandBuffer,
2673 VkPipelineBindPoint pipelineBindPoint,
2674 VkPipeline _pipeline)
2675 {
2676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2677 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2678
2679 switch (pipelineBindPoint) {
2680 case VK_PIPELINE_BIND_POINT_COMPUTE:
2681 if (cmd_buffer->state.compute_pipeline == pipeline)
2682 return;
2683 radv_mark_descriptor_sets_dirty(cmd_buffer);
2684
2685 cmd_buffer->state.compute_pipeline = pipeline;
2686 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2687 break;
2688 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2689 if (cmd_buffer->state.pipeline == pipeline)
2690 return;
2691 radv_mark_descriptor_sets_dirty(cmd_buffer);
2692
2693 cmd_buffer->state.pipeline = pipeline;
2694 if (!pipeline)
2695 break;
2696
2697 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2698 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2699
2700 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2701
2702 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2703 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2704 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2705 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2706
2707 if (radv_pipeline_has_tess(pipeline))
2708 cmd_buffer->tess_rings_needed = true;
2709
2710 if (radv_pipeline_has_gs(pipeline)) {
2711 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2712 AC_UD_SCRATCH_RING_OFFSETS);
2713 if (cmd_buffer->ring_offsets_idx == -1)
2714 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2715 else if (loc->sgpr_idx != -1)
2716 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2717 }
2718 break;
2719 default:
2720 assert(!"invalid bind point");
2721 break;
2722 }
2723 }
2724
2725 void radv_CmdSetViewport(
2726 VkCommandBuffer commandBuffer,
2727 uint32_t firstViewport,
2728 uint32_t viewportCount,
2729 const VkViewport* pViewports)
2730 {
2731 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2732 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2733
2734 assert(firstViewport < MAX_VIEWPORTS);
2735 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2736
2737 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2738 pViewports, viewportCount * sizeof(*pViewports));
2739
2740 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2741 }
2742
2743 void radv_CmdSetScissor(
2744 VkCommandBuffer commandBuffer,
2745 uint32_t firstScissor,
2746 uint32_t scissorCount,
2747 const VkRect2D* pScissors)
2748 {
2749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2750 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2751
2752 assert(firstScissor < MAX_SCISSORS);
2753 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2754
2755 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2756 pScissors, scissorCount * sizeof(*pScissors));
2757 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2758 }
2759
2760 void radv_CmdSetLineWidth(
2761 VkCommandBuffer commandBuffer,
2762 float lineWidth)
2763 {
2764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2765 cmd_buffer->state.dynamic.line_width = lineWidth;
2766 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2767 }
2768
2769 void radv_CmdSetDepthBias(
2770 VkCommandBuffer commandBuffer,
2771 float depthBiasConstantFactor,
2772 float depthBiasClamp,
2773 float depthBiasSlopeFactor)
2774 {
2775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2776
2777 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2778 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2779 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2780
2781 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2782 }
2783
2784 void radv_CmdSetBlendConstants(
2785 VkCommandBuffer commandBuffer,
2786 const float blendConstants[4])
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789
2790 memcpy(cmd_buffer->state.dynamic.blend_constants,
2791 blendConstants, sizeof(float) * 4);
2792
2793 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2794 }
2795
2796 void radv_CmdSetDepthBounds(
2797 VkCommandBuffer commandBuffer,
2798 float minDepthBounds,
2799 float maxDepthBounds)
2800 {
2801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2802
2803 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2804 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2805
2806 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2807 }
2808
2809 void radv_CmdSetStencilCompareMask(
2810 VkCommandBuffer commandBuffer,
2811 VkStencilFaceFlags faceMask,
2812 uint32_t compareMask)
2813 {
2814 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2815
2816 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2817 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2818 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2819 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2820
2821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2822 }
2823
2824 void radv_CmdSetStencilWriteMask(
2825 VkCommandBuffer commandBuffer,
2826 VkStencilFaceFlags faceMask,
2827 uint32_t writeMask)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2830
2831 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2832 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2833 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2834 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2835
2836 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2837 }
2838
2839 void radv_CmdSetStencilReference(
2840 VkCommandBuffer commandBuffer,
2841 VkStencilFaceFlags faceMask,
2842 uint32_t reference)
2843 {
2844 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2845
2846 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2847 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2848 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2849 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2850
2851 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2852 }
2853
2854 void radv_CmdExecuteCommands(
2855 VkCommandBuffer commandBuffer,
2856 uint32_t commandBufferCount,
2857 const VkCommandBuffer* pCmdBuffers)
2858 {
2859 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2860
2861 assert(commandBufferCount > 0);
2862
2863 /* Emit pending flushes on primary prior to executing secondary */
2864 si_emit_cache_flush(primary);
2865
2866 for (uint32_t i = 0; i < commandBufferCount; i++) {
2867 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2868
2869 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2870 secondary->scratch_size_needed);
2871 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2872 secondary->compute_scratch_size_needed);
2873
2874 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2875 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2876 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2877 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2878 if (secondary->tess_rings_needed)
2879 primary->tess_rings_needed = true;
2880 if (secondary->sample_positions_needed)
2881 primary->sample_positions_needed = true;
2882
2883 if (secondary->ring_offsets_idx != -1) {
2884 if (primary->ring_offsets_idx == -1)
2885 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2886 else
2887 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2888 }
2889 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2890
2891
2892 /* When the secondary command buffer is compute only we don't
2893 * need to re-emit the current graphics pipeline.
2894 */
2895 if (secondary->state.emitted_pipeline) {
2896 primary->state.emitted_pipeline =
2897 secondary->state.emitted_pipeline;
2898 }
2899
2900 /* When the secondary command buffer is graphics only we don't
2901 * need to re-emit the current compute pipeline.
2902 */
2903 if (secondary->state.emitted_compute_pipeline) {
2904 primary->state.emitted_compute_pipeline =
2905 secondary->state.emitted_compute_pipeline;
2906 }
2907
2908 /* Only re-emit the draw packets when needed. */
2909 if (secondary->state.last_primitive_reset_en != -1) {
2910 primary->state.last_primitive_reset_en =
2911 secondary->state.last_primitive_reset_en;
2912 }
2913
2914 if (secondary->state.last_primitive_reset_index) {
2915 primary->state.last_primitive_reset_index =
2916 secondary->state.last_primitive_reset_index;
2917 }
2918
2919 if (secondary->state.last_ia_multi_vgt_param) {
2920 primary->state.last_ia_multi_vgt_param =
2921 secondary->state.last_ia_multi_vgt_param;
2922 }
2923
2924 if (secondary->state.last_index_type != -1) {
2925 primary->state.last_index_type =
2926 secondary->state.last_index_type;
2927 }
2928 }
2929
2930 /* After executing commands from secondary buffers we have to dirty
2931 * some states.
2932 */
2933 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2934 RADV_CMD_DIRTY_INDEX_BUFFER |
2935 RADV_CMD_DIRTY_DYNAMIC_ALL;
2936 radv_mark_descriptor_sets_dirty(primary);
2937 }
2938
2939 VkResult radv_CreateCommandPool(
2940 VkDevice _device,
2941 const VkCommandPoolCreateInfo* pCreateInfo,
2942 const VkAllocationCallbacks* pAllocator,
2943 VkCommandPool* pCmdPool)
2944 {
2945 RADV_FROM_HANDLE(radv_device, device, _device);
2946 struct radv_cmd_pool *pool;
2947
2948 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2949 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2950 if (pool == NULL)
2951 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2952
2953 if (pAllocator)
2954 pool->alloc = *pAllocator;
2955 else
2956 pool->alloc = device->alloc;
2957
2958 list_inithead(&pool->cmd_buffers);
2959 list_inithead(&pool->free_cmd_buffers);
2960
2961 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2962
2963 *pCmdPool = radv_cmd_pool_to_handle(pool);
2964
2965 return VK_SUCCESS;
2966
2967 }
2968
2969 void radv_DestroyCommandPool(
2970 VkDevice _device,
2971 VkCommandPool commandPool,
2972 const VkAllocationCallbacks* pAllocator)
2973 {
2974 RADV_FROM_HANDLE(radv_device, device, _device);
2975 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2976
2977 if (!pool)
2978 return;
2979
2980 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2981 &pool->cmd_buffers, pool_link) {
2982 radv_cmd_buffer_destroy(cmd_buffer);
2983 }
2984
2985 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2986 &pool->free_cmd_buffers, pool_link) {
2987 radv_cmd_buffer_destroy(cmd_buffer);
2988 }
2989
2990 vk_free2(&device->alloc, pAllocator, pool);
2991 }
2992
2993 VkResult radv_ResetCommandPool(
2994 VkDevice device,
2995 VkCommandPool commandPool,
2996 VkCommandPoolResetFlags flags)
2997 {
2998 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2999 VkResult result;
3000
3001 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3002 &pool->cmd_buffers, pool_link) {
3003 result = radv_reset_cmd_buffer(cmd_buffer);
3004 if (result != VK_SUCCESS)
3005 return result;
3006 }
3007
3008 return VK_SUCCESS;
3009 }
3010
3011 void radv_TrimCommandPoolKHR(
3012 VkDevice device,
3013 VkCommandPool commandPool,
3014 VkCommandPoolTrimFlagsKHR flags)
3015 {
3016 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3017
3018 if (!pool)
3019 return;
3020
3021 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3022 &pool->free_cmd_buffers, pool_link) {
3023 radv_cmd_buffer_destroy(cmd_buffer);
3024 }
3025 }
3026
3027 void radv_CmdBeginRenderPass(
3028 VkCommandBuffer commandBuffer,
3029 const VkRenderPassBeginInfo* pRenderPassBegin,
3030 VkSubpassContents contents)
3031 {
3032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3033 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3034 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3035
3036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3037 cmd_buffer->cs, 2048);
3038 MAYBE_UNUSED VkResult result;
3039
3040 cmd_buffer->state.framebuffer = framebuffer;
3041 cmd_buffer->state.pass = pass;
3042 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3043
3044 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3045 if (result != VK_SUCCESS)
3046 return;
3047
3048 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3049 assert(cmd_buffer->cs->cdw <= cdw_max);
3050
3051 radv_cmd_buffer_clear_subpass(cmd_buffer);
3052 }
3053
3054 void radv_CmdNextSubpass(
3055 VkCommandBuffer commandBuffer,
3056 VkSubpassContents contents)
3057 {
3058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3059
3060 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3061
3062 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3063 2048);
3064
3065 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3066 radv_cmd_buffer_clear_subpass(cmd_buffer);
3067 }
3068
3069 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3070 {
3071 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3072 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3073 if (!pipeline->shaders[stage])
3074 continue;
3075 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3076 if (loc->sgpr_idx == -1)
3077 continue;
3078 uint32_t base_reg = pipeline->user_data_0[stage];
3079 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3080
3081 }
3082 if (pipeline->gs_copy_shader) {
3083 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3084 if (loc->sgpr_idx != -1) {
3085 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3086 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3087 }
3088 }
3089 }
3090
3091 static void
3092 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3093 uint32_t vertex_count)
3094 {
3095 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3096 radeon_emit(cmd_buffer->cs, vertex_count);
3097 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3098 S_0287F0_USE_OPAQUE(0));
3099 }
3100
3101 static void
3102 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3103 uint64_t index_va,
3104 uint32_t index_count)
3105 {
3106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3107 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3108 radeon_emit(cmd_buffer->cs, index_va);
3109 radeon_emit(cmd_buffer->cs, index_va >> 32);
3110 radeon_emit(cmd_buffer->cs, index_count);
3111 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3112 }
3113
3114 static void
3115 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3116 bool indexed,
3117 uint32_t draw_count,
3118 uint64_t count_va,
3119 uint32_t stride)
3120 {
3121 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3122 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3123 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3124 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3125 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3126 assert(base_reg);
3127
3128 if (draw_count == 1 && !count_va && !draw_id_enable) {
3129 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3130 PKT3_DRAW_INDIRECT, 3, false));
3131 radeon_emit(cs, 0);
3132 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3133 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3134 radeon_emit(cs, di_src_sel);
3135 } else {
3136 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3137 PKT3_DRAW_INDIRECT_MULTI,
3138 8, false));
3139 radeon_emit(cs, 0);
3140 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3141 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3142 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3143 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3144 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3145 radeon_emit(cs, draw_count); /* count */
3146 radeon_emit(cs, count_va); /* count_addr */
3147 radeon_emit(cs, count_va >> 32);
3148 radeon_emit(cs, stride); /* stride */
3149 radeon_emit(cs, di_src_sel);
3150 }
3151 }
3152
3153 struct radv_draw_info {
3154 /**
3155 * Number of vertices.
3156 */
3157 uint32_t count;
3158
3159 /**
3160 * Index of the first vertex.
3161 */
3162 int32_t vertex_offset;
3163
3164 /**
3165 * First instance id.
3166 */
3167 uint32_t first_instance;
3168
3169 /**
3170 * Number of instances.
3171 */
3172 uint32_t instance_count;
3173
3174 /**
3175 * First index (indexed draws only).
3176 */
3177 uint32_t first_index;
3178
3179 /**
3180 * Whether it's an indexed draw.
3181 */
3182 bool indexed;
3183
3184 /**
3185 * Indirect draw parameters resource.
3186 */
3187 struct radv_buffer *indirect;
3188 uint64_t indirect_offset;
3189 uint32_t stride;
3190
3191 /**
3192 * Draw count parameters resource.
3193 */
3194 struct radv_buffer *count_buffer;
3195 uint64_t count_buffer_offset;
3196 };
3197
3198 static void
3199 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3200 const struct radv_draw_info *info)
3201 {
3202 struct radv_cmd_state *state = &cmd_buffer->state;
3203 struct radeon_winsys *ws = cmd_buffer->device->ws;
3204 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3205
3206 if (info->indirect) {
3207 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3208 uint64_t count_va = 0;
3209
3210 va += info->indirect->offset + info->indirect_offset;
3211
3212 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3213
3214 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3215 radeon_emit(cs, 1);
3216 radeon_emit(cs, va);
3217 radeon_emit(cs, va >> 32);
3218
3219 if (info->count_buffer) {
3220 count_va = radv_buffer_get_va(info->count_buffer->bo);
3221 count_va += info->count_buffer->offset +
3222 info->count_buffer_offset;
3223
3224 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3225 }
3226
3227 if (!state->subpass->view_mask) {
3228 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3229 info->indexed,
3230 info->count,
3231 count_va,
3232 info->stride);
3233 } else {
3234 unsigned i;
3235 for_each_bit(i, state->subpass->view_mask) {
3236 radv_emit_view_index(cmd_buffer, i);
3237
3238 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3239 info->indexed,
3240 info->count,
3241 count_va,
3242 info->stride);
3243 }
3244 }
3245 } else {
3246 assert(state->pipeline->graphics.vtx_base_sgpr);
3247 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3248 state->pipeline->graphics.vtx_emit_num);
3249 radeon_emit(cs, info->vertex_offset);
3250 radeon_emit(cs, info->first_instance);
3251 if (state->pipeline->graphics.vtx_emit_num == 3)
3252 radeon_emit(cs, 0);
3253
3254 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3255 radeon_emit(cs, info->instance_count);
3256
3257 if (info->indexed) {
3258 int index_size = state->index_type ? 4 : 2;
3259 uint64_t index_va;
3260
3261 index_va = state->index_va;
3262 index_va += info->first_index * index_size;
3263
3264 if (!state->subpass->view_mask) {
3265 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3266 index_va,
3267 info->count);
3268 } else {
3269 unsigned i;
3270 for_each_bit(i, state->subpass->view_mask) {
3271 radv_emit_view_index(cmd_buffer, i);
3272
3273 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3274 index_va,
3275 info->count);
3276 }
3277 }
3278 } else {
3279 if (!state->subpass->view_mask) {
3280 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3281 } else {
3282 unsigned i;
3283 for_each_bit(i, state->subpass->view_mask) {
3284 radv_emit_view_index(cmd_buffer, i);
3285
3286 radv_cs_emit_draw_packet(cmd_buffer,
3287 info->count);
3288 }
3289 }
3290 }
3291 }
3292 }
3293
3294 static void
3295 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3296 const struct radv_draw_info *info)
3297 {
3298 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3299 radv_emit_graphics_pipeline(cmd_buffer);
3300
3301 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3302 radv_emit_framebuffer_state(cmd_buffer);
3303
3304 if (info->indexed) {
3305 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3306 radv_emit_index_buffer(cmd_buffer);
3307 } else {
3308 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3309 * so the state must be re-emitted before the next indexed
3310 * draw.
3311 */
3312 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3313 cmd_buffer->state.last_index_type = -1;
3314 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3315 }
3316 }
3317
3318 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3319
3320 radv_emit_draw_registers(cmd_buffer, info->indexed,
3321 info->instance_count > 1, info->indirect,
3322 info->indirect ? 0 : info->count);
3323 }
3324
3325 static void
3326 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3327 const struct radv_draw_info *info)
3328 {
3329 bool pipeline_is_dirty =
3330 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3331 cmd_buffer->state.pipeline &&
3332 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3333
3334 MAYBE_UNUSED unsigned cdw_max =
3335 radeon_check_space(cmd_buffer->device->ws,
3336 cmd_buffer->cs, 4096);
3337
3338 /* Use optimal packet order based on whether we need to sync the
3339 * pipeline.
3340 */
3341 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3342 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3343 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3344 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3345 /* If we have to wait for idle, set all states first, so that
3346 * all SET packets are processed in parallel with previous draw
3347 * calls. Then upload descriptors, set shader pointers, and
3348 * draw, and prefetch at the end. This ensures that the time
3349 * the CUs are idle is very short. (there are only SET_SH
3350 * packets between the wait and the draw)
3351 */
3352 radv_emit_all_graphics_states(cmd_buffer, info);
3353 si_emit_cache_flush(cmd_buffer);
3354 /* <-- CUs are idle here --> */
3355
3356 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3357 return;
3358
3359 radv_emit_draw_packets(cmd_buffer, info);
3360 /* <-- CUs are busy here --> */
3361
3362 /* Start prefetches after the draw has been started. Both will
3363 * run in parallel, but starting the draw first is more
3364 * important.
3365 */
3366 if (pipeline_is_dirty) {
3367 radv_emit_prefetch(cmd_buffer,
3368 cmd_buffer->state.pipeline);
3369 }
3370 } else {
3371 /* If we don't wait for idle, start prefetches first, then set
3372 * states, and draw at the end.
3373 */
3374 si_emit_cache_flush(cmd_buffer);
3375
3376 if (pipeline_is_dirty) {
3377 radv_emit_prefetch(cmd_buffer,
3378 cmd_buffer->state.pipeline);
3379 }
3380
3381 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3382 return;
3383
3384 radv_emit_all_graphics_states(cmd_buffer, info);
3385 radv_emit_draw_packets(cmd_buffer, info);
3386 }
3387
3388 assert(cmd_buffer->cs->cdw <= cdw_max);
3389 radv_cmd_buffer_after_draw(cmd_buffer);
3390 }
3391
3392 void radv_CmdDraw(
3393 VkCommandBuffer commandBuffer,
3394 uint32_t vertexCount,
3395 uint32_t instanceCount,
3396 uint32_t firstVertex,
3397 uint32_t firstInstance)
3398 {
3399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3400 struct radv_draw_info info = {};
3401
3402 info.count = vertexCount;
3403 info.instance_count = instanceCount;
3404 info.first_instance = firstInstance;
3405 info.vertex_offset = firstVertex;
3406
3407 radv_draw(cmd_buffer, &info);
3408 }
3409
3410 void radv_CmdDrawIndexed(
3411 VkCommandBuffer commandBuffer,
3412 uint32_t indexCount,
3413 uint32_t instanceCount,
3414 uint32_t firstIndex,
3415 int32_t vertexOffset,
3416 uint32_t firstInstance)
3417 {
3418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3419 struct radv_draw_info info = {};
3420
3421 info.indexed = true;
3422 info.count = indexCount;
3423 info.instance_count = instanceCount;
3424 info.first_index = firstIndex;
3425 info.vertex_offset = vertexOffset;
3426 info.first_instance = firstInstance;
3427
3428 radv_draw(cmd_buffer, &info);
3429 }
3430
3431 void radv_CmdDrawIndirect(
3432 VkCommandBuffer commandBuffer,
3433 VkBuffer _buffer,
3434 VkDeviceSize offset,
3435 uint32_t drawCount,
3436 uint32_t stride)
3437 {
3438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3439 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3440 struct radv_draw_info info = {};
3441
3442 info.count = drawCount;
3443 info.indirect = buffer;
3444 info.indirect_offset = offset;
3445 info.stride = stride;
3446
3447 radv_draw(cmd_buffer, &info);
3448 }
3449
3450 void radv_CmdDrawIndexedIndirect(
3451 VkCommandBuffer commandBuffer,
3452 VkBuffer _buffer,
3453 VkDeviceSize offset,
3454 uint32_t drawCount,
3455 uint32_t stride)
3456 {
3457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3458 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3459 struct radv_draw_info info = {};
3460
3461 info.indexed = true;
3462 info.count = drawCount;
3463 info.indirect = buffer;
3464 info.indirect_offset = offset;
3465 info.stride = stride;
3466
3467 radv_draw(cmd_buffer, &info);
3468 }
3469
3470 void radv_CmdDrawIndirectCountAMD(
3471 VkCommandBuffer commandBuffer,
3472 VkBuffer _buffer,
3473 VkDeviceSize offset,
3474 VkBuffer _countBuffer,
3475 VkDeviceSize countBufferOffset,
3476 uint32_t maxDrawCount,
3477 uint32_t stride)
3478 {
3479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3480 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3481 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3482 struct radv_draw_info info = {};
3483
3484 info.count = maxDrawCount;
3485 info.indirect = buffer;
3486 info.indirect_offset = offset;
3487 info.count_buffer = count_buffer;
3488 info.count_buffer_offset = countBufferOffset;
3489 info.stride = stride;
3490
3491 radv_draw(cmd_buffer, &info);
3492 }
3493
3494 void radv_CmdDrawIndexedIndirectCountAMD(
3495 VkCommandBuffer commandBuffer,
3496 VkBuffer _buffer,
3497 VkDeviceSize offset,
3498 VkBuffer _countBuffer,
3499 VkDeviceSize countBufferOffset,
3500 uint32_t maxDrawCount,
3501 uint32_t stride)
3502 {
3503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3504 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3505 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3506 struct radv_draw_info info = {};
3507
3508 info.indexed = true;
3509 info.count = maxDrawCount;
3510 info.indirect = buffer;
3511 info.indirect_offset = offset;
3512 info.count_buffer = count_buffer;
3513 info.count_buffer_offset = countBufferOffset;
3514 info.stride = stride;
3515
3516 radv_draw(cmd_buffer, &info);
3517 }
3518
3519 struct radv_dispatch_info {
3520 /**
3521 * Determine the layout of the grid (in block units) to be used.
3522 */
3523 uint32_t blocks[3];
3524
3525 /**
3526 * Whether it's an unaligned compute dispatch.
3527 */
3528 bool unaligned;
3529
3530 /**
3531 * Indirect compute parameters resource.
3532 */
3533 struct radv_buffer *indirect;
3534 uint64_t indirect_offset;
3535 };
3536
3537 static void
3538 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3539 const struct radv_dispatch_info *info)
3540 {
3541 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3542 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3543 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3544 struct radeon_winsys *ws = cmd_buffer->device->ws;
3545 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3546 struct ac_userdata_info *loc;
3547
3548 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3549 AC_UD_CS_GRID_SIZE);
3550
3551 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3552
3553 if (info->indirect) {
3554 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3555
3556 va += info->indirect->offset + info->indirect_offset;
3557
3558 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3559
3560 if (loc->sgpr_idx != -1) {
3561 for (unsigned i = 0; i < 3; ++i) {
3562 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3563 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3564 COPY_DATA_DST_SEL(COPY_DATA_REG));
3565 radeon_emit(cs, (va + 4 * i));
3566 radeon_emit(cs, (va + 4 * i) >> 32);
3567 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3568 + loc->sgpr_idx * 4) >> 2) + i);
3569 radeon_emit(cs, 0);
3570 }
3571 }
3572
3573 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3574 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3575 PKT3_SHADER_TYPE_S(1));
3576 radeon_emit(cs, va);
3577 radeon_emit(cs, va >> 32);
3578 radeon_emit(cs, dispatch_initiator);
3579 } else {
3580 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3581 PKT3_SHADER_TYPE_S(1));
3582 radeon_emit(cs, 1);
3583 radeon_emit(cs, va);
3584 radeon_emit(cs, va >> 32);
3585
3586 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3587 PKT3_SHADER_TYPE_S(1));
3588 radeon_emit(cs, 0);
3589 radeon_emit(cs, dispatch_initiator);
3590 }
3591 } else {
3592 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3593
3594 if (info->unaligned) {
3595 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3596 unsigned remainder[3];
3597
3598 /* If aligned, these should be an entire block size,
3599 * not 0.
3600 */
3601 remainder[0] = blocks[0] + cs_block_size[0] -
3602 align_u32_npot(blocks[0], cs_block_size[0]);
3603 remainder[1] = blocks[1] + cs_block_size[1] -
3604 align_u32_npot(blocks[1], cs_block_size[1]);
3605 remainder[2] = blocks[2] + cs_block_size[2] -
3606 align_u32_npot(blocks[2], cs_block_size[2]);
3607
3608 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3609 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3610 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3611
3612 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3613 radeon_emit(cs,
3614 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3615 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3616 radeon_emit(cs,
3617 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3618 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3619 radeon_emit(cs,
3620 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3621 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3622
3623 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3624 }
3625
3626 if (loc->sgpr_idx != -1) {
3627 assert(!loc->indirect);
3628 assert(loc->num_sgprs == 3);
3629
3630 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3631 loc->sgpr_idx * 4, 3);
3632 radeon_emit(cs, blocks[0]);
3633 radeon_emit(cs, blocks[1]);
3634 radeon_emit(cs, blocks[2]);
3635 }
3636
3637 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3638 PKT3_SHADER_TYPE_S(1));
3639 radeon_emit(cs, blocks[0]);
3640 radeon_emit(cs, blocks[1]);
3641 radeon_emit(cs, blocks[2]);
3642 radeon_emit(cs, dispatch_initiator);
3643 }
3644
3645 assert(cmd_buffer->cs->cdw <= cdw_max);
3646 }
3647
3648 static void
3649 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3650 {
3651 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3652 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3653 VK_SHADER_STAGE_COMPUTE_BIT);
3654 }
3655
3656 static void
3657 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3658 const struct radv_dispatch_info *info)
3659 {
3660 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3661 bool pipeline_is_dirty = pipeline &&
3662 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3663
3664 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3665 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3666 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3667 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3668 /* If we have to wait for idle, set all states first, so that
3669 * all SET packets are processed in parallel with previous draw
3670 * calls. Then upload descriptors, set shader pointers, and
3671 * dispatch, and prefetch at the end. This ensures that the
3672 * time the CUs are idle is very short. (there are only SET_SH
3673 * packets between the wait and the draw)
3674 */
3675 radv_emit_compute_pipeline(cmd_buffer);
3676 si_emit_cache_flush(cmd_buffer);
3677 /* <-- CUs are idle here --> */
3678
3679 radv_upload_compute_shader_descriptors(cmd_buffer);
3680
3681 radv_emit_dispatch_packets(cmd_buffer, info);
3682 /* <-- CUs are busy here --> */
3683
3684 /* Start prefetches after the dispatch has been started. Both
3685 * will run in parallel, but starting the dispatch first is
3686 * more important.
3687 */
3688 if (pipeline_is_dirty) {
3689 radv_emit_shader_prefetch(cmd_buffer,
3690 pipeline->shaders[MESA_SHADER_COMPUTE]);
3691 }
3692 } else {
3693 /* If we don't wait for idle, start prefetches first, then set
3694 * states, and dispatch at the end.
3695 */
3696 si_emit_cache_flush(cmd_buffer);
3697
3698 if (pipeline_is_dirty) {
3699 radv_emit_shader_prefetch(cmd_buffer,
3700 pipeline->shaders[MESA_SHADER_COMPUTE]);
3701 }
3702
3703 radv_upload_compute_shader_descriptors(cmd_buffer);
3704
3705 radv_emit_compute_pipeline(cmd_buffer);
3706 radv_emit_dispatch_packets(cmd_buffer, info);
3707 }
3708
3709 radv_cmd_buffer_after_draw(cmd_buffer);
3710 }
3711
3712 void radv_CmdDispatch(
3713 VkCommandBuffer commandBuffer,
3714 uint32_t x,
3715 uint32_t y,
3716 uint32_t z)
3717 {
3718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3719 struct radv_dispatch_info info = {};
3720
3721 info.blocks[0] = x;
3722 info.blocks[1] = y;
3723 info.blocks[2] = z;
3724
3725 radv_dispatch(cmd_buffer, &info);
3726 }
3727
3728 void radv_CmdDispatchIndirect(
3729 VkCommandBuffer commandBuffer,
3730 VkBuffer _buffer,
3731 VkDeviceSize offset)
3732 {
3733 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3734 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3735 struct radv_dispatch_info info = {};
3736
3737 info.indirect = buffer;
3738 info.indirect_offset = offset;
3739
3740 radv_dispatch(cmd_buffer, &info);
3741 }
3742
3743 void radv_unaligned_dispatch(
3744 struct radv_cmd_buffer *cmd_buffer,
3745 uint32_t x,
3746 uint32_t y,
3747 uint32_t z)
3748 {
3749 struct radv_dispatch_info info = {};
3750
3751 info.blocks[0] = x;
3752 info.blocks[1] = y;
3753 info.blocks[2] = z;
3754 info.unaligned = 1;
3755
3756 radv_dispatch(cmd_buffer, &info);
3757 }
3758
3759 void radv_CmdEndRenderPass(
3760 VkCommandBuffer commandBuffer)
3761 {
3762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3763
3764 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3765
3766 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3767
3768 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3769 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3770 radv_handle_subpass_image_transition(cmd_buffer,
3771 (VkAttachmentReference){i, layout});
3772 }
3773
3774 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3775
3776 cmd_buffer->state.pass = NULL;
3777 cmd_buffer->state.subpass = NULL;
3778 cmd_buffer->state.attachments = NULL;
3779 cmd_buffer->state.framebuffer = NULL;
3780 }
3781
3782 /*
3783 * For HTILE we have the following interesting clear words:
3784 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3785 * 0x0000000f: Uncompressed for depth only HTILE.
3786 * 0xfffffff0: Clear depth to 1.0
3787 * 0x00000000: Clear depth to 0.0
3788 */
3789 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3790 struct radv_image *image,
3791 const VkImageSubresourceRange *range,
3792 uint32_t clear_word)
3793 {
3794 assert(range->baseMipLevel == 0);
3795 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3796 unsigned layer_count = radv_get_layerCount(image, range);
3797 uint64_t size = image->surface.htile_slice_size * layer_count;
3798 uint64_t offset = image->offset + image->htile_offset +
3799 image->surface.htile_slice_size * range->baseArrayLayer;
3800 struct radv_cmd_state *state = &cmd_buffer->state;
3801
3802 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3803 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3804
3805 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3806 size, clear_word);
3807
3808 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3809 }
3810
3811 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3812 struct radv_image *image,
3813 VkImageLayout src_layout,
3814 VkImageLayout dst_layout,
3815 unsigned src_queue_mask,
3816 unsigned dst_queue_mask,
3817 const VkImageSubresourceRange *range,
3818 VkImageAspectFlags pending_clears)
3819 {
3820 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3821 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3822 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3823 cmd_buffer->state.render_area.extent.width == image->info.width &&
3824 cmd_buffer->state.render_area.extent.height == image->info.height) {
3825 /* The clear will initialize htile. */
3826 return;
3827 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3828 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3829 /* TODO: merge with the clear if applicable */
3830 radv_initialize_htile(cmd_buffer, image, range, 0);
3831 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3832 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3833 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3834 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3835 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3836 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3837 VkImageSubresourceRange local_range = *range;
3838 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3839 local_range.baseMipLevel = 0;
3840 local_range.levelCount = 1;
3841
3842 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3843 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3844
3845 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3846
3847 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3848 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3849 }
3850 }
3851
3852 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3853 struct radv_image *image, uint32_t value)
3854 {
3855 struct radv_cmd_state *state = &cmd_buffer->state;
3856
3857 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3858 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3859
3860 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3861 image->offset + image->cmask.offset,
3862 image->cmask.size, value);
3863
3864 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3865 }
3866
3867 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3868 struct radv_image *image,
3869 VkImageLayout src_layout,
3870 VkImageLayout dst_layout,
3871 unsigned src_queue_mask,
3872 unsigned dst_queue_mask,
3873 const VkImageSubresourceRange *range)
3874 {
3875 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3876 if (image->fmask.size)
3877 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3878 else
3879 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3880 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3881 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3882 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3883 }
3884 }
3885
3886 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3887 struct radv_image *image, uint32_t value)
3888 {
3889 struct radv_cmd_state *state = &cmd_buffer->state;
3890
3891 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3892 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3893
3894 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3895 image->offset + image->dcc_offset,
3896 image->surface.dcc_size, value);
3897
3898 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3899 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3900 }
3901
3902 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3903 struct radv_image *image,
3904 VkImageLayout src_layout,
3905 VkImageLayout dst_layout,
3906 unsigned src_queue_mask,
3907 unsigned dst_queue_mask,
3908 const VkImageSubresourceRange *range)
3909 {
3910 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3911 radv_initialize_dcc(cmd_buffer, image,
3912 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3913 0x20202020u : 0xffffffffu);
3914 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3915 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3916 radv_decompress_dcc(cmd_buffer, image, range);
3917 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3918 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3919 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3920 }
3921 }
3922
3923 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3924 struct radv_image *image,
3925 VkImageLayout src_layout,
3926 VkImageLayout dst_layout,
3927 uint32_t src_family,
3928 uint32_t dst_family,
3929 const VkImageSubresourceRange *range,
3930 VkImageAspectFlags pending_clears)
3931 {
3932 if (image->exclusive && src_family != dst_family) {
3933 /* This is an acquire or a release operation and there will be
3934 * a corresponding release/acquire. Do the transition in the
3935 * most flexible queue. */
3936
3937 assert(src_family == cmd_buffer->queue_family_index ||
3938 dst_family == cmd_buffer->queue_family_index);
3939
3940 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3941 return;
3942
3943 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3944 (src_family == RADV_QUEUE_GENERAL ||
3945 dst_family == RADV_QUEUE_GENERAL))
3946 return;
3947 }
3948
3949 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3950 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3951
3952 if (image->surface.htile_size)
3953 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3954 dst_layout, src_queue_mask,
3955 dst_queue_mask, range,
3956 pending_clears);
3957
3958 if (image->cmask.size || image->fmask.size)
3959 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3960 dst_layout, src_queue_mask,
3961 dst_queue_mask, range);
3962
3963 if (image->surface.dcc_size)
3964 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3965 dst_layout, src_queue_mask,
3966 dst_queue_mask, range);
3967 }
3968
3969 void radv_CmdPipelineBarrier(
3970 VkCommandBuffer commandBuffer,
3971 VkPipelineStageFlags srcStageMask,
3972 VkPipelineStageFlags destStageMask,
3973 VkBool32 byRegion,
3974 uint32_t memoryBarrierCount,
3975 const VkMemoryBarrier* pMemoryBarriers,
3976 uint32_t bufferMemoryBarrierCount,
3977 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3978 uint32_t imageMemoryBarrierCount,
3979 const VkImageMemoryBarrier* pImageMemoryBarriers)
3980 {
3981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3982 enum radv_cmd_flush_bits src_flush_bits = 0;
3983 enum radv_cmd_flush_bits dst_flush_bits = 0;
3984
3985 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3986 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3987 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3988 NULL);
3989 }
3990
3991 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3992 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3993 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3994 NULL);
3995 }
3996
3997 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3998 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3999 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4000 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4001 image);
4002 }
4003
4004 radv_stage_flush(cmd_buffer, srcStageMask);
4005 cmd_buffer->state.flush_bits |= src_flush_bits;
4006
4007 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4008 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4009 radv_handle_image_transition(cmd_buffer, image,
4010 pImageMemoryBarriers[i].oldLayout,
4011 pImageMemoryBarriers[i].newLayout,
4012 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4013 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4014 &pImageMemoryBarriers[i].subresourceRange,
4015 0);
4016 }
4017
4018 cmd_buffer->state.flush_bits |= dst_flush_bits;
4019 }
4020
4021
4022 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4023 struct radv_event *event,
4024 VkPipelineStageFlags stageMask,
4025 unsigned value)
4026 {
4027 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4028 uint64_t va = radv_buffer_get_va(event->bo);
4029
4030 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4031
4032 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4033
4034 /* TODO: this is overkill. Probably should figure something out from
4035 * the stage mask. */
4036
4037 si_cs_emit_write_event_eop(cs,
4038 cmd_buffer->state.predicating,
4039 cmd_buffer->device->physical_device->rad_info.chip_class,
4040 radv_cmd_buffer_uses_mec(cmd_buffer),
4041 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4042 1, va, 2, value);
4043
4044 assert(cmd_buffer->cs->cdw <= cdw_max);
4045 }
4046
4047 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4048 VkEvent _event,
4049 VkPipelineStageFlags stageMask)
4050 {
4051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4052 RADV_FROM_HANDLE(radv_event, event, _event);
4053
4054 write_event(cmd_buffer, event, stageMask, 1);
4055 }
4056
4057 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4058 VkEvent _event,
4059 VkPipelineStageFlags stageMask)
4060 {
4061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4062 RADV_FROM_HANDLE(radv_event, event, _event);
4063
4064 write_event(cmd_buffer, event, stageMask, 0);
4065 }
4066
4067 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4068 uint32_t eventCount,
4069 const VkEvent* pEvents,
4070 VkPipelineStageFlags srcStageMask,
4071 VkPipelineStageFlags dstStageMask,
4072 uint32_t memoryBarrierCount,
4073 const VkMemoryBarrier* pMemoryBarriers,
4074 uint32_t bufferMemoryBarrierCount,
4075 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4076 uint32_t imageMemoryBarrierCount,
4077 const VkImageMemoryBarrier* pImageMemoryBarriers)
4078 {
4079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4080 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4081
4082 for (unsigned i = 0; i < eventCount; ++i) {
4083 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4084 uint64_t va = radv_buffer_get_va(event->bo);
4085
4086 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4087
4088 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4089
4090 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4091 assert(cmd_buffer->cs->cdw <= cdw_max);
4092 }
4093
4094
4095 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4096 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4097
4098 radv_handle_image_transition(cmd_buffer, image,
4099 pImageMemoryBarriers[i].oldLayout,
4100 pImageMemoryBarriers[i].newLayout,
4101 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4102 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4103 &pImageMemoryBarriers[i].subresourceRange,
4104 0);
4105 }
4106
4107 /* TODO: figure out how to do memory barriers without waiting */
4108 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4109 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4110 RADV_CMD_FLAG_INV_VMEM_L1 |
4111 RADV_CMD_FLAG_INV_SMEM_L1;
4112 }