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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 static uint32_t
398 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 static struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static void
535 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline,
537 struct radv_shader_variant *shader,
538 struct ac_vs_output_info *outinfo)
539 {
540 struct radeon_winsys *ws = cmd_buffer->device->ws;
541 uint64_t va = ws->buffer_get_va(shader->bo);
542 unsigned export_count;
543
544 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
545 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
546
547 export_count = MAX2(1, outinfo->param_exports);
548 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
549 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
550
551 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
552 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
553 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
554 V_02870C_SPI_SHADER_4COMP :
555 V_02870C_SPI_SHADER_NONE) |
556 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
557 V_02870C_SPI_SHADER_4COMP :
558 V_02870C_SPI_SHADER_NONE) |
559 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
560 V_02870C_SPI_SHADER_4COMP :
561 V_02870C_SPI_SHADER_NONE));
562
563
564 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
565 radeon_emit(cmd_buffer->cs, va >> 8);
566 radeon_emit(cmd_buffer->cs, va >> 40);
567 radeon_emit(cmd_buffer->cs, shader->rsrc1);
568 radeon_emit(cmd_buffer->cs, shader->rsrc2);
569
570 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
571 S_028818_VTX_W0_FMT(1) |
572 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
573 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
574 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
575
576
577 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
578 pipeline->graphics.pa_cl_vs_out_cntl);
579
580 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
581 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
582 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
583 }
584
585 static void
586 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_shader_variant *shader,
588 struct ac_es_output_info *outinfo)
589 {
590 struct radeon_winsys *ws = cmd_buffer->device->ws;
591 uint64_t va = ws->buffer_get_va(shader->bo);
592
593 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
594 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
595
596 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 outinfo->esgs_itemsize / 4);
598 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
599 radeon_emit(cmd_buffer->cs, va >> 8);
600 radeon_emit(cmd_buffer->cs, va >> 40);
601 radeon_emit(cmd_buffer->cs, shader->rsrc1);
602 radeon_emit(cmd_buffer->cs, shader->rsrc2);
603 }
604
605 static void
606 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_shader_variant *shader)
608 {
609 struct radeon_winsys *ws = cmd_buffer->device->ws;
610 uint64_t va = ws->buffer_get_va(shader->bo);
611 uint32_t rsrc2 = shader->rsrc2;
612
613 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
614 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
615
616 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
617 radeon_emit(cmd_buffer->cs, va >> 8);
618 radeon_emit(cmd_buffer->cs, va >> 40);
619
620 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
621 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
622 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
623 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
624
625 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
626 radeon_emit(cmd_buffer->cs, shader->rsrc1);
627 radeon_emit(cmd_buffer->cs, rsrc2);
628 }
629
630 static void
631 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_shader_variant *shader)
633 {
634 struct radeon_winsys *ws = cmd_buffer->device->ws;
635 uint64_t va = ws->buffer_get_va(shader->bo);
636
637 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
638 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
639
640 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
641 radeon_emit(cmd_buffer->cs, va >> 8);
642 radeon_emit(cmd_buffer->cs, va >> 40);
643 radeon_emit(cmd_buffer->cs, shader->rsrc1);
644 radeon_emit(cmd_buffer->cs, shader->rsrc2);
645 }
646
647 static void
648 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 struct radv_shader_variant *vs;
652
653 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
654
655 vs = pipeline->shaders[MESA_SHADER_VERTEX];
656
657 if (vs->info.vs.as_ls)
658 radv_emit_hw_ls(cmd_buffer, vs);
659 else if (vs->info.vs.as_es)
660 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
661 else
662 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
663
664 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
665 }
666
667
668 static void
669 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_pipeline *pipeline)
671 {
672 if (!radv_pipeline_has_tess(pipeline))
673 return;
674
675 struct radv_shader_variant *tes, *tcs;
676
677 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
678 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
679
680 if (tes->info.tes.as_es)
681 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
682 else
683 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
684
685 radv_emit_hw_hs(cmd_buffer, tcs);
686
687 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
688 pipeline->graphics.tess.tf_param);
689
690 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
691 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
692 pipeline->graphics.tess.ls_hs_config);
693 else
694 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
695 pipeline->graphics.tess.ls_hs_config);
696
697 struct ac_userdata_info *loc;
698
699 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
700 if (loc->sgpr_idx != -1) {
701 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
702 assert(loc->num_sgprs == 4);
703 assert(!loc->indirect);
704 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
705 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
706 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
707 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
708 pipeline->graphics.tess.num_tcs_input_cp << 26);
709 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
710 }
711
712 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
713 if (loc->sgpr_idx != -1) {
714 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
715 assert(loc->num_sgprs == 1);
716 assert(!loc->indirect);
717
718 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
719 pipeline->graphics.tess.offchip_layout);
720 }
721
722 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
723 if (loc->sgpr_idx != -1) {
724 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
725 assert(loc->num_sgprs == 1);
726 assert(!loc->indirect);
727
728 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
729 pipeline->graphics.tess.tcs_in_layout);
730 }
731 }
732
733 static void
734 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
735 struct radv_pipeline *pipeline)
736 {
737 struct radeon_winsys *ws = cmd_buffer->device->ws;
738 struct radv_shader_variant *gs;
739 uint64_t va;
740
741 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
742
743 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
744 if (!gs)
745 return;
746
747 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
748
749 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
750 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
751 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
752 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
753
754 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
755
756 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
757
758 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
759 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
760 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
761 radeon_emit(cmd_buffer->cs, 0);
762 radeon_emit(cmd_buffer->cs, 0);
763 radeon_emit(cmd_buffer->cs, 0);
764
765 uint32_t gs_num_invocations = gs->info.gs.invocations;
766 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
767 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
768 S_028B90_ENABLE(gs_num_invocations > 0));
769
770 va = ws->buffer_get_va(gs->bo);
771 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
772 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
773 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
774 radeon_emit(cmd_buffer->cs, va >> 8);
775 radeon_emit(cmd_buffer->cs, va >> 40);
776 radeon_emit(cmd_buffer->cs, gs->rsrc1);
777 radeon_emit(cmd_buffer->cs, gs->rsrc2);
778
779 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
780
781 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
782 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
783 if (loc->sgpr_idx != -1) {
784 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
785 uint32_t num_entries = 64;
786 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
787
788 if (is_vi)
789 num_entries *= stride;
790
791 stride = S_008F04_STRIDE(stride);
792 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
793 radeon_emit(cmd_buffer->cs, stride);
794 radeon_emit(cmd_buffer->cs, num_entries);
795 }
796 }
797
798 static void
799 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
800 struct radv_pipeline *pipeline)
801 {
802 struct radeon_winsys *ws = cmd_buffer->device->ws;
803 struct radv_shader_variant *ps;
804 uint64_t va;
805 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
806 struct radv_blend_state *blend = &pipeline->graphics.blend;
807 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
808
809 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
810
811 va = ws->buffer_get_va(ps->bo);
812 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
813 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
814
815 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
816 radeon_emit(cmd_buffer->cs, va >> 8);
817 radeon_emit(cmd_buffer->cs, va >> 40);
818 radeon_emit(cmd_buffer->cs, ps->rsrc1);
819 radeon_emit(cmd_buffer->cs, ps->rsrc2);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
822 pipeline->graphics.db_shader_control);
823
824 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
825 ps->config.spi_ps_input_ena);
826
827 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
828 ps->config.spi_ps_input_addr);
829
830 if (ps->info.fs.force_persample)
831 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
832
833 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
834 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
835
836 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
837
838 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
839 pipeline->graphics.shader_z_format);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
842
843 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
844 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
845
846 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
847 /* optimise this? */
848 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
850 }
851
852 if (pipeline->graphics.ps_input_cntl_num) {
853 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
854 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
855 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
856 }
857 }
858 }
859
860 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
861 struct radv_pipeline *pipeline)
862 {
863 uint32_t vtx_reuse_depth = 30;
864 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
865 return;
866
867 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
868 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
869 vtx_reuse_depth = 14;
870 }
871 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
872 vtx_reuse_depth);
873 }
874
875 static void
876 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
877 struct radv_pipeline *pipeline)
878 {
879 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
880 return;
881
882 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
883 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
884 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
885 radv_update_multisample_state(cmd_buffer, pipeline);
886 radv_emit_vertex_shader(cmd_buffer, pipeline);
887 radv_emit_tess_shaders(cmd_buffer, pipeline);
888 radv_emit_geometry_shader(cmd_buffer, pipeline);
889 radv_emit_fragment_shader(cmd_buffer, pipeline);
890 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
891
892 cmd_buffer->scratch_size_needed =
893 MAX2(cmd_buffer->scratch_size_needed,
894 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
895
896 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
897 S_0286E8_WAVES(pipeline->max_waves) |
898 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
899
900 if (!cmd_buffer->state.emitted_pipeline ||
901 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
902 pipeline->graphics.can_use_guardband)
903 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
904
905 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
906
907 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
908 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
909 } else {
910 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
911 }
912 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
913
914 cmd_buffer->state.emitted_pipeline = pipeline;
915 }
916
917 static void
918 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
919 {
920 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
921 cmd_buffer->state.dynamic.viewport.viewports);
922 }
923
924 static void
925 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
926 {
927 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
928 si_write_scissors(cmd_buffer->cs, 0, count,
929 cmd_buffer->state.dynamic.scissor.scissors,
930 cmd_buffer->state.dynamic.viewport.viewports,
931 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
932 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
933 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
934 }
935
936 static void
937 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
938 int index,
939 struct radv_color_buffer_info *cb)
940 {
941 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
942
943 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
944 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
945 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
946 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
947 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
948 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
949 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
950 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
951 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
952 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
953 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
956
957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
958 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
959 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
960
961 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
962 cb->gfx9_epitch);
963 } else {
964 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
965 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
966 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
967 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
968 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
969 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
970 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
971 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
972 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
973 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
974 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
975 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
976
977 if (is_vi) { /* DCC BASE */
978 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
979 }
980 }
981 }
982
983 static void
984 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
985 struct radv_ds_buffer_info *ds,
986 struct radv_image *image,
987 VkImageLayout layout)
988 {
989 uint32_t db_z_info = ds->db_z_info;
990 uint32_t db_stencil_info = ds->db_stencil_info;
991
992 if (!radv_layout_has_htile(image, layout,
993 radv_image_queue_family_mask(image,
994 cmd_buffer->queue_family_index,
995 cmd_buffer->queue_family_index))) {
996 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
997 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
998 }
999
1000 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1001
1002 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1003 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1004 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1005 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1006 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1007
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1009 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1010 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1011 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1012 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1013 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1014 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1015 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1016 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1017 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1018 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1019
1020 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1021 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1022 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1023 } else {
1024 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1025
1026 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1027 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1028 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1029 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1030 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1031 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1032 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1033 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1034 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1035 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1036
1037 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1038 }
1039
1040 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1041 ds->pa_su_poly_offset_db_fmt_cntl);
1042 }
1043
1044 void
1045 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1046 struct radv_image *image,
1047 VkClearDepthStencilValue ds_clear_value,
1048 VkImageAspectFlags aspects)
1049 {
1050 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1051 va += image->offset + image->clear_value_offset;
1052 unsigned reg_offset = 0, reg_count = 0;
1053
1054 if (!image->surface.htile_size || !aspects)
1055 return;
1056
1057 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1058 ++reg_count;
1059 } else {
1060 ++reg_offset;
1061 va += 4;
1062 }
1063 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1064 ++reg_count;
1065
1066 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1067
1068 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1069 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1070 S_370_WR_CONFIRM(1) |
1071 S_370_ENGINE_SEL(V_370_PFP));
1072 radeon_emit(cmd_buffer->cs, va);
1073 radeon_emit(cmd_buffer->cs, va >> 32);
1074 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1075 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1076 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1077 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1078
1079 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1080 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1081 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1082 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1083 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1084 }
1085
1086 static void
1087 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1088 struct radv_image *image)
1089 {
1090 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1091 va += image->offset + image->clear_value_offset;
1092
1093 if (!image->surface.htile_size)
1094 return;
1095
1096 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1097
1098 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1099 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1100 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1101 COPY_DATA_COUNT_SEL);
1102 radeon_emit(cmd_buffer->cs, va);
1103 radeon_emit(cmd_buffer->cs, va >> 32);
1104 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1105 radeon_emit(cmd_buffer->cs, 0);
1106
1107 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1108 radeon_emit(cmd_buffer->cs, 0);
1109 }
1110
1111 void
1112 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1113 struct radv_image *image,
1114 int idx,
1115 uint32_t color_values[2])
1116 {
1117 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1118 va += image->offset + image->clear_value_offset;
1119
1120 if (!image->cmask.size && !image->surface.dcc_size)
1121 return;
1122
1123 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1124
1125 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1126 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1127 S_370_WR_CONFIRM(1) |
1128 S_370_ENGINE_SEL(V_370_PFP));
1129 radeon_emit(cmd_buffer->cs, va);
1130 radeon_emit(cmd_buffer->cs, va >> 32);
1131 radeon_emit(cmd_buffer->cs, color_values[0]);
1132 radeon_emit(cmd_buffer->cs, color_values[1]);
1133
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1135 radeon_emit(cmd_buffer->cs, color_values[0]);
1136 radeon_emit(cmd_buffer->cs, color_values[1]);
1137 }
1138
1139 static void
1140 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1141 struct radv_image *image,
1142 int idx)
1143 {
1144 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1145 va += image->offset + image->clear_value_offset;
1146
1147 if (!image->cmask.size && !image->surface.dcc_size)
1148 return;
1149
1150 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1151 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1152
1153 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1154 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1155 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1156 COPY_DATA_COUNT_SEL);
1157 radeon_emit(cmd_buffer->cs, va);
1158 radeon_emit(cmd_buffer->cs, va >> 32);
1159 radeon_emit(cmd_buffer->cs, reg >> 2);
1160 radeon_emit(cmd_buffer->cs, 0);
1161
1162 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1163 radeon_emit(cmd_buffer->cs, 0);
1164 }
1165
1166 void
1167 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1168 {
1169 int i;
1170 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1171 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1172
1173 for (i = 0; i < subpass->color_count; ++i) {
1174 int idx = subpass->color_attachments[i].attachment;
1175 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1176
1177 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1178
1179 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1180 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1181
1182 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1183 }
1184
1185 for (i = subpass->color_count; i < 8; i++)
1186 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1187 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1188
1189 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1190 int idx = subpass->depth_stencil_attachment.attachment;
1191 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1192 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1193 struct radv_image *image = att->attachment->image;
1194 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1195 uint32_t queue_mask = radv_image_queue_family_mask(image,
1196 cmd_buffer->queue_family_index,
1197 cmd_buffer->queue_family_index);
1198 /* We currently don't support writing decompressed HTILE */
1199 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1200 radv_layout_is_htile_compressed(image, layout, queue_mask));
1201
1202 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1203
1204 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1205 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1206 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1207 }
1208 radv_load_depth_clear_regs(cmd_buffer, image);
1209 } else {
1210 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1211 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1212 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1213 }
1214 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1215 S_028208_BR_X(framebuffer->width) |
1216 S_028208_BR_Y(framebuffer->height));
1217
1218 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1219 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1220 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1221 }
1222 }
1223
1224 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 uint32_t db_count_control;
1227
1228 if(!cmd_buffer->state.active_occlusion_queries) {
1229 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1230 db_count_control = 0;
1231 } else {
1232 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1233 }
1234 } else {
1235 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1236 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1237 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1238 S_028004_ZPASS_ENABLE(1) |
1239 S_028004_SLICE_EVEN_ENABLE(1) |
1240 S_028004_SLICE_ODD_ENABLE(1);
1241 } else {
1242 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1243 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1244 }
1245 }
1246
1247 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1248 }
1249
1250 static void
1251 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1252 {
1253 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1254
1255 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1256 return;
1257
1258 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1259 radv_emit_viewport(cmd_buffer);
1260
1261 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1262 radv_emit_scissor(cmd_buffer);
1263
1264 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1265 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1266 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1267 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1268 }
1269
1270 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1272 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1273 }
1274
1275 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1276 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1277 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1278 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1279 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1280 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1281 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1282 S_028430_STENCILOPVAL(1));
1283 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1284 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1285 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1286 S_028434_STENCILOPVAL_BF(1));
1287 }
1288
1289 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1290 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1291 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1292 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1293 }
1294
1295 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1296 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1297 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1298 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1299 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1300
1301 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1302 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1303 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1304 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1305 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1306 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1307 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1308 }
1309 }
1310
1311 cmd_buffer->state.dirty = 0;
1312 }
1313
1314 static void
1315 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1316 struct radv_pipeline *pipeline,
1317 int idx,
1318 uint64_t va,
1319 gl_shader_stage stage)
1320 {
1321 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1322 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1323
1324 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1325 return;
1326
1327 assert(!desc_set_loc->indirect);
1328 assert(desc_set_loc->num_sgprs == 2);
1329 radeon_set_sh_reg_seq(cmd_buffer->cs,
1330 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1331 radeon_emit(cmd_buffer->cs, va);
1332 radeon_emit(cmd_buffer->cs, va >> 32);
1333 }
1334
1335 static void
1336 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1337 VkShaderStageFlags stages,
1338 struct radv_descriptor_set *set,
1339 unsigned idx)
1340 {
1341 if (cmd_buffer->state.pipeline) {
1342 radv_foreach_stage(stage, stages) {
1343 if (cmd_buffer->state.pipeline->shaders[stage])
1344 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1345 idx, set->va,
1346 stage);
1347 }
1348 }
1349
1350 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1351 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1352 idx, set->va,
1353 MESA_SHADER_COMPUTE);
1354 }
1355
1356 static void
1357 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1358 {
1359 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1360 uint32_t *ptr = NULL;
1361 unsigned bo_offset;
1362
1363 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1364 &bo_offset,
1365 (void**) &ptr))
1366 return;
1367
1368 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1369 set->va += bo_offset;
1370
1371 memcpy(ptr, set->mapped_ptr, set->size);
1372 }
1373
1374 static void
1375 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1376 {
1377 uint32_t size = MAX_SETS * 2 * 4;
1378 uint32_t offset;
1379 void *ptr;
1380
1381 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1382 256, &offset, &ptr))
1383 return;
1384
1385 for (unsigned i = 0; i < MAX_SETS; i++) {
1386 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1387 uint64_t set_va = 0;
1388 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1389 if (set)
1390 set_va = set->va;
1391 uptr[0] = set_va & 0xffffffff;
1392 uptr[1] = set_va >> 32;
1393 }
1394
1395 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1396 va += offset;
1397
1398 if (cmd_buffer->state.pipeline) {
1399 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1400 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1401 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1402
1403 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1404 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1405 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1406
1407 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1408 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1409 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1410
1411 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1412 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1413 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1414
1415 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1416 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1417 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1418 }
1419
1420 if (cmd_buffer->state.compute_pipeline)
1421 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1422 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1423 }
1424
1425 static void
1426 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1427 VkShaderStageFlags stages)
1428 {
1429 unsigned i;
1430
1431 if (!cmd_buffer->state.descriptors_dirty)
1432 return;
1433
1434 if (cmd_buffer->state.push_descriptors_dirty)
1435 radv_flush_push_descriptors(cmd_buffer);
1436
1437 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1438 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1439 radv_flush_indirect_descriptor_sets(cmd_buffer);
1440 }
1441
1442 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1443 cmd_buffer->cs,
1444 MAX_SETS * MESA_SHADER_STAGES * 4);
1445
1446 for (i = 0; i < MAX_SETS; i++) {
1447 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1448 continue;
1449 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1450 if (!set)
1451 continue;
1452
1453 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1454 }
1455 cmd_buffer->state.descriptors_dirty = 0;
1456 cmd_buffer->state.push_descriptors_dirty = false;
1457 assert(cmd_buffer->cs->cdw <= cdw_max);
1458 }
1459
1460 static void
1461 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1462 struct radv_pipeline *pipeline,
1463 VkShaderStageFlags stages)
1464 {
1465 struct radv_pipeline_layout *layout = pipeline->layout;
1466 unsigned offset;
1467 void *ptr;
1468 uint64_t va;
1469
1470 stages &= cmd_buffer->push_constant_stages;
1471 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1472 return;
1473
1474 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1475 16 * layout->dynamic_offset_count,
1476 256, &offset, &ptr))
1477 return;
1478
1479 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1480 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1481 16 * layout->dynamic_offset_count);
1482
1483 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1484 va += offset;
1485
1486 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1487 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1488
1489 radv_foreach_stage(stage, stages) {
1490 if (pipeline->shaders[stage]) {
1491 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1492 AC_UD_PUSH_CONSTANTS, va);
1493 }
1494 }
1495
1496 cmd_buffer->push_constant_stages &= ~stages;
1497 assert(cmd_buffer->cs->cdw <= cdw_max);
1498 }
1499
1500 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1501 bool indexed_draw)
1502 {
1503 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1504
1505 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1506 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1507 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1508 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1509 primitive_reset_en);
1510 } else {
1511 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1512 primitive_reset_en);
1513 }
1514 }
1515
1516 if (primitive_reset_en) {
1517 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1518
1519 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1520 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1521 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1522 primitive_reset_index);
1523 }
1524 }
1525 }
1526
1527 static void
1528 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1529 bool indexed_draw, bool instanced_draw,
1530 bool indirect_draw,
1531 uint32_t draw_vertex_count)
1532 {
1533 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1534 struct radv_device *device = cmd_buffer->device;
1535 uint32_t ia_multi_vgt_param;
1536
1537 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1538 cmd_buffer->cs, 4096);
1539
1540 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1541 cmd_buffer->state.pipeline->num_vertex_attribs &&
1542 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1543 unsigned vb_offset;
1544 void *vb_ptr;
1545 uint32_t i = 0;
1546 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1547 uint64_t va;
1548
1549 /* allocate some descriptor state for vertex buffers */
1550 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1551 &vb_offset, &vb_ptr);
1552
1553 for (i = 0; i < num_attribs; i++) {
1554 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1555 uint32_t offset;
1556 int vb = cmd_buffer->state.pipeline->va_binding[i];
1557 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1558 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1559
1560 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1561 va = device->ws->buffer_get_va(buffer->bo);
1562
1563 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1564 va += offset + buffer->offset;
1565 desc[0] = va;
1566 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1567 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1568 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1569 else
1570 desc[2] = buffer->size - offset;
1571 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1572 }
1573
1574 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1575 va += vb_offset;
1576
1577 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1578 AC_UD_VS_VERTEX_BUFFERS, va);
1579 }
1580
1581 cmd_buffer->state.vb_dirty = 0;
1582 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1583 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1584
1585 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1586 radv_emit_framebuffer_state(cmd_buffer);
1587
1588 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1589 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1590 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1591 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1592 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1593 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1594 else
1595 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1596 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1597 }
1598
1599 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1600
1601 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1602
1603 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1604 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1605 VK_SHADER_STAGE_ALL_GRAPHICS);
1606
1607 assert(cmd_buffer->cs->cdw <= cdw_max);
1608
1609 si_emit_cache_flush(cmd_buffer);
1610 }
1611
1612 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1613 VkPipelineStageFlags src_stage_mask)
1614 {
1615 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1616 VK_PIPELINE_STAGE_TRANSFER_BIT |
1617 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1618 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1619 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1620 }
1621
1622 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1623 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1624 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1625 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1626 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1627 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1628 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1629 VK_PIPELINE_STAGE_TRANSFER_BIT |
1630 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1631 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1632 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1633 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1634 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1635 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1636 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1637 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1638 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1639 }
1640 }
1641
1642 static enum radv_cmd_flush_bits
1643 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1644 VkAccessFlags src_flags)
1645 {
1646 enum radv_cmd_flush_bits flush_bits = 0;
1647 uint32_t b;
1648 for_each_bit(b, src_flags) {
1649 switch ((VkAccessFlagBits)(1 << b)) {
1650 case VK_ACCESS_SHADER_WRITE_BIT:
1651 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1652 break;
1653 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1654 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1655 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1656 break;
1657 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1658 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1659 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1660 break;
1661 case VK_ACCESS_TRANSFER_WRITE_BIT:
1662 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1663 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1664 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1665 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1666 RADV_CMD_FLAG_INV_GLOBAL_L2;
1667 break;
1668 default:
1669 break;
1670 }
1671 }
1672 return flush_bits;
1673 }
1674
1675 static enum radv_cmd_flush_bits
1676 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1677 VkAccessFlags dst_flags,
1678 struct radv_image *image)
1679 {
1680 enum radv_cmd_flush_bits flush_bits = 0;
1681 uint32_t b;
1682 for_each_bit(b, dst_flags) {
1683 switch ((VkAccessFlagBits)(1 << b)) {
1684 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1685 case VK_ACCESS_INDEX_READ_BIT:
1686 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1687 break;
1688 case VK_ACCESS_UNIFORM_READ_BIT:
1689 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1690 break;
1691 case VK_ACCESS_SHADER_READ_BIT:
1692 case VK_ACCESS_TRANSFER_READ_BIT:
1693 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1694 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1695 RADV_CMD_FLAG_INV_GLOBAL_L2;
1696 break;
1697 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1698 /* TODO: change to image && when the image gets passed
1699 * through from the subpass. */
1700 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1701 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1702 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1703 break;
1704 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1705 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1706 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1707 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1708 break;
1709 default:
1710 break;
1711 }
1712 }
1713 return flush_bits;
1714 }
1715
1716 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1717 {
1718 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1719 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1720 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1721 NULL);
1722 }
1723
1724 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1725 VkAttachmentReference att)
1726 {
1727 unsigned idx = att.attachment;
1728 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1729 VkImageSubresourceRange range;
1730 range.aspectMask = 0;
1731 range.baseMipLevel = view->base_mip;
1732 range.levelCount = 1;
1733 range.baseArrayLayer = view->base_layer;
1734 range.layerCount = cmd_buffer->state.framebuffer->layers;
1735
1736 radv_handle_image_transition(cmd_buffer,
1737 view->image,
1738 cmd_buffer->state.attachments[idx].current_layout,
1739 att.layout, 0, 0, &range,
1740 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1741
1742 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1743
1744
1745 }
1746
1747 void
1748 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1749 const struct radv_subpass *subpass, bool transitions)
1750 {
1751 if (transitions) {
1752 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1753
1754 for (unsigned i = 0; i < subpass->color_count; ++i) {
1755 radv_handle_subpass_image_transition(cmd_buffer,
1756 subpass->color_attachments[i]);
1757 }
1758
1759 for (unsigned i = 0; i < subpass->input_count; ++i) {
1760 radv_handle_subpass_image_transition(cmd_buffer,
1761 subpass->input_attachments[i]);
1762 }
1763
1764 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1765 radv_handle_subpass_image_transition(cmd_buffer,
1766 subpass->depth_stencil_attachment);
1767 }
1768 }
1769
1770 cmd_buffer->state.subpass = subpass;
1771
1772 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1773 }
1774
1775 static void
1776 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1777 struct radv_render_pass *pass,
1778 const VkRenderPassBeginInfo *info)
1779 {
1780 struct radv_cmd_state *state = &cmd_buffer->state;
1781
1782 if (pass->attachment_count == 0) {
1783 state->attachments = NULL;
1784 return;
1785 }
1786
1787 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1788 pass->attachment_count *
1789 sizeof(state->attachments[0]),
1790 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1791 if (state->attachments == NULL) {
1792 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1793 abort();
1794 }
1795
1796 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1797 struct radv_render_pass_attachment *att = &pass->attachments[i];
1798 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1799 VkImageAspectFlags clear_aspects = 0;
1800
1801 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1802 /* color attachment */
1803 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1804 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1805 }
1806 } else {
1807 /* depthstencil attachment */
1808 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1809 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1810 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1811 }
1812 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1813 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1814 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1815 }
1816 }
1817
1818 state->attachments[i].pending_clear_aspects = clear_aspects;
1819 if (clear_aspects && info) {
1820 assert(info->clearValueCount > i);
1821 state->attachments[i].clear_value = info->pClearValues[i];
1822 }
1823
1824 state->attachments[i].current_layout = att->initial_layout;
1825 }
1826 }
1827
1828 VkResult radv_AllocateCommandBuffers(
1829 VkDevice _device,
1830 const VkCommandBufferAllocateInfo *pAllocateInfo,
1831 VkCommandBuffer *pCommandBuffers)
1832 {
1833 RADV_FROM_HANDLE(radv_device, device, _device);
1834 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1835
1836 VkResult result = VK_SUCCESS;
1837 uint32_t i;
1838
1839 memset(pCommandBuffers, 0,
1840 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1841
1842 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1843
1844 if (!list_empty(&pool->free_cmd_buffers)) {
1845 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1846
1847 list_del(&cmd_buffer->pool_link);
1848 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1849
1850 radv_reset_cmd_buffer(cmd_buffer);
1851 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1852 cmd_buffer->level = pAllocateInfo->level;
1853
1854 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1855 result = VK_SUCCESS;
1856 } else {
1857 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1858 &pCommandBuffers[i]);
1859 }
1860 if (result != VK_SUCCESS)
1861 break;
1862 }
1863
1864 if (result != VK_SUCCESS)
1865 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1866 i, pCommandBuffers);
1867
1868 return result;
1869 }
1870
1871 void radv_FreeCommandBuffers(
1872 VkDevice device,
1873 VkCommandPool commandPool,
1874 uint32_t commandBufferCount,
1875 const VkCommandBuffer *pCommandBuffers)
1876 {
1877 for (uint32_t i = 0; i < commandBufferCount; i++) {
1878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1879
1880 if (cmd_buffer) {
1881 if (cmd_buffer->pool) {
1882 list_del(&cmd_buffer->pool_link);
1883 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1884 } else
1885 radv_cmd_buffer_destroy(cmd_buffer);
1886
1887 }
1888 }
1889 }
1890
1891 VkResult radv_ResetCommandBuffer(
1892 VkCommandBuffer commandBuffer,
1893 VkCommandBufferResetFlags flags)
1894 {
1895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1896 radv_reset_cmd_buffer(cmd_buffer);
1897 return VK_SUCCESS;
1898 }
1899
1900 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1901 {
1902 struct radv_device *device = cmd_buffer->device;
1903 if (device->gfx_init) {
1904 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1905 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1906 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1907 radeon_emit(cmd_buffer->cs, va);
1908 radeon_emit(cmd_buffer->cs, va >> 32);
1909 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1910 } else
1911 si_init_config(cmd_buffer);
1912 }
1913
1914 VkResult radv_BeginCommandBuffer(
1915 VkCommandBuffer commandBuffer,
1916 const VkCommandBufferBeginInfo *pBeginInfo)
1917 {
1918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1919 radv_reset_cmd_buffer(cmd_buffer);
1920
1921 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1922 cmd_buffer->state.last_primitive_reset_en = -1;
1923
1924 /* setup initial configuration into command buffer */
1925 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1926 switch (cmd_buffer->queue_family_index) {
1927 case RADV_QUEUE_GENERAL:
1928 emit_gfx_buffer_state(cmd_buffer);
1929 radv_set_db_count_control(cmd_buffer);
1930 break;
1931 case RADV_QUEUE_COMPUTE:
1932 si_init_compute(cmd_buffer);
1933 break;
1934 case RADV_QUEUE_TRANSFER:
1935 default:
1936 break;
1937 }
1938 }
1939
1940 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1941 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1942 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1943
1944 struct radv_subpass *subpass =
1945 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1946
1947 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1948 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1949 }
1950
1951 radv_cmd_buffer_trace_emit(cmd_buffer);
1952 return VK_SUCCESS;
1953 }
1954
1955 void radv_CmdBindVertexBuffers(
1956 VkCommandBuffer commandBuffer,
1957 uint32_t firstBinding,
1958 uint32_t bindingCount,
1959 const VkBuffer* pBuffers,
1960 const VkDeviceSize* pOffsets)
1961 {
1962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1963 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1964
1965 /* We have to defer setting up vertex buffer since we need the buffer
1966 * stride from the pipeline. */
1967
1968 assert(firstBinding + bindingCount < MAX_VBS);
1969 for (uint32_t i = 0; i < bindingCount; i++) {
1970 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1971 vb[firstBinding + i].offset = pOffsets[i];
1972 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1973 }
1974 }
1975
1976 void radv_CmdBindIndexBuffer(
1977 VkCommandBuffer commandBuffer,
1978 VkBuffer buffer,
1979 VkDeviceSize offset,
1980 VkIndexType indexType)
1981 {
1982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1983
1984 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1985 cmd_buffer->state.index_offset = offset;
1986 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1987 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1988 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1989 }
1990
1991
1992 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1993 struct radv_descriptor_set *set,
1994 unsigned idx)
1995 {
1996 struct radeon_winsys *ws = cmd_buffer->device->ws;
1997
1998 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1999
2000 cmd_buffer->state.descriptors[idx] = set;
2001 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2002 if (!set)
2003 return;
2004
2005 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2006 if (set->descriptors[j])
2007 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2008
2009 if(set->bo)
2010 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2011 }
2012
2013 void radv_CmdBindDescriptorSets(
2014 VkCommandBuffer commandBuffer,
2015 VkPipelineBindPoint pipelineBindPoint,
2016 VkPipelineLayout _layout,
2017 uint32_t firstSet,
2018 uint32_t descriptorSetCount,
2019 const VkDescriptorSet* pDescriptorSets,
2020 uint32_t dynamicOffsetCount,
2021 const uint32_t* pDynamicOffsets)
2022 {
2023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2024 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2025 unsigned dyn_idx = 0;
2026
2027 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2028 unsigned idx = i + firstSet;
2029 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2030 radv_bind_descriptor_set(cmd_buffer, set, idx);
2031
2032 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2033 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2034 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2035 assert(dyn_idx < dynamicOffsetCount);
2036
2037 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2038 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2039 dst[0] = va;
2040 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2041 dst[2] = range->size;
2042 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2043 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2044 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2045 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2046 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2047 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2048 cmd_buffer->push_constant_stages |=
2049 set->layout->dynamic_shader_stages;
2050 }
2051 }
2052 }
2053
2054 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2055 struct radv_descriptor_set *set,
2056 struct radv_descriptor_set_layout *layout)
2057 {
2058 set->size = layout->size;
2059 set->layout = layout;
2060
2061 if (cmd_buffer->push_descriptors.capacity < set->size) {
2062 size_t new_size = MAX2(set->size, 1024);
2063 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2064 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2065
2066 free(set->mapped_ptr);
2067 set->mapped_ptr = malloc(new_size);
2068
2069 if (!set->mapped_ptr) {
2070 cmd_buffer->push_descriptors.capacity = 0;
2071 cmd_buffer->record_fail = true;
2072 return false;
2073 }
2074
2075 cmd_buffer->push_descriptors.capacity = new_size;
2076 }
2077
2078 return true;
2079 }
2080
2081 void radv_meta_push_descriptor_set(
2082 struct radv_cmd_buffer* cmd_buffer,
2083 VkPipelineBindPoint pipelineBindPoint,
2084 VkPipelineLayout _layout,
2085 uint32_t set,
2086 uint32_t descriptorWriteCount,
2087 const VkWriteDescriptorSet* pDescriptorWrites)
2088 {
2089 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2090 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2091 unsigned bo_offset;
2092
2093 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2094
2095 push_set->size = layout->set[set].layout->size;
2096 push_set->layout = layout->set[set].layout;
2097
2098 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2099 &bo_offset,
2100 (void**) &push_set->mapped_ptr))
2101 return;
2102
2103 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2104 push_set->va += bo_offset;
2105
2106 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2107 radv_descriptor_set_to_handle(push_set),
2108 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2109
2110 cmd_buffer->state.descriptors[set] = push_set;
2111 cmd_buffer->state.descriptors_dirty |= (1u << set);
2112 }
2113
2114 void radv_CmdPushDescriptorSetKHR(
2115 VkCommandBuffer commandBuffer,
2116 VkPipelineBindPoint pipelineBindPoint,
2117 VkPipelineLayout _layout,
2118 uint32_t set,
2119 uint32_t descriptorWriteCount,
2120 const VkWriteDescriptorSet* pDescriptorWrites)
2121 {
2122 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2123 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2124 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2125
2126 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2127
2128 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2129 return;
2130
2131 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2132 radv_descriptor_set_to_handle(push_set),
2133 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2134
2135 cmd_buffer->state.descriptors[set] = push_set;
2136 cmd_buffer->state.descriptors_dirty |= (1u << set);
2137 cmd_buffer->state.push_descriptors_dirty = true;
2138 }
2139
2140 void radv_CmdPushDescriptorSetWithTemplateKHR(
2141 VkCommandBuffer commandBuffer,
2142 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2143 VkPipelineLayout _layout,
2144 uint32_t set,
2145 const void* pData)
2146 {
2147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2148 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2149 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2150
2151 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2152
2153 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2154 return;
2155
2156 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2157 descriptorUpdateTemplate, pData);
2158
2159 cmd_buffer->state.descriptors[set] = push_set;
2160 cmd_buffer->state.descriptors_dirty |= (1u << set);
2161 cmd_buffer->state.push_descriptors_dirty = true;
2162 }
2163
2164 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2165 VkPipelineLayout layout,
2166 VkShaderStageFlags stageFlags,
2167 uint32_t offset,
2168 uint32_t size,
2169 const void* pValues)
2170 {
2171 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2172 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2173 cmd_buffer->push_constant_stages |= stageFlags;
2174 }
2175
2176 VkResult radv_EndCommandBuffer(
2177 VkCommandBuffer commandBuffer)
2178 {
2179 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2180
2181 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2182 si_emit_cache_flush(cmd_buffer);
2183
2184 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2185 cmd_buffer->record_fail)
2186 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2187 return VK_SUCCESS;
2188 }
2189
2190 static void
2191 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2192 {
2193 struct radeon_winsys *ws = cmd_buffer->device->ws;
2194 struct radv_shader_variant *compute_shader;
2195 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2196 uint64_t va;
2197
2198 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2199 return;
2200
2201 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2202
2203 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2204 va = ws->buffer_get_va(compute_shader->bo);
2205
2206 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2207 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2208
2209 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2210 cmd_buffer->cs, 16);
2211
2212 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2213 radeon_emit(cmd_buffer->cs, va >> 8);
2214 radeon_emit(cmd_buffer->cs, va >> 40);
2215
2216 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2217 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2218 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2219
2220
2221 cmd_buffer->compute_scratch_size_needed =
2222 MAX2(cmd_buffer->compute_scratch_size_needed,
2223 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2224
2225 /* change these once we have scratch support */
2226 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2227 S_00B860_WAVES(pipeline->max_waves) |
2228 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2229
2230 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2231 radeon_emit(cmd_buffer->cs,
2232 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2233 radeon_emit(cmd_buffer->cs,
2234 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2235 radeon_emit(cmd_buffer->cs,
2236 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2237
2238 assert(cmd_buffer->cs->cdw <= cdw_max);
2239 }
2240
2241 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2242 {
2243 for (unsigned i = 0; i < MAX_SETS; i++) {
2244 if (cmd_buffer->state.descriptors[i])
2245 cmd_buffer->state.descriptors_dirty |= (1u << i);
2246 }
2247 }
2248
2249 void radv_CmdBindPipeline(
2250 VkCommandBuffer commandBuffer,
2251 VkPipelineBindPoint pipelineBindPoint,
2252 VkPipeline _pipeline)
2253 {
2254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2255 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2256
2257 radv_mark_descriptor_sets_dirty(cmd_buffer);
2258
2259 switch (pipelineBindPoint) {
2260 case VK_PIPELINE_BIND_POINT_COMPUTE:
2261 cmd_buffer->state.compute_pipeline = pipeline;
2262 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2263 break;
2264 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2265 cmd_buffer->state.pipeline = pipeline;
2266 if (!pipeline)
2267 break;
2268
2269 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2270 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2271
2272 /* Apply the dynamic state from the pipeline */
2273 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2274 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2275 &pipeline->dynamic_state,
2276 pipeline->dynamic_state_mask);
2277
2278 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2279 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2280 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2281 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2282
2283 if (radv_pipeline_has_tess(pipeline))
2284 cmd_buffer->tess_rings_needed = true;
2285
2286 if (radv_pipeline_has_gs(pipeline)) {
2287 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2288 AC_UD_SCRATCH_RING_OFFSETS);
2289 if (cmd_buffer->ring_offsets_idx == -1)
2290 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2291 else if (loc->sgpr_idx != -1)
2292 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2293 }
2294 break;
2295 default:
2296 assert(!"invalid bind point");
2297 break;
2298 }
2299 }
2300
2301 void radv_CmdSetViewport(
2302 VkCommandBuffer commandBuffer,
2303 uint32_t firstViewport,
2304 uint32_t viewportCount,
2305 const VkViewport* pViewports)
2306 {
2307 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2308
2309 const uint32_t total_count = firstViewport + viewportCount;
2310 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2311 cmd_buffer->state.dynamic.viewport.count = total_count;
2312
2313 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2314 pViewports, viewportCount * sizeof(*pViewports));
2315
2316 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2317 }
2318
2319 void radv_CmdSetScissor(
2320 VkCommandBuffer commandBuffer,
2321 uint32_t firstScissor,
2322 uint32_t scissorCount,
2323 const VkRect2D* pScissors)
2324 {
2325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2326
2327 const uint32_t total_count = firstScissor + scissorCount;
2328 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2329 cmd_buffer->state.dynamic.scissor.count = total_count;
2330
2331 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2332 pScissors, scissorCount * sizeof(*pScissors));
2333 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2334 }
2335
2336 void radv_CmdSetLineWidth(
2337 VkCommandBuffer commandBuffer,
2338 float lineWidth)
2339 {
2340 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2341 cmd_buffer->state.dynamic.line_width = lineWidth;
2342 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2343 }
2344
2345 void radv_CmdSetDepthBias(
2346 VkCommandBuffer commandBuffer,
2347 float depthBiasConstantFactor,
2348 float depthBiasClamp,
2349 float depthBiasSlopeFactor)
2350 {
2351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2352
2353 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2354 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2355 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2356
2357 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2358 }
2359
2360 void radv_CmdSetBlendConstants(
2361 VkCommandBuffer commandBuffer,
2362 const float blendConstants[4])
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365
2366 memcpy(cmd_buffer->state.dynamic.blend_constants,
2367 blendConstants, sizeof(float) * 4);
2368
2369 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2370 }
2371
2372 void radv_CmdSetDepthBounds(
2373 VkCommandBuffer commandBuffer,
2374 float minDepthBounds,
2375 float maxDepthBounds)
2376 {
2377 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2378
2379 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2380 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2381
2382 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2383 }
2384
2385 void radv_CmdSetStencilCompareMask(
2386 VkCommandBuffer commandBuffer,
2387 VkStencilFaceFlags faceMask,
2388 uint32_t compareMask)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391
2392 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2393 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2394 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2395 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2396
2397 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2398 }
2399
2400 void radv_CmdSetStencilWriteMask(
2401 VkCommandBuffer commandBuffer,
2402 VkStencilFaceFlags faceMask,
2403 uint32_t writeMask)
2404 {
2405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2406
2407 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2408 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2409 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2410 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2411
2412 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2413 }
2414
2415 void radv_CmdSetStencilReference(
2416 VkCommandBuffer commandBuffer,
2417 VkStencilFaceFlags faceMask,
2418 uint32_t reference)
2419 {
2420 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2421
2422 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2423 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2424 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2425 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2426
2427 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2428 }
2429
2430 void radv_CmdExecuteCommands(
2431 VkCommandBuffer commandBuffer,
2432 uint32_t commandBufferCount,
2433 const VkCommandBuffer* pCmdBuffers)
2434 {
2435 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2436
2437 /* Emit pending flushes on primary prior to executing secondary */
2438 si_emit_cache_flush(primary);
2439
2440 for (uint32_t i = 0; i < commandBufferCount; i++) {
2441 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2442
2443 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2444 secondary->scratch_size_needed);
2445 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2446 secondary->compute_scratch_size_needed);
2447
2448 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2449 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2450 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2451 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2452 if (secondary->tess_rings_needed)
2453 primary->tess_rings_needed = true;
2454 if (secondary->sample_positions_needed)
2455 primary->sample_positions_needed = true;
2456
2457 if (secondary->ring_offsets_idx != -1) {
2458 if (primary->ring_offsets_idx == -1)
2459 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2460 else
2461 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2462 }
2463 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2464 }
2465
2466 /* if we execute secondary we need to re-emit out pipelines */
2467 if (commandBufferCount) {
2468 primary->state.emitted_pipeline = NULL;
2469 primary->state.emitted_compute_pipeline = NULL;
2470 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2471 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2472 primary->state.last_primitive_reset_en = -1;
2473 primary->state.last_primitive_reset_index = 0;
2474 radv_mark_descriptor_sets_dirty(primary);
2475 }
2476 }
2477
2478 VkResult radv_CreateCommandPool(
2479 VkDevice _device,
2480 const VkCommandPoolCreateInfo* pCreateInfo,
2481 const VkAllocationCallbacks* pAllocator,
2482 VkCommandPool* pCmdPool)
2483 {
2484 RADV_FROM_HANDLE(radv_device, device, _device);
2485 struct radv_cmd_pool *pool;
2486
2487 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2488 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2489 if (pool == NULL)
2490 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2491
2492 if (pAllocator)
2493 pool->alloc = *pAllocator;
2494 else
2495 pool->alloc = device->alloc;
2496
2497 list_inithead(&pool->cmd_buffers);
2498 list_inithead(&pool->free_cmd_buffers);
2499
2500 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2501
2502 *pCmdPool = radv_cmd_pool_to_handle(pool);
2503
2504 return VK_SUCCESS;
2505
2506 }
2507
2508 void radv_DestroyCommandPool(
2509 VkDevice _device,
2510 VkCommandPool commandPool,
2511 const VkAllocationCallbacks* pAllocator)
2512 {
2513 RADV_FROM_HANDLE(radv_device, device, _device);
2514 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2515
2516 if (!pool)
2517 return;
2518
2519 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2520 &pool->cmd_buffers, pool_link) {
2521 radv_cmd_buffer_destroy(cmd_buffer);
2522 }
2523
2524 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2525 &pool->free_cmd_buffers, pool_link) {
2526 radv_cmd_buffer_destroy(cmd_buffer);
2527 }
2528
2529 vk_free2(&device->alloc, pAllocator, pool);
2530 }
2531
2532 VkResult radv_ResetCommandPool(
2533 VkDevice device,
2534 VkCommandPool commandPool,
2535 VkCommandPoolResetFlags flags)
2536 {
2537 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2538
2539 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2540 &pool->cmd_buffers, pool_link) {
2541 radv_reset_cmd_buffer(cmd_buffer);
2542 }
2543
2544 return VK_SUCCESS;
2545 }
2546
2547 void radv_TrimCommandPoolKHR(
2548 VkDevice device,
2549 VkCommandPool commandPool,
2550 VkCommandPoolTrimFlagsKHR flags)
2551 {
2552 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2553
2554 if (!pool)
2555 return;
2556
2557 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2558 &pool->free_cmd_buffers, pool_link) {
2559 radv_cmd_buffer_destroy(cmd_buffer);
2560 }
2561 }
2562
2563 void radv_CmdBeginRenderPass(
2564 VkCommandBuffer commandBuffer,
2565 const VkRenderPassBeginInfo* pRenderPassBegin,
2566 VkSubpassContents contents)
2567 {
2568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2570 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2571
2572 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2573 cmd_buffer->cs, 2048);
2574
2575 cmd_buffer->state.framebuffer = framebuffer;
2576 cmd_buffer->state.pass = pass;
2577 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2578 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2579
2580 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2581 assert(cmd_buffer->cs->cdw <= cdw_max);
2582
2583 radv_cmd_buffer_clear_subpass(cmd_buffer);
2584 }
2585
2586 void radv_CmdNextSubpass(
2587 VkCommandBuffer commandBuffer,
2588 VkSubpassContents contents)
2589 {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2591
2592 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2593
2594 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2595 2048);
2596
2597 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2598 radv_cmd_buffer_clear_subpass(cmd_buffer);
2599 }
2600
2601 void radv_CmdDraw(
2602 VkCommandBuffer commandBuffer,
2603 uint32_t vertexCount,
2604 uint32_t instanceCount,
2605 uint32_t firstVertex,
2606 uint32_t firstInstance)
2607 {
2608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2609
2610 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2611
2612 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2613
2614 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2615 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2616 if (loc->sgpr_idx != -1) {
2617 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2618 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2619 int vs_num = 2;
2620 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2621 vs_num = 3;
2622
2623 assert (loc->num_sgprs == vs_num);
2624 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2625 radeon_emit(cmd_buffer->cs, firstVertex);
2626 radeon_emit(cmd_buffer->cs, firstInstance);
2627 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2628 radeon_emit(cmd_buffer->cs, 0);
2629 }
2630 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2631 radeon_emit(cmd_buffer->cs, instanceCount);
2632
2633 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2634 radeon_emit(cmd_buffer->cs, vertexCount);
2635 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2636 S_0287F0_USE_OPAQUE(0));
2637
2638 assert(cmd_buffer->cs->cdw <= cdw_max);
2639
2640 radv_cmd_buffer_trace_emit(cmd_buffer);
2641 }
2642
2643 static
2644 uint32_t radv_get_max_index_count(struct radv_cmd_buffer *cmd_buffer) {
2645 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2646 return (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) >> index_size_shift;
2647 }
2648
2649 void radv_CmdDrawIndexed(
2650 VkCommandBuffer commandBuffer,
2651 uint32_t indexCount,
2652 uint32_t instanceCount,
2653 uint32_t firstIndex,
2654 int32_t vertexOffset,
2655 uint32_t firstInstance)
2656 {
2657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2658 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2659 uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
2660 uint64_t index_va;
2661
2662 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2663
2664 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2665
2666 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2667 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2668 2, cmd_buffer->state.index_type);
2669 } else {
2670 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2671 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2672 }
2673
2674 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2675 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2676 if (loc->sgpr_idx != -1) {
2677 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2678 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2679 int vs_num = 2;
2680 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2681 vs_num = 3;
2682
2683 assert (loc->num_sgprs == vs_num);
2684 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2685 radeon_emit(cmd_buffer->cs, vertexOffset);
2686 radeon_emit(cmd_buffer->cs, firstInstance);
2687 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2688 radeon_emit(cmd_buffer->cs, 0);
2689 }
2690 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2691 radeon_emit(cmd_buffer->cs, instanceCount);
2692
2693 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2694 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2695 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2696 radeon_emit(cmd_buffer->cs, index_max_size);
2697 radeon_emit(cmd_buffer->cs, index_va);
2698 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2699 radeon_emit(cmd_buffer->cs, indexCount);
2700 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2701
2702 assert(cmd_buffer->cs->cdw <= cdw_max);
2703 radv_cmd_buffer_trace_emit(cmd_buffer);
2704 }
2705
2706 static void
2707 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2708 VkBuffer _buffer,
2709 VkDeviceSize offset,
2710 VkBuffer _count_buffer,
2711 VkDeviceSize count_offset,
2712 uint32_t draw_count,
2713 uint32_t stride,
2714 bool indexed)
2715 {
2716 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2717 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2718 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2719 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2720 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2721 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2722 indirect_va += offset + buffer->offset;
2723 uint64_t count_va = 0;
2724
2725 if (count_buffer) {
2726 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2727 count_va += count_offset + count_buffer->offset;
2728 }
2729
2730 if (!draw_count)
2731 return;
2732
2733 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2734
2735 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2736 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2737 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2738 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2739 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2740 assert(loc->sgpr_idx != -1);
2741 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2742 radeon_emit(cs, 1);
2743 radeon_emit(cs, indirect_va);
2744 radeon_emit(cs, indirect_va >> 32);
2745
2746 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2747 PKT3_DRAW_INDIRECT_MULTI,
2748 8, false));
2749 radeon_emit(cs, 0);
2750 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2751 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2752 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2753 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2754 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2755 radeon_emit(cs, draw_count); /* count */
2756 radeon_emit(cs, count_va); /* count_addr */
2757 radeon_emit(cs, count_va >> 32);
2758 radeon_emit(cs, stride); /* stride */
2759 radeon_emit(cs, di_src_sel);
2760 radv_cmd_buffer_trace_emit(cmd_buffer);
2761 }
2762
2763 static void
2764 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2765 VkBuffer buffer,
2766 VkDeviceSize offset,
2767 VkBuffer countBuffer,
2768 VkDeviceSize countBufferOffset,
2769 uint32_t maxDrawCount,
2770 uint32_t stride)
2771 {
2772 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2773 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2774
2775 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2776 cmd_buffer->cs, 14);
2777
2778 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2779 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2780
2781 assert(cmd_buffer->cs->cdw <= cdw_max);
2782 }
2783
2784 static void
2785 radv_cmd_draw_indexed_indirect_count(
2786 VkCommandBuffer commandBuffer,
2787 VkBuffer buffer,
2788 VkDeviceSize offset,
2789 VkBuffer countBuffer,
2790 VkDeviceSize countBufferOffset,
2791 uint32_t maxDrawCount,
2792 uint32_t stride)
2793 {
2794 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2795 uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
2796 uint64_t index_va;
2797 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2798
2799 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2800 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2801
2802 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2803
2804 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2805 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2806
2807 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2808 radeon_emit(cmd_buffer->cs, index_va);
2809 radeon_emit(cmd_buffer->cs, index_va >> 32);
2810
2811 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2812 radeon_emit(cmd_buffer->cs, index_max_size);
2813
2814 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2815 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2816
2817 assert(cmd_buffer->cs->cdw <= cdw_max);
2818 }
2819
2820 void radv_CmdDrawIndirect(
2821 VkCommandBuffer commandBuffer,
2822 VkBuffer buffer,
2823 VkDeviceSize offset,
2824 uint32_t drawCount,
2825 uint32_t stride)
2826 {
2827 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2828 VK_NULL_HANDLE, 0, drawCount, stride);
2829 }
2830
2831 void radv_CmdDrawIndexedIndirect(
2832 VkCommandBuffer commandBuffer,
2833 VkBuffer buffer,
2834 VkDeviceSize offset,
2835 uint32_t drawCount,
2836 uint32_t stride)
2837 {
2838 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2839 VK_NULL_HANDLE, 0, drawCount, stride);
2840 }
2841
2842 void radv_CmdDrawIndirectCountAMD(
2843 VkCommandBuffer commandBuffer,
2844 VkBuffer buffer,
2845 VkDeviceSize offset,
2846 VkBuffer countBuffer,
2847 VkDeviceSize countBufferOffset,
2848 uint32_t maxDrawCount,
2849 uint32_t stride)
2850 {
2851 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2852 countBuffer, countBufferOffset,
2853 maxDrawCount, stride);
2854 }
2855
2856 void radv_CmdDrawIndexedIndirectCountAMD(
2857 VkCommandBuffer commandBuffer,
2858 VkBuffer buffer,
2859 VkDeviceSize offset,
2860 VkBuffer countBuffer,
2861 VkDeviceSize countBufferOffset,
2862 uint32_t maxDrawCount,
2863 uint32_t stride)
2864 {
2865 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2866 countBuffer, countBufferOffset,
2867 maxDrawCount, stride);
2868 }
2869
2870 static void
2871 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2872 {
2873 radv_emit_compute_pipeline(cmd_buffer);
2874 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2875 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2876 VK_SHADER_STAGE_COMPUTE_BIT);
2877 si_emit_cache_flush(cmd_buffer);
2878 }
2879
2880 void radv_CmdDispatch(
2881 VkCommandBuffer commandBuffer,
2882 uint32_t x,
2883 uint32_t y,
2884 uint32_t z)
2885 {
2886 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2887
2888 radv_flush_compute_state(cmd_buffer);
2889
2890 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2891
2892 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2893 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2894 if (loc->sgpr_idx != -1) {
2895 assert(!loc->indirect);
2896 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2897 assert(loc->num_sgprs == grid_used);
2898 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2899 radeon_emit(cmd_buffer->cs, x);
2900 if (grid_used > 1)
2901 radeon_emit(cmd_buffer->cs, y);
2902 if (grid_used > 2)
2903 radeon_emit(cmd_buffer->cs, z);
2904 }
2905
2906 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2907 PKT3_SHADER_TYPE_S(1));
2908 radeon_emit(cmd_buffer->cs, x);
2909 radeon_emit(cmd_buffer->cs, y);
2910 radeon_emit(cmd_buffer->cs, z);
2911 radeon_emit(cmd_buffer->cs, 1);
2912
2913 assert(cmd_buffer->cs->cdw <= cdw_max);
2914 radv_cmd_buffer_trace_emit(cmd_buffer);
2915 }
2916
2917 void radv_CmdDispatchIndirect(
2918 VkCommandBuffer commandBuffer,
2919 VkBuffer _buffer,
2920 VkDeviceSize offset)
2921 {
2922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2923 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2924 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2925 va += buffer->offset + offset;
2926
2927 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2928
2929 radv_flush_compute_state(cmd_buffer);
2930
2931 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2932 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2933 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2934 if (loc->sgpr_idx != -1) {
2935 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2936 for (unsigned i = 0; i < grid_used; ++i) {
2937 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2938 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2939 COPY_DATA_DST_SEL(COPY_DATA_REG));
2940 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2941 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2942 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2943 radeon_emit(cmd_buffer->cs, 0);
2944 }
2945 }
2946
2947 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2948 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2949 PKT3_SHADER_TYPE_S(1));
2950 radeon_emit(cmd_buffer->cs, va);
2951 radeon_emit(cmd_buffer->cs, va >> 32);
2952 radeon_emit(cmd_buffer->cs, 1);
2953 } else {
2954 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2955 PKT3_SHADER_TYPE_S(1));
2956 radeon_emit(cmd_buffer->cs, 1);
2957 radeon_emit(cmd_buffer->cs, va);
2958 radeon_emit(cmd_buffer->cs, va >> 32);
2959
2960 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2961 PKT3_SHADER_TYPE_S(1));
2962 radeon_emit(cmd_buffer->cs, 0);
2963 radeon_emit(cmd_buffer->cs, 1);
2964 }
2965
2966 assert(cmd_buffer->cs->cdw <= cdw_max);
2967 radv_cmd_buffer_trace_emit(cmd_buffer);
2968 }
2969
2970 void radv_unaligned_dispatch(
2971 struct radv_cmd_buffer *cmd_buffer,
2972 uint32_t x,
2973 uint32_t y,
2974 uint32_t z)
2975 {
2976 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2977 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2978 uint32_t blocks[3], remainder[3];
2979
2980 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2981 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2982 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2983
2984 /* If aligned, these should be an entire block size, not 0 */
2985 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2986 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2987 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2988
2989 radv_flush_compute_state(cmd_buffer);
2990
2991 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2992
2993 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2994 radeon_emit(cmd_buffer->cs,
2995 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2996 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2997 radeon_emit(cmd_buffer->cs,
2998 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2999 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3000 radeon_emit(cmd_buffer->cs,
3001 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3002 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3003
3004 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3005 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3006 if (loc->sgpr_idx != -1) {
3007 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3008 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3009 radeon_emit(cmd_buffer->cs, blocks[0]);
3010 if (grid_used > 1)
3011 radeon_emit(cmd_buffer->cs, blocks[1]);
3012 if (grid_used > 2)
3013 radeon_emit(cmd_buffer->cs, blocks[2]);
3014 }
3015 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3016 PKT3_SHADER_TYPE_S(1));
3017 radeon_emit(cmd_buffer->cs, blocks[0]);
3018 radeon_emit(cmd_buffer->cs, blocks[1]);
3019 radeon_emit(cmd_buffer->cs, blocks[2]);
3020 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3021 S_00B800_PARTIAL_TG_EN(1));
3022
3023 assert(cmd_buffer->cs->cdw <= cdw_max);
3024 radv_cmd_buffer_trace_emit(cmd_buffer);
3025 }
3026
3027 void radv_CmdEndRenderPass(
3028 VkCommandBuffer commandBuffer)
3029 {
3030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3031
3032 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3033
3034 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3035
3036 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3037 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3038 radv_handle_subpass_image_transition(cmd_buffer,
3039 (VkAttachmentReference){i, layout});
3040 }
3041
3042 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3043
3044 cmd_buffer->state.pass = NULL;
3045 cmd_buffer->state.subpass = NULL;
3046 cmd_buffer->state.attachments = NULL;
3047 cmd_buffer->state.framebuffer = NULL;
3048 }
3049
3050 /*
3051 * For HTILE we have the following interesting clear words:
3052 * 0x0000030f: Uncompressed.
3053 * 0xfffffff0: Clear depth to 1.0
3054 * 0x00000000: Clear depth to 0.0
3055 */
3056 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3057 struct radv_image *image,
3058 const VkImageSubresourceRange *range,
3059 uint32_t clear_word)
3060 {
3061 assert(range->baseMipLevel == 0);
3062 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3063 unsigned layer_count = radv_get_layerCount(image, range);
3064 uint64_t size = image->surface.htile_slice_size * layer_count;
3065 uint64_t offset = image->offset + image->htile_offset +
3066 image->surface.htile_slice_size * range->baseArrayLayer;
3067
3068 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3069 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3070
3071 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3072
3073 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3074 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3075 RADV_CMD_FLAG_INV_VMEM_L1 |
3076 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3077 }
3078
3079 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3080 struct radv_image *image,
3081 VkImageLayout src_layout,
3082 VkImageLayout dst_layout,
3083 unsigned src_queue_mask,
3084 unsigned dst_queue_mask,
3085 const VkImageSubresourceRange *range,
3086 VkImageAspectFlags pending_clears)
3087 {
3088 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3089 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3090 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3091 cmd_buffer->state.render_area.extent.width == image->info.width &&
3092 cmd_buffer->state.render_area.extent.height == image->info.height) {
3093 /* The clear will initialize htile. */
3094 return;
3095 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3096 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3097 /* TODO: merge with the clear if applicable */
3098 radv_initialize_htile(cmd_buffer, image, range, 0);
3099 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3100 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3101 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3102 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3103 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3104 VkImageSubresourceRange local_range = *range;
3105 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3106 local_range.baseMipLevel = 0;
3107 local_range.levelCount = 1;
3108
3109 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3110 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3111
3112 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3113
3114 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3115 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3116 }
3117 }
3118
3119 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3120 struct radv_image *image, uint32_t value)
3121 {
3122 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3123 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3124
3125 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3126 image->cmask.size, value);
3127
3128 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3129 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3130 RADV_CMD_FLAG_INV_VMEM_L1 |
3131 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3132 }
3133
3134 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3135 struct radv_image *image,
3136 VkImageLayout src_layout,
3137 VkImageLayout dst_layout,
3138 unsigned src_queue_mask,
3139 unsigned dst_queue_mask,
3140 const VkImageSubresourceRange *range,
3141 VkImageAspectFlags pending_clears)
3142 {
3143 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3144 if (image->fmask.size)
3145 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3146 else
3147 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3148 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3149 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3150 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3151 }
3152 }
3153
3154 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3155 struct radv_image *image, uint32_t value)
3156 {
3157
3158 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3159 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3160
3161 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3162 image->surface.dcc_size, value);
3163
3164 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3165 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3166 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3167 RADV_CMD_FLAG_INV_VMEM_L1 |
3168 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3169 }
3170
3171 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3172 struct radv_image *image,
3173 VkImageLayout src_layout,
3174 VkImageLayout dst_layout,
3175 unsigned src_queue_mask,
3176 unsigned dst_queue_mask,
3177 const VkImageSubresourceRange *range,
3178 VkImageAspectFlags pending_clears)
3179 {
3180 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3181 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3182 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3183 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3184 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3185 }
3186 }
3187
3188 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3189 struct radv_image *image,
3190 VkImageLayout src_layout,
3191 VkImageLayout dst_layout,
3192 uint32_t src_family,
3193 uint32_t dst_family,
3194 const VkImageSubresourceRange *range,
3195 VkImageAspectFlags pending_clears)
3196 {
3197 if (image->exclusive && src_family != dst_family) {
3198 /* This is an acquire or a release operation and there will be
3199 * a corresponding release/acquire. Do the transition in the
3200 * most flexible queue. */
3201
3202 assert(src_family == cmd_buffer->queue_family_index ||
3203 dst_family == cmd_buffer->queue_family_index);
3204
3205 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3206 return;
3207
3208 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3209 (src_family == RADV_QUEUE_GENERAL ||
3210 dst_family == RADV_QUEUE_GENERAL))
3211 return;
3212 }
3213
3214 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3215 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3216
3217 if (image->surface.htile_size)
3218 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3219 dst_layout, src_queue_mask,
3220 dst_queue_mask, range,
3221 pending_clears);
3222
3223 if (image->cmask.size)
3224 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3225 dst_layout, src_queue_mask,
3226 dst_queue_mask, range,
3227 pending_clears);
3228
3229 if (image->surface.dcc_size)
3230 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3231 dst_layout, src_queue_mask,
3232 dst_queue_mask, range,
3233 pending_clears);
3234 }
3235
3236 void radv_CmdPipelineBarrier(
3237 VkCommandBuffer commandBuffer,
3238 VkPipelineStageFlags srcStageMask,
3239 VkPipelineStageFlags destStageMask,
3240 VkBool32 byRegion,
3241 uint32_t memoryBarrierCount,
3242 const VkMemoryBarrier* pMemoryBarriers,
3243 uint32_t bufferMemoryBarrierCount,
3244 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3245 uint32_t imageMemoryBarrierCount,
3246 const VkImageMemoryBarrier* pImageMemoryBarriers)
3247 {
3248 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3249 enum radv_cmd_flush_bits src_flush_bits = 0;
3250 enum radv_cmd_flush_bits dst_flush_bits = 0;
3251
3252 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3253 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3254 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3255 NULL);
3256 }
3257
3258 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3259 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3260 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3261 NULL);
3262 }
3263
3264 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3265 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3266 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3267 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3268 image);
3269 }
3270
3271 radv_stage_flush(cmd_buffer, srcStageMask);
3272 cmd_buffer->state.flush_bits |= src_flush_bits;
3273
3274 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3275 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3276 radv_handle_image_transition(cmd_buffer, image,
3277 pImageMemoryBarriers[i].oldLayout,
3278 pImageMemoryBarriers[i].newLayout,
3279 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3280 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3281 &pImageMemoryBarriers[i].subresourceRange,
3282 0);
3283 }
3284
3285 cmd_buffer->state.flush_bits |= dst_flush_bits;
3286 }
3287
3288
3289 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3290 struct radv_event *event,
3291 VkPipelineStageFlags stageMask,
3292 unsigned value)
3293 {
3294 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3295 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3296
3297 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3298
3299 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3300
3301 /* TODO: this is overkill. Probably should figure something out from
3302 * the stage mask. */
3303
3304 si_cs_emit_write_event_eop(cs,
3305 cmd_buffer->device->physical_device->rad_info.chip_class,
3306 false,
3307 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3308 1, va, 2, value);
3309
3310 assert(cmd_buffer->cs->cdw <= cdw_max);
3311 }
3312
3313 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3314 VkEvent _event,
3315 VkPipelineStageFlags stageMask)
3316 {
3317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3318 RADV_FROM_HANDLE(radv_event, event, _event);
3319
3320 write_event(cmd_buffer, event, stageMask, 1);
3321 }
3322
3323 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3324 VkEvent _event,
3325 VkPipelineStageFlags stageMask)
3326 {
3327 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3328 RADV_FROM_HANDLE(radv_event, event, _event);
3329
3330 write_event(cmd_buffer, event, stageMask, 0);
3331 }
3332
3333 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3334 uint32_t eventCount,
3335 const VkEvent* pEvents,
3336 VkPipelineStageFlags srcStageMask,
3337 VkPipelineStageFlags dstStageMask,
3338 uint32_t memoryBarrierCount,
3339 const VkMemoryBarrier* pMemoryBarriers,
3340 uint32_t bufferMemoryBarrierCount,
3341 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3342 uint32_t imageMemoryBarrierCount,
3343 const VkImageMemoryBarrier* pImageMemoryBarriers)
3344 {
3345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3346 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3347
3348 for (unsigned i = 0; i < eventCount; ++i) {
3349 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3350 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3351
3352 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3353
3354 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3355
3356 si_emit_wait_fence(cs, va, 1, 0xffffffff);
3357 assert(cmd_buffer->cs->cdw <= cdw_max);
3358 }
3359
3360
3361 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3362 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3363
3364 radv_handle_image_transition(cmd_buffer, image,
3365 pImageMemoryBarriers[i].oldLayout,
3366 pImageMemoryBarriers[i].newLayout,
3367 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3368 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3369 &pImageMemoryBarriers[i].subresourceRange,
3370 0);
3371 }
3372
3373 /* TODO: figure out how to do memory barriers without waiting */
3374 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3375 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3376 RADV_CMD_FLAG_INV_VMEM_L1 |
3377 RADV_CMD_FLAG_INV_SMEM_L1;
3378 }