2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
83 const struct radv_dynamic_state
*src
)
85 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
86 uint32_t copy_mask
= src
->mask
;
87 uint32_t dest_mask
= 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest
->viewport
.count
= src
->viewport
.count
;
93 dest
->scissor
.count
= src
->scissor
.count
;
95 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
96 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
97 src
->viewport
.count
* sizeof(VkViewport
))) {
98 typed_memcpy(dest
->viewport
.viewports
,
99 src
->viewport
.viewports
,
100 src
->viewport
.count
);
101 dest_mask
|= 1 << VK_DYNAMIC_STATE_VIEWPORT
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
106 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
107 src
->scissor
.count
* sizeof(VkRect2D
))) {
108 typed_memcpy(dest
->scissor
.scissors
,
109 src
->scissor
.scissors
, src
->scissor
.count
);
110 dest_mask
|= 1 << VK_DYNAMIC_STATE_SCISSOR
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
115 if (dest
->line_width
!= src
->line_width
) {
116 dest
->line_width
= src
->line_width
;
117 dest_mask
|= 1 << VK_DYNAMIC_STATE_LINE_WIDTH
;
121 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
122 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
123 sizeof(src
->depth_bias
))) {
124 dest
->depth_bias
= src
->depth_bias
;
125 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS
;
129 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
130 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
131 sizeof(src
->blend_constants
))) {
132 typed_memcpy(dest
->blend_constants
,
133 src
->blend_constants
, 4);
134 dest_mask
|= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
;
138 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
139 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
140 sizeof(src
->depth_bounds
))) {
141 dest
->depth_bounds
= src
->depth_bounds
;
142 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
;
146 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
147 if (memcmp(&dest
->stencil_compare_mask
,
148 &src
->stencil_compare_mask
,
149 sizeof(src
->stencil_compare_mask
))) {
150 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
151 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
;
155 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
156 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
157 sizeof(src
->stencil_write_mask
))) {
158 dest
->stencil_write_mask
= src
->stencil_write_mask
;
159 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
;
163 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
164 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
165 sizeof(src
->stencil_reference
))) {
166 dest
->stencil_reference
= src
->stencil_reference
;
167 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
;
171 cmd_buffer
->state
.dirty
|= dest_mask
;
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
176 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
177 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
180 enum ring_type
radv_queue_family_to_ring(int f
) {
182 case RADV_QUEUE_GENERAL
:
184 case RADV_QUEUE_COMPUTE
:
186 case RADV_QUEUE_TRANSFER
:
189 unreachable("Unknown queue family");
193 static VkResult
radv_create_cmd_buffer(
194 struct radv_device
* device
,
195 struct radv_cmd_pool
* pool
,
196 VkCommandBufferLevel level
,
197 VkCommandBuffer
* pCommandBuffer
)
199 struct radv_cmd_buffer
*cmd_buffer
;
201 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
203 if (cmd_buffer
== NULL
)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
206 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
207 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
208 cmd_buffer
->device
= device
;
209 cmd_buffer
->pool
= pool
;
210 cmd_buffer
->level
= level
;
213 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
214 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
217 /* Init the pool_link so we can safefly call list_del when we destroy
220 list_inithead(&cmd_buffer
->pool_link
);
221 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
224 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
226 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
227 if (!cmd_buffer
->cs
) {
228 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
232 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
234 cmd_buffer
->upload
.offset
= 0;
235 cmd_buffer
->upload
.size
= 0;
236 list_inithead(&cmd_buffer
->upload
.list
);
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
244 list_del(&cmd_buffer
->pool_link
);
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
247 &cmd_buffer
->upload
.list
, list
) {
248 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
253 if (cmd_buffer
->upload
.upload_bo
)
254 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
255 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
256 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
257 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
261 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
264 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
267 &cmd_buffer
->upload
.list
, list
) {
268 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
273 cmd_buffer
->push_constant_stages
= 0;
274 cmd_buffer
->scratch_size_needed
= 0;
275 cmd_buffer
->compute_scratch_size_needed
= 0;
276 cmd_buffer
->esgs_ring_size_needed
= 0;
277 cmd_buffer
->gsvs_ring_size_needed
= 0;
278 cmd_buffer
->tess_rings_needed
= false;
279 cmd_buffer
->sample_positions_needed
= false;
281 if (cmd_buffer
->upload
.upload_bo
)
282 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
283 cmd_buffer
->upload
.upload_bo
, 8);
284 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->record_result
= VK_SUCCESS
;
288 cmd_buffer
->ring_offsets_idx
= -1;
290 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
292 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
293 &cmd_buffer
->gfx9_fence_offset
,
295 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
298 return cmd_buffer
->record_result
;
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
306 struct radeon_winsys_bo
*bo
;
307 struct radv_cmd_buffer_upload
*upload
;
308 struct radv_device
*device
= cmd_buffer
->device
;
310 new_size
= MAX2(min_needed
, 16 * 1024);
311 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
313 bo
= device
->ws
->buffer_create(device
->ws
,
316 RADEON_FLAG_CPU_ACCESS
|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
320 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
324 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
325 if (cmd_buffer
->upload
.upload_bo
) {
326 upload
= malloc(sizeof(*upload
));
329 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
330 device
->ws
->buffer_destroy(bo
);
334 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
335 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
338 cmd_buffer
->upload
.upload_bo
= bo
;
339 cmd_buffer
->upload
.size
= new_size
;
340 cmd_buffer
->upload
.offset
= 0;
341 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
343 if (!cmd_buffer
->upload
.map
) {
344 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
355 unsigned *out_offset
,
358 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
359 if (offset
+ size
> cmd_buffer
->upload
.size
) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
365 *out_offset
= offset
;
366 *ptr
= cmd_buffer
->upload
.map
+ offset
;
368 cmd_buffer
->upload
.offset
= offset
+ size
;
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
374 unsigned size
, unsigned alignment
,
375 const void *data
, unsigned *out_offset
)
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
380 out_offset
, (void **)&ptr
))
384 memcpy(ptr
, data
, size
);
390 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
391 unsigned count
, const uint32_t *data
)
393 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
394 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME
));
398 radeon_emit(cs
, va
>> 32);
399 radeon_emit_array(cs
, data
, count
);
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
404 struct radv_device
*device
= cmd_buffer
->device
;
405 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
408 if (!device
->trace_bo
)
411 va
= radv_buffer_get_va(device
->trace_bo
);
412 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
415 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
417 ++cmd_buffer
->state
.trace_id
;
418 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
419 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
420 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
421 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
427 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
428 enum radv_cmd_flush_bits flags
;
430 /* Force wait for graphics/compute engines to be idle. */
431 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
434 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
435 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
437 radv_cmd_buffer_uses_mec(cmd_buffer
),
441 radv_cmd_buffer_trace_emit(cmd_buffer
);
445 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
446 struct radv_pipeline
*pipeline
, enum ring_type ring
)
448 struct radv_device
*device
= cmd_buffer
->device
;
449 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
453 if (!device
->trace_bo
)
456 va
= radv_buffer_get_va(device
->trace_bo
);
466 assert(!"invalid ring type");
469 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
472 data
[0] = (uintptr_t)pipeline
;
473 data
[1] = (uintptr_t)pipeline
>> 32;
475 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
476 radv_emit_write_data_packet(cs
, va
, 2, data
);
479 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
480 struct radv_descriptor_set
*set
,
483 cmd_buffer
->descriptors
[idx
] = set
;
485 cmd_buffer
->state
.valid_descriptors
|= (1u << idx
);
487 cmd_buffer
->state
.valid_descriptors
&= ~(1u << idx
);
488 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
493 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
495 struct radv_device
*device
= cmd_buffer
->device
;
496 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
497 uint32_t data
[MAX_SETS
* 2] = {};
500 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
502 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
503 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
505 for_each_bit(i
, cmd_buffer
->state
.valid_descriptors
) {
506 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
507 data
[i
* 2] = (uintptr_t)set
;
508 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
511 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
512 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
516 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
517 struct radv_pipeline
*pipeline
)
519 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
520 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
522 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
523 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
525 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
527 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
528 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
530 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
531 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
532 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
533 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
538 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
539 struct radv_pipeline
*pipeline
)
541 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
542 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
543 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
545 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
546 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
549 struct ac_userdata_info
*
550 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
551 gl_shader_stage stage
,
554 if (stage
== MESA_SHADER_VERTEX
) {
555 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
556 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.user_sgprs_locs
.shader_data
[idx
];
557 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
558 return &pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.user_sgprs_locs
.shader_data
[idx
];
559 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
560 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
561 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
562 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
563 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.user_sgprs_locs
.shader_data
[idx
];
564 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
565 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
567 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
571 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
572 struct radv_pipeline
*pipeline
,
573 gl_shader_stage stage
,
574 int idx
, uint64_t va
)
576 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
577 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
578 if (loc
->sgpr_idx
== -1)
580 assert(loc
->num_sgprs
== 2);
581 assert(!loc
->indirect
);
582 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
583 radeon_emit(cmd_buffer
->cs
, va
);
584 radeon_emit(cmd_buffer
->cs
, va
>> 32);
588 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
589 struct radv_pipeline
*pipeline
)
591 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
592 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
593 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
595 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
596 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
597 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
599 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
600 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
602 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
605 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
606 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
607 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
609 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
611 /* GFX9: Flush DFSM when the AA mode changes. */
612 if (cmd_buffer
->device
->dfsm_allowed
) {
613 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
614 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
616 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
618 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
619 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
620 if (loc
->sgpr_idx
== -1)
622 assert(loc
->num_sgprs
== 1);
623 assert(!loc
->indirect
);
624 switch (num_samples
) {
642 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
643 cmd_buffer
->sample_positions_needed
= true;
648 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
649 struct radv_pipeline
*pipeline
)
651 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
653 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
654 raster
->pa_cl_clip_cntl
);
655 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
656 raster
->spi_interp_control
);
657 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
658 raster
->pa_su_vtx_cntl
);
659 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
660 raster
->pa_su_sc_mode_cntl
);
664 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
665 struct radv_shader_variant
*shader
)
667 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
668 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
674 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
676 ws
->cs_add_buffer(cs
, shader
->bo
, 8);
677 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
678 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
682 radv_emit_shaders_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
683 struct radv_pipeline
*pipeline
)
685 radv_emit_shader_prefetch(cmd_buffer
,
686 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
687 radv_emit_shader_prefetch(cmd_buffer
,
688 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
689 radv_emit_shader_prefetch(cmd_buffer
,
690 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
691 radv_emit_shader_prefetch(cmd_buffer
,
692 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
693 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
694 radv_emit_shader_prefetch(cmd_buffer
,
695 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
699 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
700 struct radv_pipeline
*pipeline
,
701 struct radv_shader_variant
*shader
,
702 struct ac_vs_output_info
*outinfo
)
704 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
705 unsigned export_count
;
707 export_count
= MAX2(1, outinfo
->param_exports
);
708 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
709 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
711 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
712 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
713 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
714 V_02870C_SPI_SHADER_4COMP
:
715 V_02870C_SPI_SHADER_NONE
) |
716 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
717 V_02870C_SPI_SHADER_4COMP
:
718 V_02870C_SPI_SHADER_NONE
) |
719 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
720 V_02870C_SPI_SHADER_4COMP
:
721 V_02870C_SPI_SHADER_NONE
));
724 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
725 radeon_emit(cmd_buffer
->cs
, va
>> 8);
726 radeon_emit(cmd_buffer
->cs
, va
>> 40);
727 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
728 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
730 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
731 S_028818_VTX_W0_FMT(1) |
732 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
733 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
734 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
737 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
738 pipeline
->graphics
.pa_cl_vs_out_cntl
);
740 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
741 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
742 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
746 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
747 struct radv_shader_variant
*shader
,
748 struct ac_es_output_info
*outinfo
)
750 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
752 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
753 outinfo
->esgs_itemsize
/ 4);
754 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
755 radeon_emit(cmd_buffer
->cs
, va
>> 8);
756 radeon_emit(cmd_buffer
->cs
, va
>> 40);
757 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
758 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
762 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
763 struct radv_shader_variant
*shader
)
765 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
766 uint32_t rsrc2
= shader
->rsrc2
;
768 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
769 radeon_emit(cmd_buffer
->cs
, va
>> 8);
770 radeon_emit(cmd_buffer
->cs
, va
>> 40);
772 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
773 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
774 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
775 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
777 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
778 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
779 radeon_emit(cmd_buffer
->cs
, rsrc2
);
783 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
784 struct radv_shader_variant
*shader
)
786 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
788 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
789 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
790 radeon_emit(cmd_buffer
->cs
, va
>> 8);
791 radeon_emit(cmd_buffer
->cs
, va
>> 40);
793 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
794 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
795 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
|
796 S_00B42C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
));
798 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
799 radeon_emit(cmd_buffer
->cs
, va
>> 8);
800 radeon_emit(cmd_buffer
->cs
, va
>> 40);
801 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
802 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
807 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
808 struct radv_pipeline
*pipeline
)
810 struct radv_shader_variant
*vs
;
812 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
814 /* Skip shaders merged into HS/GS */
815 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
819 if (vs
->info
.vs
.as_ls
)
820 radv_emit_hw_ls(cmd_buffer
, vs
);
821 else if (vs
->info
.vs
.as_es
)
822 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
824 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
829 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
830 struct radv_pipeline
*pipeline
)
832 if (!radv_pipeline_has_tess(pipeline
))
835 struct radv_shader_variant
*tes
, *tcs
;
837 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
838 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
841 if (tes
->info
.tes
.as_es
)
842 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
844 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
847 radv_emit_hw_hs(cmd_buffer
, tcs
);
849 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
850 pipeline
->graphics
.tess
.tf_param
);
852 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
853 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
854 pipeline
->graphics
.tess
.ls_hs_config
);
856 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
857 pipeline
->graphics
.tess
.ls_hs_config
);
859 struct ac_userdata_info
*loc
;
861 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
862 if (loc
->sgpr_idx
!= -1) {
863 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
864 assert(loc
->num_sgprs
== 4);
865 assert(!loc
->indirect
);
866 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
867 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
868 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
869 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
870 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
871 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
874 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
875 if (loc
->sgpr_idx
!= -1) {
876 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
877 assert(loc
->num_sgprs
== 1);
878 assert(!loc
->indirect
);
880 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
881 pipeline
->graphics
.tess
.offchip_layout
);
884 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
885 if (loc
->sgpr_idx
!= -1) {
886 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
887 assert(loc
->num_sgprs
== 1);
888 assert(!loc
->indirect
);
890 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
891 pipeline
->graphics
.tess
.tcs_in_layout
);
896 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
897 struct radv_pipeline
*pipeline
)
899 struct radv_shader_variant
*gs
;
902 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
904 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
908 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
910 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
911 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
912 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
913 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
915 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
917 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
919 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
920 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
921 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
922 radeon_emit(cmd_buffer
->cs
, 0);
923 radeon_emit(cmd_buffer
->cs
, 0);
924 radeon_emit(cmd_buffer
->cs
, 0);
926 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
927 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
928 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
929 S_028B90_ENABLE(gs_num_invocations
> 0));
931 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
933 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
934 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
935 radeon_emit(cmd_buffer
->cs
, va
>> 8);
936 radeon_emit(cmd_buffer
->cs
, va
>> 40);
938 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
939 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
940 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
|
941 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
943 radeon_set_context_reg(cmd_buffer
->cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
944 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
945 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
, pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
947 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
948 radeon_emit(cmd_buffer
->cs
, va
>> 8);
949 radeon_emit(cmd_buffer
->cs
, va
>> 40);
950 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
951 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
954 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
956 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
957 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
958 if (loc
->sgpr_idx
!= -1) {
959 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
960 uint32_t num_entries
= 64;
961 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
964 num_entries
*= stride
;
966 stride
= S_008F04_STRIDE(stride
);
967 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
968 radeon_emit(cmd_buffer
->cs
, stride
);
969 radeon_emit(cmd_buffer
->cs
, num_entries
);
974 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
975 struct radv_pipeline
*pipeline
)
977 struct radv_shader_variant
*ps
;
979 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
980 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
981 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
983 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
984 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
986 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
987 radeon_emit(cmd_buffer
->cs
, va
>> 8);
988 radeon_emit(cmd_buffer
->cs
, va
>> 40);
989 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
990 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
992 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
993 pipeline
->graphics
.db_shader_control
);
995 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
996 ps
->config
.spi_ps_input_ena
);
998 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
999 ps
->config
.spi_ps_input_addr
);
1001 if (ps
->info
.info
.ps
.force_persample
)
1002 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1004 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
1005 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
1007 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1009 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
1010 pipeline
->graphics
.shader_z_format
);
1012 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
1014 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
1015 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
1017 if (cmd_buffer
->device
->dfsm_allowed
) {
1018 /* optimise this? */
1019 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1020 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
1023 if (pipeline
->graphics
.ps_input_cntl_num
) {
1024 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
1025 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
1026 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
1032 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
1033 struct radv_pipeline
*pipeline
)
1035 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1037 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
1040 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1041 pipeline
->graphics
.vtx_reuse_depth
);
1045 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1047 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1049 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1052 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
1053 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
1054 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
1055 radv_update_multisample_state(cmd_buffer
, pipeline
);
1056 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
1057 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
1058 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
1059 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
1060 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
1062 cmd_buffer
->scratch_size_needed
=
1063 MAX2(cmd_buffer
->scratch_size_needed
,
1064 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1066 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
1067 S_0286E8_WAVES(pipeline
->max_waves
) |
1068 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
1070 if (!cmd_buffer
->state
.emitted_pipeline
||
1071 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1072 pipeline
->graphics
.can_use_guardband
)
1073 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1075 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1077 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1078 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
1080 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
1082 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
1084 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1086 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1088 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1092 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1094 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1095 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1099 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1101 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1103 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1104 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1105 si_emit_cache_flush(cmd_buffer
);
1107 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1108 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1109 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1110 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1111 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1112 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1116 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1118 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1120 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1121 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1125 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1127 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1129 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1130 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1134 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1136 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1138 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1139 R_028430_DB_STENCILREFMASK
, 2);
1140 radeon_emit(cmd_buffer
->cs
,
1141 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1142 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1143 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1144 S_028430_STENCILOPVAL(1));
1145 radeon_emit(cmd_buffer
->cs
,
1146 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1147 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1148 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1149 S_028434_STENCILOPVAL_BF(1));
1153 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1155 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1157 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1158 fui(d
->depth_bounds
.min
));
1159 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1160 fui(d
->depth_bounds
.max
));
1164 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1166 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1167 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1168 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1169 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1171 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1172 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1173 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1174 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1175 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1176 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1177 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1178 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1183 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1185 struct radv_color_buffer_info
*cb
)
1187 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1189 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1190 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1191 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1192 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1193 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1194 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1195 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1196 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1197 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1198 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1199 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1200 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1201 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1203 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1204 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1205 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1207 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1210 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1211 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1212 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1213 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1214 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1215 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1216 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1217 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1218 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1219 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1220 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1221 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1223 if (is_vi
) { /* DCC BASE */
1224 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1230 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1231 struct radv_ds_buffer_info
*ds
,
1232 struct radv_image
*image
,
1233 VkImageLayout layout
)
1235 uint32_t db_z_info
= ds
->db_z_info
;
1236 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1238 if (!radv_layout_has_htile(image
, layout
,
1239 radv_image_queue_family_mask(image
,
1240 cmd_buffer
->queue_family_index
,
1241 cmd_buffer
->queue_family_index
))) {
1242 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1243 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1246 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1247 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1250 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1251 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1252 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1253 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1254 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1256 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1257 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1258 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1259 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1260 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1261 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1262 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1263 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1264 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1265 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1266 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1268 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1269 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1270 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1272 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1274 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1275 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1276 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1277 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1278 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1279 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1280 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1281 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1282 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1283 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1287 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1288 ds
->pa_su_poly_offset_db_fmt_cntl
);
1292 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1293 struct radv_image
*image
,
1294 VkClearDepthStencilValue ds_clear_value
,
1295 VkImageAspectFlags aspects
)
1297 uint64_t va
= radv_buffer_get_va(image
->bo
);
1298 va
+= image
->offset
+ image
->clear_value_offset
;
1299 unsigned reg_offset
= 0, reg_count
= 0;
1301 if (!image
->surface
.htile_size
|| !aspects
)
1304 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1310 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1313 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1315 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1316 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1317 S_370_WR_CONFIRM(1) |
1318 S_370_ENGINE_SEL(V_370_PFP
));
1319 radeon_emit(cmd_buffer
->cs
, va
);
1320 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1321 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1322 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1323 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1324 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1326 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1327 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1328 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1329 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1330 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1334 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1335 struct radv_image
*image
)
1337 uint64_t va
= radv_buffer_get_va(image
->bo
);
1338 va
+= image
->offset
+ image
->clear_value_offset
;
1340 if (!image
->surface
.htile_size
)
1343 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1345 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1346 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1347 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1348 COPY_DATA_COUNT_SEL
);
1349 radeon_emit(cmd_buffer
->cs
, va
);
1350 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1351 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1352 radeon_emit(cmd_buffer
->cs
, 0);
1354 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1355 radeon_emit(cmd_buffer
->cs
, 0);
1359 *with DCC some colors don't require CMASK elimiation before being
1360 * used as a texture. This sets a predicate value to determine if the
1361 * cmask eliminate is required.
1364 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1365 struct radv_image
*image
,
1368 uint64_t pred_val
= value
;
1369 uint64_t va
= radv_buffer_get_va(image
->bo
);
1370 va
+= image
->offset
+ image
->dcc_pred_offset
;
1372 if (!image
->surface
.dcc_size
)
1375 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1377 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1378 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1379 S_370_WR_CONFIRM(1) |
1380 S_370_ENGINE_SEL(V_370_PFP
));
1381 radeon_emit(cmd_buffer
->cs
, va
);
1382 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1383 radeon_emit(cmd_buffer
->cs
, pred_val
);
1384 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1388 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1389 struct radv_image
*image
,
1391 uint32_t color_values
[2])
1393 uint64_t va
= radv_buffer_get_va(image
->bo
);
1394 va
+= image
->offset
+ image
->clear_value_offset
;
1396 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1399 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1401 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1402 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1403 S_370_WR_CONFIRM(1) |
1404 S_370_ENGINE_SEL(V_370_PFP
));
1405 radeon_emit(cmd_buffer
->cs
, va
);
1406 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1407 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1408 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1410 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1411 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1412 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1416 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1417 struct radv_image
*image
,
1420 uint64_t va
= radv_buffer_get_va(image
->bo
);
1421 va
+= image
->offset
+ image
->clear_value_offset
;
1423 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1426 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1427 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1429 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1430 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1431 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1432 COPY_DATA_COUNT_SEL
);
1433 radeon_emit(cmd_buffer
->cs
, va
);
1434 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1435 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1436 radeon_emit(cmd_buffer
->cs
, 0);
1438 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1439 radeon_emit(cmd_buffer
->cs
, 0);
1443 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1446 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1447 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1449 /* this may happen for inherited secondary recording */
1453 for (i
= 0; i
< 8; ++i
) {
1454 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1455 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1456 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1460 int idx
= subpass
->color_attachments
[i
].attachment
;
1461 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1463 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1465 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1466 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1468 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1471 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1472 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1473 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1474 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1475 struct radv_image
*image
= att
->attachment
->image
;
1476 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1477 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1478 cmd_buffer
->queue_family_index
,
1479 cmd_buffer
->queue_family_index
);
1480 /* We currently don't support writing decompressed HTILE */
1481 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1482 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1484 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1486 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1487 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1488 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1490 radv_load_depth_clear_regs(cmd_buffer
, image
);
1492 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1493 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1495 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1497 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1498 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1500 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1501 S_028208_BR_X(framebuffer
->width
) |
1502 S_028208_BR_Y(framebuffer
->height
));
1504 if (cmd_buffer
->device
->dfsm_allowed
) {
1505 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1506 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1509 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1513 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1515 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1517 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1518 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1519 2, cmd_buffer
->state
.index_type
);
1521 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1522 radeon_emit(cs
, cmd_buffer
->state
.index_type
);
1525 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1526 radeon_emit(cs
, cmd_buffer
->state
.index_va
);
1527 radeon_emit(cs
, cmd_buffer
->state
.index_va
>> 32);
1529 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1530 radeon_emit(cs
, cmd_buffer
->state
.max_index_count
);
1532 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1535 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1537 uint32_t db_count_control
;
1539 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1540 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1541 db_count_control
= 0;
1543 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1546 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1547 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1548 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1549 S_028004_ZPASS_ENABLE(1) |
1550 S_028004_SLICE_EVEN_ENABLE(1) |
1551 S_028004_SLICE_ODD_ENABLE(1);
1553 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1554 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1558 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1562 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1564 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1567 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1568 radv_emit_viewport(cmd_buffer
);
1570 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1571 radv_emit_scissor(cmd_buffer
);
1573 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1574 radv_emit_line_width(cmd_buffer
);
1576 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1577 radv_emit_blend_constants(cmd_buffer
);
1579 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1580 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1581 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1582 radv_emit_stencil(cmd_buffer
);
1584 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1585 radv_emit_depth_bounds(cmd_buffer
);
1587 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1588 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1589 radv_emit_depth_biais(cmd_buffer
);
1591 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
1595 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1596 struct radv_pipeline
*pipeline
,
1599 gl_shader_stage stage
)
1601 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1602 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1604 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1607 assert(!desc_set_loc
->indirect
);
1608 assert(desc_set_loc
->num_sgprs
== 2);
1609 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1610 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1611 radeon_emit(cmd_buffer
->cs
, va
);
1612 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1616 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1617 VkShaderStageFlags stages
,
1618 struct radv_descriptor_set
*set
,
1621 if (cmd_buffer
->state
.pipeline
) {
1622 radv_foreach_stage(stage
, stages
) {
1623 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1624 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1630 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1631 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1633 MESA_SHADER_COMPUTE
);
1637 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1639 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1642 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1647 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1648 set
->va
+= bo_offset
;
1652 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1654 uint32_t size
= MAX_SETS
* 2 * 4;
1658 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1659 256, &offset
, &ptr
))
1662 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1663 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1664 uint64_t set_va
= 0;
1665 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1666 if (cmd_buffer
->state
.valid_descriptors
& (1u << i
))
1668 uptr
[0] = set_va
& 0xffffffff;
1669 uptr
[1] = set_va
>> 32;
1672 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1675 if (cmd_buffer
->state
.pipeline
) {
1676 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1677 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1678 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1680 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1681 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1682 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1684 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1685 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1686 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1688 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1689 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1690 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1692 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1693 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1694 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1697 if (cmd_buffer
->state
.compute_pipeline
)
1698 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1699 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1703 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1704 VkShaderStageFlags stages
)
1708 if (!cmd_buffer
->state
.descriptors_dirty
)
1711 if (cmd_buffer
->state
.push_descriptors_dirty
)
1712 radv_flush_push_descriptors(cmd_buffer
);
1714 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1715 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1716 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1719 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1721 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1723 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1724 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1725 if (!(cmd_buffer
->state
.valid_descriptors
& (1u << i
)))
1728 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1730 cmd_buffer
->state
.descriptors_dirty
= 0;
1731 cmd_buffer
->state
.push_descriptors_dirty
= false;
1733 if (cmd_buffer
->device
->trace_bo
)
1734 radv_save_descriptors(cmd_buffer
);
1736 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1740 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1741 struct radv_pipeline
*pipeline
,
1742 VkShaderStageFlags stages
)
1744 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1749 stages
&= cmd_buffer
->push_constant_stages
;
1750 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1753 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1754 16 * layout
->dynamic_offset_count
,
1755 256, &offset
, &ptr
))
1758 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1759 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1760 16 * layout
->dynamic_offset_count
);
1762 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1765 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1766 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1768 radv_foreach_stage(stage
, stages
) {
1769 if (pipeline
->shaders
[stage
]) {
1770 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1771 AC_UD_PUSH_CONSTANTS
, va
);
1775 cmd_buffer
->push_constant_stages
&= ~stages
;
1776 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1780 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1782 struct radv_device
*device
= cmd_buffer
->device
;
1784 if ((pipeline_is_dirty
|| cmd_buffer
->state
.vb_dirty
) &&
1785 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1786 radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.has_vertex_buffers
) {
1787 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1791 uint32_t count
= velems
->count
;
1794 /* allocate some descriptor state for vertex buffers */
1795 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1796 &vb_offset
, &vb_ptr
))
1799 for (i
= 0; i
< count
; i
++) {
1800 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1802 int vb
= velems
->binding
[i
];
1803 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1804 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1806 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1807 va
= radv_buffer_get_va(buffer
->bo
);
1809 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1810 va
+= offset
+ buffer
->offset
;
1812 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1813 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1814 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1816 desc
[2] = buffer
->size
- offset
;
1817 desc
[3] = velems
->rsrc_word3
[i
];
1820 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1823 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1824 AC_UD_VS_VERTEX_BUFFERS
, va
);
1826 cmd_buffer
->state
.vb_dirty
= false;
1832 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1834 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
))
1837 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1838 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1839 VK_SHADER_STAGE_ALL_GRAPHICS
);
1845 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1846 bool instanced_draw
, bool indirect_draw
,
1847 uint32_t draw_vertex_count
)
1849 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1850 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1851 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1852 uint32_t ia_multi_vgt_param
;
1853 int32_t primitive_reset_en
;
1856 ia_multi_vgt_param
=
1857 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1858 indirect_draw
, draw_vertex_count
);
1860 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1861 if (info
->chip_class
>= GFX9
) {
1862 radeon_set_uconfig_reg_idx(cs
,
1863 R_030960_IA_MULTI_VGT_PARAM
,
1864 4, ia_multi_vgt_param
);
1865 } else if (info
->chip_class
>= CIK
) {
1866 radeon_set_context_reg_idx(cs
,
1867 R_028AA8_IA_MULTI_VGT_PARAM
,
1868 1, ia_multi_vgt_param
);
1870 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1871 ia_multi_vgt_param
);
1873 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1876 /* Primitive restart. */
1877 primitive_reset_en
=
1878 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1880 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1881 state
->last_primitive_reset_en
= primitive_reset_en
;
1882 if (info
->chip_class
>= GFX9
) {
1883 radeon_set_uconfig_reg(cs
,
1884 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1885 primitive_reset_en
);
1887 radeon_set_context_reg(cs
,
1888 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1889 primitive_reset_en
);
1893 if (primitive_reset_en
) {
1894 uint32_t primitive_reset_index
=
1895 state
->index_type
? 0xffffffffu
: 0xffffu
;
1897 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1898 radeon_set_context_reg(cs
,
1899 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1900 primitive_reset_index
);
1901 state
->last_primitive_reset_index
= primitive_reset_index
;
1906 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1907 VkPipelineStageFlags src_stage_mask
)
1909 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1910 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1911 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1912 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1913 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1916 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1917 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1918 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1919 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1920 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1921 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1922 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1923 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1924 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1925 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1926 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1927 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1928 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1929 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1930 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1931 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1935 static enum radv_cmd_flush_bits
1936 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1937 VkAccessFlags src_flags
)
1939 enum radv_cmd_flush_bits flush_bits
= 0;
1941 for_each_bit(b
, src_flags
) {
1942 switch ((VkAccessFlagBits
)(1 << b
)) {
1943 case VK_ACCESS_SHADER_WRITE_BIT
:
1944 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1946 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1947 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1948 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1950 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1951 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1952 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1954 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1955 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1957 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1958 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1959 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1968 static enum radv_cmd_flush_bits
1969 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1970 VkAccessFlags dst_flags
,
1971 struct radv_image
*image
)
1973 enum radv_cmd_flush_bits flush_bits
= 0;
1975 for_each_bit(b
, dst_flags
) {
1976 switch ((VkAccessFlagBits
)(1 << b
)) {
1977 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1978 case VK_ACCESS_INDEX_READ_BIT
:
1979 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1981 case VK_ACCESS_UNIFORM_READ_BIT
:
1982 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1984 case VK_ACCESS_SHADER_READ_BIT
:
1985 case VK_ACCESS_TRANSFER_READ_BIT
:
1986 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1987 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1988 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1990 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1991 /* TODO: change to image && when the image gets passed
1992 * through from the subpass. */
1993 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1994 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1995 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1997 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1998 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1999 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2000 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2009 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2011 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
2012 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2013 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2017 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2018 VkAttachmentReference att
)
2020 unsigned idx
= att
.attachment
;
2021 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2022 VkImageSubresourceRange range
;
2023 range
.aspectMask
= 0;
2024 range
.baseMipLevel
= view
->base_mip
;
2025 range
.levelCount
= 1;
2026 range
.baseArrayLayer
= view
->base_layer
;
2027 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2029 radv_handle_image_transition(cmd_buffer
,
2031 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2032 att
.layout
, 0, 0, &range
,
2033 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2035 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2041 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2042 const struct radv_subpass
*subpass
, bool transitions
)
2045 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2047 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2048 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2049 radv_handle_subpass_image_transition(cmd_buffer
,
2050 subpass
->color_attachments
[i
]);
2053 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2054 radv_handle_subpass_image_transition(cmd_buffer
,
2055 subpass
->input_attachments
[i
]);
2058 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2059 radv_handle_subpass_image_transition(cmd_buffer
,
2060 subpass
->depth_stencil_attachment
);
2064 cmd_buffer
->state
.subpass
= subpass
;
2066 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2070 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2071 struct radv_render_pass
*pass
,
2072 const VkRenderPassBeginInfo
*info
)
2074 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2076 if (pass
->attachment_count
== 0) {
2077 state
->attachments
= NULL
;
2081 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2082 pass
->attachment_count
*
2083 sizeof(state
->attachments
[0]),
2084 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2085 if (state
->attachments
== NULL
) {
2086 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2087 return cmd_buffer
->record_result
;
2090 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2091 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2092 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2093 VkImageAspectFlags clear_aspects
= 0;
2095 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2096 /* color attachment */
2097 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2098 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2101 /* depthstencil attachment */
2102 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2103 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2104 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2105 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2106 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2107 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2109 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2110 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2111 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2115 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2116 state
->attachments
[i
].cleared_views
= 0;
2117 if (clear_aspects
&& info
) {
2118 assert(info
->clearValueCount
> i
);
2119 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2122 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2128 VkResult
radv_AllocateCommandBuffers(
2130 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2131 VkCommandBuffer
*pCommandBuffers
)
2133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2134 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2136 VkResult result
= VK_SUCCESS
;
2139 memset(pCommandBuffers
, 0,
2140 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
2142 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2144 if (!list_empty(&pool
->free_cmd_buffers
)) {
2145 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2147 list_del(&cmd_buffer
->pool_link
);
2148 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2150 result
= radv_reset_cmd_buffer(cmd_buffer
);
2151 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2152 cmd_buffer
->level
= pAllocateInfo
->level
;
2154 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2156 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2157 &pCommandBuffers
[i
]);
2159 if (result
!= VK_SUCCESS
)
2163 if (result
!= VK_SUCCESS
)
2164 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2165 i
, pCommandBuffers
);
2170 void radv_FreeCommandBuffers(
2172 VkCommandPool commandPool
,
2173 uint32_t commandBufferCount
,
2174 const VkCommandBuffer
*pCommandBuffers
)
2176 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2177 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2180 if (cmd_buffer
->pool
) {
2181 list_del(&cmd_buffer
->pool_link
);
2182 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2184 radv_cmd_buffer_destroy(cmd_buffer
);
2190 VkResult
radv_ResetCommandBuffer(
2191 VkCommandBuffer commandBuffer
,
2192 VkCommandBufferResetFlags flags
)
2194 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2195 return radv_reset_cmd_buffer(cmd_buffer
);
2198 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2200 struct radv_device
*device
= cmd_buffer
->device
;
2201 if (device
->gfx_init
) {
2202 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2203 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
2204 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2205 radeon_emit(cmd_buffer
->cs
, va
);
2206 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2207 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2209 si_init_config(cmd_buffer
);
2212 VkResult
radv_BeginCommandBuffer(
2213 VkCommandBuffer commandBuffer
,
2214 const VkCommandBufferBeginInfo
*pBeginInfo
)
2216 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2219 result
= radv_reset_cmd_buffer(cmd_buffer
);
2220 if (result
!= VK_SUCCESS
)
2223 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2224 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2225 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2227 /* setup initial configuration into command buffer */
2228 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2229 switch (cmd_buffer
->queue_family_index
) {
2230 case RADV_QUEUE_GENERAL
:
2231 emit_gfx_buffer_state(cmd_buffer
);
2233 case RADV_QUEUE_COMPUTE
:
2234 si_init_compute(cmd_buffer
);
2236 case RADV_QUEUE_TRANSFER
:
2242 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2243 assert(pBeginInfo
->pInheritanceInfo
);
2244 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2245 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2247 struct radv_subpass
*subpass
=
2248 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2250 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2251 if (result
!= VK_SUCCESS
)
2254 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2257 radv_cmd_buffer_trace_emit(cmd_buffer
);
2261 void radv_CmdBindVertexBuffers(
2262 VkCommandBuffer commandBuffer
,
2263 uint32_t firstBinding
,
2264 uint32_t bindingCount
,
2265 const VkBuffer
* pBuffers
,
2266 const VkDeviceSize
* pOffsets
)
2268 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2269 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2270 bool changed
= false;
2272 /* We have to defer setting up vertex buffer since we need the buffer
2273 * stride from the pipeline. */
2275 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2276 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2277 uint32_t idx
= firstBinding
+ i
;
2280 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2281 vb
[idx
].offset
!= pOffsets
[i
])) {
2285 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2286 vb
[idx
].offset
= pOffsets
[i
];
2290 /* No state changes. */
2294 cmd_buffer
->state
.vb_dirty
= true;
2297 void radv_CmdBindIndexBuffer(
2298 VkCommandBuffer commandBuffer
,
2300 VkDeviceSize offset
,
2301 VkIndexType indexType
)
2303 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2304 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2306 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2307 cmd_buffer
->state
.index_offset
== offset
&&
2308 cmd_buffer
->state
.index_type
== indexType
) {
2309 /* No state changes. */
2313 cmd_buffer
->state
.index_buffer
= index_buffer
;
2314 cmd_buffer
->state
.index_offset
= offset
;
2315 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2316 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2317 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2319 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2320 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2321 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2322 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2327 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2328 struct radv_descriptor_set
*set
, unsigned idx
)
2330 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2332 radv_set_descriptor_set(cmd_buffer
, set
, idx
);
2336 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2338 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2339 if (set
->descriptors
[j
])
2340 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2343 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2346 void radv_CmdBindDescriptorSets(
2347 VkCommandBuffer commandBuffer
,
2348 VkPipelineBindPoint pipelineBindPoint
,
2349 VkPipelineLayout _layout
,
2351 uint32_t descriptorSetCount
,
2352 const VkDescriptorSet
* pDescriptorSets
,
2353 uint32_t dynamicOffsetCount
,
2354 const uint32_t* pDynamicOffsets
)
2356 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2357 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2358 unsigned dyn_idx
= 0;
2360 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2361 unsigned idx
= i
+ firstSet
;
2362 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2363 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2365 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2366 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2367 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2368 assert(dyn_idx
< dynamicOffsetCount
);
2370 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2371 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2373 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2374 dst
[2] = range
->size
;
2375 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2376 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2377 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2378 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2379 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2380 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2381 cmd_buffer
->push_constant_stages
|=
2382 set
->layout
->dynamic_shader_stages
;
2387 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2388 struct radv_descriptor_set
*set
,
2389 struct radv_descriptor_set_layout
*layout
)
2391 set
->size
= layout
->size
;
2392 set
->layout
= layout
;
2394 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2395 size_t new_size
= MAX2(set
->size
, 1024);
2396 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2397 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2399 free(set
->mapped_ptr
);
2400 set
->mapped_ptr
= malloc(new_size
);
2402 if (!set
->mapped_ptr
) {
2403 cmd_buffer
->push_descriptors
.capacity
= 0;
2404 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2408 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2414 void radv_meta_push_descriptor_set(
2415 struct radv_cmd_buffer
* cmd_buffer
,
2416 VkPipelineBindPoint pipelineBindPoint
,
2417 VkPipelineLayout _layout
,
2419 uint32_t descriptorWriteCount
,
2420 const VkWriteDescriptorSet
* pDescriptorWrites
)
2422 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2423 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2427 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2429 push_set
->size
= layout
->set
[set
].layout
->size
;
2430 push_set
->layout
= layout
->set
[set
].layout
;
2432 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2434 (void**) &push_set
->mapped_ptr
))
2437 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2438 push_set
->va
+= bo_offset
;
2440 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2441 radv_descriptor_set_to_handle(push_set
),
2442 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2444 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2447 void radv_CmdPushDescriptorSetKHR(
2448 VkCommandBuffer commandBuffer
,
2449 VkPipelineBindPoint pipelineBindPoint
,
2450 VkPipelineLayout _layout
,
2452 uint32_t descriptorWriteCount
,
2453 const VkWriteDescriptorSet
* pDescriptorWrites
)
2455 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2456 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2457 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2459 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2461 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2464 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2465 radv_descriptor_set_to_handle(push_set
),
2466 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2468 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2469 cmd_buffer
->state
.push_descriptors_dirty
= true;
2472 void radv_CmdPushDescriptorSetWithTemplateKHR(
2473 VkCommandBuffer commandBuffer
,
2474 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2475 VkPipelineLayout _layout
,
2479 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2480 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2481 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2483 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2485 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2488 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2489 descriptorUpdateTemplate
, pData
);
2491 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2492 cmd_buffer
->state
.push_descriptors_dirty
= true;
2495 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2496 VkPipelineLayout layout
,
2497 VkShaderStageFlags stageFlags
,
2500 const void* pValues
)
2502 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2503 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2504 cmd_buffer
->push_constant_stages
|= stageFlags
;
2507 VkResult
radv_EndCommandBuffer(
2508 VkCommandBuffer commandBuffer
)
2510 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2512 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2513 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2514 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2515 si_emit_cache_flush(cmd_buffer
);
2518 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2520 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2521 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2523 return cmd_buffer
->record_result
;
2527 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2529 struct radv_shader_variant
*compute_shader
;
2530 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2533 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2536 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2538 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2539 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2541 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2542 cmd_buffer
->cs
, 16);
2544 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2545 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2546 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2548 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2549 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2550 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2553 cmd_buffer
->compute_scratch_size_needed
=
2554 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2555 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2557 /* change these once we have scratch support */
2558 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2559 S_00B860_WAVES(pipeline
->max_waves
) |
2560 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2562 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2563 radeon_emit(cmd_buffer
->cs
,
2564 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2565 radeon_emit(cmd_buffer
->cs
,
2566 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2567 radeon_emit(cmd_buffer
->cs
,
2568 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2570 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2571 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2574 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2576 cmd_buffer
->state
.descriptors_dirty
|= cmd_buffer
->state
.valid_descriptors
;
2579 void radv_CmdBindPipeline(
2580 VkCommandBuffer commandBuffer
,
2581 VkPipelineBindPoint pipelineBindPoint
,
2582 VkPipeline _pipeline
)
2584 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2585 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2587 switch (pipelineBindPoint
) {
2588 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2589 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2591 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2593 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2594 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2596 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2597 if (cmd_buffer
->state
.pipeline
== pipeline
)
2599 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2601 cmd_buffer
->state
.pipeline
= pipeline
;
2605 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2606 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2608 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2610 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2611 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2612 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2613 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2615 if (radv_pipeline_has_tess(pipeline
))
2616 cmd_buffer
->tess_rings_needed
= true;
2618 if (radv_pipeline_has_gs(pipeline
)) {
2619 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2620 AC_UD_SCRATCH_RING_OFFSETS
);
2621 if (cmd_buffer
->ring_offsets_idx
== -1)
2622 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2623 else if (loc
->sgpr_idx
!= -1)
2624 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2628 assert(!"invalid bind point");
2633 void radv_CmdSetViewport(
2634 VkCommandBuffer commandBuffer
,
2635 uint32_t firstViewport
,
2636 uint32_t viewportCount
,
2637 const VkViewport
* pViewports
)
2639 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2640 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2642 assert(firstViewport
< MAX_VIEWPORTS
);
2643 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2645 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2646 pViewports
, viewportCount
* sizeof(*pViewports
));
2648 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2651 void radv_CmdSetScissor(
2652 VkCommandBuffer commandBuffer
,
2653 uint32_t firstScissor
,
2654 uint32_t scissorCount
,
2655 const VkRect2D
* pScissors
)
2657 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2658 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2660 assert(firstScissor
< MAX_SCISSORS
);
2661 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2663 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2664 pScissors
, scissorCount
* sizeof(*pScissors
));
2665 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2668 void radv_CmdSetLineWidth(
2669 VkCommandBuffer commandBuffer
,
2672 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2673 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2674 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2677 void radv_CmdSetDepthBias(
2678 VkCommandBuffer commandBuffer
,
2679 float depthBiasConstantFactor
,
2680 float depthBiasClamp
,
2681 float depthBiasSlopeFactor
)
2683 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2685 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2686 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2687 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2689 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2692 void radv_CmdSetBlendConstants(
2693 VkCommandBuffer commandBuffer
,
2694 const float blendConstants
[4])
2696 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2698 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2699 blendConstants
, sizeof(float) * 4);
2701 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2704 void radv_CmdSetDepthBounds(
2705 VkCommandBuffer commandBuffer
,
2706 float minDepthBounds
,
2707 float maxDepthBounds
)
2709 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2711 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2712 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2714 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2717 void radv_CmdSetStencilCompareMask(
2718 VkCommandBuffer commandBuffer
,
2719 VkStencilFaceFlags faceMask
,
2720 uint32_t compareMask
)
2722 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2724 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2725 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2726 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2727 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2729 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2732 void radv_CmdSetStencilWriteMask(
2733 VkCommandBuffer commandBuffer
,
2734 VkStencilFaceFlags faceMask
,
2737 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2739 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2740 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2741 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2742 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2744 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2747 void radv_CmdSetStencilReference(
2748 VkCommandBuffer commandBuffer
,
2749 VkStencilFaceFlags faceMask
,
2752 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2754 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2755 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2756 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2757 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2759 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2762 void radv_CmdExecuteCommands(
2763 VkCommandBuffer commandBuffer
,
2764 uint32_t commandBufferCount
,
2765 const VkCommandBuffer
* pCmdBuffers
)
2767 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2769 assert(commandBufferCount
> 0);
2771 /* Emit pending flushes on primary prior to executing secondary */
2772 si_emit_cache_flush(primary
);
2774 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2775 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2777 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2778 secondary
->scratch_size_needed
);
2779 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2780 secondary
->compute_scratch_size_needed
);
2782 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2783 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2784 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2785 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2786 if (secondary
->tess_rings_needed
)
2787 primary
->tess_rings_needed
= true;
2788 if (secondary
->sample_positions_needed
)
2789 primary
->sample_positions_needed
= true;
2791 if (secondary
->ring_offsets_idx
!= -1) {
2792 if (primary
->ring_offsets_idx
== -1)
2793 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2795 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2797 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2800 /* When the secondary command buffer is compute only we don't
2801 * need to re-emit the current graphics pipeline.
2803 if (secondary
->state
.emitted_pipeline
) {
2804 primary
->state
.emitted_pipeline
=
2805 secondary
->state
.emitted_pipeline
;
2808 /* When the secondary command buffer is graphics only we don't
2809 * need to re-emit the current compute pipeline.
2811 if (secondary
->state
.emitted_compute_pipeline
) {
2812 primary
->state
.emitted_compute_pipeline
=
2813 secondary
->state
.emitted_compute_pipeline
;
2816 /* Only re-emit the draw packets when needed. */
2817 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2818 primary
->state
.last_primitive_reset_en
=
2819 secondary
->state
.last_primitive_reset_en
;
2822 if (secondary
->state
.last_primitive_reset_index
) {
2823 primary
->state
.last_primitive_reset_index
=
2824 secondary
->state
.last_primitive_reset_index
;
2827 if (secondary
->state
.last_ia_multi_vgt_param
) {
2828 primary
->state
.last_ia_multi_vgt_param
=
2829 secondary
->state
.last_ia_multi_vgt_param
;
2833 /* After executing commands from secondary buffers we have to dirty
2836 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2837 RADV_CMD_DIRTY_INDEX_BUFFER
|
2838 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2839 radv_mark_descriptor_sets_dirty(primary
);
2842 VkResult
radv_CreateCommandPool(
2844 const VkCommandPoolCreateInfo
* pCreateInfo
,
2845 const VkAllocationCallbacks
* pAllocator
,
2846 VkCommandPool
* pCmdPool
)
2848 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2849 struct radv_cmd_pool
*pool
;
2851 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2852 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2854 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2857 pool
->alloc
= *pAllocator
;
2859 pool
->alloc
= device
->alloc
;
2861 list_inithead(&pool
->cmd_buffers
);
2862 list_inithead(&pool
->free_cmd_buffers
);
2864 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2866 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2872 void radv_DestroyCommandPool(
2874 VkCommandPool commandPool
,
2875 const VkAllocationCallbacks
* pAllocator
)
2877 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2878 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2883 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2884 &pool
->cmd_buffers
, pool_link
) {
2885 radv_cmd_buffer_destroy(cmd_buffer
);
2888 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2889 &pool
->free_cmd_buffers
, pool_link
) {
2890 radv_cmd_buffer_destroy(cmd_buffer
);
2893 vk_free2(&device
->alloc
, pAllocator
, pool
);
2896 VkResult
radv_ResetCommandPool(
2898 VkCommandPool commandPool
,
2899 VkCommandPoolResetFlags flags
)
2901 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2904 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2905 &pool
->cmd_buffers
, pool_link
) {
2906 result
= radv_reset_cmd_buffer(cmd_buffer
);
2907 if (result
!= VK_SUCCESS
)
2914 void radv_TrimCommandPoolKHR(
2916 VkCommandPool commandPool
,
2917 VkCommandPoolTrimFlagsKHR flags
)
2919 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2924 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2925 &pool
->free_cmd_buffers
, pool_link
) {
2926 radv_cmd_buffer_destroy(cmd_buffer
);
2930 void radv_CmdBeginRenderPass(
2931 VkCommandBuffer commandBuffer
,
2932 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2933 VkSubpassContents contents
)
2935 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2936 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2937 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2939 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2940 cmd_buffer
->cs
, 2048);
2941 MAYBE_UNUSED VkResult result
;
2943 cmd_buffer
->state
.framebuffer
= framebuffer
;
2944 cmd_buffer
->state
.pass
= pass
;
2945 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2947 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2948 if (result
!= VK_SUCCESS
)
2951 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2952 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2954 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2957 void radv_CmdNextSubpass(
2958 VkCommandBuffer commandBuffer
,
2959 VkSubpassContents contents
)
2961 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2963 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2965 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2968 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2969 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2972 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2974 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2975 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2976 if (!pipeline
->shaders
[stage
])
2978 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2979 if (loc
->sgpr_idx
== -1)
2981 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2982 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2985 if (pipeline
->gs_copy_shader
) {
2986 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2987 if (loc
->sgpr_idx
!= -1) {
2988 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2989 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2995 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2996 uint32_t vertex_count
)
2998 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2999 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3000 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3001 S_0287F0_USE_OPAQUE(0));
3005 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3007 uint32_t index_count
)
3009 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
3010 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3011 radeon_emit(cmd_buffer
->cs
, index_va
);
3012 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3013 radeon_emit(cmd_buffer
->cs
, index_count
);
3014 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3018 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3020 uint32_t draw_count
,
3024 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3025 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3026 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3027 bool draw_id_enable
= radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.needs_draw_id
;
3028 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3031 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3032 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3033 PKT3_DRAW_INDIRECT
, 3, false));
3035 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3036 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3037 radeon_emit(cs
, di_src_sel
);
3039 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3040 PKT3_DRAW_INDIRECT_MULTI
,
3043 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3044 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3045 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3046 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3047 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3048 radeon_emit(cs
, draw_count
); /* count */
3049 radeon_emit(cs
, count_va
); /* count_addr */
3050 radeon_emit(cs
, count_va
>> 32);
3051 radeon_emit(cs
, stride
); /* stride */
3052 radeon_emit(cs
, di_src_sel
);
3056 struct radv_draw_info
{
3058 * Number of vertices.
3063 * Index of the first vertex.
3065 int32_t vertex_offset
;
3068 * First instance id.
3070 uint32_t first_instance
;
3073 * Number of instances.
3075 uint32_t instance_count
;
3078 * First index (indexed draws only).
3080 uint32_t first_index
;
3083 * Whether it's an indexed draw.
3088 * Indirect draw parameters resource.
3090 struct radv_buffer
*indirect
;
3091 uint64_t indirect_offset
;
3095 * Draw count parameters resource.
3097 struct radv_buffer
*count_buffer
;
3098 uint64_t count_buffer_offset
;
3102 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3103 const struct radv_draw_info
*info
)
3105 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3106 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3107 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3109 if (info
->indirect
) {
3110 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3111 uint64_t count_va
= 0;
3113 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3115 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3117 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3119 radeon_emit(cs
, va
);
3120 radeon_emit(cs
, va
>> 32);
3122 if (info
->count_buffer
) {
3123 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3124 count_va
+= info
->count_buffer
->offset
+
3125 info
->count_buffer_offset
;
3127 ws
->cs_add_buffer(cs
, info
->count_buffer
->bo
, 8);
3130 if (!state
->subpass
->view_mask
) {
3131 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3138 for_each_bit(i
, state
->subpass
->view_mask
) {
3139 radv_emit_view_index(cmd_buffer
, i
);
3141 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3149 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3150 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3151 state
->pipeline
->graphics
.vtx_emit_num
);
3152 radeon_emit(cs
, info
->vertex_offset
);
3153 radeon_emit(cs
, info
->first_instance
);
3154 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3157 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, state
->predicating
));
3158 radeon_emit(cs
, info
->instance_count
);
3160 if (info
->indexed
) {
3161 int index_size
= state
->index_type
? 4 : 2;
3164 index_va
= state
->index_va
;
3165 index_va
+= info
->first_index
* index_size
;
3167 if (!state
->subpass
->view_mask
) {
3168 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3173 for_each_bit(i
, state
->subpass
->view_mask
) {
3174 radv_emit_view_index(cmd_buffer
, i
);
3176 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3182 if (!state
->subpass
->view_mask
) {
3183 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3186 for_each_bit(i
, state
->subpass
->view_mask
) {
3187 radv_emit_view_index(cmd_buffer
, i
);
3189 radv_cs_emit_draw_packet(cmd_buffer
,
3198 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3199 const struct radv_draw_info
*info
)
3201 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3202 radv_emit_graphics_pipeline(cmd_buffer
);
3204 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3205 radv_emit_framebuffer_state(cmd_buffer
);
3207 if (info
->indexed
) {
3208 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3209 radv_emit_index_buffer(cmd_buffer
);
3211 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3212 * so the state must be re-emitted before the next indexed
3215 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
3216 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3219 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3221 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3222 info
->instance_count
> 1, info
->indirect
,
3223 info
->indirect
? 0 : info
->count
);
3227 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3228 const struct radv_draw_info
*info
)
3230 bool pipeline_is_dirty
=
3231 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3232 cmd_buffer
->state
.pipeline
&&
3233 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3235 MAYBE_UNUSED
unsigned cdw_max
=
3236 radeon_check_space(cmd_buffer
->device
->ws
,
3237 cmd_buffer
->cs
, 4096);
3239 /* Use optimal packet order based on whether we need to sync the
3242 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3243 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3244 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3245 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3246 /* If we have to wait for idle, set all states first, so that
3247 * all SET packets are processed in parallel with previous draw
3248 * calls. Then upload descriptors, set shader pointers, and
3249 * draw, and prefetch at the end. This ensures that the time
3250 * the CUs are idle is very short. (there are only SET_SH
3251 * packets between the wait and the draw)
3253 radv_emit_all_graphics_states(cmd_buffer
, info
);
3254 si_emit_cache_flush(cmd_buffer
);
3255 /* <-- CUs are idle here --> */
3257 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3260 radv_emit_draw_packets(cmd_buffer
, info
);
3261 /* <-- CUs are busy here --> */
3263 /* Start prefetches after the draw has been started. Both will
3264 * run in parallel, but starting the draw first is more
3267 if (pipeline_is_dirty
) {
3268 radv_emit_shaders_prefetch(cmd_buffer
,
3269 cmd_buffer
->state
.pipeline
);
3272 /* If we don't wait for idle, start prefetches first, then set
3273 * states, and draw at the end.
3275 si_emit_cache_flush(cmd_buffer
);
3277 if (pipeline_is_dirty
) {
3278 radv_emit_shaders_prefetch(cmd_buffer
,
3279 cmd_buffer
->state
.pipeline
);
3282 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3285 radv_emit_all_graphics_states(cmd_buffer
, info
);
3286 radv_emit_draw_packets(cmd_buffer
, info
);
3289 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3290 radv_cmd_buffer_after_draw(cmd_buffer
);
3294 VkCommandBuffer commandBuffer
,
3295 uint32_t vertexCount
,
3296 uint32_t instanceCount
,
3297 uint32_t firstVertex
,
3298 uint32_t firstInstance
)
3300 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3301 struct radv_draw_info info
= {};
3303 info
.count
= vertexCount
;
3304 info
.instance_count
= instanceCount
;
3305 info
.first_instance
= firstInstance
;
3306 info
.vertex_offset
= firstVertex
;
3308 radv_draw(cmd_buffer
, &info
);
3311 void radv_CmdDrawIndexed(
3312 VkCommandBuffer commandBuffer
,
3313 uint32_t indexCount
,
3314 uint32_t instanceCount
,
3315 uint32_t firstIndex
,
3316 int32_t vertexOffset
,
3317 uint32_t firstInstance
)
3319 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3320 struct radv_draw_info info
= {};
3322 info
.indexed
= true;
3323 info
.count
= indexCount
;
3324 info
.instance_count
= instanceCount
;
3325 info
.first_index
= firstIndex
;
3326 info
.vertex_offset
= vertexOffset
;
3327 info
.first_instance
= firstInstance
;
3329 radv_draw(cmd_buffer
, &info
);
3332 void radv_CmdDrawIndirect(
3333 VkCommandBuffer commandBuffer
,
3335 VkDeviceSize offset
,
3339 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3340 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3341 struct radv_draw_info info
= {};
3343 info
.count
= drawCount
;
3344 info
.indirect
= buffer
;
3345 info
.indirect_offset
= offset
;
3346 info
.stride
= stride
;
3348 radv_draw(cmd_buffer
, &info
);
3351 void radv_CmdDrawIndexedIndirect(
3352 VkCommandBuffer commandBuffer
,
3354 VkDeviceSize offset
,
3358 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3359 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3360 struct radv_draw_info info
= {};
3362 info
.indexed
= true;
3363 info
.count
= drawCount
;
3364 info
.indirect
= buffer
;
3365 info
.indirect_offset
= offset
;
3366 info
.stride
= stride
;
3368 radv_draw(cmd_buffer
, &info
);
3371 void radv_CmdDrawIndirectCountAMD(
3372 VkCommandBuffer commandBuffer
,
3374 VkDeviceSize offset
,
3375 VkBuffer _countBuffer
,
3376 VkDeviceSize countBufferOffset
,
3377 uint32_t maxDrawCount
,
3380 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3381 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3382 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3383 struct radv_draw_info info
= {};
3385 info
.count
= maxDrawCount
;
3386 info
.indirect
= buffer
;
3387 info
.indirect_offset
= offset
;
3388 info
.count_buffer
= count_buffer
;
3389 info
.count_buffer_offset
= countBufferOffset
;
3390 info
.stride
= stride
;
3392 radv_draw(cmd_buffer
, &info
);
3395 void radv_CmdDrawIndexedIndirectCountAMD(
3396 VkCommandBuffer commandBuffer
,
3398 VkDeviceSize offset
,
3399 VkBuffer _countBuffer
,
3400 VkDeviceSize countBufferOffset
,
3401 uint32_t maxDrawCount
,
3404 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3405 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3406 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3407 struct radv_draw_info info
= {};
3409 info
.indexed
= true;
3410 info
.count
= maxDrawCount
;
3411 info
.indirect
= buffer
;
3412 info
.indirect_offset
= offset
;
3413 info
.count_buffer
= count_buffer
;
3414 info
.count_buffer_offset
= countBufferOffset
;
3415 info
.stride
= stride
;
3417 radv_draw(cmd_buffer
, &info
);
3420 struct radv_dispatch_info
{
3422 * Determine the layout of the grid (in block units) to be used.
3427 * Whether it's an unaligned compute dispatch.
3432 * Indirect compute parameters resource.
3434 struct radv_buffer
*indirect
;
3435 uint64_t indirect_offset
;
3439 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3440 const struct radv_dispatch_info
*info
)
3442 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3443 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3444 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3445 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3446 struct ac_userdata_info
*loc
;
3447 unsigned dispatch_initiator
;
3450 grid_used
= compute_shader
->info
.info
.cs
.grid_components_used
;
3452 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3453 AC_UD_CS_GRID_SIZE
);
3455 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3457 dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
3458 S_00B800_FORCE_START_AT_000(1);
3460 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3461 /* If the KMD allows it (there is a KMD hw register for it),
3462 * allow launching waves out-of-order.
3464 dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3467 if (info
->indirect
) {
3468 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3470 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3472 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3474 if (loc
->sgpr_idx
!= -1) {
3475 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3476 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3477 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3478 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3479 radeon_emit(cs
, (va
+ 4 * i
));
3480 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3481 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3482 + loc
->sgpr_idx
* 4) >> 2) + i
);
3487 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3488 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3489 PKT3_SHADER_TYPE_S(1));
3490 radeon_emit(cs
, va
);
3491 radeon_emit(cs
, va
>> 32);
3492 radeon_emit(cs
, dispatch_initiator
);
3494 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3495 PKT3_SHADER_TYPE_S(1));
3497 radeon_emit(cs
, va
);
3498 radeon_emit(cs
, va
>> 32);
3500 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3501 PKT3_SHADER_TYPE_S(1));
3503 radeon_emit(cs
, dispatch_initiator
);
3506 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3508 if (info
->unaligned
) {
3509 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3510 unsigned remainder
[3];
3512 /* If aligned, these should be an entire block size,
3515 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3516 align_u32_npot(blocks
[0], cs_block_size
[0]);
3517 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3518 align_u32_npot(blocks
[1], cs_block_size
[1]);
3519 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3520 align_u32_npot(blocks
[2], cs_block_size
[2]);
3522 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3523 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3524 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3526 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3528 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3529 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3531 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3532 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3534 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3535 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3537 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3540 if (loc
->sgpr_idx
!= -1) {
3541 assert(!loc
->indirect
);
3542 assert(loc
->num_sgprs
== grid_used
);
3544 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3545 loc
->sgpr_idx
* 4, grid_used
);
3546 radeon_emit(cs
, blocks
[0]);
3548 radeon_emit(cs
, blocks
[1]);
3550 radeon_emit(cs
, blocks
[2]);
3553 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3554 PKT3_SHADER_TYPE_S(1));
3555 radeon_emit(cs
, blocks
[0]);
3556 radeon_emit(cs
, blocks
[1]);
3557 radeon_emit(cs
, blocks
[2]);
3558 radeon_emit(cs
, dispatch_initiator
);
3561 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3565 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
3567 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3568 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3569 VK_SHADER_STAGE_COMPUTE_BIT
);
3573 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3574 const struct radv_dispatch_info
*info
)
3576 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3577 bool pipeline_is_dirty
= pipeline
&&
3578 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
3580 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3581 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3582 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3583 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3584 /* If we have to wait for idle, set all states first, so that
3585 * all SET packets are processed in parallel with previous draw
3586 * calls. Then upload descriptors, set shader pointers, and
3587 * dispatch, and prefetch at the end. This ensures that the
3588 * time the CUs are idle is very short. (there are only SET_SH
3589 * packets between the wait and the draw)
3591 radv_emit_compute_pipeline(cmd_buffer
);
3592 si_emit_cache_flush(cmd_buffer
);
3593 /* <-- CUs are idle here --> */
3595 radv_upload_compute_shader_descriptors(cmd_buffer
);
3597 radv_emit_dispatch_packets(cmd_buffer
, info
);
3598 /* <-- CUs are busy here --> */
3600 /* Start prefetches after the dispatch has been started. Both
3601 * will run in parallel, but starting the dispatch first is
3604 if (pipeline_is_dirty
) {
3605 radv_emit_shader_prefetch(cmd_buffer
,
3606 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3609 /* If we don't wait for idle, start prefetches first, then set
3610 * states, and dispatch at the end.
3612 si_emit_cache_flush(cmd_buffer
);
3614 if (pipeline_is_dirty
) {
3615 radv_emit_shader_prefetch(cmd_buffer
,
3616 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3619 radv_upload_compute_shader_descriptors(cmd_buffer
);
3621 radv_emit_compute_pipeline(cmd_buffer
);
3622 radv_emit_dispatch_packets(cmd_buffer
, info
);
3625 radv_cmd_buffer_after_draw(cmd_buffer
);
3628 void radv_CmdDispatch(
3629 VkCommandBuffer commandBuffer
,
3634 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3635 struct radv_dispatch_info info
= {};
3641 radv_dispatch(cmd_buffer
, &info
);
3644 void radv_CmdDispatchIndirect(
3645 VkCommandBuffer commandBuffer
,
3647 VkDeviceSize offset
)
3649 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3650 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3651 struct radv_dispatch_info info
= {};
3653 info
.indirect
= buffer
;
3654 info
.indirect_offset
= offset
;
3656 radv_dispatch(cmd_buffer
, &info
);
3659 void radv_unaligned_dispatch(
3660 struct radv_cmd_buffer
*cmd_buffer
,
3665 struct radv_dispatch_info info
= {};
3672 radv_dispatch(cmd_buffer
, &info
);
3675 void radv_CmdEndRenderPass(
3676 VkCommandBuffer commandBuffer
)
3678 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3680 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3682 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3684 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3685 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3686 radv_handle_subpass_image_transition(cmd_buffer
,
3687 (VkAttachmentReference
){i
, layout
});
3690 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3692 cmd_buffer
->state
.pass
= NULL
;
3693 cmd_buffer
->state
.subpass
= NULL
;
3694 cmd_buffer
->state
.attachments
= NULL
;
3695 cmd_buffer
->state
.framebuffer
= NULL
;
3699 * For HTILE we have the following interesting clear words:
3700 * 0x0000030f: Uncompressed.
3701 * 0xfffffff0: Clear depth to 1.0
3702 * 0x00000000: Clear depth to 0.0
3704 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3705 struct radv_image
*image
,
3706 const VkImageSubresourceRange
*range
,
3707 uint32_t clear_word
)
3709 assert(range
->baseMipLevel
== 0);
3710 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3711 unsigned layer_count
= radv_get_layerCount(image
, range
);
3712 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3713 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3714 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3715 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3717 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3718 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3720 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
3723 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3726 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3727 struct radv_image
*image
,
3728 VkImageLayout src_layout
,
3729 VkImageLayout dst_layout
,
3730 unsigned src_queue_mask
,
3731 unsigned dst_queue_mask
,
3732 const VkImageSubresourceRange
*range
,
3733 VkImageAspectFlags pending_clears
)
3735 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3736 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3737 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3738 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3739 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3740 /* The clear will initialize htile. */
3742 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3743 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3744 /* TODO: merge with the clear if applicable */
3745 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3746 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3747 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3748 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3749 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3750 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3751 VkImageSubresourceRange local_range
= *range
;
3752 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3753 local_range
.baseMipLevel
= 0;
3754 local_range
.levelCount
= 1;
3756 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3757 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3759 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3761 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3762 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3766 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3767 struct radv_image
*image
, uint32_t value
)
3769 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3771 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3772 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3774 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3775 image
->offset
+ image
->cmask
.offset
,
3776 image
->cmask
.size
, value
);
3778 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3781 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3782 struct radv_image
*image
,
3783 VkImageLayout src_layout
,
3784 VkImageLayout dst_layout
,
3785 unsigned src_queue_mask
,
3786 unsigned dst_queue_mask
,
3787 const VkImageSubresourceRange
*range
)
3789 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3790 if (image
->fmask
.size
)
3791 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3793 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3794 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3795 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3796 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3800 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3801 struct radv_image
*image
, uint32_t value
)
3803 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3805 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3806 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3808 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3809 image
->offset
+ image
->dcc_offset
,
3810 image
->surface
.dcc_size
, value
);
3812 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3813 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3816 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3817 struct radv_image
*image
,
3818 VkImageLayout src_layout
,
3819 VkImageLayout dst_layout
,
3820 unsigned src_queue_mask
,
3821 unsigned dst_queue_mask
,
3822 const VkImageSubresourceRange
*range
)
3824 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3825 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3826 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3827 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3828 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3832 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3833 struct radv_image
*image
,
3834 VkImageLayout src_layout
,
3835 VkImageLayout dst_layout
,
3836 uint32_t src_family
,
3837 uint32_t dst_family
,
3838 const VkImageSubresourceRange
*range
,
3839 VkImageAspectFlags pending_clears
)
3841 if (image
->exclusive
&& src_family
!= dst_family
) {
3842 /* This is an acquire or a release operation and there will be
3843 * a corresponding release/acquire. Do the transition in the
3844 * most flexible queue. */
3846 assert(src_family
== cmd_buffer
->queue_family_index
||
3847 dst_family
== cmd_buffer
->queue_family_index
);
3849 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3852 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3853 (src_family
== RADV_QUEUE_GENERAL
||
3854 dst_family
== RADV_QUEUE_GENERAL
))
3858 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3859 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3861 if (image
->surface
.htile_size
)
3862 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3863 dst_layout
, src_queue_mask
,
3864 dst_queue_mask
, range
,
3867 if (image
->cmask
.size
|| image
->fmask
.size
)
3868 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3869 dst_layout
, src_queue_mask
,
3870 dst_queue_mask
, range
);
3872 if (image
->surface
.dcc_size
)
3873 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3874 dst_layout
, src_queue_mask
,
3875 dst_queue_mask
, range
);
3878 void radv_CmdPipelineBarrier(
3879 VkCommandBuffer commandBuffer
,
3880 VkPipelineStageFlags srcStageMask
,
3881 VkPipelineStageFlags destStageMask
,
3883 uint32_t memoryBarrierCount
,
3884 const VkMemoryBarrier
* pMemoryBarriers
,
3885 uint32_t bufferMemoryBarrierCount
,
3886 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3887 uint32_t imageMemoryBarrierCount
,
3888 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3890 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3891 enum radv_cmd_flush_bits src_flush_bits
= 0;
3892 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3894 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3895 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3896 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3900 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3901 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3902 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3906 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3907 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3908 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3909 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3913 radv_stage_flush(cmd_buffer
, srcStageMask
);
3914 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3916 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3917 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3918 radv_handle_image_transition(cmd_buffer
, image
,
3919 pImageMemoryBarriers
[i
].oldLayout
,
3920 pImageMemoryBarriers
[i
].newLayout
,
3921 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3922 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3923 &pImageMemoryBarriers
[i
].subresourceRange
,
3927 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3931 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3932 struct radv_event
*event
,
3933 VkPipelineStageFlags stageMask
,
3936 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3937 uint64_t va
= radv_buffer_get_va(event
->bo
);
3939 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3941 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3943 /* TODO: this is overkill. Probably should figure something out from
3944 * the stage mask. */
3946 si_cs_emit_write_event_eop(cs
,
3947 cmd_buffer
->state
.predicating
,
3948 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3950 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
3953 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3956 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3958 VkPipelineStageFlags stageMask
)
3960 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3961 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3963 write_event(cmd_buffer
, event
, stageMask
, 1);
3966 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3968 VkPipelineStageFlags stageMask
)
3970 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3971 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3973 write_event(cmd_buffer
, event
, stageMask
, 0);
3976 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3977 uint32_t eventCount
,
3978 const VkEvent
* pEvents
,
3979 VkPipelineStageFlags srcStageMask
,
3980 VkPipelineStageFlags dstStageMask
,
3981 uint32_t memoryBarrierCount
,
3982 const VkMemoryBarrier
* pMemoryBarriers
,
3983 uint32_t bufferMemoryBarrierCount
,
3984 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3985 uint32_t imageMemoryBarrierCount
,
3986 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3988 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3989 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3991 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3992 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3993 uint64_t va
= radv_buffer_get_va(event
->bo
);
3995 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3997 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3999 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
4000 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4004 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4005 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4007 radv_handle_image_transition(cmd_buffer
, image
,
4008 pImageMemoryBarriers
[i
].oldLayout
,
4009 pImageMemoryBarriers
[i
].newLayout
,
4010 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4011 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4012 &pImageMemoryBarriers
[i
].subresourceRange
,
4016 /* TODO: figure out how to do memory barriers without waiting */
4017 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
4018 RADV_CMD_FLAG_INV_GLOBAL_L2
|
4019 RADV_CMD_FLAG_INV_VMEM_L1
|
4020 RADV_CMD_FLAG_INV_SMEM_L1
;