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7d86eee97915b34d41d0d512d25269867d4127cb
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 return cmd_buffer->record_result;
296 }
297
298 static bool
299 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
300 uint64_t min_needed)
301 {
302 uint64_t new_size;
303 struct radeon_winsys_bo *bo;
304 struct radv_cmd_buffer_upload *upload;
305 struct radv_device *device = cmd_buffer->device;
306
307 new_size = MAX2(min_needed, 16 * 1024);
308 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
309
310 bo = device->ws->buffer_create(device->ws,
311 new_size, 4096,
312 RADEON_DOMAIN_GTT,
313 RADEON_FLAG_CPU_ACCESS|
314 RADEON_FLAG_NO_INTERPROCESS_SHARING);
315
316 if (!bo) {
317 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
318 return false;
319 }
320
321 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
322 if (cmd_buffer->upload.upload_bo) {
323 upload = malloc(sizeof(*upload));
324
325 if (!upload) {
326 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
327 device->ws->buffer_destroy(bo);
328 return false;
329 }
330
331 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
332 list_add(&upload->list, &cmd_buffer->upload.list);
333 }
334
335 cmd_buffer->upload.upload_bo = bo;
336 cmd_buffer->upload.size = new_size;
337 cmd_buffer->upload.offset = 0;
338 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
339
340 if (!cmd_buffer->upload.map) {
341 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
342 return false;
343 }
344
345 return true;
346 }
347
348 bool
349 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
350 unsigned size,
351 unsigned alignment,
352 unsigned *out_offset,
353 void **ptr)
354 {
355 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
356 if (offset + size > cmd_buffer->upload.size) {
357 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
358 return false;
359 offset = 0;
360 }
361
362 *out_offset = offset;
363 *ptr = cmd_buffer->upload.map + offset;
364
365 cmd_buffer->upload.offset = offset + size;
366 return true;
367 }
368
369 bool
370 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
371 unsigned size, unsigned alignment,
372 const void *data, unsigned *out_offset)
373 {
374 uint8_t *ptr;
375
376 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
377 out_offset, (void **)&ptr))
378 return false;
379
380 if (ptr)
381 memcpy(ptr, data, size);
382
383 return true;
384 }
385
386 static void
387 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
388 unsigned count, const uint32_t *data)
389 {
390 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
391 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
392 S_370_WR_CONFIRM(1) |
393 S_370_ENGINE_SEL(V_370_ME));
394 radeon_emit(cs, va);
395 radeon_emit(cs, va >> 32);
396 radeon_emit_array(cs, data, count);
397 }
398
399 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
400 {
401 struct radv_device *device = cmd_buffer->device;
402 struct radeon_winsys_cs *cs = cmd_buffer->cs;
403 uint64_t va;
404
405 va = radv_buffer_get_va(device->trace_bo);
406 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
407 va += 4;
408
409 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
410
411 ++cmd_buffer->state.trace_id;
412 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
413 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
414 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
415 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
416 }
417
418 static void
419 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
420 {
421 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
422 enum radv_cmd_flush_bits flags;
423
424 /* Force wait for graphics/compute engines to be idle. */
425 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
426 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
427
428 si_cs_emit_cache_flush(cmd_buffer->cs, false,
429 cmd_buffer->device->physical_device->rad_info.chip_class,
430 NULL, 0,
431 radv_cmd_buffer_uses_mec(cmd_buffer),
432 flags);
433 }
434
435 if (unlikely(cmd_buffer->device->trace_bo))
436 radv_cmd_buffer_trace_emit(cmd_buffer);
437 }
438
439 static void
440 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
441 struct radv_pipeline *pipeline, enum ring_type ring)
442 {
443 struct radv_device *device = cmd_buffer->device;
444 struct radeon_winsys_cs *cs = cmd_buffer->cs;
445 uint32_t data[2];
446 uint64_t va;
447
448 va = radv_buffer_get_va(device->trace_bo);
449
450 switch (ring) {
451 case RING_GFX:
452 va += 8;
453 break;
454 case RING_COMPUTE:
455 va += 16;
456 break;
457 default:
458 assert(!"invalid ring type");
459 }
460
461 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
462 cmd_buffer->cs, 6);
463
464 data[0] = (uintptr_t)pipeline;
465 data[1] = (uintptr_t)pipeline >> 32;
466
467 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
468 radv_emit_write_data_packet(cs, va, 2, data);
469 }
470
471 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
472 struct radv_descriptor_set *set,
473 unsigned idx)
474 {
475 cmd_buffer->descriptors[idx] = set;
476 if (set)
477 cmd_buffer->state.valid_descriptors |= (1u << idx);
478 else
479 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
480 cmd_buffer->state.descriptors_dirty |= (1u << idx);
481
482 }
483
484 static void
485 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[MAX_SETS * 2] = {};
490 uint64_t va;
491 unsigned i;
492 va = radv_buffer_get_va(device->trace_bo) + 24;
493
494 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
495 cmd_buffer->cs, 4 + MAX_SETS * 2);
496
497 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
498 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
499 data[i * 2] = (uintptr_t)set;
500 data[i * 2 + 1] = (uintptr_t)set >> 32;
501 }
502
503 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
504 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
505 }
506
507 static void
508 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
509 struct radv_pipeline *pipeline)
510 {
511 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
512 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
513 8);
514 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
515 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
516
517 if (cmd_buffer->device->physical_device->has_rbplus) {
518
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
521
522 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
523 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
524 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
525 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
526 }
527 }
528
529 static void
530 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
534 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
535 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
536
537 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
538 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
539 }
540
541 struct ac_userdata_info *
542 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
543 gl_shader_stage stage,
544 int idx)
545 {
546 if (stage == MESA_SHADER_VERTEX) {
547 if (pipeline->shaders[MESA_SHADER_VERTEX])
548 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
549 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
550 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
552 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
553 } else if (stage == MESA_SHADER_TESS_EVAL) {
554 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
555 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
556 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
557 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
558 }
559 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
560 }
561
562 static void
563 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_pipeline *pipeline,
565 gl_shader_stage stage,
566 int idx, uint64_t va)
567 {
568 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
569 uint32_t base_reg = pipeline->user_data_0[stage];
570 if (loc->sgpr_idx == -1)
571 return;
572 assert(loc->num_sgprs == 2);
573 assert(!loc->indirect);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
575 radeon_emit(cmd_buffer->cs, va);
576 radeon_emit(cmd_buffer->cs, va >> 32);
577 }
578
579 static void
580 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
581 struct radv_pipeline *pipeline)
582 {
583 int num_samples = pipeline->graphics.ms.num_samples;
584 struct radv_multisample_state *ms = &pipeline->graphics.ms;
585 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
586
587 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
588 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
589 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
590
591 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
592 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
593
594 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
595 return;
596
597 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
598 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
599 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
600
601 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
602
603 /* GFX9: Flush DFSM when the AA mode changes. */
604 if (cmd_buffer->device->dfsm_allowed) {
605 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
606 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
607 }
608 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
609 uint32_t offset;
610 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
611 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
612 if (loc->sgpr_idx == -1)
613 return;
614 assert(loc->num_sgprs == 1);
615 assert(!loc->indirect);
616 switch (num_samples) {
617 default:
618 offset = 0;
619 break;
620 case 2:
621 offset = 1;
622 break;
623 case 4:
624 offset = 3;
625 break;
626 case 8:
627 offset = 7;
628 break;
629 case 16:
630 offset = 15;
631 break;
632 }
633
634 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
635 cmd_buffer->sample_positions_needed = true;
636 }
637 }
638
639 static void
640 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
641 struct radv_pipeline *pipeline)
642 {
643 struct radv_raster_state *raster = &pipeline->graphics.raster;
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
646 raster->pa_cl_clip_cntl);
647 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
648 raster->spi_interp_control);
649 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
650 raster->pa_su_vtx_cntl);
651 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
652 raster->pa_su_sc_mode_cntl);
653 }
654
655 static inline void
656 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
657 unsigned size)
658 {
659 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
660 si_cp_dma_prefetch(cmd_buffer, va, size);
661 }
662
663 static void
664 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
665 {
666 if (cmd_buffer->state.vb_prefetch_dirty) {
667 radv_emit_prefetch_TC_L2_async(cmd_buffer,
668 cmd_buffer->state.vb_va,
669 cmd_buffer->state.vb_size);
670 cmd_buffer->state.vb_prefetch_dirty = false;
671 }
672 }
673
674 static void
675 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
676 struct radv_shader_variant *shader)
677 {
678 struct radeon_winsys *ws = cmd_buffer->device->ws;
679 struct radeon_winsys_cs *cs = cmd_buffer->cs;
680 uint64_t va;
681
682 if (!shader)
683 return;
684
685 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
686
687 radv_cs_add_buffer(ws, cs, shader->bo, 8);
688 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
689 }
690
691 static void
692 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
693 struct radv_pipeline *pipeline)
694 {
695 radv_emit_shader_prefetch(cmd_buffer,
696 pipeline->shaders[MESA_SHADER_VERTEX]);
697 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_GEOMETRY]);
704 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_FRAGMENT]);
707 }
708
709 static void
710 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
711 struct radv_pipeline *pipeline,
712 struct radv_shader_variant *shader)
713 {
714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
715
716 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
717 pipeline->graphics.vs.spi_vs_out_config);
718
719 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
720 pipeline->graphics.vs.spi_shader_pos_format);
721
722 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
723 radeon_emit(cmd_buffer->cs, va >> 8);
724 radeon_emit(cmd_buffer->cs, va >> 40);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2);
727
728 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
729 S_028818_VTX_W0_FMT(1) |
730 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
731 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
732 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
733
734
735 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
736 pipeline->graphics.vs.pa_cl_vs_out_cntl);
737
738 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
739 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
740 pipeline->graphics.vs.vgt_reuse_off);
741 }
742
743 static void
744 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_pipeline *pipeline,
746 struct radv_shader_variant *shader)
747 {
748 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
749
750 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
751 radeon_emit(cmd_buffer->cs, va >> 8);
752 radeon_emit(cmd_buffer->cs, va >> 40);
753 radeon_emit(cmd_buffer->cs, shader->rsrc1);
754 radeon_emit(cmd_buffer->cs, shader->rsrc2);
755 }
756
757 static void
758 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
759 struct radv_shader_variant *shader)
760 {
761 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
762 uint32_t rsrc2 = shader->rsrc2;
763
764 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
765 radeon_emit(cmd_buffer->cs, va >> 8);
766 radeon_emit(cmd_buffer->cs, va >> 40);
767
768 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
769 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
770 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
771 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
772
773 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
774 radeon_emit(cmd_buffer->cs, shader->rsrc1);
775 radeon_emit(cmd_buffer->cs, rsrc2);
776 }
777
778 static void
779 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
780 struct radv_shader_variant *shader)
781 {
782 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
783
784 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
785 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
786 radeon_emit(cmd_buffer->cs, va >> 8);
787 radeon_emit(cmd_buffer->cs, va >> 40);
788
789 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
790 radeon_emit(cmd_buffer->cs, shader->rsrc1);
791 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
792 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
793 } else {
794 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
795 radeon_emit(cmd_buffer->cs, va >> 8);
796 radeon_emit(cmd_buffer->cs, va >> 40);
797 radeon_emit(cmd_buffer->cs, shader->rsrc1);
798 radeon_emit(cmd_buffer->cs, shader->rsrc2);
799 }
800 }
801
802 static void
803 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_pipeline *pipeline)
805 {
806 struct radv_shader_variant *vs;
807
808 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
809
810 /* Skip shaders merged into HS/GS */
811 vs = pipeline->shaders[MESA_SHADER_VERTEX];
812 if (!vs)
813 return;
814
815 if (vs->info.vs.as_ls)
816 radv_emit_hw_ls(cmd_buffer, vs);
817 else if (vs->info.vs.as_es)
818 radv_emit_hw_es(cmd_buffer, pipeline, vs);
819 else
820 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
821 }
822
823
824 static void
825 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
826 struct radv_pipeline *pipeline)
827 {
828 if (!radv_pipeline_has_tess(pipeline))
829 return;
830
831 struct radv_shader_variant *tes, *tcs;
832
833 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
834 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
835
836 if (tes) {
837 if (tes->info.tes.as_es)
838 radv_emit_hw_es(cmd_buffer, pipeline, tes);
839 else
840 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
841 }
842
843 radv_emit_hw_hs(cmd_buffer, tcs);
844
845 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
846 pipeline->graphics.tess.tf_param);
847
848 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
849 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
850 pipeline->graphics.tess.ls_hs_config);
851 else
852 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
853 pipeline->graphics.tess.ls_hs_config);
854
855 struct ac_userdata_info *loc;
856
857 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
858 if (loc->sgpr_idx != -1) {
859 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
860 assert(loc->num_sgprs == 4);
861 assert(!loc->indirect);
862 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
866 pipeline->graphics.tess.num_tcs_input_cp << 26);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
868 }
869
870 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
871 if (loc->sgpr_idx != -1) {
872 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
873 assert(loc->num_sgprs == 1);
874 assert(!loc->indirect);
875
876 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
877 pipeline->graphics.tess.offchip_layout);
878 }
879
880 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
881 if (loc->sgpr_idx != -1) {
882 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
883 assert(loc->num_sgprs == 1);
884 assert(!loc->indirect);
885
886 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
887 pipeline->graphics.tess.tcs_in_layout);
888 }
889 }
890
891 static void
892 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
893 struct radv_pipeline *pipeline)
894 {
895 struct radv_shader_variant *gs;
896 uint64_t va;
897
898 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
899
900 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
901 if (!gs)
902 return;
903
904 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
905
906 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
907 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
908 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910
911 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
914
915 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
916 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
917 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
918 radeon_emit(cmd_buffer->cs, 0);
919 radeon_emit(cmd_buffer->cs, 0);
920 radeon_emit(cmd_buffer->cs, 0);
921
922 uint32_t gs_num_invocations = gs->info.gs.invocations;
923 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
924 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
925 S_028B90_ENABLE(gs_num_invocations > 0));
926
927 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
928 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
929
930 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
931
932 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
933 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
934 radeon_emit(cmd_buffer->cs, va >> 8);
935 radeon_emit(cmd_buffer->cs, va >> 40);
936
937 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
938 radeon_emit(cmd_buffer->cs, gs->rsrc1);
939 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
940 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
941
942 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
943 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
944 } else {
945 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
946 radeon_emit(cmd_buffer->cs, va >> 8);
947 radeon_emit(cmd_buffer->cs, va >> 40);
948 radeon_emit(cmd_buffer->cs, gs->rsrc1);
949 radeon_emit(cmd_buffer->cs, gs->rsrc2);
950 }
951
952 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
953
954 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
955 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
956 if (loc->sgpr_idx != -1) {
957 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
958 uint32_t num_entries = 64;
959 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
960
961 if (is_vi)
962 num_entries *= stride;
963
964 stride = S_008F04_STRIDE(stride);
965 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
966 radeon_emit(cmd_buffer->cs, stride);
967 radeon_emit(cmd_buffer->cs, num_entries);
968 }
969 }
970
971 static void
972 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
973 struct radv_pipeline *pipeline)
974 {
975 struct radv_shader_variant *ps;
976 uint64_t va;
977 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
978 struct radv_blend_state *blend = &pipeline->graphics.blend;
979 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
980
981 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
982 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
983
984 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
985 radeon_emit(cmd_buffer->cs, va >> 8);
986 radeon_emit(cmd_buffer->cs, va >> 40);
987 radeon_emit(cmd_buffer->cs, ps->rsrc1);
988 radeon_emit(cmd_buffer->cs, ps->rsrc2);
989
990 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
991 pipeline->graphics.db_shader_control);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
994 ps->config.spi_ps_input_ena);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
997 ps->config.spi_ps_input_addr);
998
999 if (ps->info.info.ps.force_persample)
1000 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1001
1002 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1003 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1008 pipeline->graphics.shader_z_format);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1013 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1014
1015 if (cmd_buffer->device->dfsm_allowed) {
1016 /* optimise this? */
1017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1018 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1019 }
1020
1021 if (pipeline->graphics.ps_input_cntl_num) {
1022 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1023 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1024 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1025 }
1026 }
1027 }
1028
1029 static void
1030 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1031 struct radv_pipeline *pipeline)
1032 {
1033 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1034
1035 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1036 return;
1037
1038 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1039 pipeline->graphics.vtx_reuse_depth);
1040 }
1041
1042 static void
1043 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1044 {
1045 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1046
1047 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1048 return;
1049
1050 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1051 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1052 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1053 radv_update_multisample_state(cmd_buffer, pipeline);
1054 radv_emit_vertex_shader(cmd_buffer, pipeline);
1055 radv_emit_tess_shaders(cmd_buffer, pipeline);
1056 radv_emit_geometry_shader(cmd_buffer, pipeline);
1057 radv_emit_fragment_shader(cmd_buffer, pipeline);
1058 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1059
1060 cmd_buffer->scratch_size_needed =
1061 MAX2(cmd_buffer->scratch_size_needed,
1062 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1063
1064 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1065 S_0286E8_WAVES(pipeline->max_waves) |
1066 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1067
1068 if (!cmd_buffer->state.emitted_pipeline ||
1069 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1070 pipeline->graphics.can_use_guardband)
1071 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1072
1073 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1074
1075 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1076 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1077 } else {
1078 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1079 }
1080 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1081
1082 if (unlikely(cmd_buffer->device->trace_bo))
1083 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1084
1085 cmd_buffer->state.emitted_pipeline = pipeline;
1086
1087 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1088 }
1089
1090 static void
1091 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1092 {
1093 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1094 cmd_buffer->state.dynamic.viewport.viewports);
1095 }
1096
1097 static void
1098 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1099 {
1100 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1101
1102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1103 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1104 si_emit_cache_flush(cmd_buffer);
1105 }
1106 si_write_scissors(cmd_buffer->cs, 0, count,
1107 cmd_buffer->state.dynamic.scissor.scissors,
1108 cmd_buffer->state.dynamic.viewport.viewports,
1109 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1110 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1111 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1112 }
1113
1114 static void
1115 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1116 {
1117 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1118
1119 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1120 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1121 }
1122
1123 static void
1124 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1125 {
1126 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1127
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1129 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1130 }
1131
1132 static void
1133 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1136
1137 radeon_set_context_reg_seq(cmd_buffer->cs,
1138 R_028430_DB_STENCILREFMASK, 2);
1139 radeon_emit(cmd_buffer->cs,
1140 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1141 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1142 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1143 S_028430_STENCILOPVAL(1));
1144 radeon_emit(cmd_buffer->cs,
1145 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1146 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1147 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1148 S_028434_STENCILOPVAL_BF(1));
1149 }
1150
1151 static void
1152 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1153 {
1154 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1155
1156 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1157 fui(d->depth_bounds.min));
1158 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1159 fui(d->depth_bounds.max));
1160 }
1161
1162 static void
1163 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1164 {
1165 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1166 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1167 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1168 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1169
1170 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1171 radeon_set_context_reg_seq(cmd_buffer->cs,
1172 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1173 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1174 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1175 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1176 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1178 }
1179 }
1180
1181 static void
1182 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1183 int index,
1184 struct radv_color_buffer_info *cb)
1185 {
1186 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1187
1188 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1189 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1190 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1191 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1192 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1196 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1201
1202 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1203 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1204 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1205
1206 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1207 cb->gfx9_epitch);
1208 } else {
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1210 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1211 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1212 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1216 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1219 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1221
1222 if (is_vi) { /* DCC BASE */
1223 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1224 }
1225 }
1226 }
1227
1228 static void
1229 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1230 struct radv_ds_buffer_info *ds,
1231 struct radv_image *image,
1232 VkImageLayout layout)
1233 {
1234 uint32_t db_z_info = ds->db_z_info;
1235 uint32_t db_stencil_info = ds->db_stencil_info;
1236
1237 if (!radv_layout_has_htile(image, layout,
1238 radv_image_queue_family_mask(image,
1239 cmd_buffer->queue_family_index,
1240 cmd_buffer->queue_family_index))) {
1241 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1242 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1243 }
1244
1245 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1246 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1247
1248
1249 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1250 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1251 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1252 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1253 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1254
1255 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1256 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1257 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1258 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1259 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1260 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1261 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1263 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1265 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1266
1267 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1268 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1269 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1270 } else {
1271 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1272
1273 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1274 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1275 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1276 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1277 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1278 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1279 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1280 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1282 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1283
1284 }
1285
1286 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1287 ds->pa_su_poly_offset_db_fmt_cntl);
1288 }
1289
1290 void
1291 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_image *image,
1293 VkClearDepthStencilValue ds_clear_value,
1294 VkImageAspectFlags aspects)
1295 {
1296 uint64_t va = radv_buffer_get_va(image->bo);
1297 va += image->offset + image->clear_value_offset;
1298 unsigned reg_offset = 0, reg_count = 0;
1299
1300 if (!image->surface.htile_size)
1301 return;
1302
1303 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1304 ++reg_count;
1305 } else {
1306 ++reg_offset;
1307 va += 4;
1308 }
1309 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1310 ++reg_count;
1311
1312 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1313 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1314 S_370_WR_CONFIRM(1) |
1315 S_370_ENGINE_SEL(V_370_PFP));
1316 radeon_emit(cmd_buffer->cs, va);
1317 radeon_emit(cmd_buffer->cs, va >> 32);
1318 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1319 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1320 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1321 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1322
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1324 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1325 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1326 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1327 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1328 }
1329
1330 static void
1331 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1332 struct radv_image *image)
1333 {
1334 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1335 uint64_t va = radv_buffer_get_va(image->bo);
1336 va += image->offset + image->clear_value_offset;
1337 unsigned reg_offset = 0, reg_count = 0;
1338
1339 if (!image->surface.htile_size)
1340 return;
1341
1342 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1343 ++reg_count;
1344 } else {
1345 ++reg_offset;
1346 va += 4;
1347 }
1348 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1349 ++reg_count;
1350
1351 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1352 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1353 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1354 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1355 radeon_emit(cmd_buffer->cs, va);
1356 radeon_emit(cmd_buffer->cs, va >> 32);
1357 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1358 radeon_emit(cmd_buffer->cs, 0);
1359
1360 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1361 radeon_emit(cmd_buffer->cs, 0);
1362 }
1363
1364 /*
1365 *with DCC some colors don't require CMASK elimiation before being
1366 * used as a texture. This sets a predicate value to determine if the
1367 * cmask eliminate is required.
1368 */
1369 void
1370 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1371 struct radv_image *image,
1372 bool value)
1373 {
1374 uint64_t pred_val = value;
1375 uint64_t va = radv_buffer_get_va(image->bo);
1376 va += image->offset + image->dcc_pred_offset;
1377
1378 if (!image->surface.dcc_size)
1379 return;
1380
1381 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1382 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1383 S_370_WR_CONFIRM(1) |
1384 S_370_ENGINE_SEL(V_370_PFP));
1385 radeon_emit(cmd_buffer->cs, va);
1386 radeon_emit(cmd_buffer->cs, va >> 32);
1387 radeon_emit(cmd_buffer->cs, pred_val);
1388 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1389 }
1390
1391 void
1392 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1393 struct radv_image *image,
1394 int idx,
1395 uint32_t color_values[2])
1396 {
1397 uint64_t va = radv_buffer_get_va(image->bo);
1398 va += image->offset + image->clear_value_offset;
1399
1400 if (!image->cmask.size && !image->surface.dcc_size)
1401 return;
1402
1403 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1404 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1405 S_370_WR_CONFIRM(1) |
1406 S_370_ENGINE_SEL(V_370_PFP));
1407 radeon_emit(cmd_buffer->cs, va);
1408 radeon_emit(cmd_buffer->cs, va >> 32);
1409 radeon_emit(cmd_buffer->cs, color_values[0]);
1410 radeon_emit(cmd_buffer->cs, color_values[1]);
1411
1412 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1413 radeon_emit(cmd_buffer->cs, color_values[0]);
1414 radeon_emit(cmd_buffer->cs, color_values[1]);
1415 }
1416
1417 static void
1418 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1419 struct radv_image *image,
1420 int idx)
1421 {
1422 uint64_t va = radv_buffer_get_va(image->bo);
1423 va += image->offset + image->clear_value_offset;
1424
1425 if (!image->cmask.size && !image->surface.dcc_size)
1426 return;
1427
1428 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1431 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1432 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1433 COPY_DATA_COUNT_SEL);
1434 radeon_emit(cmd_buffer->cs, va);
1435 radeon_emit(cmd_buffer->cs, va >> 32);
1436 radeon_emit(cmd_buffer->cs, reg >> 2);
1437 radeon_emit(cmd_buffer->cs, 0);
1438
1439 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1440 radeon_emit(cmd_buffer->cs, 0);
1441 }
1442
1443 static void
1444 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1445 {
1446 int i;
1447 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1448 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1449
1450 /* this may happen for inherited secondary recording */
1451 if (!framebuffer)
1452 return;
1453
1454 for (i = 0; i < 8; ++i) {
1455 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1456 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1457 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1458 continue;
1459 }
1460
1461 int idx = subpass->color_attachments[i].attachment;
1462 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1463
1464 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1465
1466 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1467 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1468
1469 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1470 }
1471
1472 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1473 int idx = subpass->depth_stencil_attachment.attachment;
1474 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1475 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1476 struct radv_image *image = att->attachment->image;
1477 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1478 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1479 cmd_buffer->queue_family_index,
1480 cmd_buffer->queue_family_index);
1481 /* We currently don't support writing decompressed HTILE */
1482 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1483 radv_layout_is_htile_compressed(image, layout, queue_mask));
1484
1485 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1486
1487 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1488 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1489 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1490 }
1491 radv_load_depth_clear_regs(cmd_buffer, image);
1492 } else {
1493 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1494 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1495 else
1496 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1497
1498 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1499 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1500 }
1501 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1502 S_028208_BR_X(framebuffer->width) |
1503 S_028208_BR_Y(framebuffer->height));
1504
1505 if (cmd_buffer->device->dfsm_allowed) {
1506 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1507 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1508 }
1509
1510 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1511 }
1512
1513 static void
1514 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1515 {
1516 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1517
1518 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1519 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1520 2, cmd_buffer->state.index_type);
1521 } else {
1522 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1523 radeon_emit(cs, cmd_buffer->state.index_type);
1524 }
1525
1526 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1527 radeon_emit(cs, cmd_buffer->state.index_va);
1528 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1529
1530 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1531 radeon_emit(cs, cmd_buffer->state.max_index_count);
1532
1533 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1534 }
1535
1536 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1537 {
1538 uint32_t db_count_control;
1539
1540 if(!cmd_buffer->state.active_occlusion_queries) {
1541 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1542 db_count_control = 0;
1543 } else {
1544 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1545 }
1546 } else {
1547 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1548 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1549 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1550 S_028004_ZPASS_ENABLE(1) |
1551 S_028004_SLICE_EVEN_ENABLE(1) |
1552 S_028004_SLICE_ODD_ENABLE(1);
1553 } else {
1554 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1555 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1556 }
1557 }
1558
1559 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1560 }
1561
1562 static void
1563 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1564 {
1565 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1566 return;
1567
1568 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1569 radv_emit_viewport(cmd_buffer);
1570
1571 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1572 radv_emit_scissor(cmd_buffer);
1573
1574 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1575 radv_emit_line_width(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1578 radv_emit_blend_constants(cmd_buffer);
1579
1580 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1581 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1582 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1583 radv_emit_stencil(cmd_buffer);
1584
1585 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1586 radv_emit_depth_bounds(cmd_buffer);
1587
1588 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1589 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1590 radv_emit_depth_biais(cmd_buffer);
1591
1592 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1593 }
1594
1595 static void
1596 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1597 struct radv_pipeline *pipeline,
1598 int idx,
1599 uint64_t va,
1600 gl_shader_stage stage)
1601 {
1602 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1603 uint32_t base_reg = pipeline->user_data_0[stage];
1604
1605 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1606 return;
1607
1608 assert(!desc_set_loc->indirect);
1609 assert(desc_set_loc->num_sgprs == 2);
1610 radeon_set_sh_reg_seq(cmd_buffer->cs,
1611 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1612 radeon_emit(cmd_buffer->cs, va);
1613 radeon_emit(cmd_buffer->cs, va >> 32);
1614 }
1615
1616 static void
1617 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1618 VkShaderStageFlags stages,
1619 struct radv_descriptor_set *set,
1620 unsigned idx)
1621 {
1622 if (cmd_buffer->state.pipeline) {
1623 radv_foreach_stage(stage, stages) {
1624 if (cmd_buffer->state.pipeline->shaders[stage])
1625 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1626 idx, set->va,
1627 stage);
1628 }
1629 }
1630
1631 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1632 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1633 idx, set->va,
1634 MESA_SHADER_COMPUTE);
1635 }
1636
1637 static void
1638 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1639 {
1640 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1641 unsigned bo_offset;
1642
1643 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1644 set->mapped_ptr,
1645 &bo_offset))
1646 return;
1647
1648 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1649 set->va += bo_offset;
1650 }
1651
1652 static void
1653 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1654 {
1655 uint32_t size = MAX_SETS * 2 * 4;
1656 uint32_t offset;
1657 void *ptr;
1658
1659 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1660 256, &offset, &ptr))
1661 return;
1662
1663 for (unsigned i = 0; i < MAX_SETS; i++) {
1664 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1665 uint64_t set_va = 0;
1666 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1667 if (cmd_buffer->state.valid_descriptors & (1u << i))
1668 set_va = set->va;
1669 uptr[0] = set_va & 0xffffffff;
1670 uptr[1] = set_va >> 32;
1671 }
1672
1673 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1674 va += offset;
1675
1676 if (cmd_buffer->state.pipeline) {
1677 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680
1681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696 }
1697
1698 if (cmd_buffer->state.compute_pipeline)
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 static void
1704 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1705 VkShaderStageFlags stages)
1706 {
1707 unsigned i;
1708
1709 if (!cmd_buffer->state.descriptors_dirty)
1710 return;
1711
1712 if (cmd_buffer->state.push_descriptors_dirty)
1713 radv_flush_push_descriptors(cmd_buffer);
1714
1715 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1716 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1717 radv_flush_indirect_descriptor_sets(cmd_buffer);
1718 }
1719
1720 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1721 cmd_buffer->cs,
1722 MAX_SETS * MESA_SHADER_STAGES * 4);
1723
1724 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1725 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1726 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1727 continue;
1728
1729 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1730 }
1731 cmd_buffer->state.descriptors_dirty = 0;
1732 cmd_buffer->state.push_descriptors_dirty = false;
1733
1734 if (unlikely(cmd_buffer->device->trace_bo))
1735 radv_save_descriptors(cmd_buffer);
1736
1737 assert(cmd_buffer->cs->cdw <= cdw_max);
1738 }
1739
1740 static void
1741 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1742 struct radv_pipeline *pipeline,
1743 VkShaderStageFlags stages)
1744 {
1745 struct radv_pipeline_layout *layout = pipeline->layout;
1746 unsigned offset;
1747 void *ptr;
1748 uint64_t va;
1749
1750 stages &= cmd_buffer->push_constant_stages;
1751 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1752 return;
1753
1754 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1755 16 * layout->dynamic_offset_count,
1756 256, &offset, &ptr))
1757 return;
1758
1759 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1760 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1761 16 * layout->dynamic_offset_count);
1762
1763 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1764 va += offset;
1765
1766 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1767 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1768
1769 radv_foreach_stage(stage, stages) {
1770 if (pipeline->shaders[stage]) {
1771 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1772 AC_UD_PUSH_CONSTANTS, va);
1773 }
1774 }
1775
1776 cmd_buffer->push_constant_stages &= ~stages;
1777 assert(cmd_buffer->cs->cdw <= cdw_max);
1778 }
1779
1780 static bool
1781 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1782 {
1783 if ((pipeline_is_dirty ||
1784 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1785 cmd_buffer->state.pipeline->vertex_elements.count &&
1786 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1787 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1788 unsigned vb_offset;
1789 void *vb_ptr;
1790 uint32_t i = 0;
1791 uint32_t count = velems->count;
1792 uint64_t va;
1793
1794 /* allocate some descriptor state for vertex buffers */
1795 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1796 &vb_offset, &vb_ptr))
1797 return false;
1798
1799 for (i = 0; i < count; i++) {
1800 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1801 uint32_t offset;
1802 int vb = velems->binding[i];
1803 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1804 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1805
1806 va = radv_buffer_get_va(buffer->bo);
1807
1808 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1809 va += offset + buffer->offset;
1810 desc[0] = va;
1811 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1812 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1813 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1814 else
1815 desc[2] = buffer->size - offset;
1816 desc[3] = velems->rsrc_word3[i];
1817 }
1818
1819 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1820 va += vb_offset;
1821
1822 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1823 AC_UD_VS_VERTEX_BUFFERS, va);
1824
1825 cmd_buffer->state.vb_va = va;
1826 cmd_buffer->state.vb_size = count * 16;
1827 cmd_buffer->state.vb_prefetch_dirty = true;
1828 }
1829 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1830
1831 return true;
1832 }
1833
1834 static bool
1835 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1836 {
1837 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1838 return false;
1839
1840 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1841 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1842 VK_SHADER_STAGE_ALL_GRAPHICS);
1843
1844 return true;
1845 }
1846
1847 static void
1848 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1849 bool instanced_draw, bool indirect_draw,
1850 uint32_t draw_vertex_count)
1851 {
1852 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1853 struct radv_cmd_state *state = &cmd_buffer->state;
1854 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1855 uint32_t ia_multi_vgt_param;
1856 int32_t primitive_reset_en;
1857
1858 /* Draw state. */
1859 ia_multi_vgt_param =
1860 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1861 indirect_draw, draw_vertex_count);
1862
1863 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1864 if (info->chip_class >= GFX9) {
1865 radeon_set_uconfig_reg_idx(cs,
1866 R_030960_IA_MULTI_VGT_PARAM,
1867 4, ia_multi_vgt_param);
1868 } else if (info->chip_class >= CIK) {
1869 radeon_set_context_reg_idx(cs,
1870 R_028AA8_IA_MULTI_VGT_PARAM,
1871 1, ia_multi_vgt_param);
1872 } else {
1873 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1874 ia_multi_vgt_param);
1875 }
1876 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1877 }
1878
1879 /* Primitive restart. */
1880 primitive_reset_en =
1881 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1882
1883 if (primitive_reset_en != state->last_primitive_reset_en) {
1884 state->last_primitive_reset_en = primitive_reset_en;
1885 if (info->chip_class >= GFX9) {
1886 radeon_set_uconfig_reg(cs,
1887 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1888 primitive_reset_en);
1889 } else {
1890 radeon_set_context_reg(cs,
1891 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1892 primitive_reset_en);
1893 }
1894 }
1895
1896 if (primitive_reset_en) {
1897 uint32_t primitive_reset_index =
1898 state->index_type ? 0xffffffffu : 0xffffu;
1899
1900 if (primitive_reset_index != state->last_primitive_reset_index) {
1901 radeon_set_context_reg(cs,
1902 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1903 primitive_reset_index);
1904 state->last_primitive_reset_index = primitive_reset_index;
1905 }
1906 }
1907 }
1908
1909 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1910 VkPipelineStageFlags src_stage_mask)
1911 {
1912 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1913 VK_PIPELINE_STAGE_TRANSFER_BIT |
1914 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1915 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1916 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1917 }
1918
1919 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1920 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1921 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1922 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1923 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1924 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1925 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1926 VK_PIPELINE_STAGE_TRANSFER_BIT |
1927 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1928 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1929 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1930 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1931 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1932 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1933 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1934 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1935 }
1936 }
1937
1938 static enum radv_cmd_flush_bits
1939 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1940 VkAccessFlags src_flags)
1941 {
1942 enum radv_cmd_flush_bits flush_bits = 0;
1943 uint32_t b;
1944 for_each_bit(b, src_flags) {
1945 switch ((VkAccessFlagBits)(1 << b)) {
1946 case VK_ACCESS_SHADER_WRITE_BIT:
1947 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1948 break;
1949 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1950 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1951 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1952 break;
1953 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1954 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1955 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1956 break;
1957 case VK_ACCESS_TRANSFER_WRITE_BIT:
1958 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1959 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1960 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1961 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1962 RADV_CMD_FLAG_INV_GLOBAL_L2;
1963 break;
1964 default:
1965 break;
1966 }
1967 }
1968 return flush_bits;
1969 }
1970
1971 static enum radv_cmd_flush_bits
1972 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1973 VkAccessFlags dst_flags,
1974 struct radv_image *image)
1975 {
1976 enum radv_cmd_flush_bits flush_bits = 0;
1977 uint32_t b;
1978 for_each_bit(b, dst_flags) {
1979 switch ((VkAccessFlagBits)(1 << b)) {
1980 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1981 case VK_ACCESS_INDEX_READ_BIT:
1982 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1983 break;
1984 case VK_ACCESS_UNIFORM_READ_BIT:
1985 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1986 break;
1987 case VK_ACCESS_SHADER_READ_BIT:
1988 case VK_ACCESS_TRANSFER_READ_BIT:
1989 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1990 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1991 RADV_CMD_FLAG_INV_GLOBAL_L2;
1992 break;
1993 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1994 /* TODO: change to image && when the image gets passed
1995 * through from the subpass. */
1996 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1997 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1998 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1999 break;
2000 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2001 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2002 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2003 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2004 break;
2005 default:
2006 break;
2007 }
2008 }
2009 return flush_bits;
2010 }
2011
2012 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2013 {
2014 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2015 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2016 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2017 NULL);
2018 }
2019
2020 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2021 VkAttachmentReference att)
2022 {
2023 unsigned idx = att.attachment;
2024 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2025 VkImageSubresourceRange range;
2026 range.aspectMask = 0;
2027 range.baseMipLevel = view->base_mip;
2028 range.levelCount = 1;
2029 range.baseArrayLayer = view->base_layer;
2030 range.layerCount = cmd_buffer->state.framebuffer->layers;
2031
2032 radv_handle_image_transition(cmd_buffer,
2033 view->image,
2034 cmd_buffer->state.attachments[idx].current_layout,
2035 att.layout, 0, 0, &range,
2036 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2037
2038 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2039
2040
2041 }
2042
2043 void
2044 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2045 const struct radv_subpass *subpass, bool transitions)
2046 {
2047 if (transitions) {
2048 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2049
2050 for (unsigned i = 0; i < subpass->color_count; ++i) {
2051 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2052 radv_handle_subpass_image_transition(cmd_buffer,
2053 subpass->color_attachments[i]);
2054 }
2055
2056 for (unsigned i = 0; i < subpass->input_count; ++i) {
2057 radv_handle_subpass_image_transition(cmd_buffer,
2058 subpass->input_attachments[i]);
2059 }
2060
2061 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2062 radv_handle_subpass_image_transition(cmd_buffer,
2063 subpass->depth_stencil_attachment);
2064 }
2065 }
2066
2067 cmd_buffer->state.subpass = subpass;
2068
2069 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2070 }
2071
2072 static VkResult
2073 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2074 struct radv_render_pass *pass,
2075 const VkRenderPassBeginInfo *info)
2076 {
2077 struct radv_cmd_state *state = &cmd_buffer->state;
2078
2079 if (pass->attachment_count == 0) {
2080 state->attachments = NULL;
2081 return VK_SUCCESS;
2082 }
2083
2084 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2085 pass->attachment_count *
2086 sizeof(state->attachments[0]),
2087 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2088 if (state->attachments == NULL) {
2089 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2090 return cmd_buffer->record_result;
2091 }
2092
2093 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2094 struct radv_render_pass_attachment *att = &pass->attachments[i];
2095 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2096 VkImageAspectFlags clear_aspects = 0;
2097
2098 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2099 /* color attachment */
2100 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2101 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2102 }
2103 } else {
2104 /* depthstencil attachment */
2105 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2106 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2107 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2108 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2109 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2110 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2111 }
2112 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2113 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2114 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2115 }
2116 }
2117
2118 state->attachments[i].pending_clear_aspects = clear_aspects;
2119 state->attachments[i].cleared_views = 0;
2120 if (clear_aspects && info) {
2121 assert(info->clearValueCount > i);
2122 state->attachments[i].clear_value = info->pClearValues[i];
2123 }
2124
2125 state->attachments[i].current_layout = att->initial_layout;
2126 }
2127
2128 return VK_SUCCESS;
2129 }
2130
2131 VkResult radv_AllocateCommandBuffers(
2132 VkDevice _device,
2133 const VkCommandBufferAllocateInfo *pAllocateInfo,
2134 VkCommandBuffer *pCommandBuffers)
2135 {
2136 RADV_FROM_HANDLE(radv_device, device, _device);
2137 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2138
2139 VkResult result = VK_SUCCESS;
2140 uint32_t i;
2141
2142 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2143
2144 if (!list_empty(&pool->free_cmd_buffers)) {
2145 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2146
2147 list_del(&cmd_buffer->pool_link);
2148 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2149
2150 result = radv_reset_cmd_buffer(cmd_buffer);
2151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2152 cmd_buffer->level = pAllocateInfo->level;
2153
2154 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2155 } else {
2156 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2157 &pCommandBuffers[i]);
2158 }
2159 if (result != VK_SUCCESS)
2160 break;
2161 }
2162
2163 if (result != VK_SUCCESS)
2164 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2165 i, pCommandBuffers);
2166
2167 return result;
2168 }
2169
2170 void radv_FreeCommandBuffers(
2171 VkDevice device,
2172 VkCommandPool commandPool,
2173 uint32_t commandBufferCount,
2174 const VkCommandBuffer *pCommandBuffers)
2175 {
2176 for (uint32_t i = 0; i < commandBufferCount; i++) {
2177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2178
2179 if (cmd_buffer) {
2180 if (cmd_buffer->pool) {
2181 list_del(&cmd_buffer->pool_link);
2182 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2183 } else
2184 radv_cmd_buffer_destroy(cmd_buffer);
2185
2186 }
2187 }
2188 }
2189
2190 VkResult radv_ResetCommandBuffer(
2191 VkCommandBuffer commandBuffer,
2192 VkCommandBufferResetFlags flags)
2193 {
2194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2195 return radv_reset_cmd_buffer(cmd_buffer);
2196 }
2197
2198 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2199 {
2200 struct radv_device *device = cmd_buffer->device;
2201 if (device->gfx_init) {
2202 uint64_t va = radv_buffer_get_va(device->gfx_init);
2203 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2204 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2205 radeon_emit(cmd_buffer->cs, va);
2206 radeon_emit(cmd_buffer->cs, va >> 32);
2207 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2208 } else
2209 si_init_config(cmd_buffer);
2210 }
2211
2212 VkResult radv_BeginCommandBuffer(
2213 VkCommandBuffer commandBuffer,
2214 const VkCommandBufferBeginInfo *pBeginInfo)
2215 {
2216 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2217 VkResult result;
2218
2219 result = radv_reset_cmd_buffer(cmd_buffer);
2220 if (result != VK_SUCCESS)
2221 return result;
2222
2223 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2224 cmd_buffer->state.last_primitive_reset_en = -1;
2225 cmd_buffer->usage_flags = pBeginInfo->flags;
2226
2227 /* setup initial configuration into command buffer */
2228 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2229 switch (cmd_buffer->queue_family_index) {
2230 case RADV_QUEUE_GENERAL:
2231 emit_gfx_buffer_state(cmd_buffer);
2232 break;
2233 case RADV_QUEUE_COMPUTE:
2234 si_init_compute(cmd_buffer);
2235 break;
2236 case RADV_QUEUE_TRANSFER:
2237 default:
2238 break;
2239 }
2240 }
2241
2242 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2243 assert(pBeginInfo->pInheritanceInfo);
2244 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2245 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2246
2247 struct radv_subpass *subpass =
2248 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2249
2250 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2251 if (result != VK_SUCCESS)
2252 return result;
2253
2254 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2255 }
2256
2257 if (unlikely(cmd_buffer->device->trace_bo))
2258 radv_cmd_buffer_trace_emit(cmd_buffer);
2259
2260 return result;
2261 }
2262
2263 void radv_CmdBindVertexBuffers(
2264 VkCommandBuffer commandBuffer,
2265 uint32_t firstBinding,
2266 uint32_t bindingCount,
2267 const VkBuffer* pBuffers,
2268 const VkDeviceSize* pOffsets)
2269 {
2270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2271 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2272 bool changed = false;
2273
2274 /* We have to defer setting up vertex buffer since we need the buffer
2275 * stride from the pipeline. */
2276
2277 assert(firstBinding + bindingCount <= MAX_VBS);
2278 for (uint32_t i = 0; i < bindingCount; i++) {
2279 uint32_t idx = firstBinding + i;
2280
2281 if (!changed &&
2282 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2283 vb[idx].offset != pOffsets[i])) {
2284 changed = true;
2285 }
2286
2287 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2288 vb[idx].offset = pOffsets[i];
2289
2290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2291 vb[idx].buffer->bo, 8);
2292 }
2293
2294 if (!changed) {
2295 /* No state changes. */
2296 return;
2297 }
2298
2299 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2300 }
2301
2302 void radv_CmdBindIndexBuffer(
2303 VkCommandBuffer commandBuffer,
2304 VkBuffer buffer,
2305 VkDeviceSize offset,
2306 VkIndexType indexType)
2307 {
2308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2309 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2310
2311 if (cmd_buffer->state.index_buffer == index_buffer &&
2312 cmd_buffer->state.index_offset == offset &&
2313 cmd_buffer->state.index_type == indexType) {
2314 /* No state changes. */
2315 return;
2316 }
2317
2318 cmd_buffer->state.index_buffer = index_buffer;
2319 cmd_buffer->state.index_offset = offset;
2320 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2321 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2322 cmd_buffer->state.index_va += index_buffer->offset + offset;
2323
2324 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2325 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2327 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2328 }
2329
2330
2331 static void
2332 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2333 struct radv_descriptor_set *set, unsigned idx)
2334 {
2335 struct radeon_winsys *ws = cmd_buffer->device->ws;
2336
2337 radv_set_descriptor_set(cmd_buffer, set, idx);
2338 if (!set)
2339 return;
2340
2341 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2342
2343 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2344 if (set->descriptors[j])
2345 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2346
2347 if(set->bo)
2348 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2349 }
2350
2351 void radv_CmdBindDescriptorSets(
2352 VkCommandBuffer commandBuffer,
2353 VkPipelineBindPoint pipelineBindPoint,
2354 VkPipelineLayout _layout,
2355 uint32_t firstSet,
2356 uint32_t descriptorSetCount,
2357 const VkDescriptorSet* pDescriptorSets,
2358 uint32_t dynamicOffsetCount,
2359 const uint32_t* pDynamicOffsets)
2360 {
2361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2362 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2363 unsigned dyn_idx = 0;
2364
2365 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2366 unsigned idx = i + firstSet;
2367 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2368 radv_bind_descriptor_set(cmd_buffer, set, idx);
2369
2370 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2371 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2372 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2373 assert(dyn_idx < dynamicOffsetCount);
2374
2375 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2376 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2377 dst[0] = va;
2378 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2379 dst[2] = range->size;
2380 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2381 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2382 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2383 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2384 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2385 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2386 cmd_buffer->push_constant_stages |=
2387 set->layout->dynamic_shader_stages;
2388 }
2389 }
2390 }
2391
2392 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2393 struct radv_descriptor_set *set,
2394 struct radv_descriptor_set_layout *layout)
2395 {
2396 set->size = layout->size;
2397 set->layout = layout;
2398
2399 if (cmd_buffer->push_descriptors.capacity < set->size) {
2400 size_t new_size = MAX2(set->size, 1024);
2401 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2402 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2403
2404 free(set->mapped_ptr);
2405 set->mapped_ptr = malloc(new_size);
2406
2407 if (!set->mapped_ptr) {
2408 cmd_buffer->push_descriptors.capacity = 0;
2409 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2410 return false;
2411 }
2412
2413 cmd_buffer->push_descriptors.capacity = new_size;
2414 }
2415
2416 return true;
2417 }
2418
2419 void radv_meta_push_descriptor_set(
2420 struct radv_cmd_buffer* cmd_buffer,
2421 VkPipelineBindPoint pipelineBindPoint,
2422 VkPipelineLayout _layout,
2423 uint32_t set,
2424 uint32_t descriptorWriteCount,
2425 const VkWriteDescriptorSet* pDescriptorWrites)
2426 {
2427 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2428 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2429 unsigned bo_offset;
2430
2431 assert(set == 0);
2432 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2433
2434 push_set->size = layout->set[set].layout->size;
2435 push_set->layout = layout->set[set].layout;
2436
2437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2438 &bo_offset,
2439 (void**) &push_set->mapped_ptr))
2440 return;
2441
2442 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2443 push_set->va += bo_offset;
2444
2445 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2446 radv_descriptor_set_to_handle(push_set),
2447 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2448
2449 radv_set_descriptor_set(cmd_buffer, push_set, set);
2450 }
2451
2452 void radv_CmdPushDescriptorSetKHR(
2453 VkCommandBuffer commandBuffer,
2454 VkPipelineBindPoint pipelineBindPoint,
2455 VkPipelineLayout _layout,
2456 uint32_t set,
2457 uint32_t descriptorWriteCount,
2458 const VkWriteDescriptorSet* pDescriptorWrites)
2459 {
2460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2461 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2462 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2463
2464 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2465
2466 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2467 return;
2468
2469 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2470 radv_descriptor_set_to_handle(push_set),
2471 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2472
2473 radv_set_descriptor_set(cmd_buffer, push_set, set);
2474 cmd_buffer->state.push_descriptors_dirty = true;
2475 }
2476
2477 void radv_CmdPushDescriptorSetWithTemplateKHR(
2478 VkCommandBuffer commandBuffer,
2479 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2480 VkPipelineLayout _layout,
2481 uint32_t set,
2482 const void* pData)
2483 {
2484 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2485 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2486 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2487
2488 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2489
2490 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2491 return;
2492
2493 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2494 descriptorUpdateTemplate, pData);
2495
2496 radv_set_descriptor_set(cmd_buffer, push_set, set);
2497 cmd_buffer->state.push_descriptors_dirty = true;
2498 }
2499
2500 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2501 VkPipelineLayout layout,
2502 VkShaderStageFlags stageFlags,
2503 uint32_t offset,
2504 uint32_t size,
2505 const void* pValues)
2506 {
2507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2508 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2509 cmd_buffer->push_constant_stages |= stageFlags;
2510 }
2511
2512 VkResult radv_EndCommandBuffer(
2513 VkCommandBuffer commandBuffer)
2514 {
2515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2516
2517 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2518 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2519 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2520 si_emit_cache_flush(cmd_buffer);
2521 }
2522
2523 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2524
2525 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2526 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2527
2528 return cmd_buffer->record_result;
2529 }
2530
2531 static void
2532 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2533 {
2534 struct radv_shader_variant *compute_shader;
2535 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2536 uint64_t va;
2537
2538 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2539 return;
2540
2541 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2542
2543 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2544 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2545
2546 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2547 cmd_buffer->cs, 16);
2548
2549 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2550 radeon_emit(cmd_buffer->cs, va >> 8);
2551 radeon_emit(cmd_buffer->cs, va >> 40);
2552
2553 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2554 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2555 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2556
2557
2558 cmd_buffer->compute_scratch_size_needed =
2559 MAX2(cmd_buffer->compute_scratch_size_needed,
2560 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2561
2562 /* change these once we have scratch support */
2563 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2564 S_00B860_WAVES(pipeline->max_waves) |
2565 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2566
2567 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2568 radeon_emit(cmd_buffer->cs,
2569 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2570 radeon_emit(cmd_buffer->cs,
2571 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2572 radeon_emit(cmd_buffer->cs,
2573 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2574
2575 assert(cmd_buffer->cs->cdw <= cdw_max);
2576
2577 if (unlikely(cmd_buffer->device->trace_bo))
2578 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2579 }
2580
2581 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2582 {
2583 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2584 }
2585
2586 void radv_CmdBindPipeline(
2587 VkCommandBuffer commandBuffer,
2588 VkPipelineBindPoint pipelineBindPoint,
2589 VkPipeline _pipeline)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2593
2594 switch (pipelineBindPoint) {
2595 case VK_PIPELINE_BIND_POINT_COMPUTE:
2596 if (cmd_buffer->state.compute_pipeline == pipeline)
2597 return;
2598 radv_mark_descriptor_sets_dirty(cmd_buffer);
2599
2600 cmd_buffer->state.compute_pipeline = pipeline;
2601 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2602 break;
2603 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2604 if (cmd_buffer->state.pipeline == pipeline)
2605 return;
2606 radv_mark_descriptor_sets_dirty(cmd_buffer);
2607
2608 cmd_buffer->state.pipeline = pipeline;
2609 if (!pipeline)
2610 break;
2611
2612 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2613 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2614
2615 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2616
2617 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2618 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2619 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2620 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2621
2622 if (radv_pipeline_has_tess(pipeline))
2623 cmd_buffer->tess_rings_needed = true;
2624
2625 if (radv_pipeline_has_gs(pipeline)) {
2626 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2627 AC_UD_SCRATCH_RING_OFFSETS);
2628 if (cmd_buffer->ring_offsets_idx == -1)
2629 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2630 else if (loc->sgpr_idx != -1)
2631 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2632 }
2633 break;
2634 default:
2635 assert(!"invalid bind point");
2636 break;
2637 }
2638 }
2639
2640 void radv_CmdSetViewport(
2641 VkCommandBuffer commandBuffer,
2642 uint32_t firstViewport,
2643 uint32_t viewportCount,
2644 const VkViewport* pViewports)
2645 {
2646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2647 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2648
2649 assert(firstViewport < MAX_VIEWPORTS);
2650 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2651
2652 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2653 pViewports, viewportCount * sizeof(*pViewports));
2654
2655 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2656 }
2657
2658 void radv_CmdSetScissor(
2659 VkCommandBuffer commandBuffer,
2660 uint32_t firstScissor,
2661 uint32_t scissorCount,
2662 const VkRect2D* pScissors)
2663 {
2664 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2665 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2666
2667 assert(firstScissor < MAX_SCISSORS);
2668 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2669
2670 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2671 pScissors, scissorCount * sizeof(*pScissors));
2672 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2673 }
2674
2675 void radv_CmdSetLineWidth(
2676 VkCommandBuffer commandBuffer,
2677 float lineWidth)
2678 {
2679 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2680 cmd_buffer->state.dynamic.line_width = lineWidth;
2681 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2682 }
2683
2684 void radv_CmdSetDepthBias(
2685 VkCommandBuffer commandBuffer,
2686 float depthBiasConstantFactor,
2687 float depthBiasClamp,
2688 float depthBiasSlopeFactor)
2689 {
2690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2691
2692 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2693 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2694 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2695
2696 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2697 }
2698
2699 void radv_CmdSetBlendConstants(
2700 VkCommandBuffer commandBuffer,
2701 const float blendConstants[4])
2702 {
2703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704
2705 memcpy(cmd_buffer->state.dynamic.blend_constants,
2706 blendConstants, sizeof(float) * 4);
2707
2708 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2709 }
2710
2711 void radv_CmdSetDepthBounds(
2712 VkCommandBuffer commandBuffer,
2713 float minDepthBounds,
2714 float maxDepthBounds)
2715 {
2716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2717
2718 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2719 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2720
2721 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2722 }
2723
2724 void radv_CmdSetStencilCompareMask(
2725 VkCommandBuffer commandBuffer,
2726 VkStencilFaceFlags faceMask,
2727 uint32_t compareMask)
2728 {
2729 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730
2731 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2732 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2733 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2734 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2735
2736 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2737 }
2738
2739 void radv_CmdSetStencilWriteMask(
2740 VkCommandBuffer commandBuffer,
2741 VkStencilFaceFlags faceMask,
2742 uint32_t writeMask)
2743 {
2744 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2745
2746 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2747 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2748 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2749 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2750
2751 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2752 }
2753
2754 void radv_CmdSetStencilReference(
2755 VkCommandBuffer commandBuffer,
2756 VkStencilFaceFlags faceMask,
2757 uint32_t reference)
2758 {
2759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2760
2761 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2762 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2763 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2764 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2765
2766 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2767 }
2768
2769 void radv_CmdExecuteCommands(
2770 VkCommandBuffer commandBuffer,
2771 uint32_t commandBufferCount,
2772 const VkCommandBuffer* pCmdBuffers)
2773 {
2774 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2775
2776 assert(commandBufferCount > 0);
2777
2778 /* Emit pending flushes on primary prior to executing secondary */
2779 si_emit_cache_flush(primary);
2780
2781 for (uint32_t i = 0; i < commandBufferCount; i++) {
2782 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2783
2784 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2785 secondary->scratch_size_needed);
2786 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2787 secondary->compute_scratch_size_needed);
2788
2789 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2790 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2791 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2792 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2793 if (secondary->tess_rings_needed)
2794 primary->tess_rings_needed = true;
2795 if (secondary->sample_positions_needed)
2796 primary->sample_positions_needed = true;
2797
2798 if (secondary->ring_offsets_idx != -1) {
2799 if (primary->ring_offsets_idx == -1)
2800 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2801 else
2802 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2803 }
2804 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2805
2806
2807 /* When the secondary command buffer is compute only we don't
2808 * need to re-emit the current graphics pipeline.
2809 */
2810 if (secondary->state.emitted_pipeline) {
2811 primary->state.emitted_pipeline =
2812 secondary->state.emitted_pipeline;
2813 }
2814
2815 /* When the secondary command buffer is graphics only we don't
2816 * need to re-emit the current compute pipeline.
2817 */
2818 if (secondary->state.emitted_compute_pipeline) {
2819 primary->state.emitted_compute_pipeline =
2820 secondary->state.emitted_compute_pipeline;
2821 }
2822
2823 /* Only re-emit the draw packets when needed. */
2824 if (secondary->state.last_primitive_reset_en != -1) {
2825 primary->state.last_primitive_reset_en =
2826 secondary->state.last_primitive_reset_en;
2827 }
2828
2829 if (secondary->state.last_primitive_reset_index) {
2830 primary->state.last_primitive_reset_index =
2831 secondary->state.last_primitive_reset_index;
2832 }
2833
2834 if (secondary->state.last_ia_multi_vgt_param) {
2835 primary->state.last_ia_multi_vgt_param =
2836 secondary->state.last_ia_multi_vgt_param;
2837 }
2838 }
2839
2840 /* After executing commands from secondary buffers we have to dirty
2841 * some states.
2842 */
2843 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2844 RADV_CMD_DIRTY_INDEX_BUFFER |
2845 RADV_CMD_DIRTY_DYNAMIC_ALL;
2846 radv_mark_descriptor_sets_dirty(primary);
2847 }
2848
2849 VkResult radv_CreateCommandPool(
2850 VkDevice _device,
2851 const VkCommandPoolCreateInfo* pCreateInfo,
2852 const VkAllocationCallbacks* pAllocator,
2853 VkCommandPool* pCmdPool)
2854 {
2855 RADV_FROM_HANDLE(radv_device, device, _device);
2856 struct radv_cmd_pool *pool;
2857
2858 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2859 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2860 if (pool == NULL)
2861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2862
2863 if (pAllocator)
2864 pool->alloc = *pAllocator;
2865 else
2866 pool->alloc = device->alloc;
2867
2868 list_inithead(&pool->cmd_buffers);
2869 list_inithead(&pool->free_cmd_buffers);
2870
2871 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2872
2873 *pCmdPool = radv_cmd_pool_to_handle(pool);
2874
2875 return VK_SUCCESS;
2876
2877 }
2878
2879 void radv_DestroyCommandPool(
2880 VkDevice _device,
2881 VkCommandPool commandPool,
2882 const VkAllocationCallbacks* pAllocator)
2883 {
2884 RADV_FROM_HANDLE(radv_device, device, _device);
2885 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2886
2887 if (!pool)
2888 return;
2889
2890 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2891 &pool->cmd_buffers, pool_link) {
2892 radv_cmd_buffer_destroy(cmd_buffer);
2893 }
2894
2895 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2896 &pool->free_cmd_buffers, pool_link) {
2897 radv_cmd_buffer_destroy(cmd_buffer);
2898 }
2899
2900 vk_free2(&device->alloc, pAllocator, pool);
2901 }
2902
2903 VkResult radv_ResetCommandPool(
2904 VkDevice device,
2905 VkCommandPool commandPool,
2906 VkCommandPoolResetFlags flags)
2907 {
2908 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2909 VkResult result;
2910
2911 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2912 &pool->cmd_buffers, pool_link) {
2913 result = radv_reset_cmd_buffer(cmd_buffer);
2914 if (result != VK_SUCCESS)
2915 return result;
2916 }
2917
2918 return VK_SUCCESS;
2919 }
2920
2921 void radv_TrimCommandPoolKHR(
2922 VkDevice device,
2923 VkCommandPool commandPool,
2924 VkCommandPoolTrimFlagsKHR flags)
2925 {
2926 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2927
2928 if (!pool)
2929 return;
2930
2931 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2932 &pool->free_cmd_buffers, pool_link) {
2933 radv_cmd_buffer_destroy(cmd_buffer);
2934 }
2935 }
2936
2937 void radv_CmdBeginRenderPass(
2938 VkCommandBuffer commandBuffer,
2939 const VkRenderPassBeginInfo* pRenderPassBegin,
2940 VkSubpassContents contents)
2941 {
2942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2943 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2944 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2945
2946 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2947 cmd_buffer->cs, 2048);
2948 MAYBE_UNUSED VkResult result;
2949
2950 cmd_buffer->state.framebuffer = framebuffer;
2951 cmd_buffer->state.pass = pass;
2952 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2953
2954 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2955 if (result != VK_SUCCESS)
2956 return;
2957
2958 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2959 assert(cmd_buffer->cs->cdw <= cdw_max);
2960
2961 radv_cmd_buffer_clear_subpass(cmd_buffer);
2962 }
2963
2964 void radv_CmdNextSubpass(
2965 VkCommandBuffer commandBuffer,
2966 VkSubpassContents contents)
2967 {
2968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2969
2970 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2971
2972 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2973 2048);
2974
2975 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2976 radv_cmd_buffer_clear_subpass(cmd_buffer);
2977 }
2978
2979 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2980 {
2981 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2982 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2983 if (!pipeline->shaders[stage])
2984 continue;
2985 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2986 if (loc->sgpr_idx == -1)
2987 continue;
2988 uint32_t base_reg = pipeline->user_data_0[stage];
2989 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2990
2991 }
2992 if (pipeline->gs_copy_shader) {
2993 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2994 if (loc->sgpr_idx != -1) {
2995 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2996 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2997 }
2998 }
2999 }
3000
3001 static void
3002 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3003 uint32_t vertex_count)
3004 {
3005 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3006 radeon_emit(cmd_buffer->cs, vertex_count);
3007 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3008 S_0287F0_USE_OPAQUE(0));
3009 }
3010
3011 static void
3012 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3013 uint64_t index_va,
3014 uint32_t index_count)
3015 {
3016 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3017 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3018 radeon_emit(cmd_buffer->cs, index_va);
3019 radeon_emit(cmd_buffer->cs, index_va >> 32);
3020 radeon_emit(cmd_buffer->cs, index_count);
3021 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3022 }
3023
3024 static void
3025 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3026 bool indexed,
3027 uint32_t draw_count,
3028 uint64_t count_va,
3029 uint32_t stride)
3030 {
3031 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3032 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3033 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3034 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3035 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3036 assert(base_reg);
3037
3038 if (draw_count == 1 && !count_va && !draw_id_enable) {
3039 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3040 PKT3_DRAW_INDIRECT, 3, false));
3041 radeon_emit(cs, 0);
3042 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3043 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3044 radeon_emit(cs, di_src_sel);
3045 } else {
3046 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3047 PKT3_DRAW_INDIRECT_MULTI,
3048 8, false));
3049 radeon_emit(cs, 0);
3050 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3051 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3052 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3053 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3054 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3055 radeon_emit(cs, draw_count); /* count */
3056 radeon_emit(cs, count_va); /* count_addr */
3057 radeon_emit(cs, count_va >> 32);
3058 radeon_emit(cs, stride); /* stride */
3059 radeon_emit(cs, di_src_sel);
3060 }
3061 }
3062
3063 struct radv_draw_info {
3064 /**
3065 * Number of vertices.
3066 */
3067 uint32_t count;
3068
3069 /**
3070 * Index of the first vertex.
3071 */
3072 int32_t vertex_offset;
3073
3074 /**
3075 * First instance id.
3076 */
3077 uint32_t first_instance;
3078
3079 /**
3080 * Number of instances.
3081 */
3082 uint32_t instance_count;
3083
3084 /**
3085 * First index (indexed draws only).
3086 */
3087 uint32_t first_index;
3088
3089 /**
3090 * Whether it's an indexed draw.
3091 */
3092 bool indexed;
3093
3094 /**
3095 * Indirect draw parameters resource.
3096 */
3097 struct radv_buffer *indirect;
3098 uint64_t indirect_offset;
3099 uint32_t stride;
3100
3101 /**
3102 * Draw count parameters resource.
3103 */
3104 struct radv_buffer *count_buffer;
3105 uint64_t count_buffer_offset;
3106 };
3107
3108 static void
3109 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3110 const struct radv_draw_info *info)
3111 {
3112 struct radv_cmd_state *state = &cmd_buffer->state;
3113 struct radeon_winsys *ws = cmd_buffer->device->ws;
3114 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3115
3116 if (info->indirect) {
3117 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3118 uint64_t count_va = 0;
3119
3120 va += info->indirect->offset + info->indirect_offset;
3121
3122 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3123
3124 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3125 radeon_emit(cs, 1);
3126 radeon_emit(cs, va);
3127 radeon_emit(cs, va >> 32);
3128
3129 if (info->count_buffer) {
3130 count_va = radv_buffer_get_va(info->count_buffer->bo);
3131 count_va += info->count_buffer->offset +
3132 info->count_buffer_offset;
3133
3134 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3135 }
3136
3137 if (!state->subpass->view_mask) {
3138 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3139 info->indexed,
3140 info->count,
3141 count_va,
3142 info->stride);
3143 } else {
3144 unsigned i;
3145 for_each_bit(i, state->subpass->view_mask) {
3146 radv_emit_view_index(cmd_buffer, i);
3147
3148 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3149 info->indexed,
3150 info->count,
3151 count_va,
3152 info->stride);
3153 }
3154 }
3155 } else {
3156 assert(state->pipeline->graphics.vtx_base_sgpr);
3157 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3158 state->pipeline->graphics.vtx_emit_num);
3159 radeon_emit(cs, info->vertex_offset);
3160 radeon_emit(cs, info->first_instance);
3161 if (state->pipeline->graphics.vtx_emit_num == 3)
3162 radeon_emit(cs, 0);
3163
3164 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3165 radeon_emit(cs, info->instance_count);
3166
3167 if (info->indexed) {
3168 int index_size = state->index_type ? 4 : 2;
3169 uint64_t index_va;
3170
3171 index_va = state->index_va;
3172 index_va += info->first_index * index_size;
3173
3174 if (!state->subpass->view_mask) {
3175 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3176 index_va,
3177 info->count);
3178 } else {
3179 unsigned i;
3180 for_each_bit(i, state->subpass->view_mask) {
3181 radv_emit_view_index(cmd_buffer, i);
3182
3183 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3184 index_va,
3185 info->count);
3186 }
3187 }
3188 } else {
3189 if (!state->subpass->view_mask) {
3190 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3191 } else {
3192 unsigned i;
3193 for_each_bit(i, state->subpass->view_mask) {
3194 radv_emit_view_index(cmd_buffer, i);
3195
3196 radv_cs_emit_draw_packet(cmd_buffer,
3197 info->count);
3198 }
3199 }
3200 }
3201 }
3202 }
3203
3204 static void
3205 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3206 const struct radv_draw_info *info)
3207 {
3208 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3209 radv_emit_graphics_pipeline(cmd_buffer);
3210
3211 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3212 radv_emit_framebuffer_state(cmd_buffer);
3213
3214 if (info->indexed) {
3215 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3216 radv_emit_index_buffer(cmd_buffer);
3217 } else {
3218 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3219 * so the state must be re-emitted before the next indexed
3220 * draw.
3221 */
3222 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3223 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3224 }
3225
3226 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3227
3228 radv_emit_draw_registers(cmd_buffer, info->indexed,
3229 info->instance_count > 1, info->indirect,
3230 info->indirect ? 0 : info->count);
3231 }
3232
3233 static void
3234 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3235 const struct radv_draw_info *info)
3236 {
3237 bool pipeline_is_dirty =
3238 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3239 cmd_buffer->state.pipeline &&
3240 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3241
3242 MAYBE_UNUSED unsigned cdw_max =
3243 radeon_check_space(cmd_buffer->device->ws,
3244 cmd_buffer->cs, 4096);
3245
3246 /* Use optimal packet order based on whether we need to sync the
3247 * pipeline.
3248 */
3249 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3250 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3251 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3252 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3253 /* If we have to wait for idle, set all states first, so that
3254 * all SET packets are processed in parallel with previous draw
3255 * calls. Then upload descriptors, set shader pointers, and
3256 * draw, and prefetch at the end. This ensures that the time
3257 * the CUs are idle is very short. (there are only SET_SH
3258 * packets between the wait and the draw)
3259 */
3260 radv_emit_all_graphics_states(cmd_buffer, info);
3261 si_emit_cache_flush(cmd_buffer);
3262 /* <-- CUs are idle here --> */
3263
3264 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3265 return;
3266
3267 radv_emit_draw_packets(cmd_buffer, info);
3268 /* <-- CUs are busy here --> */
3269
3270 /* Start prefetches after the draw has been started. Both will
3271 * run in parallel, but starting the draw first is more
3272 * important.
3273 */
3274 if (pipeline_is_dirty) {
3275 radv_emit_prefetch(cmd_buffer,
3276 cmd_buffer->state.pipeline);
3277 }
3278 } else {
3279 /* If we don't wait for idle, start prefetches first, then set
3280 * states, and draw at the end.
3281 */
3282 si_emit_cache_flush(cmd_buffer);
3283
3284 if (pipeline_is_dirty) {
3285 radv_emit_prefetch(cmd_buffer,
3286 cmd_buffer->state.pipeline);
3287 }
3288
3289 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3290 return;
3291
3292 radv_emit_all_graphics_states(cmd_buffer, info);
3293 radv_emit_draw_packets(cmd_buffer, info);
3294 }
3295
3296 assert(cmd_buffer->cs->cdw <= cdw_max);
3297 radv_cmd_buffer_after_draw(cmd_buffer);
3298 }
3299
3300 void radv_CmdDraw(
3301 VkCommandBuffer commandBuffer,
3302 uint32_t vertexCount,
3303 uint32_t instanceCount,
3304 uint32_t firstVertex,
3305 uint32_t firstInstance)
3306 {
3307 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3308 struct radv_draw_info info = {};
3309
3310 info.count = vertexCount;
3311 info.instance_count = instanceCount;
3312 info.first_instance = firstInstance;
3313 info.vertex_offset = firstVertex;
3314
3315 radv_draw(cmd_buffer, &info);
3316 }
3317
3318 void radv_CmdDrawIndexed(
3319 VkCommandBuffer commandBuffer,
3320 uint32_t indexCount,
3321 uint32_t instanceCount,
3322 uint32_t firstIndex,
3323 int32_t vertexOffset,
3324 uint32_t firstInstance)
3325 {
3326 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3327 struct radv_draw_info info = {};
3328
3329 info.indexed = true;
3330 info.count = indexCount;
3331 info.instance_count = instanceCount;
3332 info.first_index = firstIndex;
3333 info.vertex_offset = vertexOffset;
3334 info.first_instance = firstInstance;
3335
3336 radv_draw(cmd_buffer, &info);
3337 }
3338
3339 void radv_CmdDrawIndirect(
3340 VkCommandBuffer commandBuffer,
3341 VkBuffer _buffer,
3342 VkDeviceSize offset,
3343 uint32_t drawCount,
3344 uint32_t stride)
3345 {
3346 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3347 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3348 struct radv_draw_info info = {};
3349
3350 info.count = drawCount;
3351 info.indirect = buffer;
3352 info.indirect_offset = offset;
3353 info.stride = stride;
3354
3355 radv_draw(cmd_buffer, &info);
3356 }
3357
3358 void radv_CmdDrawIndexedIndirect(
3359 VkCommandBuffer commandBuffer,
3360 VkBuffer _buffer,
3361 VkDeviceSize offset,
3362 uint32_t drawCount,
3363 uint32_t stride)
3364 {
3365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3366 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3367 struct radv_draw_info info = {};
3368
3369 info.indexed = true;
3370 info.count = drawCount;
3371 info.indirect = buffer;
3372 info.indirect_offset = offset;
3373 info.stride = stride;
3374
3375 radv_draw(cmd_buffer, &info);
3376 }
3377
3378 void radv_CmdDrawIndirectCountAMD(
3379 VkCommandBuffer commandBuffer,
3380 VkBuffer _buffer,
3381 VkDeviceSize offset,
3382 VkBuffer _countBuffer,
3383 VkDeviceSize countBufferOffset,
3384 uint32_t maxDrawCount,
3385 uint32_t stride)
3386 {
3387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3388 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3389 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3390 struct radv_draw_info info = {};
3391
3392 info.count = maxDrawCount;
3393 info.indirect = buffer;
3394 info.indirect_offset = offset;
3395 info.count_buffer = count_buffer;
3396 info.count_buffer_offset = countBufferOffset;
3397 info.stride = stride;
3398
3399 radv_draw(cmd_buffer, &info);
3400 }
3401
3402 void radv_CmdDrawIndexedIndirectCountAMD(
3403 VkCommandBuffer commandBuffer,
3404 VkBuffer _buffer,
3405 VkDeviceSize offset,
3406 VkBuffer _countBuffer,
3407 VkDeviceSize countBufferOffset,
3408 uint32_t maxDrawCount,
3409 uint32_t stride)
3410 {
3411 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3412 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3413 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3414 struct radv_draw_info info = {};
3415
3416 info.indexed = true;
3417 info.count = maxDrawCount;
3418 info.indirect = buffer;
3419 info.indirect_offset = offset;
3420 info.count_buffer = count_buffer;
3421 info.count_buffer_offset = countBufferOffset;
3422 info.stride = stride;
3423
3424 radv_draw(cmd_buffer, &info);
3425 }
3426
3427 struct radv_dispatch_info {
3428 /**
3429 * Determine the layout of the grid (in block units) to be used.
3430 */
3431 uint32_t blocks[3];
3432
3433 /**
3434 * Whether it's an unaligned compute dispatch.
3435 */
3436 bool unaligned;
3437
3438 /**
3439 * Indirect compute parameters resource.
3440 */
3441 struct radv_buffer *indirect;
3442 uint64_t indirect_offset;
3443 };
3444
3445 static void
3446 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3447 const struct radv_dispatch_info *info)
3448 {
3449 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3450 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3451 struct radeon_winsys *ws = cmd_buffer->device->ws;
3452 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3453 struct ac_userdata_info *loc;
3454 unsigned dispatch_initiator;
3455 uint8_t grid_used;
3456
3457 grid_used = compute_shader->info.info.cs.grid_components_used;
3458
3459 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3460 AC_UD_CS_GRID_SIZE);
3461
3462 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3463
3464 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3465 S_00B800_FORCE_START_AT_000(1);
3466
3467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3468 /* If the KMD allows it (there is a KMD hw register for it),
3469 * allow launching waves out-of-order.
3470 */
3471 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3472 }
3473
3474 if (info->indirect) {
3475 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3476
3477 va += info->indirect->offset + info->indirect_offset;
3478
3479 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3480
3481 if (loc->sgpr_idx != -1) {
3482 for (unsigned i = 0; i < grid_used; ++i) {
3483 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3484 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3485 COPY_DATA_DST_SEL(COPY_DATA_REG));
3486 radeon_emit(cs, (va + 4 * i));
3487 radeon_emit(cs, (va + 4 * i) >> 32);
3488 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3489 + loc->sgpr_idx * 4) >> 2) + i);
3490 radeon_emit(cs, 0);
3491 }
3492 }
3493
3494 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3495 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3496 PKT3_SHADER_TYPE_S(1));
3497 radeon_emit(cs, va);
3498 radeon_emit(cs, va >> 32);
3499 radeon_emit(cs, dispatch_initiator);
3500 } else {
3501 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3502 PKT3_SHADER_TYPE_S(1));
3503 radeon_emit(cs, 1);
3504 radeon_emit(cs, va);
3505 radeon_emit(cs, va >> 32);
3506
3507 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3508 PKT3_SHADER_TYPE_S(1));
3509 radeon_emit(cs, 0);
3510 radeon_emit(cs, dispatch_initiator);
3511 }
3512 } else {
3513 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3514
3515 if (info->unaligned) {
3516 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3517 unsigned remainder[3];
3518
3519 /* If aligned, these should be an entire block size,
3520 * not 0.
3521 */
3522 remainder[0] = blocks[0] + cs_block_size[0] -
3523 align_u32_npot(blocks[0], cs_block_size[0]);
3524 remainder[1] = blocks[1] + cs_block_size[1] -
3525 align_u32_npot(blocks[1], cs_block_size[1]);
3526 remainder[2] = blocks[2] + cs_block_size[2] -
3527 align_u32_npot(blocks[2], cs_block_size[2]);
3528
3529 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3530 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3531 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3532
3533 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3534 radeon_emit(cs,
3535 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3536 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3537 radeon_emit(cs,
3538 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3539 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3540 radeon_emit(cs,
3541 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3542 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3543
3544 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3545 }
3546
3547 if (loc->sgpr_idx != -1) {
3548 assert(!loc->indirect);
3549 assert(loc->num_sgprs == grid_used);
3550
3551 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3552 loc->sgpr_idx * 4, grid_used);
3553 radeon_emit(cs, blocks[0]);
3554 if (grid_used > 1)
3555 radeon_emit(cs, blocks[1]);
3556 if (grid_used > 2)
3557 radeon_emit(cs, blocks[2]);
3558 }
3559
3560 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3561 PKT3_SHADER_TYPE_S(1));
3562 radeon_emit(cs, blocks[0]);
3563 radeon_emit(cs, blocks[1]);
3564 radeon_emit(cs, blocks[2]);
3565 radeon_emit(cs, dispatch_initiator);
3566 }
3567
3568 assert(cmd_buffer->cs->cdw <= cdw_max);
3569 }
3570
3571 static void
3572 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3573 {
3574 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3575 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3576 VK_SHADER_STAGE_COMPUTE_BIT);
3577 }
3578
3579 static void
3580 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3581 const struct radv_dispatch_info *info)
3582 {
3583 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3584 bool pipeline_is_dirty = pipeline &&
3585 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3586
3587 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3588 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3589 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3590 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3591 /* If we have to wait for idle, set all states first, so that
3592 * all SET packets are processed in parallel with previous draw
3593 * calls. Then upload descriptors, set shader pointers, and
3594 * dispatch, and prefetch at the end. This ensures that the
3595 * time the CUs are idle is very short. (there are only SET_SH
3596 * packets between the wait and the draw)
3597 */
3598 radv_emit_compute_pipeline(cmd_buffer);
3599 si_emit_cache_flush(cmd_buffer);
3600 /* <-- CUs are idle here --> */
3601
3602 radv_upload_compute_shader_descriptors(cmd_buffer);
3603
3604 radv_emit_dispatch_packets(cmd_buffer, info);
3605 /* <-- CUs are busy here --> */
3606
3607 /* Start prefetches after the dispatch has been started. Both
3608 * will run in parallel, but starting the dispatch first is
3609 * more important.
3610 */
3611 if (pipeline_is_dirty) {
3612 radv_emit_shader_prefetch(cmd_buffer,
3613 pipeline->shaders[MESA_SHADER_COMPUTE]);
3614 }
3615 } else {
3616 /* If we don't wait for idle, start prefetches first, then set
3617 * states, and dispatch at the end.
3618 */
3619 si_emit_cache_flush(cmd_buffer);
3620
3621 if (pipeline_is_dirty) {
3622 radv_emit_shader_prefetch(cmd_buffer,
3623 pipeline->shaders[MESA_SHADER_COMPUTE]);
3624 }
3625
3626 radv_upload_compute_shader_descriptors(cmd_buffer);
3627
3628 radv_emit_compute_pipeline(cmd_buffer);
3629 radv_emit_dispatch_packets(cmd_buffer, info);
3630 }
3631
3632 radv_cmd_buffer_after_draw(cmd_buffer);
3633 }
3634
3635 void radv_CmdDispatch(
3636 VkCommandBuffer commandBuffer,
3637 uint32_t x,
3638 uint32_t y,
3639 uint32_t z)
3640 {
3641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3642 struct radv_dispatch_info info = {};
3643
3644 info.blocks[0] = x;
3645 info.blocks[1] = y;
3646 info.blocks[2] = z;
3647
3648 radv_dispatch(cmd_buffer, &info);
3649 }
3650
3651 void radv_CmdDispatchIndirect(
3652 VkCommandBuffer commandBuffer,
3653 VkBuffer _buffer,
3654 VkDeviceSize offset)
3655 {
3656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3657 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3658 struct radv_dispatch_info info = {};
3659
3660 info.indirect = buffer;
3661 info.indirect_offset = offset;
3662
3663 radv_dispatch(cmd_buffer, &info);
3664 }
3665
3666 void radv_unaligned_dispatch(
3667 struct radv_cmd_buffer *cmd_buffer,
3668 uint32_t x,
3669 uint32_t y,
3670 uint32_t z)
3671 {
3672 struct radv_dispatch_info info = {};
3673
3674 info.blocks[0] = x;
3675 info.blocks[1] = y;
3676 info.blocks[2] = z;
3677 info.unaligned = 1;
3678
3679 radv_dispatch(cmd_buffer, &info);
3680 }
3681
3682 void radv_CmdEndRenderPass(
3683 VkCommandBuffer commandBuffer)
3684 {
3685 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3686
3687 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3688
3689 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3690
3691 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3692 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3693 radv_handle_subpass_image_transition(cmd_buffer,
3694 (VkAttachmentReference){i, layout});
3695 }
3696
3697 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3698
3699 cmd_buffer->state.pass = NULL;
3700 cmd_buffer->state.subpass = NULL;
3701 cmd_buffer->state.attachments = NULL;
3702 cmd_buffer->state.framebuffer = NULL;
3703 }
3704
3705 /*
3706 * For HTILE we have the following interesting clear words:
3707 * 0x0000030f: Uncompressed.
3708 * 0xfffffff0: Clear depth to 1.0
3709 * 0x00000000: Clear depth to 0.0
3710 */
3711 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3712 struct radv_image *image,
3713 const VkImageSubresourceRange *range,
3714 uint32_t clear_word)
3715 {
3716 assert(range->baseMipLevel == 0);
3717 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3718 unsigned layer_count = radv_get_layerCount(image, range);
3719 uint64_t size = image->surface.htile_slice_size * layer_count;
3720 uint64_t offset = image->offset + image->htile_offset +
3721 image->surface.htile_slice_size * range->baseArrayLayer;
3722 struct radv_cmd_state *state = &cmd_buffer->state;
3723
3724 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3726
3727 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3728 size, clear_word);
3729
3730 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3731 }
3732
3733 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3734 struct radv_image *image,
3735 VkImageLayout src_layout,
3736 VkImageLayout dst_layout,
3737 unsigned src_queue_mask,
3738 unsigned dst_queue_mask,
3739 const VkImageSubresourceRange *range,
3740 VkImageAspectFlags pending_clears)
3741 {
3742 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3743 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3744 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3745 cmd_buffer->state.render_area.extent.width == image->info.width &&
3746 cmd_buffer->state.render_area.extent.height == image->info.height) {
3747 /* The clear will initialize htile. */
3748 return;
3749 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3750 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3751 /* TODO: merge with the clear if applicable */
3752 radv_initialize_htile(cmd_buffer, image, range, 0);
3753 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3754 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3755 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3756 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3757 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3758 VkImageSubresourceRange local_range = *range;
3759 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3760 local_range.baseMipLevel = 0;
3761 local_range.levelCount = 1;
3762
3763 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3764 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3765
3766 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3767
3768 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3769 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3770 }
3771 }
3772
3773 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3774 struct radv_image *image, uint32_t value)
3775 {
3776 struct radv_cmd_state *state = &cmd_buffer->state;
3777
3778 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3779 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3780
3781 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3782 image->offset + image->cmask.offset,
3783 image->cmask.size, value);
3784
3785 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3786 }
3787
3788 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3789 struct radv_image *image,
3790 VkImageLayout src_layout,
3791 VkImageLayout dst_layout,
3792 unsigned src_queue_mask,
3793 unsigned dst_queue_mask,
3794 const VkImageSubresourceRange *range)
3795 {
3796 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3797 if (image->fmask.size)
3798 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3799 else
3800 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3801 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3802 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3803 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3804 }
3805 }
3806
3807 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3808 struct radv_image *image, uint32_t value)
3809 {
3810 struct radv_cmd_state *state = &cmd_buffer->state;
3811
3812 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3813 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3814
3815 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3816 image->offset + image->dcc_offset,
3817 image->surface.dcc_size, value);
3818
3819 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3820 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3821 }
3822
3823 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3824 struct radv_image *image,
3825 VkImageLayout src_layout,
3826 VkImageLayout dst_layout,
3827 unsigned src_queue_mask,
3828 unsigned dst_queue_mask,
3829 const VkImageSubresourceRange *range)
3830 {
3831 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3832 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3833 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3834 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3835 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3836 }
3837 }
3838
3839 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3840 struct radv_image *image,
3841 VkImageLayout src_layout,
3842 VkImageLayout dst_layout,
3843 uint32_t src_family,
3844 uint32_t dst_family,
3845 const VkImageSubresourceRange *range,
3846 VkImageAspectFlags pending_clears)
3847 {
3848 if (image->exclusive && src_family != dst_family) {
3849 /* This is an acquire or a release operation and there will be
3850 * a corresponding release/acquire. Do the transition in the
3851 * most flexible queue. */
3852
3853 assert(src_family == cmd_buffer->queue_family_index ||
3854 dst_family == cmd_buffer->queue_family_index);
3855
3856 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3857 return;
3858
3859 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3860 (src_family == RADV_QUEUE_GENERAL ||
3861 dst_family == RADV_QUEUE_GENERAL))
3862 return;
3863 }
3864
3865 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3866 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3867
3868 if (image->surface.htile_size)
3869 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3870 dst_layout, src_queue_mask,
3871 dst_queue_mask, range,
3872 pending_clears);
3873
3874 if (image->cmask.size || image->fmask.size)
3875 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3876 dst_layout, src_queue_mask,
3877 dst_queue_mask, range);
3878
3879 if (image->surface.dcc_size)
3880 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3881 dst_layout, src_queue_mask,
3882 dst_queue_mask, range);
3883 }
3884
3885 void radv_CmdPipelineBarrier(
3886 VkCommandBuffer commandBuffer,
3887 VkPipelineStageFlags srcStageMask,
3888 VkPipelineStageFlags destStageMask,
3889 VkBool32 byRegion,
3890 uint32_t memoryBarrierCount,
3891 const VkMemoryBarrier* pMemoryBarriers,
3892 uint32_t bufferMemoryBarrierCount,
3893 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3894 uint32_t imageMemoryBarrierCount,
3895 const VkImageMemoryBarrier* pImageMemoryBarriers)
3896 {
3897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3898 enum radv_cmd_flush_bits src_flush_bits = 0;
3899 enum radv_cmd_flush_bits dst_flush_bits = 0;
3900
3901 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3902 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3903 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3904 NULL);
3905 }
3906
3907 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3908 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3909 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3910 NULL);
3911 }
3912
3913 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3914 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3915 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3916 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3917 image);
3918 }
3919
3920 radv_stage_flush(cmd_buffer, srcStageMask);
3921 cmd_buffer->state.flush_bits |= src_flush_bits;
3922
3923 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3924 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3925 radv_handle_image_transition(cmd_buffer, image,
3926 pImageMemoryBarriers[i].oldLayout,
3927 pImageMemoryBarriers[i].newLayout,
3928 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3929 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3930 &pImageMemoryBarriers[i].subresourceRange,
3931 0);
3932 }
3933
3934 cmd_buffer->state.flush_bits |= dst_flush_bits;
3935 }
3936
3937
3938 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3939 struct radv_event *event,
3940 VkPipelineStageFlags stageMask,
3941 unsigned value)
3942 {
3943 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3944 uint64_t va = radv_buffer_get_va(event->bo);
3945
3946 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3947
3948 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3949
3950 /* TODO: this is overkill. Probably should figure something out from
3951 * the stage mask. */
3952
3953 si_cs_emit_write_event_eop(cs,
3954 cmd_buffer->state.predicating,
3955 cmd_buffer->device->physical_device->rad_info.chip_class,
3956 false,
3957 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3958 1, va, 2, value);
3959
3960 assert(cmd_buffer->cs->cdw <= cdw_max);
3961 }
3962
3963 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3964 VkEvent _event,
3965 VkPipelineStageFlags stageMask)
3966 {
3967 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3968 RADV_FROM_HANDLE(radv_event, event, _event);
3969
3970 write_event(cmd_buffer, event, stageMask, 1);
3971 }
3972
3973 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3974 VkEvent _event,
3975 VkPipelineStageFlags stageMask)
3976 {
3977 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3978 RADV_FROM_HANDLE(radv_event, event, _event);
3979
3980 write_event(cmd_buffer, event, stageMask, 0);
3981 }
3982
3983 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3984 uint32_t eventCount,
3985 const VkEvent* pEvents,
3986 VkPipelineStageFlags srcStageMask,
3987 VkPipelineStageFlags dstStageMask,
3988 uint32_t memoryBarrierCount,
3989 const VkMemoryBarrier* pMemoryBarriers,
3990 uint32_t bufferMemoryBarrierCount,
3991 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3992 uint32_t imageMemoryBarrierCount,
3993 const VkImageMemoryBarrier* pImageMemoryBarriers)
3994 {
3995 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3996 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3997
3998 for (unsigned i = 0; i < eventCount; ++i) {
3999 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4000 uint64_t va = radv_buffer_get_va(event->bo);
4001
4002 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4003
4004 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4005
4006 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4007 assert(cmd_buffer->cs->cdw <= cdw_max);
4008 }
4009
4010
4011 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4012 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4013
4014 radv_handle_image_transition(cmd_buffer, image,
4015 pImageMemoryBarriers[i].oldLayout,
4016 pImageMemoryBarriers[i].newLayout,
4017 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4018 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4019 &pImageMemoryBarriers[i].subresourceRange,
4020 0);
4021 }
4022
4023 /* TODO: figure out how to do memory barriers without waiting */
4024 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4025 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4026 RADV_CMD_FLAG_INV_VMEM_L1 |
4027 RADV_CMD_FLAG_INV_SMEM_L1;
4028 }