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radv: Correctly detect changed shaders for vertex descriptors.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 if (stage == MESA_SHADER_VERTEX) {
497 if (pipeline->shaders[MESA_SHADER_VERTEX])
498 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
499 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
500 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
501 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
502 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
503 } else if (stage == MESA_SHADER_TESS_EVAL) {
504 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
505 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
506 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
507 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
508 }
509 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
510 }
511
512 static void
513 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
514 struct radv_pipeline *pipeline,
515 gl_shader_stage stage,
516 int idx, uint64_t va)
517 {
518 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
519 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
520 if (loc->sgpr_idx == -1)
521 return;
522 assert(loc->num_sgprs == 2);
523 assert(!loc->indirect);
524 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
525 radeon_emit(cmd_buffer->cs, va);
526 radeon_emit(cmd_buffer->cs, va >> 32);
527 }
528
529 static void
530 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 int num_samples = pipeline->graphics.ms.num_samples;
534 struct radv_multisample_state *ms = &pipeline->graphics.ms;
535 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
536
537 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
538 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
539 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
540
541 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
542 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
543
544 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
545 return;
546
547 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
548 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
549 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
550
551 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
552
553 /* GFX9: Flush DFSM when the AA mode changes. */
554 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
555 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
556 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
557 }
558 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
559 uint32_t offset;
560 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
561 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
562 if (loc->sgpr_idx == -1)
563 return;
564 assert(loc->num_sgprs == 1);
565 assert(!loc->indirect);
566 switch (num_samples) {
567 default:
568 offset = 0;
569 break;
570 case 2:
571 offset = 1;
572 break;
573 case 4:
574 offset = 3;
575 break;
576 case 8:
577 offset = 7;
578 break;
579 case 16:
580 offset = 15;
581 break;
582 }
583
584 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
585 cmd_buffer->sample_positions_needed = true;
586 }
587 }
588
589 static void
590 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline)
592 {
593 struct radv_raster_state *raster = &pipeline->graphics.raster;
594
595 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
596 raster->pa_cl_clip_cntl);
597 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
598 raster->spi_interp_control);
599 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
600 raster->pa_su_vtx_cntl);
601 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
602 raster->pa_su_sc_mode_cntl);
603 }
604
605 static void
606 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_shader_variant *shader)
608 {
609 struct radeon_winsys *ws = cmd_buffer->device->ws;
610 struct radeon_winsys_cs *cs = cmd_buffer->cs;
611 uint64_t va;
612
613 if (!shader)
614 return;
615
616 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
617
618 ws->cs_add_buffer(cs, shader->bo, 8);
619 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
620 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
621 }
622
623 static void
624 radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 radv_emit_shader_prefetch(cmd_buffer,
628 pipeline->shaders[MESA_SHADER_VERTEX]);
629 radv_emit_shader_prefetch(cmd_buffer,
630 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
631 radv_emit_shader_prefetch(cmd_buffer,
632 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
633 radv_emit_shader_prefetch(cmd_buffer,
634 pipeline->shaders[MESA_SHADER_GEOMETRY]);
635 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
636 radv_emit_shader_prefetch(cmd_buffer,
637 pipeline->shaders[MESA_SHADER_FRAGMENT]);
638 }
639
640 static void
641 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
642 struct radv_pipeline *pipeline,
643 struct radv_shader_variant *shader,
644 struct ac_vs_output_info *outinfo)
645 {
646 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
647 unsigned export_count;
648
649 export_count = MAX2(1, outinfo->param_exports);
650 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
651 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
652
653 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
654 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
655 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
656 V_02870C_SPI_SHADER_4COMP :
657 V_02870C_SPI_SHADER_NONE) |
658 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
659 V_02870C_SPI_SHADER_4COMP :
660 V_02870C_SPI_SHADER_NONE) |
661 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
662 V_02870C_SPI_SHADER_4COMP :
663 V_02870C_SPI_SHADER_NONE));
664
665
666 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
667 radeon_emit(cmd_buffer->cs, va >> 8);
668 radeon_emit(cmd_buffer->cs, va >> 40);
669 radeon_emit(cmd_buffer->cs, shader->rsrc1);
670 radeon_emit(cmd_buffer->cs, shader->rsrc2);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
673 S_028818_VTX_W0_FMT(1) |
674 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
675 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
676 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
677
678
679 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
680 pipeline->graphics.pa_cl_vs_out_cntl);
681
682 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
683 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
684 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
685 }
686
687 static void
688 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
689 struct radv_shader_variant *shader,
690 struct ac_es_output_info *outinfo)
691 {
692 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
693
694 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
695 outinfo->esgs_itemsize / 4);
696 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
697 radeon_emit(cmd_buffer->cs, va >> 8);
698 radeon_emit(cmd_buffer->cs, va >> 40);
699 radeon_emit(cmd_buffer->cs, shader->rsrc1);
700 radeon_emit(cmd_buffer->cs, shader->rsrc2);
701 }
702
703 static void
704 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
705 struct radv_shader_variant *shader)
706 {
707 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
708 uint32_t rsrc2 = shader->rsrc2;
709
710 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
711 radeon_emit(cmd_buffer->cs, va >> 8);
712 radeon_emit(cmd_buffer->cs, va >> 40);
713
714 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
715 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
716 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
717 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
718
719 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
720 radeon_emit(cmd_buffer->cs, shader->rsrc1);
721 radeon_emit(cmd_buffer->cs, rsrc2);
722 }
723
724 static void
725 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
726 struct radv_shader_variant *shader)
727 {
728 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
729
730 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
731 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
732 radeon_emit(cmd_buffer->cs, va >> 8);
733 radeon_emit(cmd_buffer->cs, va >> 40);
734
735 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
736 radeon_emit(cmd_buffer->cs, shader->rsrc1);
737 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
738 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
739 } else {
740 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
741 radeon_emit(cmd_buffer->cs, va >> 8);
742 radeon_emit(cmd_buffer->cs, va >> 40);
743 radeon_emit(cmd_buffer->cs, shader->rsrc1);
744 radeon_emit(cmd_buffer->cs, shader->rsrc2);
745 }
746 }
747
748 static void
749 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
750 struct radv_pipeline *pipeline)
751 {
752 struct radv_shader_variant *vs;
753
754 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
755
756 /* Skip shaders merged into HS/GS */
757 vs = pipeline->shaders[MESA_SHADER_VERTEX];
758 if (!vs)
759 return;
760
761 if (vs->info.vs.as_ls)
762 radv_emit_hw_ls(cmd_buffer, vs);
763 else if (vs->info.vs.as_es)
764 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
765 else
766 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
767 }
768
769
770 static void
771 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
772 struct radv_pipeline *pipeline)
773 {
774 if (!radv_pipeline_has_tess(pipeline))
775 return;
776
777 struct radv_shader_variant *tes, *tcs;
778
779 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
780 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
781
782 if (tes) {
783 if (tes->info.tes.as_es)
784 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
785 else
786 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
787 }
788
789 radv_emit_hw_hs(cmd_buffer, tcs);
790
791 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
792 pipeline->graphics.tess.tf_param);
793
794 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
795 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
796 pipeline->graphics.tess.ls_hs_config);
797 else
798 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
799 pipeline->graphics.tess.ls_hs_config);
800
801 struct ac_userdata_info *loc;
802
803 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
804 if (loc->sgpr_idx != -1) {
805 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
806 assert(loc->num_sgprs == 4);
807 assert(!loc->indirect);
808 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
809 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
810 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
811 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
812 pipeline->graphics.tess.num_tcs_input_cp << 26);
813 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
814 }
815
816 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
817 if (loc->sgpr_idx != -1) {
818 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
819 assert(loc->num_sgprs == 1);
820 assert(!loc->indirect);
821
822 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
823 pipeline->graphics.tess.offchip_layout);
824 }
825
826 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
827 if (loc->sgpr_idx != -1) {
828 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
829 assert(loc->num_sgprs == 1);
830 assert(!loc->indirect);
831
832 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
833 pipeline->graphics.tess.tcs_in_layout);
834 }
835 }
836
837 static void
838 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline)
840 {
841 struct radv_shader_variant *gs;
842 uint64_t va;
843
844 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
845
846 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
847 if (!gs)
848 return;
849
850 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
851
852 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
853 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
854 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
855 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
856
857 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
858
859 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
860
861 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
862 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
863 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
864 radeon_emit(cmd_buffer->cs, 0);
865 radeon_emit(cmd_buffer->cs, 0);
866 radeon_emit(cmd_buffer->cs, 0);
867
868 uint32_t gs_num_invocations = gs->info.gs.invocations;
869 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
870 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
871 S_028B90_ENABLE(gs_num_invocations > 0));
872
873 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
874
875 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
876 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
877 radeon_emit(cmd_buffer->cs, va >> 8);
878 radeon_emit(cmd_buffer->cs, va >> 40);
879
880 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
881 radeon_emit(cmd_buffer->cs, gs->rsrc1);
882 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
883 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
884
885 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
886 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
887 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize);
888 } else {
889 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
890 radeon_emit(cmd_buffer->cs, va >> 8);
891 radeon_emit(cmd_buffer->cs, va >> 40);
892 radeon_emit(cmd_buffer->cs, gs->rsrc1);
893 radeon_emit(cmd_buffer->cs, gs->rsrc2);
894 }
895
896 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
897
898 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
899 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
900 if (loc->sgpr_idx != -1) {
901 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
902 uint32_t num_entries = 64;
903 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
904
905 if (is_vi)
906 num_entries *= stride;
907
908 stride = S_008F04_STRIDE(stride);
909 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
910 radeon_emit(cmd_buffer->cs, stride);
911 radeon_emit(cmd_buffer->cs, num_entries);
912 }
913 }
914
915 static void
916 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
917 struct radv_pipeline *pipeline)
918 {
919 struct radv_shader_variant *ps;
920 uint64_t va;
921 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
922 struct radv_blend_state *blend = &pipeline->graphics.blend;
923 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
924
925 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
926 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
927
928 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
929 radeon_emit(cmd_buffer->cs, va >> 8);
930 radeon_emit(cmd_buffer->cs, va >> 40);
931 radeon_emit(cmd_buffer->cs, ps->rsrc1);
932 radeon_emit(cmd_buffer->cs, ps->rsrc2);
933
934 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
935 pipeline->graphics.db_shader_control);
936
937 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
938 ps->config.spi_ps_input_ena);
939
940 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
941 ps->config.spi_ps_input_addr);
942
943 if (ps->info.info.ps.force_persample)
944 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
945
946 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
947 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
948
949 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
952 pipeline->graphics.shader_z_format);
953
954 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
955
956 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
957 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
958
959 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
960 /* optimise this? */
961 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
962 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
963 }
964
965 if (pipeline->graphics.ps_input_cntl_num) {
966 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
967 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
968 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
969 }
970 }
971 }
972
973 static void
974 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_pipeline *pipeline)
976 {
977 struct radeon_winsys_cs *cs = cmd_buffer->cs;
978
979 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
980 return;
981
982 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
983 pipeline->graphics.vtx_reuse_depth);
984 }
985
986 static void
987 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
988 {
989 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
990
991 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
992 return;
993
994 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
995 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
996 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
997 radv_update_multisample_state(cmd_buffer, pipeline);
998 radv_emit_vertex_shader(cmd_buffer, pipeline);
999 radv_emit_tess_shaders(cmd_buffer, pipeline);
1000 radv_emit_geometry_shader(cmd_buffer, pipeline);
1001 radv_emit_fragment_shader(cmd_buffer, pipeline);
1002 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1003
1004 cmd_buffer->scratch_size_needed =
1005 MAX2(cmd_buffer->scratch_size_needed,
1006 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1009 S_0286E8_WAVES(pipeline->max_waves) |
1010 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1011
1012 if (!cmd_buffer->state.emitted_pipeline ||
1013 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1014 pipeline->graphics.can_use_guardband)
1015 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1016
1017 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1018
1019 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1020 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1021 } else {
1022 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1023 }
1024 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1025
1026 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1027
1028 cmd_buffer->state.emitted_pipeline = pipeline;
1029
1030 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1031 }
1032
1033 static void
1034 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1035 {
1036 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1037 cmd_buffer->state.dynamic.viewport.viewports);
1038 }
1039
1040 static void
1041 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1042 {
1043 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1044
1045 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1046 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1047 si_emit_cache_flush(cmd_buffer);
1048 }
1049 si_write_scissors(cmd_buffer->cs, 0, count,
1050 cmd_buffer->state.dynamic.scissor.scissors,
1051 cmd_buffer->state.dynamic.viewport.viewports,
1052 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1053 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1054 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1055 }
1056
1057 static void
1058 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1059 {
1060 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1061
1062 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1063 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1064 }
1065
1066 static void
1067 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1068 {
1069 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1070
1071 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1072 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1073 }
1074
1075 static void
1076 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1077 {
1078 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1079
1080 radeon_set_context_reg_seq(cmd_buffer->cs,
1081 R_028430_DB_STENCILREFMASK, 2);
1082 radeon_emit(cmd_buffer->cs,
1083 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1084 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1085 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1086 S_028430_STENCILOPVAL(1));
1087 radeon_emit(cmd_buffer->cs,
1088 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1089 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1090 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1091 S_028434_STENCILOPVAL_BF(1));
1092 }
1093
1094 static void
1095 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1096 {
1097 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1098
1099 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1100 fui(d->depth_bounds.min));
1101 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1102 fui(d->depth_bounds.max));
1103 }
1104
1105 static void
1106 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1107 {
1108 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1109 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1110 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1111 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1112
1113 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1114 radeon_set_context_reg_seq(cmd_buffer->cs,
1115 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1116 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1117 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1118 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1119 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1120 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1121 }
1122 }
1123
1124 static void
1125 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1126 int index,
1127 struct radv_color_buffer_info *cb)
1128 {
1129 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1130
1131 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1132 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1133 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1134 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1135 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1136 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1137 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1138 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1139 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1140 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1141 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1142 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1143 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1144
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1146 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1147 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1148
1149 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1150 cb->gfx9_epitch);
1151 } else {
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1153 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1154 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1155 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1156 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1157 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1158 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1159 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1160 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1161 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1162 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1163 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1164
1165 if (is_vi) { /* DCC BASE */
1166 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1167 }
1168 }
1169 }
1170
1171 static void
1172 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1173 struct radv_ds_buffer_info *ds,
1174 struct radv_image *image,
1175 VkImageLayout layout)
1176 {
1177 uint32_t db_z_info = ds->db_z_info;
1178 uint32_t db_stencil_info = ds->db_stencil_info;
1179
1180 if (!radv_layout_has_htile(image, layout,
1181 radv_image_queue_family_mask(image,
1182 cmd_buffer->queue_family_index,
1183 cmd_buffer->queue_family_index))) {
1184 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1185 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1186 }
1187
1188 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1189 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1190
1191
1192 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1193 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1194 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1195 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1196 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1197
1198 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1199 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1200 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1201 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1202 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1203 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1204 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1205 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1206 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1207 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1208 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1209
1210 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1211 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1212 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1213 } else {
1214 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1215
1216 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1217 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1218 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1219 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1220 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1221 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1222 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1223 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1224 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1225 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1226
1227 }
1228
1229 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1230 ds->pa_su_poly_offset_db_fmt_cntl);
1231 }
1232
1233 void
1234 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1235 struct radv_image *image,
1236 VkClearDepthStencilValue ds_clear_value,
1237 VkImageAspectFlags aspects)
1238 {
1239 uint64_t va = radv_buffer_get_va(image->bo);
1240 va += image->offset + image->clear_value_offset;
1241 unsigned reg_offset = 0, reg_count = 0;
1242
1243 if (!image->surface.htile_size || !aspects)
1244 return;
1245
1246 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1247 ++reg_count;
1248 } else {
1249 ++reg_offset;
1250 va += 4;
1251 }
1252 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1253 ++reg_count;
1254
1255 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1256
1257 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1258 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1259 S_370_WR_CONFIRM(1) |
1260 S_370_ENGINE_SEL(V_370_PFP));
1261 radeon_emit(cmd_buffer->cs, va);
1262 radeon_emit(cmd_buffer->cs, va >> 32);
1263 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1264 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1265 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1266 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1267
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1270 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1271 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1272 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1273 }
1274
1275 static void
1276 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1277 struct radv_image *image)
1278 {
1279 uint64_t va = radv_buffer_get_va(image->bo);
1280 va += image->offset + image->clear_value_offset;
1281
1282 if (!image->surface.htile_size)
1283 return;
1284
1285 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1286
1287 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1288 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1289 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1290 COPY_DATA_COUNT_SEL);
1291 radeon_emit(cmd_buffer->cs, va);
1292 radeon_emit(cmd_buffer->cs, va >> 32);
1293 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1294 radeon_emit(cmd_buffer->cs, 0);
1295
1296 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1297 radeon_emit(cmd_buffer->cs, 0);
1298 }
1299
1300 /*
1301 *with DCC some colors don't require CMASK elimiation before being
1302 * used as a texture. This sets a predicate value to determine if the
1303 * cmask eliminate is required.
1304 */
1305 void
1306 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1307 struct radv_image *image,
1308 bool value)
1309 {
1310 uint64_t pred_val = value;
1311 uint64_t va = radv_buffer_get_va(image->bo);
1312 va += image->offset + image->dcc_pred_offset;
1313
1314 if (!image->surface.dcc_size)
1315 return;
1316
1317 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1318
1319 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1320 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1321 S_370_WR_CONFIRM(1) |
1322 S_370_ENGINE_SEL(V_370_PFP));
1323 radeon_emit(cmd_buffer->cs, va);
1324 radeon_emit(cmd_buffer->cs, va >> 32);
1325 radeon_emit(cmd_buffer->cs, pred_val);
1326 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1327 }
1328
1329 void
1330 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1331 struct radv_image *image,
1332 int idx,
1333 uint32_t color_values[2])
1334 {
1335 uint64_t va = radv_buffer_get_va(image->bo);
1336 va += image->offset + image->clear_value_offset;
1337
1338 if (!image->cmask.size && !image->surface.dcc_size)
1339 return;
1340
1341 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1342
1343 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1344 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1345 S_370_WR_CONFIRM(1) |
1346 S_370_ENGINE_SEL(V_370_PFP));
1347 radeon_emit(cmd_buffer->cs, va);
1348 radeon_emit(cmd_buffer->cs, va >> 32);
1349 radeon_emit(cmd_buffer->cs, color_values[0]);
1350 radeon_emit(cmd_buffer->cs, color_values[1]);
1351
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1353 radeon_emit(cmd_buffer->cs, color_values[0]);
1354 radeon_emit(cmd_buffer->cs, color_values[1]);
1355 }
1356
1357 static void
1358 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1359 struct radv_image *image,
1360 int idx)
1361 {
1362 uint64_t va = radv_buffer_get_va(image->bo);
1363 va += image->offset + image->clear_value_offset;
1364
1365 if (!image->cmask.size && !image->surface.dcc_size)
1366 return;
1367
1368 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1369 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1370
1371 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1372 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1373 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1374 COPY_DATA_COUNT_SEL);
1375 radeon_emit(cmd_buffer->cs, va);
1376 radeon_emit(cmd_buffer->cs, va >> 32);
1377 radeon_emit(cmd_buffer->cs, reg >> 2);
1378 radeon_emit(cmd_buffer->cs, 0);
1379
1380 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1381 radeon_emit(cmd_buffer->cs, 0);
1382 }
1383
1384 void
1385 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1386 {
1387 int i;
1388 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1389 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1390
1391 /* this may happen for inherited secondary recording */
1392 if (!framebuffer)
1393 return;
1394
1395 for (i = 0; i < 8; ++i) {
1396 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1397 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1398 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1399 continue;
1400 }
1401
1402 int idx = subpass->color_attachments[i].attachment;
1403 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1404
1405 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1406
1407 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1408 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1409
1410 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1411 }
1412
1413 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1414 int idx = subpass->depth_stencil_attachment.attachment;
1415 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1416 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1417 struct radv_image *image = att->attachment->image;
1418 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1419 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1420 cmd_buffer->queue_family_index,
1421 cmd_buffer->queue_family_index);
1422 /* We currently don't support writing decompressed HTILE */
1423 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1424 radv_layout_is_htile_compressed(image, layout, queue_mask));
1425
1426 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1427
1428 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1429 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1430 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1431 }
1432 radv_load_depth_clear_regs(cmd_buffer, image);
1433 } else {
1434 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1436 else
1437 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1438
1439 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1440 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1441 }
1442 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1443 S_028208_BR_X(framebuffer->width) |
1444 S_028208_BR_Y(framebuffer->height));
1445
1446 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1447 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1448 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1449 }
1450
1451 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1452 }
1453
1454 static void
1455 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1456 {
1457 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1458
1459 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1460 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1461 2, cmd_buffer->state.index_type);
1462 } else {
1463 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1464 radeon_emit(cs, cmd_buffer->state.index_type);
1465 }
1466
1467 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1468 radeon_emit(cs, cmd_buffer->state.index_va);
1469 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1470
1471 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1472 radeon_emit(cs, cmd_buffer->state.max_index_count);
1473
1474 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1475 }
1476
1477 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1478 {
1479 uint32_t db_count_control;
1480
1481 if(!cmd_buffer->state.active_occlusion_queries) {
1482 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1483 db_count_control = 0;
1484 } else {
1485 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1486 }
1487 } else {
1488 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1489 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1490 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1491 S_028004_ZPASS_ENABLE(1) |
1492 S_028004_SLICE_EVEN_ENABLE(1) |
1493 S_028004_SLICE_ODD_ENABLE(1);
1494 } else {
1495 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1496 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1497 }
1498 }
1499
1500 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1501 }
1502
1503 static void
1504 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1505 {
1506 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1507 return;
1508
1509 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1510 radv_emit_viewport(cmd_buffer);
1511
1512 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1513 radv_emit_scissor(cmd_buffer);
1514
1515 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1516 radv_emit_line_width(cmd_buffer);
1517
1518 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1519 radv_emit_blend_constants(cmd_buffer);
1520
1521 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1522 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1523 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1524 radv_emit_stencil(cmd_buffer);
1525
1526 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1527 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1528 radv_emit_depth_bounds(cmd_buffer);
1529
1530 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1531 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1532 radv_emit_depth_biais(cmd_buffer);
1533
1534 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1535 }
1536
1537 static void
1538 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1539 struct radv_pipeline *pipeline,
1540 int idx,
1541 uint64_t va,
1542 gl_shader_stage stage)
1543 {
1544 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1545 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1546
1547 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1548 return;
1549
1550 assert(!desc_set_loc->indirect);
1551 assert(desc_set_loc->num_sgprs == 2);
1552 radeon_set_sh_reg_seq(cmd_buffer->cs,
1553 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1554 radeon_emit(cmd_buffer->cs, va);
1555 radeon_emit(cmd_buffer->cs, va >> 32);
1556 }
1557
1558 static void
1559 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1560 VkShaderStageFlags stages,
1561 struct radv_descriptor_set *set,
1562 unsigned idx)
1563 {
1564 if (cmd_buffer->state.pipeline) {
1565 radv_foreach_stage(stage, stages) {
1566 if (cmd_buffer->state.pipeline->shaders[stage])
1567 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1568 idx, set->va,
1569 stage);
1570 }
1571 }
1572
1573 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1574 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1575 idx, set->va,
1576 MESA_SHADER_COMPUTE);
1577 }
1578
1579 static void
1580 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1581 {
1582 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1583 unsigned bo_offset;
1584
1585 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1586 set->mapped_ptr,
1587 &bo_offset))
1588 return;
1589
1590 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1591 set->va += bo_offset;
1592 }
1593
1594 static void
1595 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1596 {
1597 uint32_t size = MAX_SETS * 2 * 4;
1598 uint32_t offset;
1599 void *ptr;
1600
1601 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1602 256, &offset, &ptr))
1603 return;
1604
1605 for (unsigned i = 0; i < MAX_SETS; i++) {
1606 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1607 uint64_t set_va = 0;
1608 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1609 if (set)
1610 set_va = set->va;
1611 uptr[0] = set_va & 0xffffffff;
1612 uptr[1] = set_va >> 32;
1613 }
1614
1615 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1616 va += offset;
1617
1618 if (cmd_buffer->state.pipeline) {
1619 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1620 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1621 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1622
1623 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1624 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1625 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1626
1627 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1628 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1629 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1630
1631 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1632 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1633 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1634
1635 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1636 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1637 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1638 }
1639
1640 if (cmd_buffer->state.compute_pipeline)
1641 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1642 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1643 }
1644
1645 static void
1646 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1647 VkShaderStageFlags stages)
1648 {
1649 unsigned i;
1650
1651 if (!cmd_buffer->state.descriptors_dirty)
1652 return;
1653
1654 if (cmd_buffer->state.push_descriptors_dirty)
1655 radv_flush_push_descriptors(cmd_buffer);
1656
1657 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1658 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1659 radv_flush_indirect_descriptor_sets(cmd_buffer);
1660 }
1661
1662 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1663 cmd_buffer->cs,
1664 MAX_SETS * MESA_SHADER_STAGES * 4);
1665
1666 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1667 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1668 if (!set)
1669 continue;
1670
1671 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1672 }
1673 cmd_buffer->state.descriptors_dirty = 0;
1674 cmd_buffer->state.push_descriptors_dirty = false;
1675
1676 radv_save_descriptors(cmd_buffer);
1677
1678 assert(cmd_buffer->cs->cdw <= cdw_max);
1679 }
1680
1681 static void
1682 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1683 struct radv_pipeline *pipeline,
1684 VkShaderStageFlags stages)
1685 {
1686 struct radv_pipeline_layout *layout = pipeline->layout;
1687 unsigned offset;
1688 void *ptr;
1689 uint64_t va;
1690
1691 stages &= cmd_buffer->push_constant_stages;
1692 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1693 return;
1694
1695 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1696 16 * layout->dynamic_offset_count,
1697 256, &offset, &ptr))
1698 return;
1699
1700 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1701 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1702 16 * layout->dynamic_offset_count);
1703
1704 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1705 va += offset;
1706
1707 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1708 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1709
1710 radv_foreach_stage(stage, stages) {
1711 if (pipeline->shaders[stage]) {
1712 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1713 AC_UD_PUSH_CONSTANTS, va);
1714 }
1715 }
1716
1717 cmd_buffer->push_constant_stages &= ~stages;
1718 assert(cmd_buffer->cs->cdw <= cdw_max);
1719 }
1720
1721 static bool
1722 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1723 {
1724 struct radv_device *device = cmd_buffer->device;
1725
1726 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1727 cmd_buffer->state.pipeline->vertex_elements.count &&
1728 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1729 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1730 unsigned vb_offset;
1731 void *vb_ptr;
1732 uint32_t i = 0;
1733 uint32_t count = velems->count;
1734 uint64_t va;
1735
1736 /* allocate some descriptor state for vertex buffers */
1737 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1738 &vb_offset, &vb_ptr))
1739 return false;
1740
1741 for (i = 0; i < count; i++) {
1742 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1743 uint32_t offset;
1744 int vb = velems->binding[i];
1745 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1746 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1747
1748 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1749 va = radv_buffer_get_va(buffer->bo);
1750
1751 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1752 va += offset + buffer->offset;
1753 desc[0] = va;
1754 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1755 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1756 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1757 else
1758 desc[2] = buffer->size - offset;
1759 desc[3] = velems->rsrc_word3[i];
1760 }
1761
1762 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1763 va += vb_offset;
1764
1765 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1766 AC_UD_VS_VERTEX_BUFFERS, va);
1767 }
1768 cmd_buffer->state.vb_dirty = false;
1769
1770 return true;
1771 }
1772
1773 static bool
1774 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1775 {
1776 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1777 return false;
1778
1779 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1780 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1781 VK_SHADER_STAGE_ALL_GRAPHICS);
1782
1783 return true;
1784 }
1785
1786 static void
1787 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1788 bool instanced_draw, bool indirect_draw,
1789 uint32_t draw_vertex_count)
1790 {
1791 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1792 struct radv_cmd_state *state = &cmd_buffer->state;
1793 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1794 uint32_t ia_multi_vgt_param;
1795 int32_t primitive_reset_en;
1796
1797 /* Draw state. */
1798 ia_multi_vgt_param =
1799 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1800 indirect_draw, draw_vertex_count);
1801
1802 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1803 if (info->chip_class >= GFX9) {
1804 radeon_set_uconfig_reg_idx(cs,
1805 R_030960_IA_MULTI_VGT_PARAM,
1806 4, ia_multi_vgt_param);
1807 } else if (info->chip_class >= CIK) {
1808 radeon_set_context_reg_idx(cs,
1809 R_028AA8_IA_MULTI_VGT_PARAM,
1810 1, ia_multi_vgt_param);
1811 } else {
1812 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1813 ia_multi_vgt_param);
1814 }
1815 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1816 }
1817
1818 /* Primitive restart. */
1819 primitive_reset_en =
1820 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1821
1822 if (primitive_reset_en != state->last_primitive_reset_en) {
1823 state->last_primitive_reset_en = primitive_reset_en;
1824 if (info->chip_class >= GFX9) {
1825 radeon_set_uconfig_reg(cs,
1826 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1827 primitive_reset_en);
1828 } else {
1829 radeon_set_context_reg(cs,
1830 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1831 primitive_reset_en);
1832 }
1833 }
1834
1835 if (primitive_reset_en) {
1836 uint32_t primitive_reset_index =
1837 state->index_type ? 0xffffffffu : 0xffffu;
1838
1839 if (primitive_reset_index != state->last_primitive_reset_index) {
1840 radeon_set_context_reg(cs,
1841 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1842 primitive_reset_index);
1843 state->last_primitive_reset_index = primitive_reset_index;
1844 }
1845 }
1846 }
1847
1848 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1849 VkPipelineStageFlags src_stage_mask)
1850 {
1851 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1852 VK_PIPELINE_STAGE_TRANSFER_BIT |
1853 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1854 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1855 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1856 }
1857
1858 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1859 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1860 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1861 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1862 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1863 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1864 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1865 VK_PIPELINE_STAGE_TRANSFER_BIT |
1866 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1867 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1868 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1869 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1870 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1871 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1872 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1873 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1874 }
1875 }
1876
1877 static enum radv_cmd_flush_bits
1878 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1879 VkAccessFlags src_flags)
1880 {
1881 enum radv_cmd_flush_bits flush_bits = 0;
1882 uint32_t b;
1883 for_each_bit(b, src_flags) {
1884 switch ((VkAccessFlagBits)(1 << b)) {
1885 case VK_ACCESS_SHADER_WRITE_BIT:
1886 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1887 break;
1888 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1889 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1890 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1891 break;
1892 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1893 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1894 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1895 break;
1896 case VK_ACCESS_TRANSFER_WRITE_BIT:
1897 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1898 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1899 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1900 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1901 RADV_CMD_FLAG_INV_GLOBAL_L2;
1902 break;
1903 default:
1904 break;
1905 }
1906 }
1907 return flush_bits;
1908 }
1909
1910 static enum radv_cmd_flush_bits
1911 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1912 VkAccessFlags dst_flags,
1913 struct radv_image *image)
1914 {
1915 enum radv_cmd_flush_bits flush_bits = 0;
1916 uint32_t b;
1917 for_each_bit(b, dst_flags) {
1918 switch ((VkAccessFlagBits)(1 << b)) {
1919 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1920 case VK_ACCESS_INDEX_READ_BIT:
1921 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1922 break;
1923 case VK_ACCESS_UNIFORM_READ_BIT:
1924 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1925 break;
1926 case VK_ACCESS_SHADER_READ_BIT:
1927 case VK_ACCESS_TRANSFER_READ_BIT:
1928 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1929 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1930 RADV_CMD_FLAG_INV_GLOBAL_L2;
1931 break;
1932 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1933 /* TODO: change to image && when the image gets passed
1934 * through from the subpass. */
1935 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1936 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1937 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1938 break;
1939 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1940 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1941 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1942 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1943 break;
1944 default:
1945 break;
1946 }
1947 }
1948 return flush_bits;
1949 }
1950
1951 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1952 {
1953 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1954 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1955 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1956 NULL);
1957 }
1958
1959 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1960 VkAttachmentReference att)
1961 {
1962 unsigned idx = att.attachment;
1963 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1964 VkImageSubresourceRange range;
1965 range.aspectMask = 0;
1966 range.baseMipLevel = view->base_mip;
1967 range.levelCount = 1;
1968 range.baseArrayLayer = view->base_layer;
1969 range.layerCount = cmd_buffer->state.framebuffer->layers;
1970
1971 radv_handle_image_transition(cmd_buffer,
1972 view->image,
1973 cmd_buffer->state.attachments[idx].current_layout,
1974 att.layout, 0, 0, &range,
1975 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1976
1977 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1978
1979
1980 }
1981
1982 void
1983 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1984 const struct radv_subpass *subpass, bool transitions)
1985 {
1986 if (transitions) {
1987 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1988
1989 for (unsigned i = 0; i < subpass->color_count; ++i) {
1990 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1991 radv_handle_subpass_image_transition(cmd_buffer,
1992 subpass->color_attachments[i]);
1993 }
1994
1995 for (unsigned i = 0; i < subpass->input_count; ++i) {
1996 radv_handle_subpass_image_transition(cmd_buffer,
1997 subpass->input_attachments[i]);
1998 }
1999
2000 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2001 radv_handle_subpass_image_transition(cmd_buffer,
2002 subpass->depth_stencil_attachment);
2003 }
2004 }
2005
2006 cmd_buffer->state.subpass = subpass;
2007
2008 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2009 }
2010
2011 static VkResult
2012 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2013 struct radv_render_pass *pass,
2014 const VkRenderPassBeginInfo *info)
2015 {
2016 struct radv_cmd_state *state = &cmd_buffer->state;
2017
2018 if (pass->attachment_count == 0) {
2019 state->attachments = NULL;
2020 return VK_SUCCESS;
2021 }
2022
2023 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2024 pass->attachment_count *
2025 sizeof(state->attachments[0]),
2026 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2027 if (state->attachments == NULL) {
2028 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2029 return cmd_buffer->record_result;
2030 }
2031
2032 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2033 struct radv_render_pass_attachment *att = &pass->attachments[i];
2034 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2035 VkImageAspectFlags clear_aspects = 0;
2036
2037 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2038 /* color attachment */
2039 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2040 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2041 }
2042 } else {
2043 /* depthstencil attachment */
2044 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2045 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2046 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2047 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2048 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2049 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2050 }
2051 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2052 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2053 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2054 }
2055 }
2056
2057 state->attachments[i].pending_clear_aspects = clear_aspects;
2058 state->attachments[i].cleared_views = 0;
2059 if (clear_aspects && info) {
2060 assert(info->clearValueCount > i);
2061 state->attachments[i].clear_value = info->pClearValues[i];
2062 }
2063
2064 state->attachments[i].current_layout = att->initial_layout;
2065 }
2066
2067 return VK_SUCCESS;
2068 }
2069
2070 VkResult radv_AllocateCommandBuffers(
2071 VkDevice _device,
2072 const VkCommandBufferAllocateInfo *pAllocateInfo,
2073 VkCommandBuffer *pCommandBuffers)
2074 {
2075 RADV_FROM_HANDLE(radv_device, device, _device);
2076 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2077
2078 VkResult result = VK_SUCCESS;
2079 uint32_t i;
2080
2081 memset(pCommandBuffers, 0,
2082 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2083
2084 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2085
2086 if (!list_empty(&pool->free_cmd_buffers)) {
2087 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2088
2089 list_del(&cmd_buffer->pool_link);
2090 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2091
2092 result = radv_reset_cmd_buffer(cmd_buffer);
2093 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2094 cmd_buffer->level = pAllocateInfo->level;
2095
2096 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2097 } else {
2098 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2099 &pCommandBuffers[i]);
2100 }
2101 if (result != VK_SUCCESS)
2102 break;
2103 }
2104
2105 if (result != VK_SUCCESS)
2106 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2107 i, pCommandBuffers);
2108
2109 return result;
2110 }
2111
2112 void radv_FreeCommandBuffers(
2113 VkDevice device,
2114 VkCommandPool commandPool,
2115 uint32_t commandBufferCount,
2116 const VkCommandBuffer *pCommandBuffers)
2117 {
2118 for (uint32_t i = 0; i < commandBufferCount; i++) {
2119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2120
2121 if (cmd_buffer) {
2122 if (cmd_buffer->pool) {
2123 list_del(&cmd_buffer->pool_link);
2124 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2125 } else
2126 radv_cmd_buffer_destroy(cmd_buffer);
2127
2128 }
2129 }
2130 }
2131
2132 VkResult radv_ResetCommandBuffer(
2133 VkCommandBuffer commandBuffer,
2134 VkCommandBufferResetFlags flags)
2135 {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2137 return radv_reset_cmd_buffer(cmd_buffer);
2138 }
2139
2140 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2141 {
2142 struct radv_device *device = cmd_buffer->device;
2143 if (device->gfx_init) {
2144 uint64_t va = radv_buffer_get_va(device->gfx_init);
2145 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2146 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2147 radeon_emit(cmd_buffer->cs, va);
2148 radeon_emit(cmd_buffer->cs, va >> 32);
2149 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2150 } else
2151 si_init_config(cmd_buffer);
2152 }
2153
2154 VkResult radv_BeginCommandBuffer(
2155 VkCommandBuffer commandBuffer,
2156 const VkCommandBufferBeginInfo *pBeginInfo)
2157 {
2158 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2159 VkResult result;
2160
2161 result = radv_reset_cmd_buffer(cmd_buffer);
2162 if (result != VK_SUCCESS)
2163 return result;
2164
2165 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2166 cmd_buffer->state.last_primitive_reset_en = -1;
2167 cmd_buffer->usage_flags = pBeginInfo->flags;
2168
2169 /* setup initial configuration into command buffer */
2170 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2171 switch (cmd_buffer->queue_family_index) {
2172 case RADV_QUEUE_GENERAL:
2173 emit_gfx_buffer_state(cmd_buffer);
2174 break;
2175 case RADV_QUEUE_COMPUTE:
2176 si_init_compute(cmd_buffer);
2177 break;
2178 case RADV_QUEUE_TRANSFER:
2179 default:
2180 break;
2181 }
2182 }
2183
2184 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2185 assert(pBeginInfo->pInheritanceInfo);
2186 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2187 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2188
2189 struct radv_subpass *subpass =
2190 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2191
2192 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2193 if (result != VK_SUCCESS)
2194 return result;
2195
2196 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2197 }
2198
2199 radv_cmd_buffer_trace_emit(cmd_buffer);
2200 return result;
2201 }
2202
2203 void radv_CmdBindVertexBuffers(
2204 VkCommandBuffer commandBuffer,
2205 uint32_t firstBinding,
2206 uint32_t bindingCount,
2207 const VkBuffer* pBuffers,
2208 const VkDeviceSize* pOffsets)
2209 {
2210 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2211 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2212
2213 /* We have to defer setting up vertex buffer since we need the buffer
2214 * stride from the pipeline. */
2215
2216 assert(firstBinding + bindingCount <= MAX_VBS);
2217 for (uint32_t i = 0; i < bindingCount; i++) {
2218 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2219 vb[firstBinding + i].offset = pOffsets[i];
2220 }
2221
2222 cmd_buffer->state.vb_dirty = true;
2223 }
2224
2225 void radv_CmdBindIndexBuffer(
2226 VkCommandBuffer commandBuffer,
2227 VkBuffer buffer,
2228 VkDeviceSize offset,
2229 VkIndexType indexType)
2230 {
2231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2232 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2233
2234 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2235 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2236 cmd_buffer->state.index_va += index_buffer->offset + offset;
2237
2238 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2239 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2240 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2241 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2242 }
2243
2244
2245 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2246 struct radv_descriptor_set *set,
2247 unsigned idx)
2248 {
2249 struct radeon_winsys *ws = cmd_buffer->device->ws;
2250
2251 cmd_buffer->state.descriptors[idx] = set;
2252 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2253 if (!set)
2254 return;
2255
2256 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2257
2258 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2259 if (set->descriptors[j])
2260 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2261
2262 if(set->bo)
2263 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2264 }
2265
2266 void radv_CmdBindDescriptorSets(
2267 VkCommandBuffer commandBuffer,
2268 VkPipelineBindPoint pipelineBindPoint,
2269 VkPipelineLayout _layout,
2270 uint32_t firstSet,
2271 uint32_t descriptorSetCount,
2272 const VkDescriptorSet* pDescriptorSets,
2273 uint32_t dynamicOffsetCount,
2274 const uint32_t* pDynamicOffsets)
2275 {
2276 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2277 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2278 unsigned dyn_idx = 0;
2279
2280 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2281 unsigned idx = i + firstSet;
2282 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2283 radv_bind_descriptor_set(cmd_buffer, set, idx);
2284
2285 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2286 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2287 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2288 assert(dyn_idx < dynamicOffsetCount);
2289
2290 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2291 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2292 dst[0] = va;
2293 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2294 dst[2] = range->size;
2295 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2296 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2297 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2298 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2299 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2300 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2301 cmd_buffer->push_constant_stages |=
2302 set->layout->dynamic_shader_stages;
2303 }
2304 }
2305 }
2306
2307 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2308 struct radv_descriptor_set *set,
2309 struct radv_descriptor_set_layout *layout)
2310 {
2311 set->size = layout->size;
2312 set->layout = layout;
2313
2314 if (cmd_buffer->push_descriptors.capacity < set->size) {
2315 size_t new_size = MAX2(set->size, 1024);
2316 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2317 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2318
2319 free(set->mapped_ptr);
2320 set->mapped_ptr = malloc(new_size);
2321
2322 if (!set->mapped_ptr) {
2323 cmd_buffer->push_descriptors.capacity = 0;
2324 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2325 return false;
2326 }
2327
2328 cmd_buffer->push_descriptors.capacity = new_size;
2329 }
2330
2331 return true;
2332 }
2333
2334 void radv_meta_push_descriptor_set(
2335 struct radv_cmd_buffer* cmd_buffer,
2336 VkPipelineBindPoint pipelineBindPoint,
2337 VkPipelineLayout _layout,
2338 uint32_t set,
2339 uint32_t descriptorWriteCount,
2340 const VkWriteDescriptorSet* pDescriptorWrites)
2341 {
2342 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2343 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2344 unsigned bo_offset;
2345
2346 assert(set == 0);
2347 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2348
2349 push_set->size = layout->set[set].layout->size;
2350 push_set->layout = layout->set[set].layout;
2351
2352 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2353 &bo_offset,
2354 (void**) &push_set->mapped_ptr))
2355 return;
2356
2357 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2358 push_set->va += bo_offset;
2359
2360 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2361 radv_descriptor_set_to_handle(push_set),
2362 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2363
2364 cmd_buffer->state.descriptors[set] = push_set;
2365 cmd_buffer->state.descriptors_dirty |= (1u << set);
2366 }
2367
2368 void radv_CmdPushDescriptorSetKHR(
2369 VkCommandBuffer commandBuffer,
2370 VkPipelineBindPoint pipelineBindPoint,
2371 VkPipelineLayout _layout,
2372 uint32_t set,
2373 uint32_t descriptorWriteCount,
2374 const VkWriteDescriptorSet* pDescriptorWrites)
2375 {
2376 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2377 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2378 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2379
2380 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2381
2382 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2383 return;
2384
2385 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2386 radv_descriptor_set_to_handle(push_set),
2387 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2388
2389 cmd_buffer->state.descriptors[set] = push_set;
2390 cmd_buffer->state.descriptors_dirty |= (1u << set);
2391 cmd_buffer->state.push_descriptors_dirty = true;
2392 }
2393
2394 void radv_CmdPushDescriptorSetWithTemplateKHR(
2395 VkCommandBuffer commandBuffer,
2396 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2397 VkPipelineLayout _layout,
2398 uint32_t set,
2399 const void* pData)
2400 {
2401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2402 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2403 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2404
2405 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2406
2407 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2408 return;
2409
2410 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2411 descriptorUpdateTemplate, pData);
2412
2413 cmd_buffer->state.descriptors[set] = push_set;
2414 cmd_buffer->state.descriptors_dirty |= (1u << set);
2415 cmd_buffer->state.push_descriptors_dirty = true;
2416 }
2417
2418 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2419 VkPipelineLayout layout,
2420 VkShaderStageFlags stageFlags,
2421 uint32_t offset,
2422 uint32_t size,
2423 const void* pValues)
2424 {
2425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2426 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2427 cmd_buffer->push_constant_stages |= stageFlags;
2428 }
2429
2430 VkResult radv_EndCommandBuffer(
2431 VkCommandBuffer commandBuffer)
2432 {
2433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2434
2435 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2436 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2437 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2438 si_emit_cache_flush(cmd_buffer);
2439 }
2440
2441 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2442 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2443
2444 return cmd_buffer->record_result;
2445 }
2446
2447 static void
2448 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2449 {
2450 struct radv_shader_variant *compute_shader;
2451 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2452 uint64_t va;
2453
2454 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2455 return;
2456
2457 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2458
2459 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2460 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2461
2462 radv_emit_shader_prefetch(cmd_buffer, compute_shader);
2463
2464 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2465 cmd_buffer->cs, 16);
2466
2467 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2468 radeon_emit(cmd_buffer->cs, va >> 8);
2469 radeon_emit(cmd_buffer->cs, va >> 40);
2470
2471 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2472 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2473 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2474
2475
2476 cmd_buffer->compute_scratch_size_needed =
2477 MAX2(cmd_buffer->compute_scratch_size_needed,
2478 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2479
2480 /* change these once we have scratch support */
2481 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2482 S_00B860_WAVES(pipeline->max_waves) |
2483 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2484
2485 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2486 radeon_emit(cmd_buffer->cs,
2487 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2488 radeon_emit(cmd_buffer->cs,
2489 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2490 radeon_emit(cmd_buffer->cs,
2491 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2492
2493 assert(cmd_buffer->cs->cdw <= cdw_max);
2494 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2495 }
2496
2497 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2498 {
2499 for (unsigned i = 0; i < MAX_SETS; i++) {
2500 if (cmd_buffer->state.descriptors[i])
2501 cmd_buffer->state.descriptors_dirty |= (1u << i);
2502 }
2503 }
2504
2505 void radv_CmdBindPipeline(
2506 VkCommandBuffer commandBuffer,
2507 VkPipelineBindPoint pipelineBindPoint,
2508 VkPipeline _pipeline)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2511 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2512
2513 switch (pipelineBindPoint) {
2514 case VK_PIPELINE_BIND_POINT_COMPUTE:
2515 if (cmd_buffer->state.compute_pipeline == pipeline)
2516 return;
2517 radv_mark_descriptor_sets_dirty(cmd_buffer);
2518
2519 cmd_buffer->state.compute_pipeline = pipeline;
2520 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2521 break;
2522 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2523 if (cmd_buffer->state.pipeline == pipeline)
2524 return;
2525 radv_mark_descriptor_sets_dirty(cmd_buffer);
2526
2527 cmd_buffer->state.pipeline = pipeline;
2528 if (!pipeline)
2529 break;
2530
2531 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2532 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2533
2534 /* Apply the dynamic state from the pipeline */
2535 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2536 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2537 &pipeline->dynamic_state,
2538 pipeline->dynamic_state_mask);
2539
2540 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2541 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2542 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2543 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2544
2545 if (radv_pipeline_has_tess(pipeline))
2546 cmd_buffer->tess_rings_needed = true;
2547
2548 if (radv_pipeline_has_gs(pipeline)) {
2549 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2550 AC_UD_SCRATCH_RING_OFFSETS);
2551 if (cmd_buffer->ring_offsets_idx == -1)
2552 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2553 else if (loc->sgpr_idx != -1)
2554 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2555 }
2556 break;
2557 default:
2558 assert(!"invalid bind point");
2559 break;
2560 }
2561 }
2562
2563 void radv_CmdSetViewport(
2564 VkCommandBuffer commandBuffer,
2565 uint32_t firstViewport,
2566 uint32_t viewportCount,
2567 const VkViewport* pViewports)
2568 {
2569 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2570 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2571
2572 assert(firstViewport < MAX_VIEWPORTS);
2573 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2574
2575 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2576 pViewports, viewportCount * sizeof(*pViewports));
2577
2578 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2579 }
2580
2581 void radv_CmdSetScissor(
2582 VkCommandBuffer commandBuffer,
2583 uint32_t firstScissor,
2584 uint32_t scissorCount,
2585 const VkRect2D* pScissors)
2586 {
2587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2588 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2589
2590 assert(firstScissor < MAX_SCISSORS);
2591 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2592
2593 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2594 pScissors, scissorCount * sizeof(*pScissors));
2595 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2596 }
2597
2598 void radv_CmdSetLineWidth(
2599 VkCommandBuffer commandBuffer,
2600 float lineWidth)
2601 {
2602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2603 cmd_buffer->state.dynamic.line_width = lineWidth;
2604 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2605 }
2606
2607 void radv_CmdSetDepthBias(
2608 VkCommandBuffer commandBuffer,
2609 float depthBiasConstantFactor,
2610 float depthBiasClamp,
2611 float depthBiasSlopeFactor)
2612 {
2613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2614
2615 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2616 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2617 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2618
2619 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2620 }
2621
2622 void radv_CmdSetBlendConstants(
2623 VkCommandBuffer commandBuffer,
2624 const float blendConstants[4])
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627
2628 memcpy(cmd_buffer->state.dynamic.blend_constants,
2629 blendConstants, sizeof(float) * 4);
2630
2631 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2632 }
2633
2634 void radv_CmdSetDepthBounds(
2635 VkCommandBuffer commandBuffer,
2636 float minDepthBounds,
2637 float maxDepthBounds)
2638 {
2639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2640
2641 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2642 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2643
2644 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2645 }
2646
2647 void radv_CmdSetStencilCompareMask(
2648 VkCommandBuffer commandBuffer,
2649 VkStencilFaceFlags faceMask,
2650 uint32_t compareMask)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653
2654 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2655 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2656 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2657 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2658
2659 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2660 }
2661
2662 void radv_CmdSetStencilWriteMask(
2663 VkCommandBuffer commandBuffer,
2664 VkStencilFaceFlags faceMask,
2665 uint32_t writeMask)
2666 {
2667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2668
2669 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2670 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2671 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2672 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2673
2674 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2675 }
2676
2677 void radv_CmdSetStencilReference(
2678 VkCommandBuffer commandBuffer,
2679 VkStencilFaceFlags faceMask,
2680 uint32_t reference)
2681 {
2682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2683
2684 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2685 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2686 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2687 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2688
2689 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2690 }
2691
2692 void radv_CmdExecuteCommands(
2693 VkCommandBuffer commandBuffer,
2694 uint32_t commandBufferCount,
2695 const VkCommandBuffer* pCmdBuffers)
2696 {
2697 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2698
2699 assert(commandBufferCount > 0);
2700
2701 /* Emit pending flushes on primary prior to executing secondary */
2702 si_emit_cache_flush(primary);
2703
2704 for (uint32_t i = 0; i < commandBufferCount; i++) {
2705 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2706
2707 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2708 secondary->scratch_size_needed);
2709 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2710 secondary->compute_scratch_size_needed);
2711
2712 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2713 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2714 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2715 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2716 if (secondary->tess_rings_needed)
2717 primary->tess_rings_needed = true;
2718 if (secondary->sample_positions_needed)
2719 primary->sample_positions_needed = true;
2720
2721 if (secondary->ring_offsets_idx != -1) {
2722 if (primary->ring_offsets_idx == -1)
2723 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2724 else
2725 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2726 }
2727 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2728
2729
2730 /* When the secondary command buffer is compute only we don't
2731 * need to re-emit the current graphics pipeline.
2732 */
2733 if (secondary->state.emitted_pipeline) {
2734 primary->state.emitted_pipeline =
2735 secondary->state.emitted_pipeline;
2736 }
2737
2738 /* When the secondary command buffer is graphics only we don't
2739 * need to re-emit the current compute pipeline.
2740 */
2741 if (secondary->state.emitted_compute_pipeline) {
2742 primary->state.emitted_compute_pipeline =
2743 secondary->state.emitted_compute_pipeline;
2744 }
2745
2746 /* Only re-emit the draw packets when needed. */
2747 if (secondary->state.last_primitive_reset_en != -1) {
2748 primary->state.last_primitive_reset_en =
2749 secondary->state.last_primitive_reset_en;
2750 }
2751
2752 if (secondary->state.last_primitive_reset_index) {
2753 primary->state.last_primitive_reset_index =
2754 secondary->state.last_primitive_reset_index;
2755 }
2756
2757 if (secondary->state.last_ia_multi_vgt_param) {
2758 primary->state.last_ia_multi_vgt_param =
2759 secondary->state.last_ia_multi_vgt_param;
2760 }
2761 }
2762
2763 /* After executing commands from secondary buffers we have to dirty
2764 * some states.
2765 */
2766 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2767 RADV_CMD_DIRTY_INDEX_BUFFER |
2768 RADV_CMD_DIRTY_DYNAMIC_ALL;
2769 radv_mark_descriptor_sets_dirty(primary);
2770 }
2771
2772 VkResult radv_CreateCommandPool(
2773 VkDevice _device,
2774 const VkCommandPoolCreateInfo* pCreateInfo,
2775 const VkAllocationCallbacks* pAllocator,
2776 VkCommandPool* pCmdPool)
2777 {
2778 RADV_FROM_HANDLE(radv_device, device, _device);
2779 struct radv_cmd_pool *pool;
2780
2781 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2782 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2783 if (pool == NULL)
2784 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2785
2786 if (pAllocator)
2787 pool->alloc = *pAllocator;
2788 else
2789 pool->alloc = device->alloc;
2790
2791 list_inithead(&pool->cmd_buffers);
2792 list_inithead(&pool->free_cmd_buffers);
2793
2794 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2795
2796 *pCmdPool = radv_cmd_pool_to_handle(pool);
2797
2798 return VK_SUCCESS;
2799
2800 }
2801
2802 void radv_DestroyCommandPool(
2803 VkDevice _device,
2804 VkCommandPool commandPool,
2805 const VkAllocationCallbacks* pAllocator)
2806 {
2807 RADV_FROM_HANDLE(radv_device, device, _device);
2808 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2809
2810 if (!pool)
2811 return;
2812
2813 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2814 &pool->cmd_buffers, pool_link) {
2815 radv_cmd_buffer_destroy(cmd_buffer);
2816 }
2817
2818 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2819 &pool->free_cmd_buffers, pool_link) {
2820 radv_cmd_buffer_destroy(cmd_buffer);
2821 }
2822
2823 vk_free2(&device->alloc, pAllocator, pool);
2824 }
2825
2826 VkResult radv_ResetCommandPool(
2827 VkDevice device,
2828 VkCommandPool commandPool,
2829 VkCommandPoolResetFlags flags)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2832 VkResult result;
2833
2834 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2835 &pool->cmd_buffers, pool_link) {
2836 result = radv_reset_cmd_buffer(cmd_buffer);
2837 if (result != VK_SUCCESS)
2838 return result;
2839 }
2840
2841 return VK_SUCCESS;
2842 }
2843
2844 void radv_TrimCommandPoolKHR(
2845 VkDevice device,
2846 VkCommandPool commandPool,
2847 VkCommandPoolTrimFlagsKHR flags)
2848 {
2849 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2850
2851 if (!pool)
2852 return;
2853
2854 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2855 &pool->free_cmd_buffers, pool_link) {
2856 radv_cmd_buffer_destroy(cmd_buffer);
2857 }
2858 }
2859
2860 void radv_CmdBeginRenderPass(
2861 VkCommandBuffer commandBuffer,
2862 const VkRenderPassBeginInfo* pRenderPassBegin,
2863 VkSubpassContents contents)
2864 {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2866 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2867 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2868
2869 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2870 cmd_buffer->cs, 2048);
2871 MAYBE_UNUSED VkResult result;
2872
2873 cmd_buffer->state.framebuffer = framebuffer;
2874 cmd_buffer->state.pass = pass;
2875 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2876
2877 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2878 if (result != VK_SUCCESS)
2879 return;
2880
2881 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2882 assert(cmd_buffer->cs->cdw <= cdw_max);
2883
2884 radv_cmd_buffer_clear_subpass(cmd_buffer);
2885 }
2886
2887 void radv_CmdNextSubpass(
2888 VkCommandBuffer commandBuffer,
2889 VkSubpassContents contents)
2890 {
2891 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2892
2893 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2894
2895 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2896 2048);
2897
2898 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2899 radv_cmd_buffer_clear_subpass(cmd_buffer);
2900 }
2901
2902 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2903 {
2904 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2905 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2906 if (!pipeline->shaders[stage])
2907 continue;
2908 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2909 if (loc->sgpr_idx == -1)
2910 continue;
2911 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2912 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2913
2914 }
2915 if (pipeline->gs_copy_shader) {
2916 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2917 if (loc->sgpr_idx != -1) {
2918 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2919 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2920 }
2921 }
2922 }
2923
2924 static void
2925 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2926 uint32_t vertex_count)
2927 {
2928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2929 radeon_emit(cmd_buffer->cs, vertex_count);
2930 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2931 S_0287F0_USE_OPAQUE(0));
2932 }
2933
2934 static void
2935 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2936 uint64_t index_va,
2937 uint32_t index_count)
2938 {
2939 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2940 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2941 radeon_emit(cmd_buffer->cs, index_va);
2942 radeon_emit(cmd_buffer->cs, index_va >> 32);
2943 radeon_emit(cmd_buffer->cs, index_count);
2944 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2945 }
2946
2947 static void
2948 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2949 bool indexed,
2950 uint32_t draw_count,
2951 uint64_t count_va,
2952 uint32_t stride)
2953 {
2954 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2955 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2956 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2957 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2958 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2959 assert(base_reg);
2960
2961 if (draw_count == 1 && !count_va && !draw_id_enable) {
2962 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2963 PKT3_DRAW_INDIRECT, 3, false));
2964 radeon_emit(cs, 0);
2965 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2966 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2967 radeon_emit(cs, di_src_sel);
2968 } else {
2969 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2970 PKT3_DRAW_INDIRECT_MULTI,
2971 8, false));
2972 radeon_emit(cs, 0);
2973 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2974 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2975 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2976 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2977 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2978 radeon_emit(cs, draw_count); /* count */
2979 radeon_emit(cs, count_va); /* count_addr */
2980 radeon_emit(cs, count_va >> 32);
2981 radeon_emit(cs, stride); /* stride */
2982 radeon_emit(cs, di_src_sel);
2983 }
2984 }
2985
2986 struct radv_draw_info {
2987 /**
2988 * Number of vertices.
2989 */
2990 uint32_t count;
2991
2992 /**
2993 * Index of the first vertex.
2994 */
2995 int32_t vertex_offset;
2996
2997 /**
2998 * First instance id.
2999 */
3000 uint32_t first_instance;
3001
3002 /**
3003 * Number of instances.
3004 */
3005 uint32_t instance_count;
3006
3007 /**
3008 * First index (indexed draws only).
3009 */
3010 uint32_t first_index;
3011
3012 /**
3013 * Whether it's an indexed draw.
3014 */
3015 bool indexed;
3016
3017 /**
3018 * Indirect draw parameters resource.
3019 */
3020 struct radv_buffer *indirect;
3021 uint64_t indirect_offset;
3022 uint32_t stride;
3023
3024 /**
3025 * Draw count parameters resource.
3026 */
3027 struct radv_buffer *count_buffer;
3028 uint64_t count_buffer_offset;
3029 };
3030
3031 static void
3032 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3033 const struct radv_draw_info *info)
3034 {
3035 struct radv_cmd_state *state = &cmd_buffer->state;
3036 struct radeon_winsys *ws = cmd_buffer->device->ws;
3037 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3038
3039 if (info->indirect) {
3040 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3041 uint64_t count_va = 0;
3042
3043 va += info->indirect->offset + info->indirect_offset;
3044
3045 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3046
3047 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3048 radeon_emit(cs, 1);
3049 radeon_emit(cs, va);
3050 radeon_emit(cs, va >> 32);
3051
3052 if (info->count_buffer) {
3053 count_va = radv_buffer_get_va(info->count_buffer->bo);
3054 count_va += info->count_buffer->offset +
3055 info->count_buffer_offset;
3056
3057 ws->cs_add_buffer(cs, info->count_buffer->bo, 8);
3058 }
3059
3060 if (!state->subpass->view_mask) {
3061 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3062 info->indexed,
3063 info->count,
3064 count_va,
3065 info->stride);
3066 } else {
3067 unsigned i;
3068 for_each_bit(i, state->subpass->view_mask) {
3069 radv_emit_view_index(cmd_buffer, i);
3070
3071 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3072 info->indexed,
3073 info->count,
3074 count_va,
3075 info->stride);
3076 }
3077 }
3078 } else {
3079 assert(state->pipeline->graphics.vtx_base_sgpr);
3080 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3081 state->pipeline->graphics.vtx_emit_num);
3082 radeon_emit(cs, info->vertex_offset);
3083 radeon_emit(cs, info->first_instance);
3084 if (state->pipeline->graphics.vtx_emit_num == 3)
3085 radeon_emit(cs, 0);
3086
3087 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3088 radeon_emit(cs, info->instance_count);
3089
3090 if (info->indexed) {
3091 int index_size = state->index_type ? 4 : 2;
3092 uint64_t index_va;
3093
3094 index_va = state->index_va;
3095 index_va += info->first_index * index_size;
3096
3097 if (!state->subpass->view_mask) {
3098 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3099 index_va,
3100 info->count);
3101 } else {
3102 unsigned i;
3103 for_each_bit(i, state->subpass->view_mask) {
3104 radv_emit_view_index(cmd_buffer, i);
3105
3106 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3107 index_va,
3108 info->count);
3109 }
3110 }
3111 } else {
3112 if (!state->subpass->view_mask) {
3113 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3114 } else {
3115 unsigned i;
3116 for_each_bit(i, state->subpass->view_mask) {
3117 radv_emit_view_index(cmd_buffer, i);
3118
3119 radv_cs_emit_draw_packet(cmd_buffer,
3120 info->count);
3121 }
3122 }
3123 }
3124 }
3125 }
3126
3127 static void
3128 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3129 const struct radv_draw_info *info)
3130 {
3131 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3132 radv_emit_graphics_pipeline(cmd_buffer);
3133
3134 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3135 radv_emit_framebuffer_state(cmd_buffer);
3136
3137 if (info->indexed) {
3138 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3139 radv_emit_index_buffer(cmd_buffer);
3140 } else {
3141 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3142 * so the state must be re-emitted before the next indexed
3143 * draw.
3144 */
3145 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3146 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3147 }
3148
3149 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3150
3151 radv_emit_draw_registers(cmd_buffer, info->indexed,
3152 info->instance_count > 1, info->indirect,
3153 info->indirect ? 0 : info->count);
3154
3155 cmd_buffer->state.dirty = 0;
3156 }
3157
3158 static void
3159 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3160 const struct radv_draw_info *info)
3161 {
3162 bool pipeline_is_dirty =
3163 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3164 cmd_buffer->state.pipeline &&
3165 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3166
3167 MAYBE_UNUSED unsigned cdw_max =
3168 radeon_check_space(cmd_buffer->device->ws,
3169 cmd_buffer->cs, 4096);
3170
3171 /* Use optimal packet order based on whether we need to sync the
3172 * pipeline.
3173 */
3174 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3175 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3176 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3177 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3178 /* If we have to wait for idle, set all states first, so that
3179 * all SET packets are processed in parallel with previous draw
3180 * calls. Then upload descriptors, set shader pointers, and
3181 * draw, and prefetch at the end. This ensures that the time
3182 * the CUs are idle is very short. (there are only SET_SH
3183 * packets between the wait and the draw)
3184 */
3185 radv_emit_all_graphics_states(cmd_buffer, info);
3186 si_emit_cache_flush(cmd_buffer);
3187 /* <-- CUs are idle here --> */
3188
3189 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3190 return;
3191
3192 radv_emit_draw_packets(cmd_buffer, info);
3193 /* <-- CUs are busy here --> */
3194
3195 /* Start prefetches after the draw has been started. Both will
3196 * run in parallel, but starting the draw first is more
3197 * important.
3198 */
3199 if (pipeline_is_dirty) {
3200 radv_emit_shaders_prefetch(cmd_buffer,
3201 cmd_buffer->state.pipeline);
3202 }
3203 } else {
3204 /* If we don't wait for idle, start prefetches first, then set
3205 * states, and draw at the end.
3206 */
3207 si_emit_cache_flush(cmd_buffer);
3208
3209 if (pipeline_is_dirty) {
3210 radv_emit_shaders_prefetch(cmd_buffer,
3211 cmd_buffer->state.pipeline);
3212 }
3213
3214 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3215 return;
3216
3217 radv_emit_all_graphics_states(cmd_buffer, info);
3218 radv_emit_draw_packets(cmd_buffer, info);
3219 }
3220
3221 assert(cmd_buffer->cs->cdw <= cdw_max);
3222 radv_cmd_buffer_after_draw(cmd_buffer);
3223 }
3224
3225 void radv_CmdDraw(
3226 VkCommandBuffer commandBuffer,
3227 uint32_t vertexCount,
3228 uint32_t instanceCount,
3229 uint32_t firstVertex,
3230 uint32_t firstInstance)
3231 {
3232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3233 struct radv_draw_info info = {};
3234
3235 info.count = vertexCount;
3236 info.instance_count = instanceCount;
3237 info.first_instance = firstInstance;
3238 info.vertex_offset = firstVertex;
3239
3240 radv_draw(cmd_buffer, &info);
3241 }
3242
3243 void radv_CmdDrawIndexed(
3244 VkCommandBuffer commandBuffer,
3245 uint32_t indexCount,
3246 uint32_t instanceCount,
3247 uint32_t firstIndex,
3248 int32_t vertexOffset,
3249 uint32_t firstInstance)
3250 {
3251 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3252 struct radv_draw_info info = {};
3253
3254 info.indexed = true;
3255 info.count = indexCount;
3256 info.instance_count = instanceCount;
3257 info.first_index = firstIndex;
3258 info.vertex_offset = vertexOffset;
3259 info.first_instance = firstInstance;
3260
3261 radv_draw(cmd_buffer, &info);
3262 }
3263
3264 void radv_CmdDrawIndirect(
3265 VkCommandBuffer commandBuffer,
3266 VkBuffer _buffer,
3267 VkDeviceSize offset,
3268 uint32_t drawCount,
3269 uint32_t stride)
3270 {
3271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3272 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3273 struct radv_draw_info info = {};
3274
3275 info.count = drawCount;
3276 info.indirect = buffer;
3277 info.indirect_offset = offset;
3278 info.stride = stride;
3279
3280 radv_draw(cmd_buffer, &info);
3281 }
3282
3283 void radv_CmdDrawIndexedIndirect(
3284 VkCommandBuffer commandBuffer,
3285 VkBuffer _buffer,
3286 VkDeviceSize offset,
3287 uint32_t drawCount,
3288 uint32_t stride)
3289 {
3290 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3291 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3292 struct radv_draw_info info = {};
3293
3294 info.indexed = true;
3295 info.count = drawCount;
3296 info.indirect = buffer;
3297 info.indirect_offset = offset;
3298 info.stride = stride;
3299
3300 radv_draw(cmd_buffer, &info);
3301 }
3302
3303 void radv_CmdDrawIndirectCountAMD(
3304 VkCommandBuffer commandBuffer,
3305 VkBuffer _buffer,
3306 VkDeviceSize offset,
3307 VkBuffer _countBuffer,
3308 VkDeviceSize countBufferOffset,
3309 uint32_t maxDrawCount,
3310 uint32_t stride)
3311 {
3312 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3313 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3314 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3315 struct radv_draw_info info = {};
3316
3317 info.count = maxDrawCount;
3318 info.indirect = buffer;
3319 info.indirect_offset = offset;
3320 info.count_buffer = count_buffer;
3321 info.count_buffer_offset = countBufferOffset;
3322 info.stride = stride;
3323
3324 radv_draw(cmd_buffer, &info);
3325 }
3326
3327 void radv_CmdDrawIndexedIndirectCountAMD(
3328 VkCommandBuffer commandBuffer,
3329 VkBuffer _buffer,
3330 VkDeviceSize offset,
3331 VkBuffer _countBuffer,
3332 VkDeviceSize countBufferOffset,
3333 uint32_t maxDrawCount,
3334 uint32_t stride)
3335 {
3336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3337 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3338 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3339 struct radv_draw_info info = {};
3340
3341 info.indexed = true;
3342 info.count = maxDrawCount;
3343 info.indirect = buffer;
3344 info.indirect_offset = offset;
3345 info.count_buffer = count_buffer;
3346 info.count_buffer_offset = countBufferOffset;
3347 info.stride = stride;
3348
3349 radv_draw(cmd_buffer, &info);
3350 }
3351
3352 struct radv_dispatch_info {
3353 /**
3354 * Determine the layout of the grid (in block units) to be used.
3355 */
3356 uint32_t blocks[3];
3357
3358 /**
3359 * Whether it's an unaligned compute dispatch.
3360 */
3361 bool unaligned;
3362
3363 /**
3364 * Indirect compute parameters resource.
3365 */
3366 struct radv_buffer *indirect;
3367 uint64_t indirect_offset;
3368 };
3369
3370 static void
3371 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3372 const struct radv_dispatch_info *info)
3373 {
3374 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3375 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3376 struct radeon_winsys *ws = cmd_buffer->device->ws;
3377 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3378 struct ac_userdata_info *loc;
3379 unsigned dispatch_initiator;
3380 uint8_t grid_used;
3381
3382 grid_used = compute_shader->info.info.cs.grid_components_used;
3383
3384 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3385 AC_UD_CS_GRID_SIZE);
3386
3387 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3388
3389 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3390 S_00B800_FORCE_START_AT_000(1);
3391
3392 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3393 /* If the KMD allows it (there is a KMD hw register for it),
3394 * allow launching waves out-of-order.
3395 */
3396 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3397 }
3398
3399 if (info->indirect) {
3400 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3401
3402 va += info->indirect->offset + info->indirect_offset;
3403
3404 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3405
3406 if (loc->sgpr_idx != -1) {
3407 for (unsigned i = 0; i < grid_used; ++i) {
3408 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3409 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3410 COPY_DATA_DST_SEL(COPY_DATA_REG));
3411 radeon_emit(cs, (va + 4 * i));
3412 radeon_emit(cs, (va + 4 * i) >> 32);
3413 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3414 + loc->sgpr_idx * 4) >> 2) + i);
3415 radeon_emit(cs, 0);
3416 }
3417 }
3418
3419 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3420 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3421 PKT3_SHADER_TYPE_S(1));
3422 radeon_emit(cs, va);
3423 radeon_emit(cs, va >> 32);
3424 radeon_emit(cs, dispatch_initiator);
3425 } else {
3426 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3427 PKT3_SHADER_TYPE_S(1));
3428 radeon_emit(cs, 1);
3429 radeon_emit(cs, va);
3430 radeon_emit(cs, va >> 32);
3431
3432 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3433 PKT3_SHADER_TYPE_S(1));
3434 radeon_emit(cs, 0);
3435 radeon_emit(cs, dispatch_initiator);
3436 }
3437 } else {
3438 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3439
3440 if (info->unaligned) {
3441 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3442 unsigned remainder[3];
3443
3444 /* If aligned, these should be an entire block size,
3445 * not 0.
3446 */
3447 remainder[0] = blocks[0] + cs_block_size[0] -
3448 align_u32_npot(blocks[0], cs_block_size[0]);
3449 remainder[1] = blocks[1] + cs_block_size[1] -
3450 align_u32_npot(blocks[1], cs_block_size[1]);
3451 remainder[2] = blocks[2] + cs_block_size[2] -
3452 align_u32_npot(blocks[2], cs_block_size[2]);
3453
3454 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3455 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3456 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3457
3458 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3459 radeon_emit(cs,
3460 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3461 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3462 radeon_emit(cs,
3463 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3464 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3465 radeon_emit(cs,
3466 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3467 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3468
3469 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3470 }
3471
3472 if (loc->sgpr_idx != -1) {
3473 assert(!loc->indirect);
3474 assert(loc->num_sgprs == grid_used);
3475
3476 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3477 loc->sgpr_idx * 4, grid_used);
3478 radeon_emit(cs, blocks[0]);
3479 if (grid_used > 1)
3480 radeon_emit(cs, blocks[1]);
3481 if (grid_used > 2)
3482 radeon_emit(cs, blocks[2]);
3483 }
3484
3485 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3486 PKT3_SHADER_TYPE_S(1));
3487 radeon_emit(cs, blocks[0]);
3488 radeon_emit(cs, blocks[1]);
3489 radeon_emit(cs, blocks[2]);
3490 radeon_emit(cs, dispatch_initiator);
3491 }
3492
3493 assert(cmd_buffer->cs->cdw <= cdw_max);
3494 }
3495
3496 static void
3497 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3498 const struct radv_dispatch_info *info)
3499 {
3500 radv_emit_compute_pipeline(cmd_buffer);
3501
3502 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3503 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3504 VK_SHADER_STAGE_COMPUTE_BIT);
3505
3506 si_emit_cache_flush(cmd_buffer);
3507
3508 radv_emit_dispatch_packets(cmd_buffer, info);
3509
3510 radv_cmd_buffer_after_draw(cmd_buffer);
3511 }
3512
3513 void radv_CmdDispatch(
3514 VkCommandBuffer commandBuffer,
3515 uint32_t x,
3516 uint32_t y,
3517 uint32_t z)
3518 {
3519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3520 struct radv_dispatch_info info = {};
3521
3522 info.blocks[0] = x;
3523 info.blocks[1] = y;
3524 info.blocks[2] = z;
3525
3526 radv_dispatch(cmd_buffer, &info);
3527 }
3528
3529 void radv_CmdDispatchIndirect(
3530 VkCommandBuffer commandBuffer,
3531 VkBuffer _buffer,
3532 VkDeviceSize offset)
3533 {
3534 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3535 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3536 struct radv_dispatch_info info = {};
3537
3538 info.indirect = buffer;
3539 info.indirect_offset = offset;
3540
3541 radv_dispatch(cmd_buffer, &info);
3542 }
3543
3544 void radv_unaligned_dispatch(
3545 struct radv_cmd_buffer *cmd_buffer,
3546 uint32_t x,
3547 uint32_t y,
3548 uint32_t z)
3549 {
3550 struct radv_dispatch_info info = {};
3551
3552 info.blocks[0] = x;
3553 info.blocks[1] = y;
3554 info.blocks[2] = z;
3555 info.unaligned = 1;
3556
3557 radv_dispatch(cmd_buffer, &info);
3558 }
3559
3560 void radv_CmdEndRenderPass(
3561 VkCommandBuffer commandBuffer)
3562 {
3563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3564
3565 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3566
3567 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3568
3569 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3570 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3571 radv_handle_subpass_image_transition(cmd_buffer,
3572 (VkAttachmentReference){i, layout});
3573 }
3574
3575 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3576
3577 cmd_buffer->state.pass = NULL;
3578 cmd_buffer->state.subpass = NULL;
3579 cmd_buffer->state.attachments = NULL;
3580 cmd_buffer->state.framebuffer = NULL;
3581 }
3582
3583 /*
3584 * For HTILE we have the following interesting clear words:
3585 * 0x0000030f: Uncompressed.
3586 * 0xfffffff0: Clear depth to 1.0
3587 * 0x00000000: Clear depth to 0.0
3588 */
3589 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3590 struct radv_image *image,
3591 const VkImageSubresourceRange *range,
3592 uint32_t clear_word)
3593 {
3594 assert(range->baseMipLevel == 0);
3595 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3596 unsigned layer_count = radv_get_layerCount(image, range);
3597 uint64_t size = image->surface.htile_slice_size * layer_count;
3598 uint64_t offset = image->offset + image->htile_offset +
3599 image->surface.htile_slice_size * range->baseArrayLayer;
3600
3601 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3602 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3603
3604 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3605
3606 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3607 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3608 RADV_CMD_FLAG_INV_VMEM_L1 |
3609 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3610 }
3611
3612 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3613 struct radv_image *image,
3614 VkImageLayout src_layout,
3615 VkImageLayout dst_layout,
3616 unsigned src_queue_mask,
3617 unsigned dst_queue_mask,
3618 const VkImageSubresourceRange *range,
3619 VkImageAspectFlags pending_clears)
3620 {
3621 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3622 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3623 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3624 cmd_buffer->state.render_area.extent.width == image->info.width &&
3625 cmd_buffer->state.render_area.extent.height == image->info.height) {
3626 /* The clear will initialize htile. */
3627 return;
3628 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3629 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3630 /* TODO: merge with the clear if applicable */
3631 radv_initialize_htile(cmd_buffer, image, range, 0);
3632 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3633 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3634 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3635 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3636 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3637 VkImageSubresourceRange local_range = *range;
3638 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3639 local_range.baseMipLevel = 0;
3640 local_range.levelCount = 1;
3641
3642 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3643 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3644
3645 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3646
3647 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3648 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3649 }
3650 }
3651
3652 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3653 struct radv_image *image, uint32_t value)
3654 {
3655 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3656 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3657
3658 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3659 image->cmask.size, value);
3660
3661 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3662 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3663 RADV_CMD_FLAG_INV_VMEM_L1 |
3664 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3665 }
3666
3667 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3668 struct radv_image *image,
3669 VkImageLayout src_layout,
3670 VkImageLayout dst_layout,
3671 unsigned src_queue_mask,
3672 unsigned dst_queue_mask,
3673 const VkImageSubresourceRange *range)
3674 {
3675 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3676 if (image->fmask.size)
3677 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3678 else
3679 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3680 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3681 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3682 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3683 }
3684 }
3685
3686 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3687 struct radv_image *image, uint32_t value)
3688 {
3689
3690 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3691 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3692
3693 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3694 image->surface.dcc_size, value);
3695
3696 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3697 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3698 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3699 RADV_CMD_FLAG_INV_VMEM_L1 |
3700 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3701 }
3702
3703 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3704 struct radv_image *image,
3705 VkImageLayout src_layout,
3706 VkImageLayout dst_layout,
3707 unsigned src_queue_mask,
3708 unsigned dst_queue_mask,
3709 const VkImageSubresourceRange *range)
3710 {
3711 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3712 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3713 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3714 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3715 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3716 }
3717 }
3718
3719 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3720 struct radv_image *image,
3721 VkImageLayout src_layout,
3722 VkImageLayout dst_layout,
3723 uint32_t src_family,
3724 uint32_t dst_family,
3725 const VkImageSubresourceRange *range,
3726 VkImageAspectFlags pending_clears)
3727 {
3728 if (image->exclusive && src_family != dst_family) {
3729 /* This is an acquire or a release operation and there will be
3730 * a corresponding release/acquire. Do the transition in the
3731 * most flexible queue. */
3732
3733 assert(src_family == cmd_buffer->queue_family_index ||
3734 dst_family == cmd_buffer->queue_family_index);
3735
3736 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3737 return;
3738
3739 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3740 (src_family == RADV_QUEUE_GENERAL ||
3741 dst_family == RADV_QUEUE_GENERAL))
3742 return;
3743 }
3744
3745 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3746 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3747
3748 if (image->surface.htile_size)
3749 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3750 dst_layout, src_queue_mask,
3751 dst_queue_mask, range,
3752 pending_clears);
3753
3754 if (image->cmask.size || image->fmask.size)
3755 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3756 dst_layout, src_queue_mask,
3757 dst_queue_mask, range);
3758
3759 if (image->surface.dcc_size)
3760 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3761 dst_layout, src_queue_mask,
3762 dst_queue_mask, range);
3763 }
3764
3765 void radv_CmdPipelineBarrier(
3766 VkCommandBuffer commandBuffer,
3767 VkPipelineStageFlags srcStageMask,
3768 VkPipelineStageFlags destStageMask,
3769 VkBool32 byRegion,
3770 uint32_t memoryBarrierCount,
3771 const VkMemoryBarrier* pMemoryBarriers,
3772 uint32_t bufferMemoryBarrierCount,
3773 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3774 uint32_t imageMemoryBarrierCount,
3775 const VkImageMemoryBarrier* pImageMemoryBarriers)
3776 {
3777 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3778 enum radv_cmd_flush_bits src_flush_bits = 0;
3779 enum radv_cmd_flush_bits dst_flush_bits = 0;
3780
3781 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3782 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3783 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3784 NULL);
3785 }
3786
3787 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3788 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3789 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3790 NULL);
3791 }
3792
3793 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3794 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3795 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3796 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3797 image);
3798 }
3799
3800 radv_stage_flush(cmd_buffer, srcStageMask);
3801 cmd_buffer->state.flush_bits |= src_flush_bits;
3802
3803 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3804 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3805 radv_handle_image_transition(cmd_buffer, image,
3806 pImageMemoryBarriers[i].oldLayout,
3807 pImageMemoryBarriers[i].newLayout,
3808 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3809 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3810 &pImageMemoryBarriers[i].subresourceRange,
3811 0);
3812 }
3813
3814 cmd_buffer->state.flush_bits |= dst_flush_bits;
3815 }
3816
3817
3818 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3819 struct radv_event *event,
3820 VkPipelineStageFlags stageMask,
3821 unsigned value)
3822 {
3823 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3824 uint64_t va = radv_buffer_get_va(event->bo);
3825
3826 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3827
3828 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3829
3830 /* TODO: this is overkill. Probably should figure something out from
3831 * the stage mask. */
3832
3833 si_cs_emit_write_event_eop(cs,
3834 cmd_buffer->state.predicating,
3835 cmd_buffer->device->physical_device->rad_info.chip_class,
3836 false,
3837 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3838 1, va, 2, value);
3839
3840 assert(cmd_buffer->cs->cdw <= cdw_max);
3841 }
3842
3843 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3844 VkEvent _event,
3845 VkPipelineStageFlags stageMask)
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3848 RADV_FROM_HANDLE(radv_event, event, _event);
3849
3850 write_event(cmd_buffer, event, stageMask, 1);
3851 }
3852
3853 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3854 VkEvent _event,
3855 VkPipelineStageFlags stageMask)
3856 {
3857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3858 RADV_FROM_HANDLE(radv_event, event, _event);
3859
3860 write_event(cmd_buffer, event, stageMask, 0);
3861 }
3862
3863 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3864 uint32_t eventCount,
3865 const VkEvent* pEvents,
3866 VkPipelineStageFlags srcStageMask,
3867 VkPipelineStageFlags dstStageMask,
3868 uint32_t memoryBarrierCount,
3869 const VkMemoryBarrier* pMemoryBarriers,
3870 uint32_t bufferMemoryBarrierCount,
3871 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3872 uint32_t imageMemoryBarrierCount,
3873 const VkImageMemoryBarrier* pImageMemoryBarriers)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3877
3878 for (unsigned i = 0; i < eventCount; ++i) {
3879 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3880 uint64_t va = radv_buffer_get_va(event->bo);
3881
3882 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3883
3884 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3885
3886 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3887 assert(cmd_buffer->cs->cdw <= cdw_max);
3888 }
3889
3890
3891 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3892 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3893
3894 radv_handle_image_transition(cmd_buffer, image,
3895 pImageMemoryBarriers[i].oldLayout,
3896 pImageMemoryBarriers[i].newLayout,
3897 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3898 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3899 &pImageMemoryBarriers[i].subresourceRange,
3900 0);
3901 }
3902
3903 /* TODO: figure out how to do memory barriers without waiting */
3904 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3905 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3906 RADV_CMD_FLAG_INV_VMEM_L1 |
3907 RADV_CMD_FLAG_INV_SMEM_L1;
3908 }