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8c5c75d3cb6d2671ae4e2c23d093f17759be8418
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 if (stage == MESA_SHADER_VERTEX) {
497 if (pipeline->shaders[MESA_SHADER_VERTEX])
498 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
499 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
500 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
501 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
502 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
503 } else if (stage == MESA_SHADER_TESS_EVAL) {
504 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
505 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
506 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
507 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
508 }
509 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
510 }
511
512 static void
513 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
514 struct radv_pipeline *pipeline,
515 gl_shader_stage stage,
516 int idx, uint64_t va)
517 {
518 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
519 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
520 if (loc->sgpr_idx == -1)
521 return;
522 assert(loc->num_sgprs == 2);
523 assert(!loc->indirect);
524 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
525 radeon_emit(cmd_buffer->cs, va);
526 radeon_emit(cmd_buffer->cs, va >> 32);
527 }
528
529 static void
530 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 int num_samples = pipeline->graphics.ms.num_samples;
534 struct radv_multisample_state *ms = &pipeline->graphics.ms;
535 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
536
537 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
538 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
539 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
540
541 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
542 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
543
544 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
545 return;
546
547 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
548 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
549 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
550
551 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
552
553 /* GFX9: Flush DFSM when the AA mode changes. */
554 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
555 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
556 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
557 }
558 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
559 uint32_t offset;
560 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
561 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
562 if (loc->sgpr_idx == -1)
563 return;
564 assert(loc->num_sgprs == 1);
565 assert(!loc->indirect);
566 switch (num_samples) {
567 default:
568 offset = 0;
569 break;
570 case 2:
571 offset = 1;
572 break;
573 case 4:
574 offset = 3;
575 break;
576 case 8:
577 offset = 7;
578 break;
579 case 16:
580 offset = 15;
581 break;
582 }
583
584 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
585 cmd_buffer->sample_positions_needed = true;
586 }
587 }
588
589 static void
590 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline)
592 {
593 struct radv_raster_state *raster = &pipeline->graphics.raster;
594
595 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
596 raster->pa_cl_clip_cntl);
597 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
598 raster->spi_interp_control);
599 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
600 raster->pa_su_vtx_cntl);
601 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
602 raster->pa_su_sc_mode_cntl);
603 }
604
605 static inline void
606 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
607 unsigned size)
608 {
609 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
610 si_cp_dma_prefetch(cmd_buffer, va, size);
611 }
612
613 static void
614 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline,
616 struct radv_shader_variant *shader,
617 struct ac_vs_output_info *outinfo)
618 {
619 struct radeon_winsys *ws = cmd_buffer->device->ws;
620 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
621 unsigned export_count;
622
623 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
624 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
625
626 export_count = MAX2(1, outinfo->param_exports);
627 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
628 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
629
630 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
631 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
632 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
633 V_02870C_SPI_SHADER_4COMP :
634 V_02870C_SPI_SHADER_NONE) |
635 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
636 V_02870C_SPI_SHADER_4COMP :
637 V_02870C_SPI_SHADER_NONE) |
638 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
639 V_02870C_SPI_SHADER_4COMP :
640 V_02870C_SPI_SHADER_NONE));
641
642
643 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
644 radeon_emit(cmd_buffer->cs, va >> 8);
645 radeon_emit(cmd_buffer->cs, va >> 40);
646 radeon_emit(cmd_buffer->cs, shader->rsrc1);
647 radeon_emit(cmd_buffer->cs, shader->rsrc2);
648
649 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
650 S_028818_VTX_W0_FMT(1) |
651 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
652 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
653 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
654
655
656 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
657 pipeline->graphics.pa_cl_vs_out_cntl);
658
659 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
660 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
661 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
662 }
663
664 static void
665 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
666 struct radv_shader_variant *shader,
667 struct ac_es_output_info *outinfo)
668 {
669 struct radeon_winsys *ws = cmd_buffer->device->ws;
670 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
671
672 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
673 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
674
675 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
676 outinfo->esgs_itemsize / 4);
677 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
678 radeon_emit(cmd_buffer->cs, va >> 8);
679 radeon_emit(cmd_buffer->cs, va >> 40);
680 radeon_emit(cmd_buffer->cs, shader->rsrc1);
681 radeon_emit(cmd_buffer->cs, shader->rsrc2);
682 }
683
684 static void
685 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
686 struct radv_shader_variant *shader)
687 {
688 struct radeon_winsys *ws = cmd_buffer->device->ws;
689 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
690 uint32_t rsrc2 = shader->rsrc2;
691
692 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
693 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
694
695 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
696 radeon_emit(cmd_buffer->cs, va >> 8);
697 radeon_emit(cmd_buffer->cs, va >> 40);
698
699 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
700 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
701 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
702 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
703
704 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
705 radeon_emit(cmd_buffer->cs, shader->rsrc1);
706 radeon_emit(cmd_buffer->cs, rsrc2);
707 }
708
709 static void
710 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
711 struct radv_shader_variant *shader)
712 {
713 struct radeon_winsys *ws = cmd_buffer->device->ws;
714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
715
716 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
717 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
718
719 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
720 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
721 radeon_emit(cmd_buffer->cs, va >> 8);
722 radeon_emit(cmd_buffer->cs, va >> 40);
723
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
727 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
728 } else {
729 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
730 radeon_emit(cmd_buffer->cs, va >> 8);
731 radeon_emit(cmd_buffer->cs, va >> 40);
732 radeon_emit(cmd_buffer->cs, shader->rsrc1);
733 radeon_emit(cmd_buffer->cs, shader->rsrc2);
734 }
735 }
736
737 static void
738 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
739 struct radv_pipeline *pipeline)
740 {
741 struct radv_shader_variant *vs;
742
743 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
744
745 /* Skip shaders merged into HS/GS */
746 vs = pipeline->shaders[MESA_SHADER_VERTEX];
747 if (!vs)
748 return;
749
750 if (vs->info.vs.as_ls)
751 radv_emit_hw_ls(cmd_buffer, vs);
752 else if (vs->info.vs.as_es)
753 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
754 else
755 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
756 }
757
758
759 static void
760 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_pipeline *pipeline)
762 {
763 if (!radv_pipeline_has_tess(pipeline))
764 return;
765
766 struct radv_shader_variant *tes, *tcs;
767
768 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
769 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
770
771 if (tes) {
772 if (tes->info.tes.as_es)
773 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
774 else
775 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
776 }
777
778 radv_emit_hw_hs(cmd_buffer, tcs);
779
780 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
781 pipeline->graphics.tess.tf_param);
782
783 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
784 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
785 pipeline->graphics.tess.ls_hs_config);
786 else
787 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
788 pipeline->graphics.tess.ls_hs_config);
789
790 struct ac_userdata_info *loc;
791
792 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
793 if (loc->sgpr_idx != -1) {
794 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
795 assert(loc->num_sgprs == 4);
796 assert(!loc->indirect);
797 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
798 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
799 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
800 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
801 pipeline->graphics.tess.num_tcs_input_cp << 26);
802 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
803 }
804
805 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
806 if (loc->sgpr_idx != -1) {
807 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
808 assert(loc->num_sgprs == 1);
809 assert(!loc->indirect);
810
811 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
812 pipeline->graphics.tess.offchip_layout);
813 }
814
815 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
816 if (loc->sgpr_idx != -1) {
817 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
818 assert(loc->num_sgprs == 1);
819 assert(!loc->indirect);
820
821 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
822 pipeline->graphics.tess.tcs_in_layout);
823 }
824 }
825
826 static void
827 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
828 struct radv_pipeline *pipeline)
829 {
830 struct radeon_winsys *ws = cmd_buffer->device->ws;
831 struct radv_shader_variant *gs;
832 uint64_t va;
833
834 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
835
836 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
837 if (!gs)
838 return;
839
840 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
841
842 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
843 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
844 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
845 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
848
849 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
850
851 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
852 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
853 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
854 radeon_emit(cmd_buffer->cs, 0);
855 radeon_emit(cmd_buffer->cs, 0);
856 radeon_emit(cmd_buffer->cs, 0);
857
858 uint32_t gs_num_invocations = gs->info.gs.invocations;
859 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
860 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
861 S_028B90_ENABLE(gs_num_invocations > 0));
862
863 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
864 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
865 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
866
867 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
868 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
869 radeon_emit(cmd_buffer->cs, va >> 8);
870 radeon_emit(cmd_buffer->cs, va >> 40);
871
872 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
873 radeon_emit(cmd_buffer->cs, gs->rsrc1);
874 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
875 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
876
877 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
878 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
879 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize);
880 } else {
881 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
882 radeon_emit(cmd_buffer->cs, va >> 8);
883 radeon_emit(cmd_buffer->cs, va >> 40);
884 radeon_emit(cmd_buffer->cs, gs->rsrc1);
885 radeon_emit(cmd_buffer->cs, gs->rsrc2);
886 }
887
888 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
889
890 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
891 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
892 if (loc->sgpr_idx != -1) {
893 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
894 uint32_t num_entries = 64;
895 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
896
897 if (is_vi)
898 num_entries *= stride;
899
900 stride = S_008F04_STRIDE(stride);
901 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
902 radeon_emit(cmd_buffer->cs, stride);
903 radeon_emit(cmd_buffer->cs, num_entries);
904 }
905 }
906
907 static void
908 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
909 struct radv_pipeline *pipeline)
910 {
911 struct radeon_winsys *ws = cmd_buffer->device->ws;
912 struct radv_shader_variant *ps;
913 uint64_t va;
914 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
915 struct radv_blend_state *blend = &pipeline->graphics.blend;
916 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
917
918 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
919 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
920 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
921 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
922
923 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
924 radeon_emit(cmd_buffer->cs, va >> 8);
925 radeon_emit(cmd_buffer->cs, va >> 40);
926 radeon_emit(cmd_buffer->cs, ps->rsrc1);
927 radeon_emit(cmd_buffer->cs, ps->rsrc2);
928
929 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
930 pipeline->graphics.db_shader_control);
931
932 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
933 ps->config.spi_ps_input_ena);
934
935 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
936 ps->config.spi_ps_input_addr);
937
938 if (ps->info.info.ps.force_persample)
939 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
940
941 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
942 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
943
944 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
947 pipeline->graphics.shader_z_format);
948
949 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
952 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
953
954 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
955 /* optimise this? */
956 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
957 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
958 }
959
960 if (pipeline->graphics.ps_input_cntl_num) {
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
962 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
963 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
964 }
965 }
966 }
967
968 static void
969 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
970 struct radv_pipeline *pipeline)
971 {
972 struct radeon_winsys_cs *cs = cmd_buffer->cs;
973
974 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
975 return;
976
977 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
978 pipeline->graphics.vtx_reuse_depth);
979 }
980
981 static void
982 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
983 {
984 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
985
986 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
987 return;
988
989 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
990 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
991 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
992 radv_update_multisample_state(cmd_buffer, pipeline);
993 radv_emit_vertex_shader(cmd_buffer, pipeline);
994 radv_emit_tess_shaders(cmd_buffer, pipeline);
995 radv_emit_geometry_shader(cmd_buffer, pipeline);
996 radv_emit_fragment_shader(cmd_buffer, pipeline);
997 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
998
999 cmd_buffer->scratch_size_needed =
1000 MAX2(cmd_buffer->scratch_size_needed,
1001 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1002
1003 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1004 S_0286E8_WAVES(pipeline->max_waves) |
1005 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1006
1007 if (!cmd_buffer->state.emitted_pipeline ||
1008 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1009 pipeline->graphics.can_use_guardband)
1010 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1013
1014 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1015 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1016 } else {
1017 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1018 }
1019 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1020
1021 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1022
1023 cmd_buffer->state.emitted_pipeline = pipeline;
1024 }
1025
1026 static void
1027 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1028 {
1029 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1030 cmd_buffer->state.dynamic.viewport.viewports);
1031 }
1032
1033 static void
1034 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1035 {
1036 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1037
1038 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1039 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1040 si_emit_cache_flush(cmd_buffer);
1041 }
1042 si_write_scissors(cmd_buffer->cs, 0, count,
1043 cmd_buffer->state.dynamic.scissor.scissors,
1044 cmd_buffer->state.dynamic.viewport.viewports,
1045 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1046 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1047 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1048 }
1049
1050 static void
1051 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1052 {
1053 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1054
1055 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1056 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1057 }
1058
1059 static void
1060 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1061 {
1062 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1063
1064 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1065 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1066 }
1067
1068 static void
1069 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1070 {
1071 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1072
1073 radeon_set_context_reg_seq(cmd_buffer->cs,
1074 R_028430_DB_STENCILREFMASK, 2);
1075 radeon_emit(cmd_buffer->cs,
1076 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1077 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1078 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1079 S_028430_STENCILOPVAL(1));
1080 radeon_emit(cmd_buffer->cs,
1081 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1082 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1083 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1084 S_028434_STENCILOPVAL_BF(1));
1085 }
1086
1087 static void
1088 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1089 {
1090 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1091
1092 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1093 fui(d->depth_bounds.min));
1094 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1095 fui(d->depth_bounds.max));
1096 }
1097
1098 static void
1099 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1100 {
1101 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1102 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1103 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1104 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1105
1106 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1107 radeon_set_context_reg_seq(cmd_buffer->cs,
1108 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1109 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1110 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1111 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1112 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1113 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1114 }
1115 }
1116
1117 static void
1118 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1119 int index,
1120 struct radv_color_buffer_info *cb)
1121 {
1122 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1123
1124 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1125 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1126 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1127 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1128 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1129 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1130 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1131 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1132 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1133 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1134 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1135 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1136 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1137
1138 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1139 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1140 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1141
1142 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1143 cb->gfx9_epitch);
1144 } else {
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1146 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1147 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1148 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1149 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1150 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1151 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1152 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1153 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1154 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1155 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1156 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1157
1158 if (is_vi) { /* DCC BASE */
1159 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1160 }
1161 }
1162 }
1163
1164 static void
1165 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1166 struct radv_ds_buffer_info *ds,
1167 struct radv_image *image,
1168 VkImageLayout layout)
1169 {
1170 uint32_t db_z_info = ds->db_z_info;
1171 uint32_t db_stencil_info = ds->db_stencil_info;
1172
1173 if (!radv_layout_has_htile(image, layout,
1174 radv_image_queue_family_mask(image,
1175 cmd_buffer->queue_family_index,
1176 cmd_buffer->queue_family_index))) {
1177 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1178 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1179 }
1180
1181 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1182 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1183
1184
1185 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1186 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1187 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1188 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1189 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1190
1191 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1192 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1193 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1194 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1196 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1198 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1199 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1200 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1201 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1202
1203 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1204 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1205 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1206 } else {
1207 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1208
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1210 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1211 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1212 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1213 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1214 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1215 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1216 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1217 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1218 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1219
1220 }
1221
1222 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1223 ds->pa_su_poly_offset_db_fmt_cntl);
1224 }
1225
1226 void
1227 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1228 struct radv_image *image,
1229 VkClearDepthStencilValue ds_clear_value,
1230 VkImageAspectFlags aspects)
1231 {
1232 uint64_t va = radv_buffer_get_va(image->bo);
1233 va += image->offset + image->clear_value_offset;
1234 unsigned reg_offset = 0, reg_count = 0;
1235
1236 if (!image->surface.htile_size || !aspects)
1237 return;
1238
1239 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1240 ++reg_count;
1241 } else {
1242 ++reg_offset;
1243 va += 4;
1244 }
1245 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1246 ++reg_count;
1247
1248 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1249
1250 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1251 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1252 S_370_WR_CONFIRM(1) |
1253 S_370_ENGINE_SEL(V_370_PFP));
1254 radeon_emit(cmd_buffer->cs, va);
1255 radeon_emit(cmd_buffer->cs, va >> 32);
1256 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1257 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1258 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1259 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1260
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1262 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1263 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1264 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1265 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1266 }
1267
1268 static void
1269 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1270 struct radv_image *image)
1271 {
1272 uint64_t va = radv_buffer_get_va(image->bo);
1273 va += image->offset + image->clear_value_offset;
1274
1275 if (!image->surface.htile_size)
1276 return;
1277
1278 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1279
1280 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1281 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1282 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1283 COPY_DATA_COUNT_SEL);
1284 radeon_emit(cmd_buffer->cs, va);
1285 radeon_emit(cmd_buffer->cs, va >> 32);
1286 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1287 radeon_emit(cmd_buffer->cs, 0);
1288
1289 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1290 radeon_emit(cmd_buffer->cs, 0);
1291 }
1292
1293 /*
1294 *with DCC some colors don't require CMASK elimiation before being
1295 * used as a texture. This sets a predicate value to determine if the
1296 * cmask eliminate is required.
1297 */
1298 void
1299 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1300 struct radv_image *image,
1301 bool value)
1302 {
1303 uint64_t pred_val = value;
1304 uint64_t va = radv_buffer_get_va(image->bo);
1305 va += image->offset + image->dcc_pred_offset;
1306
1307 if (!image->surface.dcc_size)
1308 return;
1309
1310 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1311
1312 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1313 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1314 S_370_WR_CONFIRM(1) |
1315 S_370_ENGINE_SEL(V_370_PFP));
1316 radeon_emit(cmd_buffer->cs, va);
1317 radeon_emit(cmd_buffer->cs, va >> 32);
1318 radeon_emit(cmd_buffer->cs, pred_val);
1319 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1320 }
1321
1322 void
1323 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1324 struct radv_image *image,
1325 int idx,
1326 uint32_t color_values[2])
1327 {
1328 uint64_t va = radv_buffer_get_va(image->bo);
1329 va += image->offset + image->clear_value_offset;
1330
1331 if (!image->cmask.size && !image->surface.dcc_size)
1332 return;
1333
1334 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1335
1336 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1337 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1338 S_370_WR_CONFIRM(1) |
1339 S_370_ENGINE_SEL(V_370_PFP));
1340 radeon_emit(cmd_buffer->cs, va);
1341 radeon_emit(cmd_buffer->cs, va >> 32);
1342 radeon_emit(cmd_buffer->cs, color_values[0]);
1343 radeon_emit(cmd_buffer->cs, color_values[1]);
1344
1345 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1346 radeon_emit(cmd_buffer->cs, color_values[0]);
1347 radeon_emit(cmd_buffer->cs, color_values[1]);
1348 }
1349
1350 static void
1351 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_image *image,
1353 int idx)
1354 {
1355 uint64_t va = radv_buffer_get_va(image->bo);
1356 va += image->offset + image->clear_value_offset;
1357
1358 if (!image->cmask.size && !image->surface.dcc_size)
1359 return;
1360
1361 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1362 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1363
1364 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1365 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1366 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1367 COPY_DATA_COUNT_SEL);
1368 radeon_emit(cmd_buffer->cs, va);
1369 radeon_emit(cmd_buffer->cs, va >> 32);
1370 radeon_emit(cmd_buffer->cs, reg >> 2);
1371 radeon_emit(cmd_buffer->cs, 0);
1372
1373 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1374 radeon_emit(cmd_buffer->cs, 0);
1375 }
1376
1377 void
1378 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1379 {
1380 int i;
1381 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1382 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1383
1384 /* this may happen for inherited secondary recording */
1385 if (!framebuffer)
1386 return;
1387
1388 for (i = 0; i < 8; ++i) {
1389 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1390 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1391 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1392 continue;
1393 }
1394
1395 int idx = subpass->color_attachments[i].attachment;
1396 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1397
1398 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1399
1400 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1401 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1402
1403 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1404 }
1405
1406 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1407 int idx = subpass->depth_stencil_attachment.attachment;
1408 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1409 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1410 struct radv_image *image = att->attachment->image;
1411 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1412 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1413 cmd_buffer->queue_family_index,
1414 cmd_buffer->queue_family_index);
1415 /* We currently don't support writing decompressed HTILE */
1416 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1417 radv_layout_is_htile_compressed(image, layout, queue_mask));
1418
1419 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1420
1421 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1422 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1423 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1424 }
1425 radv_load_depth_clear_regs(cmd_buffer, image);
1426 } else {
1427 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1429 else
1430 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1431
1432 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1433 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1434 }
1435 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1436 S_028208_BR_X(framebuffer->width) |
1437 S_028208_BR_Y(framebuffer->height));
1438
1439 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1440 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1441 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1442 }
1443 }
1444
1445 static void
1446 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1447 {
1448 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1449
1450 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1451 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1452 2, cmd_buffer->state.index_type);
1453 } else {
1454 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1455 radeon_emit(cs, cmd_buffer->state.index_type);
1456 }
1457
1458 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1459 radeon_emit(cs, cmd_buffer->state.index_va);
1460 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1461
1462 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1463 radeon_emit(cs, cmd_buffer->state.max_index_count);
1464 }
1465
1466 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1467 {
1468 uint32_t db_count_control;
1469
1470 if(!cmd_buffer->state.active_occlusion_queries) {
1471 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1472 db_count_control = 0;
1473 } else {
1474 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1475 }
1476 } else {
1477 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1478 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1479 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1480 S_028004_ZPASS_ENABLE(1) |
1481 S_028004_SLICE_EVEN_ENABLE(1) |
1482 S_028004_SLICE_ODD_ENABLE(1);
1483 } else {
1484 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1485 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1486 }
1487 }
1488
1489 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1490 }
1491
1492 static void
1493 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1494 {
1495 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1496 return;
1497
1498 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1499 radv_emit_viewport(cmd_buffer);
1500
1501 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1502 radv_emit_scissor(cmd_buffer);
1503
1504 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1505 radv_emit_line_width(cmd_buffer);
1506
1507 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1508 radv_emit_blend_constants(cmd_buffer);
1509
1510 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1511 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1512 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1513 radv_emit_stencil(cmd_buffer);
1514
1515 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1516 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1517 radv_emit_depth_bounds(cmd_buffer);
1518
1519 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1520 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1521 radv_emit_depth_biais(cmd_buffer);
1522 }
1523
1524 static void
1525 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1526 struct radv_pipeline *pipeline,
1527 int idx,
1528 uint64_t va,
1529 gl_shader_stage stage)
1530 {
1531 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1532 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1533
1534 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1535 return;
1536
1537 assert(!desc_set_loc->indirect);
1538 assert(desc_set_loc->num_sgprs == 2);
1539 radeon_set_sh_reg_seq(cmd_buffer->cs,
1540 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1541 radeon_emit(cmd_buffer->cs, va);
1542 radeon_emit(cmd_buffer->cs, va >> 32);
1543 }
1544
1545 static void
1546 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1547 VkShaderStageFlags stages,
1548 struct radv_descriptor_set *set,
1549 unsigned idx)
1550 {
1551 if (cmd_buffer->state.pipeline) {
1552 radv_foreach_stage(stage, stages) {
1553 if (cmd_buffer->state.pipeline->shaders[stage])
1554 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1555 idx, set->va,
1556 stage);
1557 }
1558 }
1559
1560 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1561 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1562 idx, set->va,
1563 MESA_SHADER_COMPUTE);
1564 }
1565
1566 static void
1567 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1568 {
1569 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1570 unsigned bo_offset;
1571
1572 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1573 set->mapped_ptr,
1574 &bo_offset))
1575 return;
1576
1577 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1578 set->va += bo_offset;
1579 }
1580
1581 static void
1582 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1583 {
1584 uint32_t size = MAX_SETS * 2 * 4;
1585 uint32_t offset;
1586 void *ptr;
1587
1588 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1589 256, &offset, &ptr))
1590 return;
1591
1592 for (unsigned i = 0; i < MAX_SETS; i++) {
1593 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1594 uint64_t set_va = 0;
1595 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1596 if (set)
1597 set_va = set->va;
1598 uptr[0] = set_va & 0xffffffff;
1599 uptr[1] = set_va >> 32;
1600 }
1601
1602 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1603 va += offset;
1604
1605 if (cmd_buffer->state.pipeline) {
1606 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1607 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1608 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1609
1610 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1611 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1612 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1613
1614 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1615 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1616 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1617
1618 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1619 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1620 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1621
1622 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1623 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1624 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1625 }
1626
1627 if (cmd_buffer->state.compute_pipeline)
1628 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1629 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1630 }
1631
1632 static void
1633 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1634 VkShaderStageFlags stages)
1635 {
1636 unsigned i;
1637
1638 if (!cmd_buffer->state.descriptors_dirty)
1639 return;
1640
1641 if (cmd_buffer->state.push_descriptors_dirty)
1642 radv_flush_push_descriptors(cmd_buffer);
1643
1644 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1645 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1646 radv_flush_indirect_descriptor_sets(cmd_buffer);
1647 }
1648
1649 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1650 cmd_buffer->cs,
1651 MAX_SETS * MESA_SHADER_STAGES * 4);
1652
1653 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1654 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1655 if (!set)
1656 continue;
1657
1658 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1659 }
1660 cmd_buffer->state.descriptors_dirty = 0;
1661 cmd_buffer->state.push_descriptors_dirty = false;
1662
1663 radv_save_descriptors(cmd_buffer);
1664
1665 assert(cmd_buffer->cs->cdw <= cdw_max);
1666 }
1667
1668 static void
1669 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1670 struct radv_pipeline *pipeline,
1671 VkShaderStageFlags stages)
1672 {
1673 struct radv_pipeline_layout *layout = pipeline->layout;
1674 unsigned offset;
1675 void *ptr;
1676 uint64_t va;
1677
1678 stages &= cmd_buffer->push_constant_stages;
1679 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1680 return;
1681
1682 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1683 16 * layout->dynamic_offset_count,
1684 256, &offset, &ptr))
1685 return;
1686
1687 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1688 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1689 16 * layout->dynamic_offset_count);
1690
1691 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1692 va += offset;
1693
1694 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1695 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1696
1697 radv_foreach_stage(stage, stages) {
1698 if (pipeline->shaders[stage]) {
1699 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1700 AC_UD_PUSH_CONSTANTS, va);
1701 }
1702 }
1703
1704 cmd_buffer->push_constant_stages &= ~stages;
1705 assert(cmd_buffer->cs->cdw <= cdw_max);
1706 }
1707
1708 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1709 bool indexed_draw)
1710 {
1711 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1712
1713 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1714 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1715 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1716 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1717 primitive_reset_en);
1718 } else {
1719 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1720 primitive_reset_en);
1721 }
1722 }
1723
1724 if (primitive_reset_en) {
1725 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1726
1727 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1728 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1729 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1730 primitive_reset_index);
1731 }
1732 }
1733 }
1734
1735 static bool
1736 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1737 {
1738 struct radv_device *device = cmd_buffer->device;
1739
1740 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1741 cmd_buffer->state.pipeline->vertex_elements.count &&
1742 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1743 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1744 unsigned vb_offset;
1745 void *vb_ptr;
1746 uint32_t i = 0;
1747 uint32_t count = velems->count;
1748 uint64_t va;
1749
1750 /* allocate some descriptor state for vertex buffers */
1751 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1752 &vb_offset, &vb_ptr))
1753 return false;
1754
1755 for (i = 0; i < count; i++) {
1756 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1757 uint32_t offset;
1758 int vb = velems->binding[i];
1759 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1760 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1761
1762 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1763 va = radv_buffer_get_va(buffer->bo);
1764
1765 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1766 va += offset + buffer->offset;
1767 desc[0] = va;
1768 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1769 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1770 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1771 else
1772 desc[2] = buffer->size - offset;
1773 desc[3] = velems->rsrc_word3[i];
1774 }
1775
1776 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1777 va += vb_offset;
1778
1779 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1780 AC_UD_VS_VERTEX_BUFFERS, va);
1781 }
1782 cmd_buffer->state.vb_dirty = false;
1783
1784 return true;
1785 }
1786
1787 static void
1788 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1789 bool indexed_draw, bool instanced_draw,
1790 bool indirect_draw,
1791 uint32_t draw_vertex_count)
1792 {
1793 uint32_t ia_multi_vgt_param;
1794
1795 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1796 cmd_buffer->cs, 4096);
1797
1798 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1799 return;
1800
1801 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1802 radv_emit_graphics_pipeline(cmd_buffer);
1803
1804 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1805 radv_emit_framebuffer_state(cmd_buffer);
1806
1807 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
1808 radv_emit_index_buffer(cmd_buffer);
1809
1810 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1811 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1812 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1813 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1814 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1815 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1816 else
1817 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1818 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1819 }
1820
1821 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1822
1823 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1824
1825 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1826 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1827 VK_SHADER_STAGE_ALL_GRAPHICS);
1828
1829 assert(cmd_buffer->cs->cdw <= cdw_max);
1830
1831 si_emit_cache_flush(cmd_buffer);
1832
1833 cmd_buffer->state.dirty = 0;
1834 }
1835
1836 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1837 VkPipelineStageFlags src_stage_mask)
1838 {
1839 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1840 VK_PIPELINE_STAGE_TRANSFER_BIT |
1841 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1842 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1843 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1844 }
1845
1846 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1847 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1848 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1849 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1850 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1851 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1852 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1853 VK_PIPELINE_STAGE_TRANSFER_BIT |
1854 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1855 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1856 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1857 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1858 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1859 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1860 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1861 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1862 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1863 }
1864 }
1865
1866 static enum radv_cmd_flush_bits
1867 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1868 VkAccessFlags src_flags)
1869 {
1870 enum radv_cmd_flush_bits flush_bits = 0;
1871 uint32_t b;
1872 for_each_bit(b, src_flags) {
1873 switch ((VkAccessFlagBits)(1 << b)) {
1874 case VK_ACCESS_SHADER_WRITE_BIT:
1875 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1876 break;
1877 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1878 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1879 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1880 break;
1881 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1882 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1883 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1884 break;
1885 case VK_ACCESS_TRANSFER_WRITE_BIT:
1886 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1887 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1888 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1889 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1890 RADV_CMD_FLAG_INV_GLOBAL_L2;
1891 break;
1892 default:
1893 break;
1894 }
1895 }
1896 return flush_bits;
1897 }
1898
1899 static enum radv_cmd_flush_bits
1900 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1901 VkAccessFlags dst_flags,
1902 struct radv_image *image)
1903 {
1904 enum radv_cmd_flush_bits flush_bits = 0;
1905 uint32_t b;
1906 for_each_bit(b, dst_flags) {
1907 switch ((VkAccessFlagBits)(1 << b)) {
1908 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1909 case VK_ACCESS_INDEX_READ_BIT:
1910 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1911 break;
1912 case VK_ACCESS_UNIFORM_READ_BIT:
1913 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1914 break;
1915 case VK_ACCESS_SHADER_READ_BIT:
1916 case VK_ACCESS_TRANSFER_READ_BIT:
1917 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1918 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1919 RADV_CMD_FLAG_INV_GLOBAL_L2;
1920 break;
1921 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1922 /* TODO: change to image && when the image gets passed
1923 * through from the subpass. */
1924 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1925 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1926 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1927 break;
1928 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1929 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1930 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1931 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1932 break;
1933 default:
1934 break;
1935 }
1936 }
1937 return flush_bits;
1938 }
1939
1940 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1941 {
1942 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1943 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1944 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1945 NULL);
1946 }
1947
1948 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1949 VkAttachmentReference att)
1950 {
1951 unsigned idx = att.attachment;
1952 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1953 VkImageSubresourceRange range;
1954 range.aspectMask = 0;
1955 range.baseMipLevel = view->base_mip;
1956 range.levelCount = 1;
1957 range.baseArrayLayer = view->base_layer;
1958 range.layerCount = cmd_buffer->state.framebuffer->layers;
1959
1960 radv_handle_image_transition(cmd_buffer,
1961 view->image,
1962 cmd_buffer->state.attachments[idx].current_layout,
1963 att.layout, 0, 0, &range,
1964 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1965
1966 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1967
1968
1969 }
1970
1971 void
1972 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1973 const struct radv_subpass *subpass, bool transitions)
1974 {
1975 if (transitions) {
1976 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1977
1978 for (unsigned i = 0; i < subpass->color_count; ++i) {
1979 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1980 radv_handle_subpass_image_transition(cmd_buffer,
1981 subpass->color_attachments[i]);
1982 }
1983
1984 for (unsigned i = 0; i < subpass->input_count; ++i) {
1985 radv_handle_subpass_image_transition(cmd_buffer,
1986 subpass->input_attachments[i]);
1987 }
1988
1989 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1990 radv_handle_subpass_image_transition(cmd_buffer,
1991 subpass->depth_stencil_attachment);
1992 }
1993 }
1994
1995 cmd_buffer->state.subpass = subpass;
1996
1997 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1998 }
1999
2000 static VkResult
2001 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2002 struct radv_render_pass *pass,
2003 const VkRenderPassBeginInfo *info)
2004 {
2005 struct radv_cmd_state *state = &cmd_buffer->state;
2006
2007 if (pass->attachment_count == 0) {
2008 state->attachments = NULL;
2009 return VK_SUCCESS;
2010 }
2011
2012 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2013 pass->attachment_count *
2014 sizeof(state->attachments[0]),
2015 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2016 if (state->attachments == NULL) {
2017 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2018 return cmd_buffer->record_result;
2019 }
2020
2021 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2022 struct radv_render_pass_attachment *att = &pass->attachments[i];
2023 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2024 VkImageAspectFlags clear_aspects = 0;
2025
2026 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2027 /* color attachment */
2028 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2029 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2030 }
2031 } else {
2032 /* depthstencil attachment */
2033 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2034 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2035 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2036 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2037 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2038 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2039 }
2040 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2041 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2042 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2043 }
2044 }
2045
2046 state->attachments[i].pending_clear_aspects = clear_aspects;
2047 state->attachments[i].cleared_views = 0;
2048 if (clear_aspects && info) {
2049 assert(info->clearValueCount > i);
2050 state->attachments[i].clear_value = info->pClearValues[i];
2051 }
2052
2053 state->attachments[i].current_layout = att->initial_layout;
2054 }
2055
2056 return VK_SUCCESS;
2057 }
2058
2059 VkResult radv_AllocateCommandBuffers(
2060 VkDevice _device,
2061 const VkCommandBufferAllocateInfo *pAllocateInfo,
2062 VkCommandBuffer *pCommandBuffers)
2063 {
2064 RADV_FROM_HANDLE(radv_device, device, _device);
2065 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2066
2067 VkResult result = VK_SUCCESS;
2068 uint32_t i;
2069
2070 memset(pCommandBuffers, 0,
2071 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2072
2073 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2074
2075 if (!list_empty(&pool->free_cmd_buffers)) {
2076 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2077
2078 list_del(&cmd_buffer->pool_link);
2079 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2080
2081 result = radv_reset_cmd_buffer(cmd_buffer);
2082 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2083 cmd_buffer->level = pAllocateInfo->level;
2084
2085 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2086 } else {
2087 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2088 &pCommandBuffers[i]);
2089 }
2090 if (result != VK_SUCCESS)
2091 break;
2092 }
2093
2094 if (result != VK_SUCCESS)
2095 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2096 i, pCommandBuffers);
2097
2098 return result;
2099 }
2100
2101 void radv_FreeCommandBuffers(
2102 VkDevice device,
2103 VkCommandPool commandPool,
2104 uint32_t commandBufferCount,
2105 const VkCommandBuffer *pCommandBuffers)
2106 {
2107 for (uint32_t i = 0; i < commandBufferCount; i++) {
2108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2109
2110 if (cmd_buffer) {
2111 if (cmd_buffer->pool) {
2112 list_del(&cmd_buffer->pool_link);
2113 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2114 } else
2115 radv_cmd_buffer_destroy(cmd_buffer);
2116
2117 }
2118 }
2119 }
2120
2121 VkResult radv_ResetCommandBuffer(
2122 VkCommandBuffer commandBuffer,
2123 VkCommandBufferResetFlags flags)
2124 {
2125 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2126 return radv_reset_cmd_buffer(cmd_buffer);
2127 }
2128
2129 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2130 {
2131 struct radv_device *device = cmd_buffer->device;
2132 if (device->gfx_init) {
2133 uint64_t va = radv_buffer_get_va(device->gfx_init);
2134 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2135 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2136 radeon_emit(cmd_buffer->cs, va);
2137 radeon_emit(cmd_buffer->cs, va >> 32);
2138 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2139 } else
2140 si_init_config(cmd_buffer);
2141 }
2142
2143 VkResult radv_BeginCommandBuffer(
2144 VkCommandBuffer commandBuffer,
2145 const VkCommandBufferBeginInfo *pBeginInfo)
2146 {
2147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2148 VkResult result;
2149
2150 result = radv_reset_cmd_buffer(cmd_buffer);
2151 if (result != VK_SUCCESS)
2152 return result;
2153
2154 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2155 cmd_buffer->state.last_primitive_reset_en = -1;
2156 cmd_buffer->usage_flags = pBeginInfo->flags;
2157
2158 /* setup initial configuration into command buffer */
2159 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2160 switch (cmd_buffer->queue_family_index) {
2161 case RADV_QUEUE_GENERAL:
2162 emit_gfx_buffer_state(cmd_buffer);
2163 break;
2164 case RADV_QUEUE_COMPUTE:
2165 si_init_compute(cmd_buffer);
2166 break;
2167 case RADV_QUEUE_TRANSFER:
2168 default:
2169 break;
2170 }
2171 }
2172
2173 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2174 assert(pBeginInfo->pInheritanceInfo);
2175 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2176 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2177
2178 struct radv_subpass *subpass =
2179 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2180
2181 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2182 if (result != VK_SUCCESS)
2183 return result;
2184
2185 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2186 }
2187
2188 radv_cmd_buffer_trace_emit(cmd_buffer);
2189 return result;
2190 }
2191
2192 void radv_CmdBindVertexBuffers(
2193 VkCommandBuffer commandBuffer,
2194 uint32_t firstBinding,
2195 uint32_t bindingCount,
2196 const VkBuffer* pBuffers,
2197 const VkDeviceSize* pOffsets)
2198 {
2199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2200 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2201
2202 /* We have to defer setting up vertex buffer since we need the buffer
2203 * stride from the pipeline. */
2204
2205 assert(firstBinding + bindingCount <= MAX_VBS);
2206 for (uint32_t i = 0; i < bindingCount; i++) {
2207 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2208 vb[firstBinding + i].offset = pOffsets[i];
2209 }
2210
2211 cmd_buffer->state.vb_dirty = true;
2212 }
2213
2214 void radv_CmdBindIndexBuffer(
2215 VkCommandBuffer commandBuffer,
2216 VkBuffer buffer,
2217 VkDeviceSize offset,
2218 VkIndexType indexType)
2219 {
2220 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2221 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2222
2223 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2224 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2225 cmd_buffer->state.index_va += index_buffer->offset + offset;
2226
2227 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2228 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2229 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2231 }
2232
2233
2234 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2235 struct radv_descriptor_set *set,
2236 unsigned idx)
2237 {
2238 struct radeon_winsys *ws = cmd_buffer->device->ws;
2239
2240 cmd_buffer->state.descriptors[idx] = set;
2241 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2242 if (!set)
2243 return;
2244
2245 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2246
2247 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2248 if (set->descriptors[j])
2249 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2250
2251 if(set->bo)
2252 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2253 }
2254
2255 void radv_CmdBindDescriptorSets(
2256 VkCommandBuffer commandBuffer,
2257 VkPipelineBindPoint pipelineBindPoint,
2258 VkPipelineLayout _layout,
2259 uint32_t firstSet,
2260 uint32_t descriptorSetCount,
2261 const VkDescriptorSet* pDescriptorSets,
2262 uint32_t dynamicOffsetCount,
2263 const uint32_t* pDynamicOffsets)
2264 {
2265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2266 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2267 unsigned dyn_idx = 0;
2268
2269 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2270 unsigned idx = i + firstSet;
2271 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2272 radv_bind_descriptor_set(cmd_buffer, set, idx);
2273
2274 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2275 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2276 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2277 assert(dyn_idx < dynamicOffsetCount);
2278
2279 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2280 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2281 dst[0] = va;
2282 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2283 dst[2] = range->size;
2284 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2288 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2290 cmd_buffer->push_constant_stages |=
2291 set->layout->dynamic_shader_stages;
2292 }
2293 }
2294 }
2295
2296 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2297 struct radv_descriptor_set *set,
2298 struct radv_descriptor_set_layout *layout)
2299 {
2300 set->size = layout->size;
2301 set->layout = layout;
2302
2303 if (cmd_buffer->push_descriptors.capacity < set->size) {
2304 size_t new_size = MAX2(set->size, 1024);
2305 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2306 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2307
2308 free(set->mapped_ptr);
2309 set->mapped_ptr = malloc(new_size);
2310
2311 if (!set->mapped_ptr) {
2312 cmd_buffer->push_descriptors.capacity = 0;
2313 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2314 return false;
2315 }
2316
2317 cmd_buffer->push_descriptors.capacity = new_size;
2318 }
2319
2320 return true;
2321 }
2322
2323 void radv_meta_push_descriptor_set(
2324 struct radv_cmd_buffer* cmd_buffer,
2325 VkPipelineBindPoint pipelineBindPoint,
2326 VkPipelineLayout _layout,
2327 uint32_t set,
2328 uint32_t descriptorWriteCount,
2329 const VkWriteDescriptorSet* pDescriptorWrites)
2330 {
2331 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2332 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2333 unsigned bo_offset;
2334
2335 assert(set == 0);
2336 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2337
2338 push_set->size = layout->set[set].layout->size;
2339 push_set->layout = layout->set[set].layout;
2340
2341 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2342 &bo_offset,
2343 (void**) &push_set->mapped_ptr))
2344 return;
2345
2346 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2347 push_set->va += bo_offset;
2348
2349 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2350 radv_descriptor_set_to_handle(push_set),
2351 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2352
2353 cmd_buffer->state.descriptors[set] = push_set;
2354 cmd_buffer->state.descriptors_dirty |= (1u << set);
2355 }
2356
2357 void radv_CmdPushDescriptorSetKHR(
2358 VkCommandBuffer commandBuffer,
2359 VkPipelineBindPoint pipelineBindPoint,
2360 VkPipelineLayout _layout,
2361 uint32_t set,
2362 uint32_t descriptorWriteCount,
2363 const VkWriteDescriptorSet* pDescriptorWrites)
2364 {
2365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2366 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2367 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2368
2369 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2370
2371 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2372 return;
2373
2374 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2375 radv_descriptor_set_to_handle(push_set),
2376 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2377
2378 cmd_buffer->state.descriptors[set] = push_set;
2379 cmd_buffer->state.descriptors_dirty |= (1u << set);
2380 cmd_buffer->state.push_descriptors_dirty = true;
2381 }
2382
2383 void radv_CmdPushDescriptorSetWithTemplateKHR(
2384 VkCommandBuffer commandBuffer,
2385 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2386 VkPipelineLayout _layout,
2387 uint32_t set,
2388 const void* pData)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2392 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2393
2394 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2395
2396 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2397 return;
2398
2399 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2400 descriptorUpdateTemplate, pData);
2401
2402 cmd_buffer->state.descriptors[set] = push_set;
2403 cmd_buffer->state.descriptors_dirty |= (1u << set);
2404 cmd_buffer->state.push_descriptors_dirty = true;
2405 }
2406
2407 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2408 VkPipelineLayout layout,
2409 VkShaderStageFlags stageFlags,
2410 uint32_t offset,
2411 uint32_t size,
2412 const void* pValues)
2413 {
2414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2415 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2416 cmd_buffer->push_constant_stages |= stageFlags;
2417 }
2418
2419 VkResult radv_EndCommandBuffer(
2420 VkCommandBuffer commandBuffer)
2421 {
2422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2423
2424 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2425 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2426 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2427 si_emit_cache_flush(cmd_buffer);
2428 }
2429
2430 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2431 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2432
2433 return cmd_buffer->record_result;
2434 }
2435
2436 static void
2437 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2438 {
2439 struct radeon_winsys *ws = cmd_buffer->device->ws;
2440 struct radv_shader_variant *compute_shader;
2441 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2442 uint64_t va;
2443
2444 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2445 return;
2446
2447 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2448
2449 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2450 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2451
2452 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2453 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2454
2455 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2456 cmd_buffer->cs, 16);
2457
2458 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2459 radeon_emit(cmd_buffer->cs, va >> 8);
2460 radeon_emit(cmd_buffer->cs, va >> 40);
2461
2462 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2463 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2464 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2465
2466
2467 cmd_buffer->compute_scratch_size_needed =
2468 MAX2(cmd_buffer->compute_scratch_size_needed,
2469 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2470
2471 /* change these once we have scratch support */
2472 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2473 S_00B860_WAVES(pipeline->max_waves) |
2474 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2475
2476 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2477 radeon_emit(cmd_buffer->cs,
2478 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2479 radeon_emit(cmd_buffer->cs,
2480 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2481 radeon_emit(cmd_buffer->cs,
2482 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2483
2484 assert(cmd_buffer->cs->cdw <= cdw_max);
2485 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2486 }
2487
2488 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2489 {
2490 for (unsigned i = 0; i < MAX_SETS; i++) {
2491 if (cmd_buffer->state.descriptors[i])
2492 cmd_buffer->state.descriptors_dirty |= (1u << i);
2493 }
2494 }
2495
2496 void radv_CmdBindPipeline(
2497 VkCommandBuffer commandBuffer,
2498 VkPipelineBindPoint pipelineBindPoint,
2499 VkPipeline _pipeline)
2500 {
2501 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2502 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2503
2504 switch (pipelineBindPoint) {
2505 case VK_PIPELINE_BIND_POINT_COMPUTE:
2506 if (cmd_buffer->state.compute_pipeline == pipeline)
2507 return;
2508 radv_mark_descriptor_sets_dirty(cmd_buffer);
2509
2510 cmd_buffer->state.compute_pipeline = pipeline;
2511 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2512 break;
2513 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2514 if (cmd_buffer->state.pipeline == pipeline)
2515 return;
2516 radv_mark_descriptor_sets_dirty(cmd_buffer);
2517
2518 cmd_buffer->state.pipeline = pipeline;
2519 if (!pipeline)
2520 break;
2521
2522 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2523 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2524
2525 /* Apply the dynamic state from the pipeline */
2526 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2527 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2528 &pipeline->dynamic_state,
2529 pipeline->dynamic_state_mask);
2530
2531 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2532 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2533 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2534 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2535
2536 if (radv_pipeline_has_tess(pipeline))
2537 cmd_buffer->tess_rings_needed = true;
2538
2539 if (radv_pipeline_has_gs(pipeline)) {
2540 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2541 AC_UD_SCRATCH_RING_OFFSETS);
2542 if (cmd_buffer->ring_offsets_idx == -1)
2543 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2544 else if (loc->sgpr_idx != -1)
2545 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2546 }
2547 break;
2548 default:
2549 assert(!"invalid bind point");
2550 break;
2551 }
2552 }
2553
2554 void radv_CmdSetViewport(
2555 VkCommandBuffer commandBuffer,
2556 uint32_t firstViewport,
2557 uint32_t viewportCount,
2558 const VkViewport* pViewports)
2559 {
2560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2561 const uint32_t total_count = firstViewport + viewportCount;
2562
2563 assert(firstViewport < MAX_VIEWPORTS);
2564 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2565
2566 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2567 pViewports, viewportCount * sizeof(*pViewports));
2568
2569 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2570 }
2571
2572 void radv_CmdSetScissor(
2573 VkCommandBuffer commandBuffer,
2574 uint32_t firstScissor,
2575 uint32_t scissorCount,
2576 const VkRect2D* pScissors)
2577 {
2578 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2579 const uint32_t total_count = firstScissor + scissorCount;
2580
2581 assert(firstScissor < MAX_SCISSORS);
2582 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2583
2584 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2585 pScissors, scissorCount * sizeof(*pScissors));
2586 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2587 }
2588
2589 void radv_CmdSetLineWidth(
2590 VkCommandBuffer commandBuffer,
2591 float lineWidth)
2592 {
2593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2594 cmd_buffer->state.dynamic.line_width = lineWidth;
2595 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2596 }
2597
2598 void radv_CmdSetDepthBias(
2599 VkCommandBuffer commandBuffer,
2600 float depthBiasConstantFactor,
2601 float depthBiasClamp,
2602 float depthBiasSlopeFactor)
2603 {
2604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2605
2606 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2607 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2608 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2609
2610 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2611 }
2612
2613 void radv_CmdSetBlendConstants(
2614 VkCommandBuffer commandBuffer,
2615 const float blendConstants[4])
2616 {
2617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2618
2619 memcpy(cmd_buffer->state.dynamic.blend_constants,
2620 blendConstants, sizeof(float) * 4);
2621
2622 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2623 }
2624
2625 void radv_CmdSetDepthBounds(
2626 VkCommandBuffer commandBuffer,
2627 float minDepthBounds,
2628 float maxDepthBounds)
2629 {
2630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2631
2632 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2633 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2634
2635 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2636 }
2637
2638 void radv_CmdSetStencilCompareMask(
2639 VkCommandBuffer commandBuffer,
2640 VkStencilFaceFlags faceMask,
2641 uint32_t compareMask)
2642 {
2643 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2644
2645 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2646 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2647 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2648 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2649
2650 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2651 }
2652
2653 void radv_CmdSetStencilWriteMask(
2654 VkCommandBuffer commandBuffer,
2655 VkStencilFaceFlags faceMask,
2656 uint32_t writeMask)
2657 {
2658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2659
2660 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2661 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2662 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2663 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2664
2665 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2666 }
2667
2668 void radv_CmdSetStencilReference(
2669 VkCommandBuffer commandBuffer,
2670 VkStencilFaceFlags faceMask,
2671 uint32_t reference)
2672 {
2673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2674
2675 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2676 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2677 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2678 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2679
2680 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2681 }
2682
2683 void radv_CmdExecuteCommands(
2684 VkCommandBuffer commandBuffer,
2685 uint32_t commandBufferCount,
2686 const VkCommandBuffer* pCmdBuffers)
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2689
2690 assert(commandBufferCount > 0);
2691
2692 /* Emit pending flushes on primary prior to executing secondary */
2693 si_emit_cache_flush(primary);
2694
2695 for (uint32_t i = 0; i < commandBufferCount; i++) {
2696 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2697
2698 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2699 secondary->scratch_size_needed);
2700 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2701 secondary->compute_scratch_size_needed);
2702
2703 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2704 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2705 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2706 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2707 if (secondary->tess_rings_needed)
2708 primary->tess_rings_needed = true;
2709 if (secondary->sample_positions_needed)
2710 primary->sample_positions_needed = true;
2711
2712 if (secondary->ring_offsets_idx != -1) {
2713 if (primary->ring_offsets_idx == -1)
2714 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2715 else
2716 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2717 }
2718 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2719
2720
2721 /* When the secondary command buffer is compute only we don't
2722 * need to re-emit the current graphics pipeline.
2723 */
2724 if (secondary->state.emitted_pipeline) {
2725 primary->state.emitted_pipeline =
2726 secondary->state.emitted_pipeline;
2727 }
2728
2729 /* When the secondary command buffer is graphics only we don't
2730 * need to re-emit the current compute pipeline.
2731 */
2732 if (secondary->state.emitted_compute_pipeline) {
2733 primary->state.emitted_compute_pipeline =
2734 secondary->state.emitted_compute_pipeline;
2735 }
2736
2737 /* Only re-emit the draw packets when needed. */
2738 if (secondary->state.last_primitive_reset_en != -1) {
2739 primary->state.last_primitive_reset_en =
2740 secondary->state.last_primitive_reset_en;
2741 }
2742
2743 if (secondary->state.last_primitive_reset_index) {
2744 primary->state.last_primitive_reset_index =
2745 secondary->state.last_primitive_reset_index;
2746 }
2747
2748 if (secondary->state.last_ia_multi_vgt_param) {
2749 primary->state.last_ia_multi_vgt_param =
2750 secondary->state.last_ia_multi_vgt_param;
2751 }
2752 }
2753
2754 /* After executing commands from secondary buffers we have to dirty
2755 * some states.
2756 */
2757 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2758 RADV_CMD_DIRTY_INDEX_BUFFER |
2759 RADV_CMD_DIRTY_DYNAMIC_ALL;
2760 radv_mark_descriptor_sets_dirty(primary);
2761 }
2762
2763 VkResult radv_CreateCommandPool(
2764 VkDevice _device,
2765 const VkCommandPoolCreateInfo* pCreateInfo,
2766 const VkAllocationCallbacks* pAllocator,
2767 VkCommandPool* pCmdPool)
2768 {
2769 RADV_FROM_HANDLE(radv_device, device, _device);
2770 struct radv_cmd_pool *pool;
2771
2772 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2773 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2774 if (pool == NULL)
2775 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2776
2777 if (pAllocator)
2778 pool->alloc = *pAllocator;
2779 else
2780 pool->alloc = device->alloc;
2781
2782 list_inithead(&pool->cmd_buffers);
2783 list_inithead(&pool->free_cmd_buffers);
2784
2785 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2786
2787 *pCmdPool = radv_cmd_pool_to_handle(pool);
2788
2789 return VK_SUCCESS;
2790
2791 }
2792
2793 void radv_DestroyCommandPool(
2794 VkDevice _device,
2795 VkCommandPool commandPool,
2796 const VkAllocationCallbacks* pAllocator)
2797 {
2798 RADV_FROM_HANDLE(radv_device, device, _device);
2799 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2800
2801 if (!pool)
2802 return;
2803
2804 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2805 &pool->cmd_buffers, pool_link) {
2806 radv_cmd_buffer_destroy(cmd_buffer);
2807 }
2808
2809 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2810 &pool->free_cmd_buffers, pool_link) {
2811 radv_cmd_buffer_destroy(cmd_buffer);
2812 }
2813
2814 vk_free2(&device->alloc, pAllocator, pool);
2815 }
2816
2817 VkResult radv_ResetCommandPool(
2818 VkDevice device,
2819 VkCommandPool commandPool,
2820 VkCommandPoolResetFlags flags)
2821 {
2822 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2823 VkResult result;
2824
2825 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2826 &pool->cmd_buffers, pool_link) {
2827 result = radv_reset_cmd_buffer(cmd_buffer);
2828 if (result != VK_SUCCESS)
2829 return result;
2830 }
2831
2832 return VK_SUCCESS;
2833 }
2834
2835 void radv_TrimCommandPoolKHR(
2836 VkDevice device,
2837 VkCommandPool commandPool,
2838 VkCommandPoolTrimFlagsKHR flags)
2839 {
2840 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2841
2842 if (!pool)
2843 return;
2844
2845 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2846 &pool->free_cmd_buffers, pool_link) {
2847 radv_cmd_buffer_destroy(cmd_buffer);
2848 }
2849 }
2850
2851 void radv_CmdBeginRenderPass(
2852 VkCommandBuffer commandBuffer,
2853 const VkRenderPassBeginInfo* pRenderPassBegin,
2854 VkSubpassContents contents)
2855 {
2856 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2857 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2858 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2859
2860 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2861 cmd_buffer->cs, 2048);
2862 MAYBE_UNUSED VkResult result;
2863
2864 cmd_buffer->state.framebuffer = framebuffer;
2865 cmd_buffer->state.pass = pass;
2866 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2867
2868 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2869 if (result != VK_SUCCESS)
2870 return;
2871
2872 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2873 assert(cmd_buffer->cs->cdw <= cdw_max);
2874
2875 radv_cmd_buffer_clear_subpass(cmd_buffer);
2876 }
2877
2878 void radv_CmdNextSubpass(
2879 VkCommandBuffer commandBuffer,
2880 VkSubpassContents contents)
2881 {
2882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2883
2884 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2885
2886 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2887 2048);
2888
2889 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2890 radv_cmd_buffer_clear_subpass(cmd_buffer);
2891 }
2892
2893 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2894 {
2895 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2896 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2897 if (!pipeline->shaders[stage])
2898 continue;
2899 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2900 if (loc->sgpr_idx == -1)
2901 continue;
2902 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2903 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2904
2905 }
2906 if (pipeline->gs_copy_shader) {
2907 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2908 if (loc->sgpr_idx != -1) {
2909 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2910 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2911 }
2912 }
2913 }
2914
2915 static void
2916 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2917 uint32_t vertex_count)
2918 {
2919 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2920 radeon_emit(cmd_buffer->cs, vertex_count);
2921 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2922 S_0287F0_USE_OPAQUE(0));
2923 }
2924
2925 void radv_CmdDraw(
2926 VkCommandBuffer commandBuffer,
2927 uint32_t vertexCount,
2928 uint32_t instanceCount,
2929 uint32_t firstVertex,
2930 uint32_t firstInstance)
2931 {
2932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2933
2934 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2935
2936 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2937
2938 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2939 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2940 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2941 radeon_emit(cmd_buffer->cs, firstVertex);
2942 radeon_emit(cmd_buffer->cs, firstInstance);
2943 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2944 radeon_emit(cmd_buffer->cs, 0);
2945
2946 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2947 radeon_emit(cmd_buffer->cs, instanceCount);
2948
2949 if (!cmd_buffer->state.subpass->view_mask) {
2950 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2951 } else {
2952 unsigned i;
2953 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2954 radv_emit_view_index(cmd_buffer, i);
2955
2956 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2957 }
2958 }
2959
2960 assert(cmd_buffer->cs->cdw <= cdw_max);
2961
2962 radv_cmd_buffer_after_draw(cmd_buffer);
2963 }
2964
2965
2966 static void
2967 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2968 uint64_t index_va,
2969 uint32_t index_count)
2970 {
2971 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2972 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2973 radeon_emit(cmd_buffer->cs, index_va);
2974 radeon_emit(cmd_buffer->cs, index_va >> 32);
2975 radeon_emit(cmd_buffer->cs, index_count);
2976 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2977 }
2978
2979 void radv_CmdDrawIndexed(
2980 VkCommandBuffer commandBuffer,
2981 uint32_t indexCount,
2982 uint32_t instanceCount,
2983 uint32_t firstIndex,
2984 int32_t vertexOffset,
2985 uint32_t firstInstance)
2986 {
2987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2988 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2989 uint64_t index_va;
2990
2991 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2992
2993 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2994
2995 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2996 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2997 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2998 radeon_emit(cmd_buffer->cs, vertexOffset);
2999 radeon_emit(cmd_buffer->cs, firstInstance);
3000 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
3001 radeon_emit(cmd_buffer->cs, 0);
3002
3003 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
3004 radeon_emit(cmd_buffer->cs, instanceCount);
3005
3006 index_va = cmd_buffer->state.index_va;
3007 index_va += firstIndex * index_size;
3008 if (!cmd_buffer->state.subpass->view_mask) {
3009 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
3010 } else {
3011 unsigned i;
3012 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3013 radv_emit_view_index(cmd_buffer, i);
3014
3015 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
3016 }
3017 }
3018
3019 assert(cmd_buffer->cs->cdw <= cdw_max);
3020 radv_cmd_buffer_after_draw(cmd_buffer);
3021 }
3022
3023 static void
3024 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3025 bool indexed,
3026 uint32_t draw_count,
3027 uint64_t count_va,
3028 uint32_t stride)
3029 {
3030 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3031 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3032 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3033 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3034 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3035 assert(base_reg);
3036
3037 if (draw_count == 1 && !count_va && !draw_id_enable) {
3038 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3039 PKT3_DRAW_INDIRECT, 3, false));
3040 radeon_emit(cs, 0);
3041 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3042 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3043 radeon_emit(cs, di_src_sel);
3044 } else {
3045 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3046 PKT3_DRAW_INDIRECT_MULTI,
3047 8, false));
3048 radeon_emit(cs, 0);
3049 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3050 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3051 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3052 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3053 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3054 radeon_emit(cs, draw_count); /* count */
3055 radeon_emit(cs, count_va); /* count_addr */
3056 radeon_emit(cs, count_va >> 32);
3057 radeon_emit(cs, stride); /* stride */
3058 radeon_emit(cs, di_src_sel);
3059 }
3060 }
3061
3062 static void
3063 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
3064 VkBuffer _buffer,
3065 VkDeviceSize offset,
3066 VkBuffer _count_buffer,
3067 VkDeviceSize count_offset,
3068 uint32_t draw_count,
3069 uint32_t stride,
3070 bool indexed)
3071 {
3072 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3073 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
3074 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3075
3076 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
3077 indirect_va += offset + buffer->offset;
3078 uint64_t count_va = 0;
3079
3080 if (count_buffer) {
3081 count_va = radv_buffer_get_va(count_buffer->bo);
3082 count_va += count_offset + count_buffer->offset;
3083
3084 cmd_buffer->device->ws->cs_add_buffer(cs, count_buffer->bo, 8);
3085 }
3086
3087 if (!draw_count)
3088 return;
3089
3090 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3091
3092 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3093 radeon_emit(cs, 1);
3094 radeon_emit(cs, indirect_va);
3095 radeon_emit(cs, indirect_va >> 32);
3096
3097 if (!cmd_buffer->state.subpass->view_mask) {
3098 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3099 } else {
3100 unsigned i;
3101 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3102 radv_emit_view_index(cmd_buffer, i);
3103
3104 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3105 }
3106 }
3107 radv_cmd_buffer_after_draw(cmd_buffer);
3108 }
3109
3110 static void
3111 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3112 VkBuffer buffer,
3113 VkDeviceSize offset,
3114 VkBuffer countBuffer,
3115 VkDeviceSize countBufferOffset,
3116 uint32_t maxDrawCount,
3117 uint32_t stride)
3118 {
3119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3120 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3121
3122 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3123 cmd_buffer->cs, 24 * MAX_VIEWS);
3124
3125 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3126 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3127
3128 assert(cmd_buffer->cs->cdw <= cdw_max);
3129 }
3130
3131 static void
3132 radv_cmd_draw_indexed_indirect_count(
3133 VkCommandBuffer commandBuffer,
3134 VkBuffer buffer,
3135 VkDeviceSize offset,
3136 VkBuffer countBuffer,
3137 VkDeviceSize countBufferOffset,
3138 uint32_t maxDrawCount,
3139 uint32_t stride)
3140 {
3141 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3142
3143 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3144
3145 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3146
3147 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3148 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3149
3150 assert(cmd_buffer->cs->cdw <= cdw_max);
3151 }
3152
3153 void radv_CmdDrawIndirect(
3154 VkCommandBuffer commandBuffer,
3155 VkBuffer buffer,
3156 VkDeviceSize offset,
3157 uint32_t drawCount,
3158 uint32_t stride)
3159 {
3160 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3161 VK_NULL_HANDLE, 0, drawCount, stride);
3162 }
3163
3164 void radv_CmdDrawIndexedIndirect(
3165 VkCommandBuffer commandBuffer,
3166 VkBuffer buffer,
3167 VkDeviceSize offset,
3168 uint32_t drawCount,
3169 uint32_t stride)
3170 {
3171 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3172 VK_NULL_HANDLE, 0, drawCount, stride);
3173 }
3174
3175 void radv_CmdDrawIndirectCountAMD(
3176 VkCommandBuffer commandBuffer,
3177 VkBuffer buffer,
3178 VkDeviceSize offset,
3179 VkBuffer countBuffer,
3180 VkDeviceSize countBufferOffset,
3181 uint32_t maxDrawCount,
3182 uint32_t stride)
3183 {
3184 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3185 countBuffer, countBufferOffset,
3186 maxDrawCount, stride);
3187 }
3188
3189 void radv_CmdDrawIndexedIndirectCountAMD(
3190 VkCommandBuffer commandBuffer,
3191 VkBuffer buffer,
3192 VkDeviceSize offset,
3193 VkBuffer countBuffer,
3194 VkDeviceSize countBufferOffset,
3195 uint32_t maxDrawCount,
3196 uint32_t stride)
3197 {
3198 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3199 countBuffer, countBufferOffset,
3200 maxDrawCount, stride);
3201 }
3202
3203 struct radv_dispatch_info {
3204 /**
3205 * Determine the layout of the grid (in block units) to be used.
3206 */
3207 uint32_t blocks[3];
3208
3209 /**
3210 * Whether it's an unaligned compute dispatch.
3211 */
3212 bool unaligned;
3213
3214 /**
3215 * Indirect compute parameters resource.
3216 */
3217 struct radv_buffer *indirect;
3218 uint64_t indirect_offset;
3219 };
3220
3221 static void
3222 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3223 const struct radv_dispatch_info *info)
3224 {
3225 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3226 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3227 struct radeon_winsys *ws = cmd_buffer->device->ws;
3228 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3229 struct ac_userdata_info *loc;
3230 unsigned dispatch_initiator;
3231 uint8_t grid_used;
3232
3233 grid_used = compute_shader->info.info.cs.grid_components_used;
3234
3235 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3236 AC_UD_CS_GRID_SIZE);
3237
3238 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3239
3240 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3241 S_00B800_FORCE_START_AT_000(1);
3242
3243 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3244 /* If the KMD allows it (there is a KMD hw register for it),
3245 * allow launching waves out-of-order.
3246 */
3247 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3248 }
3249
3250 if (info->indirect) {
3251 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3252
3253 va += info->indirect->offset + info->indirect_offset;
3254
3255 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3256
3257 if (loc->sgpr_idx != -1) {
3258 for (unsigned i = 0; i < grid_used; ++i) {
3259 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3260 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3261 COPY_DATA_DST_SEL(COPY_DATA_REG));
3262 radeon_emit(cs, (va + 4 * i));
3263 radeon_emit(cs, (va + 4 * i) >> 32);
3264 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3265 + loc->sgpr_idx * 4) >> 2) + i);
3266 radeon_emit(cs, 0);
3267 }
3268 }
3269
3270 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3271 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3272 PKT3_SHADER_TYPE_S(1));
3273 radeon_emit(cs, va);
3274 radeon_emit(cs, va >> 32);
3275 radeon_emit(cs, dispatch_initiator);
3276 } else {
3277 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3278 PKT3_SHADER_TYPE_S(1));
3279 radeon_emit(cs, 1);
3280 radeon_emit(cs, va);
3281 radeon_emit(cs, va >> 32);
3282
3283 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3284 PKT3_SHADER_TYPE_S(1));
3285 radeon_emit(cs, 0);
3286 radeon_emit(cs, dispatch_initiator);
3287 }
3288 } else {
3289 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3290
3291 if (info->unaligned) {
3292 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3293 unsigned remainder[3];
3294
3295 /* If aligned, these should be an entire block size,
3296 * not 0.
3297 */
3298 remainder[0] = blocks[0] + cs_block_size[0] -
3299 align_u32_npot(blocks[0], cs_block_size[0]);
3300 remainder[1] = blocks[1] + cs_block_size[1] -
3301 align_u32_npot(blocks[1], cs_block_size[1]);
3302 remainder[2] = blocks[2] + cs_block_size[2] -
3303 align_u32_npot(blocks[2], cs_block_size[2]);
3304
3305 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3306 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3307 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3308
3309 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3310 radeon_emit(cs,
3311 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3312 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3313 radeon_emit(cs,
3314 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3315 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3316 radeon_emit(cs,
3317 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3318 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3319
3320 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3321 }
3322
3323 if (loc->sgpr_idx != -1) {
3324 assert(!loc->indirect);
3325 assert(loc->num_sgprs == grid_used);
3326
3327 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3328 loc->sgpr_idx * 4, grid_used);
3329 radeon_emit(cs, blocks[0]);
3330 if (grid_used > 1)
3331 radeon_emit(cs, blocks[1]);
3332 if (grid_used > 2)
3333 radeon_emit(cs, blocks[2]);
3334 }
3335
3336 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3337 PKT3_SHADER_TYPE_S(1));
3338 radeon_emit(cs, blocks[0]);
3339 radeon_emit(cs, blocks[1]);
3340 radeon_emit(cs, blocks[2]);
3341 radeon_emit(cs, dispatch_initiator);
3342 }
3343
3344 assert(cmd_buffer->cs->cdw <= cdw_max);
3345 }
3346
3347 static void
3348 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3349 const struct radv_dispatch_info *info)
3350 {
3351 radv_emit_compute_pipeline(cmd_buffer);
3352
3353 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3354 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3355 VK_SHADER_STAGE_COMPUTE_BIT);
3356
3357 si_emit_cache_flush(cmd_buffer);
3358
3359 radv_emit_dispatch_packets(cmd_buffer, info);
3360
3361 radv_cmd_buffer_after_draw(cmd_buffer);
3362 }
3363
3364 void radv_CmdDispatch(
3365 VkCommandBuffer commandBuffer,
3366 uint32_t x,
3367 uint32_t y,
3368 uint32_t z)
3369 {
3370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3371 struct radv_dispatch_info info = {};
3372
3373 info.blocks[0] = x;
3374 info.blocks[1] = y;
3375 info.blocks[2] = z;
3376
3377 radv_dispatch(cmd_buffer, &info);
3378 }
3379
3380 void radv_CmdDispatchIndirect(
3381 VkCommandBuffer commandBuffer,
3382 VkBuffer _buffer,
3383 VkDeviceSize offset)
3384 {
3385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3386 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3387 struct radv_dispatch_info info = {};
3388
3389 info.indirect = buffer;
3390 info.indirect_offset = offset;
3391
3392 radv_dispatch(cmd_buffer, &info);
3393 }
3394
3395 void radv_unaligned_dispatch(
3396 struct radv_cmd_buffer *cmd_buffer,
3397 uint32_t x,
3398 uint32_t y,
3399 uint32_t z)
3400 {
3401 struct radv_dispatch_info info = {};
3402
3403 info.blocks[0] = x;
3404 info.blocks[1] = y;
3405 info.blocks[2] = z;
3406 info.unaligned = 1;
3407
3408 radv_dispatch(cmd_buffer, &info);
3409 }
3410
3411 void radv_CmdEndRenderPass(
3412 VkCommandBuffer commandBuffer)
3413 {
3414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3415
3416 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3417
3418 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3419
3420 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3421 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3422 radv_handle_subpass_image_transition(cmd_buffer,
3423 (VkAttachmentReference){i, layout});
3424 }
3425
3426 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3427
3428 cmd_buffer->state.pass = NULL;
3429 cmd_buffer->state.subpass = NULL;
3430 cmd_buffer->state.attachments = NULL;
3431 cmd_buffer->state.framebuffer = NULL;
3432 }
3433
3434 /*
3435 * For HTILE we have the following interesting clear words:
3436 * 0x0000030f: Uncompressed.
3437 * 0xfffffff0: Clear depth to 1.0
3438 * 0x00000000: Clear depth to 0.0
3439 */
3440 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3441 struct radv_image *image,
3442 const VkImageSubresourceRange *range,
3443 uint32_t clear_word)
3444 {
3445 assert(range->baseMipLevel == 0);
3446 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3447 unsigned layer_count = radv_get_layerCount(image, range);
3448 uint64_t size = image->surface.htile_slice_size * layer_count;
3449 uint64_t offset = image->offset + image->htile_offset +
3450 image->surface.htile_slice_size * range->baseArrayLayer;
3451
3452 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3453 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3454
3455 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3456
3457 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3458 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3459 RADV_CMD_FLAG_INV_VMEM_L1 |
3460 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3461 }
3462
3463 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3464 struct radv_image *image,
3465 VkImageLayout src_layout,
3466 VkImageLayout dst_layout,
3467 unsigned src_queue_mask,
3468 unsigned dst_queue_mask,
3469 const VkImageSubresourceRange *range,
3470 VkImageAspectFlags pending_clears)
3471 {
3472 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3473 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3474 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3475 cmd_buffer->state.render_area.extent.width == image->info.width &&
3476 cmd_buffer->state.render_area.extent.height == image->info.height) {
3477 /* The clear will initialize htile. */
3478 return;
3479 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3480 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3481 /* TODO: merge with the clear if applicable */
3482 radv_initialize_htile(cmd_buffer, image, range, 0);
3483 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3484 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3485 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3486 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3487 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3488 VkImageSubresourceRange local_range = *range;
3489 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3490 local_range.baseMipLevel = 0;
3491 local_range.levelCount = 1;
3492
3493 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3494 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3495
3496 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3497
3498 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3499 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3500 }
3501 }
3502
3503 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3504 struct radv_image *image, uint32_t value)
3505 {
3506 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3507 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3508
3509 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3510 image->cmask.size, value);
3511
3512 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3513 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3514 RADV_CMD_FLAG_INV_VMEM_L1 |
3515 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3516 }
3517
3518 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3519 struct radv_image *image,
3520 VkImageLayout src_layout,
3521 VkImageLayout dst_layout,
3522 unsigned src_queue_mask,
3523 unsigned dst_queue_mask,
3524 const VkImageSubresourceRange *range)
3525 {
3526 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3527 if (image->fmask.size)
3528 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3529 else
3530 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3531 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3532 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3533 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3534 }
3535 }
3536
3537 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3538 struct radv_image *image, uint32_t value)
3539 {
3540
3541 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3542 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3543
3544 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3545 image->surface.dcc_size, value);
3546
3547 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3548 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3549 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3550 RADV_CMD_FLAG_INV_VMEM_L1 |
3551 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3552 }
3553
3554 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3555 struct radv_image *image,
3556 VkImageLayout src_layout,
3557 VkImageLayout dst_layout,
3558 unsigned src_queue_mask,
3559 unsigned dst_queue_mask,
3560 const VkImageSubresourceRange *range)
3561 {
3562 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3563 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3564 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3565 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3566 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3567 }
3568 }
3569
3570 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3571 struct radv_image *image,
3572 VkImageLayout src_layout,
3573 VkImageLayout dst_layout,
3574 uint32_t src_family,
3575 uint32_t dst_family,
3576 const VkImageSubresourceRange *range,
3577 VkImageAspectFlags pending_clears)
3578 {
3579 if (image->exclusive && src_family != dst_family) {
3580 /* This is an acquire or a release operation and there will be
3581 * a corresponding release/acquire. Do the transition in the
3582 * most flexible queue. */
3583
3584 assert(src_family == cmd_buffer->queue_family_index ||
3585 dst_family == cmd_buffer->queue_family_index);
3586
3587 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3588 return;
3589
3590 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3591 (src_family == RADV_QUEUE_GENERAL ||
3592 dst_family == RADV_QUEUE_GENERAL))
3593 return;
3594 }
3595
3596 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3597 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3598
3599 if (image->surface.htile_size)
3600 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3601 dst_layout, src_queue_mask,
3602 dst_queue_mask, range,
3603 pending_clears);
3604
3605 if (image->cmask.size || image->fmask.size)
3606 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3607 dst_layout, src_queue_mask,
3608 dst_queue_mask, range);
3609
3610 if (image->surface.dcc_size)
3611 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3612 dst_layout, src_queue_mask,
3613 dst_queue_mask, range);
3614 }
3615
3616 void radv_CmdPipelineBarrier(
3617 VkCommandBuffer commandBuffer,
3618 VkPipelineStageFlags srcStageMask,
3619 VkPipelineStageFlags destStageMask,
3620 VkBool32 byRegion,
3621 uint32_t memoryBarrierCount,
3622 const VkMemoryBarrier* pMemoryBarriers,
3623 uint32_t bufferMemoryBarrierCount,
3624 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3625 uint32_t imageMemoryBarrierCount,
3626 const VkImageMemoryBarrier* pImageMemoryBarriers)
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 enum radv_cmd_flush_bits src_flush_bits = 0;
3630 enum radv_cmd_flush_bits dst_flush_bits = 0;
3631
3632 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3633 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3634 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3635 NULL);
3636 }
3637
3638 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3639 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3640 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3641 NULL);
3642 }
3643
3644 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3645 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3646 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3647 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3648 image);
3649 }
3650
3651 radv_stage_flush(cmd_buffer, srcStageMask);
3652 cmd_buffer->state.flush_bits |= src_flush_bits;
3653
3654 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3655 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3656 radv_handle_image_transition(cmd_buffer, image,
3657 pImageMemoryBarriers[i].oldLayout,
3658 pImageMemoryBarriers[i].newLayout,
3659 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3660 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3661 &pImageMemoryBarriers[i].subresourceRange,
3662 0);
3663 }
3664
3665 cmd_buffer->state.flush_bits |= dst_flush_bits;
3666 }
3667
3668
3669 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3670 struct radv_event *event,
3671 VkPipelineStageFlags stageMask,
3672 unsigned value)
3673 {
3674 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3675 uint64_t va = radv_buffer_get_va(event->bo);
3676
3677 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3678
3679 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3680
3681 /* TODO: this is overkill. Probably should figure something out from
3682 * the stage mask. */
3683
3684 si_cs_emit_write_event_eop(cs,
3685 cmd_buffer->state.predicating,
3686 cmd_buffer->device->physical_device->rad_info.chip_class,
3687 false,
3688 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3689 1, va, 2, value);
3690
3691 assert(cmd_buffer->cs->cdw <= cdw_max);
3692 }
3693
3694 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3695 VkEvent _event,
3696 VkPipelineStageFlags stageMask)
3697 {
3698 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3699 RADV_FROM_HANDLE(radv_event, event, _event);
3700
3701 write_event(cmd_buffer, event, stageMask, 1);
3702 }
3703
3704 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3705 VkEvent _event,
3706 VkPipelineStageFlags stageMask)
3707 {
3708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3709 RADV_FROM_HANDLE(radv_event, event, _event);
3710
3711 write_event(cmd_buffer, event, stageMask, 0);
3712 }
3713
3714 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3715 uint32_t eventCount,
3716 const VkEvent* pEvents,
3717 VkPipelineStageFlags srcStageMask,
3718 VkPipelineStageFlags dstStageMask,
3719 uint32_t memoryBarrierCount,
3720 const VkMemoryBarrier* pMemoryBarriers,
3721 uint32_t bufferMemoryBarrierCount,
3722 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3723 uint32_t imageMemoryBarrierCount,
3724 const VkImageMemoryBarrier* pImageMemoryBarriers)
3725 {
3726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3727 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3728
3729 for (unsigned i = 0; i < eventCount; ++i) {
3730 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3731 uint64_t va = radv_buffer_get_va(event->bo);
3732
3733 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3734
3735 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3736
3737 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3738 assert(cmd_buffer->cs->cdw <= cdw_max);
3739 }
3740
3741
3742 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3743 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3744
3745 radv_handle_image_transition(cmd_buffer, image,
3746 pImageMemoryBarriers[i].oldLayout,
3747 pImageMemoryBarriers[i].newLayout,
3748 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3749 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3750 &pImageMemoryBarriers[i].subresourceRange,
3751 0);
3752 }
3753
3754 /* TODO: figure out how to do memory barriers without waiting */
3755 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3756 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3757 RADV_CMD_FLAG_INV_VMEM_L1 |
3758 RADV_CMD_FLAG_INV_SMEM_L1;
3759 }