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radv/winsys: start adding support for DMA/compute queue
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
36 struct radv_image *image,
37 VkImageLayout src_layout,
38 VkImageLayout dst_layout,
39 VkImageSubresourceRange range,
40 VkImageAspectFlags pending_clears);
41
42 const struct radv_dynamic_state default_dynamic_state = {
43 .viewport = {
44 .count = 0,
45 },
46 .scissor = {
47 .count = 0,
48 },
49 .line_width = 1.0f,
50 .depth_bias = {
51 .bias = 0.0f,
52 .clamp = 0.0f,
53 .slope = 0.0f,
54 },
55 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
56 .depth_bounds = {
57 .min = 0.0f,
58 .max = 1.0f,
59 },
60 .stencil_compare_mask = {
61 .front = ~0u,
62 .back = ~0u,
63 },
64 .stencil_write_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_reference = {
69 .front = 0u,
70 .back = 0u,
71 },
72 };
73
74 void
75 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
76 const struct radv_dynamic_state *src,
77 uint32_t copy_mask)
78 {
79 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
80 dest->viewport.count = src->viewport.count;
81 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
82 src->viewport.count);
83 }
84
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
86 dest->scissor.count = src->scissor.count;
87 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
88 src->scissor.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
92 dest->line_width = src->line_width;
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
95 dest->depth_bias = src->depth_bias;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
98 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
101 dest->depth_bounds = src->depth_bounds;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
104 dest->stencil_compare_mask = src->stencil_compare_mask;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
107 dest->stencil_write_mask = src->stencil_write_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
110 dest->stencil_reference = src->stencil_reference;
111 }
112
113 static VkResult radv_create_cmd_buffer(
114 struct radv_device * device,
115 struct radv_cmd_pool * pool,
116 VkCommandBufferLevel level,
117 VkCommandBuffer* pCommandBuffer)
118 {
119 struct radv_cmd_buffer *cmd_buffer;
120 VkResult result;
121
122 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
123 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
124 if (cmd_buffer == NULL)
125 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
126
127 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
128 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
129 cmd_buffer->device = device;
130 cmd_buffer->pool = pool;
131 cmd_buffer->level = level;
132
133 if (pool) {
134 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
135 } else {
136 /* Init the pool_link so we can safefly call list_del when we destroy
137 * the command buffer
138 */
139 list_inithead(&cmd_buffer->pool_link);
140 }
141
142 cmd_buffer->cs = device->ws->cs_create(device->ws, RING_GFX);
143 if (!cmd_buffer->cs) {
144 result = VK_ERROR_OUT_OF_HOST_MEMORY;
145 goto fail;
146 }
147
148 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
149
150 cmd_buffer->upload.offset = 0;
151 cmd_buffer->upload.size = 0;
152 list_inithead(&cmd_buffer->upload.list);
153
154 return VK_SUCCESS;
155
156 fail:
157 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
158
159 return result;
160 }
161
162 static bool
163 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
164 uint64_t min_needed)
165 {
166 uint64_t new_size;
167 struct radeon_winsys_bo *bo;
168 struct radv_cmd_buffer_upload *upload;
169 struct radv_device *device = cmd_buffer->device;
170
171 new_size = MAX2(min_needed, 16 * 1024);
172 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
173
174 bo = device->ws->buffer_create(device->ws,
175 new_size, 4096,
176 RADEON_DOMAIN_GTT,
177 RADEON_FLAG_CPU_ACCESS);
178
179 if (!bo) {
180 cmd_buffer->record_fail = true;
181 return false;
182 }
183
184 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
185 if (cmd_buffer->upload.upload_bo) {
186 upload = malloc(sizeof(*upload));
187
188 if (!upload) {
189 cmd_buffer->record_fail = true;
190 device->ws->buffer_destroy(bo);
191 return false;
192 }
193
194 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
195 list_add(&upload->list, &cmd_buffer->upload.list);
196 }
197
198 cmd_buffer->upload.upload_bo = bo;
199 cmd_buffer->upload.size = new_size;
200 cmd_buffer->upload.offset = 0;
201 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
202
203 if (!cmd_buffer->upload.map) {
204 cmd_buffer->record_fail = true;
205 return false;
206 }
207
208 return true;
209 }
210
211 bool
212 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
213 unsigned size,
214 unsigned alignment,
215 unsigned *out_offset,
216 void **ptr)
217 {
218 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
219 if (offset + size > cmd_buffer->upload.size) {
220 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
221 return false;
222 offset = 0;
223 }
224
225 *out_offset = offset;
226 *ptr = cmd_buffer->upload.map + offset;
227
228 cmd_buffer->upload.offset = offset + size;
229 return true;
230 }
231
232 bool
233 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
234 unsigned size, unsigned alignment,
235 const void *data, unsigned *out_offset)
236 {
237 uint8_t *ptr;
238
239 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
240 out_offset, (void **)&ptr))
241 return false;
242
243 if (ptr)
244 memcpy(ptr, data, size);
245
246 return true;
247 }
248
249 static void
250 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
251 struct radv_pipeline *pipeline)
252 {
253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
254 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
255 8);
256 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
257 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
258 }
259
260 static void
261 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
262 struct radv_pipeline *pipeline)
263 {
264 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
265 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
266 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
267
268 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
269 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
270 }
271
272 /* 12.4 fixed-point */
273 static unsigned radv_pack_float_12p4(float x)
274 {
275 return x <= 0 ? 0 :
276 x >= 4096 ? 0xffff : x * 16;
277 }
278
279 static uint32_t
280 shader_stage_to_user_data_0(gl_shader_stage stage)
281 {
282 switch (stage) {
283 case MESA_SHADER_FRAGMENT:
284 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
285 case MESA_SHADER_VERTEX:
286 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
287 case MESA_SHADER_COMPUTE:
288 return R_00B900_COMPUTE_USER_DATA_0;
289 default:
290 unreachable("unknown shader");
291 }
292 }
293
294 static struct ac_userdata_info *
295 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
296 gl_shader_stage stage,
297 int idx)
298 {
299 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
300 }
301
302 static void
303 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
304 struct radv_pipeline *pipeline,
305 gl_shader_stage stage,
306 int idx, uint64_t va)
307 {
308 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
309 uint32_t base_reg = shader_stage_to_user_data_0(stage);
310 if (loc->sgpr_idx == -1)
311 return;
312 assert(loc->num_sgprs == 2);
313 assert(!loc->indirect);
314 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
315 radeon_emit(cmd_buffer->cs, va);
316 radeon_emit(cmd_buffer->cs, va >> 32);
317 }
318
319 static void
320 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
321 struct radv_pipeline *pipeline)
322 {
323 int num_samples = pipeline->graphics.ms.num_samples;
324 struct radv_multisample_state *ms = &pipeline->graphics.ms;
325 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
326
327 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
328 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
329 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
330
331 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
332 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
333
334 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
335 return;
336
337 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
338 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
339 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
340
341 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
342
343 uint32_t samples_offset;
344 void *samples_ptr;
345 void *src;
346 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
347 &samples_ptr);
348 switch (num_samples) {
349 case 1:
350 src = cmd_buffer->device->sample_locations_1x;
351 break;
352 case 2:
353 src = cmd_buffer->device->sample_locations_2x;
354 break;
355 case 4:
356 src = cmd_buffer->device->sample_locations_4x;
357 break;
358 case 8:
359 src = cmd_buffer->device->sample_locations_8x;
360 break;
361 case 16:
362 src = cmd_buffer->device->sample_locations_16x;
363 break;
364 }
365 memcpy(samples_ptr, src, num_samples * 4 * 2);
366
367 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
368 va += samples_offset;
369
370 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
371 AC_UD_PS_SAMPLE_POS, va);
372 }
373
374 static void
375 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
376 struct radv_pipeline *pipeline)
377 {
378 struct radv_raster_state *raster = &pipeline->graphics.raster;
379
380 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
381 raster->pa_cl_clip_cntl);
382
383 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
384 raster->spi_interp_control);
385
386 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
387 radeon_emit(cmd_buffer->cs, 0);
388 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
389 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
390
391 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
392 raster->pa_su_vtx_cntl);
393
394 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
395 raster->pa_su_sc_mode_cntl);
396 }
397
398 static void
399 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
400 struct radv_pipeline *pipeline)
401 {
402 struct radeon_winsys *ws = cmd_buffer->device->ws;
403 struct radv_shader_variant *vs;
404 uint64_t va;
405 unsigned export_count;
406 unsigned clip_dist_mask, cull_dist_mask, total_mask;
407
408 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
409
410 vs = pipeline->shaders[MESA_SHADER_VERTEX];
411 va = ws->buffer_get_va(vs->bo);
412 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
413
414 clip_dist_mask = vs->info.vs.clip_dist_mask;
415 cull_dist_mask = vs->info.vs.cull_dist_mask;
416 total_mask = clip_dist_mask | cull_dist_mask;
417 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
418 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
419
420 export_count = MAX2(1, vs->info.vs.param_exports);
421 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
422 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
423 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
424 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
425 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
426 V_02870C_SPI_SHADER_4COMP :
427 V_02870C_SPI_SHADER_NONE) |
428 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
429 V_02870C_SPI_SHADER_4COMP :
430 V_02870C_SPI_SHADER_NONE) |
431 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
432 V_02870C_SPI_SHADER_4COMP :
433 V_02870C_SPI_SHADER_NONE));
434
435 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
436 radeon_emit(cmd_buffer->cs, va >> 8);
437 radeon_emit(cmd_buffer->cs, va >> 40);
438 radeon_emit(cmd_buffer->cs, vs->rsrc1);
439 radeon_emit(cmd_buffer->cs, vs->rsrc2);
440
441 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
442 S_028818_VTX_W0_FMT(1) |
443 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
444 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
445 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
446
447 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
448 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
449 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize) |
450 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
451 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
452 pipeline->graphics.raster.pa_cl_vs_out_cntl |
453 cull_dist_mask << 8 |
454 clip_dist_mask);
455
456 }
457
458
459
460 static void
461 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
462 struct radv_pipeline *pipeline)
463 {
464 struct radeon_winsys *ws = cmd_buffer->device->ws;
465 struct radv_shader_variant *ps, *vs;
466 uint64_t va;
467 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
468 struct radv_blend_state *blend = &pipeline->graphics.blend;
469 unsigned ps_offset = 0;
470 unsigned z_order;
471 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
472
473 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
474 vs = pipeline->shaders[MESA_SHADER_VERTEX];
475 va = ws->buffer_get_va(ps->bo);
476 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
477
478 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
479 radeon_emit(cmd_buffer->cs, va >> 8);
480 radeon_emit(cmd_buffer->cs, va >> 40);
481 radeon_emit(cmd_buffer->cs, ps->rsrc1);
482 radeon_emit(cmd_buffer->cs, ps->rsrc2);
483
484 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
485 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
486 else
487 z_order = V_02880C_LATE_Z;
488
489
490 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
491 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
492 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
493 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
494 S_02880C_Z_ORDER(z_order) |
495 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
496 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
497 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
498
499 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
500 ps->config.spi_ps_input_ena);
501
502 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
503 ps->config.spi_ps_input_addr);
504
505 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
506 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
507 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
508
509 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
510
511 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
512 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
513 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
514 V_028710_SPI_SHADER_ZERO);
515
516 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
519 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
520
521 if (ps->info.fs.has_pcoord) {
522 unsigned val;
523 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
524 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
525 ps_offset = 1;
526 }
527
528 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
529 unsigned vs_offset, flat_shade;
530 unsigned val;
531
532 if (!(ps->info.fs.input_mask & (1u << i)))
533 continue;
534
535
536 if (!(vs->info.vs.export_mask & (1u << i))) {
537 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
538 S_028644_OFFSET(0x20));
539 ++ps_offset;
540 continue;
541 }
542
543 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
544 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
545
546 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
547 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
548 ++ps_offset;
549 }
550 }
551
552 static void
553 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
554 struct radv_pipeline *pipeline)
555 {
556 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
557 return;
558
559 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
560 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
561 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
562 radv_update_multisample_state(cmd_buffer, pipeline);
563 radv_emit_vertex_shader(cmd_buffer, pipeline);
564 radv_emit_fragment_shader(cmd_buffer, pipeline);
565
566 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
567 pipeline->graphics.prim_restart_enable);
568
569 cmd_buffer->state.emitted_pipeline = pipeline;
570 }
571
572 static void
573 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
574 {
575 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
576 cmd_buffer->state.dynamic.viewport.viewports);
577 }
578
579 static void
580 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
581 {
582 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
583 si_write_scissors(cmd_buffer->cs, 0, count,
584 cmd_buffer->state.dynamic.scissor.scissors);
585 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
586 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
587 }
588
589 static void
590 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
591 int index,
592 struct radv_color_buffer_info *cb)
593 {
594 bool is_vi = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= VI;
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
596 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
597 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
598 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
599 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
600 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
601 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
602 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
603 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
604 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
605 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
606 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
607
608 if (is_vi) { /* DCC BASE */
609 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
610 }
611 }
612
613 static void
614 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_ds_buffer_info *ds,
616 struct radv_image *image,
617 VkImageLayout layout)
618 {
619 uint32_t db_z_info = ds->db_z_info;
620
621 if (!radv_layout_has_htile(image, layout))
622 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
623
624 if (!radv_layout_can_expclear(image, layout))
625 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
626
627 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
628 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
629
630 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
631 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
632 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
633 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
634 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
635 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
636 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
637 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
638 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
639 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
642 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
643 ds->pa_su_poly_offset_db_fmt_cntl);
644 }
645
646 /*
647 * To hw resolve multisample images both src and dst need to have the same
648 * micro tiling mode. However we don't always know in advance when creating
649 * the images. This function gets called if we have a resolve attachment,
650 * and tests if the attachment image has the same tiling mode, then it
651 * checks if the generated framebuffer data has the same tiling mode, and
652 * updates it if not.
653 */
654 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
655 struct radv_attachment_info *att,
656 uint32_t micro_tile_mode)
657 {
658 struct radv_image *image = att->attachment->image;
659 uint32_t tile_mode_index;
660 if (image->surface.nsamples <= 1)
661 return;
662
663 if (image->surface.micro_tile_mode != micro_tile_mode) {
664 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
665 }
666
667 if (att->cb.micro_tile_mode != micro_tile_mode) {
668 tile_mode_index = image->surface.tiling_index[0];
669
670 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
671 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
672 att->cb.micro_tile_mode = micro_tile_mode;
673 }
674 }
675
676 void
677 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_image *image,
679 VkClearDepthStencilValue ds_clear_value,
680 VkImageAspectFlags aspects)
681 {
682 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
683 va += image->offset + image->clear_value_offset;
684 unsigned reg_offset = 0, reg_count = 0;
685
686 if (!image->htile.size || !aspects)
687 return;
688
689 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
690 ++reg_count;
691 } else {
692 ++reg_offset;
693 va += 4;
694 }
695 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
696 ++reg_count;
697
698 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
699
700 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
701 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
702 S_370_WR_CONFIRM(1) |
703 S_370_ENGINE_SEL(V_370_PFP));
704 radeon_emit(cmd_buffer->cs, va);
705 radeon_emit(cmd_buffer->cs, va >> 32);
706 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
707 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
708 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
709 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
710
711 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
712 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
713 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
714 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
715 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
716 }
717
718 static void
719 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
720 struct radv_image *image)
721 {
722 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
723 va += image->offset + image->clear_value_offset;
724
725 if (!image->htile.size)
726 return;
727
728 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
729
730 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
731 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
732 COPY_DATA_DST_SEL(COPY_DATA_REG) |
733 COPY_DATA_COUNT_SEL);
734 radeon_emit(cmd_buffer->cs, va);
735 radeon_emit(cmd_buffer->cs, va >> 32);
736 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
737 radeon_emit(cmd_buffer->cs, 0);
738
739 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
740 radeon_emit(cmd_buffer->cs, 0);
741 }
742
743 void
744 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_image *image,
746 int idx,
747 uint32_t color_values[2])
748 {
749 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
750 va += image->offset + image->clear_value_offset;
751
752 if (!image->cmask.size && !image->surface.dcc_size)
753 return;
754
755 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
756
757 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
758 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
759 S_370_WR_CONFIRM(1) |
760 S_370_ENGINE_SEL(V_370_PFP));
761 radeon_emit(cmd_buffer->cs, va);
762 radeon_emit(cmd_buffer->cs, va >> 32);
763 radeon_emit(cmd_buffer->cs, color_values[0]);
764 radeon_emit(cmd_buffer->cs, color_values[1]);
765
766 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
767 radeon_emit(cmd_buffer->cs, color_values[0]);
768 radeon_emit(cmd_buffer->cs, color_values[1]);
769 }
770
771 static void
772 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
773 struct radv_image *image,
774 int idx)
775 {
776 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
777 va += image->offset + image->clear_value_offset;
778
779 if (!image->cmask.size && !image->surface.dcc_size)
780 return;
781
782 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
783 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
784
785 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
786 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
787 COPY_DATA_DST_SEL(COPY_DATA_REG) |
788 COPY_DATA_COUNT_SEL);
789 radeon_emit(cmd_buffer->cs, va);
790 radeon_emit(cmd_buffer->cs, va >> 32);
791 radeon_emit(cmd_buffer->cs, reg >> 2);
792 radeon_emit(cmd_buffer->cs, 0);
793
794 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
795 radeon_emit(cmd_buffer->cs, 0);
796 }
797
798 void
799 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
800 {
801 int i;
802 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
803 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
804 int dst_resolve_micro_tile_mode = -1;
805
806 if (subpass->has_resolve) {
807 uint32_t a = subpass->resolve_attachments[0].attachment;
808 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
809 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
810 }
811 for (i = 0; i < subpass->color_count; ++i) {
812 int idx = subpass->color_attachments[i].attachment;
813 struct radv_attachment_info *att = &framebuffer->attachments[idx];
814
815 if (dst_resolve_micro_tile_mode != -1) {
816 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
817 att, dst_resolve_micro_tile_mode);
818 }
819 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
820
821 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
822 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
823
824 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
825 }
826
827 for (i = subpass->color_count; i < 8; i++)
828 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
829 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
830
831 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
832 int idx = subpass->depth_stencil_attachment.attachment;
833 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
834 struct radv_attachment_info *att = &framebuffer->attachments[idx];
835 struct radv_image *image = att->attachment->image;
836 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
837
838 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
839
840 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
841 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
842 cmd_buffer->state.offset_scale = att->ds.offset_scale;
843 }
844 radv_load_depth_clear_regs(cmd_buffer, image);
845 } else {
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
847 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
848 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
849 }
850 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
851 S_028208_BR_X(framebuffer->width) |
852 S_028208_BR_Y(framebuffer->height));
853 }
854
855 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
856 {
857 uint32_t db_count_control;
858
859 if(!cmd_buffer->state.active_occlusion_queries) {
860 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
861 db_count_control = 0;
862 } else {
863 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
864 }
865 } else {
866 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
867 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
868 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
869 S_028004_ZPASS_ENABLE(1) |
870 S_028004_SLICE_EVEN_ENABLE(1) |
871 S_028004_SLICE_ODD_ENABLE(1);
872 } else {
873 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
874 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
875 }
876 }
877
878 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
879 }
880
881 static void
882 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
883 {
884 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
885
886 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
887 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
888 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
889 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
890 }
891
892 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
893 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
894 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
895 }
896
897 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
898 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
899 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
900 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
901 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
902 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
903 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
904 S_028430_STENCILOPVAL(1));
905 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
906 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
907 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
908 S_028434_STENCILOPVAL_BF(1));
909 }
910
911 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
912 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
913 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
914 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
915 }
916
917 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
918 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
919 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
920 unsigned slope = fui(d->depth_bias.slope * 16.0f);
921 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
922
923 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
924 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
925 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
926 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
927 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
928 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
929 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
930 }
931 }
932
933 cmd_buffer->state.dirty = 0;
934 }
935
936 static void
937 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
938 struct radv_pipeline *pipeline,
939 int idx,
940 uint64_t va,
941 gl_shader_stage stage)
942 {
943 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
944 uint32_t base_reg = shader_stage_to_user_data_0(stage);
945
946 if (desc_set_loc->sgpr_idx == -1)
947 return;
948
949 assert(!desc_set_loc->indirect);
950 assert(desc_set_loc->num_sgprs == 2);
951 radeon_set_sh_reg_seq(cmd_buffer->cs,
952 base_reg + desc_set_loc->sgpr_idx * 4, 2);
953 radeon_emit(cmd_buffer->cs, va);
954 radeon_emit(cmd_buffer->cs, va >> 32);
955 }
956
957 static void
958 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
959 struct radv_pipeline *pipeline,
960 VkShaderStageFlags stages,
961 struct radv_descriptor_set *set,
962 unsigned idx)
963 {
964 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
965 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
966 idx, set->va,
967 MESA_SHADER_FRAGMENT);
968
969 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
970 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
971 idx, set->va,
972 MESA_SHADER_VERTEX);
973
974 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
975 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
976 idx, set->va,
977 MESA_SHADER_COMPUTE);
978 }
979
980 static void
981 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
982 struct radv_pipeline *pipeline,
983 VkShaderStageFlags stages)
984 {
985 unsigned i;
986 if (!cmd_buffer->state.descriptors_dirty)
987 return;
988
989 for (i = 0; i < MAX_SETS; i++) {
990 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
991 continue;
992 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
993 if (!set)
994 continue;
995
996 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
997 }
998 cmd_buffer->state.descriptors_dirty = 0;
999 }
1000
1001 static void
1002 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1003 struct radv_pipeline *pipeline,
1004 VkShaderStageFlags stages)
1005 {
1006 struct radv_pipeline_layout *layout = pipeline->layout;
1007 unsigned offset;
1008 void *ptr;
1009 uint64_t va;
1010
1011 stages &= cmd_buffer->push_constant_stages;
1012 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1013 return;
1014
1015 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1016 16 * layout->dynamic_offset_count,
1017 256, &offset, &ptr);
1018
1019 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1020 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1021 16 * layout->dynamic_offset_count);
1022
1023 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1024 va += offset;
1025
1026 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1027 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1028 AC_UD_PUSH_CONSTANTS, va);
1029
1030 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1031 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1032 AC_UD_PUSH_CONSTANTS, va);
1033
1034 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1035 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1036 AC_UD_PUSH_CONSTANTS, va);
1037
1038 cmd_buffer->push_constant_stages &= ~stages;
1039 }
1040
1041 static void
1042 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1043 {
1044 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1045 struct radv_device *device = cmd_buffer->device;
1046 uint32_t ia_multi_vgt_param;
1047 uint32_t ls_hs_config = 0;
1048
1049 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1050 cmd_buffer->cs, 4096);
1051
1052 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1053 cmd_buffer->state.pipeline->num_vertex_attribs) {
1054 unsigned vb_offset;
1055 void *vb_ptr;
1056 uint32_t i = 0;
1057 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1058 uint64_t va;
1059
1060 /* allocate some descriptor state for vertex buffers */
1061 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1062 &vb_offset, &vb_ptr);
1063
1064 for (i = 0; i < num_attribs; i++) {
1065 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1066 uint32_t offset;
1067 int vb = cmd_buffer->state.pipeline->va_binding[i];
1068 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1069 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1070
1071 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1072 va = device->ws->buffer_get_va(buffer->bo);
1073
1074 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1075 va += offset + buffer->offset;
1076 desc[0] = va;
1077 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1078 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class <= CIK && stride)
1079 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1080 else
1081 desc[2] = buffer->size - offset;
1082 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1083 }
1084
1085 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1086 va += vb_offset;
1087
1088 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1089 AC_UD_VS_VERTEX_BUFFERS, va);
1090 }
1091
1092 cmd_buffer->state.vertex_descriptors_dirty = false;
1093 cmd_buffer->state.vb_dirty = 0;
1094 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1095 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1096
1097 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1098 radv_emit_framebuffer_state(cmd_buffer);
1099
1100 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1101 radv_emit_viewport(cmd_buffer);
1102
1103 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1104 radv_emit_scissor(cmd_buffer);
1105
1106 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1107 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1108 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1109
1110 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1111 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1112 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1113 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1114 } else {
1115 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1116 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1117 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1118 }
1119 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1120 }
1121
1122 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1123
1124 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1125 VK_SHADER_STAGE_ALL_GRAPHICS);
1126 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1127 VK_SHADER_STAGE_ALL_GRAPHICS);
1128
1129 assert(cmd_buffer->cs->cdw <= cdw_max);
1130
1131 si_emit_cache_flush(cmd_buffer);
1132 }
1133
1134 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1135 VkPipelineStageFlags src_stage_mask)
1136 {
1137 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1138 VK_PIPELINE_STAGE_TRANSFER_BIT |
1139 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1140 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1141 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1142 }
1143
1144 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1145 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1146 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1147 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1148 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1149 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1150 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1151 VK_PIPELINE_STAGE_TRANSFER_BIT |
1152 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1153 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1154 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1155 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1156 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1157 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1158 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1159 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1160 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1161 }
1162 }
1163
1164 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1165 {
1166 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1167
1168 /* TODO: actual cache flushes */
1169 }
1170
1171 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1172 VkAttachmentReference att)
1173 {
1174 unsigned idx = att.attachment;
1175 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1176 VkImageSubresourceRange range;
1177 range.aspectMask = 0;
1178 range.baseMipLevel = view->base_mip;
1179 range.levelCount = 1;
1180 range.baseArrayLayer = view->base_layer;
1181 range.layerCount = cmd_buffer->state.framebuffer->layers;
1182
1183 radv_handle_image_transition(cmd_buffer,
1184 view->image,
1185 cmd_buffer->state.attachments[idx].current_layout,
1186 att.layout, range,
1187 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1188
1189 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1190
1191
1192 }
1193
1194 void
1195 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1196 const struct radv_subpass *subpass, bool transitions)
1197 {
1198 if (transitions) {
1199 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1200
1201 for (unsigned i = 0; i < subpass->color_count; ++i) {
1202 radv_handle_subpass_image_transition(cmd_buffer,
1203 subpass->color_attachments[i]);
1204 }
1205
1206 for (unsigned i = 0; i < subpass->input_count; ++i) {
1207 radv_handle_subpass_image_transition(cmd_buffer,
1208 subpass->input_attachments[i]);
1209 }
1210
1211 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1212 radv_handle_subpass_image_transition(cmd_buffer,
1213 subpass->depth_stencil_attachment);
1214 }
1215 }
1216
1217 cmd_buffer->state.subpass = subpass;
1218
1219 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1220 }
1221
1222 static void
1223 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1224 struct radv_render_pass *pass,
1225 const VkRenderPassBeginInfo *info)
1226 {
1227 struct radv_cmd_state *state = &cmd_buffer->state;
1228
1229 if (pass->attachment_count == 0) {
1230 state->attachments = NULL;
1231 return;
1232 }
1233
1234 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1235 pass->attachment_count *
1236 sizeof(state->attachments[0]),
1237 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1238 if (state->attachments == NULL) {
1239 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1240 abort();
1241 }
1242
1243 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1244 struct radv_render_pass_attachment *att = &pass->attachments[i];
1245 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1246 VkImageAspectFlags clear_aspects = 0;
1247
1248 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1249 /* color attachment */
1250 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1251 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1252 }
1253 } else {
1254 /* depthstencil attachment */
1255 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1256 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1257 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1258 }
1259 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1260 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1261 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1262 }
1263 }
1264
1265 state->attachments[i].pending_clear_aspects = clear_aspects;
1266 if (clear_aspects && info) {
1267 assert(info->clearValueCount > i);
1268 state->attachments[i].clear_value = info->pClearValues[i];
1269 }
1270
1271 state->attachments[i].current_layout = att->initial_layout;
1272 }
1273 }
1274
1275 VkResult radv_AllocateCommandBuffers(
1276 VkDevice _device,
1277 const VkCommandBufferAllocateInfo *pAllocateInfo,
1278 VkCommandBuffer *pCommandBuffers)
1279 {
1280 RADV_FROM_HANDLE(radv_device, device, _device);
1281 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1282
1283 VkResult result = VK_SUCCESS;
1284 uint32_t i;
1285
1286 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1287 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1288 &pCommandBuffers[i]);
1289 if (result != VK_SUCCESS)
1290 break;
1291 }
1292
1293 if (result != VK_SUCCESS)
1294 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1295 i, pCommandBuffers);
1296
1297 return result;
1298 }
1299
1300 static void
1301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1302 {
1303 list_del(&cmd_buffer->pool_link);
1304
1305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1306 &cmd_buffer->upload.list, list) {
1307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1308 list_del(&up->list);
1309 free(up);
1310 }
1311
1312 if (cmd_buffer->upload.upload_bo)
1313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1315 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1316 }
1317
1318 void radv_FreeCommandBuffers(
1319 VkDevice device,
1320 VkCommandPool commandPool,
1321 uint32_t commandBufferCount,
1322 const VkCommandBuffer *pCommandBuffers)
1323 {
1324 for (uint32_t i = 0; i < commandBufferCount; i++) {
1325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1326
1327 if (cmd_buffer)
1328 radv_cmd_buffer_destroy(cmd_buffer);
1329 }
1330 }
1331
1332 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1333 {
1334
1335 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1336
1337 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1338 &cmd_buffer->upload.list, list) {
1339 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1340 list_del(&up->list);
1341 free(up);
1342 }
1343
1344 if (cmd_buffer->upload.upload_bo)
1345 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1346 cmd_buffer->upload.upload_bo, 8);
1347 cmd_buffer->upload.offset = 0;
1348
1349 cmd_buffer->record_fail = false;
1350 }
1351
1352 VkResult radv_ResetCommandBuffer(
1353 VkCommandBuffer commandBuffer,
1354 VkCommandBufferResetFlags flags)
1355 {
1356 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1357 radv_reset_cmd_buffer(cmd_buffer);
1358 return VK_SUCCESS;
1359 }
1360
1361 VkResult radv_BeginCommandBuffer(
1362 VkCommandBuffer commandBuffer,
1363 const VkCommandBufferBeginInfo *pBeginInfo)
1364 {
1365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1366 radv_reset_cmd_buffer(cmd_buffer);
1367
1368 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1369
1370 /* setup initial configuration into command buffer */
1371 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1372 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1373 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1374 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1375 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1376 RADV_CMD_FLAG_INV_VMEM_L1 |
1377 RADV_CMD_FLAG_INV_SMEM_L1 |
1378 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1379 RADV_CMD_FLAG_INV_GLOBAL_L2;
1380 si_init_config(&cmd_buffer->device->instance->physicalDevice, cmd_buffer);
1381 radv_set_db_count_control(cmd_buffer);
1382 si_emit_cache_flush(cmd_buffer);
1383 }
1384
1385 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1386 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1387 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1388
1389 struct radv_subpass *subpass =
1390 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1391
1392 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1393 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1394 }
1395
1396 return VK_SUCCESS;
1397 }
1398
1399 void radv_CmdBindVertexBuffers(
1400 VkCommandBuffer commandBuffer,
1401 uint32_t firstBinding,
1402 uint32_t bindingCount,
1403 const VkBuffer* pBuffers,
1404 const VkDeviceSize* pOffsets)
1405 {
1406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1407 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1408
1409 /* We have to defer setting up vertex buffer since we need the buffer
1410 * stride from the pipeline. */
1411
1412 assert(firstBinding + bindingCount < MAX_VBS);
1413 for (uint32_t i = 0; i < bindingCount; i++) {
1414 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1415 vb[firstBinding + i].offset = pOffsets[i];
1416 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1417 }
1418 }
1419
1420 void radv_CmdBindIndexBuffer(
1421 VkCommandBuffer commandBuffer,
1422 VkBuffer buffer,
1423 VkDeviceSize offset,
1424 VkIndexType indexType)
1425 {
1426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1427
1428 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1429 cmd_buffer->state.index_offset = offset;
1430 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1431 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1432 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1433 }
1434
1435
1436 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1437 struct radv_descriptor_set *set,
1438 unsigned idx)
1439 {
1440 struct radeon_winsys *ws = cmd_buffer->device->ws;
1441
1442 cmd_buffer->state.descriptors[idx] = set;
1443 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1444 if (!set)
1445 return;
1446
1447 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1448 if (set->descriptors[j])
1449 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1450
1451 if(set->bo)
1452 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1453 }
1454
1455 void radv_CmdBindDescriptorSets(
1456 VkCommandBuffer commandBuffer,
1457 VkPipelineBindPoint pipelineBindPoint,
1458 VkPipelineLayout _layout,
1459 uint32_t firstSet,
1460 uint32_t descriptorSetCount,
1461 const VkDescriptorSet* pDescriptorSets,
1462 uint32_t dynamicOffsetCount,
1463 const uint32_t* pDynamicOffsets)
1464 {
1465 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1466 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1467 unsigned dyn_idx = 0;
1468
1469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1470 cmd_buffer->cs, MAX_SETS * 4 * 6);
1471
1472 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1473 unsigned idx = i + firstSet;
1474 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1475 radv_bind_descriptor_set(cmd_buffer, set, idx);
1476
1477 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1478 unsigned idx = j + layout->set[i].dynamic_offset_start;
1479 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1480 assert(dyn_idx < dynamicOffsetCount);
1481
1482 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1483 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1484 dst[0] = va;
1485 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1486 dst[2] = range->size;
1487 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1488 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1489 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1490 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1491 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1492 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1493 cmd_buffer->push_constant_stages |=
1494 set->layout->dynamic_shader_stages;
1495 }
1496 }
1497
1498 assert(cmd_buffer->cs->cdw <= cdw_max);
1499 }
1500
1501 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1502 VkPipelineLayout layout,
1503 VkShaderStageFlags stageFlags,
1504 uint32_t offset,
1505 uint32_t size,
1506 const void* pValues)
1507 {
1508 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1509 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1510 cmd_buffer->push_constant_stages |= stageFlags;
1511 }
1512
1513 VkResult radv_EndCommandBuffer(
1514 VkCommandBuffer commandBuffer)
1515 {
1516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1517
1518 si_emit_cache_flush(cmd_buffer);
1519 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1520 cmd_buffer->record_fail)
1521 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1522 return VK_SUCCESS;
1523 }
1524
1525 static void
1526 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1527 {
1528 struct radeon_winsys *ws = cmd_buffer->device->ws;
1529 struct radv_shader_variant *compute_shader;
1530 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1531 uint64_t va;
1532
1533 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1534 return;
1535
1536 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1537
1538 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1539 va = ws->buffer_get_va(compute_shader->bo);
1540
1541 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1542
1543 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1544 cmd_buffer->cs, 16);
1545
1546 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1547 radeon_emit(cmd_buffer->cs, va >> 8);
1548 radeon_emit(cmd_buffer->cs, va >> 40);
1549
1550 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1551 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1552 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1553
1554 /* change these once we have scratch support */
1555 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1556 S_00B860_WAVES(32) | S_00B860_WAVESIZE(0));
1557
1558 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1559 radeon_emit(cmd_buffer->cs,
1560 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1561 radeon_emit(cmd_buffer->cs,
1562 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1563 radeon_emit(cmd_buffer->cs,
1564 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1565
1566 assert(cmd_buffer->cs->cdw <= cdw_max);
1567 }
1568
1569
1570 void radv_CmdBindPipeline(
1571 VkCommandBuffer commandBuffer,
1572 VkPipelineBindPoint pipelineBindPoint,
1573 VkPipeline _pipeline)
1574 {
1575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1576 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1577
1578 for (unsigned i = 0; i < MAX_SETS; i++) {
1579 if (cmd_buffer->state.descriptors[i])
1580 cmd_buffer->state.descriptors_dirty |= (1 << i);
1581 }
1582
1583 switch (pipelineBindPoint) {
1584 case VK_PIPELINE_BIND_POINT_COMPUTE:
1585 cmd_buffer->state.compute_pipeline = pipeline;
1586 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1587 break;
1588 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1589 cmd_buffer->state.pipeline = pipeline;
1590 cmd_buffer->state.vertex_descriptors_dirty = true;
1591 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1592 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1593
1594 /* Apply the dynamic state from the pipeline */
1595 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1596 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1597 &pipeline->dynamic_state,
1598 pipeline->dynamic_state_mask);
1599 break;
1600 default:
1601 assert(!"invalid bind point");
1602 break;
1603 }
1604 }
1605
1606 void radv_CmdSetViewport(
1607 VkCommandBuffer commandBuffer,
1608 uint32_t firstViewport,
1609 uint32_t viewportCount,
1610 const VkViewport* pViewports)
1611 {
1612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1613
1614 const uint32_t total_count = firstViewport + viewportCount;
1615 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1616 cmd_buffer->state.dynamic.viewport.count = total_count;
1617
1618 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1619 pViewports, viewportCount * sizeof(*pViewports));
1620
1621 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1622 }
1623
1624 void radv_CmdSetScissor(
1625 VkCommandBuffer commandBuffer,
1626 uint32_t firstScissor,
1627 uint32_t scissorCount,
1628 const VkRect2D* pScissors)
1629 {
1630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1631
1632 const uint32_t total_count = firstScissor + scissorCount;
1633 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1634 cmd_buffer->state.dynamic.scissor.count = total_count;
1635
1636 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1637 pScissors, scissorCount * sizeof(*pScissors));
1638 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1639 }
1640
1641 void radv_CmdSetLineWidth(
1642 VkCommandBuffer commandBuffer,
1643 float lineWidth)
1644 {
1645 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1646 cmd_buffer->state.dynamic.line_width = lineWidth;
1647 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1648 }
1649
1650 void radv_CmdSetDepthBias(
1651 VkCommandBuffer commandBuffer,
1652 float depthBiasConstantFactor,
1653 float depthBiasClamp,
1654 float depthBiasSlopeFactor)
1655 {
1656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1657
1658 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1659 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1660 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1661
1662 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1663 }
1664
1665 void radv_CmdSetBlendConstants(
1666 VkCommandBuffer commandBuffer,
1667 const float blendConstants[4])
1668 {
1669 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1670
1671 memcpy(cmd_buffer->state.dynamic.blend_constants,
1672 blendConstants, sizeof(float) * 4);
1673
1674 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1675 }
1676
1677 void radv_CmdSetDepthBounds(
1678 VkCommandBuffer commandBuffer,
1679 float minDepthBounds,
1680 float maxDepthBounds)
1681 {
1682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1683
1684 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1685 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1686
1687 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1688 }
1689
1690 void radv_CmdSetStencilCompareMask(
1691 VkCommandBuffer commandBuffer,
1692 VkStencilFaceFlags faceMask,
1693 uint32_t compareMask)
1694 {
1695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1696
1697 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1698 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1699 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1700 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1701
1702 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1703 }
1704
1705 void radv_CmdSetStencilWriteMask(
1706 VkCommandBuffer commandBuffer,
1707 VkStencilFaceFlags faceMask,
1708 uint32_t writeMask)
1709 {
1710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1711
1712 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1713 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1714 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1715 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1716
1717 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1718 }
1719
1720 void radv_CmdSetStencilReference(
1721 VkCommandBuffer commandBuffer,
1722 VkStencilFaceFlags faceMask,
1723 uint32_t reference)
1724 {
1725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1726
1727 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1728 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1729 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1730 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1731
1732 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1733 }
1734
1735
1736 void radv_CmdExecuteCommands(
1737 VkCommandBuffer commandBuffer,
1738 uint32_t commandBufferCount,
1739 const VkCommandBuffer* pCmdBuffers)
1740 {
1741 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1742
1743 for (uint32_t i = 0; i < commandBufferCount; i++) {
1744 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1745
1746 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1747 }
1748
1749 /* if we execute secondary we need to re-emit out pipelines */
1750 if (commandBufferCount) {
1751 primary->state.emitted_pipeline = NULL;
1752 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1753 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1754 }
1755 }
1756
1757 VkResult radv_CreateCommandPool(
1758 VkDevice _device,
1759 const VkCommandPoolCreateInfo* pCreateInfo,
1760 const VkAllocationCallbacks* pAllocator,
1761 VkCommandPool* pCmdPool)
1762 {
1763 RADV_FROM_HANDLE(radv_device, device, _device);
1764 struct radv_cmd_pool *pool;
1765
1766 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1767 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1768 if (pool == NULL)
1769 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1770
1771 if (pAllocator)
1772 pool->alloc = *pAllocator;
1773 else
1774 pool->alloc = device->alloc;
1775
1776 list_inithead(&pool->cmd_buffers);
1777
1778 *pCmdPool = radv_cmd_pool_to_handle(pool);
1779
1780 return VK_SUCCESS;
1781
1782 }
1783
1784 void radv_DestroyCommandPool(
1785 VkDevice _device,
1786 VkCommandPool commandPool,
1787 const VkAllocationCallbacks* pAllocator)
1788 {
1789 RADV_FROM_HANDLE(radv_device, device, _device);
1790 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1791
1792 if (!pool)
1793 return;
1794
1795 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1796 &pool->cmd_buffers, pool_link) {
1797 radv_cmd_buffer_destroy(cmd_buffer);
1798 }
1799
1800 vk_free2(&device->alloc, pAllocator, pool);
1801 }
1802
1803 VkResult radv_ResetCommandPool(
1804 VkDevice device,
1805 VkCommandPool commandPool,
1806 VkCommandPoolResetFlags flags)
1807 {
1808 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1809
1810 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1811 &pool->cmd_buffers, pool_link) {
1812 radv_reset_cmd_buffer(cmd_buffer);
1813 }
1814
1815 return VK_SUCCESS;
1816 }
1817
1818 void radv_CmdBeginRenderPass(
1819 VkCommandBuffer commandBuffer,
1820 const VkRenderPassBeginInfo* pRenderPassBegin,
1821 VkSubpassContents contents)
1822 {
1823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1824 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1825 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1826
1827 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1828 cmd_buffer->cs, 2048);
1829
1830 cmd_buffer->state.framebuffer = framebuffer;
1831 cmd_buffer->state.pass = pass;
1832 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1833 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1834
1835 si_emit_cache_flush(cmd_buffer);
1836
1837 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1838 assert(cmd_buffer->cs->cdw <= cdw_max);
1839
1840 radv_cmd_buffer_clear_subpass(cmd_buffer);
1841 }
1842
1843 void radv_CmdNextSubpass(
1844 VkCommandBuffer commandBuffer,
1845 VkSubpassContents contents)
1846 {
1847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1848
1849 si_emit_cache_flush(cmd_buffer);
1850 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1851
1852 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1853 2048);
1854
1855 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1856 radv_cmd_buffer_clear_subpass(cmd_buffer);
1857 }
1858
1859 void radv_CmdDraw(
1860 VkCommandBuffer commandBuffer,
1861 uint32_t vertexCount,
1862 uint32_t instanceCount,
1863 uint32_t firstVertex,
1864 uint32_t firstInstance)
1865 {
1866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1867 radv_cmd_buffer_flush_state(cmd_buffer);
1868
1869 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1870
1871 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1872 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1873 if (loc->sgpr_idx != -1) {
1874 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1875 radeon_emit(cmd_buffer->cs, firstVertex);
1876 radeon_emit(cmd_buffer->cs, firstInstance);
1877 }
1878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1879 radeon_emit(cmd_buffer->cs, instanceCount);
1880
1881 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1882 radeon_emit(cmd_buffer->cs, vertexCount);
1883 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1884 S_0287F0_USE_OPAQUE(0));
1885
1886 assert(cmd_buffer->cs->cdw <= cdw_max);
1887 }
1888
1889 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
1890 {
1891 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
1892
1893 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
1894 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1895 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1896 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1897 primitive_reset_index);
1898 }
1899 }
1900
1901 void radv_CmdDrawIndexed(
1902 VkCommandBuffer commandBuffer,
1903 uint32_t indexCount,
1904 uint32_t instanceCount,
1905 uint32_t firstIndex,
1906 int32_t vertexOffset,
1907 uint32_t firstInstance)
1908 {
1909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1910 int index_size = cmd_buffer->state.index_type ? 4 : 2;
1911 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
1912 uint64_t index_va;
1913
1914 radv_cmd_buffer_flush_state(cmd_buffer);
1915 radv_emit_primitive_reset_index(cmd_buffer);
1916
1917 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
1918
1919 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1920 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
1921
1922 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1923 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1924 if (loc->sgpr_idx != -1) {
1925 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1926 radeon_emit(cmd_buffer->cs, vertexOffset);
1927 radeon_emit(cmd_buffer->cs, firstInstance);
1928 }
1929 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1930 radeon_emit(cmd_buffer->cs, instanceCount);
1931
1932 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
1933 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
1934 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
1935 radeon_emit(cmd_buffer->cs, index_max_size);
1936 radeon_emit(cmd_buffer->cs, index_va);
1937 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
1938 radeon_emit(cmd_buffer->cs, indexCount);
1939 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
1940
1941 assert(cmd_buffer->cs->cdw <= cdw_max);
1942 }
1943
1944 static void
1945 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
1946 VkBuffer _buffer,
1947 VkDeviceSize offset,
1948 VkBuffer _count_buffer,
1949 VkDeviceSize count_offset,
1950 uint32_t draw_count,
1951 uint32_t stride,
1952 bool indexed)
1953 {
1954 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1955 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
1956 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1957 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
1958 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
1959 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
1960 indirect_va += offset + buffer->offset;
1961 uint64_t count_va = 0;
1962
1963 if (count_buffer) {
1964 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
1965 count_va += count_offset + count_buffer->offset;
1966 }
1967
1968 if (!draw_count)
1969 return;
1970
1971 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
1972
1973 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1974 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1975 assert(loc->sgpr_idx != -1);
1976 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
1977 radeon_emit(cs, 1);
1978 radeon_emit(cs, indirect_va);
1979 radeon_emit(cs, indirect_va >> 32);
1980
1981 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
1982 PKT3_DRAW_INDIRECT_MULTI,
1983 8, false));
1984 radeon_emit(cs, 0);
1985 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
1986 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
1987 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
1988 radeon_emit(cs, draw_count); /* count */
1989 radeon_emit(cs, count_va); /* count_addr */
1990 radeon_emit(cs, count_va >> 32);
1991 radeon_emit(cs, stride); /* stride */
1992 radeon_emit(cs, di_src_sel);
1993 }
1994
1995 static void
1996 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
1997 VkBuffer buffer,
1998 VkDeviceSize offset,
1999 VkBuffer countBuffer,
2000 VkDeviceSize countBufferOffset,
2001 uint32_t maxDrawCount,
2002 uint32_t stride)
2003 {
2004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2005 radv_cmd_buffer_flush_state(cmd_buffer);
2006
2007 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2008 cmd_buffer->cs, 14);
2009
2010 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2011 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2012
2013 assert(cmd_buffer->cs->cdw <= cdw_max);
2014 }
2015
2016 static void
2017 radv_cmd_draw_indexed_indirect_count(
2018 VkCommandBuffer commandBuffer,
2019 VkBuffer buffer,
2020 VkDeviceSize offset,
2021 VkBuffer countBuffer,
2022 VkDeviceSize countBufferOffset,
2023 uint32_t maxDrawCount,
2024 uint32_t stride)
2025 {
2026 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2027 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2028 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2029 uint64_t index_va;
2030 radv_cmd_buffer_flush_state(cmd_buffer);
2031 radv_emit_primitive_reset_index(cmd_buffer);
2032
2033 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2034 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2035
2036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2037
2038 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2039 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2040
2041 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2042 radeon_emit(cmd_buffer->cs, index_va);
2043 radeon_emit(cmd_buffer->cs, index_va >> 32);
2044
2045 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2046 radeon_emit(cmd_buffer->cs, index_max_size);
2047
2048 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2049 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2050
2051 assert(cmd_buffer->cs->cdw <= cdw_max);
2052 }
2053
2054 void radv_CmdDrawIndirect(
2055 VkCommandBuffer commandBuffer,
2056 VkBuffer buffer,
2057 VkDeviceSize offset,
2058 uint32_t drawCount,
2059 uint32_t stride)
2060 {
2061 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2062 VK_NULL_HANDLE, 0, drawCount, stride);
2063 }
2064
2065 void radv_CmdDrawIndexedIndirect(
2066 VkCommandBuffer commandBuffer,
2067 VkBuffer buffer,
2068 VkDeviceSize offset,
2069 uint32_t drawCount,
2070 uint32_t stride)
2071 {
2072 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2073 VK_NULL_HANDLE, 0, drawCount, stride);
2074 }
2075
2076 void radv_CmdDrawIndirectCountAMD(
2077 VkCommandBuffer commandBuffer,
2078 VkBuffer buffer,
2079 VkDeviceSize offset,
2080 VkBuffer countBuffer,
2081 VkDeviceSize countBufferOffset,
2082 uint32_t maxDrawCount,
2083 uint32_t stride)
2084 {
2085 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2086 countBuffer, countBufferOffset,
2087 maxDrawCount, stride);
2088 }
2089
2090 void radv_CmdDrawIndexedIndirectCountAMD(
2091 VkCommandBuffer commandBuffer,
2092 VkBuffer buffer,
2093 VkDeviceSize offset,
2094 VkBuffer countBuffer,
2095 VkDeviceSize countBufferOffset,
2096 uint32_t maxDrawCount,
2097 uint32_t stride)
2098 {
2099 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2100 countBuffer, countBufferOffset,
2101 maxDrawCount, stride);
2102 }
2103
2104 static void
2105 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2106 {
2107 radv_emit_compute_pipeline(cmd_buffer);
2108 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2109 VK_SHADER_STAGE_COMPUTE_BIT);
2110 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2111 VK_SHADER_STAGE_COMPUTE_BIT);
2112 si_emit_cache_flush(cmd_buffer);
2113 }
2114
2115 void radv_CmdDispatch(
2116 VkCommandBuffer commandBuffer,
2117 uint32_t x,
2118 uint32_t y,
2119 uint32_t z)
2120 {
2121 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2122
2123 radv_flush_compute_state(cmd_buffer);
2124
2125 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2126
2127 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2128 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2129 if (loc->sgpr_idx != -1) {
2130 assert(!loc->indirect);
2131 assert(loc->num_sgprs == 3);
2132 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2133 radeon_emit(cmd_buffer->cs, x);
2134 radeon_emit(cmd_buffer->cs, y);
2135 radeon_emit(cmd_buffer->cs, z);
2136 }
2137
2138 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2139 PKT3_SHADER_TYPE_S(1));
2140 radeon_emit(cmd_buffer->cs, x);
2141 radeon_emit(cmd_buffer->cs, y);
2142 radeon_emit(cmd_buffer->cs, z);
2143 radeon_emit(cmd_buffer->cs, 1);
2144
2145 assert(cmd_buffer->cs->cdw <= cdw_max);
2146 }
2147
2148 void radv_CmdDispatchIndirect(
2149 VkCommandBuffer commandBuffer,
2150 VkBuffer _buffer,
2151 VkDeviceSize offset)
2152 {
2153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2154 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2155 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2156 va += buffer->offset + offset;
2157
2158 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2159
2160 radv_flush_compute_state(cmd_buffer);
2161
2162 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2163 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2164 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2165 if (loc->sgpr_idx != -1) {
2166 for (unsigned i = 0; i < 3; ++i) {
2167 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2168 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2169 COPY_DATA_DST_SEL(COPY_DATA_REG));
2170 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2171 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2172 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2173 radeon_emit(cmd_buffer->cs, 0);
2174 }
2175 }
2176
2177 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2178 PKT3_SHADER_TYPE_S(1));
2179 radeon_emit(cmd_buffer->cs, 1);
2180 radeon_emit(cmd_buffer->cs, va);
2181 radeon_emit(cmd_buffer->cs, va >> 32);
2182
2183 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2184 PKT3_SHADER_TYPE_S(1));
2185 radeon_emit(cmd_buffer->cs, 0);
2186 radeon_emit(cmd_buffer->cs, 1);
2187
2188 assert(cmd_buffer->cs->cdw <= cdw_max);
2189 }
2190
2191 void radv_unaligned_dispatch(
2192 struct radv_cmd_buffer *cmd_buffer,
2193 uint32_t x,
2194 uint32_t y,
2195 uint32_t z)
2196 {
2197 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2198 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2199 uint32_t blocks[3], remainder[3];
2200
2201 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2202 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2203 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2204
2205 /* If aligned, these should be an entire block size, not 0 */
2206 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2207 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2208 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2209
2210 radv_flush_compute_state(cmd_buffer);
2211
2212 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2213
2214 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2215 radeon_emit(cmd_buffer->cs,
2216 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2217 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2218 radeon_emit(cmd_buffer->cs,
2219 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2220 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2221 radeon_emit(cmd_buffer->cs,
2222 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2223 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2224
2225 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2226 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2227 if (loc->sgpr_idx != -1) {
2228 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2229 radeon_emit(cmd_buffer->cs, blocks[0]);
2230 radeon_emit(cmd_buffer->cs, blocks[1]);
2231 radeon_emit(cmd_buffer->cs, blocks[2]);
2232 }
2233 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2234 PKT3_SHADER_TYPE_S(1));
2235 radeon_emit(cmd_buffer->cs, blocks[0]);
2236 radeon_emit(cmd_buffer->cs, blocks[1]);
2237 radeon_emit(cmd_buffer->cs, blocks[2]);
2238 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2239 S_00B800_PARTIAL_TG_EN(1));
2240
2241 assert(cmd_buffer->cs->cdw <= cdw_max);
2242 }
2243
2244 void radv_CmdEndRenderPass(
2245 VkCommandBuffer commandBuffer)
2246 {
2247 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2248
2249 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2250
2251 si_emit_cache_flush(cmd_buffer);
2252 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2253
2254 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2255 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2256 radv_handle_subpass_image_transition(cmd_buffer,
2257 (VkAttachmentReference){i, layout});
2258 }
2259
2260 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2261
2262 cmd_buffer->state.pass = NULL;
2263 cmd_buffer->state.subpass = NULL;
2264 cmd_buffer->state.attachments = NULL;
2265 cmd_buffer->state.framebuffer = NULL;
2266 }
2267
2268
2269 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2270 struct radv_image *image)
2271 {
2272
2273 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2274 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2275
2276 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2277 image->htile.size, 0xffffffff);
2278
2279 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2280 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2281 RADV_CMD_FLAG_INV_VMEM_L1 |
2282 RADV_CMD_FLAG_INV_GLOBAL_L2;
2283 }
2284
2285 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2286 struct radv_image *image,
2287 VkImageLayout src_layout,
2288 VkImageLayout dst_layout,
2289 VkImageSubresourceRange range,
2290 VkImageAspectFlags pending_clears)
2291 {
2292 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2293 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2294 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2295 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2296 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2297 /* The clear will initialize htile. */
2298 return;
2299 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2300 radv_layout_has_htile(image, dst_layout)) {
2301 /* TODO: merge with the clear if applicable */
2302 radv_initialize_htile(cmd_buffer, image);
2303 } else if (!radv_layout_has_htile(image, src_layout) &&
2304 radv_layout_has_htile(image, dst_layout)) {
2305 radv_initialize_htile(cmd_buffer, image);
2306 } else if ((radv_layout_has_htile(image, src_layout) &&
2307 !radv_layout_has_htile(image, dst_layout)) ||
2308 (radv_layout_is_htile_compressed(image, src_layout) &&
2309 !radv_layout_is_htile_compressed(image, dst_layout))) {
2310
2311 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2312 range.baseMipLevel = 0;
2313 range.levelCount = 1;
2314
2315 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2316 }
2317 }
2318
2319 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2320 struct radv_image *image, uint32_t value)
2321 {
2322 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2323 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2324
2325 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2326 image->cmask.size, value);
2327
2328 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2329 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2330 RADV_CMD_FLAG_INV_VMEM_L1 |
2331 RADV_CMD_FLAG_INV_GLOBAL_L2;
2332 }
2333
2334 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2335 struct radv_image *image,
2336 VkImageLayout src_layout,
2337 VkImageLayout dst_layout,
2338 VkImageSubresourceRange range,
2339 VkImageAspectFlags pending_clears)
2340 {
2341 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2342 if (image->fmask.size)
2343 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2344 else
2345 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2346 } else if (radv_layout_has_cmask(image, src_layout) &&
2347 !radv_layout_has_cmask(image, dst_layout)) {
2348 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2349 }
2350 }
2351
2352 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2353 struct radv_image *image, uint32_t value)
2354 {
2355
2356 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2357 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2358
2359 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2360 image->surface.dcc_size, value);
2361
2362 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2363 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2364 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2365 RADV_CMD_FLAG_INV_VMEM_L1 |
2366 RADV_CMD_FLAG_INV_GLOBAL_L2;
2367 }
2368
2369 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2370 struct radv_image *image,
2371 VkImageLayout src_layout,
2372 VkImageLayout dst_layout,
2373 VkImageSubresourceRange range,
2374 VkImageAspectFlags pending_clears)
2375 {
2376 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2377 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2378 } else if(src_layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
2379 dst_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
2380 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2381 }
2382 }
2383
2384 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2385 struct radv_image *image,
2386 VkImageLayout src_layout,
2387 VkImageLayout dst_layout,
2388 VkImageSubresourceRange range,
2389 VkImageAspectFlags pending_clears)
2390 {
2391 if (image->htile.size)
2392 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2393 dst_layout, range, pending_clears);
2394
2395 if (image->cmask.size)
2396 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2397 dst_layout, range, pending_clears);
2398
2399 if (image->surface.dcc_size)
2400 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2401 dst_layout, range, pending_clears);
2402 }
2403
2404 void radv_CmdPipelineBarrier(
2405 VkCommandBuffer commandBuffer,
2406 VkPipelineStageFlags srcStageMask,
2407 VkPipelineStageFlags destStageMask,
2408 VkBool32 byRegion,
2409 uint32_t memoryBarrierCount,
2410 const VkMemoryBarrier* pMemoryBarriers,
2411 uint32_t bufferMemoryBarrierCount,
2412 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2413 uint32_t imageMemoryBarrierCount,
2414 const VkImageMemoryBarrier* pImageMemoryBarriers)
2415 {
2416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2417 VkAccessFlags src_flags = 0;
2418 VkAccessFlags dst_flags = 0;
2419 uint32_t b;
2420 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2421 src_flags |= pMemoryBarriers[i].srcAccessMask;
2422 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2423 }
2424
2425 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2426 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2427 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2428 }
2429
2430 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2431 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2432 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2433 }
2434
2435 enum radv_cmd_flush_bits flush_bits = 0;
2436 for_each_bit(b, src_flags) {
2437 switch ((VkAccessFlagBits)(1 << b)) {
2438 case VK_ACCESS_SHADER_WRITE_BIT:
2439 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2440 break;
2441 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2442 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2443 break;
2444 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2445 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2446 break;
2447 case VK_ACCESS_TRANSFER_WRITE_BIT:
2448 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2449 break;
2450 default:
2451 break;
2452 }
2453 }
2454 cmd_buffer->state.flush_bits |= flush_bits;
2455
2456 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2457 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2458 radv_handle_image_transition(cmd_buffer, image,
2459 pImageMemoryBarriers[i].oldLayout,
2460 pImageMemoryBarriers[i].newLayout,
2461 pImageMemoryBarriers[i].subresourceRange,
2462 0);
2463 }
2464
2465 flush_bits = 0;
2466
2467 for_each_bit(b, dst_flags) {
2468 switch ((VkAccessFlagBits)(1 << b)) {
2469 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2470 case VK_ACCESS_INDEX_READ_BIT:
2471 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2472 case VK_ACCESS_UNIFORM_READ_BIT:
2473 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2474 break;
2475 case VK_ACCESS_SHADER_READ_BIT:
2476 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2477 break;
2478 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2479 case VK_ACCESS_TRANSFER_READ_BIT:
2480 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2481 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2482 default:
2483 break;
2484 }
2485 }
2486
2487 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2488 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2489
2490 cmd_buffer->state.flush_bits |= flush_bits;
2491 }
2492
2493
2494 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2495 struct radv_event *event,
2496 VkPipelineStageFlags stageMask,
2497 unsigned value)
2498 {
2499 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2500 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2501
2502 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2503
2504 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2505
2506 /* TODO: this is overkill. Probably should figure something out from
2507 * the stage mask. */
2508
2509 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class == CIK) {
2510 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2511 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2512 EVENT_INDEX(5));
2513 radeon_emit(cs, va);
2514 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2515 radeon_emit(cs, 2);
2516 radeon_emit(cs, 0);
2517 }
2518
2519 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2520 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2521 EVENT_INDEX(5));
2522 radeon_emit(cs, va);
2523 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2524 radeon_emit(cs, value);
2525 radeon_emit(cs, 0);
2526
2527 assert(cmd_buffer->cs->cdw <= cdw_max);
2528 }
2529
2530 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2531 VkEvent _event,
2532 VkPipelineStageFlags stageMask)
2533 {
2534 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2535 RADV_FROM_HANDLE(radv_event, event, _event);
2536
2537 write_event(cmd_buffer, event, stageMask, 1);
2538 }
2539
2540 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2541 VkEvent _event,
2542 VkPipelineStageFlags stageMask)
2543 {
2544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2545 RADV_FROM_HANDLE(radv_event, event, _event);
2546
2547 write_event(cmd_buffer, event, stageMask, 0);
2548 }
2549
2550 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2551 uint32_t eventCount,
2552 const VkEvent* pEvents,
2553 VkPipelineStageFlags srcStageMask,
2554 VkPipelineStageFlags dstStageMask,
2555 uint32_t memoryBarrierCount,
2556 const VkMemoryBarrier* pMemoryBarriers,
2557 uint32_t bufferMemoryBarrierCount,
2558 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2559 uint32_t imageMemoryBarrierCount,
2560 const VkImageMemoryBarrier* pImageMemoryBarriers)
2561 {
2562 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2563 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2564
2565 for (unsigned i = 0; i < eventCount; ++i) {
2566 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2567 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2568
2569 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2570
2571 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2572
2573 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2574 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2575 radeon_emit(cs, va);
2576 radeon_emit(cs, va >> 32);
2577 radeon_emit(cs, 1); /* reference value */
2578 radeon_emit(cs, 0xffffffff); /* mask */
2579 radeon_emit(cs, 4); /* poll interval */
2580
2581 assert(cmd_buffer->cs->cdw <= cdw_max);
2582 }
2583
2584
2585 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2586 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2587
2588 radv_handle_image_transition(cmd_buffer, image,
2589 pImageMemoryBarriers[i].oldLayout,
2590 pImageMemoryBarriers[i].newLayout,
2591 pImageMemoryBarriers[i].subresourceRange,
2592 0);
2593 }
2594
2595 /* TODO: figure out how to do memory barriers without waiting */
2596 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2597 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2598 RADV_CMD_FLAG_INV_VMEM_L1 |
2599 RADV_CMD_FLAG_INV_SMEM_L1;
2600 }