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radv: only re-mit the index type when it changes
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
597 return;
598
599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
600 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
602
603 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
604
605 /* GFX9: Flush DFSM when the AA mode changes. */
606 if (cmd_buffer->device->dfsm_allowed) {
607 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
608 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
609 }
610 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
611 uint32_t offset;
612 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
613 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
614 if (loc->sgpr_idx == -1)
615 return;
616 assert(loc->num_sgprs == 1);
617 assert(!loc->indirect);
618 switch (num_samples) {
619 default:
620 offset = 0;
621 break;
622 case 2:
623 offset = 1;
624 break;
625 case 4:
626 offset = 3;
627 break;
628 case 8:
629 offset = 7;
630 break;
631 case 16:
632 offset = 15;
633 break;
634 }
635
636 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
637 cmd_buffer->sample_positions_needed = true;
638 }
639 }
640
641 static void
642 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline)
644 {
645 struct radv_raster_state *raster = &pipeline->graphics.raster;
646
647 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
648 raster->pa_cl_clip_cntl);
649 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
650 raster->spi_interp_control);
651 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
652 raster->pa_su_vtx_cntl);
653 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
654 raster->pa_su_sc_mode_cntl);
655 }
656
657 static inline void
658 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
659 unsigned size)
660 {
661 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
662 si_cp_dma_prefetch(cmd_buffer, va, size);
663 }
664
665 static void
666 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
667 {
668 if (cmd_buffer->state.vb_prefetch_dirty) {
669 radv_emit_prefetch_TC_L2_async(cmd_buffer,
670 cmd_buffer->state.vb_va,
671 cmd_buffer->state.vb_size);
672 cmd_buffer->state.vb_prefetch_dirty = false;
673 }
674 }
675
676 static void
677 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_shader_variant *shader)
679 {
680 struct radeon_winsys *ws = cmd_buffer->device->ws;
681 struct radeon_winsys_cs *cs = cmd_buffer->cs;
682 uint64_t va;
683
684 if (!shader)
685 return;
686
687 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
688
689 radv_cs_add_buffer(ws, cs, shader->bo, 8);
690 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
691 }
692
693 static void
694 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
695 struct radv_pipeline *pipeline)
696 {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_VERTEX]);
699 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
704 radv_emit_shader_prefetch(cmd_buffer,
705 pipeline->shaders[MESA_SHADER_GEOMETRY]);
706 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709 }
710
711 static void
712 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline,
714 struct radv_shader_variant *shader)
715 {
716 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
717
718 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
719 pipeline->graphics.vs.spi_vs_out_config);
720
721 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
722 pipeline->graphics.vs.spi_shader_pos_format);
723
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
725 radeon_emit(cmd_buffer->cs, va >> 8);
726 radeon_emit(cmd_buffer->cs, va >> 40);
727 radeon_emit(cmd_buffer->cs, shader->rsrc1);
728 radeon_emit(cmd_buffer->cs, shader->rsrc2);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
731 S_028818_VTX_W0_FMT(1) |
732 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
733 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
734 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
735
736
737 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
738 pipeline->graphics.vs.pa_cl_vs_out_cntl);
739
740 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
741 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
742 pipeline->graphics.vs.vgt_reuse_off);
743 }
744
745 static void
746 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
747 struct radv_pipeline *pipeline,
748 struct radv_shader_variant *shader)
749 {
750 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
751
752 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
753 radeon_emit(cmd_buffer->cs, va >> 8);
754 radeon_emit(cmd_buffer->cs, va >> 40);
755 radeon_emit(cmd_buffer->cs, shader->rsrc1);
756 radeon_emit(cmd_buffer->cs, shader->rsrc2);
757 }
758
759 static void
760 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_shader_variant *shader)
762 {
763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
764 uint32_t rsrc2 = shader->rsrc2;
765
766 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
767 radeon_emit(cmd_buffer->cs, va >> 8);
768 radeon_emit(cmd_buffer->cs, va >> 40);
769
770 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
771 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
772 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
773 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
774
775 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
776 radeon_emit(cmd_buffer->cs, shader->rsrc1);
777 radeon_emit(cmd_buffer->cs, rsrc2);
778 }
779
780 static void
781 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
782 struct radv_shader_variant *shader)
783 {
784 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
785
786 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
787 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
788 radeon_emit(cmd_buffer->cs, va >> 8);
789 radeon_emit(cmd_buffer->cs, va >> 40);
790
791 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
792 radeon_emit(cmd_buffer->cs, shader->rsrc1);
793 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
794 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
795 } else {
796 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
797 radeon_emit(cmd_buffer->cs, va >> 8);
798 radeon_emit(cmd_buffer->cs, va >> 40);
799 radeon_emit(cmd_buffer->cs, shader->rsrc1);
800 radeon_emit(cmd_buffer->cs, shader->rsrc2);
801 }
802 }
803
804 static void
805 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
806 struct radv_pipeline *pipeline)
807 {
808 struct radv_shader_variant *vs;
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
811
812 /* Skip shaders merged into HS/GS */
813 vs = pipeline->shaders[MESA_SHADER_VERTEX];
814 if (!vs)
815 return;
816
817 if (vs->info.vs.as_ls)
818 radv_emit_hw_ls(cmd_buffer, vs);
819 else if (vs->info.vs.as_es)
820 radv_emit_hw_es(cmd_buffer, pipeline, vs);
821 else
822 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
823 }
824
825
826 static void
827 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
828 struct radv_pipeline *pipeline)
829 {
830 if (!radv_pipeline_has_tess(pipeline))
831 return;
832
833 struct radv_shader_variant *tes, *tcs;
834
835 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
836 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
837
838 if (tes) {
839 if (tes->info.tes.as_es)
840 radv_emit_hw_es(cmd_buffer, pipeline, tes);
841 else
842 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
843 }
844
845 radv_emit_hw_hs(cmd_buffer, tcs);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
848 pipeline->graphics.tess.tf_param);
849
850 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
851 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
852 pipeline->graphics.tess.ls_hs_config);
853 else
854 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
855 pipeline->graphics.tess.ls_hs_config);
856
857 struct ac_userdata_info *loc;
858
859 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
860 if (loc->sgpr_idx != -1) {
861 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
862 assert(loc->num_sgprs == 4);
863 assert(!loc->indirect);
864 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
868 pipeline->graphics.tess.num_tcs_input_cp << 26);
869 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
870 }
871
872 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
873 if (loc->sgpr_idx != -1) {
874 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
875 assert(loc->num_sgprs == 1);
876 assert(!loc->indirect);
877
878 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
879 pipeline->graphics.tess.offchip_layout);
880 }
881
882 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
883 if (loc->sgpr_idx != -1) {
884 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
885 assert(loc->num_sgprs == 1);
886 assert(!loc->indirect);
887
888 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
889 pipeline->graphics.tess.tcs_in_layout);
890 }
891 }
892
893 static void
894 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
895 struct radv_pipeline *pipeline)
896 {
897 struct radv_shader_variant *gs;
898 uint64_t va;
899
900 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
901
902 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
903 if (!gs)
904 return;
905
906 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
907
908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
916
917 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
918 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
919 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
920 radeon_emit(cmd_buffer->cs, 0);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923
924 uint32_t gs_num_invocations = gs->info.gs.invocations;
925 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
926 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
927 S_028B90_ENABLE(gs_num_invocations > 0));
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
930 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
931
932 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
933
934 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
935 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
936 radeon_emit(cmd_buffer->cs, va >> 8);
937 radeon_emit(cmd_buffer->cs, va >> 40);
938
939 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
940 radeon_emit(cmd_buffer->cs, gs->rsrc1);
941 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
942 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
943
944 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
945 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
946 } else {
947 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
948 radeon_emit(cmd_buffer->cs, va >> 8);
949 radeon_emit(cmd_buffer->cs, va >> 40);
950 radeon_emit(cmd_buffer->cs, gs->rsrc1);
951 radeon_emit(cmd_buffer->cs, gs->rsrc2);
952 }
953
954 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
955
956 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
957 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
958 if (loc->sgpr_idx != -1) {
959 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
960 uint32_t num_entries = 64;
961 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
962
963 if (is_vi)
964 num_entries *= stride;
965
966 stride = S_008F04_STRIDE(stride);
967 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
968 radeon_emit(cmd_buffer->cs, stride);
969 radeon_emit(cmd_buffer->cs, num_entries);
970 }
971 }
972
973 static void
974 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_pipeline *pipeline)
976 {
977 struct radv_shader_variant *ps;
978 uint64_t va;
979 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
980 struct radv_blend_state *blend = &pipeline->graphics.blend;
981 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
984 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
985
986 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
987 radeon_emit(cmd_buffer->cs, va >> 8);
988 radeon_emit(cmd_buffer->cs, va >> 40);
989 radeon_emit(cmd_buffer->cs, ps->rsrc1);
990 radeon_emit(cmd_buffer->cs, ps->rsrc2);
991
992 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
993 pipeline->graphics.db_shader_control);
994
995 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
996 ps->config.spi_ps_input_ena);
997
998 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
999 ps->config.spi_ps_input_addr);
1000
1001 if (ps->info.info.ps.force_persample)
1002 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1005 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1008
1009 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1010 pipeline->graphics.shader_z_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1013
1014 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1015 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1016
1017 if (cmd_buffer->device->dfsm_allowed) {
1018 /* optimise this? */
1019 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1020 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1021 }
1022
1023 if (pipeline->graphics.ps_input_cntl_num) {
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1025 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1026 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1027 }
1028 }
1029 }
1030
1031 static void
1032 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_pipeline *pipeline)
1034 {
1035 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1036
1037 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1038 return;
1039
1040 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1041 pipeline->graphics.vtx_reuse_depth);
1042 }
1043
1044 static void
1045 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1046 {
1047 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1048
1049 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1050 return;
1051
1052 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1053 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1054 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1055 radv_update_multisample_state(cmd_buffer, pipeline);
1056 radv_emit_vertex_shader(cmd_buffer, pipeline);
1057 radv_emit_tess_shaders(cmd_buffer, pipeline);
1058 radv_emit_geometry_shader(cmd_buffer, pipeline);
1059 radv_emit_fragment_shader(cmd_buffer, pipeline);
1060 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1061
1062 cmd_buffer->scratch_size_needed =
1063 MAX2(cmd_buffer->scratch_size_needed,
1064 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1065
1066 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1067 S_0286E8_WAVES(pipeline->max_waves) |
1068 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1069
1070 if (!cmd_buffer->state.emitted_pipeline ||
1071 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1072 pipeline->graphics.can_use_guardband)
1073 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1074
1075 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1076
1077 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1078 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1079 } else {
1080 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1081 }
1082 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1083
1084 if (unlikely(cmd_buffer->device->trace_bo))
1085 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1086
1087 cmd_buffer->state.emitted_pipeline = pipeline;
1088
1089 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1090 }
1091
1092 static void
1093 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1094 {
1095 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1096 cmd_buffer->state.dynamic.viewport.viewports);
1097 }
1098
1099 static void
1100 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1101 {
1102 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1103
1104 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1105 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1106 si_emit_cache_flush(cmd_buffer);
1107 }
1108 si_write_scissors(cmd_buffer->cs, 0, count,
1109 cmd_buffer->state.dynamic.scissor.scissors,
1110 cmd_buffer->state.dynamic.viewport.viewports,
1111 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1112 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1113 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1114 }
1115
1116 static void
1117 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1120
1121 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1122 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1123 }
1124
1125 static void
1126 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1127 {
1128 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1129
1130 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1131 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1132 }
1133
1134 static void
1135 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1136 {
1137 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs,
1140 R_028430_DB_STENCILREFMASK, 2);
1141 radeon_emit(cmd_buffer->cs,
1142 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1143 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1144 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1145 S_028430_STENCILOPVAL(1));
1146 radeon_emit(cmd_buffer->cs,
1147 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1148 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1149 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1150 S_028434_STENCILOPVAL_BF(1));
1151 }
1152
1153 static void
1154 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1155 {
1156 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1157
1158 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1159 fui(d->depth_bounds.min));
1160 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1161 fui(d->depth_bounds.max));
1162 }
1163
1164 static void
1165 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1166 {
1167 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1168 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1169 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1170 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1171
1172 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1173 radeon_set_context_reg_seq(cmd_buffer->cs,
1174 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1175 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1176 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1178 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1179 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1180 }
1181 }
1182
1183 static void
1184 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1185 int index,
1186 struct radv_attachment_info *att)
1187 {
1188 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1189 struct radv_color_buffer_info *cb = &att->cb;
1190
1191 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1192 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1196 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1197 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1199 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1204
1205 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1206 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1207 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1208
1209 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1210 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1211 } else {
1212 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1216 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1217 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1219 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1222 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1223 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1224
1225 if (is_vi) { /* DCC BASE */
1226 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1227 }
1228 }
1229 }
1230
1231 static void
1232 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1233 struct radv_ds_buffer_info *ds,
1234 struct radv_image *image,
1235 VkImageLayout layout)
1236 {
1237 uint32_t db_z_info = ds->db_z_info;
1238 uint32_t db_stencil_info = ds->db_stencil_info;
1239
1240 if (!radv_layout_has_htile(image, layout,
1241 radv_image_queue_family_mask(image,
1242 cmd_buffer->queue_family_index,
1243 cmd_buffer->queue_family_index))) {
1244 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1245 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1246 }
1247
1248 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1249 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1250
1251
1252 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1254 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1255 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1256 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1257
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1259 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1260 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1261 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1262 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1263 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1265 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1267 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1268 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1269
1270 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1271 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1272 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1273 } else {
1274 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1275
1276 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1277 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1278 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1279 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1280 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1282 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1283 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1284 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1285 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1286
1287 }
1288
1289 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1290 ds->pa_su_poly_offset_db_fmt_cntl);
1291 }
1292
1293 void
1294 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image,
1296 VkClearDepthStencilValue ds_clear_value,
1297 VkImageAspectFlags aspects)
1298 {
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 va += image->offset + image->clear_value_offset;
1301 unsigned reg_offset = 0, reg_count = 0;
1302
1303 if (!image->surface.htile_size)
1304 return;
1305
1306 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1307 ++reg_count;
1308 } else {
1309 ++reg_offset;
1310 va += 4;
1311 }
1312 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1313 ++reg_count;
1314
1315 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1316 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1317 S_370_WR_CONFIRM(1) |
1318 S_370_ENGINE_SEL(V_370_PFP));
1319 radeon_emit(cmd_buffer->cs, va);
1320 radeon_emit(cmd_buffer->cs, va >> 32);
1321 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1322 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1323 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1324 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1325
1326 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1327 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1328 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1329 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1330 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1331 }
1332
1333 static void
1334 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1335 struct radv_image *image)
1336 {
1337 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1338 uint64_t va = radv_buffer_get_va(image->bo);
1339 va += image->offset + image->clear_value_offset;
1340 unsigned reg_offset = 0, reg_count = 0;
1341
1342 if (!image->surface.htile_size)
1343 return;
1344
1345 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1346 ++reg_count;
1347 } else {
1348 ++reg_offset;
1349 va += 4;
1350 }
1351 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1352 ++reg_count;
1353
1354 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1355 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1356 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1357 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1358 radeon_emit(cmd_buffer->cs, va);
1359 radeon_emit(cmd_buffer->cs, va >> 32);
1360 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1361 radeon_emit(cmd_buffer->cs, 0);
1362
1363 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1364 radeon_emit(cmd_buffer->cs, 0);
1365 }
1366
1367 /*
1368 *with DCC some colors don't require CMASK elimiation before being
1369 * used as a texture. This sets a predicate value to determine if the
1370 * cmask eliminate is required.
1371 */
1372 void
1373 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 bool value)
1376 {
1377 uint64_t pred_val = value;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379 va += image->offset + image->dcc_pred_offset;
1380
1381 if (!image->surface.dcc_size)
1382 return;
1383
1384 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1385 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP));
1388 radeon_emit(cmd_buffer->cs, va);
1389 radeon_emit(cmd_buffer->cs, va >> 32);
1390 radeon_emit(cmd_buffer->cs, pred_val);
1391 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1392 }
1393
1394 void
1395 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_image *image,
1397 int idx,
1398 uint32_t color_values[2])
1399 {
1400 uint64_t va = radv_buffer_get_va(image->bo);
1401 va += image->offset + image->clear_value_offset;
1402
1403 if (!image->cmask.size && !image->surface.dcc_size)
1404 return;
1405
1406 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1407 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1408 S_370_WR_CONFIRM(1) |
1409 S_370_ENGINE_SEL(V_370_PFP));
1410 radeon_emit(cmd_buffer->cs, va);
1411 radeon_emit(cmd_buffer->cs, va >> 32);
1412 radeon_emit(cmd_buffer->cs, color_values[0]);
1413 radeon_emit(cmd_buffer->cs, color_values[1]);
1414
1415 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1416 radeon_emit(cmd_buffer->cs, color_values[0]);
1417 radeon_emit(cmd_buffer->cs, color_values[1]);
1418 }
1419
1420 static void
1421 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1422 struct radv_image *image,
1423 int idx)
1424 {
1425 uint64_t va = radv_buffer_get_va(image->bo);
1426 va += image->offset + image->clear_value_offset;
1427
1428 if (!image->cmask.size && !image->surface.dcc_size)
1429 return;
1430
1431 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1432
1433 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1434 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1435 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1436 COPY_DATA_COUNT_SEL);
1437 radeon_emit(cmd_buffer->cs, va);
1438 radeon_emit(cmd_buffer->cs, va >> 32);
1439 radeon_emit(cmd_buffer->cs, reg >> 2);
1440 radeon_emit(cmd_buffer->cs, 0);
1441
1442 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1443 radeon_emit(cmd_buffer->cs, 0);
1444 }
1445
1446 static void
1447 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1448 {
1449 int i;
1450 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1451 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1452
1453 /* this may happen for inherited secondary recording */
1454 if (!framebuffer)
1455 return;
1456
1457 for (i = 0; i < 8; ++i) {
1458 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1459 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1460 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1461 continue;
1462 }
1463
1464 int idx = subpass->color_attachments[i].attachment;
1465 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1466
1467 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1468
1469 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1470 radv_emit_fb_color_state(cmd_buffer, i, att);
1471
1472 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1473 }
1474
1475 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1476 int idx = subpass->depth_stencil_attachment.attachment;
1477 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1478 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1479 struct radv_image *image = att->attachment->image;
1480 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1481 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1482 cmd_buffer->queue_family_index,
1483 cmd_buffer->queue_family_index);
1484 /* We currently don't support writing decompressed HTILE */
1485 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1486 radv_layout_is_htile_compressed(image, layout, queue_mask));
1487
1488 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1489
1490 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1491 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1492 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1493 }
1494 radv_load_depth_clear_regs(cmd_buffer, image);
1495 } else {
1496 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1498 else
1499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1500
1501 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1502 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1503 }
1504 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1505 S_028208_BR_X(framebuffer->width) |
1506 S_028208_BR_Y(framebuffer->height));
1507
1508 if (cmd_buffer->device->dfsm_allowed) {
1509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1510 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1511 }
1512
1513 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1514 }
1515
1516 static void
1517 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1518 {
1519 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1520 struct radv_cmd_state *state = &cmd_buffer->state;
1521
1522 if (state->index_type != state->last_index_type) {
1523 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1524 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1525 2, state->index_type);
1526 } else {
1527 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1528 radeon_emit(cs, state->index_type);
1529 }
1530
1531 state->last_index_type = state->index_type;
1532 }
1533
1534 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1535 radeon_emit(cs, state->index_va);
1536 radeon_emit(cs, state->index_va >> 32);
1537
1538 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1539 radeon_emit(cs, state->max_index_count);
1540
1541 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1542 }
1543
1544 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1545 {
1546 uint32_t db_count_control;
1547
1548 if(!cmd_buffer->state.active_occlusion_queries) {
1549 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1550 db_count_control = 0;
1551 } else {
1552 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1553 }
1554 } else {
1555 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1556 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1557 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1558 S_028004_ZPASS_ENABLE(1) |
1559 S_028004_SLICE_EVEN_ENABLE(1) |
1560 S_028004_SLICE_ODD_ENABLE(1);
1561 } else {
1562 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1563 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1564 }
1565 }
1566
1567 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1568 }
1569
1570 static void
1571 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1572 {
1573 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1574 return;
1575
1576 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1577 radv_emit_viewport(cmd_buffer);
1578
1579 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1580 radv_emit_scissor(cmd_buffer);
1581
1582 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1583 radv_emit_line_width(cmd_buffer);
1584
1585 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1586 radv_emit_blend_constants(cmd_buffer);
1587
1588 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1589 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1590 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1591 radv_emit_stencil(cmd_buffer);
1592
1593 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1594 radv_emit_depth_bounds(cmd_buffer);
1595
1596 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1597 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1598 radv_emit_depth_biais(cmd_buffer);
1599
1600 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1601 }
1602
1603 static void
1604 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1605 struct radv_pipeline *pipeline,
1606 int idx,
1607 uint64_t va,
1608 gl_shader_stage stage)
1609 {
1610 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1611 uint32_t base_reg = pipeline->user_data_0[stage];
1612
1613 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1614 return;
1615
1616 assert(!desc_set_loc->indirect);
1617 assert(desc_set_loc->num_sgprs == 2);
1618 radeon_set_sh_reg_seq(cmd_buffer->cs,
1619 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1620 radeon_emit(cmd_buffer->cs, va);
1621 radeon_emit(cmd_buffer->cs, va >> 32);
1622 }
1623
1624 static void
1625 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1626 VkShaderStageFlags stages,
1627 struct radv_descriptor_set *set,
1628 unsigned idx)
1629 {
1630 if (cmd_buffer->state.pipeline) {
1631 radv_foreach_stage(stage, stages) {
1632 if (cmd_buffer->state.pipeline->shaders[stage])
1633 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1634 idx, set->va,
1635 stage);
1636 }
1637 }
1638
1639 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1640 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1641 idx, set->va,
1642 MESA_SHADER_COMPUTE);
1643 }
1644
1645 static void
1646 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1647 {
1648 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1649 unsigned bo_offset;
1650
1651 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1652 set->mapped_ptr,
1653 &bo_offset))
1654 return;
1655
1656 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1657 set->va += bo_offset;
1658 }
1659
1660 static void
1661 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1662 {
1663 uint32_t size = MAX_SETS * 2 * 4;
1664 uint32_t offset;
1665 void *ptr;
1666
1667 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1668 256, &offset, &ptr))
1669 return;
1670
1671 for (unsigned i = 0; i < MAX_SETS; i++) {
1672 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1673 uint64_t set_va = 0;
1674 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1675 if (cmd_buffer->state.valid_descriptors & (1u << i))
1676 set_va = set->va;
1677 uptr[0] = set_va & 0xffffffff;
1678 uptr[1] = set_va >> 32;
1679 }
1680
1681 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1682 va += offset;
1683
1684 if (cmd_buffer->state.pipeline) {
1685 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696
1697 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1698 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1699 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1700
1701 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1702 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1703 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1704 }
1705
1706 if (cmd_buffer->state.compute_pipeline)
1707 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1708 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1709 }
1710
1711 static void
1712 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1713 VkShaderStageFlags stages)
1714 {
1715 unsigned i;
1716
1717 if (!cmd_buffer->state.descriptors_dirty)
1718 return;
1719
1720 if (cmd_buffer->state.push_descriptors_dirty)
1721 radv_flush_push_descriptors(cmd_buffer);
1722
1723 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1724 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1725 radv_flush_indirect_descriptor_sets(cmd_buffer);
1726 }
1727
1728 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1729 cmd_buffer->cs,
1730 MAX_SETS * MESA_SHADER_STAGES * 4);
1731
1732 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1733 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1734 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1735 continue;
1736
1737 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1738 }
1739 cmd_buffer->state.descriptors_dirty = 0;
1740 cmd_buffer->state.push_descriptors_dirty = false;
1741
1742 if (unlikely(cmd_buffer->device->trace_bo))
1743 radv_save_descriptors(cmd_buffer);
1744
1745 assert(cmd_buffer->cs->cdw <= cdw_max);
1746 }
1747
1748 static void
1749 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1750 struct radv_pipeline *pipeline,
1751 VkShaderStageFlags stages)
1752 {
1753 struct radv_pipeline_layout *layout = pipeline->layout;
1754 unsigned offset;
1755 void *ptr;
1756 uint64_t va;
1757
1758 stages &= cmd_buffer->push_constant_stages;
1759 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1760 return;
1761
1762 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1763 16 * layout->dynamic_offset_count,
1764 256, &offset, &ptr))
1765 return;
1766
1767 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1768 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1769 16 * layout->dynamic_offset_count);
1770
1771 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1772 va += offset;
1773
1774 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1775 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1776
1777 radv_foreach_stage(stage, stages) {
1778 if (pipeline->shaders[stage]) {
1779 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1780 AC_UD_PUSH_CONSTANTS, va);
1781 }
1782 }
1783
1784 cmd_buffer->push_constant_stages &= ~stages;
1785 assert(cmd_buffer->cs->cdw <= cdw_max);
1786 }
1787
1788 static bool
1789 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1790 {
1791 if ((pipeline_is_dirty ||
1792 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1793 cmd_buffer->state.pipeline->vertex_elements.count &&
1794 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1795 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1796 unsigned vb_offset;
1797 void *vb_ptr;
1798 uint32_t i = 0;
1799 uint32_t count = velems->count;
1800 uint64_t va;
1801
1802 /* allocate some descriptor state for vertex buffers */
1803 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1804 &vb_offset, &vb_ptr))
1805 return false;
1806
1807 for (i = 0; i < count; i++) {
1808 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1809 uint32_t offset;
1810 int vb = velems->binding[i];
1811 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1812 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1813
1814 va = radv_buffer_get_va(buffer->bo);
1815
1816 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1817 va += offset + buffer->offset;
1818 desc[0] = va;
1819 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1820 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1821 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1822 else
1823 desc[2] = buffer->size - offset;
1824 desc[3] = velems->rsrc_word3[i];
1825 }
1826
1827 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1828 va += vb_offset;
1829
1830 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1831 AC_UD_VS_VERTEX_BUFFERS, va);
1832
1833 cmd_buffer->state.vb_va = va;
1834 cmd_buffer->state.vb_size = count * 16;
1835 cmd_buffer->state.vb_prefetch_dirty = true;
1836 }
1837 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1838
1839 return true;
1840 }
1841
1842 static bool
1843 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1844 {
1845 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1846 return false;
1847
1848 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1849 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1850 VK_SHADER_STAGE_ALL_GRAPHICS);
1851
1852 return true;
1853 }
1854
1855 static void
1856 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1857 bool instanced_draw, bool indirect_draw,
1858 uint32_t draw_vertex_count)
1859 {
1860 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1861 struct radv_cmd_state *state = &cmd_buffer->state;
1862 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1863 uint32_t ia_multi_vgt_param;
1864 int32_t primitive_reset_en;
1865
1866 /* Draw state. */
1867 ia_multi_vgt_param =
1868 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1869 indirect_draw, draw_vertex_count);
1870
1871 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1872 if (info->chip_class >= GFX9) {
1873 radeon_set_uconfig_reg_idx(cs,
1874 R_030960_IA_MULTI_VGT_PARAM,
1875 4, ia_multi_vgt_param);
1876 } else if (info->chip_class >= CIK) {
1877 radeon_set_context_reg_idx(cs,
1878 R_028AA8_IA_MULTI_VGT_PARAM,
1879 1, ia_multi_vgt_param);
1880 } else {
1881 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1882 ia_multi_vgt_param);
1883 }
1884 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1885 }
1886
1887 /* Primitive restart. */
1888 primitive_reset_en =
1889 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1890
1891 if (primitive_reset_en != state->last_primitive_reset_en) {
1892 state->last_primitive_reset_en = primitive_reset_en;
1893 if (info->chip_class >= GFX9) {
1894 radeon_set_uconfig_reg(cs,
1895 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1896 primitive_reset_en);
1897 } else {
1898 radeon_set_context_reg(cs,
1899 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1900 primitive_reset_en);
1901 }
1902 }
1903
1904 if (primitive_reset_en) {
1905 uint32_t primitive_reset_index =
1906 state->index_type ? 0xffffffffu : 0xffffu;
1907
1908 if (primitive_reset_index != state->last_primitive_reset_index) {
1909 radeon_set_context_reg(cs,
1910 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1911 primitive_reset_index);
1912 state->last_primitive_reset_index = primitive_reset_index;
1913 }
1914 }
1915 }
1916
1917 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1918 VkPipelineStageFlags src_stage_mask)
1919 {
1920 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1921 VK_PIPELINE_STAGE_TRANSFER_BIT |
1922 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1923 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1924 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1925 }
1926
1927 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1928 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1929 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1930 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1931 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1932 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1933 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1934 VK_PIPELINE_STAGE_TRANSFER_BIT |
1935 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1936 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1937 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1938 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1939 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1940 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1941 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1942 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1943 }
1944 }
1945
1946 static enum radv_cmd_flush_bits
1947 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1948 VkAccessFlags src_flags)
1949 {
1950 enum radv_cmd_flush_bits flush_bits = 0;
1951 uint32_t b;
1952 for_each_bit(b, src_flags) {
1953 switch ((VkAccessFlagBits)(1 << b)) {
1954 case VK_ACCESS_SHADER_WRITE_BIT:
1955 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1956 break;
1957 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1958 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1959 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1960 break;
1961 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1962 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1963 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1964 break;
1965 case VK_ACCESS_TRANSFER_WRITE_BIT:
1966 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1967 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1968 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1969 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1970 RADV_CMD_FLAG_INV_GLOBAL_L2;
1971 break;
1972 default:
1973 break;
1974 }
1975 }
1976 return flush_bits;
1977 }
1978
1979 static enum radv_cmd_flush_bits
1980 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1981 VkAccessFlags dst_flags,
1982 struct radv_image *image)
1983 {
1984 enum radv_cmd_flush_bits flush_bits = 0;
1985 uint32_t b;
1986 for_each_bit(b, dst_flags) {
1987 switch ((VkAccessFlagBits)(1 << b)) {
1988 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1989 case VK_ACCESS_INDEX_READ_BIT:
1990 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1991 break;
1992 case VK_ACCESS_UNIFORM_READ_BIT:
1993 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1994 break;
1995 case VK_ACCESS_SHADER_READ_BIT:
1996 case VK_ACCESS_TRANSFER_READ_BIT:
1997 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1998 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1999 RADV_CMD_FLAG_INV_GLOBAL_L2;
2000 break;
2001 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2002 /* TODO: change to image && when the image gets passed
2003 * through from the subpass. */
2004 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2005 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2006 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2007 break;
2008 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2009 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2010 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2011 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2012 break;
2013 default:
2014 break;
2015 }
2016 }
2017 return flush_bits;
2018 }
2019
2020 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2021 {
2022 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2023 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2024 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2025 NULL);
2026 }
2027
2028 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2029 VkAttachmentReference att)
2030 {
2031 unsigned idx = att.attachment;
2032 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2033 VkImageSubresourceRange range;
2034 range.aspectMask = 0;
2035 range.baseMipLevel = view->base_mip;
2036 range.levelCount = 1;
2037 range.baseArrayLayer = view->base_layer;
2038 range.layerCount = cmd_buffer->state.framebuffer->layers;
2039
2040 radv_handle_image_transition(cmd_buffer,
2041 view->image,
2042 cmd_buffer->state.attachments[idx].current_layout,
2043 att.layout, 0, 0, &range,
2044 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2045
2046 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2047
2048
2049 }
2050
2051 void
2052 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2053 const struct radv_subpass *subpass, bool transitions)
2054 {
2055 if (transitions) {
2056 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2057
2058 for (unsigned i = 0; i < subpass->color_count; ++i) {
2059 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2060 radv_handle_subpass_image_transition(cmd_buffer,
2061 subpass->color_attachments[i]);
2062 }
2063
2064 for (unsigned i = 0; i < subpass->input_count; ++i) {
2065 radv_handle_subpass_image_transition(cmd_buffer,
2066 subpass->input_attachments[i]);
2067 }
2068
2069 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2070 radv_handle_subpass_image_transition(cmd_buffer,
2071 subpass->depth_stencil_attachment);
2072 }
2073 }
2074
2075 cmd_buffer->state.subpass = subpass;
2076
2077 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2078 }
2079
2080 static VkResult
2081 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2082 struct radv_render_pass *pass,
2083 const VkRenderPassBeginInfo *info)
2084 {
2085 struct radv_cmd_state *state = &cmd_buffer->state;
2086
2087 if (pass->attachment_count == 0) {
2088 state->attachments = NULL;
2089 return VK_SUCCESS;
2090 }
2091
2092 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2093 pass->attachment_count *
2094 sizeof(state->attachments[0]),
2095 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2096 if (state->attachments == NULL) {
2097 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2098 return cmd_buffer->record_result;
2099 }
2100
2101 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2102 struct radv_render_pass_attachment *att = &pass->attachments[i];
2103 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2104 VkImageAspectFlags clear_aspects = 0;
2105
2106 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2107 /* color attachment */
2108 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2109 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2110 }
2111 } else {
2112 /* depthstencil attachment */
2113 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2114 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2115 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2116 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2117 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2118 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2119 }
2120 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2121 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2122 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2123 }
2124 }
2125
2126 state->attachments[i].pending_clear_aspects = clear_aspects;
2127 state->attachments[i].cleared_views = 0;
2128 if (clear_aspects && info) {
2129 assert(info->clearValueCount > i);
2130 state->attachments[i].clear_value = info->pClearValues[i];
2131 }
2132
2133 state->attachments[i].current_layout = att->initial_layout;
2134 }
2135
2136 return VK_SUCCESS;
2137 }
2138
2139 VkResult radv_AllocateCommandBuffers(
2140 VkDevice _device,
2141 const VkCommandBufferAllocateInfo *pAllocateInfo,
2142 VkCommandBuffer *pCommandBuffers)
2143 {
2144 RADV_FROM_HANDLE(radv_device, device, _device);
2145 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2146
2147 VkResult result = VK_SUCCESS;
2148 uint32_t i;
2149
2150 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2151
2152 if (!list_empty(&pool->free_cmd_buffers)) {
2153 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2154
2155 list_del(&cmd_buffer->pool_link);
2156 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2157
2158 result = radv_reset_cmd_buffer(cmd_buffer);
2159 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2160 cmd_buffer->level = pAllocateInfo->level;
2161
2162 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2163 } else {
2164 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2165 &pCommandBuffers[i]);
2166 }
2167 if (result != VK_SUCCESS)
2168 break;
2169 }
2170
2171 if (result != VK_SUCCESS) {
2172 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2173 i, pCommandBuffers);
2174
2175 /* From the Vulkan 1.0.66 spec:
2176 *
2177 * "vkAllocateCommandBuffers can be used to create multiple
2178 * command buffers. If the creation of any of those command
2179 * buffers fails, the implementation must destroy all
2180 * successfully created command buffer objects from this
2181 * command, set all entries of the pCommandBuffers array to
2182 * NULL and return the error."
2183 */
2184 memset(pCommandBuffers, 0,
2185 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2186 }
2187
2188 return result;
2189 }
2190
2191 void radv_FreeCommandBuffers(
2192 VkDevice device,
2193 VkCommandPool commandPool,
2194 uint32_t commandBufferCount,
2195 const VkCommandBuffer *pCommandBuffers)
2196 {
2197 for (uint32_t i = 0; i < commandBufferCount; i++) {
2198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2199
2200 if (cmd_buffer) {
2201 if (cmd_buffer->pool) {
2202 list_del(&cmd_buffer->pool_link);
2203 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2204 } else
2205 radv_cmd_buffer_destroy(cmd_buffer);
2206
2207 }
2208 }
2209 }
2210
2211 VkResult radv_ResetCommandBuffer(
2212 VkCommandBuffer commandBuffer,
2213 VkCommandBufferResetFlags flags)
2214 {
2215 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2216 return radv_reset_cmd_buffer(cmd_buffer);
2217 }
2218
2219 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2220 {
2221 struct radv_device *device = cmd_buffer->device;
2222 if (device->gfx_init) {
2223 uint64_t va = radv_buffer_get_va(device->gfx_init);
2224 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2225 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2226 radeon_emit(cmd_buffer->cs, va);
2227 radeon_emit(cmd_buffer->cs, va >> 32);
2228 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2229 } else
2230 si_init_config(cmd_buffer);
2231 }
2232
2233 VkResult radv_BeginCommandBuffer(
2234 VkCommandBuffer commandBuffer,
2235 const VkCommandBufferBeginInfo *pBeginInfo)
2236 {
2237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2238 VkResult result = VK_SUCCESS;
2239
2240 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2241 /* If the command buffer has already been resetted with
2242 * vkResetCommandBuffer, no need to do it again.
2243 */
2244 result = radv_reset_cmd_buffer(cmd_buffer);
2245 if (result != VK_SUCCESS)
2246 return result;
2247 }
2248
2249 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2250 cmd_buffer->state.last_primitive_reset_en = -1;
2251 cmd_buffer->state.last_index_type = -1;
2252 cmd_buffer->usage_flags = pBeginInfo->flags;
2253
2254 /* setup initial configuration into command buffer */
2255 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2256 switch (cmd_buffer->queue_family_index) {
2257 case RADV_QUEUE_GENERAL:
2258 emit_gfx_buffer_state(cmd_buffer);
2259 break;
2260 case RADV_QUEUE_COMPUTE:
2261 si_init_compute(cmd_buffer);
2262 break;
2263 case RADV_QUEUE_TRANSFER:
2264 default:
2265 break;
2266 }
2267 }
2268
2269 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2270 assert(pBeginInfo->pInheritanceInfo);
2271 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2272 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2273
2274 struct radv_subpass *subpass =
2275 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2276
2277 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2278 if (result != VK_SUCCESS)
2279 return result;
2280
2281 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2282 }
2283
2284 if (unlikely(cmd_buffer->device->trace_bo))
2285 radv_cmd_buffer_trace_emit(cmd_buffer);
2286
2287 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2288
2289 return result;
2290 }
2291
2292 void radv_CmdBindVertexBuffers(
2293 VkCommandBuffer commandBuffer,
2294 uint32_t firstBinding,
2295 uint32_t bindingCount,
2296 const VkBuffer* pBuffers,
2297 const VkDeviceSize* pOffsets)
2298 {
2299 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2300 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2301 bool changed = false;
2302
2303 /* We have to defer setting up vertex buffer since we need the buffer
2304 * stride from the pipeline. */
2305
2306 assert(firstBinding + bindingCount <= MAX_VBS);
2307 for (uint32_t i = 0; i < bindingCount; i++) {
2308 uint32_t idx = firstBinding + i;
2309
2310 if (!changed &&
2311 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2312 vb[idx].offset != pOffsets[i])) {
2313 changed = true;
2314 }
2315
2316 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2317 vb[idx].offset = pOffsets[i];
2318
2319 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2320 vb[idx].buffer->bo, 8);
2321 }
2322
2323 if (!changed) {
2324 /* No state changes. */
2325 return;
2326 }
2327
2328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2329 }
2330
2331 void radv_CmdBindIndexBuffer(
2332 VkCommandBuffer commandBuffer,
2333 VkBuffer buffer,
2334 VkDeviceSize offset,
2335 VkIndexType indexType)
2336 {
2337 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2338 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2339
2340 if (cmd_buffer->state.index_buffer == index_buffer &&
2341 cmd_buffer->state.index_offset == offset &&
2342 cmd_buffer->state.index_type == indexType) {
2343 /* No state changes. */
2344 return;
2345 }
2346
2347 cmd_buffer->state.index_buffer = index_buffer;
2348 cmd_buffer->state.index_offset = offset;
2349 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2350 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2351 cmd_buffer->state.index_va += index_buffer->offset + offset;
2352
2353 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2354 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2355 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2356 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2357 }
2358
2359
2360 static void
2361 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2362 struct radv_descriptor_set *set, unsigned idx)
2363 {
2364 struct radeon_winsys *ws = cmd_buffer->device->ws;
2365
2366 radv_set_descriptor_set(cmd_buffer, set, idx);
2367 if (!set)
2368 return;
2369
2370 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2371
2372 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2373 if (set->descriptors[j])
2374 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2375
2376 if(set->bo)
2377 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2378 }
2379
2380 void radv_CmdBindDescriptorSets(
2381 VkCommandBuffer commandBuffer,
2382 VkPipelineBindPoint pipelineBindPoint,
2383 VkPipelineLayout _layout,
2384 uint32_t firstSet,
2385 uint32_t descriptorSetCount,
2386 const VkDescriptorSet* pDescriptorSets,
2387 uint32_t dynamicOffsetCount,
2388 const uint32_t* pDynamicOffsets)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2392 unsigned dyn_idx = 0;
2393
2394 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2395 unsigned idx = i + firstSet;
2396 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2397 radv_bind_descriptor_set(cmd_buffer, set, idx);
2398
2399 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2400 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2401 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2402 assert(dyn_idx < dynamicOffsetCount);
2403
2404 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2405 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2406 dst[0] = va;
2407 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2408 dst[2] = range->size;
2409 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2410 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2411 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2412 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2413 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2414 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2415 cmd_buffer->push_constant_stages |=
2416 set->layout->dynamic_shader_stages;
2417 }
2418 }
2419 }
2420
2421 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2422 struct radv_descriptor_set *set,
2423 struct radv_descriptor_set_layout *layout)
2424 {
2425 set->size = layout->size;
2426 set->layout = layout;
2427
2428 if (cmd_buffer->push_descriptors.capacity < set->size) {
2429 size_t new_size = MAX2(set->size, 1024);
2430 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2431 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2432
2433 free(set->mapped_ptr);
2434 set->mapped_ptr = malloc(new_size);
2435
2436 if (!set->mapped_ptr) {
2437 cmd_buffer->push_descriptors.capacity = 0;
2438 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2439 return false;
2440 }
2441
2442 cmd_buffer->push_descriptors.capacity = new_size;
2443 }
2444
2445 return true;
2446 }
2447
2448 void radv_meta_push_descriptor_set(
2449 struct radv_cmd_buffer* cmd_buffer,
2450 VkPipelineBindPoint pipelineBindPoint,
2451 VkPipelineLayout _layout,
2452 uint32_t set,
2453 uint32_t descriptorWriteCount,
2454 const VkWriteDescriptorSet* pDescriptorWrites)
2455 {
2456 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2457 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2458 unsigned bo_offset;
2459
2460 assert(set == 0);
2461 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2462
2463 push_set->size = layout->set[set].layout->size;
2464 push_set->layout = layout->set[set].layout;
2465
2466 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2467 &bo_offset,
2468 (void**) &push_set->mapped_ptr))
2469 return;
2470
2471 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2472 push_set->va += bo_offset;
2473
2474 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2475 radv_descriptor_set_to_handle(push_set),
2476 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2477
2478 radv_set_descriptor_set(cmd_buffer, push_set, set);
2479 }
2480
2481 void radv_CmdPushDescriptorSetKHR(
2482 VkCommandBuffer commandBuffer,
2483 VkPipelineBindPoint pipelineBindPoint,
2484 VkPipelineLayout _layout,
2485 uint32_t set,
2486 uint32_t descriptorWriteCount,
2487 const VkWriteDescriptorSet* pDescriptorWrites)
2488 {
2489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2490 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2491 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2492
2493 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2494
2495 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2496 return;
2497
2498 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2499 radv_descriptor_set_to_handle(push_set),
2500 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2501
2502 radv_set_descriptor_set(cmd_buffer, push_set, set);
2503 cmd_buffer->state.push_descriptors_dirty = true;
2504 }
2505
2506 void radv_CmdPushDescriptorSetWithTemplateKHR(
2507 VkCommandBuffer commandBuffer,
2508 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2509 VkPipelineLayout _layout,
2510 uint32_t set,
2511 const void* pData)
2512 {
2513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2514 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2515 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2516
2517 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2518
2519 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2520 return;
2521
2522 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2523 descriptorUpdateTemplate, pData);
2524
2525 radv_set_descriptor_set(cmd_buffer, push_set, set);
2526 cmd_buffer->state.push_descriptors_dirty = true;
2527 }
2528
2529 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2530 VkPipelineLayout layout,
2531 VkShaderStageFlags stageFlags,
2532 uint32_t offset,
2533 uint32_t size,
2534 const void* pValues)
2535 {
2536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2537 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2538 cmd_buffer->push_constant_stages |= stageFlags;
2539 }
2540
2541 VkResult radv_EndCommandBuffer(
2542 VkCommandBuffer commandBuffer)
2543 {
2544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2545
2546 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2547 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2548 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2549 si_emit_cache_flush(cmd_buffer);
2550 }
2551
2552 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2553
2554 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2555 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2556
2557 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2558
2559 return cmd_buffer->record_result;
2560 }
2561
2562 static void
2563 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2564 {
2565 struct radv_shader_variant *compute_shader;
2566 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2567 uint64_t va;
2568
2569 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2570 return;
2571
2572 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2573
2574 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2575 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2576
2577 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2578 cmd_buffer->cs, 16);
2579
2580 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2581 radeon_emit(cmd_buffer->cs, va >> 8);
2582 radeon_emit(cmd_buffer->cs, va >> 40);
2583
2584 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2585 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2586 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2587
2588
2589 cmd_buffer->compute_scratch_size_needed =
2590 MAX2(cmd_buffer->compute_scratch_size_needed,
2591 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2592
2593 /* change these once we have scratch support */
2594 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2595 S_00B860_WAVES(pipeline->max_waves) |
2596 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2597
2598 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2599 radeon_emit(cmd_buffer->cs,
2600 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2601 radeon_emit(cmd_buffer->cs,
2602 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2603 radeon_emit(cmd_buffer->cs,
2604 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2605
2606 assert(cmd_buffer->cs->cdw <= cdw_max);
2607
2608 if (unlikely(cmd_buffer->device->trace_bo))
2609 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2610 }
2611
2612 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2613 {
2614 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2615 }
2616
2617 void radv_CmdBindPipeline(
2618 VkCommandBuffer commandBuffer,
2619 VkPipelineBindPoint pipelineBindPoint,
2620 VkPipeline _pipeline)
2621 {
2622 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2623 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2624
2625 switch (pipelineBindPoint) {
2626 case VK_PIPELINE_BIND_POINT_COMPUTE:
2627 if (cmd_buffer->state.compute_pipeline == pipeline)
2628 return;
2629 radv_mark_descriptor_sets_dirty(cmd_buffer);
2630
2631 cmd_buffer->state.compute_pipeline = pipeline;
2632 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2633 break;
2634 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2635 if (cmd_buffer->state.pipeline == pipeline)
2636 return;
2637 radv_mark_descriptor_sets_dirty(cmd_buffer);
2638
2639 cmd_buffer->state.pipeline = pipeline;
2640 if (!pipeline)
2641 break;
2642
2643 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2644 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2645
2646 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2647
2648 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2649 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2650 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2651 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2652
2653 if (radv_pipeline_has_tess(pipeline))
2654 cmd_buffer->tess_rings_needed = true;
2655
2656 if (radv_pipeline_has_gs(pipeline)) {
2657 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2658 AC_UD_SCRATCH_RING_OFFSETS);
2659 if (cmd_buffer->ring_offsets_idx == -1)
2660 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2661 else if (loc->sgpr_idx != -1)
2662 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2663 }
2664 break;
2665 default:
2666 assert(!"invalid bind point");
2667 break;
2668 }
2669 }
2670
2671 void radv_CmdSetViewport(
2672 VkCommandBuffer commandBuffer,
2673 uint32_t firstViewport,
2674 uint32_t viewportCount,
2675 const VkViewport* pViewports)
2676 {
2677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2678 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2679
2680 assert(firstViewport < MAX_VIEWPORTS);
2681 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2682
2683 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2684 pViewports, viewportCount * sizeof(*pViewports));
2685
2686 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2687 }
2688
2689 void radv_CmdSetScissor(
2690 VkCommandBuffer commandBuffer,
2691 uint32_t firstScissor,
2692 uint32_t scissorCount,
2693 const VkRect2D* pScissors)
2694 {
2695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2696 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2697
2698 assert(firstScissor < MAX_SCISSORS);
2699 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2700
2701 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2702 pScissors, scissorCount * sizeof(*pScissors));
2703 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2704 }
2705
2706 void radv_CmdSetLineWidth(
2707 VkCommandBuffer commandBuffer,
2708 float lineWidth)
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711 cmd_buffer->state.dynamic.line_width = lineWidth;
2712 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2713 }
2714
2715 void radv_CmdSetDepthBias(
2716 VkCommandBuffer commandBuffer,
2717 float depthBiasConstantFactor,
2718 float depthBiasClamp,
2719 float depthBiasSlopeFactor)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722
2723 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2724 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2725 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2726
2727 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2728 }
2729
2730 void radv_CmdSetBlendConstants(
2731 VkCommandBuffer commandBuffer,
2732 const float blendConstants[4])
2733 {
2734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2735
2736 memcpy(cmd_buffer->state.dynamic.blend_constants,
2737 blendConstants, sizeof(float) * 4);
2738
2739 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2740 }
2741
2742 void radv_CmdSetDepthBounds(
2743 VkCommandBuffer commandBuffer,
2744 float minDepthBounds,
2745 float maxDepthBounds)
2746 {
2747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2748
2749 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2750 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2751
2752 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2753 }
2754
2755 void radv_CmdSetStencilCompareMask(
2756 VkCommandBuffer commandBuffer,
2757 VkStencilFaceFlags faceMask,
2758 uint32_t compareMask)
2759 {
2760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2761
2762 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2763 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2764 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2765 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2766
2767 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2768 }
2769
2770 void radv_CmdSetStencilWriteMask(
2771 VkCommandBuffer commandBuffer,
2772 VkStencilFaceFlags faceMask,
2773 uint32_t writeMask)
2774 {
2775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2776
2777 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2778 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2779 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2780 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2781
2782 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2783 }
2784
2785 void radv_CmdSetStencilReference(
2786 VkCommandBuffer commandBuffer,
2787 VkStencilFaceFlags faceMask,
2788 uint32_t reference)
2789 {
2790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2791
2792 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2793 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2794 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2795 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2796
2797 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2798 }
2799
2800 void radv_CmdExecuteCommands(
2801 VkCommandBuffer commandBuffer,
2802 uint32_t commandBufferCount,
2803 const VkCommandBuffer* pCmdBuffers)
2804 {
2805 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2806
2807 assert(commandBufferCount > 0);
2808
2809 /* Emit pending flushes on primary prior to executing secondary */
2810 si_emit_cache_flush(primary);
2811
2812 for (uint32_t i = 0; i < commandBufferCount; i++) {
2813 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2814
2815 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2816 secondary->scratch_size_needed);
2817 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2818 secondary->compute_scratch_size_needed);
2819
2820 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2821 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2822 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2823 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2824 if (secondary->tess_rings_needed)
2825 primary->tess_rings_needed = true;
2826 if (secondary->sample_positions_needed)
2827 primary->sample_positions_needed = true;
2828
2829 if (secondary->ring_offsets_idx != -1) {
2830 if (primary->ring_offsets_idx == -1)
2831 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2832 else
2833 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2834 }
2835 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2836
2837
2838 /* When the secondary command buffer is compute only we don't
2839 * need to re-emit the current graphics pipeline.
2840 */
2841 if (secondary->state.emitted_pipeline) {
2842 primary->state.emitted_pipeline =
2843 secondary->state.emitted_pipeline;
2844 }
2845
2846 /* When the secondary command buffer is graphics only we don't
2847 * need to re-emit the current compute pipeline.
2848 */
2849 if (secondary->state.emitted_compute_pipeline) {
2850 primary->state.emitted_compute_pipeline =
2851 secondary->state.emitted_compute_pipeline;
2852 }
2853
2854 /* Only re-emit the draw packets when needed. */
2855 if (secondary->state.last_primitive_reset_en != -1) {
2856 primary->state.last_primitive_reset_en =
2857 secondary->state.last_primitive_reset_en;
2858 }
2859
2860 if (secondary->state.last_primitive_reset_index) {
2861 primary->state.last_primitive_reset_index =
2862 secondary->state.last_primitive_reset_index;
2863 }
2864
2865 if (secondary->state.last_ia_multi_vgt_param) {
2866 primary->state.last_ia_multi_vgt_param =
2867 secondary->state.last_ia_multi_vgt_param;
2868 }
2869
2870 if (secondary->state.last_index_type != -1) {
2871 primary->state.last_index_type =
2872 secondary->state.last_index_type;
2873 }
2874 }
2875
2876 /* After executing commands from secondary buffers we have to dirty
2877 * some states.
2878 */
2879 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2880 RADV_CMD_DIRTY_INDEX_BUFFER |
2881 RADV_CMD_DIRTY_DYNAMIC_ALL;
2882 radv_mark_descriptor_sets_dirty(primary);
2883 }
2884
2885 VkResult radv_CreateCommandPool(
2886 VkDevice _device,
2887 const VkCommandPoolCreateInfo* pCreateInfo,
2888 const VkAllocationCallbacks* pAllocator,
2889 VkCommandPool* pCmdPool)
2890 {
2891 RADV_FROM_HANDLE(radv_device, device, _device);
2892 struct radv_cmd_pool *pool;
2893
2894 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2895 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2896 if (pool == NULL)
2897 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2898
2899 if (pAllocator)
2900 pool->alloc = *pAllocator;
2901 else
2902 pool->alloc = device->alloc;
2903
2904 list_inithead(&pool->cmd_buffers);
2905 list_inithead(&pool->free_cmd_buffers);
2906
2907 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2908
2909 *pCmdPool = radv_cmd_pool_to_handle(pool);
2910
2911 return VK_SUCCESS;
2912
2913 }
2914
2915 void radv_DestroyCommandPool(
2916 VkDevice _device,
2917 VkCommandPool commandPool,
2918 const VkAllocationCallbacks* pAllocator)
2919 {
2920 RADV_FROM_HANDLE(radv_device, device, _device);
2921 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2922
2923 if (!pool)
2924 return;
2925
2926 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2927 &pool->cmd_buffers, pool_link) {
2928 radv_cmd_buffer_destroy(cmd_buffer);
2929 }
2930
2931 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2932 &pool->free_cmd_buffers, pool_link) {
2933 radv_cmd_buffer_destroy(cmd_buffer);
2934 }
2935
2936 vk_free2(&device->alloc, pAllocator, pool);
2937 }
2938
2939 VkResult radv_ResetCommandPool(
2940 VkDevice device,
2941 VkCommandPool commandPool,
2942 VkCommandPoolResetFlags flags)
2943 {
2944 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2945 VkResult result;
2946
2947 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2948 &pool->cmd_buffers, pool_link) {
2949 result = radv_reset_cmd_buffer(cmd_buffer);
2950 if (result != VK_SUCCESS)
2951 return result;
2952 }
2953
2954 return VK_SUCCESS;
2955 }
2956
2957 void radv_TrimCommandPoolKHR(
2958 VkDevice device,
2959 VkCommandPool commandPool,
2960 VkCommandPoolTrimFlagsKHR flags)
2961 {
2962 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2963
2964 if (!pool)
2965 return;
2966
2967 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2968 &pool->free_cmd_buffers, pool_link) {
2969 radv_cmd_buffer_destroy(cmd_buffer);
2970 }
2971 }
2972
2973 void radv_CmdBeginRenderPass(
2974 VkCommandBuffer commandBuffer,
2975 const VkRenderPassBeginInfo* pRenderPassBegin,
2976 VkSubpassContents contents)
2977 {
2978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2979 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2980 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2981
2982 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2983 cmd_buffer->cs, 2048);
2984 MAYBE_UNUSED VkResult result;
2985
2986 cmd_buffer->state.framebuffer = framebuffer;
2987 cmd_buffer->state.pass = pass;
2988 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2989
2990 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2991 if (result != VK_SUCCESS)
2992 return;
2993
2994 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2995 assert(cmd_buffer->cs->cdw <= cdw_max);
2996
2997 radv_cmd_buffer_clear_subpass(cmd_buffer);
2998 }
2999
3000 void radv_CmdNextSubpass(
3001 VkCommandBuffer commandBuffer,
3002 VkSubpassContents contents)
3003 {
3004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3005
3006 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3007
3008 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3009 2048);
3010
3011 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3012 radv_cmd_buffer_clear_subpass(cmd_buffer);
3013 }
3014
3015 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3016 {
3017 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3018 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3019 if (!pipeline->shaders[stage])
3020 continue;
3021 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3022 if (loc->sgpr_idx == -1)
3023 continue;
3024 uint32_t base_reg = pipeline->user_data_0[stage];
3025 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3026
3027 }
3028 if (pipeline->gs_copy_shader) {
3029 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3030 if (loc->sgpr_idx != -1) {
3031 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3032 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3033 }
3034 }
3035 }
3036
3037 static void
3038 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3039 uint32_t vertex_count)
3040 {
3041 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3042 radeon_emit(cmd_buffer->cs, vertex_count);
3043 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3044 S_0287F0_USE_OPAQUE(0));
3045 }
3046
3047 static void
3048 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3049 uint64_t index_va,
3050 uint32_t index_count)
3051 {
3052 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3053 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3054 radeon_emit(cmd_buffer->cs, index_va);
3055 radeon_emit(cmd_buffer->cs, index_va >> 32);
3056 radeon_emit(cmd_buffer->cs, index_count);
3057 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3058 }
3059
3060 static void
3061 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3062 bool indexed,
3063 uint32_t draw_count,
3064 uint64_t count_va,
3065 uint32_t stride)
3066 {
3067 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3068 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3069 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3070 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3071 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3072 assert(base_reg);
3073
3074 if (draw_count == 1 && !count_va && !draw_id_enable) {
3075 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3076 PKT3_DRAW_INDIRECT, 3, false));
3077 radeon_emit(cs, 0);
3078 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3079 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3080 radeon_emit(cs, di_src_sel);
3081 } else {
3082 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3083 PKT3_DRAW_INDIRECT_MULTI,
3084 8, false));
3085 radeon_emit(cs, 0);
3086 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3087 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3088 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3089 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3090 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3091 radeon_emit(cs, draw_count); /* count */
3092 radeon_emit(cs, count_va); /* count_addr */
3093 radeon_emit(cs, count_va >> 32);
3094 radeon_emit(cs, stride); /* stride */
3095 radeon_emit(cs, di_src_sel);
3096 }
3097 }
3098
3099 struct radv_draw_info {
3100 /**
3101 * Number of vertices.
3102 */
3103 uint32_t count;
3104
3105 /**
3106 * Index of the first vertex.
3107 */
3108 int32_t vertex_offset;
3109
3110 /**
3111 * First instance id.
3112 */
3113 uint32_t first_instance;
3114
3115 /**
3116 * Number of instances.
3117 */
3118 uint32_t instance_count;
3119
3120 /**
3121 * First index (indexed draws only).
3122 */
3123 uint32_t first_index;
3124
3125 /**
3126 * Whether it's an indexed draw.
3127 */
3128 bool indexed;
3129
3130 /**
3131 * Indirect draw parameters resource.
3132 */
3133 struct radv_buffer *indirect;
3134 uint64_t indirect_offset;
3135 uint32_t stride;
3136
3137 /**
3138 * Draw count parameters resource.
3139 */
3140 struct radv_buffer *count_buffer;
3141 uint64_t count_buffer_offset;
3142 };
3143
3144 static void
3145 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3146 const struct radv_draw_info *info)
3147 {
3148 struct radv_cmd_state *state = &cmd_buffer->state;
3149 struct radeon_winsys *ws = cmd_buffer->device->ws;
3150 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3151
3152 if (info->indirect) {
3153 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3154 uint64_t count_va = 0;
3155
3156 va += info->indirect->offset + info->indirect_offset;
3157
3158 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3159
3160 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3161 radeon_emit(cs, 1);
3162 radeon_emit(cs, va);
3163 radeon_emit(cs, va >> 32);
3164
3165 if (info->count_buffer) {
3166 count_va = radv_buffer_get_va(info->count_buffer->bo);
3167 count_va += info->count_buffer->offset +
3168 info->count_buffer_offset;
3169
3170 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3171 }
3172
3173 if (!state->subpass->view_mask) {
3174 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3175 info->indexed,
3176 info->count,
3177 count_va,
3178 info->stride);
3179 } else {
3180 unsigned i;
3181 for_each_bit(i, state->subpass->view_mask) {
3182 radv_emit_view_index(cmd_buffer, i);
3183
3184 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3185 info->indexed,
3186 info->count,
3187 count_va,
3188 info->stride);
3189 }
3190 }
3191 } else {
3192 assert(state->pipeline->graphics.vtx_base_sgpr);
3193 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3194 state->pipeline->graphics.vtx_emit_num);
3195 radeon_emit(cs, info->vertex_offset);
3196 radeon_emit(cs, info->first_instance);
3197 if (state->pipeline->graphics.vtx_emit_num == 3)
3198 radeon_emit(cs, 0);
3199
3200 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3201 radeon_emit(cs, info->instance_count);
3202
3203 if (info->indexed) {
3204 int index_size = state->index_type ? 4 : 2;
3205 uint64_t index_va;
3206
3207 index_va = state->index_va;
3208 index_va += info->first_index * index_size;
3209
3210 if (!state->subpass->view_mask) {
3211 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3212 index_va,
3213 info->count);
3214 } else {
3215 unsigned i;
3216 for_each_bit(i, state->subpass->view_mask) {
3217 radv_emit_view_index(cmd_buffer, i);
3218
3219 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3220 index_va,
3221 info->count);
3222 }
3223 }
3224 } else {
3225 if (!state->subpass->view_mask) {
3226 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3227 } else {
3228 unsigned i;
3229 for_each_bit(i, state->subpass->view_mask) {
3230 radv_emit_view_index(cmd_buffer, i);
3231
3232 radv_cs_emit_draw_packet(cmd_buffer,
3233 info->count);
3234 }
3235 }
3236 }
3237 }
3238 }
3239
3240 static void
3241 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3242 const struct radv_draw_info *info)
3243 {
3244 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3245 radv_emit_graphics_pipeline(cmd_buffer);
3246
3247 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3248 radv_emit_framebuffer_state(cmd_buffer);
3249
3250 if (info->indexed) {
3251 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3252 radv_emit_index_buffer(cmd_buffer);
3253 } else {
3254 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3255 * so the state must be re-emitted before the next indexed
3256 * draw.
3257 */
3258 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3259 cmd_buffer->state.last_index_type = -1;
3260 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3261 }
3262 }
3263
3264 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3265
3266 radv_emit_draw_registers(cmd_buffer, info->indexed,
3267 info->instance_count > 1, info->indirect,
3268 info->indirect ? 0 : info->count);
3269 }
3270
3271 static void
3272 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3273 const struct radv_draw_info *info)
3274 {
3275 bool pipeline_is_dirty =
3276 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3277 cmd_buffer->state.pipeline &&
3278 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3279
3280 MAYBE_UNUSED unsigned cdw_max =
3281 radeon_check_space(cmd_buffer->device->ws,
3282 cmd_buffer->cs, 4096);
3283
3284 /* Use optimal packet order based on whether we need to sync the
3285 * pipeline.
3286 */
3287 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3288 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3289 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3290 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3291 /* If we have to wait for idle, set all states first, so that
3292 * all SET packets are processed in parallel with previous draw
3293 * calls. Then upload descriptors, set shader pointers, and
3294 * draw, and prefetch at the end. This ensures that the time
3295 * the CUs are idle is very short. (there are only SET_SH
3296 * packets between the wait and the draw)
3297 */
3298 radv_emit_all_graphics_states(cmd_buffer, info);
3299 si_emit_cache_flush(cmd_buffer);
3300 /* <-- CUs are idle here --> */
3301
3302 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3303 return;
3304
3305 radv_emit_draw_packets(cmd_buffer, info);
3306 /* <-- CUs are busy here --> */
3307
3308 /* Start prefetches after the draw has been started. Both will
3309 * run in parallel, but starting the draw first is more
3310 * important.
3311 */
3312 if (pipeline_is_dirty) {
3313 radv_emit_prefetch(cmd_buffer,
3314 cmd_buffer->state.pipeline);
3315 }
3316 } else {
3317 /* If we don't wait for idle, start prefetches first, then set
3318 * states, and draw at the end.
3319 */
3320 si_emit_cache_flush(cmd_buffer);
3321
3322 if (pipeline_is_dirty) {
3323 radv_emit_prefetch(cmd_buffer,
3324 cmd_buffer->state.pipeline);
3325 }
3326
3327 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3328 return;
3329
3330 radv_emit_all_graphics_states(cmd_buffer, info);
3331 radv_emit_draw_packets(cmd_buffer, info);
3332 }
3333
3334 assert(cmd_buffer->cs->cdw <= cdw_max);
3335 radv_cmd_buffer_after_draw(cmd_buffer);
3336 }
3337
3338 void radv_CmdDraw(
3339 VkCommandBuffer commandBuffer,
3340 uint32_t vertexCount,
3341 uint32_t instanceCount,
3342 uint32_t firstVertex,
3343 uint32_t firstInstance)
3344 {
3345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3346 struct radv_draw_info info = {};
3347
3348 info.count = vertexCount;
3349 info.instance_count = instanceCount;
3350 info.first_instance = firstInstance;
3351 info.vertex_offset = firstVertex;
3352
3353 radv_draw(cmd_buffer, &info);
3354 }
3355
3356 void radv_CmdDrawIndexed(
3357 VkCommandBuffer commandBuffer,
3358 uint32_t indexCount,
3359 uint32_t instanceCount,
3360 uint32_t firstIndex,
3361 int32_t vertexOffset,
3362 uint32_t firstInstance)
3363 {
3364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3365 struct radv_draw_info info = {};
3366
3367 info.indexed = true;
3368 info.count = indexCount;
3369 info.instance_count = instanceCount;
3370 info.first_index = firstIndex;
3371 info.vertex_offset = vertexOffset;
3372 info.first_instance = firstInstance;
3373
3374 radv_draw(cmd_buffer, &info);
3375 }
3376
3377 void radv_CmdDrawIndirect(
3378 VkCommandBuffer commandBuffer,
3379 VkBuffer _buffer,
3380 VkDeviceSize offset,
3381 uint32_t drawCount,
3382 uint32_t stride)
3383 {
3384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3385 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3386 struct radv_draw_info info = {};
3387
3388 info.count = drawCount;
3389 info.indirect = buffer;
3390 info.indirect_offset = offset;
3391 info.stride = stride;
3392
3393 radv_draw(cmd_buffer, &info);
3394 }
3395
3396 void radv_CmdDrawIndexedIndirect(
3397 VkCommandBuffer commandBuffer,
3398 VkBuffer _buffer,
3399 VkDeviceSize offset,
3400 uint32_t drawCount,
3401 uint32_t stride)
3402 {
3403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3404 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3405 struct radv_draw_info info = {};
3406
3407 info.indexed = true;
3408 info.count = drawCount;
3409 info.indirect = buffer;
3410 info.indirect_offset = offset;
3411 info.stride = stride;
3412
3413 radv_draw(cmd_buffer, &info);
3414 }
3415
3416 void radv_CmdDrawIndirectCountAMD(
3417 VkCommandBuffer commandBuffer,
3418 VkBuffer _buffer,
3419 VkDeviceSize offset,
3420 VkBuffer _countBuffer,
3421 VkDeviceSize countBufferOffset,
3422 uint32_t maxDrawCount,
3423 uint32_t stride)
3424 {
3425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3426 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3427 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3428 struct radv_draw_info info = {};
3429
3430 info.count = maxDrawCount;
3431 info.indirect = buffer;
3432 info.indirect_offset = offset;
3433 info.count_buffer = count_buffer;
3434 info.count_buffer_offset = countBufferOffset;
3435 info.stride = stride;
3436
3437 radv_draw(cmd_buffer, &info);
3438 }
3439
3440 void radv_CmdDrawIndexedIndirectCountAMD(
3441 VkCommandBuffer commandBuffer,
3442 VkBuffer _buffer,
3443 VkDeviceSize offset,
3444 VkBuffer _countBuffer,
3445 VkDeviceSize countBufferOffset,
3446 uint32_t maxDrawCount,
3447 uint32_t stride)
3448 {
3449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3450 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3451 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3452 struct radv_draw_info info = {};
3453
3454 info.indexed = true;
3455 info.count = maxDrawCount;
3456 info.indirect = buffer;
3457 info.indirect_offset = offset;
3458 info.count_buffer = count_buffer;
3459 info.count_buffer_offset = countBufferOffset;
3460 info.stride = stride;
3461
3462 radv_draw(cmd_buffer, &info);
3463 }
3464
3465 struct radv_dispatch_info {
3466 /**
3467 * Determine the layout of the grid (in block units) to be used.
3468 */
3469 uint32_t blocks[3];
3470
3471 /**
3472 * Whether it's an unaligned compute dispatch.
3473 */
3474 bool unaligned;
3475
3476 /**
3477 * Indirect compute parameters resource.
3478 */
3479 struct radv_buffer *indirect;
3480 uint64_t indirect_offset;
3481 };
3482
3483 static void
3484 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3485 const struct radv_dispatch_info *info)
3486 {
3487 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3488 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3489 struct radeon_winsys *ws = cmd_buffer->device->ws;
3490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3491 struct ac_userdata_info *loc;
3492 unsigned dispatch_initiator;
3493 uint8_t grid_used;
3494
3495 grid_used = compute_shader->info.info.cs.grid_components_used;
3496
3497 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3498 AC_UD_CS_GRID_SIZE);
3499
3500 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3501
3502 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3503 S_00B800_FORCE_START_AT_000(1);
3504
3505 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3506 /* If the KMD allows it (there is a KMD hw register for it),
3507 * allow launching waves out-of-order.
3508 */
3509 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3510 }
3511
3512 if (info->indirect) {
3513 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3514
3515 va += info->indirect->offset + info->indirect_offset;
3516
3517 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3518
3519 if (loc->sgpr_idx != -1) {
3520 for (unsigned i = 0; i < grid_used; ++i) {
3521 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3522 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3523 COPY_DATA_DST_SEL(COPY_DATA_REG));
3524 radeon_emit(cs, (va + 4 * i));
3525 radeon_emit(cs, (va + 4 * i) >> 32);
3526 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3527 + loc->sgpr_idx * 4) >> 2) + i);
3528 radeon_emit(cs, 0);
3529 }
3530 }
3531
3532 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3533 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3534 PKT3_SHADER_TYPE_S(1));
3535 radeon_emit(cs, va);
3536 radeon_emit(cs, va >> 32);
3537 radeon_emit(cs, dispatch_initiator);
3538 } else {
3539 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3540 PKT3_SHADER_TYPE_S(1));
3541 radeon_emit(cs, 1);
3542 radeon_emit(cs, va);
3543 radeon_emit(cs, va >> 32);
3544
3545 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3546 PKT3_SHADER_TYPE_S(1));
3547 radeon_emit(cs, 0);
3548 radeon_emit(cs, dispatch_initiator);
3549 }
3550 } else {
3551 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3552
3553 if (info->unaligned) {
3554 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3555 unsigned remainder[3];
3556
3557 /* If aligned, these should be an entire block size,
3558 * not 0.
3559 */
3560 remainder[0] = blocks[0] + cs_block_size[0] -
3561 align_u32_npot(blocks[0], cs_block_size[0]);
3562 remainder[1] = blocks[1] + cs_block_size[1] -
3563 align_u32_npot(blocks[1], cs_block_size[1]);
3564 remainder[2] = blocks[2] + cs_block_size[2] -
3565 align_u32_npot(blocks[2], cs_block_size[2]);
3566
3567 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3568 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3569 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3570
3571 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3572 radeon_emit(cs,
3573 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3574 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3575 radeon_emit(cs,
3576 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3577 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3578 radeon_emit(cs,
3579 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3580 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3581
3582 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3583 }
3584
3585 if (loc->sgpr_idx != -1) {
3586 assert(!loc->indirect);
3587 assert(loc->num_sgprs == grid_used);
3588
3589 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3590 loc->sgpr_idx * 4, grid_used);
3591 radeon_emit(cs, blocks[0]);
3592 if (grid_used > 1)
3593 radeon_emit(cs, blocks[1]);
3594 if (grid_used > 2)
3595 radeon_emit(cs, blocks[2]);
3596 }
3597
3598 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3599 PKT3_SHADER_TYPE_S(1));
3600 radeon_emit(cs, blocks[0]);
3601 radeon_emit(cs, blocks[1]);
3602 radeon_emit(cs, blocks[2]);
3603 radeon_emit(cs, dispatch_initiator);
3604 }
3605
3606 assert(cmd_buffer->cs->cdw <= cdw_max);
3607 }
3608
3609 static void
3610 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3611 {
3612 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3613 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3614 VK_SHADER_STAGE_COMPUTE_BIT);
3615 }
3616
3617 static void
3618 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3619 const struct radv_dispatch_info *info)
3620 {
3621 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3622 bool pipeline_is_dirty = pipeline &&
3623 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3624
3625 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3626 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3627 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3628 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3629 /* If we have to wait for idle, set all states first, so that
3630 * all SET packets are processed in parallel with previous draw
3631 * calls. Then upload descriptors, set shader pointers, and
3632 * dispatch, and prefetch at the end. This ensures that the
3633 * time the CUs are idle is very short. (there are only SET_SH
3634 * packets between the wait and the draw)
3635 */
3636 radv_emit_compute_pipeline(cmd_buffer);
3637 si_emit_cache_flush(cmd_buffer);
3638 /* <-- CUs are idle here --> */
3639
3640 radv_upload_compute_shader_descriptors(cmd_buffer);
3641
3642 radv_emit_dispatch_packets(cmd_buffer, info);
3643 /* <-- CUs are busy here --> */
3644
3645 /* Start prefetches after the dispatch has been started. Both
3646 * will run in parallel, but starting the dispatch first is
3647 * more important.
3648 */
3649 if (pipeline_is_dirty) {
3650 radv_emit_shader_prefetch(cmd_buffer,
3651 pipeline->shaders[MESA_SHADER_COMPUTE]);
3652 }
3653 } else {
3654 /* If we don't wait for idle, start prefetches first, then set
3655 * states, and dispatch at the end.
3656 */
3657 si_emit_cache_flush(cmd_buffer);
3658
3659 if (pipeline_is_dirty) {
3660 radv_emit_shader_prefetch(cmd_buffer,
3661 pipeline->shaders[MESA_SHADER_COMPUTE]);
3662 }
3663
3664 radv_upload_compute_shader_descriptors(cmd_buffer);
3665
3666 radv_emit_compute_pipeline(cmd_buffer);
3667 radv_emit_dispatch_packets(cmd_buffer, info);
3668 }
3669
3670 radv_cmd_buffer_after_draw(cmd_buffer);
3671 }
3672
3673 void radv_CmdDispatch(
3674 VkCommandBuffer commandBuffer,
3675 uint32_t x,
3676 uint32_t y,
3677 uint32_t z)
3678 {
3679 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3680 struct radv_dispatch_info info = {};
3681
3682 info.blocks[0] = x;
3683 info.blocks[1] = y;
3684 info.blocks[2] = z;
3685
3686 radv_dispatch(cmd_buffer, &info);
3687 }
3688
3689 void radv_CmdDispatchIndirect(
3690 VkCommandBuffer commandBuffer,
3691 VkBuffer _buffer,
3692 VkDeviceSize offset)
3693 {
3694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3695 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3696 struct radv_dispatch_info info = {};
3697
3698 info.indirect = buffer;
3699 info.indirect_offset = offset;
3700
3701 radv_dispatch(cmd_buffer, &info);
3702 }
3703
3704 void radv_unaligned_dispatch(
3705 struct radv_cmd_buffer *cmd_buffer,
3706 uint32_t x,
3707 uint32_t y,
3708 uint32_t z)
3709 {
3710 struct radv_dispatch_info info = {};
3711
3712 info.blocks[0] = x;
3713 info.blocks[1] = y;
3714 info.blocks[2] = z;
3715 info.unaligned = 1;
3716
3717 radv_dispatch(cmd_buffer, &info);
3718 }
3719
3720 void radv_CmdEndRenderPass(
3721 VkCommandBuffer commandBuffer)
3722 {
3723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3724
3725 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3726
3727 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3728
3729 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3730 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3731 radv_handle_subpass_image_transition(cmd_buffer,
3732 (VkAttachmentReference){i, layout});
3733 }
3734
3735 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3736
3737 cmd_buffer->state.pass = NULL;
3738 cmd_buffer->state.subpass = NULL;
3739 cmd_buffer->state.attachments = NULL;
3740 cmd_buffer->state.framebuffer = NULL;
3741 }
3742
3743 /*
3744 * For HTILE we have the following interesting clear words:
3745 * 0x0000030f: Uncompressed.
3746 * 0xfffffff0: Clear depth to 1.0
3747 * 0x00000000: Clear depth to 0.0
3748 */
3749 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3750 struct radv_image *image,
3751 const VkImageSubresourceRange *range,
3752 uint32_t clear_word)
3753 {
3754 assert(range->baseMipLevel == 0);
3755 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3756 unsigned layer_count = radv_get_layerCount(image, range);
3757 uint64_t size = image->surface.htile_slice_size * layer_count;
3758 uint64_t offset = image->offset + image->htile_offset +
3759 image->surface.htile_slice_size * range->baseArrayLayer;
3760 struct radv_cmd_state *state = &cmd_buffer->state;
3761
3762 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3763 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3764
3765 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3766 size, clear_word);
3767
3768 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3769 }
3770
3771 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3772 struct radv_image *image,
3773 VkImageLayout src_layout,
3774 VkImageLayout dst_layout,
3775 unsigned src_queue_mask,
3776 unsigned dst_queue_mask,
3777 const VkImageSubresourceRange *range,
3778 VkImageAspectFlags pending_clears)
3779 {
3780 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3781 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3782 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3783 cmd_buffer->state.render_area.extent.width == image->info.width &&
3784 cmd_buffer->state.render_area.extent.height == image->info.height) {
3785 /* The clear will initialize htile. */
3786 return;
3787 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3788 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3789 /* TODO: merge with the clear if applicable */
3790 radv_initialize_htile(cmd_buffer, image, range, 0);
3791 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3792 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3793 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3794 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3795 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3796 VkImageSubresourceRange local_range = *range;
3797 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3798 local_range.baseMipLevel = 0;
3799 local_range.levelCount = 1;
3800
3801 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3802 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3803
3804 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3805
3806 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3807 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3808 }
3809 }
3810
3811 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3812 struct radv_image *image, uint32_t value)
3813 {
3814 struct radv_cmd_state *state = &cmd_buffer->state;
3815
3816 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3817 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3818
3819 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3820 image->offset + image->cmask.offset,
3821 image->cmask.size, value);
3822
3823 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3824 }
3825
3826 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3827 struct radv_image *image,
3828 VkImageLayout src_layout,
3829 VkImageLayout dst_layout,
3830 unsigned src_queue_mask,
3831 unsigned dst_queue_mask,
3832 const VkImageSubresourceRange *range)
3833 {
3834 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3835 if (image->fmask.size)
3836 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3837 else
3838 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3839 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3840 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3841 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3842 }
3843 }
3844
3845 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3846 struct radv_image *image, uint32_t value)
3847 {
3848 struct radv_cmd_state *state = &cmd_buffer->state;
3849
3850 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3851 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3852
3853 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3854 image->offset + image->dcc_offset,
3855 image->surface.dcc_size, value);
3856
3857 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3858 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3859 }
3860
3861 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3862 struct radv_image *image,
3863 VkImageLayout src_layout,
3864 VkImageLayout dst_layout,
3865 unsigned src_queue_mask,
3866 unsigned dst_queue_mask,
3867 const VkImageSubresourceRange *range)
3868 {
3869 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3870 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3871 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3872 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3873 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3874 }
3875 }
3876
3877 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3878 struct radv_image *image,
3879 VkImageLayout src_layout,
3880 VkImageLayout dst_layout,
3881 uint32_t src_family,
3882 uint32_t dst_family,
3883 const VkImageSubresourceRange *range,
3884 VkImageAspectFlags pending_clears)
3885 {
3886 if (image->exclusive && src_family != dst_family) {
3887 /* This is an acquire or a release operation and there will be
3888 * a corresponding release/acquire. Do the transition in the
3889 * most flexible queue. */
3890
3891 assert(src_family == cmd_buffer->queue_family_index ||
3892 dst_family == cmd_buffer->queue_family_index);
3893
3894 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3895 return;
3896
3897 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3898 (src_family == RADV_QUEUE_GENERAL ||
3899 dst_family == RADV_QUEUE_GENERAL))
3900 return;
3901 }
3902
3903 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3904 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3905
3906 if (image->surface.htile_size)
3907 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3908 dst_layout, src_queue_mask,
3909 dst_queue_mask, range,
3910 pending_clears);
3911
3912 if (image->cmask.size || image->fmask.size)
3913 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3914 dst_layout, src_queue_mask,
3915 dst_queue_mask, range);
3916
3917 if (image->surface.dcc_size)
3918 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3919 dst_layout, src_queue_mask,
3920 dst_queue_mask, range);
3921 }
3922
3923 void radv_CmdPipelineBarrier(
3924 VkCommandBuffer commandBuffer,
3925 VkPipelineStageFlags srcStageMask,
3926 VkPipelineStageFlags destStageMask,
3927 VkBool32 byRegion,
3928 uint32_t memoryBarrierCount,
3929 const VkMemoryBarrier* pMemoryBarriers,
3930 uint32_t bufferMemoryBarrierCount,
3931 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3932 uint32_t imageMemoryBarrierCount,
3933 const VkImageMemoryBarrier* pImageMemoryBarriers)
3934 {
3935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3936 enum radv_cmd_flush_bits src_flush_bits = 0;
3937 enum radv_cmd_flush_bits dst_flush_bits = 0;
3938
3939 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3940 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3941 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3942 NULL);
3943 }
3944
3945 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3946 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3947 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3948 NULL);
3949 }
3950
3951 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3952 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3953 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3954 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3955 image);
3956 }
3957
3958 radv_stage_flush(cmd_buffer, srcStageMask);
3959 cmd_buffer->state.flush_bits |= src_flush_bits;
3960
3961 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3962 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3963 radv_handle_image_transition(cmd_buffer, image,
3964 pImageMemoryBarriers[i].oldLayout,
3965 pImageMemoryBarriers[i].newLayout,
3966 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3967 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3968 &pImageMemoryBarriers[i].subresourceRange,
3969 0);
3970 }
3971
3972 cmd_buffer->state.flush_bits |= dst_flush_bits;
3973 }
3974
3975
3976 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3977 struct radv_event *event,
3978 VkPipelineStageFlags stageMask,
3979 unsigned value)
3980 {
3981 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3982 uint64_t va = radv_buffer_get_va(event->bo);
3983
3984 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3985
3986 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3987
3988 /* TODO: this is overkill. Probably should figure something out from
3989 * the stage mask. */
3990
3991 si_cs_emit_write_event_eop(cs,
3992 cmd_buffer->state.predicating,
3993 cmd_buffer->device->physical_device->rad_info.chip_class,
3994 false,
3995 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3996 1, va, 2, value);
3997
3998 assert(cmd_buffer->cs->cdw <= cdw_max);
3999 }
4000
4001 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4002 VkEvent _event,
4003 VkPipelineStageFlags stageMask)
4004 {
4005 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4006 RADV_FROM_HANDLE(radv_event, event, _event);
4007
4008 write_event(cmd_buffer, event, stageMask, 1);
4009 }
4010
4011 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4012 VkEvent _event,
4013 VkPipelineStageFlags stageMask)
4014 {
4015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4016 RADV_FROM_HANDLE(radv_event, event, _event);
4017
4018 write_event(cmd_buffer, event, stageMask, 0);
4019 }
4020
4021 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4022 uint32_t eventCount,
4023 const VkEvent* pEvents,
4024 VkPipelineStageFlags srcStageMask,
4025 VkPipelineStageFlags dstStageMask,
4026 uint32_t memoryBarrierCount,
4027 const VkMemoryBarrier* pMemoryBarriers,
4028 uint32_t bufferMemoryBarrierCount,
4029 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4030 uint32_t imageMemoryBarrierCount,
4031 const VkImageMemoryBarrier* pImageMemoryBarriers)
4032 {
4033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4034 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4035
4036 for (unsigned i = 0; i < eventCount; ++i) {
4037 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4038 uint64_t va = radv_buffer_get_va(event->bo);
4039
4040 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4041
4042 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4043
4044 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4045 assert(cmd_buffer->cs->cdw <= cdw_max);
4046 }
4047
4048
4049 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4050 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4051
4052 radv_handle_image_transition(cmd_buffer, image,
4053 pImageMemoryBarriers[i].oldLayout,
4054 pImageMemoryBarriers[i].newLayout,
4055 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4056 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4057 &pImageMemoryBarriers[i].subresourceRange,
4058 0);
4059 }
4060
4061 /* TODO: figure out how to do memory barriers without waiting */
4062 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4063 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4064 RADV_CMD_FLAG_INV_VMEM_L1 |
4065 RADV_CMD_FLAG_INV_SMEM_L1;
4066 }