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radv: add support for push constants inlining when possible
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
336 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned fence_offset, eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_va =
344 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
345 cmd_buffer->gfx9_fence_va += fence_offset;
346
347 /* Allocate a buffer for the EOP bug on GFX9. */
348 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
349 &eop_bug_offset, &fence_ptr);
350 cmd_buffer->gfx9_eop_bug_va =
351 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
352 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
353 }
354
355 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
356
357 return cmd_buffer->record_result;
358 }
359
360 static bool
361 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
362 uint64_t min_needed)
363 {
364 uint64_t new_size;
365 struct radeon_winsys_bo *bo;
366 struct radv_cmd_buffer_upload *upload;
367 struct radv_device *device = cmd_buffer->device;
368
369 new_size = MAX2(min_needed, 16 * 1024);
370 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
371
372 bo = device->ws->buffer_create(device->ws,
373 new_size, 4096,
374 RADEON_DOMAIN_GTT,
375 RADEON_FLAG_CPU_ACCESS|
376 RADEON_FLAG_NO_INTERPROCESS_SHARING |
377 RADEON_FLAG_32BIT,
378 RADV_BO_PRIORITY_UPLOAD_BUFFER);
379
380 if (!bo) {
381 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
382 return false;
383 }
384
385 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
386 if (cmd_buffer->upload.upload_bo) {
387 upload = malloc(sizeof(*upload));
388
389 if (!upload) {
390 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
391 device->ws->buffer_destroy(bo);
392 return false;
393 }
394
395 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
396 list_add(&upload->list, &cmd_buffer->upload.list);
397 }
398
399 cmd_buffer->upload.upload_bo = bo;
400 cmd_buffer->upload.size = new_size;
401 cmd_buffer->upload.offset = 0;
402 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
403
404 if (!cmd_buffer->upload.map) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 return true;
410 }
411
412 bool
413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
414 unsigned size,
415 unsigned alignment,
416 unsigned *out_offset,
417 void **ptr)
418 {
419 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
420 if (offset + size > cmd_buffer->upload.size) {
421 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
422 return false;
423 offset = 0;
424 }
425
426 *out_offset = offset;
427 *ptr = cmd_buffer->upload.map + offset;
428
429 cmd_buffer->upload.offset = offset + size;
430 return true;
431 }
432
433 bool
434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
435 unsigned size, unsigned alignment,
436 const void *data, unsigned *out_offset)
437 {
438 uint8_t *ptr;
439
440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
441 out_offset, (void **)&ptr))
442 return false;
443
444 if (ptr)
445 memcpy(ptr, data, size);
446
447 return true;
448 }
449
450 static void
451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
452 unsigned count, const uint32_t *data)
453 {
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455
456 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
457
458 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
459 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
460 S_370_WR_CONFIRM(1) |
461 S_370_ENGINE_SEL(V_370_ME));
462 radeon_emit(cs, va);
463 radeon_emit(cs, va >> 32);
464 radeon_emit_array(cs, data, count);
465 }
466
467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
468 {
469 struct radv_device *device = cmd_buffer->device;
470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
471 uint64_t va;
472
473 va = radv_buffer_get_va(device->trace_bo);
474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
475 va += 4;
476
477 ++cmd_buffer->state.trace_id;
478 radv_emit_write_data_packet(cmd_buffer, va, 1,
479 &cmd_buffer->state.trace_id);
480
481 radeon_check_space(cmd_buffer->device->ws, cs, 2);
482
483 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
484 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
485 }
486
487 static void
488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
489 enum radv_cmd_flush_bits flags)
490 {
491 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
496
497 /* Force wait for graphics or compute engines to be idle. */
498 si_cs_emit_cache_flush(cmd_buffer->cs,
499 cmd_buffer->device->physical_device->rad_info.chip_class,
500 &cmd_buffer->gfx9_fence_idx,
501 cmd_buffer->gfx9_fence_va,
502 radv_cmd_buffer_uses_mec(cmd_buffer),
503 flags, cmd_buffer->gfx9_eop_bug_va);
504 }
505
506 if (unlikely(cmd_buffer->device->trace_bo))
507 radv_cmd_buffer_trace_emit(cmd_buffer);
508 }
509
510 static void
511 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
512 struct radv_pipeline *pipeline, enum ring_type ring)
513 {
514 struct radv_device *device = cmd_buffer->device;
515 uint32_t data[2];
516 uint64_t va;
517
518 va = radv_buffer_get_va(device->trace_bo);
519
520 switch (ring) {
521 case RING_GFX:
522 va += 8;
523 break;
524 case RING_COMPUTE:
525 va += 16;
526 break;
527 default:
528 assert(!"invalid ring type");
529 }
530
531 data[0] = (uintptr_t)pipeline;
532 data[1] = (uintptr_t)pipeline >> 32;
533
534 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
535 }
536
537 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
538 VkPipelineBindPoint bind_point,
539 struct radv_descriptor_set *set,
540 unsigned idx)
541 {
542 struct radv_descriptor_state *descriptors_state =
543 radv_get_descriptors_state(cmd_buffer, bind_point);
544
545 descriptors_state->sets[idx] = set;
546
547 descriptors_state->valid |= (1u << idx); /* active descriptors */
548 descriptors_state->dirty |= (1u << idx);
549 }
550
551 static void
552 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
553 VkPipelineBindPoint bind_point)
554 {
555 struct radv_descriptor_state *descriptors_state =
556 radv_get_descriptors_state(cmd_buffer, bind_point);
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[MAX_SETS * 2] = {};
559 uint64_t va;
560 unsigned i;
561 va = radv_buffer_get_va(device->trace_bo) + 24;
562
563 for_each_bit(i, descriptors_state->valid) {
564 struct radv_descriptor_set *set = descriptors_state->sets[i];
565 data[i * 2] = (uintptr_t)set;
566 data[i * 2 + 1] = (uintptr_t)set >> 32;
567 }
568
569 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
570 }
571
572 struct radv_userdata_info *
573 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
574 gl_shader_stage stage,
575 int idx)
576 {
577 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
578 return &shader->info.user_sgprs_locs.shader_data[idx];
579 }
580
581 static void
582 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline,
584 gl_shader_stage stage,
585 int idx, uint64_t va)
586 {
587 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
588 uint32_t base_reg = pipeline->user_data_0[stage];
589 if (loc->sgpr_idx == -1)
590 return;
591
592 assert(loc->num_sgprs == 1);
593
594 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
595 base_reg + loc->sgpr_idx * 4, va, false);
596 }
597
598 static void
599 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
600 struct radv_pipeline *pipeline,
601 struct radv_descriptor_state *descriptors_state,
602 gl_shader_stage stage)
603 {
604 struct radv_device *device = cmd_buffer->device;
605 struct radeon_cmdbuf *cs = cmd_buffer->cs;
606 uint32_t sh_base = pipeline->user_data_0[stage];
607 struct radv_userdata_locations *locs =
608 &pipeline->shaders[stage]->info.user_sgprs_locs;
609 unsigned mask = locs->descriptor_sets_enabled;
610
611 mask &= descriptors_state->dirty & descriptors_state->valid;
612
613 while (mask) {
614 int start, count;
615
616 u_bit_scan_consecutive_range(&mask, &start, &count);
617
618 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
619 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
620
621 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
622 for (int i = 0; i < count; i++) {
623 struct radv_descriptor_set *set =
624 descriptors_state->sets[start + i];
625
626 radv_emit_shader_pointer_body(device, cs, set->va, true);
627 }
628 }
629 }
630
631 static void
632 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
633 struct radv_pipeline *pipeline,
634 gl_shader_stage stage,
635 int idx, int count, uint32_t *values)
636 {
637 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
638 uint32_t base_reg = pipeline->user_data_0[stage];
639 if (loc->sgpr_idx == -1)
640 return;
641
642 assert(loc->num_sgprs == count);
643
644 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
645 radeon_emit_array(cmd_buffer->cs, values, count);
646 }
647
648 static void
649 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
650 struct radv_pipeline *pipeline)
651 {
652 int num_samples = pipeline->graphics.ms.num_samples;
653 struct radv_multisample_state *ms = &pipeline->graphics.ms;
654 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
655
656 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
657 cmd_buffer->sample_positions_needed = true;
658
659 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
660 return;
661
662 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
663 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
664 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
665
666 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
667
668 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
669
670 /* GFX9: Flush DFSM when the AA mode changes. */
671 if (cmd_buffer->device->dfsm_allowed) {
672 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
673 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
674 }
675
676 cmd_buffer->state.context_roll_without_scissor_emitted = true;
677 }
678
679 static void
680 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
681 struct radv_shader_variant *shader)
682 {
683 uint64_t va;
684
685 if (!shader)
686 return;
687
688 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
689
690 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
691 }
692
693 static void
694 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
695 struct radv_pipeline *pipeline,
696 bool vertex_stage_only)
697 {
698 struct radv_cmd_state *state = &cmd_buffer->state;
699 uint32_t mask = state->prefetch_L2_mask;
700
701 if (vertex_stage_only) {
702 /* Fast prefetch path for starting draws as soon as possible.
703 */
704 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
705 RADV_PREFETCH_VBO_DESCRIPTORS);
706 }
707
708 if (mask & RADV_PREFETCH_VS)
709 radv_emit_shader_prefetch(cmd_buffer,
710 pipeline->shaders[MESA_SHADER_VERTEX]);
711
712 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
713 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
714
715 if (mask & RADV_PREFETCH_TCS)
716 radv_emit_shader_prefetch(cmd_buffer,
717 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
718
719 if (mask & RADV_PREFETCH_TES)
720 radv_emit_shader_prefetch(cmd_buffer,
721 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
722
723 if (mask & RADV_PREFETCH_GS) {
724 radv_emit_shader_prefetch(cmd_buffer,
725 pipeline->shaders[MESA_SHADER_GEOMETRY]);
726 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
727 }
728
729 if (mask & RADV_PREFETCH_PS)
730 radv_emit_shader_prefetch(cmd_buffer,
731 pipeline->shaders[MESA_SHADER_FRAGMENT]);
732
733 state->prefetch_L2_mask &= ~mask;
734 }
735
736 static void
737 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
738 {
739 if (!cmd_buffer->device->physical_device->rbplus_allowed)
740 return;
741
742 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
743 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
744 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
745
746 unsigned sx_ps_downconvert = 0;
747 unsigned sx_blend_opt_epsilon = 0;
748 unsigned sx_blend_opt_control = 0;
749
750 for (unsigned i = 0; i < subpass->color_count; ++i) {
751 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
752 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
753 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
754 continue;
755 }
756
757 int idx = subpass->color_attachments[i].attachment;
758 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
759
760 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
761 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
762 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
763 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
764
765 bool has_alpha, has_rgb;
766
767 /* Set if RGB and A are present. */
768 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
769
770 if (format == V_028C70_COLOR_8 ||
771 format == V_028C70_COLOR_16 ||
772 format == V_028C70_COLOR_32)
773 has_rgb = !has_alpha;
774 else
775 has_rgb = true;
776
777 /* Check the colormask and export format. */
778 if (!(colormask & 0x7))
779 has_rgb = false;
780 if (!(colormask & 0x8))
781 has_alpha = false;
782
783 if (spi_format == V_028714_SPI_SHADER_ZERO) {
784 has_rgb = false;
785 has_alpha = false;
786 }
787
788 /* Disable value checking for disabled channels. */
789 if (!has_rgb)
790 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
791 if (!has_alpha)
792 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
793
794 /* Enable down-conversion for 32bpp and smaller formats. */
795 switch (format) {
796 case V_028C70_COLOR_8:
797 case V_028C70_COLOR_8_8:
798 case V_028C70_COLOR_8_8_8_8:
799 /* For 1 and 2-channel formats, use the superset thereof. */
800 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
801 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
802 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
803 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
804 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
805 }
806 break;
807
808 case V_028C70_COLOR_5_6_5:
809 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
810 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
811 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
812 }
813 break;
814
815 case V_028C70_COLOR_1_5_5_5:
816 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
817 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
818 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
819 }
820 break;
821
822 case V_028C70_COLOR_4_4_4_4:
823 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
825 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
826 }
827 break;
828
829 case V_028C70_COLOR_32:
830 if (swap == V_028C70_SWAP_STD &&
831 spi_format == V_028714_SPI_SHADER_32_R)
832 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
833 else if (swap == V_028C70_SWAP_ALT_REV &&
834 spi_format == V_028714_SPI_SHADER_32_AR)
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
836 break;
837
838 case V_028C70_COLOR_16:
839 case V_028C70_COLOR_16_16:
840 /* For 1-channel formats, use the superset thereof. */
841 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
842 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
843 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
844 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
845 if (swap == V_028C70_SWAP_STD ||
846 swap == V_028C70_SWAP_STD_REV)
847 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
848 else
849 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
850 }
851 break;
852
853 case V_028C70_COLOR_10_11_11:
854 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
855 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
856 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
857 }
858 break;
859
860 case V_028C70_COLOR_2_10_10_10:
861 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
862 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
863 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
864 }
865 break;
866 }
867 }
868
869 for (unsigned i = subpass->color_count; i < 8; ++i) {
870 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
871 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
872 }
873 /* TODO: avoid redundantly setting context registers */
874 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
875 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
876 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
877 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
878
879 cmd_buffer->state.context_roll_without_scissor_emitted = true;
880 }
881
882 static void
883 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
884 {
885 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
886
887 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
888 return;
889
890 radv_update_multisample_state(cmd_buffer, pipeline);
891
892 cmd_buffer->scratch_size_needed =
893 MAX2(cmd_buffer->scratch_size_needed,
894 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
895
896 if (!cmd_buffer->state.emitted_pipeline ||
897 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
898 pipeline->graphics.can_use_guardband)
899 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
900
901 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
902
903 if (!cmd_buffer->state.emitted_pipeline ||
904 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
905 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
906 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
907 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
908 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
909 cmd_buffer->state.context_roll_without_scissor_emitted = true;
910 }
911
912 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
913 if (!pipeline->shaders[i])
914 continue;
915
916 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
917 pipeline->shaders[i]->bo);
918 }
919
920 if (radv_pipeline_has_gs(pipeline))
921 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
922 pipeline->gs_copy_shader->bo);
923
924 if (unlikely(cmd_buffer->device->trace_bo))
925 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
926
927 cmd_buffer->state.emitted_pipeline = pipeline;
928
929 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
930 }
931
932 static void
933 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
934 {
935 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
936 cmd_buffer->state.dynamic.viewport.viewports);
937 }
938
939 static void
940 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
941 {
942 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
943
944 si_write_scissors(cmd_buffer->cs, 0, count,
945 cmd_buffer->state.dynamic.scissor.scissors,
946 cmd_buffer->state.dynamic.viewport.viewports,
947 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
948
949 cmd_buffer->state.context_roll_without_scissor_emitted = false;
950 }
951
952 static void
953 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
954 {
955 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
956 return;
957
958 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
959 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
960 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
961 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
962 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
963 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
964 S_028214_BR_Y(rect.offset.y + rect.extent.height));
965 }
966 }
967
968 static void
969 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
970 {
971 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
972
973 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
974 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
975 }
976
977 static void
978 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
979 {
980 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
981
982 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
983 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
984 }
985
986 static void
987 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
988 {
989 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
990
991 radeon_set_context_reg_seq(cmd_buffer->cs,
992 R_028430_DB_STENCILREFMASK, 2);
993 radeon_emit(cmd_buffer->cs,
994 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
995 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
996 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
997 S_028430_STENCILOPVAL(1));
998 radeon_emit(cmd_buffer->cs,
999 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1000 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1001 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1002 S_028434_STENCILOPVAL_BF(1));
1003 }
1004
1005 static void
1006 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1007 {
1008 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1011 fui(d->depth_bounds.min));
1012 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1013 fui(d->depth_bounds.max));
1014 }
1015
1016 static void
1017 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1018 {
1019 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1020 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1021 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1022
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs,
1025 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1026 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1027 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1028 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1029 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1030 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1031 }
1032
1033 static void
1034 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1035 int index,
1036 struct radv_attachment_info *att,
1037 struct radv_image *image,
1038 VkImageLayout layout)
1039 {
1040 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1041 struct radv_color_buffer_info *cb = &att->cb;
1042 uint32_t cb_color_info = cb->cb_color_info;
1043
1044 if (!radv_layout_dcc_compressed(image, layout,
1045 radv_image_queue_family_mask(image,
1046 cmd_buffer->queue_family_index,
1047 cmd_buffer->queue_family_index))) {
1048 cb_color_info &= C_028C70_DCC_ENABLE;
1049 }
1050
1051 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1052 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1054 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1057 radeon_emit(cmd_buffer->cs, cb_color_info);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1059 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1060 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1061 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1062 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1063 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1064
1065 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1066 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1067 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1068
1069 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1070 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1071 } else {
1072 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1073 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1074 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1075 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1076 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1077 radeon_emit(cmd_buffer->cs, cb_color_info);
1078 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1079 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1080 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1081 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1082 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1083 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1084
1085 if (is_vi) { /* DCC BASE */
1086 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1087 }
1088 }
1089
1090 if (radv_image_has_dcc(image)) {
1091 /* Drawing with DCC enabled also compresses colorbuffers. */
1092 radv_update_dcc_metadata(cmd_buffer, image, true);
1093 }
1094 }
1095
1096 static void
1097 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1098 struct radv_ds_buffer_info *ds,
1099 struct radv_image *image, VkImageLayout layout,
1100 bool requires_cond_exec)
1101 {
1102 uint32_t db_z_info = ds->db_z_info;
1103 uint32_t db_z_info_reg;
1104
1105 if (!radv_image_is_tc_compat_htile(image))
1106 return;
1107
1108 if (!radv_layout_has_htile(image, layout,
1109 radv_image_queue_family_mask(image,
1110 cmd_buffer->queue_family_index,
1111 cmd_buffer->queue_family_index))) {
1112 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1113 }
1114
1115 db_z_info &= C_028040_ZRANGE_PRECISION;
1116
1117 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1118 db_z_info_reg = R_028038_DB_Z_INFO;
1119 } else {
1120 db_z_info_reg = R_028040_DB_Z_INFO;
1121 }
1122
1123 /* When we don't know the last fast clear value we need to emit a
1124 * conditional packet that will eventually skip the following
1125 * SET_CONTEXT_REG packet.
1126 */
1127 if (requires_cond_exec) {
1128 uint64_t va = radv_buffer_get_va(image->bo);
1129 va += image->offset + image->tc_compat_zrange_offset;
1130
1131 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1132 radeon_emit(cmd_buffer->cs, va);
1133 radeon_emit(cmd_buffer->cs, va >> 32);
1134 radeon_emit(cmd_buffer->cs, 0);
1135 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1136 }
1137
1138 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1139 }
1140
1141 static void
1142 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1143 struct radv_ds_buffer_info *ds,
1144 struct radv_image *image,
1145 VkImageLayout layout)
1146 {
1147 uint32_t db_z_info = ds->db_z_info;
1148 uint32_t db_stencil_info = ds->db_stencil_info;
1149
1150 if (!radv_layout_has_htile(image, layout,
1151 radv_image_queue_family_mask(image,
1152 cmd_buffer->queue_family_index,
1153 cmd_buffer->queue_family_index))) {
1154 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1155 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1156 }
1157
1158 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1159 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1160
1161
1162 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1163 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1164 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1165 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1166 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1167
1168 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1169 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1170 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1171 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1172 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1173 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1174 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1175 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1176 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1177 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1178 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1179
1180 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1181 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1182 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1183 } else {
1184 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1185
1186 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1187 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1188 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1189 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1190 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1191 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1192 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1193 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1195 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1196
1197 }
1198
1199 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1200 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1201
1202 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1203 ds->pa_su_poly_offset_db_fmt_cntl);
1204 }
1205
1206 /**
1207 * Update the fast clear depth/stencil values if the image is bound as a
1208 * depth/stencil buffer.
1209 */
1210 static void
1211 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1212 struct radv_image *image,
1213 VkClearDepthStencilValue ds_clear_value,
1214 VkImageAspectFlags aspects)
1215 {
1216 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1217 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1218 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1219 struct radv_attachment_info *att;
1220 uint32_t att_idx;
1221
1222 if (!framebuffer || !subpass)
1223 return;
1224
1225 if (!subpass->depth_stencil_attachment)
1226 return;
1227
1228 att_idx = subpass->depth_stencil_attachment->attachment;
1229 att = &framebuffer->attachments[att_idx];
1230 if (att->attachment->image != image)
1231 return;
1232
1233 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1234 radeon_emit(cs, ds_clear_value.stencil);
1235 radeon_emit(cs, fui(ds_clear_value.depth));
1236
1237 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1238 * only needed when clearing Z to 0.0.
1239 */
1240 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1241 ds_clear_value.depth == 0.0) {
1242 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1243
1244 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1245 layout, false);
1246 }
1247
1248 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1249 }
1250
1251 /**
1252 * Set the clear depth/stencil values to the image's metadata.
1253 */
1254 static void
1255 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1256 struct radv_image *image,
1257 VkClearDepthStencilValue ds_clear_value,
1258 VkImageAspectFlags aspects)
1259 {
1260 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1261 uint64_t va = radv_buffer_get_va(image->bo);
1262 unsigned reg_offset = 0, reg_count = 0;
1263
1264 va += image->offset + image->clear_value_offset;
1265
1266 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1267 ++reg_count;
1268 } else {
1269 ++reg_offset;
1270 va += 4;
1271 }
1272 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1273 ++reg_count;
1274
1275 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1276 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1277 S_370_WR_CONFIRM(1) |
1278 S_370_ENGINE_SEL(V_370_PFP));
1279 radeon_emit(cs, va);
1280 radeon_emit(cs, va >> 32);
1281 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1282 radeon_emit(cs, ds_clear_value.stencil);
1283 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1284 radeon_emit(cs, fui(ds_clear_value.depth));
1285 }
1286
1287 /**
1288 * Update the TC-compat metadata value for this image.
1289 */
1290 static void
1291 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_image *image,
1293 uint32_t value)
1294 {
1295 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1296 uint64_t va = radv_buffer_get_va(image->bo);
1297 va += image->offset + image->tc_compat_zrange_offset;
1298
1299 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1300 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1301 S_370_WR_CONFIRM(1) |
1302 S_370_ENGINE_SEL(V_370_PFP));
1303 radeon_emit(cs, va);
1304 radeon_emit(cs, va >> 32);
1305 radeon_emit(cs, value);
1306 }
1307
1308 static void
1309 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1310 struct radv_image *image,
1311 VkClearDepthStencilValue ds_clear_value)
1312 {
1313 uint64_t va = radv_buffer_get_va(image->bo);
1314 va += image->offset + image->tc_compat_zrange_offset;
1315 uint32_t cond_val;
1316
1317 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1318 * depth clear value is 0.0f.
1319 */
1320 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1321
1322 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1323 }
1324
1325 /**
1326 * Update the clear depth/stencil values for this image.
1327 */
1328 void
1329 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1330 struct radv_image *image,
1331 VkClearDepthStencilValue ds_clear_value,
1332 VkImageAspectFlags aspects)
1333 {
1334 assert(radv_image_has_htile(image));
1335
1336 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1337
1338 if (radv_image_is_tc_compat_htile(image) &&
1339 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1340 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1341 ds_clear_value);
1342 }
1343
1344 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1345 aspects);
1346 }
1347
1348 /**
1349 * Load the clear depth/stencil values from the image's metadata.
1350 */
1351 static void
1352 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1353 struct radv_image *image)
1354 {
1355 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1356 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1357 uint64_t va = radv_buffer_get_va(image->bo);
1358 unsigned reg_offset = 0, reg_count = 0;
1359
1360 va += image->offset + image->clear_value_offset;
1361
1362 if (!radv_image_has_htile(image))
1363 return;
1364
1365 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1366 ++reg_count;
1367 } else {
1368 ++reg_offset;
1369 va += 4;
1370 }
1371 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1372 ++reg_count;
1373
1374 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1375
1376 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1377 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1378 radeon_emit(cs, va);
1379 radeon_emit(cs, va >> 32);
1380 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1381 radeon_emit(cs, reg_count);
1382 } else {
1383 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1384 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1385 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1386 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1387 radeon_emit(cs, va);
1388 radeon_emit(cs, va >> 32);
1389 radeon_emit(cs, reg >> 2);
1390 radeon_emit(cs, 0);
1391
1392 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1393 radeon_emit(cs, 0);
1394 }
1395 }
1396
1397 /*
1398 * With DCC some colors don't require CMASK elimination before being
1399 * used as a texture. This sets a predicate value to determine if the
1400 * cmask eliminate is required.
1401 */
1402 void
1403 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1404 struct radv_image *image, bool value)
1405 {
1406 uint64_t pred_val = value;
1407 uint64_t va = radv_buffer_get_va(image->bo);
1408 va += image->offset + image->fce_pred_offset;
1409
1410 assert(radv_image_has_dcc(image));
1411
1412 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1413 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1414 S_370_WR_CONFIRM(1) |
1415 S_370_ENGINE_SEL(V_370_PFP));
1416 radeon_emit(cmd_buffer->cs, va);
1417 radeon_emit(cmd_buffer->cs, va >> 32);
1418 radeon_emit(cmd_buffer->cs, pred_val);
1419 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1420 }
1421
1422 /**
1423 * Update the DCC predicate to reflect the compression state.
1424 */
1425 void
1426 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_image *image, bool value)
1428 {
1429 uint64_t pred_val = value;
1430 uint64_t va = radv_buffer_get_va(image->bo);
1431 va += image->offset + image->dcc_pred_offset;
1432
1433 assert(radv_image_has_dcc(image));
1434
1435 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1436 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1437 S_370_WR_CONFIRM(1) |
1438 S_370_ENGINE_SEL(V_370_PFP));
1439 radeon_emit(cmd_buffer->cs, va);
1440 radeon_emit(cmd_buffer->cs, va >> 32);
1441 radeon_emit(cmd_buffer->cs, pred_val);
1442 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1443 }
1444
1445 /**
1446 * Update the fast clear color values if the image is bound as a color buffer.
1447 */
1448 static void
1449 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1450 struct radv_image *image,
1451 int cb_idx,
1452 uint32_t color_values[2])
1453 {
1454 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1455 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1456 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1457 struct radv_attachment_info *att;
1458 uint32_t att_idx;
1459
1460 if (!framebuffer || !subpass)
1461 return;
1462
1463 att_idx = subpass->color_attachments[cb_idx].attachment;
1464 if (att_idx == VK_ATTACHMENT_UNUSED)
1465 return;
1466
1467 att = &framebuffer->attachments[att_idx];
1468 if (att->attachment->image != image)
1469 return;
1470
1471 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1472 radeon_emit(cs, color_values[0]);
1473 radeon_emit(cs, color_values[1]);
1474
1475 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1476 }
1477
1478 /**
1479 * Set the clear color values to the image's metadata.
1480 */
1481 static void
1482 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1483 struct radv_image *image,
1484 uint32_t color_values[2])
1485 {
1486 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1487 uint64_t va = radv_buffer_get_va(image->bo);
1488
1489 va += image->offset + image->clear_value_offset;
1490
1491 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1492
1493 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1494 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1495 S_370_WR_CONFIRM(1) |
1496 S_370_ENGINE_SEL(V_370_PFP));
1497 radeon_emit(cs, va);
1498 radeon_emit(cs, va >> 32);
1499 radeon_emit(cs, color_values[0]);
1500 radeon_emit(cs, color_values[1]);
1501 }
1502
1503 /**
1504 * Update the clear color values for this image.
1505 */
1506 void
1507 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1508 struct radv_image *image,
1509 int cb_idx,
1510 uint32_t color_values[2])
1511 {
1512 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1513
1514 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1515
1516 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1517 color_values);
1518 }
1519
1520 /**
1521 * Load the clear color values from the image's metadata.
1522 */
1523 static void
1524 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1525 struct radv_image *image,
1526 int cb_idx)
1527 {
1528 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1529 uint64_t va = radv_buffer_get_va(image->bo);
1530
1531 va += image->offset + image->clear_value_offset;
1532
1533 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1534 return;
1535
1536 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1537
1538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1539 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1540 radeon_emit(cs, va);
1541 radeon_emit(cs, va >> 32);
1542 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1543 radeon_emit(cs, 2);
1544 } else {
1545 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1546 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1547 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1548 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1549 COPY_DATA_COUNT_SEL);
1550 radeon_emit(cs, va);
1551 radeon_emit(cs, va >> 32);
1552 radeon_emit(cs, reg >> 2);
1553 radeon_emit(cs, 0);
1554
1555 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1556 radeon_emit(cs, 0);
1557 }
1558 }
1559
1560 static void
1561 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1562 {
1563 int i;
1564 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1565 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1566 unsigned num_bpp64_colorbufs = 0;
1567
1568 /* this may happen for inherited secondary recording */
1569 if (!framebuffer)
1570 return;
1571
1572 for (i = 0; i < 8; ++i) {
1573 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1574 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1575 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1576 continue;
1577 }
1578
1579 int idx = subpass->color_attachments[i].attachment;
1580 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1581 struct radv_image *image = att->attachment->image;
1582 VkImageLayout layout = subpass->color_attachments[i].layout;
1583
1584 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1585
1586 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1587 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1588
1589 radv_load_color_clear_metadata(cmd_buffer, image, i);
1590
1591 if (image->surface.bpe >= 8)
1592 num_bpp64_colorbufs++;
1593 }
1594
1595 if (subpass->depth_stencil_attachment) {
1596 int idx = subpass->depth_stencil_attachment->attachment;
1597 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1598 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1599 struct radv_image *image = att->attachment->image;
1600 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1601 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1602 cmd_buffer->queue_family_index,
1603 cmd_buffer->queue_family_index);
1604 /* We currently don't support writing decompressed HTILE */
1605 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1606 radv_layout_is_htile_compressed(image, layout, queue_mask));
1607
1608 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1609
1610 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1611 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1612 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1613 }
1614 radv_load_ds_clear_metadata(cmd_buffer, image);
1615 } else {
1616 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1617 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1618 else
1619 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1620
1621 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1622 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1623 }
1624 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1625 S_028208_BR_X(framebuffer->width) |
1626 S_028208_BR_Y(framebuffer->height));
1627
1628 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1629 uint8_t watermark = 4; /* Default value for VI. */
1630
1631 /* For optimal DCC performance. */
1632 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1633 if (num_bpp64_colorbufs >= 5) {
1634 watermark = 8;
1635 } else {
1636 watermark = 6;
1637 }
1638 }
1639
1640 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1641 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1642 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1643 }
1644
1645 if (cmd_buffer->device->dfsm_allowed) {
1646 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1647 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1648 }
1649
1650 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1651 }
1652
1653 static void
1654 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1655 {
1656 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1657 struct radv_cmd_state *state = &cmd_buffer->state;
1658
1659 if (state->index_type != state->last_index_type) {
1660 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1661 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1662 2, state->index_type);
1663 } else {
1664 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1665 radeon_emit(cs, state->index_type);
1666 }
1667
1668 state->last_index_type = state->index_type;
1669 }
1670
1671 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1672 radeon_emit(cs, state->index_va);
1673 radeon_emit(cs, state->index_va >> 32);
1674
1675 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1676 radeon_emit(cs, state->max_index_count);
1677
1678 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1679 }
1680
1681 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1682 {
1683 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1684 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1685 uint32_t pa_sc_mode_cntl_1 =
1686 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1687 uint32_t db_count_control;
1688
1689 if(!cmd_buffer->state.active_occlusion_queries) {
1690 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1691 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1692 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1693 has_perfect_queries) {
1694 /* Re-enable out-of-order rasterization if the
1695 * bound pipeline supports it and if it's has
1696 * been disabled before starting any perfect
1697 * occlusion queries.
1698 */
1699 radeon_set_context_reg(cmd_buffer->cs,
1700 R_028A4C_PA_SC_MODE_CNTL_1,
1701 pa_sc_mode_cntl_1);
1702 }
1703 }
1704 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1705 } else {
1706 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1707 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1708
1709 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1710 db_count_control =
1711 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1712 S_028004_SAMPLE_RATE(sample_rate) |
1713 S_028004_ZPASS_ENABLE(1) |
1714 S_028004_SLICE_EVEN_ENABLE(1) |
1715 S_028004_SLICE_ODD_ENABLE(1);
1716
1717 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1718 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1719 has_perfect_queries) {
1720 /* If the bound pipeline has enabled
1721 * out-of-order rasterization, we should
1722 * disable it before starting any perfect
1723 * occlusion queries.
1724 */
1725 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1726
1727 radeon_set_context_reg(cmd_buffer->cs,
1728 R_028A4C_PA_SC_MODE_CNTL_1,
1729 pa_sc_mode_cntl_1);
1730 }
1731 } else {
1732 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1733 S_028004_SAMPLE_RATE(sample_rate);
1734 }
1735 }
1736
1737 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1738
1739 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1740 }
1741
1742 static void
1743 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1744 {
1745 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1746
1747 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1748 radv_emit_viewport(cmd_buffer);
1749
1750 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1751 !cmd_buffer->device->physical_device->has_scissor_bug)
1752 radv_emit_scissor(cmd_buffer);
1753
1754 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1755 radv_emit_line_width(cmd_buffer);
1756
1757 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1758 radv_emit_blend_constants(cmd_buffer);
1759
1760 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1761 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1762 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1763 radv_emit_stencil(cmd_buffer);
1764
1765 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1766 radv_emit_depth_bounds(cmd_buffer);
1767
1768 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1769 radv_emit_depth_bias(cmd_buffer);
1770
1771 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1772 radv_emit_discard_rectangle(cmd_buffer);
1773
1774 cmd_buffer->state.dirty &= ~states;
1775 }
1776
1777 static void
1778 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1779 VkPipelineBindPoint bind_point)
1780 {
1781 struct radv_descriptor_state *descriptors_state =
1782 radv_get_descriptors_state(cmd_buffer, bind_point);
1783 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1784 unsigned bo_offset;
1785
1786 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1787 set->mapped_ptr,
1788 &bo_offset))
1789 return;
1790
1791 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1792 set->va += bo_offset;
1793 }
1794
1795 static void
1796 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1797 VkPipelineBindPoint bind_point)
1798 {
1799 struct radv_descriptor_state *descriptors_state =
1800 radv_get_descriptors_state(cmd_buffer, bind_point);
1801 uint32_t size = MAX_SETS * 4;
1802 uint32_t offset;
1803 void *ptr;
1804
1805 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1806 256, &offset, &ptr))
1807 return;
1808
1809 for (unsigned i = 0; i < MAX_SETS; i++) {
1810 uint32_t *uptr = ((uint32_t *)ptr) + i;
1811 uint64_t set_va = 0;
1812 struct radv_descriptor_set *set = descriptors_state->sets[i];
1813 if (descriptors_state->valid & (1u << i))
1814 set_va = set->va;
1815 uptr[0] = set_va & 0xffffffff;
1816 }
1817
1818 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1819 va += offset;
1820
1821 if (cmd_buffer->state.pipeline) {
1822 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1823 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1824 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1825
1826 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1827 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1828 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1829
1830 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1831 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1832 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1833
1834 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1835 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1836 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1837
1838 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1839 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1840 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1841 }
1842
1843 if (cmd_buffer->state.compute_pipeline)
1844 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1845 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1846 }
1847
1848 static void
1849 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1850 VkShaderStageFlags stages)
1851 {
1852 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1853 VK_PIPELINE_BIND_POINT_COMPUTE :
1854 VK_PIPELINE_BIND_POINT_GRAPHICS;
1855 struct radv_descriptor_state *descriptors_state =
1856 radv_get_descriptors_state(cmd_buffer, bind_point);
1857 struct radv_cmd_state *state = &cmd_buffer->state;
1858 bool flush_indirect_descriptors;
1859
1860 if (!descriptors_state->dirty)
1861 return;
1862
1863 if (descriptors_state->push_dirty)
1864 radv_flush_push_descriptors(cmd_buffer, bind_point);
1865
1866 flush_indirect_descriptors =
1867 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1868 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1869 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1870 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1871
1872 if (flush_indirect_descriptors)
1873 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1874
1875 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1876 cmd_buffer->cs,
1877 MAX_SETS * MESA_SHADER_STAGES * 4);
1878
1879 if (cmd_buffer->state.pipeline) {
1880 radv_foreach_stage(stage, stages) {
1881 if (!cmd_buffer->state.pipeline->shaders[stage])
1882 continue;
1883
1884 radv_emit_descriptor_pointers(cmd_buffer,
1885 cmd_buffer->state.pipeline,
1886 descriptors_state, stage);
1887 }
1888 }
1889
1890 if (cmd_buffer->state.compute_pipeline &&
1891 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1892 radv_emit_descriptor_pointers(cmd_buffer,
1893 cmd_buffer->state.compute_pipeline,
1894 descriptors_state,
1895 MESA_SHADER_COMPUTE);
1896 }
1897
1898 descriptors_state->dirty = 0;
1899 descriptors_state->push_dirty = false;
1900
1901 assert(cmd_buffer->cs->cdw <= cdw_max);
1902
1903 if (unlikely(cmd_buffer->device->trace_bo))
1904 radv_save_descriptors(cmd_buffer, bind_point);
1905 }
1906
1907 static void
1908 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1909 VkShaderStageFlags stages)
1910 {
1911 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1912 ? cmd_buffer->state.compute_pipeline
1913 : cmd_buffer->state.pipeline;
1914 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1915 VK_PIPELINE_BIND_POINT_COMPUTE :
1916 VK_PIPELINE_BIND_POINT_GRAPHICS;
1917 struct radv_descriptor_state *descriptors_state =
1918 radv_get_descriptors_state(cmd_buffer, bind_point);
1919 struct radv_pipeline_layout *layout = pipeline->layout;
1920 struct radv_shader_variant *shader, *prev_shader;
1921 bool need_push_constants = false;
1922 unsigned offset;
1923 void *ptr;
1924 uint64_t va;
1925
1926 stages &= cmd_buffer->push_constant_stages;
1927 if (!stages ||
1928 (!layout->push_constant_size && !layout->dynamic_offset_count))
1929 return;
1930
1931 radv_foreach_stage(stage, stages) {
1932 if (!pipeline->shaders[stage])
1933 continue;
1934
1935 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1936 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1937
1938 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1939 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1940
1941 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1942 AC_UD_INLINE_PUSH_CONSTANTS,
1943 count,
1944 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1945 }
1946
1947 if (need_push_constants) {
1948 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1949 16 * layout->dynamic_offset_count,
1950 256, &offset, &ptr))
1951 return;
1952
1953 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1954 memcpy((char*)ptr + layout->push_constant_size,
1955 descriptors_state->dynamic_buffers,
1956 16 * layout->dynamic_offset_count);
1957
1958 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1959 va += offset;
1960
1961 MAYBE_UNUSED unsigned cdw_max =
1962 radeon_check_space(cmd_buffer->device->ws,
1963 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1964
1965 prev_shader = NULL;
1966 radv_foreach_stage(stage, stages) {
1967 shader = radv_get_shader(pipeline, stage);
1968
1969 /* Avoid redundantly emitting the address for merged stages. */
1970 if (shader && shader != prev_shader) {
1971 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1972 AC_UD_PUSH_CONSTANTS, va);
1973
1974 prev_shader = shader;
1975 }
1976 }
1977 assert(cmd_buffer->cs->cdw <= cdw_max);
1978 }
1979
1980 cmd_buffer->push_constant_stages &= ~stages;
1981 }
1982
1983 static void
1984 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1985 bool pipeline_is_dirty)
1986 {
1987 if ((pipeline_is_dirty ||
1988 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1989 cmd_buffer->state.pipeline->vertex_elements.count &&
1990 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1991 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1992 unsigned vb_offset;
1993 void *vb_ptr;
1994 uint32_t i = 0;
1995 uint32_t count = velems->count;
1996 uint64_t va;
1997
1998 /* allocate some descriptor state for vertex buffers */
1999 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2000 &vb_offset, &vb_ptr))
2001 return;
2002
2003 for (i = 0; i < count; i++) {
2004 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2005 uint32_t offset;
2006 int vb = velems->binding[i];
2007 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
2008 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
2009
2010 va = radv_buffer_get_va(buffer->bo);
2011
2012 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
2013 va += offset + buffer->offset;
2014 desc[0] = va;
2015 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2016 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2017 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2018 else
2019 desc[2] = buffer->size - offset;
2020 desc[3] = velems->rsrc_word3[i];
2021 }
2022
2023 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2024 va += vb_offset;
2025
2026 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2027 AC_UD_VS_VERTEX_BUFFERS, va);
2028
2029 cmd_buffer->state.vb_va = va;
2030 cmd_buffer->state.vb_size = count * 16;
2031 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2032 }
2033 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2034 }
2035
2036 static void
2037 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2038 {
2039 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2040 struct radv_userdata_info *loc;
2041 uint32_t base_reg;
2042
2043 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2044 if (!radv_get_shader(pipeline, stage))
2045 continue;
2046
2047 loc = radv_lookup_user_sgpr(pipeline, stage,
2048 AC_UD_STREAMOUT_BUFFERS);
2049 if (loc->sgpr_idx == -1)
2050 continue;
2051
2052 base_reg = pipeline->user_data_0[stage];
2053
2054 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2055 base_reg + loc->sgpr_idx * 4, va, false);
2056 }
2057
2058 if (pipeline->gs_copy_shader) {
2059 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2060 if (loc->sgpr_idx != -1) {
2061 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2062
2063 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2064 base_reg + loc->sgpr_idx * 4, va, false);
2065 }
2066 }
2067 }
2068
2069 static void
2070 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2071 {
2072 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2073 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2074 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2075 unsigned so_offset;
2076 void *so_ptr;
2077 uint64_t va;
2078
2079 /* Allocate some descriptor state for streamout buffers. */
2080 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2081 MAX_SO_BUFFERS * 16, 256,
2082 &so_offset, &so_ptr))
2083 return;
2084
2085 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2086 struct radv_buffer *buffer = sb[i].buffer;
2087 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2088
2089 if (!(so->enabled_mask & (1 << i)))
2090 continue;
2091
2092 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2093
2094 va += sb[i].offset;
2095
2096 /* Set the descriptor.
2097 *
2098 * On VI, the format must be non-INVALID, otherwise
2099 * the buffer will be considered not bound and store
2100 * instructions will be no-ops.
2101 */
2102 desc[0] = va;
2103 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2104 desc[2] = 0xffffffff;
2105 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2106 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2107 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2108 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2109 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2110 }
2111
2112 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2113 va += so_offset;
2114
2115 radv_emit_streamout_buffers(cmd_buffer, va);
2116 }
2117
2118 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2119 }
2120
2121 static void
2122 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2123 {
2124 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2125 radv_flush_streamout_descriptors(cmd_buffer);
2126 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2127 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2128 }
2129
2130 struct radv_draw_info {
2131 /**
2132 * Number of vertices.
2133 */
2134 uint32_t count;
2135
2136 /**
2137 * Index of the first vertex.
2138 */
2139 int32_t vertex_offset;
2140
2141 /**
2142 * First instance id.
2143 */
2144 uint32_t first_instance;
2145
2146 /**
2147 * Number of instances.
2148 */
2149 uint32_t instance_count;
2150
2151 /**
2152 * First index (indexed draws only).
2153 */
2154 uint32_t first_index;
2155
2156 /**
2157 * Whether it's an indexed draw.
2158 */
2159 bool indexed;
2160
2161 /**
2162 * Indirect draw parameters resource.
2163 */
2164 struct radv_buffer *indirect;
2165 uint64_t indirect_offset;
2166 uint32_t stride;
2167
2168 /**
2169 * Draw count parameters resource.
2170 */
2171 struct radv_buffer *count_buffer;
2172 uint64_t count_buffer_offset;
2173
2174 /**
2175 * Stream output parameters resource.
2176 */
2177 struct radv_buffer *strmout_buffer;
2178 uint64_t strmout_buffer_offset;
2179 };
2180
2181 static void
2182 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2183 const struct radv_draw_info *draw_info)
2184 {
2185 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2186 struct radv_cmd_state *state = &cmd_buffer->state;
2187 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2188 uint32_t ia_multi_vgt_param;
2189 int32_t primitive_reset_en;
2190
2191 /* Draw state. */
2192 ia_multi_vgt_param =
2193 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2194 draw_info->indirect,
2195 draw_info->indirect ? 0 : draw_info->count);
2196
2197 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2198 if (info->chip_class >= GFX9) {
2199 radeon_set_uconfig_reg_idx(cs,
2200 R_030960_IA_MULTI_VGT_PARAM,
2201 4, ia_multi_vgt_param);
2202 } else if (info->chip_class >= CIK) {
2203 radeon_set_context_reg_idx(cs,
2204 R_028AA8_IA_MULTI_VGT_PARAM,
2205 1, ia_multi_vgt_param);
2206 } else {
2207 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2208 ia_multi_vgt_param);
2209 }
2210 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2211 }
2212
2213 /* Primitive restart. */
2214 primitive_reset_en =
2215 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2216
2217 if (primitive_reset_en != state->last_primitive_reset_en) {
2218 state->last_primitive_reset_en = primitive_reset_en;
2219 if (info->chip_class >= GFX9) {
2220 radeon_set_uconfig_reg(cs,
2221 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2222 primitive_reset_en);
2223 } else {
2224 radeon_set_context_reg(cs,
2225 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2226 primitive_reset_en);
2227 }
2228 }
2229
2230 if (primitive_reset_en) {
2231 uint32_t primitive_reset_index =
2232 state->index_type ? 0xffffffffu : 0xffffu;
2233
2234 if (primitive_reset_index != state->last_primitive_reset_index) {
2235 radeon_set_context_reg(cs,
2236 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2237 primitive_reset_index);
2238 state->last_primitive_reset_index = primitive_reset_index;
2239 }
2240 }
2241
2242 if (draw_info->strmout_buffer) {
2243 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2244
2245 va += draw_info->strmout_buffer->offset +
2246 draw_info->strmout_buffer_offset;
2247
2248 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2249 draw_info->stride);
2250
2251 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2252 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2253 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2254 COPY_DATA_WR_CONFIRM);
2255 radeon_emit(cs, va);
2256 radeon_emit(cs, va >> 32);
2257 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2258 radeon_emit(cs, 0); /* unused */
2259
2260 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2261 }
2262 }
2263
2264 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2265 VkPipelineStageFlags src_stage_mask)
2266 {
2267 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2268 VK_PIPELINE_STAGE_TRANSFER_BIT |
2269 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2270 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2271 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2272 }
2273
2274 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2275 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2276 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2277 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2278 VK_PIPELINE_STAGE_TRANSFER_BIT |
2279 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2280 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2281 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2282 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2283 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2284 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2285 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2286 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2287 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2288 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2289 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2290 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2291 }
2292 }
2293
2294 static enum radv_cmd_flush_bits
2295 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2296 VkAccessFlags src_flags,
2297 struct radv_image *image)
2298 {
2299 bool flush_CB_meta = true, flush_DB_meta = true;
2300 enum radv_cmd_flush_bits flush_bits = 0;
2301 uint32_t b;
2302
2303 if (image) {
2304 if (!radv_image_has_CB_metadata(image))
2305 flush_CB_meta = false;
2306 if (!radv_image_has_htile(image))
2307 flush_DB_meta = false;
2308 }
2309
2310 for_each_bit(b, src_flags) {
2311 switch ((VkAccessFlagBits)(1 << b)) {
2312 case VK_ACCESS_SHADER_WRITE_BIT:
2313 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2314 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2315 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2316 break;
2317 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2318 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2319 if (flush_CB_meta)
2320 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2321 break;
2322 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2323 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2324 if (flush_DB_meta)
2325 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2326 break;
2327 case VK_ACCESS_TRANSFER_WRITE_BIT:
2328 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2329 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2330 RADV_CMD_FLAG_INV_GLOBAL_L2;
2331
2332 if (flush_CB_meta)
2333 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2334 if (flush_DB_meta)
2335 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2336 break;
2337 default:
2338 break;
2339 }
2340 }
2341 return flush_bits;
2342 }
2343
2344 static enum radv_cmd_flush_bits
2345 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2346 VkAccessFlags dst_flags,
2347 struct radv_image *image)
2348 {
2349 bool flush_CB_meta = true, flush_DB_meta = true;
2350 enum radv_cmd_flush_bits flush_bits = 0;
2351 bool flush_CB = true, flush_DB = true;
2352 bool image_is_coherent = false;
2353 uint32_t b;
2354
2355 if (image) {
2356 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2357 flush_CB = false;
2358 flush_DB = false;
2359 }
2360
2361 if (!radv_image_has_CB_metadata(image))
2362 flush_CB_meta = false;
2363 if (!radv_image_has_htile(image))
2364 flush_DB_meta = false;
2365
2366 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2367 if (image->info.samples == 1 &&
2368 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2369 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2370 !vk_format_is_stencil(image->vk_format)) {
2371 /* Single-sample color and single-sample depth
2372 * (not stencil) are coherent with shaders on
2373 * GFX9.
2374 */
2375 image_is_coherent = true;
2376 }
2377 }
2378 }
2379
2380 for_each_bit(b, dst_flags) {
2381 switch ((VkAccessFlagBits)(1 << b)) {
2382 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2383 case VK_ACCESS_INDEX_READ_BIT:
2384 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2385 break;
2386 case VK_ACCESS_UNIFORM_READ_BIT:
2387 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2388 break;
2389 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2390 case VK_ACCESS_TRANSFER_READ_BIT:
2391 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2392 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2393 RADV_CMD_FLAG_INV_GLOBAL_L2;
2394 break;
2395 case VK_ACCESS_SHADER_READ_BIT:
2396 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2397
2398 if (!image_is_coherent)
2399 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2400 break;
2401 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2402 if (flush_CB)
2403 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2404 if (flush_CB_meta)
2405 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2406 break;
2407 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2408 if (flush_DB)
2409 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2410 if (flush_DB_meta)
2411 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2412 break;
2413 default:
2414 break;
2415 }
2416 }
2417 return flush_bits;
2418 }
2419
2420 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2421 const struct radv_subpass_barrier *barrier)
2422 {
2423 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2424 NULL);
2425 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2426 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2427 NULL);
2428 }
2429
2430 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2431 struct radv_subpass_attachment att)
2432 {
2433 unsigned idx = att.attachment;
2434 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2435 VkImageSubresourceRange range;
2436 range.aspectMask = 0;
2437 range.baseMipLevel = view->base_mip;
2438 range.levelCount = 1;
2439 range.baseArrayLayer = view->base_layer;
2440 range.layerCount = cmd_buffer->state.framebuffer->layers;
2441
2442 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2443 /* If the current subpass uses multiview, the driver might have
2444 * performed a fast color/depth clear to the whole image
2445 * (including all layers). To make sure the driver will
2446 * decompress the image correctly (if needed), we have to
2447 * account for the "real" number of layers. If the view mask is
2448 * sparse, this will decompress more layers than needed.
2449 */
2450 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2451 }
2452
2453 radv_handle_image_transition(cmd_buffer,
2454 view->image,
2455 cmd_buffer->state.attachments[idx].current_layout,
2456 att.layout, 0, 0, &range);
2457
2458 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2459
2460
2461 }
2462
2463 void
2464 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2465 const struct radv_subpass *subpass)
2466 {
2467 cmd_buffer->state.subpass = subpass;
2468
2469 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2470 }
2471
2472 static VkResult
2473 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2474 struct radv_render_pass *pass,
2475 const VkRenderPassBeginInfo *info)
2476 {
2477 struct radv_cmd_state *state = &cmd_buffer->state;
2478
2479 if (pass->attachment_count == 0) {
2480 state->attachments = NULL;
2481 return VK_SUCCESS;
2482 }
2483
2484 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2485 pass->attachment_count *
2486 sizeof(state->attachments[0]),
2487 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2488 if (state->attachments == NULL) {
2489 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2490 return cmd_buffer->record_result;
2491 }
2492
2493 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2494 struct radv_render_pass_attachment *att = &pass->attachments[i];
2495 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2496 VkImageAspectFlags clear_aspects = 0;
2497
2498 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2499 /* color attachment */
2500 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2501 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2502 }
2503 } else {
2504 /* depthstencil attachment */
2505 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2506 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2507 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2508 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2509 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2510 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2511 }
2512 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2513 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2514 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2515 }
2516 }
2517
2518 state->attachments[i].pending_clear_aspects = clear_aspects;
2519 state->attachments[i].cleared_views = 0;
2520 if (clear_aspects && info) {
2521 assert(info->clearValueCount > i);
2522 state->attachments[i].clear_value = info->pClearValues[i];
2523 }
2524
2525 state->attachments[i].current_layout = att->initial_layout;
2526 }
2527
2528 return VK_SUCCESS;
2529 }
2530
2531 VkResult radv_AllocateCommandBuffers(
2532 VkDevice _device,
2533 const VkCommandBufferAllocateInfo *pAllocateInfo,
2534 VkCommandBuffer *pCommandBuffers)
2535 {
2536 RADV_FROM_HANDLE(radv_device, device, _device);
2537 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2538
2539 VkResult result = VK_SUCCESS;
2540 uint32_t i;
2541
2542 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2543
2544 if (!list_empty(&pool->free_cmd_buffers)) {
2545 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2546
2547 list_del(&cmd_buffer->pool_link);
2548 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2549
2550 result = radv_reset_cmd_buffer(cmd_buffer);
2551 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2552 cmd_buffer->level = pAllocateInfo->level;
2553
2554 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2555 } else {
2556 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2557 &pCommandBuffers[i]);
2558 }
2559 if (result != VK_SUCCESS)
2560 break;
2561 }
2562
2563 if (result != VK_SUCCESS) {
2564 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2565 i, pCommandBuffers);
2566
2567 /* From the Vulkan 1.0.66 spec:
2568 *
2569 * "vkAllocateCommandBuffers can be used to create multiple
2570 * command buffers. If the creation of any of those command
2571 * buffers fails, the implementation must destroy all
2572 * successfully created command buffer objects from this
2573 * command, set all entries of the pCommandBuffers array to
2574 * NULL and return the error."
2575 */
2576 memset(pCommandBuffers, 0,
2577 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2578 }
2579
2580 return result;
2581 }
2582
2583 void radv_FreeCommandBuffers(
2584 VkDevice device,
2585 VkCommandPool commandPool,
2586 uint32_t commandBufferCount,
2587 const VkCommandBuffer *pCommandBuffers)
2588 {
2589 for (uint32_t i = 0; i < commandBufferCount; i++) {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2591
2592 if (cmd_buffer) {
2593 if (cmd_buffer->pool) {
2594 list_del(&cmd_buffer->pool_link);
2595 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2596 } else
2597 radv_cmd_buffer_destroy(cmd_buffer);
2598
2599 }
2600 }
2601 }
2602
2603 VkResult radv_ResetCommandBuffer(
2604 VkCommandBuffer commandBuffer,
2605 VkCommandBufferResetFlags flags)
2606 {
2607 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2608 return radv_reset_cmd_buffer(cmd_buffer);
2609 }
2610
2611 VkResult radv_BeginCommandBuffer(
2612 VkCommandBuffer commandBuffer,
2613 const VkCommandBufferBeginInfo *pBeginInfo)
2614 {
2615 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2616 VkResult result = VK_SUCCESS;
2617
2618 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2619 /* If the command buffer has already been resetted with
2620 * vkResetCommandBuffer, no need to do it again.
2621 */
2622 result = radv_reset_cmd_buffer(cmd_buffer);
2623 if (result != VK_SUCCESS)
2624 return result;
2625 }
2626
2627 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2628 cmd_buffer->state.last_primitive_reset_en = -1;
2629 cmd_buffer->state.last_index_type = -1;
2630 cmd_buffer->state.last_num_instances = -1;
2631 cmd_buffer->state.last_vertex_offset = -1;
2632 cmd_buffer->state.last_first_instance = -1;
2633 cmd_buffer->state.predication_type = -1;
2634 cmd_buffer->usage_flags = pBeginInfo->flags;
2635
2636 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2637 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2638 assert(pBeginInfo->pInheritanceInfo);
2639 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2640 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2641
2642 struct radv_subpass *subpass =
2643 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2644
2645 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2646 if (result != VK_SUCCESS)
2647 return result;
2648
2649 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2650 }
2651
2652 if (unlikely(cmd_buffer->device->trace_bo)) {
2653 struct radv_device *device = cmd_buffer->device;
2654
2655 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2656 device->trace_bo);
2657
2658 radv_cmd_buffer_trace_emit(cmd_buffer);
2659 }
2660
2661 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2662
2663 return result;
2664 }
2665
2666 void radv_CmdBindVertexBuffers(
2667 VkCommandBuffer commandBuffer,
2668 uint32_t firstBinding,
2669 uint32_t bindingCount,
2670 const VkBuffer* pBuffers,
2671 const VkDeviceSize* pOffsets)
2672 {
2673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2674 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2675 bool changed = false;
2676
2677 /* We have to defer setting up vertex buffer since we need the buffer
2678 * stride from the pipeline. */
2679
2680 assert(firstBinding + bindingCount <= MAX_VBS);
2681 for (uint32_t i = 0; i < bindingCount; i++) {
2682 uint32_t idx = firstBinding + i;
2683
2684 if (!changed &&
2685 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2686 vb[idx].offset != pOffsets[i])) {
2687 changed = true;
2688 }
2689
2690 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2691 vb[idx].offset = pOffsets[i];
2692
2693 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2694 vb[idx].buffer->bo);
2695 }
2696
2697 if (!changed) {
2698 /* No state changes. */
2699 return;
2700 }
2701
2702 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2703 }
2704
2705 void radv_CmdBindIndexBuffer(
2706 VkCommandBuffer commandBuffer,
2707 VkBuffer buffer,
2708 VkDeviceSize offset,
2709 VkIndexType indexType)
2710 {
2711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2712 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2713
2714 if (cmd_buffer->state.index_buffer == index_buffer &&
2715 cmd_buffer->state.index_offset == offset &&
2716 cmd_buffer->state.index_type == indexType) {
2717 /* No state changes. */
2718 return;
2719 }
2720
2721 cmd_buffer->state.index_buffer = index_buffer;
2722 cmd_buffer->state.index_offset = offset;
2723 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2724 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2725 cmd_buffer->state.index_va += index_buffer->offset + offset;
2726
2727 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2728 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2729 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2730 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2731 }
2732
2733
2734 static void
2735 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2736 VkPipelineBindPoint bind_point,
2737 struct radv_descriptor_set *set, unsigned idx)
2738 {
2739 struct radeon_winsys *ws = cmd_buffer->device->ws;
2740
2741 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2742
2743 assert(set);
2744 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2745
2746 if (!cmd_buffer->device->use_global_bo_list) {
2747 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2748 if (set->descriptors[j])
2749 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2750 }
2751
2752 if(set->bo)
2753 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2754 }
2755
2756 void radv_CmdBindDescriptorSets(
2757 VkCommandBuffer commandBuffer,
2758 VkPipelineBindPoint pipelineBindPoint,
2759 VkPipelineLayout _layout,
2760 uint32_t firstSet,
2761 uint32_t descriptorSetCount,
2762 const VkDescriptorSet* pDescriptorSets,
2763 uint32_t dynamicOffsetCount,
2764 const uint32_t* pDynamicOffsets)
2765 {
2766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2767 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2768 unsigned dyn_idx = 0;
2769
2770 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2771 struct radv_descriptor_state *descriptors_state =
2772 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2773
2774 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2775 unsigned idx = i + firstSet;
2776 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2777 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2778
2779 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2780 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2781 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2782 assert(dyn_idx < dynamicOffsetCount);
2783
2784 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2785 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2786 dst[0] = va;
2787 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2788 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2789 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2790 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2791 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2792 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2793 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2794 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2795 cmd_buffer->push_constant_stages |=
2796 set->layout->dynamic_shader_stages;
2797 }
2798 }
2799 }
2800
2801 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2802 struct radv_descriptor_set *set,
2803 struct radv_descriptor_set_layout *layout,
2804 VkPipelineBindPoint bind_point)
2805 {
2806 struct radv_descriptor_state *descriptors_state =
2807 radv_get_descriptors_state(cmd_buffer, bind_point);
2808 set->size = layout->size;
2809 set->layout = layout;
2810
2811 if (descriptors_state->push_set.capacity < set->size) {
2812 size_t new_size = MAX2(set->size, 1024);
2813 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2814 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2815
2816 free(set->mapped_ptr);
2817 set->mapped_ptr = malloc(new_size);
2818
2819 if (!set->mapped_ptr) {
2820 descriptors_state->push_set.capacity = 0;
2821 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2822 return false;
2823 }
2824
2825 descriptors_state->push_set.capacity = new_size;
2826 }
2827
2828 return true;
2829 }
2830
2831 void radv_meta_push_descriptor_set(
2832 struct radv_cmd_buffer* cmd_buffer,
2833 VkPipelineBindPoint pipelineBindPoint,
2834 VkPipelineLayout _layout,
2835 uint32_t set,
2836 uint32_t descriptorWriteCount,
2837 const VkWriteDescriptorSet* pDescriptorWrites)
2838 {
2839 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2840 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2841 unsigned bo_offset;
2842
2843 assert(set == 0);
2844 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2845
2846 push_set->size = layout->set[set].layout->size;
2847 push_set->layout = layout->set[set].layout;
2848
2849 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2850 &bo_offset,
2851 (void**) &push_set->mapped_ptr))
2852 return;
2853
2854 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2855 push_set->va += bo_offset;
2856
2857 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2858 radv_descriptor_set_to_handle(push_set),
2859 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2860
2861 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2862 }
2863
2864 void radv_CmdPushDescriptorSetKHR(
2865 VkCommandBuffer commandBuffer,
2866 VkPipelineBindPoint pipelineBindPoint,
2867 VkPipelineLayout _layout,
2868 uint32_t set,
2869 uint32_t descriptorWriteCount,
2870 const VkWriteDescriptorSet* pDescriptorWrites)
2871 {
2872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2873 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2874 struct radv_descriptor_state *descriptors_state =
2875 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2876 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2877
2878 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2879
2880 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2881 layout->set[set].layout,
2882 pipelineBindPoint))
2883 return;
2884
2885 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2886 radv_descriptor_set_to_handle(push_set),
2887 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2888
2889 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2890 descriptors_state->push_dirty = true;
2891 }
2892
2893 void radv_CmdPushDescriptorSetWithTemplateKHR(
2894 VkCommandBuffer commandBuffer,
2895 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2896 VkPipelineLayout _layout,
2897 uint32_t set,
2898 const void* pData)
2899 {
2900 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2901 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2902 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2903 struct radv_descriptor_state *descriptors_state =
2904 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2905 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2906
2907 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2908
2909 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2910 layout->set[set].layout,
2911 templ->bind_point))
2912 return;
2913
2914 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2915 descriptorUpdateTemplate, pData);
2916
2917 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2918 descriptors_state->push_dirty = true;
2919 }
2920
2921 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2922 VkPipelineLayout layout,
2923 VkShaderStageFlags stageFlags,
2924 uint32_t offset,
2925 uint32_t size,
2926 const void* pValues)
2927 {
2928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2929 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2930 cmd_buffer->push_constant_stages |= stageFlags;
2931 }
2932
2933 VkResult radv_EndCommandBuffer(
2934 VkCommandBuffer commandBuffer)
2935 {
2936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2937
2938 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2939 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2940 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2941 si_emit_cache_flush(cmd_buffer);
2942 }
2943
2944 /* Make sure CP DMA is idle at the end of IBs because the kernel
2945 * doesn't wait for it.
2946 */
2947 si_cp_dma_wait_for_idle(cmd_buffer);
2948
2949 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2950
2951 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2952 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2953
2954 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2955
2956 return cmd_buffer->record_result;
2957 }
2958
2959 static void
2960 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2961 {
2962 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2963
2964 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2965 return;
2966
2967 assert(!pipeline->ctx_cs.cdw);
2968
2969 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2970
2971 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2972 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2973
2974 cmd_buffer->compute_scratch_size_needed =
2975 MAX2(cmd_buffer->compute_scratch_size_needed,
2976 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2977
2978 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2979 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2980
2981 if (unlikely(cmd_buffer->device->trace_bo))
2982 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2983 }
2984
2985 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2986 VkPipelineBindPoint bind_point)
2987 {
2988 struct radv_descriptor_state *descriptors_state =
2989 radv_get_descriptors_state(cmd_buffer, bind_point);
2990
2991 descriptors_state->dirty |= descriptors_state->valid;
2992 }
2993
2994 void radv_CmdBindPipeline(
2995 VkCommandBuffer commandBuffer,
2996 VkPipelineBindPoint pipelineBindPoint,
2997 VkPipeline _pipeline)
2998 {
2999 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3000 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3001
3002 switch (pipelineBindPoint) {
3003 case VK_PIPELINE_BIND_POINT_COMPUTE:
3004 if (cmd_buffer->state.compute_pipeline == pipeline)
3005 return;
3006 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3007
3008 cmd_buffer->state.compute_pipeline = pipeline;
3009 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3010 break;
3011 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3012 if (cmd_buffer->state.pipeline == pipeline)
3013 return;
3014 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3015
3016 cmd_buffer->state.pipeline = pipeline;
3017 if (!pipeline)
3018 break;
3019
3020 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3021 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3022
3023 /* the new vertex shader might not have the same user regs */
3024 cmd_buffer->state.last_first_instance = -1;
3025 cmd_buffer->state.last_vertex_offset = -1;
3026
3027 /* Prefetch all pipeline shaders at first draw time. */
3028 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3029
3030 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3031 radv_bind_streamout_state(cmd_buffer, pipeline);
3032
3033 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3034 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3035 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3036 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3037
3038 if (radv_pipeline_has_tess(pipeline))
3039 cmd_buffer->tess_rings_needed = true;
3040 break;
3041 default:
3042 assert(!"invalid bind point");
3043 break;
3044 }
3045 }
3046
3047 void radv_CmdSetViewport(
3048 VkCommandBuffer commandBuffer,
3049 uint32_t firstViewport,
3050 uint32_t viewportCount,
3051 const VkViewport* pViewports)
3052 {
3053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3054 struct radv_cmd_state *state = &cmd_buffer->state;
3055 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3056
3057 assert(firstViewport < MAX_VIEWPORTS);
3058 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3059
3060 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3061 pViewports, viewportCount * sizeof(*pViewports))) {
3062 return;
3063 }
3064
3065 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3066 viewportCount * sizeof(*pViewports));
3067
3068 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3069 }
3070
3071 void radv_CmdSetScissor(
3072 VkCommandBuffer commandBuffer,
3073 uint32_t firstScissor,
3074 uint32_t scissorCount,
3075 const VkRect2D* pScissors)
3076 {
3077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3078 struct radv_cmd_state *state = &cmd_buffer->state;
3079 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3080
3081 assert(firstScissor < MAX_SCISSORS);
3082 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3083
3084 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3085 scissorCount * sizeof(*pScissors))) {
3086 return;
3087 }
3088
3089 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3090 scissorCount * sizeof(*pScissors));
3091
3092 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3093 }
3094
3095 void radv_CmdSetLineWidth(
3096 VkCommandBuffer commandBuffer,
3097 float lineWidth)
3098 {
3099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3100
3101 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3102 return;
3103
3104 cmd_buffer->state.dynamic.line_width = lineWidth;
3105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3106 }
3107
3108 void radv_CmdSetDepthBias(
3109 VkCommandBuffer commandBuffer,
3110 float depthBiasConstantFactor,
3111 float depthBiasClamp,
3112 float depthBiasSlopeFactor)
3113 {
3114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3115 struct radv_cmd_state *state = &cmd_buffer->state;
3116
3117 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3118 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3119 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3120 return;
3121 }
3122
3123 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3124 state->dynamic.depth_bias.clamp = depthBiasClamp;
3125 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3126
3127 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3128 }
3129
3130 void radv_CmdSetBlendConstants(
3131 VkCommandBuffer commandBuffer,
3132 const float blendConstants[4])
3133 {
3134 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3135 struct radv_cmd_state *state = &cmd_buffer->state;
3136
3137 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3138 return;
3139
3140 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3141
3142 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3143 }
3144
3145 void radv_CmdSetDepthBounds(
3146 VkCommandBuffer commandBuffer,
3147 float minDepthBounds,
3148 float maxDepthBounds)
3149 {
3150 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3151 struct radv_cmd_state *state = &cmd_buffer->state;
3152
3153 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3154 state->dynamic.depth_bounds.max == maxDepthBounds) {
3155 return;
3156 }
3157
3158 state->dynamic.depth_bounds.min = minDepthBounds;
3159 state->dynamic.depth_bounds.max = maxDepthBounds;
3160
3161 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3162 }
3163
3164 void radv_CmdSetStencilCompareMask(
3165 VkCommandBuffer commandBuffer,
3166 VkStencilFaceFlags faceMask,
3167 uint32_t compareMask)
3168 {
3169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3170 struct radv_cmd_state *state = &cmd_buffer->state;
3171 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3172 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3173
3174 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3175 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3176 return;
3177 }
3178
3179 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3180 state->dynamic.stencil_compare_mask.front = compareMask;
3181 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3182 state->dynamic.stencil_compare_mask.back = compareMask;
3183
3184 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3185 }
3186
3187 void radv_CmdSetStencilWriteMask(
3188 VkCommandBuffer commandBuffer,
3189 VkStencilFaceFlags faceMask,
3190 uint32_t writeMask)
3191 {
3192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3193 struct radv_cmd_state *state = &cmd_buffer->state;
3194 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3195 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3196
3197 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3198 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3199 return;
3200 }
3201
3202 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3203 state->dynamic.stencil_write_mask.front = writeMask;
3204 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3205 state->dynamic.stencil_write_mask.back = writeMask;
3206
3207 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3208 }
3209
3210 void radv_CmdSetStencilReference(
3211 VkCommandBuffer commandBuffer,
3212 VkStencilFaceFlags faceMask,
3213 uint32_t reference)
3214 {
3215 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3216 struct radv_cmd_state *state = &cmd_buffer->state;
3217 bool front_same = state->dynamic.stencil_reference.front == reference;
3218 bool back_same = state->dynamic.stencil_reference.back == reference;
3219
3220 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3221 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3222 return;
3223 }
3224
3225 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3226 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3227 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3228 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3229
3230 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3231 }
3232
3233 void radv_CmdSetDiscardRectangleEXT(
3234 VkCommandBuffer commandBuffer,
3235 uint32_t firstDiscardRectangle,
3236 uint32_t discardRectangleCount,
3237 const VkRect2D* pDiscardRectangles)
3238 {
3239 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3240 struct radv_cmd_state *state = &cmd_buffer->state;
3241 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3242
3243 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3244 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3245
3246 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3247 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3248 return;
3249 }
3250
3251 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3252 pDiscardRectangles, discardRectangleCount);
3253
3254 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3255 }
3256
3257 void radv_CmdExecuteCommands(
3258 VkCommandBuffer commandBuffer,
3259 uint32_t commandBufferCount,
3260 const VkCommandBuffer* pCmdBuffers)
3261 {
3262 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3263
3264 assert(commandBufferCount > 0);
3265
3266 /* Emit pending flushes on primary prior to executing secondary */
3267 si_emit_cache_flush(primary);
3268
3269 for (uint32_t i = 0; i < commandBufferCount; i++) {
3270 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3271
3272 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3273 secondary->scratch_size_needed);
3274 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3275 secondary->compute_scratch_size_needed);
3276
3277 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3278 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3279 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3280 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3281 if (secondary->tess_rings_needed)
3282 primary->tess_rings_needed = true;
3283 if (secondary->sample_positions_needed)
3284 primary->sample_positions_needed = true;
3285
3286 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3287
3288
3289 /* When the secondary command buffer is compute only we don't
3290 * need to re-emit the current graphics pipeline.
3291 */
3292 if (secondary->state.emitted_pipeline) {
3293 primary->state.emitted_pipeline =
3294 secondary->state.emitted_pipeline;
3295 }
3296
3297 /* When the secondary command buffer is graphics only we don't
3298 * need to re-emit the current compute pipeline.
3299 */
3300 if (secondary->state.emitted_compute_pipeline) {
3301 primary->state.emitted_compute_pipeline =
3302 secondary->state.emitted_compute_pipeline;
3303 }
3304
3305 /* Only re-emit the draw packets when needed. */
3306 if (secondary->state.last_primitive_reset_en != -1) {
3307 primary->state.last_primitive_reset_en =
3308 secondary->state.last_primitive_reset_en;
3309 }
3310
3311 if (secondary->state.last_primitive_reset_index) {
3312 primary->state.last_primitive_reset_index =
3313 secondary->state.last_primitive_reset_index;
3314 }
3315
3316 if (secondary->state.last_ia_multi_vgt_param) {
3317 primary->state.last_ia_multi_vgt_param =
3318 secondary->state.last_ia_multi_vgt_param;
3319 }
3320
3321 primary->state.last_first_instance = secondary->state.last_first_instance;
3322 primary->state.last_num_instances = secondary->state.last_num_instances;
3323 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3324
3325 if (secondary->state.last_index_type != -1) {
3326 primary->state.last_index_type =
3327 secondary->state.last_index_type;
3328 }
3329 }
3330
3331 /* After executing commands from secondary buffers we have to dirty
3332 * some states.
3333 */
3334 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3335 RADV_CMD_DIRTY_INDEX_BUFFER |
3336 RADV_CMD_DIRTY_DYNAMIC_ALL;
3337 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3338 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3339 }
3340
3341 VkResult radv_CreateCommandPool(
3342 VkDevice _device,
3343 const VkCommandPoolCreateInfo* pCreateInfo,
3344 const VkAllocationCallbacks* pAllocator,
3345 VkCommandPool* pCmdPool)
3346 {
3347 RADV_FROM_HANDLE(radv_device, device, _device);
3348 struct radv_cmd_pool *pool;
3349
3350 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3351 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3352 if (pool == NULL)
3353 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3354
3355 if (pAllocator)
3356 pool->alloc = *pAllocator;
3357 else
3358 pool->alloc = device->alloc;
3359
3360 list_inithead(&pool->cmd_buffers);
3361 list_inithead(&pool->free_cmd_buffers);
3362
3363 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3364
3365 *pCmdPool = radv_cmd_pool_to_handle(pool);
3366
3367 return VK_SUCCESS;
3368
3369 }
3370
3371 void radv_DestroyCommandPool(
3372 VkDevice _device,
3373 VkCommandPool commandPool,
3374 const VkAllocationCallbacks* pAllocator)
3375 {
3376 RADV_FROM_HANDLE(radv_device, device, _device);
3377 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3378
3379 if (!pool)
3380 return;
3381
3382 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3383 &pool->cmd_buffers, pool_link) {
3384 radv_cmd_buffer_destroy(cmd_buffer);
3385 }
3386
3387 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3388 &pool->free_cmd_buffers, pool_link) {
3389 radv_cmd_buffer_destroy(cmd_buffer);
3390 }
3391
3392 vk_free2(&device->alloc, pAllocator, pool);
3393 }
3394
3395 VkResult radv_ResetCommandPool(
3396 VkDevice device,
3397 VkCommandPool commandPool,
3398 VkCommandPoolResetFlags flags)
3399 {
3400 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3401 VkResult result;
3402
3403 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3404 &pool->cmd_buffers, pool_link) {
3405 result = radv_reset_cmd_buffer(cmd_buffer);
3406 if (result != VK_SUCCESS)
3407 return result;
3408 }
3409
3410 return VK_SUCCESS;
3411 }
3412
3413 void radv_TrimCommandPool(
3414 VkDevice device,
3415 VkCommandPool commandPool,
3416 VkCommandPoolTrimFlags flags)
3417 {
3418 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3419
3420 if (!pool)
3421 return;
3422
3423 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3424 &pool->free_cmd_buffers, pool_link) {
3425 radv_cmd_buffer_destroy(cmd_buffer);
3426 }
3427 }
3428
3429 static uint32_t
3430 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3431 {
3432 struct radv_cmd_state *state = &cmd_buffer->state;
3433 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3434
3435 /* The id of this subpass shouldn't exceed the number of subpasses in
3436 * this render pass minus 1.
3437 */
3438 assert(subpass_id < state->pass->subpass_count);
3439 return subpass_id;
3440 }
3441
3442 static void
3443 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3444 uint32_t subpass_id)
3445 {
3446 struct radv_cmd_state *state = &cmd_buffer->state;
3447 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3448
3449 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3450 cmd_buffer->cs, 2048);
3451
3452 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3453
3454 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3455 const uint32_t a = subpass->attachments[i].attachment;
3456 if (a == VK_ATTACHMENT_UNUSED)
3457 continue;
3458
3459 radv_handle_subpass_image_transition(cmd_buffer,
3460 subpass->attachments[i]);
3461 }
3462
3463 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3464 radv_cmd_buffer_clear_subpass(cmd_buffer);
3465
3466 assert(cmd_buffer->cs->cdw <= cdw_max);
3467 }
3468
3469 static void
3470 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3471 {
3472 struct radv_cmd_state *state = &cmd_buffer->state;
3473 const struct radv_subpass *subpass = state->subpass;
3474 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3475
3476 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3477
3478 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3479 const uint32_t a = subpass->attachments[i].attachment;
3480 if (a == VK_ATTACHMENT_UNUSED)
3481 continue;
3482
3483 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3484 continue;
3485
3486 VkImageLayout layout = state->pass->attachments[a].final_layout;
3487 radv_handle_subpass_image_transition(cmd_buffer,
3488 (struct radv_subpass_attachment){a, layout});
3489 }
3490 }
3491
3492 void radv_CmdBeginRenderPass(
3493 VkCommandBuffer commandBuffer,
3494 const VkRenderPassBeginInfo* pRenderPassBegin,
3495 VkSubpassContents contents)
3496 {
3497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3498 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3499 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3500 VkResult result;
3501
3502 cmd_buffer->state.framebuffer = framebuffer;
3503 cmd_buffer->state.pass = pass;
3504 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3505
3506 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3507 if (result != VK_SUCCESS)
3508 return;
3509
3510 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3511 }
3512
3513 void radv_CmdBeginRenderPass2KHR(
3514 VkCommandBuffer commandBuffer,
3515 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3516 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3517 {
3518 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3519 pSubpassBeginInfo->contents);
3520 }
3521
3522 void radv_CmdNextSubpass(
3523 VkCommandBuffer commandBuffer,
3524 VkSubpassContents contents)
3525 {
3526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527
3528 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3529 radv_cmd_buffer_end_subpass(cmd_buffer);
3530 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3531 }
3532
3533 void radv_CmdNextSubpass2KHR(
3534 VkCommandBuffer commandBuffer,
3535 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3536 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3537 {
3538 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3539 }
3540
3541 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3542 {
3543 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3544 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3545 if (!radv_get_shader(pipeline, stage))
3546 continue;
3547
3548 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3549 if (loc->sgpr_idx == -1)
3550 continue;
3551 uint32_t base_reg = pipeline->user_data_0[stage];
3552 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3553
3554 }
3555 if (pipeline->gs_copy_shader) {
3556 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3557 if (loc->sgpr_idx != -1) {
3558 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3559 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3560 }
3561 }
3562 }
3563
3564 static void
3565 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3566 uint32_t vertex_count,
3567 bool use_opaque)
3568 {
3569 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3570 radeon_emit(cmd_buffer->cs, vertex_count);
3571 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3572 S_0287F0_USE_OPAQUE(use_opaque));
3573 }
3574
3575 static void
3576 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3577 uint64_t index_va,
3578 uint32_t index_count)
3579 {
3580 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3581 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3582 radeon_emit(cmd_buffer->cs, index_va);
3583 radeon_emit(cmd_buffer->cs, index_va >> 32);
3584 radeon_emit(cmd_buffer->cs, index_count);
3585 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3586 }
3587
3588 static void
3589 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3590 bool indexed,
3591 uint32_t draw_count,
3592 uint64_t count_va,
3593 uint32_t stride)
3594 {
3595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3596 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3597 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3598 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3599 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3600 bool predicating = cmd_buffer->state.predicating;
3601 assert(base_reg);
3602
3603 /* just reset draw state for vertex data */
3604 cmd_buffer->state.last_first_instance = -1;
3605 cmd_buffer->state.last_num_instances = -1;
3606 cmd_buffer->state.last_vertex_offset = -1;
3607
3608 if (draw_count == 1 && !count_va && !draw_id_enable) {
3609 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3610 PKT3_DRAW_INDIRECT, 3, predicating));
3611 radeon_emit(cs, 0);
3612 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3613 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3614 radeon_emit(cs, di_src_sel);
3615 } else {
3616 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3617 PKT3_DRAW_INDIRECT_MULTI,
3618 8, predicating));
3619 radeon_emit(cs, 0);
3620 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3621 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3622 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3623 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3624 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3625 radeon_emit(cs, draw_count); /* count */
3626 radeon_emit(cs, count_va); /* count_addr */
3627 radeon_emit(cs, count_va >> 32);
3628 radeon_emit(cs, stride); /* stride */
3629 radeon_emit(cs, di_src_sel);
3630 }
3631 }
3632
3633 static void
3634 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3635 const struct radv_draw_info *info)
3636 {
3637 struct radv_cmd_state *state = &cmd_buffer->state;
3638 struct radeon_winsys *ws = cmd_buffer->device->ws;
3639 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3640
3641 if (info->indirect) {
3642 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3643 uint64_t count_va = 0;
3644
3645 va += info->indirect->offset + info->indirect_offset;
3646
3647 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3648
3649 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3650 radeon_emit(cs, 1);
3651 radeon_emit(cs, va);
3652 radeon_emit(cs, va >> 32);
3653
3654 if (info->count_buffer) {
3655 count_va = radv_buffer_get_va(info->count_buffer->bo);
3656 count_va += info->count_buffer->offset +
3657 info->count_buffer_offset;
3658
3659 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3660 }
3661
3662 if (!state->subpass->view_mask) {
3663 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3664 info->indexed,
3665 info->count,
3666 count_va,
3667 info->stride);
3668 } else {
3669 unsigned i;
3670 for_each_bit(i, state->subpass->view_mask) {
3671 radv_emit_view_index(cmd_buffer, i);
3672
3673 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3674 info->indexed,
3675 info->count,
3676 count_va,
3677 info->stride);
3678 }
3679 }
3680 } else {
3681 assert(state->pipeline->graphics.vtx_base_sgpr);
3682
3683 if (info->vertex_offset != state->last_vertex_offset ||
3684 info->first_instance != state->last_first_instance) {
3685 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3686 state->pipeline->graphics.vtx_emit_num);
3687
3688 radeon_emit(cs, info->vertex_offset);
3689 radeon_emit(cs, info->first_instance);
3690 if (state->pipeline->graphics.vtx_emit_num == 3)
3691 radeon_emit(cs, 0);
3692 state->last_first_instance = info->first_instance;
3693 state->last_vertex_offset = info->vertex_offset;
3694 }
3695
3696 if (state->last_num_instances != info->instance_count) {
3697 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3698 radeon_emit(cs, info->instance_count);
3699 state->last_num_instances = info->instance_count;
3700 }
3701
3702 if (info->indexed) {
3703 int index_size = state->index_type ? 4 : 2;
3704 uint64_t index_va;
3705
3706 index_va = state->index_va;
3707 index_va += info->first_index * index_size;
3708
3709 if (!state->subpass->view_mask) {
3710 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3711 index_va,
3712 info->count);
3713 } else {
3714 unsigned i;
3715 for_each_bit(i, state->subpass->view_mask) {
3716 radv_emit_view_index(cmd_buffer, i);
3717
3718 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3719 index_va,
3720 info->count);
3721 }
3722 }
3723 } else {
3724 if (!state->subpass->view_mask) {
3725 radv_cs_emit_draw_packet(cmd_buffer,
3726 info->count,
3727 !!info->strmout_buffer);
3728 } else {
3729 unsigned i;
3730 for_each_bit(i, state->subpass->view_mask) {
3731 radv_emit_view_index(cmd_buffer, i);
3732
3733 radv_cs_emit_draw_packet(cmd_buffer,
3734 info->count,
3735 !!info->strmout_buffer);
3736 }
3737 }
3738 }
3739 }
3740 }
3741
3742 /*
3743 * Vega and raven have a bug which triggers if there are multiple context
3744 * register contexts active at the same time with different scissor values.
3745 *
3746 * There are two possible workarounds:
3747 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3748 * there is only ever 1 active set of scissor values at the same time.
3749 *
3750 * 2) Whenever the hardware switches contexts we have to set the scissor
3751 * registers again even if it is a noop. That way the new context gets
3752 * the correct scissor values.
3753 *
3754 * This implements option 2. radv_need_late_scissor_emission needs to
3755 * return true on affected HW if radv_emit_all_graphics_states sets
3756 * any context registers.
3757 */
3758 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3759 const struct radv_draw_info *info)
3760 {
3761 struct radv_cmd_state *state = &cmd_buffer->state;
3762
3763 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3764 return false;
3765
3766 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3767 return true;
3768
3769 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3770
3771 /* Index, vertex and streamout buffers don't change context regs, and
3772 * pipeline is already handled.
3773 */
3774 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3775 RADV_CMD_DIRTY_VERTEX_BUFFER |
3776 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3777 RADV_CMD_DIRTY_PIPELINE);
3778
3779 if (cmd_buffer->state.dirty & used_states)
3780 return true;
3781
3782 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3783 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3784 return true;
3785
3786 return false;
3787 }
3788
3789 static void
3790 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3791 const struct radv_draw_info *info)
3792 {
3793 bool late_scissor_emission;
3794
3795 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3796 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3797 radv_emit_rbplus_state(cmd_buffer);
3798
3799 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3800 radv_emit_graphics_pipeline(cmd_buffer);
3801
3802 /* This should be before the cmd_buffer->state.dirty is cleared
3803 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3804 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3805 late_scissor_emission =
3806 radv_need_late_scissor_emission(cmd_buffer, info);
3807
3808 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3809 radv_emit_framebuffer_state(cmd_buffer);
3810
3811 if (info->indexed) {
3812 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3813 radv_emit_index_buffer(cmd_buffer);
3814 } else {
3815 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3816 * so the state must be re-emitted before the next indexed
3817 * draw.
3818 */
3819 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3820 cmd_buffer->state.last_index_type = -1;
3821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3822 }
3823 }
3824
3825 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3826
3827 radv_emit_draw_registers(cmd_buffer, info);
3828
3829 if (late_scissor_emission)
3830 radv_emit_scissor(cmd_buffer);
3831 }
3832
3833 static void
3834 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3835 const struct radv_draw_info *info)
3836 {
3837 struct radeon_info *rad_info =
3838 &cmd_buffer->device->physical_device->rad_info;
3839 bool has_prefetch =
3840 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3841 bool pipeline_is_dirty =
3842 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3843 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3844
3845 MAYBE_UNUSED unsigned cdw_max =
3846 radeon_check_space(cmd_buffer->device->ws,
3847 cmd_buffer->cs, 4096);
3848
3849 if (likely(!info->indirect)) {
3850 /* SI-CI treat instance_count==0 as instance_count==1. There is
3851 * no workaround for indirect draws, but we can at least skip
3852 * direct draws.
3853 */
3854 if (unlikely(!info->instance_count))
3855 return;
3856
3857 /* Handle count == 0. */
3858 if (unlikely(!info->count && !info->strmout_buffer))
3859 return;
3860 }
3861
3862 /* Use optimal packet order based on whether we need to sync the
3863 * pipeline.
3864 */
3865 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3866 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3867 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3868 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3869 /* If we have to wait for idle, set all states first, so that
3870 * all SET packets are processed in parallel with previous draw
3871 * calls. Then upload descriptors, set shader pointers, and
3872 * draw, and prefetch at the end. This ensures that the time
3873 * the CUs are idle is very short. (there are only SET_SH
3874 * packets between the wait and the draw)
3875 */
3876 radv_emit_all_graphics_states(cmd_buffer, info);
3877 si_emit_cache_flush(cmd_buffer);
3878 /* <-- CUs are idle here --> */
3879
3880 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3881
3882 radv_emit_draw_packets(cmd_buffer, info);
3883 /* <-- CUs are busy here --> */
3884
3885 /* Start prefetches after the draw has been started. Both will
3886 * run in parallel, but starting the draw first is more
3887 * important.
3888 */
3889 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3890 radv_emit_prefetch_L2(cmd_buffer,
3891 cmd_buffer->state.pipeline, false);
3892 }
3893 } else {
3894 /* If we don't wait for idle, start prefetches first, then set
3895 * states, and draw at the end.
3896 */
3897 si_emit_cache_flush(cmd_buffer);
3898
3899 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3900 /* Only prefetch the vertex shader and VBO descriptors
3901 * in order to start the draw as soon as possible.
3902 */
3903 radv_emit_prefetch_L2(cmd_buffer,
3904 cmd_buffer->state.pipeline, true);
3905 }
3906
3907 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3908
3909 radv_emit_all_graphics_states(cmd_buffer, info);
3910 radv_emit_draw_packets(cmd_buffer, info);
3911
3912 /* Prefetch the remaining shaders after the draw has been
3913 * started.
3914 */
3915 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3916 radv_emit_prefetch_L2(cmd_buffer,
3917 cmd_buffer->state.pipeline, false);
3918 }
3919 }
3920
3921 /* Workaround for a VGT hang when streamout is enabled.
3922 * It must be done after drawing.
3923 */
3924 if (cmd_buffer->state.streamout.streamout_enabled &&
3925 (rad_info->family == CHIP_HAWAII ||
3926 rad_info->family == CHIP_TONGA ||
3927 rad_info->family == CHIP_FIJI)) {
3928 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3929 }
3930
3931 assert(cmd_buffer->cs->cdw <= cdw_max);
3932 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3933 }
3934
3935 void radv_CmdDraw(
3936 VkCommandBuffer commandBuffer,
3937 uint32_t vertexCount,
3938 uint32_t instanceCount,
3939 uint32_t firstVertex,
3940 uint32_t firstInstance)
3941 {
3942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3943 struct radv_draw_info info = {};
3944
3945 info.count = vertexCount;
3946 info.instance_count = instanceCount;
3947 info.first_instance = firstInstance;
3948 info.vertex_offset = firstVertex;
3949
3950 radv_draw(cmd_buffer, &info);
3951 }
3952
3953 void radv_CmdDrawIndexed(
3954 VkCommandBuffer commandBuffer,
3955 uint32_t indexCount,
3956 uint32_t instanceCount,
3957 uint32_t firstIndex,
3958 int32_t vertexOffset,
3959 uint32_t firstInstance)
3960 {
3961 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3962 struct radv_draw_info info = {};
3963
3964 info.indexed = true;
3965 info.count = indexCount;
3966 info.instance_count = instanceCount;
3967 info.first_index = firstIndex;
3968 info.vertex_offset = vertexOffset;
3969 info.first_instance = firstInstance;
3970
3971 radv_draw(cmd_buffer, &info);
3972 }
3973
3974 void radv_CmdDrawIndirect(
3975 VkCommandBuffer commandBuffer,
3976 VkBuffer _buffer,
3977 VkDeviceSize offset,
3978 uint32_t drawCount,
3979 uint32_t stride)
3980 {
3981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3982 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3983 struct radv_draw_info info = {};
3984
3985 info.count = drawCount;
3986 info.indirect = buffer;
3987 info.indirect_offset = offset;
3988 info.stride = stride;
3989
3990 radv_draw(cmd_buffer, &info);
3991 }
3992
3993 void radv_CmdDrawIndexedIndirect(
3994 VkCommandBuffer commandBuffer,
3995 VkBuffer _buffer,
3996 VkDeviceSize offset,
3997 uint32_t drawCount,
3998 uint32_t stride)
3999 {
4000 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4001 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4002 struct radv_draw_info info = {};
4003
4004 info.indexed = true;
4005 info.count = drawCount;
4006 info.indirect = buffer;
4007 info.indirect_offset = offset;
4008 info.stride = stride;
4009
4010 radv_draw(cmd_buffer, &info);
4011 }
4012
4013 void radv_CmdDrawIndirectCountAMD(
4014 VkCommandBuffer commandBuffer,
4015 VkBuffer _buffer,
4016 VkDeviceSize offset,
4017 VkBuffer _countBuffer,
4018 VkDeviceSize countBufferOffset,
4019 uint32_t maxDrawCount,
4020 uint32_t stride)
4021 {
4022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4023 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4024 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4025 struct radv_draw_info info = {};
4026
4027 info.count = maxDrawCount;
4028 info.indirect = buffer;
4029 info.indirect_offset = offset;
4030 info.count_buffer = count_buffer;
4031 info.count_buffer_offset = countBufferOffset;
4032 info.stride = stride;
4033
4034 radv_draw(cmd_buffer, &info);
4035 }
4036
4037 void radv_CmdDrawIndexedIndirectCountAMD(
4038 VkCommandBuffer commandBuffer,
4039 VkBuffer _buffer,
4040 VkDeviceSize offset,
4041 VkBuffer _countBuffer,
4042 VkDeviceSize countBufferOffset,
4043 uint32_t maxDrawCount,
4044 uint32_t stride)
4045 {
4046 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4047 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4048 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4049 struct radv_draw_info info = {};
4050
4051 info.indexed = true;
4052 info.count = maxDrawCount;
4053 info.indirect = buffer;
4054 info.indirect_offset = offset;
4055 info.count_buffer = count_buffer;
4056 info.count_buffer_offset = countBufferOffset;
4057 info.stride = stride;
4058
4059 radv_draw(cmd_buffer, &info);
4060 }
4061
4062 void radv_CmdDrawIndirectCountKHR(
4063 VkCommandBuffer commandBuffer,
4064 VkBuffer _buffer,
4065 VkDeviceSize offset,
4066 VkBuffer _countBuffer,
4067 VkDeviceSize countBufferOffset,
4068 uint32_t maxDrawCount,
4069 uint32_t stride)
4070 {
4071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4072 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4073 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4074 struct radv_draw_info info = {};
4075
4076 info.count = maxDrawCount;
4077 info.indirect = buffer;
4078 info.indirect_offset = offset;
4079 info.count_buffer = count_buffer;
4080 info.count_buffer_offset = countBufferOffset;
4081 info.stride = stride;
4082
4083 radv_draw(cmd_buffer, &info);
4084 }
4085
4086 void radv_CmdDrawIndexedIndirectCountKHR(
4087 VkCommandBuffer commandBuffer,
4088 VkBuffer _buffer,
4089 VkDeviceSize offset,
4090 VkBuffer _countBuffer,
4091 VkDeviceSize countBufferOffset,
4092 uint32_t maxDrawCount,
4093 uint32_t stride)
4094 {
4095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4096 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4097 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4098 struct radv_draw_info info = {};
4099
4100 info.indexed = true;
4101 info.count = maxDrawCount;
4102 info.indirect = buffer;
4103 info.indirect_offset = offset;
4104 info.count_buffer = count_buffer;
4105 info.count_buffer_offset = countBufferOffset;
4106 info.stride = stride;
4107
4108 radv_draw(cmd_buffer, &info);
4109 }
4110
4111 struct radv_dispatch_info {
4112 /**
4113 * Determine the layout of the grid (in block units) to be used.
4114 */
4115 uint32_t blocks[3];
4116
4117 /**
4118 * A starting offset for the grid. If unaligned is set, the offset
4119 * must still be aligned.
4120 */
4121 uint32_t offsets[3];
4122 /**
4123 * Whether it's an unaligned compute dispatch.
4124 */
4125 bool unaligned;
4126
4127 /**
4128 * Indirect compute parameters resource.
4129 */
4130 struct radv_buffer *indirect;
4131 uint64_t indirect_offset;
4132 };
4133
4134 static void
4135 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4136 const struct radv_dispatch_info *info)
4137 {
4138 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4139 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4140 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4141 struct radeon_winsys *ws = cmd_buffer->device->ws;
4142 bool predicating = cmd_buffer->state.predicating;
4143 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4144 struct radv_userdata_info *loc;
4145
4146 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4147 AC_UD_CS_GRID_SIZE);
4148
4149 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4150
4151 if (info->indirect) {
4152 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4153
4154 va += info->indirect->offset + info->indirect_offset;
4155
4156 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4157
4158 if (loc->sgpr_idx != -1) {
4159 for (unsigned i = 0; i < 3; ++i) {
4160 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4161 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4162 COPY_DATA_DST_SEL(COPY_DATA_REG));
4163 radeon_emit(cs, (va + 4 * i));
4164 radeon_emit(cs, (va + 4 * i) >> 32);
4165 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4166 + loc->sgpr_idx * 4) >> 2) + i);
4167 radeon_emit(cs, 0);
4168 }
4169 }
4170
4171 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4172 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4173 PKT3_SHADER_TYPE_S(1));
4174 radeon_emit(cs, va);
4175 radeon_emit(cs, va >> 32);
4176 radeon_emit(cs, dispatch_initiator);
4177 } else {
4178 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4179 PKT3_SHADER_TYPE_S(1));
4180 radeon_emit(cs, 1);
4181 radeon_emit(cs, va);
4182 radeon_emit(cs, va >> 32);
4183
4184 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4185 PKT3_SHADER_TYPE_S(1));
4186 radeon_emit(cs, 0);
4187 radeon_emit(cs, dispatch_initiator);
4188 }
4189 } else {
4190 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4191 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4192
4193 if (info->unaligned) {
4194 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4195 unsigned remainder[3];
4196
4197 /* If aligned, these should be an entire block size,
4198 * not 0.
4199 */
4200 remainder[0] = blocks[0] + cs_block_size[0] -
4201 align_u32_npot(blocks[0], cs_block_size[0]);
4202 remainder[1] = blocks[1] + cs_block_size[1] -
4203 align_u32_npot(blocks[1], cs_block_size[1]);
4204 remainder[2] = blocks[2] + cs_block_size[2] -
4205 align_u32_npot(blocks[2], cs_block_size[2]);
4206
4207 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4208 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4209 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4210
4211 for(unsigned i = 0; i < 3; ++i) {
4212 assert(offsets[i] % cs_block_size[i] == 0);
4213 offsets[i] /= cs_block_size[i];
4214 }
4215
4216 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4217 radeon_emit(cs,
4218 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4219 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4220 radeon_emit(cs,
4221 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4222 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4223 radeon_emit(cs,
4224 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4225 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4226
4227 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4228 }
4229
4230 if (loc->sgpr_idx != -1) {
4231 assert(loc->num_sgprs == 3);
4232
4233 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4234 loc->sgpr_idx * 4, 3);
4235 radeon_emit(cs, blocks[0]);
4236 radeon_emit(cs, blocks[1]);
4237 radeon_emit(cs, blocks[2]);
4238 }
4239
4240 if (offsets[0] || offsets[1] || offsets[2]) {
4241 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4242 radeon_emit(cs, offsets[0]);
4243 radeon_emit(cs, offsets[1]);
4244 radeon_emit(cs, offsets[2]);
4245
4246 /* The blocks in the packet are not counts but end values. */
4247 for (unsigned i = 0; i < 3; ++i)
4248 blocks[i] += offsets[i];
4249 } else {
4250 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4251 }
4252
4253 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4254 PKT3_SHADER_TYPE_S(1));
4255 radeon_emit(cs, blocks[0]);
4256 radeon_emit(cs, blocks[1]);
4257 radeon_emit(cs, blocks[2]);
4258 radeon_emit(cs, dispatch_initiator);
4259 }
4260
4261 assert(cmd_buffer->cs->cdw <= cdw_max);
4262 }
4263
4264 static void
4265 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4266 {
4267 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4268 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4269 }
4270
4271 static void
4272 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4273 const struct radv_dispatch_info *info)
4274 {
4275 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4276 bool has_prefetch =
4277 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4278 bool pipeline_is_dirty = pipeline &&
4279 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4280
4281 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4282 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4283 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4284 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4285 /* If we have to wait for idle, set all states first, so that
4286 * all SET packets are processed in parallel with previous draw
4287 * calls. Then upload descriptors, set shader pointers, and
4288 * dispatch, and prefetch at the end. This ensures that the
4289 * time the CUs are idle is very short. (there are only SET_SH
4290 * packets between the wait and the draw)
4291 */
4292 radv_emit_compute_pipeline(cmd_buffer);
4293 si_emit_cache_flush(cmd_buffer);
4294 /* <-- CUs are idle here --> */
4295
4296 radv_upload_compute_shader_descriptors(cmd_buffer);
4297
4298 radv_emit_dispatch_packets(cmd_buffer, info);
4299 /* <-- CUs are busy here --> */
4300
4301 /* Start prefetches after the dispatch has been started. Both
4302 * will run in parallel, but starting the dispatch first is
4303 * more important.
4304 */
4305 if (has_prefetch && pipeline_is_dirty) {
4306 radv_emit_shader_prefetch(cmd_buffer,
4307 pipeline->shaders[MESA_SHADER_COMPUTE]);
4308 }
4309 } else {
4310 /* If we don't wait for idle, start prefetches first, then set
4311 * states, and dispatch at the end.
4312 */
4313 si_emit_cache_flush(cmd_buffer);
4314
4315 if (has_prefetch && pipeline_is_dirty) {
4316 radv_emit_shader_prefetch(cmd_buffer,
4317 pipeline->shaders[MESA_SHADER_COMPUTE]);
4318 }
4319
4320 radv_upload_compute_shader_descriptors(cmd_buffer);
4321
4322 radv_emit_compute_pipeline(cmd_buffer);
4323 radv_emit_dispatch_packets(cmd_buffer, info);
4324 }
4325
4326 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4327 }
4328
4329 void radv_CmdDispatchBase(
4330 VkCommandBuffer commandBuffer,
4331 uint32_t base_x,
4332 uint32_t base_y,
4333 uint32_t base_z,
4334 uint32_t x,
4335 uint32_t y,
4336 uint32_t z)
4337 {
4338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4339 struct radv_dispatch_info info = {};
4340
4341 info.blocks[0] = x;
4342 info.blocks[1] = y;
4343 info.blocks[2] = z;
4344
4345 info.offsets[0] = base_x;
4346 info.offsets[1] = base_y;
4347 info.offsets[2] = base_z;
4348 radv_dispatch(cmd_buffer, &info);
4349 }
4350
4351 void radv_CmdDispatch(
4352 VkCommandBuffer commandBuffer,
4353 uint32_t x,
4354 uint32_t y,
4355 uint32_t z)
4356 {
4357 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4358 }
4359
4360 void radv_CmdDispatchIndirect(
4361 VkCommandBuffer commandBuffer,
4362 VkBuffer _buffer,
4363 VkDeviceSize offset)
4364 {
4365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4366 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4367 struct radv_dispatch_info info = {};
4368
4369 info.indirect = buffer;
4370 info.indirect_offset = offset;
4371
4372 radv_dispatch(cmd_buffer, &info);
4373 }
4374
4375 void radv_unaligned_dispatch(
4376 struct radv_cmd_buffer *cmd_buffer,
4377 uint32_t x,
4378 uint32_t y,
4379 uint32_t z)
4380 {
4381 struct radv_dispatch_info info = {};
4382
4383 info.blocks[0] = x;
4384 info.blocks[1] = y;
4385 info.blocks[2] = z;
4386 info.unaligned = 1;
4387
4388 radv_dispatch(cmd_buffer, &info);
4389 }
4390
4391 void radv_CmdEndRenderPass(
4392 VkCommandBuffer commandBuffer)
4393 {
4394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4395
4396 radv_cmd_buffer_end_subpass(cmd_buffer);
4397
4398 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4399
4400 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4401
4402 cmd_buffer->state.pass = NULL;
4403 cmd_buffer->state.subpass = NULL;
4404 cmd_buffer->state.attachments = NULL;
4405 cmd_buffer->state.framebuffer = NULL;
4406 }
4407
4408 void radv_CmdEndRenderPass2KHR(
4409 VkCommandBuffer commandBuffer,
4410 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4411 {
4412 radv_CmdEndRenderPass(commandBuffer);
4413 }
4414
4415 /*
4416 * For HTILE we have the following interesting clear words:
4417 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4418 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4419 * 0xfffffff0: Clear depth to 1.0
4420 * 0x00000000: Clear depth to 0.0
4421 */
4422 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4423 struct radv_image *image,
4424 const VkImageSubresourceRange *range,
4425 uint32_t clear_word)
4426 {
4427 assert(range->baseMipLevel == 0);
4428 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4429 unsigned layer_count = radv_get_layerCount(image, range);
4430 uint64_t size = image->surface.htile_slice_size * layer_count;
4431 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4432 uint64_t offset = image->offset + image->htile_offset +
4433 image->surface.htile_slice_size * range->baseArrayLayer;
4434 struct radv_cmd_state *state = &cmd_buffer->state;
4435 VkClearDepthStencilValue value = {};
4436
4437 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4438 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4439
4440 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4441 size, clear_word);
4442
4443 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4444
4445 if (vk_format_is_stencil(image->vk_format))
4446 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4447
4448 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4449
4450 if (radv_image_is_tc_compat_htile(image)) {
4451 /* Initialize the TC-compat metada value to 0 because by
4452 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4453 * need have to conditionally update its value when performing
4454 * a fast depth clear.
4455 */
4456 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4457 }
4458 }
4459
4460 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4461 struct radv_image *image,
4462 VkImageLayout src_layout,
4463 VkImageLayout dst_layout,
4464 unsigned src_queue_mask,
4465 unsigned dst_queue_mask,
4466 const VkImageSubresourceRange *range)
4467 {
4468 if (!radv_image_has_htile(image))
4469 return;
4470
4471 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4472 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4473 /* TODO: merge with the clear if applicable */
4474 radv_initialize_htile(cmd_buffer, image, range, 0);
4475 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4476 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4477 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4478 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4479 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4480 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4481 VkImageSubresourceRange local_range = *range;
4482 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4483 local_range.baseMipLevel = 0;
4484 local_range.levelCount = 1;
4485
4486 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4487 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4488
4489 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4490
4491 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4492 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4493 }
4494 }
4495
4496 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4497 struct radv_image *image, uint32_t value)
4498 {
4499 struct radv_cmd_state *state = &cmd_buffer->state;
4500
4501 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4502 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4503
4504 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4505
4506 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4507 }
4508
4509 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4510 struct radv_image *image)
4511 {
4512 struct radv_cmd_state *state = &cmd_buffer->state;
4513 static const uint32_t fmask_clear_values[4] = {
4514 0x00000000,
4515 0x02020202,
4516 0xE4E4E4E4,
4517 0x76543210
4518 };
4519 uint32_t log2_samples = util_logbase2(image->info.samples);
4520 uint32_t value = fmask_clear_values[log2_samples];
4521
4522 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4523 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4524
4525 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4526
4527 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4528 }
4529
4530 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4531 struct radv_image *image, uint32_t value)
4532 {
4533 struct radv_cmd_state *state = &cmd_buffer->state;
4534
4535 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4536 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4537
4538 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4539
4540 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4541 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4542 }
4543
4544 /**
4545 * Initialize DCC/FMASK/CMASK metadata for a color image.
4546 */
4547 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4548 struct radv_image *image,
4549 VkImageLayout src_layout,
4550 VkImageLayout dst_layout,
4551 unsigned src_queue_mask,
4552 unsigned dst_queue_mask)
4553 {
4554 if (radv_image_has_cmask(image)) {
4555 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4556
4557 /* TODO: clarify this. */
4558 if (radv_image_has_fmask(image)) {
4559 value = 0xccccccccu;
4560 }
4561
4562 radv_initialise_cmask(cmd_buffer, image, value);
4563 }
4564
4565 if (radv_image_has_fmask(image)) {
4566 radv_initialize_fmask(cmd_buffer, image);
4567 }
4568
4569 if (radv_image_has_dcc(image)) {
4570 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4571 bool need_decompress_pass = false;
4572
4573 if (radv_layout_dcc_compressed(image, dst_layout,
4574 dst_queue_mask)) {
4575 value = 0x20202020u;
4576 need_decompress_pass = true;
4577 }
4578
4579 radv_initialize_dcc(cmd_buffer, image, value);
4580
4581 radv_update_fce_metadata(cmd_buffer, image,
4582 need_decompress_pass);
4583 }
4584
4585 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4586 uint32_t color_values[2] = {};
4587 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4588 }
4589 }
4590
4591 /**
4592 * Handle color image transitions for DCC/FMASK/CMASK.
4593 */
4594 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4595 struct radv_image *image,
4596 VkImageLayout src_layout,
4597 VkImageLayout dst_layout,
4598 unsigned src_queue_mask,
4599 unsigned dst_queue_mask,
4600 const VkImageSubresourceRange *range)
4601 {
4602 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4603 radv_init_color_image_metadata(cmd_buffer, image,
4604 src_layout, dst_layout,
4605 src_queue_mask, dst_queue_mask);
4606 return;
4607 }
4608
4609 if (radv_image_has_dcc(image)) {
4610 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4611 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4612 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4613 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4614 radv_decompress_dcc(cmd_buffer, image, range);
4615 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4616 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4617 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4618 }
4619 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4620 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4621 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4622 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4623 }
4624
4625 if (radv_image_has_fmask(image)) {
4626 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4627 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4628 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4629 }
4630 }
4631 }
4632 }
4633
4634 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4635 struct radv_image *image,
4636 VkImageLayout src_layout,
4637 VkImageLayout dst_layout,
4638 uint32_t src_family,
4639 uint32_t dst_family,
4640 const VkImageSubresourceRange *range)
4641 {
4642 if (image->exclusive && src_family != dst_family) {
4643 /* This is an acquire or a release operation and there will be
4644 * a corresponding release/acquire. Do the transition in the
4645 * most flexible queue. */
4646
4647 assert(src_family == cmd_buffer->queue_family_index ||
4648 dst_family == cmd_buffer->queue_family_index);
4649
4650 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4651 return;
4652
4653 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4654 (src_family == RADV_QUEUE_GENERAL ||
4655 dst_family == RADV_QUEUE_GENERAL))
4656 return;
4657 }
4658
4659 if (src_layout == dst_layout)
4660 return;
4661
4662 unsigned src_queue_mask =
4663 radv_image_queue_family_mask(image, src_family,
4664 cmd_buffer->queue_family_index);
4665 unsigned dst_queue_mask =
4666 radv_image_queue_family_mask(image, dst_family,
4667 cmd_buffer->queue_family_index);
4668
4669 if (vk_format_is_depth(image->vk_format)) {
4670 radv_handle_depth_image_transition(cmd_buffer, image,
4671 src_layout, dst_layout,
4672 src_queue_mask, dst_queue_mask,
4673 range);
4674 } else {
4675 radv_handle_color_image_transition(cmd_buffer, image,
4676 src_layout, dst_layout,
4677 src_queue_mask, dst_queue_mask,
4678 range);
4679 }
4680 }
4681
4682 struct radv_barrier_info {
4683 uint32_t eventCount;
4684 const VkEvent *pEvents;
4685 VkPipelineStageFlags srcStageMask;
4686 VkPipelineStageFlags dstStageMask;
4687 };
4688
4689 static void
4690 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4691 uint32_t memoryBarrierCount,
4692 const VkMemoryBarrier *pMemoryBarriers,
4693 uint32_t bufferMemoryBarrierCount,
4694 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4695 uint32_t imageMemoryBarrierCount,
4696 const VkImageMemoryBarrier *pImageMemoryBarriers,
4697 const struct radv_barrier_info *info)
4698 {
4699 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4700 enum radv_cmd_flush_bits src_flush_bits = 0;
4701 enum radv_cmd_flush_bits dst_flush_bits = 0;
4702
4703 for (unsigned i = 0; i < info->eventCount; ++i) {
4704 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4705 uint64_t va = radv_buffer_get_va(event->bo);
4706
4707 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4708
4709 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4710
4711 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4712 assert(cmd_buffer->cs->cdw <= cdw_max);
4713 }
4714
4715 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4716 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4717 NULL);
4718 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4719 NULL);
4720 }
4721
4722 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4723 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4724 NULL);
4725 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4726 NULL);
4727 }
4728
4729 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4730 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4731
4732 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4733 image);
4734 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4735 image);
4736 }
4737
4738 /* The Vulkan spec 1.1.98 says:
4739 *
4740 * "An execution dependency with only
4741 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4742 * will only prevent that stage from executing in subsequently
4743 * submitted commands. As this stage does not perform any actual
4744 * execution, this is not observable - in effect, it does not delay
4745 * processing of subsequent commands. Similarly an execution dependency
4746 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4747 * will effectively not wait for any prior commands to complete."
4748 */
4749 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4750 radv_stage_flush(cmd_buffer, info->srcStageMask);
4751 cmd_buffer->state.flush_bits |= src_flush_bits;
4752
4753 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4754 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4755 radv_handle_image_transition(cmd_buffer, image,
4756 pImageMemoryBarriers[i].oldLayout,
4757 pImageMemoryBarriers[i].newLayout,
4758 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4759 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4760 &pImageMemoryBarriers[i].subresourceRange);
4761 }
4762
4763 /* Make sure CP DMA is idle because the driver might have performed a
4764 * DMA operation for copying or filling buffers/images.
4765 */
4766 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4767 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4768 si_cp_dma_wait_for_idle(cmd_buffer);
4769
4770 cmd_buffer->state.flush_bits |= dst_flush_bits;
4771 }
4772
4773 void radv_CmdPipelineBarrier(
4774 VkCommandBuffer commandBuffer,
4775 VkPipelineStageFlags srcStageMask,
4776 VkPipelineStageFlags destStageMask,
4777 VkBool32 byRegion,
4778 uint32_t memoryBarrierCount,
4779 const VkMemoryBarrier* pMemoryBarriers,
4780 uint32_t bufferMemoryBarrierCount,
4781 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4782 uint32_t imageMemoryBarrierCount,
4783 const VkImageMemoryBarrier* pImageMemoryBarriers)
4784 {
4785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4786 struct radv_barrier_info info;
4787
4788 info.eventCount = 0;
4789 info.pEvents = NULL;
4790 info.srcStageMask = srcStageMask;
4791 info.dstStageMask = destStageMask;
4792
4793 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4794 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4795 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4796 }
4797
4798
4799 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4800 struct radv_event *event,
4801 VkPipelineStageFlags stageMask,
4802 unsigned value)
4803 {
4804 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4805 uint64_t va = radv_buffer_get_va(event->bo);
4806
4807 si_emit_cache_flush(cmd_buffer);
4808
4809 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4810
4811 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4812
4813 /* Flags that only require a top-of-pipe event. */
4814 VkPipelineStageFlags top_of_pipe_flags =
4815 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4816
4817 /* Flags that only require a post-index-fetch event. */
4818 VkPipelineStageFlags post_index_fetch_flags =
4819 top_of_pipe_flags |
4820 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4821 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4822
4823 /* Make sure CP DMA is idle because the driver might have performed a
4824 * DMA operation for copying or filling buffers/images.
4825 */
4826 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4827 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4828 si_cp_dma_wait_for_idle(cmd_buffer);
4829
4830 /* TODO: Emit EOS events for syncing PS/CS stages. */
4831
4832 if (!(stageMask & ~top_of_pipe_flags)) {
4833 /* Just need to sync the PFP engine. */
4834 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4835 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4836 S_370_WR_CONFIRM(1) |
4837 S_370_ENGINE_SEL(V_370_PFP));
4838 radeon_emit(cs, va);
4839 radeon_emit(cs, va >> 32);
4840 radeon_emit(cs, value);
4841 } else if (!(stageMask & ~post_index_fetch_flags)) {
4842 /* Sync ME because PFP reads index and indirect buffers. */
4843 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4844 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4845 S_370_WR_CONFIRM(1) |
4846 S_370_ENGINE_SEL(V_370_ME));
4847 radeon_emit(cs, va);
4848 radeon_emit(cs, va >> 32);
4849 radeon_emit(cs, value);
4850 } else {
4851 /* Otherwise, sync all prior GPU work using an EOP event. */
4852 si_cs_emit_write_event_eop(cs,
4853 cmd_buffer->device->physical_device->rad_info.chip_class,
4854 radv_cmd_buffer_uses_mec(cmd_buffer),
4855 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4856 EOP_DATA_SEL_VALUE_32BIT, va, value,
4857 cmd_buffer->gfx9_eop_bug_va);
4858 }
4859
4860 assert(cmd_buffer->cs->cdw <= cdw_max);
4861 }
4862
4863 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4864 VkEvent _event,
4865 VkPipelineStageFlags stageMask)
4866 {
4867 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4868 RADV_FROM_HANDLE(radv_event, event, _event);
4869
4870 write_event(cmd_buffer, event, stageMask, 1);
4871 }
4872
4873 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4874 VkEvent _event,
4875 VkPipelineStageFlags stageMask)
4876 {
4877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4878 RADV_FROM_HANDLE(radv_event, event, _event);
4879
4880 write_event(cmd_buffer, event, stageMask, 0);
4881 }
4882
4883 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4884 uint32_t eventCount,
4885 const VkEvent* pEvents,
4886 VkPipelineStageFlags srcStageMask,
4887 VkPipelineStageFlags dstStageMask,
4888 uint32_t memoryBarrierCount,
4889 const VkMemoryBarrier* pMemoryBarriers,
4890 uint32_t bufferMemoryBarrierCount,
4891 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4892 uint32_t imageMemoryBarrierCount,
4893 const VkImageMemoryBarrier* pImageMemoryBarriers)
4894 {
4895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4896 struct radv_barrier_info info;
4897
4898 info.eventCount = eventCount;
4899 info.pEvents = pEvents;
4900 info.srcStageMask = 0;
4901
4902 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4903 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4904 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4905 }
4906
4907
4908 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4909 uint32_t deviceMask)
4910 {
4911 /* No-op */
4912 }
4913
4914 /* VK_EXT_conditional_rendering */
4915 void radv_CmdBeginConditionalRenderingEXT(
4916 VkCommandBuffer commandBuffer,
4917 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4918 {
4919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4920 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4921 bool draw_visible = true;
4922 uint64_t va;
4923
4924 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4925
4926 /* By default, if the 32-bit value at offset in buffer memory is zero,
4927 * then the rendering commands are discarded, otherwise they are
4928 * executed as normal. If the inverted flag is set, all commands are
4929 * discarded if the value is non zero.
4930 */
4931 if (pConditionalRenderingBegin->flags &
4932 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4933 draw_visible = false;
4934 }
4935
4936 si_emit_cache_flush(cmd_buffer);
4937
4938 /* Enable predication for this command buffer. */
4939 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4940 cmd_buffer->state.predicating = true;
4941
4942 /* Store conditional rendering user info. */
4943 cmd_buffer->state.predication_type = draw_visible;
4944 cmd_buffer->state.predication_va = va;
4945 }
4946
4947 void radv_CmdEndConditionalRenderingEXT(
4948 VkCommandBuffer commandBuffer)
4949 {
4950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4951
4952 /* Disable predication for this command buffer. */
4953 si_emit_set_predication_state(cmd_buffer, false, 0);
4954 cmd_buffer->state.predicating = false;
4955
4956 /* Reset conditional rendering user info. */
4957 cmd_buffer->state.predication_type = -1;
4958 cmd_buffer->state.predication_va = 0;
4959 }
4960
4961 /* VK_EXT_transform_feedback */
4962 void radv_CmdBindTransformFeedbackBuffersEXT(
4963 VkCommandBuffer commandBuffer,
4964 uint32_t firstBinding,
4965 uint32_t bindingCount,
4966 const VkBuffer* pBuffers,
4967 const VkDeviceSize* pOffsets,
4968 const VkDeviceSize* pSizes)
4969 {
4970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4971 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4972 uint8_t enabled_mask = 0;
4973
4974 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4975 for (uint32_t i = 0; i < bindingCount; i++) {
4976 uint32_t idx = firstBinding + i;
4977
4978 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4979 sb[idx].offset = pOffsets[i];
4980 sb[idx].size = pSizes[i];
4981
4982 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4983 sb[idx].buffer->bo);
4984
4985 enabled_mask |= 1 << idx;
4986 }
4987
4988 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4989
4990 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4991 }
4992
4993 static void
4994 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4995 {
4996 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4997 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4998
4999 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5000 radeon_emit(cs,
5001 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5002 S_028B94_RAST_STREAM(0) |
5003 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5004 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5005 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5006 radeon_emit(cs, so->hw_enabled_mask &
5007 so->enabled_stream_buffers_mask);
5008
5009 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5010 }
5011
5012 static void
5013 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5014 {
5015 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5016 bool old_streamout_enabled = so->streamout_enabled;
5017 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5018
5019 so->streamout_enabled = enable;
5020
5021 so->hw_enabled_mask = so->enabled_mask |
5022 (so->enabled_mask << 4) |
5023 (so->enabled_mask << 8) |
5024 (so->enabled_mask << 12);
5025
5026 if ((old_streamout_enabled != so->streamout_enabled) ||
5027 (old_hw_enabled_mask != so->hw_enabled_mask))
5028 radv_emit_streamout_enable(cmd_buffer);
5029 }
5030
5031 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5032 {
5033 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5034 unsigned reg_strmout_cntl;
5035
5036 /* The register is at different places on different ASICs. */
5037 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5038 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5039 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5040 } else {
5041 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5042 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5043 }
5044
5045 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5046 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5047
5048 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5049 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5050 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5051 radeon_emit(cs, 0);
5052 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5053 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5054 radeon_emit(cs, 4); /* poll interval */
5055 }
5056
5057 void radv_CmdBeginTransformFeedbackEXT(
5058 VkCommandBuffer commandBuffer,
5059 uint32_t firstCounterBuffer,
5060 uint32_t counterBufferCount,
5061 const VkBuffer* pCounterBuffers,
5062 const VkDeviceSize* pCounterBufferOffsets)
5063 {
5064 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5065 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5066 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5067 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5068 uint32_t i;
5069
5070 radv_flush_vgt_streamout(cmd_buffer);
5071
5072 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5073 for_each_bit(i, so->enabled_mask) {
5074 int32_t counter_buffer_idx = i - firstCounterBuffer;
5075 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5076 counter_buffer_idx = -1;
5077
5078 /* SI binds streamout buffers as shader resources.
5079 * VGT only counts primitives and tells the shader through
5080 * SGPRs what to do.
5081 */
5082 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5083 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5084 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5085
5086 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5087
5088 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5089 /* The array of counter buffers is optional. */
5090 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5091 uint64_t va = radv_buffer_get_va(buffer->bo);
5092
5093 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5094
5095 /* Append */
5096 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5097 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5098 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5099 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5100 radeon_emit(cs, 0); /* unused */
5101 radeon_emit(cs, 0); /* unused */
5102 radeon_emit(cs, va); /* src address lo */
5103 radeon_emit(cs, va >> 32); /* src address hi */
5104
5105 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5106 } else {
5107 /* Start from the beginning. */
5108 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5109 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5110 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5111 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5112 radeon_emit(cs, 0); /* unused */
5113 radeon_emit(cs, 0); /* unused */
5114 radeon_emit(cs, 0); /* unused */
5115 radeon_emit(cs, 0); /* unused */
5116 }
5117 }
5118
5119 radv_set_streamout_enable(cmd_buffer, true);
5120 }
5121
5122 void radv_CmdEndTransformFeedbackEXT(
5123 VkCommandBuffer commandBuffer,
5124 uint32_t firstCounterBuffer,
5125 uint32_t counterBufferCount,
5126 const VkBuffer* pCounterBuffers,
5127 const VkDeviceSize* pCounterBufferOffsets)
5128 {
5129 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5130 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5131 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5132 uint32_t i;
5133
5134 radv_flush_vgt_streamout(cmd_buffer);
5135
5136 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5137 for_each_bit(i, so->enabled_mask) {
5138 int32_t counter_buffer_idx = i - firstCounterBuffer;
5139 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5140 counter_buffer_idx = -1;
5141
5142 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5143 /* The array of counters buffer is optional. */
5144 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5145 uint64_t va = radv_buffer_get_va(buffer->bo);
5146
5147 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5148
5149 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5150 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5151 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5152 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5153 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5154 radeon_emit(cs, va); /* dst address lo */
5155 radeon_emit(cs, va >> 32); /* dst address hi */
5156 radeon_emit(cs, 0); /* unused */
5157 radeon_emit(cs, 0); /* unused */
5158
5159 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5160 }
5161
5162 /* Deactivate transform feedback by zeroing the buffer size.
5163 * The counters (primitives generated, primitives emitted) may
5164 * be enabled even if there is not buffer bound. This ensures
5165 * that the primitives-emitted query won't increment.
5166 */
5167 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5168
5169 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5170 }
5171
5172 radv_set_streamout_enable(cmd_buffer, false);
5173 }
5174
5175 void radv_CmdDrawIndirectByteCountEXT(
5176 VkCommandBuffer commandBuffer,
5177 uint32_t instanceCount,
5178 uint32_t firstInstance,
5179 VkBuffer _counterBuffer,
5180 VkDeviceSize counterBufferOffset,
5181 uint32_t counterOffset,
5182 uint32_t vertexStride)
5183 {
5184 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5185 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5186 struct radv_draw_info info = {};
5187
5188 info.instance_count = instanceCount;
5189 info.first_instance = firstInstance;
5190 info.strmout_buffer = counterBuffer;
5191 info.strmout_buffer_offset = counterBufferOffset;
5192 info.stride = vertexStride;
5193
5194 radv_draw(cmd_buffer, &info);
5195 }