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9bc50ad0929c3cf44a3ab2026911782efbdebe4a
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 int src_family,
42 int dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_GEOMETRY:
342 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
343 case MESA_SHADER_COMPUTE:
344 return R_00B900_COMPUTE_USER_DATA_0;
345 default:
346 unreachable("unknown shader");
347 }
348 }
349
350 static struct ac_userdata_info *
351 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
352 gl_shader_stage stage,
353 int idx)
354 {
355 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
356 }
357
358 static void
359 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
360 struct radv_pipeline *pipeline,
361 gl_shader_stage stage,
362 int idx, uint64_t va)
363 {
364 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
365 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
366 if (loc->sgpr_idx == -1)
367 return;
368 assert(loc->num_sgprs == 2);
369 assert(!loc->indirect);
370 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
371 radeon_emit(cmd_buffer->cs, va);
372 radeon_emit(cmd_buffer->cs, va >> 32);
373 }
374
375 static void
376 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
377 struct radv_pipeline *pipeline)
378 {
379 int num_samples = pipeline->graphics.ms.num_samples;
380 struct radv_multisample_state *ms = &pipeline->graphics.ms;
381 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
382
383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
384 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
385 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
386
387 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
388 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
389
390 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
391 return;
392
393 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
394 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
395 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
396
397 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
398
399 uint32_t samples_offset;
400 void *samples_ptr;
401 void *src;
402 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
403 &samples_ptr);
404 switch (num_samples) {
405 case 1:
406 src = cmd_buffer->device->sample_locations_1x;
407 break;
408 case 2:
409 src = cmd_buffer->device->sample_locations_2x;
410 break;
411 case 4:
412 src = cmd_buffer->device->sample_locations_4x;
413 break;
414 case 8:
415 src = cmd_buffer->device->sample_locations_8x;
416 break;
417 case 16:
418 src = cmd_buffer->device->sample_locations_16x;
419 break;
420 default:
421 unreachable("unknown number of samples");
422 }
423 memcpy(samples_ptr, src, num_samples * 4 * 2);
424
425 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
426 va += samples_offset;
427
428 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
429 AC_UD_PS_SAMPLE_POS, va);
430 }
431
432 static void
433 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline)
435 {
436 struct radv_raster_state *raster = &pipeline->graphics.raster;
437
438 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
439 raster->pa_cl_clip_cntl);
440
441 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
442 raster->spi_interp_control);
443
444 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
445 unsigned tmp = (unsigned)(1.0 * 8.0);
446 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
447 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
448 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
449
450 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
451 raster->pa_su_vtx_cntl);
452
453 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
454 raster->pa_su_sc_mode_cntl);
455 }
456
457 static void
458 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline,
460 struct radv_shader_variant *shader)
461 {
462 struct radeon_winsys *ws = cmd_buffer->device->ws;
463 uint64_t va = ws->buffer_get_va(shader->bo);
464 unsigned export_count;
465
466 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
467
468 export_count = MAX2(1, shader->info.vs.param_exports);
469 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
470 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
471
472 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
473 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
474 S_02870C_POS1_EXPORT_FORMAT(shader->info.vs.pos_exports > 1 ?
475 V_02870C_SPI_SHADER_4COMP :
476 V_02870C_SPI_SHADER_NONE) |
477 S_02870C_POS2_EXPORT_FORMAT(shader->info.vs.pos_exports > 2 ?
478 V_02870C_SPI_SHADER_4COMP :
479 V_02870C_SPI_SHADER_NONE) |
480 S_02870C_POS3_EXPORT_FORMAT(shader->info.vs.pos_exports > 3 ?
481 V_02870C_SPI_SHADER_4COMP :
482 V_02870C_SPI_SHADER_NONE));
483
484
485 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
486 radeon_emit(cmd_buffer->cs, va >> 8);
487 radeon_emit(cmd_buffer->cs, va >> 40);
488 radeon_emit(cmd_buffer->cs, shader->rsrc1);
489 radeon_emit(cmd_buffer->cs, shader->rsrc2);
490
491 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
492 S_028818_VTX_W0_FMT(1) |
493 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
494 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
495 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
496
497 unsigned clip_dist_mask, cull_dist_mask, total_mask;
498 clip_dist_mask = shader->info.vs.clip_dist_mask;
499 cull_dist_mask = shader->info.vs.cull_dist_mask;
500 total_mask = clip_dist_mask | cull_dist_mask;
501
502 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(shader->info.vs.writes_pointsize) |
504 S_02881C_USE_VTX_RENDER_TARGET_INDX(shader->info.vs.writes_layer) |
505 S_02881C_USE_VTX_VIEWPORT_INDX(shader->info.vs.writes_viewport_index) |
506 S_02881C_VS_OUT_MISC_VEC_ENA(shader->info.vs.writes_pointsize ||
507 shader->info.vs.writes_layer ||
508 shader->info.vs.writes_viewport_index) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
511 pipeline->graphics.raster.pa_cl_vs_out_cntl |
512 cull_dist_mask << 8 |
513 clip_dist_mask);
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
516 S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
517 }
518
519 static void
520 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_shader_variant *shader)
522 {
523 struct radeon_winsys *ws = cmd_buffer->device->ws;
524 uint64_t va = ws->buffer_get_va(shader->bo);
525
526 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
527
528 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
529 radeon_emit(cmd_buffer->cs, va >> 8);
530 radeon_emit(cmd_buffer->cs, va >> 40);
531 radeon_emit(cmd_buffer->cs, shader->rsrc1);
532 radeon_emit(cmd_buffer->cs, shader->rsrc2);
533 }
534
535 static void
536 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
537 struct radv_pipeline *pipeline)
538 {
539 struct radv_shader_variant *vs;
540
541 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
542
543 vs = pipeline->shaders[MESA_SHADER_VERTEX];
544
545 if (vs->info.vs.as_es)
546 radv_emit_hw_es(cmd_buffer, vs);
547 else
548 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
549
550 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
551 }
552
553
554
555 static void
556 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
557 struct radv_pipeline *pipeline)
558 {
559 struct radeon_winsys *ws = cmd_buffer->device->ws;
560 struct radv_shader_variant *ps, *vs;
561 uint64_t va;
562 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
563 struct radv_blend_state *blend = &pipeline->graphics.blend;
564 unsigned ps_offset = 0;
565 unsigned z_order;
566 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
567
568 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
569 vs = pipeline->shaders[MESA_SHADER_VERTEX];
570 va = ws->buffer_get_va(ps->bo);
571 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
572
573 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
574 radeon_emit(cmd_buffer->cs, va >> 8);
575 radeon_emit(cmd_buffer->cs, va >> 40);
576 radeon_emit(cmd_buffer->cs, ps->rsrc1);
577 radeon_emit(cmd_buffer->cs, ps->rsrc2);
578
579 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
580 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
581 else
582 z_order = V_02880C_LATE_Z;
583
584
585 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
586 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
587 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
588 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
589 S_02880C_Z_ORDER(z_order) |
590 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
591 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
592 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
593
594 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
595 ps->config.spi_ps_input_ena);
596
597 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
598 ps->config.spi_ps_input_addr);
599
600 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
601 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
602 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
603
604 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
605
606 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
607 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
608 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
609 V_028710_SPI_SHADER_ZERO);
610
611 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
614 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
615
616 if (ps->info.fs.has_pcoord) {
617 unsigned val;
618 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
619 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
620 ps_offset = 1;
621 }
622
623 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
624 unsigned vs_offset, flat_shade;
625 unsigned val;
626
627 if (!(ps->info.fs.input_mask & (1u << i)))
628 continue;
629
630
631 if (!(vs->info.vs.export_mask & (1u << i))) {
632 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
633 S_028644_OFFSET(0x20));
634 ++ps_offset;
635 continue;
636 }
637
638 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
639 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
640
641 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
642 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
643 ++ps_offset;
644 }
645 }
646
647 static void
648 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
652 return;
653
654 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
655 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
656 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
657 radv_update_multisample_state(cmd_buffer, pipeline);
658 radv_emit_vertex_shader(cmd_buffer, pipeline);
659 radv_emit_fragment_shader(cmd_buffer, pipeline);
660
661 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
662 pipeline->graphics.prim_restart_enable);
663
664 cmd_buffer->scratch_size_needed =
665 MAX2(cmd_buffer->scratch_size_needed,
666 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
667
668 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
669 S_0286E8_WAVES(pipeline->max_waves) |
670 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
671 cmd_buffer->state.emitted_pipeline = pipeline;
672 }
673
674 static void
675 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
676 {
677 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
678 cmd_buffer->state.dynamic.viewport.viewports);
679 }
680
681 static void
682 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
683 {
684 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
685 si_write_scissors(cmd_buffer->cs, 0, count,
686 cmd_buffer->state.dynamic.scissor.scissors);
687 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
688 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
689 }
690
691 static void
692 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
693 int index,
694 struct radv_color_buffer_info *cb)
695 {
696 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
697 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
698 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
699 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
700 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
701 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
702 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
703 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
704 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
705 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
706 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
707 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
708 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
709
710 if (is_vi) { /* DCC BASE */
711 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
712 }
713 }
714
715 static void
716 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
717 struct radv_ds_buffer_info *ds,
718 struct radv_image *image,
719 VkImageLayout layout)
720 {
721 uint32_t db_z_info = ds->db_z_info;
722
723 if (!radv_layout_has_htile(image, layout))
724 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
725
726 if (!radv_layout_can_expclear(image, layout))
727 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
728
729 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
730 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
731
732 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
733 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
734 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
735 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
736 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
737 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
738 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
739 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
740 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
741 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
742
743 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
744 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
745 ds->pa_su_poly_offset_db_fmt_cntl);
746 }
747
748 /*
749 * To hw resolve multisample images both src and dst need to have the same
750 * micro tiling mode. However we don't always know in advance when creating
751 * the images. This function gets called if we have a resolve attachment,
752 * and tests if the attachment image has the same tiling mode, then it
753 * checks if the generated framebuffer data has the same tiling mode, and
754 * updates it if not.
755 */
756 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
757 struct radv_attachment_info *att,
758 uint32_t micro_tile_mode)
759 {
760 struct radv_image *image = att->attachment->image;
761 uint32_t tile_mode_index;
762 if (image->surface.nsamples <= 1)
763 return;
764
765 if (image->surface.micro_tile_mode != micro_tile_mode) {
766 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
767 }
768
769 if (att->cb.micro_tile_mode != micro_tile_mode) {
770 tile_mode_index = image->surface.tiling_index[0];
771
772 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
773 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
774 att->cb.micro_tile_mode = micro_tile_mode;
775 }
776 }
777
778 void
779 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
780 struct radv_image *image,
781 VkClearDepthStencilValue ds_clear_value,
782 VkImageAspectFlags aspects)
783 {
784 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
785 va += image->offset + image->clear_value_offset;
786 unsigned reg_offset = 0, reg_count = 0;
787
788 if (!image->htile.size || !aspects)
789 return;
790
791 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
792 ++reg_count;
793 } else {
794 ++reg_offset;
795 va += 4;
796 }
797 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
798 ++reg_count;
799
800 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
801
802 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
803 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
804 S_370_WR_CONFIRM(1) |
805 S_370_ENGINE_SEL(V_370_PFP));
806 radeon_emit(cmd_buffer->cs, va);
807 radeon_emit(cmd_buffer->cs, va >> 32);
808 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
809 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
810 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
811 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
812
813 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
814 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
815 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
816 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
817 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
818 }
819
820 static void
821 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
822 struct radv_image *image)
823 {
824 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
825 va += image->offset + image->clear_value_offset;
826
827 if (!image->htile.size)
828 return;
829
830 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
831
832 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
833 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
834 COPY_DATA_DST_SEL(COPY_DATA_REG) |
835 COPY_DATA_COUNT_SEL);
836 radeon_emit(cmd_buffer->cs, va);
837 radeon_emit(cmd_buffer->cs, va >> 32);
838 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
839 radeon_emit(cmd_buffer->cs, 0);
840
841 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
842 radeon_emit(cmd_buffer->cs, 0);
843 }
844
845 void
846 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
847 struct radv_image *image,
848 int idx,
849 uint32_t color_values[2])
850 {
851 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
852 va += image->offset + image->clear_value_offset;
853
854 if (!image->cmask.size && !image->surface.dcc_size)
855 return;
856
857 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
858
859 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
860 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
861 S_370_WR_CONFIRM(1) |
862 S_370_ENGINE_SEL(V_370_PFP));
863 radeon_emit(cmd_buffer->cs, va);
864 radeon_emit(cmd_buffer->cs, va >> 32);
865 radeon_emit(cmd_buffer->cs, color_values[0]);
866 radeon_emit(cmd_buffer->cs, color_values[1]);
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
869 radeon_emit(cmd_buffer->cs, color_values[0]);
870 radeon_emit(cmd_buffer->cs, color_values[1]);
871 }
872
873 static void
874 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
875 struct radv_image *image,
876 int idx)
877 {
878 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
879 va += image->offset + image->clear_value_offset;
880
881 if (!image->cmask.size && !image->surface.dcc_size)
882 return;
883
884 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
885 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
886
887 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
888 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
889 COPY_DATA_DST_SEL(COPY_DATA_REG) |
890 COPY_DATA_COUNT_SEL);
891 radeon_emit(cmd_buffer->cs, va);
892 radeon_emit(cmd_buffer->cs, va >> 32);
893 radeon_emit(cmd_buffer->cs, reg >> 2);
894 radeon_emit(cmd_buffer->cs, 0);
895
896 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
897 radeon_emit(cmd_buffer->cs, 0);
898 }
899
900 void
901 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
902 {
903 int i;
904 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
905 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
906 int dst_resolve_micro_tile_mode = -1;
907
908 if (subpass->has_resolve) {
909 uint32_t a = subpass->resolve_attachments[0].attachment;
910 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
911 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
912 }
913 for (i = 0; i < subpass->color_count; ++i) {
914 int idx = subpass->color_attachments[i].attachment;
915 struct radv_attachment_info *att = &framebuffer->attachments[idx];
916
917 if (dst_resolve_micro_tile_mode != -1) {
918 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
919 att, dst_resolve_micro_tile_mode);
920 }
921 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
922
923 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
924 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
925
926 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
927 }
928
929 for (i = subpass->color_count; i < 8; i++)
930 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
931 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
932
933 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
934 int idx = subpass->depth_stencil_attachment.attachment;
935 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
936 struct radv_attachment_info *att = &framebuffer->attachments[idx];
937 struct radv_image *image = att->attachment->image;
938 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
939
940 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
941
942 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
943 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
944 cmd_buffer->state.offset_scale = att->ds.offset_scale;
945 }
946 radv_load_depth_clear_regs(cmd_buffer, image);
947 } else {
948 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
949 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
950 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
951 }
952 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
953 S_028208_BR_X(framebuffer->width) |
954 S_028208_BR_Y(framebuffer->height));
955 }
956
957 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
958 {
959 uint32_t db_count_control;
960
961 if(!cmd_buffer->state.active_occlusion_queries) {
962 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
963 db_count_control = 0;
964 } else {
965 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
966 }
967 } else {
968 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
969 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
970 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
971 S_028004_ZPASS_ENABLE(1) |
972 S_028004_SLICE_EVEN_ENABLE(1) |
973 S_028004_SLICE_ODD_ENABLE(1);
974 } else {
975 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
976 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
977 }
978 }
979
980 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
981 }
982
983 static void
984 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
985 {
986 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
987
988 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
989 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
990 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
991 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
992 }
993
994 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
995 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
996 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
997 }
998
999 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1000 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1001 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1002 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1003 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1004 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1005 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1006 S_028430_STENCILOPVAL(1));
1007 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1008 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1009 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1010 S_028434_STENCILOPVAL_BF(1));
1011 }
1012
1013 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1014 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1015 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1016 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1017 }
1018
1019 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1020 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1021 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1022 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1023 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1024
1025 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1026 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1027 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1028 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1029 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1030 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1031 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1032 }
1033 }
1034
1035 cmd_buffer->state.dirty = 0;
1036 }
1037
1038 static void
1039 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1040 struct radv_pipeline *pipeline,
1041 int idx,
1042 uint64_t va,
1043 gl_shader_stage stage)
1044 {
1045 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1046 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1047
1048 if (desc_set_loc->sgpr_idx == -1)
1049 return;
1050
1051 assert(!desc_set_loc->indirect);
1052 assert(desc_set_loc->num_sgprs == 2);
1053 radeon_set_sh_reg_seq(cmd_buffer->cs,
1054 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1055 radeon_emit(cmd_buffer->cs, va);
1056 radeon_emit(cmd_buffer->cs, va >> 32);
1057 }
1058
1059 static void
1060 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1061 struct radv_pipeline *pipeline,
1062 VkShaderStageFlags stages,
1063 struct radv_descriptor_set *set,
1064 unsigned idx)
1065 {
1066 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1067 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1068 idx, set->va,
1069 MESA_SHADER_FRAGMENT);
1070
1071 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1072 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1073 idx, set->va,
1074 MESA_SHADER_VERTEX);
1075
1076 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1077 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1078 idx, set->va,
1079 MESA_SHADER_GEOMETRY);
1080
1081 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1082 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1083 idx, set->va,
1084 MESA_SHADER_COMPUTE);
1085 }
1086
1087 static void
1088 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1089 struct radv_pipeline *pipeline,
1090 VkShaderStageFlags stages)
1091 {
1092 unsigned i;
1093 if (!cmd_buffer->state.descriptors_dirty)
1094 return;
1095
1096 for (i = 0; i < MAX_SETS; i++) {
1097 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1098 continue;
1099 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1100 if (!set)
1101 continue;
1102
1103 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1104 }
1105 cmd_buffer->state.descriptors_dirty = 0;
1106 }
1107
1108 static void
1109 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1110 struct radv_pipeline *pipeline,
1111 VkShaderStageFlags stages)
1112 {
1113 struct radv_pipeline_layout *layout = pipeline->layout;
1114 unsigned offset;
1115 void *ptr;
1116 uint64_t va;
1117
1118 stages &= cmd_buffer->push_constant_stages;
1119 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1120 return;
1121
1122 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1123 16 * layout->dynamic_offset_count,
1124 256, &offset, &ptr);
1125
1126 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1127 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1128 16 * layout->dynamic_offset_count);
1129
1130 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1131 va += offset;
1132
1133 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1134 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1135 AC_UD_PUSH_CONSTANTS, va);
1136
1137 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1138 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1139 AC_UD_PUSH_CONSTANTS, va);
1140
1141 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1142 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1143 AC_UD_PUSH_CONSTANTS, va);
1144
1145 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1146 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1147 AC_UD_PUSH_CONSTANTS, va);
1148
1149 cmd_buffer->push_constant_stages &= ~stages;
1150 }
1151
1152 static void
1153 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1154 {
1155 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1156 struct radv_device *device = cmd_buffer->device;
1157 uint32_t ia_multi_vgt_param;
1158 uint32_t ls_hs_config = 0;
1159
1160 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1161 cmd_buffer->cs, 4096);
1162
1163 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1164 cmd_buffer->state.pipeline->num_vertex_attribs) {
1165 unsigned vb_offset;
1166 void *vb_ptr;
1167 uint32_t i = 0;
1168 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1169 uint64_t va;
1170
1171 /* allocate some descriptor state for vertex buffers */
1172 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1173 &vb_offset, &vb_ptr);
1174
1175 for (i = 0; i < num_attribs; i++) {
1176 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1177 uint32_t offset;
1178 int vb = cmd_buffer->state.pipeline->va_binding[i];
1179 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1180 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1181
1182 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1183 va = device->ws->buffer_get_va(buffer->bo);
1184
1185 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1186 va += offset + buffer->offset;
1187 desc[0] = va;
1188 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1189 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1190 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1191 else
1192 desc[2] = buffer->size - offset;
1193 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1194 }
1195
1196 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1197 va += vb_offset;
1198
1199 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1200 AC_UD_VS_VERTEX_BUFFERS, va);
1201 }
1202
1203 cmd_buffer->state.vertex_descriptors_dirty = false;
1204 cmd_buffer->state.vb_dirty = 0;
1205 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1206 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1207
1208 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1209 radv_emit_framebuffer_state(cmd_buffer);
1210
1211 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1212 radv_emit_viewport(cmd_buffer);
1213
1214 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1215 radv_emit_scissor(cmd_buffer);
1216
1217 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1218 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1219 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1220
1221 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1222 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1223 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1224 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1225 } else {
1226 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1227 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1228 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1229 }
1230 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1231 }
1232
1233 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1234
1235 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1236 VK_SHADER_STAGE_ALL_GRAPHICS);
1237 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1238 VK_SHADER_STAGE_ALL_GRAPHICS);
1239
1240 assert(cmd_buffer->cs->cdw <= cdw_max);
1241
1242 si_emit_cache_flush(cmd_buffer);
1243 }
1244
1245 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1246 VkPipelineStageFlags src_stage_mask)
1247 {
1248 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1249 VK_PIPELINE_STAGE_TRANSFER_BIT |
1250 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1251 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1252 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1253 }
1254
1255 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1256 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1257 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1258 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1259 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1260 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1261 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1262 VK_PIPELINE_STAGE_TRANSFER_BIT |
1263 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1264 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1265 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1266 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1267 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1268 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1269 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1270 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1271 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1272 }
1273 }
1274
1275 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1276 {
1277 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1278
1279 /* TODO: actual cache flushes */
1280 }
1281
1282 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1283 VkAttachmentReference att)
1284 {
1285 unsigned idx = att.attachment;
1286 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1287 VkImageSubresourceRange range;
1288 range.aspectMask = 0;
1289 range.baseMipLevel = view->base_mip;
1290 range.levelCount = 1;
1291 range.baseArrayLayer = view->base_layer;
1292 range.layerCount = cmd_buffer->state.framebuffer->layers;
1293
1294 radv_handle_image_transition(cmd_buffer,
1295 view->image,
1296 cmd_buffer->state.attachments[idx].current_layout,
1297 att.layout, 0, 0, range,
1298 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1299
1300 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1301
1302
1303 }
1304
1305 void
1306 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1307 const struct radv_subpass *subpass, bool transitions)
1308 {
1309 if (transitions) {
1310 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1311
1312 for (unsigned i = 0; i < subpass->color_count; ++i) {
1313 radv_handle_subpass_image_transition(cmd_buffer,
1314 subpass->color_attachments[i]);
1315 }
1316
1317 for (unsigned i = 0; i < subpass->input_count; ++i) {
1318 radv_handle_subpass_image_transition(cmd_buffer,
1319 subpass->input_attachments[i]);
1320 }
1321
1322 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1323 radv_handle_subpass_image_transition(cmd_buffer,
1324 subpass->depth_stencil_attachment);
1325 }
1326 }
1327
1328 cmd_buffer->state.subpass = subpass;
1329
1330 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1331 }
1332
1333 static void
1334 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1335 struct radv_render_pass *pass,
1336 const VkRenderPassBeginInfo *info)
1337 {
1338 struct radv_cmd_state *state = &cmd_buffer->state;
1339
1340 if (pass->attachment_count == 0) {
1341 state->attachments = NULL;
1342 return;
1343 }
1344
1345 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1346 pass->attachment_count *
1347 sizeof(state->attachments[0]),
1348 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1349 if (state->attachments == NULL) {
1350 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1351 abort();
1352 }
1353
1354 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1355 struct radv_render_pass_attachment *att = &pass->attachments[i];
1356 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1357 VkImageAspectFlags clear_aspects = 0;
1358
1359 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1360 /* color attachment */
1361 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1362 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1363 }
1364 } else {
1365 /* depthstencil attachment */
1366 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1367 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1368 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1369 }
1370 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1371 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1372 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1373 }
1374 }
1375
1376 state->attachments[i].pending_clear_aspects = clear_aspects;
1377 if (clear_aspects && info) {
1378 assert(info->clearValueCount > i);
1379 state->attachments[i].clear_value = info->pClearValues[i];
1380 }
1381
1382 state->attachments[i].current_layout = att->initial_layout;
1383 }
1384 }
1385
1386 VkResult radv_AllocateCommandBuffers(
1387 VkDevice _device,
1388 const VkCommandBufferAllocateInfo *pAllocateInfo,
1389 VkCommandBuffer *pCommandBuffers)
1390 {
1391 RADV_FROM_HANDLE(radv_device, device, _device);
1392 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1393
1394 VkResult result = VK_SUCCESS;
1395 uint32_t i;
1396
1397 memset(pCommandBuffers, 0,
1398 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1399
1400 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1401 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1402 &pCommandBuffers[i]);
1403 if (result != VK_SUCCESS)
1404 break;
1405 }
1406
1407 if (result != VK_SUCCESS)
1408 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1409 i, pCommandBuffers);
1410
1411 return result;
1412 }
1413
1414 static void
1415 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1416 {
1417 list_del(&cmd_buffer->pool_link);
1418
1419 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1420 &cmd_buffer->upload.list, list) {
1421 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1422 list_del(&up->list);
1423 free(up);
1424 }
1425
1426 if (cmd_buffer->upload.upload_bo)
1427 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1428 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1429 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1430 }
1431
1432 void radv_FreeCommandBuffers(
1433 VkDevice device,
1434 VkCommandPool commandPool,
1435 uint32_t commandBufferCount,
1436 const VkCommandBuffer *pCommandBuffers)
1437 {
1438 for (uint32_t i = 0; i < commandBufferCount; i++) {
1439 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1440
1441 if (cmd_buffer)
1442 radv_cmd_buffer_destroy(cmd_buffer);
1443 }
1444 }
1445
1446 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1447 {
1448
1449 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1450
1451 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1452 &cmd_buffer->upload.list, list) {
1453 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1454 list_del(&up->list);
1455 free(up);
1456 }
1457
1458 cmd_buffer->scratch_size_needed = 0;
1459 cmd_buffer->compute_scratch_size_needed = 0;
1460 cmd_buffer->esgs_ring_size_needed = 0;
1461 cmd_buffer->gsvs_ring_size_needed = 0;
1462
1463 if (cmd_buffer->upload.upload_bo)
1464 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1465 cmd_buffer->upload.upload_bo, 8);
1466 cmd_buffer->upload.offset = 0;
1467
1468 cmd_buffer->record_fail = false;
1469
1470 cmd_buffer->ring_offsets_idx = -1;
1471 }
1472
1473 VkResult radv_ResetCommandBuffer(
1474 VkCommandBuffer commandBuffer,
1475 VkCommandBufferResetFlags flags)
1476 {
1477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1478 radv_reset_cmd_buffer(cmd_buffer);
1479 return VK_SUCCESS;
1480 }
1481
1482 VkResult radv_BeginCommandBuffer(
1483 VkCommandBuffer commandBuffer,
1484 const VkCommandBufferBeginInfo *pBeginInfo)
1485 {
1486 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1487 radv_reset_cmd_buffer(cmd_buffer);
1488
1489 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1490
1491 /* setup initial configuration into command buffer */
1492 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1493 switch (cmd_buffer->queue_family_index) {
1494 case RADV_QUEUE_GENERAL:
1495 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1496 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1497 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1498 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1499 RADV_CMD_FLAG_INV_VMEM_L1 |
1500 RADV_CMD_FLAG_INV_SMEM_L1 |
1501 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1502 RADV_CMD_FLAG_INV_GLOBAL_L2;
1503 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1504 radv_set_db_count_control(cmd_buffer);
1505 si_emit_cache_flush(cmd_buffer);
1506 break;
1507 case RADV_QUEUE_COMPUTE:
1508 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1509 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1510 RADV_CMD_FLAG_INV_VMEM_L1 |
1511 RADV_CMD_FLAG_INV_SMEM_L1 |
1512 RADV_CMD_FLAG_INV_GLOBAL_L2;
1513 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1514 si_emit_cache_flush(cmd_buffer);
1515 break;
1516 case RADV_QUEUE_TRANSFER:
1517 default:
1518 break;
1519 }
1520 }
1521
1522 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1523 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1524 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1525
1526 struct radv_subpass *subpass =
1527 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1528
1529 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1530 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1531 }
1532
1533 return VK_SUCCESS;
1534 }
1535
1536 void radv_CmdBindVertexBuffers(
1537 VkCommandBuffer commandBuffer,
1538 uint32_t firstBinding,
1539 uint32_t bindingCount,
1540 const VkBuffer* pBuffers,
1541 const VkDeviceSize* pOffsets)
1542 {
1543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1544 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1545
1546 /* We have to defer setting up vertex buffer since we need the buffer
1547 * stride from the pipeline. */
1548
1549 assert(firstBinding + bindingCount < MAX_VBS);
1550 for (uint32_t i = 0; i < bindingCount; i++) {
1551 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1552 vb[firstBinding + i].offset = pOffsets[i];
1553 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1554 }
1555 }
1556
1557 void radv_CmdBindIndexBuffer(
1558 VkCommandBuffer commandBuffer,
1559 VkBuffer buffer,
1560 VkDeviceSize offset,
1561 VkIndexType indexType)
1562 {
1563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1564
1565 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1566 cmd_buffer->state.index_offset = offset;
1567 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1568 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1569 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1570 }
1571
1572
1573 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1574 struct radv_descriptor_set *set,
1575 unsigned idx)
1576 {
1577 struct radeon_winsys *ws = cmd_buffer->device->ws;
1578
1579 cmd_buffer->state.descriptors[idx] = set;
1580 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1581 if (!set)
1582 return;
1583
1584 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1585 if (set->descriptors[j])
1586 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1587
1588 if(set->bo)
1589 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1590 }
1591
1592 void radv_CmdBindDescriptorSets(
1593 VkCommandBuffer commandBuffer,
1594 VkPipelineBindPoint pipelineBindPoint,
1595 VkPipelineLayout _layout,
1596 uint32_t firstSet,
1597 uint32_t descriptorSetCount,
1598 const VkDescriptorSet* pDescriptorSets,
1599 uint32_t dynamicOffsetCount,
1600 const uint32_t* pDynamicOffsets)
1601 {
1602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1603 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1604 unsigned dyn_idx = 0;
1605
1606 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1607 cmd_buffer->cs, MAX_SETS * 4 * 6);
1608
1609 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1610 unsigned idx = i + firstSet;
1611 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1612 radv_bind_descriptor_set(cmd_buffer, set, idx);
1613
1614 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1615 unsigned idx = j + layout->set[i].dynamic_offset_start;
1616 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1617 assert(dyn_idx < dynamicOffsetCount);
1618
1619 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1620 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1621 dst[0] = va;
1622 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1623 dst[2] = range->size;
1624 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1625 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1626 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1627 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1628 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1629 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1630 cmd_buffer->push_constant_stages |=
1631 set->layout->dynamic_shader_stages;
1632 }
1633 }
1634
1635 assert(cmd_buffer->cs->cdw <= cdw_max);
1636 }
1637
1638 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1639 VkPipelineLayout layout,
1640 VkShaderStageFlags stageFlags,
1641 uint32_t offset,
1642 uint32_t size,
1643 const void* pValues)
1644 {
1645 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1646 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1647 cmd_buffer->push_constant_stages |= stageFlags;
1648 }
1649
1650 VkResult radv_EndCommandBuffer(
1651 VkCommandBuffer commandBuffer)
1652 {
1653 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1654
1655 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1656 si_emit_cache_flush(cmd_buffer);
1657
1658 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1659 cmd_buffer->record_fail)
1660 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1661 return VK_SUCCESS;
1662 }
1663
1664 static void
1665 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1666 {
1667 struct radeon_winsys *ws = cmd_buffer->device->ws;
1668 struct radv_shader_variant *compute_shader;
1669 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1670 uint64_t va;
1671
1672 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1673 return;
1674
1675 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1676
1677 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1678 va = ws->buffer_get_va(compute_shader->bo);
1679
1680 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1681
1682 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1683 cmd_buffer->cs, 16);
1684
1685 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1686 radeon_emit(cmd_buffer->cs, va >> 8);
1687 radeon_emit(cmd_buffer->cs, va >> 40);
1688
1689 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1690 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1691 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1692
1693
1694 cmd_buffer->compute_scratch_size_needed =
1695 MAX2(cmd_buffer->compute_scratch_size_needed,
1696 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1697
1698 /* change these once we have scratch support */
1699 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1700 S_00B860_WAVES(pipeline->max_waves) |
1701 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1702
1703 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1704 radeon_emit(cmd_buffer->cs,
1705 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1706 radeon_emit(cmd_buffer->cs,
1707 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1708 radeon_emit(cmd_buffer->cs,
1709 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1710
1711 assert(cmd_buffer->cs->cdw <= cdw_max);
1712 }
1713
1714
1715 void radv_CmdBindPipeline(
1716 VkCommandBuffer commandBuffer,
1717 VkPipelineBindPoint pipelineBindPoint,
1718 VkPipeline _pipeline)
1719 {
1720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1721 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1722
1723 for (unsigned i = 0; i < MAX_SETS; i++) {
1724 if (cmd_buffer->state.descriptors[i])
1725 cmd_buffer->state.descriptors_dirty |= (1 << i);
1726 }
1727
1728 switch (pipelineBindPoint) {
1729 case VK_PIPELINE_BIND_POINT_COMPUTE:
1730 cmd_buffer->state.compute_pipeline = pipeline;
1731 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1732 break;
1733 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1734 cmd_buffer->state.pipeline = pipeline;
1735 cmd_buffer->state.vertex_descriptors_dirty = true;
1736 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1737 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1738
1739 /* Apply the dynamic state from the pipeline */
1740 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1741 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1742 &pipeline->dynamic_state,
1743 pipeline->dynamic_state_mask);
1744
1745 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1746 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1747 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1748 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1749
1750 if (radv_pipeline_has_gs(pipeline)) {
1751 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1752 AC_UD_SCRATCH_RING_OFFSETS);
1753 if (cmd_buffer->ring_offsets_idx == -1)
1754 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1755 else if (loc->sgpr_idx != -1)
1756 assert(loc->sgpr_idx != cmd_buffer->ring_offsets_idx);
1757 }
1758 break;
1759 default:
1760 assert(!"invalid bind point");
1761 break;
1762 }
1763 }
1764
1765 void radv_CmdSetViewport(
1766 VkCommandBuffer commandBuffer,
1767 uint32_t firstViewport,
1768 uint32_t viewportCount,
1769 const VkViewport* pViewports)
1770 {
1771 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1772
1773 const uint32_t total_count = firstViewport + viewportCount;
1774 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1775 cmd_buffer->state.dynamic.viewport.count = total_count;
1776
1777 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1778 pViewports, viewportCount * sizeof(*pViewports));
1779
1780 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1781 }
1782
1783 void radv_CmdSetScissor(
1784 VkCommandBuffer commandBuffer,
1785 uint32_t firstScissor,
1786 uint32_t scissorCount,
1787 const VkRect2D* pScissors)
1788 {
1789 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1790
1791 const uint32_t total_count = firstScissor + scissorCount;
1792 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1793 cmd_buffer->state.dynamic.scissor.count = total_count;
1794
1795 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1796 pScissors, scissorCount * sizeof(*pScissors));
1797 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1798 }
1799
1800 void radv_CmdSetLineWidth(
1801 VkCommandBuffer commandBuffer,
1802 float lineWidth)
1803 {
1804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1805 cmd_buffer->state.dynamic.line_width = lineWidth;
1806 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1807 }
1808
1809 void radv_CmdSetDepthBias(
1810 VkCommandBuffer commandBuffer,
1811 float depthBiasConstantFactor,
1812 float depthBiasClamp,
1813 float depthBiasSlopeFactor)
1814 {
1815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1816
1817 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1818 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1819 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1820
1821 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1822 }
1823
1824 void radv_CmdSetBlendConstants(
1825 VkCommandBuffer commandBuffer,
1826 const float blendConstants[4])
1827 {
1828 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1829
1830 memcpy(cmd_buffer->state.dynamic.blend_constants,
1831 blendConstants, sizeof(float) * 4);
1832
1833 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1834 }
1835
1836 void radv_CmdSetDepthBounds(
1837 VkCommandBuffer commandBuffer,
1838 float minDepthBounds,
1839 float maxDepthBounds)
1840 {
1841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1842
1843 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1844 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1845
1846 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1847 }
1848
1849 void radv_CmdSetStencilCompareMask(
1850 VkCommandBuffer commandBuffer,
1851 VkStencilFaceFlags faceMask,
1852 uint32_t compareMask)
1853 {
1854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1855
1856 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1857 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1858 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1859 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1860
1861 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1862 }
1863
1864 void radv_CmdSetStencilWriteMask(
1865 VkCommandBuffer commandBuffer,
1866 VkStencilFaceFlags faceMask,
1867 uint32_t writeMask)
1868 {
1869 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1870
1871 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1872 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1873 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1874 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1875
1876 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1877 }
1878
1879 void radv_CmdSetStencilReference(
1880 VkCommandBuffer commandBuffer,
1881 VkStencilFaceFlags faceMask,
1882 uint32_t reference)
1883 {
1884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1885
1886 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1887 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1888 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1889 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1890
1891 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1892 }
1893
1894
1895 void radv_CmdExecuteCommands(
1896 VkCommandBuffer commandBuffer,
1897 uint32_t commandBufferCount,
1898 const VkCommandBuffer* pCmdBuffers)
1899 {
1900 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1901
1902 for (uint32_t i = 0; i < commandBufferCount; i++) {
1903 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1904
1905 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
1906 secondary->scratch_size_needed);
1907 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
1908 secondary->compute_scratch_size_needed);
1909
1910 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
1911 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
1912 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
1913 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
1914
1915 if (secondary->ring_offsets_idx != -1) {
1916 if (primary->ring_offsets_idx == -1)
1917 primary->ring_offsets_idx = secondary->ring_offsets_idx;
1918 else
1919 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
1920 }
1921 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1922 }
1923
1924 /* if we execute secondary we need to re-emit out pipelines */
1925 if (commandBufferCount) {
1926 primary->state.emitted_pipeline = NULL;
1927 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1928 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1929 }
1930 }
1931
1932 VkResult radv_CreateCommandPool(
1933 VkDevice _device,
1934 const VkCommandPoolCreateInfo* pCreateInfo,
1935 const VkAllocationCallbacks* pAllocator,
1936 VkCommandPool* pCmdPool)
1937 {
1938 RADV_FROM_HANDLE(radv_device, device, _device);
1939 struct radv_cmd_pool *pool;
1940
1941 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1942 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1943 if (pool == NULL)
1944 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1945
1946 if (pAllocator)
1947 pool->alloc = *pAllocator;
1948 else
1949 pool->alloc = device->alloc;
1950
1951 list_inithead(&pool->cmd_buffers);
1952
1953 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1954
1955 *pCmdPool = radv_cmd_pool_to_handle(pool);
1956
1957 return VK_SUCCESS;
1958
1959 }
1960
1961 void radv_DestroyCommandPool(
1962 VkDevice _device,
1963 VkCommandPool commandPool,
1964 const VkAllocationCallbacks* pAllocator)
1965 {
1966 RADV_FROM_HANDLE(radv_device, device, _device);
1967 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1968
1969 if (!pool)
1970 return;
1971
1972 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1973 &pool->cmd_buffers, pool_link) {
1974 radv_cmd_buffer_destroy(cmd_buffer);
1975 }
1976
1977 vk_free2(&device->alloc, pAllocator, pool);
1978 }
1979
1980 VkResult radv_ResetCommandPool(
1981 VkDevice device,
1982 VkCommandPool commandPool,
1983 VkCommandPoolResetFlags flags)
1984 {
1985 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1986
1987 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1988 &pool->cmd_buffers, pool_link) {
1989 radv_reset_cmd_buffer(cmd_buffer);
1990 }
1991
1992 return VK_SUCCESS;
1993 }
1994
1995 void radv_TrimCommandPoolKHR(
1996 VkDevice device,
1997 VkCommandPool commandPool,
1998 VkCommandPoolTrimFlagsKHR flags)
1999 {
2000 }
2001
2002 void radv_CmdBeginRenderPass(
2003 VkCommandBuffer commandBuffer,
2004 const VkRenderPassBeginInfo* pRenderPassBegin,
2005 VkSubpassContents contents)
2006 {
2007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2008 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2009 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2010
2011 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2012 cmd_buffer->cs, 2048);
2013
2014 cmd_buffer->state.framebuffer = framebuffer;
2015 cmd_buffer->state.pass = pass;
2016 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2017 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2018
2019 si_emit_cache_flush(cmd_buffer);
2020
2021 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2022 assert(cmd_buffer->cs->cdw <= cdw_max);
2023
2024 radv_cmd_buffer_clear_subpass(cmd_buffer);
2025 }
2026
2027 void radv_CmdNextSubpass(
2028 VkCommandBuffer commandBuffer,
2029 VkSubpassContents contents)
2030 {
2031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2032
2033 si_emit_cache_flush(cmd_buffer);
2034 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2035
2036 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2037 2048);
2038
2039 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2040 radv_cmd_buffer_clear_subpass(cmd_buffer);
2041 }
2042
2043 void radv_CmdDraw(
2044 VkCommandBuffer commandBuffer,
2045 uint32_t vertexCount,
2046 uint32_t instanceCount,
2047 uint32_t firstVertex,
2048 uint32_t firstInstance)
2049 {
2050 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2051 radv_cmd_buffer_flush_state(cmd_buffer);
2052
2053 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
2054
2055 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2056 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2057 if (loc->sgpr_idx != -1) {
2058 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2059 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
2060 radeon_emit(cmd_buffer->cs, firstVertex);
2061 radeon_emit(cmd_buffer->cs, firstInstance);
2062 }
2063 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2064 radeon_emit(cmd_buffer->cs, instanceCount);
2065
2066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2067 radeon_emit(cmd_buffer->cs, vertexCount);
2068 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2069 S_0287F0_USE_OPAQUE(0));
2070
2071 assert(cmd_buffer->cs->cdw <= cdw_max);
2072
2073 radv_cmd_buffer_trace_emit(cmd_buffer);
2074 }
2075
2076 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2077 {
2078 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2079
2080 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2081 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2082 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2083 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2084 primitive_reset_index);
2085 }
2086 }
2087
2088 void radv_CmdDrawIndexed(
2089 VkCommandBuffer commandBuffer,
2090 uint32_t indexCount,
2091 uint32_t instanceCount,
2092 uint32_t firstIndex,
2093 int32_t vertexOffset,
2094 uint32_t firstInstance)
2095 {
2096 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2097 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2098 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2099 uint64_t index_va;
2100
2101 radv_cmd_buffer_flush_state(cmd_buffer);
2102 radv_emit_primitive_reset_index(cmd_buffer);
2103
2104 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
2105
2106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2107 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2108
2109 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2110 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2111 if (loc->sgpr_idx != -1) {
2112 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2113 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
2114 radeon_emit(cmd_buffer->cs, vertexOffset);
2115 radeon_emit(cmd_buffer->cs, firstInstance);
2116 }
2117 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2118 radeon_emit(cmd_buffer->cs, instanceCount);
2119
2120 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2121 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2123 radeon_emit(cmd_buffer->cs, index_max_size);
2124 radeon_emit(cmd_buffer->cs, index_va);
2125 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2126 radeon_emit(cmd_buffer->cs, indexCount);
2127 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2128
2129 assert(cmd_buffer->cs->cdw <= cdw_max);
2130 radv_cmd_buffer_trace_emit(cmd_buffer);
2131 }
2132
2133 static void
2134 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2135 VkBuffer _buffer,
2136 VkDeviceSize offset,
2137 VkBuffer _count_buffer,
2138 VkDeviceSize count_offset,
2139 uint32_t draw_count,
2140 uint32_t stride,
2141 bool indexed)
2142 {
2143 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2144 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2145 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2146 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2147 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2148 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2149 indirect_va += offset + buffer->offset;
2150 uint64_t count_va = 0;
2151
2152 if (count_buffer) {
2153 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2154 count_va += count_offset + count_buffer->offset;
2155 }
2156
2157 if (!draw_count)
2158 return;
2159
2160 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2161
2162 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2163 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2164 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2165 assert(loc->sgpr_idx != -1);
2166 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2167 radeon_emit(cs, 1);
2168 radeon_emit(cs, indirect_va);
2169 radeon_emit(cs, indirect_va >> 32);
2170
2171 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2172 PKT3_DRAW_INDIRECT_MULTI,
2173 8, false));
2174 radeon_emit(cs, 0);
2175 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2176 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2177 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2178 radeon_emit(cs, draw_count); /* count */
2179 radeon_emit(cs, count_va); /* count_addr */
2180 radeon_emit(cs, count_va >> 32);
2181 radeon_emit(cs, stride); /* stride */
2182 radeon_emit(cs, di_src_sel);
2183 radv_cmd_buffer_trace_emit(cmd_buffer);
2184 }
2185
2186 static void
2187 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2188 VkBuffer buffer,
2189 VkDeviceSize offset,
2190 VkBuffer countBuffer,
2191 VkDeviceSize countBufferOffset,
2192 uint32_t maxDrawCount,
2193 uint32_t stride)
2194 {
2195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2196 radv_cmd_buffer_flush_state(cmd_buffer);
2197
2198 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2199 cmd_buffer->cs, 14);
2200
2201 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2202 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2203
2204 assert(cmd_buffer->cs->cdw <= cdw_max);
2205 }
2206
2207 static void
2208 radv_cmd_draw_indexed_indirect_count(
2209 VkCommandBuffer commandBuffer,
2210 VkBuffer buffer,
2211 VkDeviceSize offset,
2212 VkBuffer countBuffer,
2213 VkDeviceSize countBufferOffset,
2214 uint32_t maxDrawCount,
2215 uint32_t stride)
2216 {
2217 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2218 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2219 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2220 uint64_t index_va;
2221 radv_cmd_buffer_flush_state(cmd_buffer);
2222 radv_emit_primitive_reset_index(cmd_buffer);
2223
2224 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2225 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2226
2227 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2228
2229 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2230 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2231
2232 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2233 radeon_emit(cmd_buffer->cs, index_va);
2234 radeon_emit(cmd_buffer->cs, index_va >> 32);
2235
2236 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2237 radeon_emit(cmd_buffer->cs, index_max_size);
2238
2239 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2240 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2241
2242 assert(cmd_buffer->cs->cdw <= cdw_max);
2243 }
2244
2245 void radv_CmdDrawIndirect(
2246 VkCommandBuffer commandBuffer,
2247 VkBuffer buffer,
2248 VkDeviceSize offset,
2249 uint32_t drawCount,
2250 uint32_t stride)
2251 {
2252 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2253 VK_NULL_HANDLE, 0, drawCount, stride);
2254 }
2255
2256 void radv_CmdDrawIndexedIndirect(
2257 VkCommandBuffer commandBuffer,
2258 VkBuffer buffer,
2259 VkDeviceSize offset,
2260 uint32_t drawCount,
2261 uint32_t stride)
2262 {
2263 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2264 VK_NULL_HANDLE, 0, drawCount, stride);
2265 }
2266
2267 void radv_CmdDrawIndirectCountAMD(
2268 VkCommandBuffer commandBuffer,
2269 VkBuffer buffer,
2270 VkDeviceSize offset,
2271 VkBuffer countBuffer,
2272 VkDeviceSize countBufferOffset,
2273 uint32_t maxDrawCount,
2274 uint32_t stride)
2275 {
2276 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2277 countBuffer, countBufferOffset,
2278 maxDrawCount, stride);
2279 }
2280
2281 void radv_CmdDrawIndexedIndirectCountAMD(
2282 VkCommandBuffer commandBuffer,
2283 VkBuffer buffer,
2284 VkDeviceSize offset,
2285 VkBuffer countBuffer,
2286 VkDeviceSize countBufferOffset,
2287 uint32_t maxDrawCount,
2288 uint32_t stride)
2289 {
2290 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2291 countBuffer, countBufferOffset,
2292 maxDrawCount, stride);
2293 }
2294
2295 static void
2296 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2297 {
2298 radv_emit_compute_pipeline(cmd_buffer);
2299 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2300 VK_SHADER_STAGE_COMPUTE_BIT);
2301 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2302 VK_SHADER_STAGE_COMPUTE_BIT);
2303 si_emit_cache_flush(cmd_buffer);
2304 }
2305
2306 void radv_CmdDispatch(
2307 VkCommandBuffer commandBuffer,
2308 uint32_t x,
2309 uint32_t y,
2310 uint32_t z)
2311 {
2312 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2313
2314 radv_flush_compute_state(cmd_buffer);
2315
2316 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2317
2318 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2319 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2320 if (loc->sgpr_idx != -1) {
2321 assert(!loc->indirect);
2322 assert(loc->num_sgprs == 3);
2323 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2324 radeon_emit(cmd_buffer->cs, x);
2325 radeon_emit(cmd_buffer->cs, y);
2326 radeon_emit(cmd_buffer->cs, z);
2327 }
2328
2329 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2330 PKT3_SHADER_TYPE_S(1));
2331 radeon_emit(cmd_buffer->cs, x);
2332 radeon_emit(cmd_buffer->cs, y);
2333 radeon_emit(cmd_buffer->cs, z);
2334 radeon_emit(cmd_buffer->cs, 1);
2335
2336 assert(cmd_buffer->cs->cdw <= cdw_max);
2337 radv_cmd_buffer_trace_emit(cmd_buffer);
2338 }
2339
2340 void radv_CmdDispatchIndirect(
2341 VkCommandBuffer commandBuffer,
2342 VkBuffer _buffer,
2343 VkDeviceSize offset)
2344 {
2345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2346 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2347 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2348 va += buffer->offset + offset;
2349
2350 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2351
2352 radv_flush_compute_state(cmd_buffer);
2353
2354 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2355 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2356 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2357 if (loc->sgpr_idx != -1) {
2358 for (unsigned i = 0; i < 3; ++i) {
2359 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2360 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2361 COPY_DATA_DST_SEL(COPY_DATA_REG));
2362 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2363 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2364 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2365 radeon_emit(cmd_buffer->cs, 0);
2366 }
2367 }
2368
2369 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2370 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2371 PKT3_SHADER_TYPE_S(1));
2372 radeon_emit(cmd_buffer->cs, va);
2373 radeon_emit(cmd_buffer->cs, va >> 32);
2374 radeon_emit(cmd_buffer->cs, 1);
2375 } else {
2376 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2377 PKT3_SHADER_TYPE_S(1));
2378 radeon_emit(cmd_buffer->cs, 1);
2379 radeon_emit(cmd_buffer->cs, va);
2380 radeon_emit(cmd_buffer->cs, va >> 32);
2381
2382 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2383 PKT3_SHADER_TYPE_S(1));
2384 radeon_emit(cmd_buffer->cs, 0);
2385 radeon_emit(cmd_buffer->cs, 1);
2386 }
2387
2388 assert(cmd_buffer->cs->cdw <= cdw_max);
2389 radv_cmd_buffer_trace_emit(cmd_buffer);
2390 }
2391
2392 void radv_unaligned_dispatch(
2393 struct radv_cmd_buffer *cmd_buffer,
2394 uint32_t x,
2395 uint32_t y,
2396 uint32_t z)
2397 {
2398 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2399 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2400 uint32_t blocks[3], remainder[3];
2401
2402 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2403 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2404 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2405
2406 /* If aligned, these should be an entire block size, not 0 */
2407 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2408 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2409 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2410
2411 radv_flush_compute_state(cmd_buffer);
2412
2413 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2414
2415 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2416 radeon_emit(cmd_buffer->cs,
2417 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2418 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2419 radeon_emit(cmd_buffer->cs,
2420 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2421 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2422 radeon_emit(cmd_buffer->cs,
2423 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2424 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2425
2426 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2427 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2428 if (loc->sgpr_idx != -1) {
2429 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2430 radeon_emit(cmd_buffer->cs, blocks[0]);
2431 radeon_emit(cmd_buffer->cs, blocks[1]);
2432 radeon_emit(cmd_buffer->cs, blocks[2]);
2433 }
2434 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2435 PKT3_SHADER_TYPE_S(1));
2436 radeon_emit(cmd_buffer->cs, blocks[0]);
2437 radeon_emit(cmd_buffer->cs, blocks[1]);
2438 radeon_emit(cmd_buffer->cs, blocks[2]);
2439 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2440 S_00B800_PARTIAL_TG_EN(1));
2441
2442 assert(cmd_buffer->cs->cdw <= cdw_max);
2443 radv_cmd_buffer_trace_emit(cmd_buffer);
2444 }
2445
2446 void radv_CmdEndRenderPass(
2447 VkCommandBuffer commandBuffer)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450
2451 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2452
2453 si_emit_cache_flush(cmd_buffer);
2454 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2455
2456 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2457 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2458 radv_handle_subpass_image_transition(cmd_buffer,
2459 (VkAttachmentReference){i, layout});
2460 }
2461
2462 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2463
2464 cmd_buffer->state.pass = NULL;
2465 cmd_buffer->state.subpass = NULL;
2466 cmd_buffer->state.attachments = NULL;
2467 cmd_buffer->state.framebuffer = NULL;
2468 }
2469
2470
2471 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2472 struct radv_image *image)
2473 {
2474
2475 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2476 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2477
2478 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2479 image->htile.size, 0xffffffff);
2480
2481 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2482 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2483 RADV_CMD_FLAG_INV_VMEM_L1 |
2484 RADV_CMD_FLAG_INV_GLOBAL_L2;
2485 }
2486
2487 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2488 struct radv_image *image,
2489 VkImageLayout src_layout,
2490 VkImageLayout dst_layout,
2491 VkImageSubresourceRange range,
2492 VkImageAspectFlags pending_clears)
2493 {
2494 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2495 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2496 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2497 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2498 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2499 /* The clear will initialize htile. */
2500 return;
2501 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2502 radv_layout_has_htile(image, dst_layout)) {
2503 /* TODO: merge with the clear if applicable */
2504 radv_initialize_htile(cmd_buffer, image);
2505 } else if (!radv_layout_has_htile(image, src_layout) &&
2506 radv_layout_has_htile(image, dst_layout)) {
2507 radv_initialize_htile(cmd_buffer, image);
2508 } else if ((radv_layout_has_htile(image, src_layout) &&
2509 !radv_layout_has_htile(image, dst_layout)) ||
2510 (radv_layout_is_htile_compressed(image, src_layout) &&
2511 !radv_layout_is_htile_compressed(image, dst_layout))) {
2512
2513 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2514 range.baseMipLevel = 0;
2515 range.levelCount = 1;
2516
2517 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2518 }
2519 }
2520
2521 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2522 struct radv_image *image, uint32_t value)
2523 {
2524 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2525 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2526
2527 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2528 image->cmask.size, value);
2529
2530 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2531 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2532 RADV_CMD_FLAG_INV_VMEM_L1 |
2533 RADV_CMD_FLAG_INV_GLOBAL_L2;
2534 }
2535
2536 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2537 struct radv_image *image,
2538 VkImageLayout src_layout,
2539 VkImageLayout dst_layout,
2540 unsigned src_queue_mask,
2541 unsigned dst_queue_mask,
2542 VkImageSubresourceRange range,
2543 VkImageAspectFlags pending_clears)
2544 {
2545 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2546 if (image->fmask.size)
2547 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2548 else
2549 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2550 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2551 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2552 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2553 }
2554 }
2555
2556 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2557 struct radv_image *image, uint32_t value)
2558 {
2559
2560 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2561 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2562
2563 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2564 image->surface.dcc_size, value);
2565
2566 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2567 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2568 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2569 RADV_CMD_FLAG_INV_VMEM_L1 |
2570 RADV_CMD_FLAG_INV_GLOBAL_L2;
2571 }
2572
2573 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2574 struct radv_image *image,
2575 VkImageLayout src_layout,
2576 VkImageLayout dst_layout,
2577 unsigned src_queue_mask,
2578 unsigned dst_queue_mask,
2579 VkImageSubresourceRange range,
2580 VkImageAspectFlags pending_clears)
2581 {
2582 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2583 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2584 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2585 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2586 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2587 }
2588 }
2589
2590 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2591 struct radv_image *image,
2592 VkImageLayout src_layout,
2593 VkImageLayout dst_layout,
2594 int src_family,
2595 int dst_family,
2596 VkImageSubresourceRange range,
2597 VkImageAspectFlags pending_clears)
2598 {
2599 if (image->exclusive && src_family != dst_family) {
2600 /* This is an acquire or a release operation and there will be
2601 * a corresponding release/acquire. Do the transition in the
2602 * most flexible queue. */
2603
2604 assert(src_family == cmd_buffer->queue_family_index ||
2605 dst_family == cmd_buffer->queue_family_index);
2606
2607 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2608 return;
2609
2610 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2611 (src_family == RADV_QUEUE_GENERAL ||
2612 dst_family == RADV_QUEUE_GENERAL))
2613 return;
2614 }
2615
2616 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family);
2617 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family);
2618
2619 if (image->htile.size)
2620 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2621 dst_layout, range, pending_clears);
2622
2623 if (image->cmask.size)
2624 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2625 dst_layout, src_queue_mask,
2626 dst_queue_mask, range,
2627 pending_clears);
2628
2629 if (image->surface.dcc_size)
2630 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2631 dst_layout, src_queue_mask,
2632 dst_queue_mask, range,
2633 pending_clears);
2634 }
2635
2636 void radv_CmdPipelineBarrier(
2637 VkCommandBuffer commandBuffer,
2638 VkPipelineStageFlags srcStageMask,
2639 VkPipelineStageFlags destStageMask,
2640 VkBool32 byRegion,
2641 uint32_t memoryBarrierCount,
2642 const VkMemoryBarrier* pMemoryBarriers,
2643 uint32_t bufferMemoryBarrierCount,
2644 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2645 uint32_t imageMemoryBarrierCount,
2646 const VkImageMemoryBarrier* pImageMemoryBarriers)
2647 {
2648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2649 VkAccessFlags src_flags = 0;
2650 VkAccessFlags dst_flags = 0;
2651 uint32_t b;
2652 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2653 src_flags |= pMemoryBarriers[i].srcAccessMask;
2654 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2655 }
2656
2657 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2658 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2659 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2660 }
2661
2662 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2663 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2664 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2665 }
2666
2667 enum radv_cmd_flush_bits flush_bits = 0;
2668 for_each_bit(b, src_flags) {
2669 switch ((VkAccessFlagBits)(1 << b)) {
2670 case VK_ACCESS_SHADER_WRITE_BIT:
2671 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2672 break;
2673 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2674 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2675 break;
2676 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2677 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2678 break;
2679 case VK_ACCESS_TRANSFER_WRITE_BIT:
2680 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2681 break;
2682 default:
2683 break;
2684 }
2685 }
2686 cmd_buffer->state.flush_bits |= flush_bits;
2687
2688 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2689 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2690 radv_handle_image_transition(cmd_buffer, image,
2691 pImageMemoryBarriers[i].oldLayout,
2692 pImageMemoryBarriers[i].newLayout,
2693 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2694 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2695 pImageMemoryBarriers[i].subresourceRange,
2696 0);
2697 }
2698
2699 flush_bits = 0;
2700
2701 for_each_bit(b, dst_flags) {
2702 switch ((VkAccessFlagBits)(1 << b)) {
2703 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2704 case VK_ACCESS_INDEX_READ_BIT:
2705 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2706 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2707 break;
2708 case VK_ACCESS_UNIFORM_READ_BIT:
2709 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2710 break;
2711 case VK_ACCESS_SHADER_READ_BIT:
2712 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2713 break;
2714 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2715 case VK_ACCESS_TRANSFER_READ_BIT:
2716 case VK_ACCESS_TRANSFER_WRITE_BIT:
2717 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2718 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2719 default:
2720 break;
2721 }
2722 }
2723
2724 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2725 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2726
2727 cmd_buffer->state.flush_bits |= flush_bits;
2728 }
2729
2730
2731 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2732 struct radv_event *event,
2733 VkPipelineStageFlags stageMask,
2734 unsigned value)
2735 {
2736 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2737 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2738
2739 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2740
2741 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2742
2743 /* TODO: this is overkill. Probably should figure something out from
2744 * the stage mask. */
2745
2746 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2747 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2748 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2749 EVENT_INDEX(5));
2750 radeon_emit(cs, va);
2751 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2752 radeon_emit(cs, 2);
2753 radeon_emit(cs, 0);
2754 }
2755
2756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2757 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2758 EVENT_INDEX(5));
2759 radeon_emit(cs, va);
2760 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2761 radeon_emit(cs, value);
2762 radeon_emit(cs, 0);
2763
2764 assert(cmd_buffer->cs->cdw <= cdw_max);
2765 }
2766
2767 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2768 VkEvent _event,
2769 VkPipelineStageFlags stageMask)
2770 {
2771 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2772 RADV_FROM_HANDLE(radv_event, event, _event);
2773
2774 write_event(cmd_buffer, event, stageMask, 1);
2775 }
2776
2777 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2778 VkEvent _event,
2779 VkPipelineStageFlags stageMask)
2780 {
2781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2782 RADV_FROM_HANDLE(radv_event, event, _event);
2783
2784 write_event(cmd_buffer, event, stageMask, 0);
2785 }
2786
2787 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2788 uint32_t eventCount,
2789 const VkEvent* pEvents,
2790 VkPipelineStageFlags srcStageMask,
2791 VkPipelineStageFlags dstStageMask,
2792 uint32_t memoryBarrierCount,
2793 const VkMemoryBarrier* pMemoryBarriers,
2794 uint32_t bufferMemoryBarrierCount,
2795 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2796 uint32_t imageMemoryBarrierCount,
2797 const VkImageMemoryBarrier* pImageMemoryBarriers)
2798 {
2799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2800 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2801
2802 for (unsigned i = 0; i < eventCount; ++i) {
2803 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2804 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2805
2806 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2807
2808 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2809
2810 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2811 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2812 radeon_emit(cs, va);
2813 radeon_emit(cs, va >> 32);
2814 radeon_emit(cs, 1); /* reference value */
2815 radeon_emit(cs, 0xffffffff); /* mask */
2816 radeon_emit(cs, 4); /* poll interval */
2817
2818 assert(cmd_buffer->cs->cdw <= cdw_max);
2819 }
2820
2821
2822 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2823 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2824
2825 radv_handle_image_transition(cmd_buffer, image,
2826 pImageMemoryBarriers[i].oldLayout,
2827 pImageMemoryBarriers[i].newLayout,
2828 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2829 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2830 pImageMemoryBarriers[i].subresourceRange,
2831 0);
2832 }
2833
2834 /* TODO: figure out how to do memory barriers without waiting */
2835 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2836 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2837 RADV_CMD_FLAG_INV_VMEM_L1 |
2838 RADV_CMD_FLAG_INV_SMEM_L1;
2839 }