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9fcef5a62d32fba9995ea0067013a22d62663260
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 #include "addrlib/gfx9/chip/gfx9_enum.h"
41
42 enum {
43 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
44 RADV_PREFETCH_VS = (1 << 1),
45 RADV_PREFETCH_TCS = (1 << 2),
46 RADV_PREFETCH_TES = (1 << 3),
47 RADV_PREFETCH_GS = (1 << 4),
48 RADV_PREFETCH_PS = (1 << 5),
49 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
50 RADV_PREFETCH_TCS |
51 RADV_PREFETCH_TES |
52 RADV_PREFETCH_GS |
53 RADV_PREFETCH_PS)
54 };
55
56 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
57 struct radv_image *image,
58 VkImageLayout src_layout,
59 VkImageLayout dst_layout,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 VkImageAspectFlags pending_clears);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111
112 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
113 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
114 src->viewport.count * sizeof(VkViewport))) {
115 typed_memcpy(dest->viewport.viewports,
116 src->viewport.viewports,
117 src->viewport.count);
118 dest_mask |= RADV_DYNAMIC_VIEWPORT;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
123 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
124 src->scissor.count * sizeof(VkRect2D))) {
125 typed_memcpy(dest->scissor.scissors,
126 src->scissor.scissors, src->scissor.count);
127 dest_mask |= RADV_DYNAMIC_SCISSOR;
128 }
129 }
130
131 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
132 if (dest->line_width != src->line_width) {
133 dest->line_width = src->line_width;
134 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
135 }
136 }
137
138 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
139 if (memcmp(&dest->depth_bias, &src->depth_bias,
140 sizeof(src->depth_bias))) {
141 dest->depth_bias = src->depth_bias;
142 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
143 }
144 }
145
146 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
147 if (memcmp(&dest->blend_constants, &src->blend_constants,
148 sizeof(src->blend_constants))) {
149 typed_memcpy(dest->blend_constants,
150 src->blend_constants, 4);
151 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
152 }
153 }
154
155 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
156 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
157 sizeof(src->depth_bounds))) {
158 dest->depth_bounds = src->depth_bounds;
159 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
160 }
161 }
162
163 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
164 if (memcmp(&dest->stencil_compare_mask,
165 &src->stencil_compare_mask,
166 sizeof(src->stencil_compare_mask))) {
167 dest->stencil_compare_mask = src->stencil_compare_mask;
168 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
173 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
174 sizeof(src->stencil_write_mask))) {
175 dest->stencil_write_mask = src->stencil_write_mask;
176 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
177 }
178 }
179
180 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
181 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
182 sizeof(src->stencil_reference))) {
183 dest->stencil_reference = src->stencil_reference;
184 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
185 }
186 }
187
188 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
189 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
190 src->discard_rectangle.count * sizeof(VkRect2D))) {
191 typed_memcpy(dest->discard_rectangle.rectangles,
192 src->discard_rectangle.rectangles,
193 src->discard_rectangle.count);
194 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
195 }
196 }
197
198 cmd_buffer->state.dirty |= dest_mask;
199 }
200
201 static void
202 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
203 struct radv_pipeline *pipeline)
204 {
205 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
206 struct radv_shader_info *info;
207
208 if (!pipeline->streamout_shader)
209 return;
210
211 info = &pipeline->streamout_shader->info.info;
212 for (int i = 0; i < MAX_SO_BUFFERS; i++)
213 so->stride_in_dw[i] = info->so.strides[i];
214
215 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
216 }
217
218 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
219 {
220 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
221 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
222 }
223
224 enum ring_type radv_queue_family_to_ring(int f) {
225 switch (f) {
226 case RADV_QUEUE_GENERAL:
227 return RING_GFX;
228 case RADV_QUEUE_COMPUTE:
229 return RING_COMPUTE;
230 case RADV_QUEUE_TRANSFER:
231 return RING_DMA;
232 default:
233 unreachable("Unknown queue family");
234 }
235 }
236
237 static VkResult radv_create_cmd_buffer(
238 struct radv_device * device,
239 struct radv_cmd_pool * pool,
240 VkCommandBufferLevel level,
241 VkCommandBuffer* pCommandBuffer)
242 {
243 struct radv_cmd_buffer *cmd_buffer;
244 unsigned ring;
245 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
246 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
247 if (cmd_buffer == NULL)
248 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
249
250 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251 cmd_buffer->device = device;
252 cmd_buffer->pool = pool;
253 cmd_buffer->level = level;
254
255 if (pool) {
256 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
257 cmd_buffer->queue_family_index = pool->queue_family_index;
258
259 } else {
260 /* Init the pool_link so we can safely call list_del when we destroy
261 * the command buffer
262 */
263 list_inithead(&cmd_buffer->pool_link);
264 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
265 }
266
267 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
268
269 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
270 if (!cmd_buffer->cs) {
271 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
273 }
274
275 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
276
277 list_inithead(&cmd_buffer->upload.list);
278
279 return VK_SUCCESS;
280 }
281
282 static void
283 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
284 {
285 list_del(&cmd_buffer->pool_link);
286
287 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
288 &cmd_buffer->upload.list, list) {
289 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
290 list_del(&up->list);
291 free(up);
292 }
293
294 if (cmd_buffer->upload.upload_bo)
295 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
296 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
297
298 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
299 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
300
301 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
302 }
303
304 static VkResult
305 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
306 {
307
308 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 cmd_buffer->push_constant_stages = 0;
318 cmd_buffer->scratch_size_needed = 0;
319 cmd_buffer->compute_scratch_size_needed = 0;
320 cmd_buffer->esgs_ring_size_needed = 0;
321 cmd_buffer->gsvs_ring_size_needed = 0;
322 cmd_buffer->tess_rings_needed = false;
323 cmd_buffer->sample_positions_needed = false;
324
325 if (cmd_buffer->upload.upload_bo)
326 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
327 cmd_buffer->upload.upload_bo);
328 cmd_buffer->upload.offset = 0;
329
330 cmd_buffer->record_result = VK_SUCCESS;
331
332 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
333 cmd_buffer->descriptors[i].dirty = 0;
334 cmd_buffer->descriptors[i].valid = 0;
335 cmd_buffer->descriptors[i].push_dirty = false;
336 }
337
338 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
339 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
340 unsigned eop_bug_offset;
341 void *fence_ptr;
342
343 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
344 &cmd_buffer->gfx9_fence_offset,
345 &fence_ptr);
346 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
347
348 /* Allocate a buffer for the EOP bug on GFX9. */
349 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
350 &eop_bug_offset, &fence_ptr);
351 cmd_buffer->gfx9_eop_bug_va =
352 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
353 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
354 }
355
356 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
357
358 return cmd_buffer->record_result;
359 }
360
361 static bool
362 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
363 uint64_t min_needed)
364 {
365 uint64_t new_size;
366 struct radeon_winsys_bo *bo;
367 struct radv_cmd_buffer_upload *upload;
368 struct radv_device *device = cmd_buffer->device;
369
370 new_size = MAX2(min_needed, 16 * 1024);
371 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
372
373 bo = device->ws->buffer_create(device->ws,
374 new_size, 4096,
375 RADEON_DOMAIN_GTT,
376 RADEON_FLAG_CPU_ACCESS|
377 RADEON_FLAG_NO_INTERPROCESS_SHARING |
378 RADEON_FLAG_32BIT);
379
380 if (!bo) {
381 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
382 return false;
383 }
384
385 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
386 if (cmd_buffer->upload.upload_bo) {
387 upload = malloc(sizeof(*upload));
388
389 if (!upload) {
390 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
391 device->ws->buffer_destroy(bo);
392 return false;
393 }
394
395 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
396 list_add(&upload->list, &cmd_buffer->upload.list);
397 }
398
399 cmd_buffer->upload.upload_bo = bo;
400 cmd_buffer->upload.size = new_size;
401 cmd_buffer->upload.offset = 0;
402 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
403
404 if (!cmd_buffer->upload.map) {
405 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
406 return false;
407 }
408
409 return true;
410 }
411
412 bool
413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
414 unsigned size,
415 unsigned alignment,
416 unsigned *out_offset,
417 void **ptr)
418 {
419 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
420 if (offset + size > cmd_buffer->upload.size) {
421 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
422 return false;
423 offset = 0;
424 }
425
426 *out_offset = offset;
427 *ptr = cmd_buffer->upload.map + offset;
428
429 cmd_buffer->upload.offset = offset + size;
430 return true;
431 }
432
433 bool
434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
435 unsigned size, unsigned alignment,
436 const void *data, unsigned *out_offset)
437 {
438 uint8_t *ptr;
439
440 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
441 out_offset, (void **)&ptr))
442 return false;
443
444 if (ptr)
445 memcpy(ptr, data, size);
446
447 return true;
448 }
449
450 static void
451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
452 unsigned count, const uint32_t *data)
453 {
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455
456 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
457
458 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
459 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
460 S_370_WR_CONFIRM(1) |
461 S_370_ENGINE_SEL(V_370_ME));
462 radeon_emit(cs, va);
463 radeon_emit(cs, va >> 32);
464 radeon_emit_array(cs, data, count);
465 }
466
467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
468 {
469 struct radv_device *device = cmd_buffer->device;
470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
471 uint64_t va;
472
473 va = radv_buffer_get_va(device->trace_bo);
474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
475 va += 4;
476
477 ++cmd_buffer->state.trace_id;
478 radv_emit_write_data_packet(cmd_buffer, va, 1,
479 &cmd_buffer->state.trace_id);
480
481 radeon_check_space(cmd_buffer->device->ws, cs, 2);
482
483 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
484 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
485 }
486
487 static void
488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
489 enum radv_cmd_flush_bits flags)
490 {
491 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
492 uint32_t *ptr = NULL;
493 uint64_t va = 0;
494
495 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
496 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
497
498 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
499 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
500 cmd_buffer->gfx9_fence_offset;
501 ptr = &cmd_buffer->gfx9_fence_idx;
502 }
503
504 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
505
506 /* Force wait for graphics or compute engines to be idle. */
507 si_cs_emit_cache_flush(cmd_buffer->cs,
508 cmd_buffer->device->physical_device->rad_info.chip_class,
509 ptr, va,
510 radv_cmd_buffer_uses_mec(cmd_buffer),
511 flags, cmd_buffer->gfx9_eop_bug_va);
512 }
513
514 if (unlikely(cmd_buffer->device->trace_bo))
515 radv_cmd_buffer_trace_emit(cmd_buffer);
516 }
517
518 static void
519 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
520 struct radv_pipeline *pipeline, enum ring_type ring)
521 {
522 struct radv_device *device = cmd_buffer->device;
523 uint32_t data[2];
524 uint64_t va;
525
526 va = radv_buffer_get_va(device->trace_bo);
527
528 switch (ring) {
529 case RING_GFX:
530 va += 8;
531 break;
532 case RING_COMPUTE:
533 va += 16;
534 break;
535 default:
536 assert(!"invalid ring type");
537 }
538
539 data[0] = (uintptr_t)pipeline;
540 data[1] = (uintptr_t)pipeline >> 32;
541
542 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
543 }
544
545 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
546 VkPipelineBindPoint bind_point,
547 struct radv_descriptor_set *set,
548 unsigned idx)
549 {
550 struct radv_descriptor_state *descriptors_state =
551 radv_get_descriptors_state(cmd_buffer, bind_point);
552
553 descriptors_state->sets[idx] = set;
554
555 descriptors_state->valid |= (1u << idx); /* active descriptors */
556 descriptors_state->dirty |= (1u << idx);
557 }
558
559 static void
560 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
561 VkPipelineBindPoint bind_point)
562 {
563 struct radv_descriptor_state *descriptors_state =
564 radv_get_descriptors_state(cmd_buffer, bind_point);
565 struct radv_device *device = cmd_buffer->device;
566 uint32_t data[MAX_SETS * 2] = {};
567 uint64_t va;
568 unsigned i;
569 va = radv_buffer_get_va(device->trace_bo) + 24;
570
571 for_each_bit(i, descriptors_state->valid) {
572 struct radv_descriptor_set *set = descriptors_state->sets[i];
573 data[i * 2] = (uintptr_t)set;
574 data[i * 2 + 1] = (uintptr_t)set >> 32;
575 }
576
577 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
578 }
579
580 struct radv_userdata_info *
581 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
582 gl_shader_stage stage,
583 int idx)
584 {
585 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
586 return &shader->info.user_sgprs_locs.shader_data[idx];
587 }
588
589 static void
590 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline,
592 gl_shader_stage stage,
593 int idx, uint64_t va)
594 {
595 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
596 uint32_t base_reg = pipeline->user_data_0[stage];
597 if (loc->sgpr_idx == -1)
598 return;
599
600 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
601 assert(!loc->indirect);
602
603 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
604 base_reg + loc->sgpr_idx * 4, va, false);
605 }
606
607 static void
608 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
609 struct radv_pipeline *pipeline,
610 struct radv_descriptor_state *descriptors_state,
611 gl_shader_stage stage)
612 {
613 struct radv_device *device = cmd_buffer->device;
614 struct radeon_cmdbuf *cs = cmd_buffer->cs;
615 uint32_t sh_base = pipeline->user_data_0[stage];
616 struct radv_userdata_locations *locs =
617 &pipeline->shaders[stage]->info.user_sgprs_locs;
618 unsigned mask = locs->descriptor_sets_enabled;
619
620 mask &= descriptors_state->dirty & descriptors_state->valid;
621
622 while (mask) {
623 int start, count;
624
625 u_bit_scan_consecutive_range(&mask, &start, &count);
626
627 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
628 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
629
630 radv_emit_shader_pointer_head(cs, sh_offset, count,
631 HAVE_32BIT_POINTERS);
632 for (int i = 0; i < count; i++) {
633 struct radv_descriptor_set *set =
634 descriptors_state->sets[start + i];
635
636 radv_emit_shader_pointer_body(device, cs, set->va,
637 HAVE_32BIT_POINTERS);
638 }
639 }
640 }
641
642 static void
643 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 int num_samples = pipeline->graphics.ms.num_samples;
647 struct radv_multisample_state *ms = &pipeline->graphics.ms;
648 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
649
650 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
651 cmd_buffer->sample_positions_needed = true;
652
653 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
654 return;
655
656 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
657 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
658 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
659
660 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
661
662 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
663
664 /* GFX9: Flush DFSM when the AA mode changes. */
665 if (cmd_buffer->device->dfsm_allowed) {
666 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
667 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
668 }
669 }
670
671 static void
672 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 uint64_t va;
676
677 if (!shader)
678 return;
679
680 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
681
682 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
683 }
684
685 static void
686 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
687 struct radv_pipeline *pipeline,
688 bool vertex_stage_only)
689 {
690 struct radv_cmd_state *state = &cmd_buffer->state;
691 uint32_t mask = state->prefetch_L2_mask;
692
693 if (vertex_stage_only) {
694 /* Fast prefetch path for starting draws as soon as possible.
695 */
696 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
697 RADV_PREFETCH_VBO_DESCRIPTORS);
698 }
699
700 if (mask & RADV_PREFETCH_VS)
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_VERTEX]);
703
704 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
705 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
706
707 if (mask & RADV_PREFETCH_TCS)
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
710
711 if (mask & RADV_PREFETCH_TES)
712 radv_emit_shader_prefetch(cmd_buffer,
713 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
714
715 if (mask & RADV_PREFETCH_GS) {
716 radv_emit_shader_prefetch(cmd_buffer,
717 pipeline->shaders[MESA_SHADER_GEOMETRY]);
718 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
719 }
720
721 if (mask & RADV_PREFETCH_PS)
722 radv_emit_shader_prefetch(cmd_buffer,
723 pipeline->shaders[MESA_SHADER_FRAGMENT]);
724
725 state->prefetch_L2_mask &= ~mask;
726 }
727
728 static void
729 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
730 {
731 if (!cmd_buffer->device->physical_device->rbplus_allowed)
732 return;
733
734 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
735 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
736 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
737
738 unsigned sx_ps_downconvert = 0;
739 unsigned sx_blend_opt_epsilon = 0;
740 unsigned sx_blend_opt_control = 0;
741
742 for (unsigned i = 0; i < subpass->color_count; ++i) {
743 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
744 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
745 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
746 continue;
747 }
748
749 int idx = subpass->color_attachments[i].attachment;
750 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
751
752 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
753 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
754 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
755 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
756
757 bool has_alpha, has_rgb;
758
759 /* Set if RGB and A are present. */
760 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
761
762 if (format == V_028C70_COLOR_8 ||
763 format == V_028C70_COLOR_16 ||
764 format == V_028C70_COLOR_32)
765 has_rgb = !has_alpha;
766 else
767 has_rgb = true;
768
769 /* Check the colormask and export format. */
770 if (!(colormask & 0x7))
771 has_rgb = false;
772 if (!(colormask & 0x8))
773 has_alpha = false;
774
775 if (spi_format == V_028714_SPI_SHADER_ZERO) {
776 has_rgb = false;
777 has_alpha = false;
778 }
779
780 /* Disable value checking for disabled channels. */
781 if (!has_rgb)
782 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
783 if (!has_alpha)
784 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
785
786 /* Enable down-conversion for 32bpp and smaller formats. */
787 switch (format) {
788 case V_028C70_COLOR_8:
789 case V_028C70_COLOR_8_8:
790 case V_028C70_COLOR_8_8_8_8:
791 /* For 1 and 2-channel formats, use the superset thereof. */
792 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
793 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
794 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
795 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
796 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
797 }
798 break;
799
800 case V_028C70_COLOR_5_6_5:
801 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
802 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
803 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
804 }
805 break;
806
807 case V_028C70_COLOR_1_5_5_5:
808 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
810 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
811 }
812 break;
813
814 case V_028C70_COLOR_4_4_4_4:
815 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
816 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
817 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
818 }
819 break;
820
821 case V_028C70_COLOR_32:
822 if (swap == V_028C70_SWAP_STD &&
823 spi_format == V_028714_SPI_SHADER_32_R)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
825 else if (swap == V_028C70_SWAP_ALT_REV &&
826 spi_format == V_028714_SPI_SHADER_32_AR)
827 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
828 break;
829
830 case V_028C70_COLOR_16:
831 case V_028C70_COLOR_16_16:
832 /* For 1-channel formats, use the superset thereof. */
833 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
834 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
835 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
836 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
837 if (swap == V_028C70_SWAP_STD ||
838 swap == V_028C70_SWAP_STD_REV)
839 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
840 else
841 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
842 }
843 break;
844
845 case V_028C70_COLOR_10_11_11:
846 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
847 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
848 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
849 }
850 break;
851
852 case V_028C70_COLOR_2_10_10_10:
853 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
854 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
855 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
856 }
857 break;
858 }
859 }
860
861 for (unsigned i = subpass->color_count; i < 8; ++i) {
862 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
863 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
864 }
865 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
866 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
867 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
868 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
869 }
870
871 static void
872 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
873 {
874 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
875
876 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
877 return;
878
879 radv_update_multisample_state(cmd_buffer, pipeline);
880
881 cmd_buffer->scratch_size_needed =
882 MAX2(cmd_buffer->scratch_size_needed,
883 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
884
885 if (!cmd_buffer->state.emitted_pipeline ||
886 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
887 pipeline->graphics.can_use_guardband)
888 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
889
890 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
891
892 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
893 if (!pipeline->shaders[i])
894 continue;
895
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->shaders[i]->bo);
898 }
899
900 if (radv_pipeline_has_gs(pipeline))
901 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
902 pipeline->gs_copy_shader->bo);
903
904 if (unlikely(cmd_buffer->device->trace_bo))
905 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
906
907 cmd_buffer->state.emitted_pipeline = pipeline;
908
909 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
910 }
911
912 static void
913 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
914 {
915 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
916 cmd_buffer->state.dynamic.viewport.viewports);
917 }
918
919 static void
920 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
921 {
922 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
923
924 si_write_scissors(cmd_buffer->cs, 0, count,
925 cmd_buffer->state.dynamic.scissor.scissors,
926 cmd_buffer->state.dynamic.viewport.viewports,
927 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
928 }
929
930 static void
931 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
932 {
933 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
934 return;
935
936 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
937 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
938 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
939 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
940 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
941 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
942 S_028214_BR_Y(rect.offset.y + rect.extent.height));
943 }
944 }
945
946 static void
947 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
948 {
949 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
952 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
953 }
954
955 static void
956 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
957 {
958 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
959
960 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
961 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
962 }
963
964 static void
965 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg_seq(cmd_buffer->cs,
970 R_028430_DB_STENCILREFMASK, 2);
971 radeon_emit(cmd_buffer->cs,
972 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
973 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
974 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
975 S_028430_STENCILOPVAL(1));
976 radeon_emit(cmd_buffer->cs,
977 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
978 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
979 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
980 S_028434_STENCILOPVAL_BF(1));
981 }
982
983 static void
984 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
985 {
986 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
989 fui(d->depth_bounds.min));
990 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
991 fui(d->depth_bounds.max));
992 }
993
994 static void
995 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
996 {
997 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
998 unsigned slope = fui(d->depth_bias.slope * 16.0f);
999 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1000
1001
1002 radeon_set_context_reg_seq(cmd_buffer->cs,
1003 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1004 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1005 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1006 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1007 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1008 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1009 }
1010
1011 static void
1012 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1013 int index,
1014 struct radv_attachment_info *att,
1015 struct radv_image *image,
1016 VkImageLayout layout)
1017 {
1018 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1019 struct radv_color_buffer_info *cb = &att->cb;
1020 uint32_t cb_color_info = cb->cb_color_info;
1021
1022 if (!radv_layout_dcc_compressed(image, layout,
1023 radv_image_queue_family_mask(image,
1024 cmd_buffer->queue_family_index,
1025 cmd_buffer->queue_family_index))) {
1026 cb_color_info &= C_028C70_DCC_ENABLE;
1027 }
1028
1029 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1030 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1032 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1035 radeon_emit(cmd_buffer->cs, cb_color_info);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1037 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1039 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1041 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1042
1043 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1044 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1045 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1046
1047 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1048 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1049 } else {
1050 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1052 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1055 radeon_emit(cmd_buffer->cs, cb_color_info);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1057 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1060 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1061 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1062
1063 if (is_vi) { /* DCC BASE */
1064 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1065 }
1066 }
1067 }
1068
1069 static void
1070 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_ds_buffer_info *ds,
1072 struct radv_image *image, VkImageLayout layout,
1073 bool requires_cond_write)
1074 {
1075 uint32_t db_z_info = ds->db_z_info;
1076 uint32_t db_z_info_reg;
1077
1078 if (!radv_image_is_tc_compat_htile(image))
1079 return;
1080
1081 if (!radv_layout_has_htile(image, layout,
1082 radv_image_queue_family_mask(image,
1083 cmd_buffer->queue_family_index,
1084 cmd_buffer->queue_family_index))) {
1085 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1086 }
1087
1088 db_z_info &= C_028040_ZRANGE_PRECISION;
1089
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 db_z_info_reg = R_028038_DB_Z_INFO;
1092 } else {
1093 db_z_info_reg = R_028040_DB_Z_INFO;
1094 }
1095
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet, otherwise we can update DB_Z_INFO directly.
1098 */
1099 if (requires_cond_write) {
1100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1101
1102 const uint32_t write_space = 0 << 8; /* register */
1103 const uint32_t poll_space = 1 << 4; /* memory */
1104 const uint32_t function = 3 << 0; /* equal to the reference */
1105 const uint32_t options = write_space | poll_space | function;
1106 radeon_emit(cmd_buffer->cs, options);
1107
1108 /* poll address - location of the depth clear value */
1109 uint64_t va = radv_buffer_get_va(image->bo);
1110 va += image->offset + image->clear_value_offset;
1111
1112 /* In presence of stencil format, we have to adjust the base
1113 * address because the first value is the stencil clear value.
1114 */
1115 if (vk_format_is_stencil(image->vk_format))
1116 va += 4;
1117
1118 radeon_emit(cmd_buffer->cs, va);
1119 radeon_emit(cmd_buffer->cs, va >> 32);
1120
1121 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1122 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1123 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1124 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1125 radeon_emit(cmd_buffer->cs, db_z_info);
1126 } else {
1127 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1128 }
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1190 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1191
1192 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1193 ds->pa_su_poly_offset_db_fmt_cntl);
1194 }
1195
1196 /**
1197 * Update the fast clear depth/stencil values if the image is bound as a
1198 * depth/stencil buffer.
1199 */
1200 static void
1201 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1202 struct radv_image *image,
1203 VkClearDepthStencilValue ds_clear_value,
1204 VkImageAspectFlags aspects)
1205 {
1206 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1207 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1208 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1209 struct radv_attachment_info *att;
1210 uint32_t att_idx;
1211
1212 if (!framebuffer || !subpass)
1213 return;
1214
1215 att_idx = subpass->depth_stencil_attachment.attachment;
1216 if (att_idx == VK_ATTACHMENT_UNUSED)
1217 return;
1218
1219 att = &framebuffer->attachments[att_idx];
1220 if (att->attachment->image != image)
1221 return;
1222
1223 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1224 radeon_emit(cs, ds_clear_value.stencil);
1225 radeon_emit(cs, fui(ds_clear_value.depth));
1226
1227 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1228 * only needed when clearing Z to 0.0.
1229 */
1230 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1231 ds_clear_value.depth == 0.0) {
1232 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1233
1234 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1235 layout, false);
1236 }
1237 }
1238
1239 /**
1240 * Set the clear depth/stencil values to the image's metadata.
1241 */
1242 static void
1243 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1244 struct radv_image *image,
1245 VkClearDepthStencilValue ds_clear_value,
1246 VkImageAspectFlags aspects)
1247 {
1248 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1249 uint64_t va = radv_buffer_get_va(image->bo);
1250 unsigned reg_offset = 0, reg_count = 0;
1251
1252 va += image->offset + image->clear_value_offset;
1253
1254 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1255 ++reg_count;
1256 } else {
1257 ++reg_offset;
1258 va += 4;
1259 }
1260 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1261 ++reg_count;
1262
1263 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1264 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1265 S_370_WR_CONFIRM(1) |
1266 S_370_ENGINE_SEL(V_370_PFP));
1267 radeon_emit(cs, va);
1268 radeon_emit(cs, va >> 32);
1269 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1270 radeon_emit(cs, ds_clear_value.stencil);
1271 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1272 radeon_emit(cs, fui(ds_clear_value.depth));
1273 }
1274
1275 /**
1276 * Update the clear depth/stencil values for this image.
1277 */
1278 void
1279 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1280 struct radv_image *image,
1281 VkClearDepthStencilValue ds_clear_value,
1282 VkImageAspectFlags aspects)
1283 {
1284 assert(radv_image_has_htile(image));
1285
1286 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1287
1288 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1289 aspects);
1290 }
1291
1292 /**
1293 * Load the clear depth/stencil values from the image's metadata.
1294 */
1295 static void
1296 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_image *image)
1298 {
1299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1300 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1301 uint64_t va = radv_buffer_get_va(image->bo);
1302 unsigned reg_offset = 0, reg_count = 0;
1303
1304 va += image->offset + image->clear_value_offset;
1305
1306 if (!radv_image_has_htile(image))
1307 return;
1308
1309 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1310 ++reg_count;
1311 } else {
1312 ++reg_offset;
1313 va += 4;
1314 }
1315 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1316 ++reg_count;
1317
1318 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1319
1320 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1321 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1322 radeon_emit(cs, va);
1323 radeon_emit(cs, va >> 32);
1324 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1325 radeon_emit(cs, reg_count);
1326 } else {
1327 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1328 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1329 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1330 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1331 radeon_emit(cs, va);
1332 radeon_emit(cs, va >> 32);
1333 radeon_emit(cs, reg >> 2);
1334 radeon_emit(cs, 0);
1335
1336 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1337 radeon_emit(cs, 0);
1338 }
1339 }
1340
1341 /*
1342 * With DCC some colors don't require CMASK elimination before being
1343 * used as a texture. This sets a predicate value to determine if the
1344 * cmask eliminate is required.
1345 */
1346 void
1347 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1348 struct radv_image *image, bool value)
1349 {
1350 uint64_t pred_val = value;
1351 uint64_t va = radv_buffer_get_va(image->bo);
1352 va += image->offset + image->fce_pred_offset;
1353
1354 assert(radv_image_has_dcc(image));
1355
1356 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1357 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1358 S_370_WR_CONFIRM(1) |
1359 S_370_ENGINE_SEL(V_370_PFP));
1360 radeon_emit(cmd_buffer->cs, va);
1361 radeon_emit(cmd_buffer->cs, va >> 32);
1362 radeon_emit(cmd_buffer->cs, pred_val);
1363 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1364 }
1365
1366 /**
1367 * Update the fast clear color values if the image is bound as a color buffer.
1368 */
1369 static void
1370 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1371 struct radv_image *image,
1372 int cb_idx,
1373 uint32_t color_values[2])
1374 {
1375 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1376 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 struct radv_attachment_info *att;
1379 uint32_t att_idx;
1380
1381 if (!framebuffer || !subpass)
1382 return;
1383
1384 att_idx = subpass->color_attachments[cb_idx].attachment;
1385 if (att_idx == VK_ATTACHMENT_UNUSED)
1386 return;
1387
1388 att = &framebuffer->attachments[att_idx];
1389 if (att->attachment->image != image)
1390 return;
1391
1392 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1393 radeon_emit(cs, color_values[0]);
1394 radeon_emit(cs, color_values[1]);
1395 }
1396
1397 /**
1398 * Set the clear color values to the image's metadata.
1399 */
1400 static void
1401 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1402 struct radv_image *image,
1403 uint32_t color_values[2])
1404 {
1405 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1406 uint64_t va = radv_buffer_get_va(image->bo);
1407
1408 va += image->offset + image->clear_value_offset;
1409
1410 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1411
1412 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1413 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1414 S_370_WR_CONFIRM(1) |
1415 S_370_ENGINE_SEL(V_370_PFP));
1416 radeon_emit(cs, va);
1417 radeon_emit(cs, va >> 32);
1418 radeon_emit(cs, color_values[0]);
1419 radeon_emit(cs, color_values[1]);
1420 }
1421
1422 /**
1423 * Update the clear color values for this image.
1424 */
1425 void
1426 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_image *image,
1428 int cb_idx,
1429 uint32_t color_values[2])
1430 {
1431 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1432
1433 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1434
1435 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1436 color_values);
1437 }
1438
1439 /**
1440 * Load the clear color values from the image's metadata.
1441 */
1442 static void
1443 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1444 struct radv_image *image,
1445 int cb_idx)
1446 {
1447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1448 uint64_t va = radv_buffer_get_va(image->bo);
1449
1450 va += image->offset + image->clear_value_offset;
1451
1452 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1453 return;
1454
1455 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1456
1457 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1458 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1459 radeon_emit(cs, va);
1460 radeon_emit(cs, va >> 32);
1461 radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
1462 radeon_emit(cs, 2);
1463 } else {
1464 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1465 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1466 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1467 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1468 COPY_DATA_COUNT_SEL);
1469 radeon_emit(cs, va);
1470 radeon_emit(cs, va >> 32);
1471 radeon_emit(cs, reg >> 2);
1472 radeon_emit(cs, 0);
1473
1474 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1475 radeon_emit(cs, 0);
1476 }
1477 }
1478
1479 static void
1480 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1481 {
1482 int i;
1483 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1484 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1485 unsigned num_bpp64_colorbufs = 0;
1486
1487 /* this may happen for inherited secondary recording */
1488 if (!framebuffer)
1489 return;
1490
1491 for (i = 0; i < 8; ++i) {
1492 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1493 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1494 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1495 continue;
1496 }
1497
1498 int idx = subpass->color_attachments[i].attachment;
1499 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1500 struct radv_image *image = att->attachment->image;
1501 VkImageLayout layout = subpass->color_attachments[i].layout;
1502
1503 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1504
1505 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1506 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1507
1508 radv_load_color_clear_metadata(cmd_buffer, image, i);
1509
1510 if (image->surface.bpe >= 8)
1511 num_bpp64_colorbufs++;
1512 }
1513
1514 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1515 int idx = subpass->depth_stencil_attachment.attachment;
1516 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1517 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1518 struct radv_image *image = att->attachment->image;
1519 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1520 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1521 cmd_buffer->queue_family_index,
1522 cmd_buffer->queue_family_index);
1523 /* We currently don't support writing decompressed HTILE */
1524 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1525 radv_layout_is_htile_compressed(image, layout, queue_mask));
1526
1527 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1528
1529 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1530 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1531 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1532 }
1533 radv_load_ds_clear_metadata(cmd_buffer, image);
1534 } else {
1535 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1536 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1537 else
1538 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1539
1540 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1541 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1542 }
1543 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1544 S_028208_BR_X(framebuffer->width) |
1545 S_028208_BR_Y(framebuffer->height));
1546
1547 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1548 uint8_t watermark = 4; /* Default value for VI. */
1549
1550 /* For optimal DCC performance. */
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1552 if (num_bpp64_colorbufs >= 5) {
1553 watermark = 8;
1554 } else {
1555 watermark = 6;
1556 }
1557 }
1558
1559 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1560 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1561 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1562 }
1563
1564 if (cmd_buffer->device->dfsm_allowed) {
1565 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1566 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1567 }
1568
1569 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1570 }
1571
1572 static void
1573 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1574 {
1575 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1576 struct radv_cmd_state *state = &cmd_buffer->state;
1577
1578 if (state->index_type != state->last_index_type) {
1579 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1580 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1581 2, state->index_type);
1582 } else {
1583 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1584 radeon_emit(cs, state->index_type);
1585 }
1586
1587 state->last_index_type = state->index_type;
1588 }
1589
1590 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1591 radeon_emit(cs, state->index_va);
1592 radeon_emit(cs, state->index_va >> 32);
1593
1594 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1595 radeon_emit(cs, state->max_index_count);
1596
1597 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1598 }
1599
1600 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1601 {
1602 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1603 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1604 uint32_t pa_sc_mode_cntl_1 =
1605 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1606 uint32_t db_count_control;
1607
1608 if(!cmd_buffer->state.active_occlusion_queries) {
1609 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1610 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1611 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1612 has_perfect_queries) {
1613 /* Re-enable out-of-order rasterization if the
1614 * bound pipeline supports it and if it's has
1615 * been disabled before starting any perfect
1616 * occlusion queries.
1617 */
1618 radeon_set_context_reg(cmd_buffer->cs,
1619 R_028A4C_PA_SC_MODE_CNTL_1,
1620 pa_sc_mode_cntl_1);
1621 }
1622 }
1623 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1624 } else {
1625 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1626 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1627
1628 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1629 db_count_control =
1630 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1631 S_028004_SAMPLE_RATE(sample_rate) |
1632 S_028004_ZPASS_ENABLE(1) |
1633 S_028004_SLICE_EVEN_ENABLE(1) |
1634 S_028004_SLICE_ODD_ENABLE(1);
1635
1636 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1637 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1638 has_perfect_queries) {
1639 /* If the bound pipeline has enabled
1640 * out-of-order rasterization, we should
1641 * disable it before starting any perfect
1642 * occlusion queries.
1643 */
1644 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1645
1646 radeon_set_context_reg(cmd_buffer->cs,
1647 R_028A4C_PA_SC_MODE_CNTL_1,
1648 pa_sc_mode_cntl_1);
1649 }
1650 } else {
1651 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1652 S_028004_SAMPLE_RATE(sample_rate);
1653 }
1654 }
1655
1656 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1657 }
1658
1659 static void
1660 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1661 {
1662 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1663
1664 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1665 radv_emit_viewport(cmd_buffer);
1666
1667 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1668 !cmd_buffer->device->physical_device->has_scissor_bug)
1669 radv_emit_scissor(cmd_buffer);
1670
1671 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1672 radv_emit_line_width(cmd_buffer);
1673
1674 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1675 radv_emit_blend_constants(cmd_buffer);
1676
1677 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1678 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1679 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1680 radv_emit_stencil(cmd_buffer);
1681
1682 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1683 radv_emit_depth_bounds(cmd_buffer);
1684
1685 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1686 radv_emit_depth_bias(cmd_buffer);
1687
1688 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1689 radv_emit_discard_rectangle(cmd_buffer);
1690
1691 cmd_buffer->state.dirty &= ~states;
1692 }
1693
1694 static void
1695 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1696 VkPipelineBindPoint bind_point)
1697 {
1698 struct radv_descriptor_state *descriptors_state =
1699 radv_get_descriptors_state(cmd_buffer, bind_point);
1700 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1701 unsigned bo_offset;
1702
1703 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1704 set->mapped_ptr,
1705 &bo_offset))
1706 return;
1707
1708 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1709 set->va += bo_offset;
1710 }
1711
1712 static void
1713 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1714 VkPipelineBindPoint bind_point)
1715 {
1716 struct radv_descriptor_state *descriptors_state =
1717 radv_get_descriptors_state(cmd_buffer, bind_point);
1718 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1719 uint32_t size = MAX_SETS * 4 * ptr_size;
1720 uint32_t offset;
1721 void *ptr;
1722
1723 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1724 256, &offset, &ptr))
1725 return;
1726
1727 for (unsigned i = 0; i < MAX_SETS; i++) {
1728 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1729 uint64_t set_va = 0;
1730 struct radv_descriptor_set *set = descriptors_state->sets[i];
1731 if (descriptors_state->valid & (1u << i))
1732 set_va = set->va;
1733 uptr[0] = set_va & 0xffffffff;
1734 if (ptr_size == 2)
1735 uptr[1] = set_va >> 32;
1736 }
1737
1738 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1739 va += offset;
1740
1741 if (cmd_buffer->state.pipeline) {
1742 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1743 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1744 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1745
1746 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1747 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1748 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1749
1750 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1751 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1752 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1753
1754 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1755 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1756 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1757
1758 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1759 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1760 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1761 }
1762
1763 if (cmd_buffer->state.compute_pipeline)
1764 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1765 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1766 }
1767
1768 static void
1769 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1770 VkShaderStageFlags stages)
1771 {
1772 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1773 VK_PIPELINE_BIND_POINT_COMPUTE :
1774 VK_PIPELINE_BIND_POINT_GRAPHICS;
1775 struct radv_descriptor_state *descriptors_state =
1776 radv_get_descriptors_state(cmd_buffer, bind_point);
1777 struct radv_cmd_state *state = &cmd_buffer->state;
1778 bool flush_indirect_descriptors;
1779
1780 if (!descriptors_state->dirty)
1781 return;
1782
1783 if (descriptors_state->push_dirty)
1784 radv_flush_push_descriptors(cmd_buffer, bind_point);
1785
1786 flush_indirect_descriptors =
1787 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1788 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1789 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1790 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1791
1792 if (flush_indirect_descriptors)
1793 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1794
1795 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1796 cmd_buffer->cs,
1797 MAX_SETS * MESA_SHADER_STAGES * 4);
1798
1799 if (cmd_buffer->state.pipeline) {
1800 radv_foreach_stage(stage, stages) {
1801 if (!cmd_buffer->state.pipeline->shaders[stage])
1802 continue;
1803
1804 radv_emit_descriptor_pointers(cmd_buffer,
1805 cmd_buffer->state.pipeline,
1806 descriptors_state, stage);
1807 }
1808 }
1809
1810 if (cmd_buffer->state.compute_pipeline &&
1811 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1812 radv_emit_descriptor_pointers(cmd_buffer,
1813 cmd_buffer->state.compute_pipeline,
1814 descriptors_state,
1815 MESA_SHADER_COMPUTE);
1816 }
1817
1818 descriptors_state->dirty = 0;
1819 descriptors_state->push_dirty = false;
1820
1821 assert(cmd_buffer->cs->cdw <= cdw_max);
1822
1823 if (unlikely(cmd_buffer->device->trace_bo))
1824 radv_save_descriptors(cmd_buffer, bind_point);
1825 }
1826
1827 static void
1828 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1829 VkShaderStageFlags stages)
1830 {
1831 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1832 ? cmd_buffer->state.compute_pipeline
1833 : cmd_buffer->state.pipeline;
1834 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1835 VK_PIPELINE_BIND_POINT_COMPUTE :
1836 VK_PIPELINE_BIND_POINT_GRAPHICS;
1837 struct radv_descriptor_state *descriptors_state =
1838 radv_get_descriptors_state(cmd_buffer, bind_point);
1839 struct radv_pipeline_layout *layout = pipeline->layout;
1840 struct radv_shader_variant *shader, *prev_shader;
1841 unsigned offset;
1842 void *ptr;
1843 uint64_t va;
1844
1845 stages &= cmd_buffer->push_constant_stages;
1846 if (!stages ||
1847 (!layout->push_constant_size && !layout->dynamic_offset_count))
1848 return;
1849
1850 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1851 16 * layout->dynamic_offset_count,
1852 256, &offset, &ptr))
1853 return;
1854
1855 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1856 memcpy((char*)ptr + layout->push_constant_size,
1857 descriptors_state->dynamic_buffers,
1858 16 * layout->dynamic_offset_count);
1859
1860 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1861 va += offset;
1862
1863 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1864 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1865
1866 prev_shader = NULL;
1867 radv_foreach_stage(stage, stages) {
1868 shader = radv_get_shader(pipeline, stage);
1869
1870 /* Avoid redundantly emitting the address for merged stages. */
1871 if (shader && shader != prev_shader) {
1872 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1873 AC_UD_PUSH_CONSTANTS, va);
1874
1875 prev_shader = shader;
1876 }
1877 }
1878
1879 cmd_buffer->push_constant_stages &= ~stages;
1880 assert(cmd_buffer->cs->cdw <= cdw_max);
1881 }
1882
1883 static void
1884 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1885 bool pipeline_is_dirty)
1886 {
1887 if ((pipeline_is_dirty ||
1888 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1889 cmd_buffer->state.pipeline->vertex_elements.count &&
1890 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1891 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1892 unsigned vb_offset;
1893 void *vb_ptr;
1894 uint32_t i = 0;
1895 uint32_t count = velems->count;
1896 uint64_t va;
1897
1898 /* allocate some descriptor state for vertex buffers */
1899 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1900 &vb_offset, &vb_ptr))
1901 return;
1902
1903 for (i = 0; i < count; i++) {
1904 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1905 uint32_t offset;
1906 int vb = velems->binding[i];
1907 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1908 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1909
1910 va = radv_buffer_get_va(buffer->bo);
1911
1912 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1913 va += offset + buffer->offset;
1914 desc[0] = va;
1915 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1916 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1917 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1918 else
1919 desc[2] = buffer->size - offset;
1920 desc[3] = velems->rsrc_word3[i];
1921 }
1922
1923 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1924 va += vb_offset;
1925
1926 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1927 AC_UD_VS_VERTEX_BUFFERS, va);
1928
1929 cmd_buffer->state.vb_va = va;
1930 cmd_buffer->state.vb_size = count * 16;
1931 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1932 }
1933 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1934 }
1935
1936 static void
1937 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1938 {
1939 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1940 struct radv_userdata_info *loc;
1941 uint32_t base_reg;
1942
1943 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1944 if (!radv_get_shader(pipeline, stage))
1945 continue;
1946
1947 loc = radv_lookup_user_sgpr(pipeline, stage,
1948 AC_UD_STREAMOUT_BUFFERS);
1949 if (loc->sgpr_idx == -1)
1950 continue;
1951
1952 base_reg = pipeline->user_data_0[stage];
1953
1954 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1955 base_reg + loc->sgpr_idx * 4, va, false);
1956 }
1957
1958 if (pipeline->gs_copy_shader) {
1959 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1960 if (loc->sgpr_idx != -1) {
1961 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1962
1963 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1964 base_reg + loc->sgpr_idx * 4, va, false);
1965 }
1966 }
1967 }
1968
1969 static void
1970 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1971 {
1972 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1973 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1974 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1975 unsigned so_offset;
1976 void *so_ptr;
1977 uint64_t va;
1978
1979 /* Allocate some descriptor state for streamout buffers. */
1980 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1981 MAX_SO_BUFFERS * 16, 256,
1982 &so_offset, &so_ptr))
1983 return;
1984
1985 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1986 struct radv_buffer *buffer = sb[i].buffer;
1987 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1988
1989 if (!(so->enabled_mask & (1 << i)))
1990 continue;
1991
1992 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1993
1994 va += sb[i].offset;
1995
1996 /* Set the descriptor.
1997 *
1998 * On VI, the format must be non-INVALID, otherwise
1999 * the buffer will be considered not bound and store
2000 * instructions will be no-ops.
2001 */
2002 desc[0] = va;
2003 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2004 desc[2] = 0xffffffff;
2005 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2009 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2010 }
2011
2012 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2013 va += so_offset;
2014
2015 radv_emit_streamout_buffers(cmd_buffer, va);
2016 }
2017
2018 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2019 }
2020
2021 static void
2022 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2023 {
2024 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2025 radv_flush_streamout_descriptors(cmd_buffer);
2026 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2027 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2028 }
2029
2030 static void
2031 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2032 bool instanced_draw, bool indirect_draw,
2033 uint32_t draw_vertex_count)
2034 {
2035 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2036 struct radv_cmd_state *state = &cmd_buffer->state;
2037 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2038 uint32_t ia_multi_vgt_param;
2039 int32_t primitive_reset_en;
2040
2041 /* Draw state. */
2042 ia_multi_vgt_param =
2043 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2044 indirect_draw, draw_vertex_count);
2045
2046 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2047 if (info->chip_class >= GFX9) {
2048 radeon_set_uconfig_reg_idx(cs,
2049 R_030960_IA_MULTI_VGT_PARAM,
2050 4, ia_multi_vgt_param);
2051 } else if (info->chip_class >= CIK) {
2052 radeon_set_context_reg_idx(cs,
2053 R_028AA8_IA_MULTI_VGT_PARAM,
2054 1, ia_multi_vgt_param);
2055 } else {
2056 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2057 ia_multi_vgt_param);
2058 }
2059 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2060 }
2061
2062 /* Primitive restart. */
2063 primitive_reset_en =
2064 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2065
2066 if (primitive_reset_en != state->last_primitive_reset_en) {
2067 state->last_primitive_reset_en = primitive_reset_en;
2068 if (info->chip_class >= GFX9) {
2069 radeon_set_uconfig_reg(cs,
2070 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2071 primitive_reset_en);
2072 } else {
2073 radeon_set_context_reg(cs,
2074 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2075 primitive_reset_en);
2076 }
2077 }
2078
2079 if (primitive_reset_en) {
2080 uint32_t primitive_reset_index =
2081 state->index_type ? 0xffffffffu : 0xffffu;
2082
2083 if (primitive_reset_index != state->last_primitive_reset_index) {
2084 radeon_set_context_reg(cs,
2085 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2086 primitive_reset_index);
2087 state->last_primitive_reset_index = primitive_reset_index;
2088 }
2089 }
2090 }
2091
2092 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2093 VkPipelineStageFlags src_stage_mask)
2094 {
2095 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2096 VK_PIPELINE_STAGE_TRANSFER_BIT |
2097 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2098 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2099 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2100 }
2101
2102 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2103 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2104 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2105 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2106 VK_PIPELINE_STAGE_TRANSFER_BIT |
2107 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2108 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2109 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2110 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2111 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2112 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2113 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2114 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2115 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2116 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2117 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2118 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2119 }
2120 }
2121
2122 static enum radv_cmd_flush_bits
2123 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2124 VkAccessFlags src_flags,
2125 struct radv_image *image)
2126 {
2127 bool flush_CB_meta = true, flush_DB_meta = true;
2128 enum radv_cmd_flush_bits flush_bits = 0;
2129 uint32_t b;
2130
2131 if (image) {
2132 if (!radv_image_has_CB_metadata(image))
2133 flush_CB_meta = false;
2134 if (!radv_image_has_htile(image))
2135 flush_DB_meta = false;
2136 }
2137
2138 for_each_bit(b, src_flags) {
2139 switch ((VkAccessFlagBits)(1 << b)) {
2140 case VK_ACCESS_SHADER_WRITE_BIT:
2141 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2142 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2143 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2144 break;
2145 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2146 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2147 if (flush_CB_meta)
2148 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2149 break;
2150 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2151 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2152 if (flush_DB_meta)
2153 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2154 break;
2155 case VK_ACCESS_TRANSFER_WRITE_BIT:
2156 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2157 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2158 RADV_CMD_FLAG_INV_GLOBAL_L2;
2159
2160 if (flush_CB_meta)
2161 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2162 if (flush_DB_meta)
2163 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2164 break;
2165 default:
2166 break;
2167 }
2168 }
2169 return flush_bits;
2170 }
2171
2172 static enum radv_cmd_flush_bits
2173 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2174 VkAccessFlags dst_flags,
2175 struct radv_image *image)
2176 {
2177 bool flush_CB_meta = true, flush_DB_meta = true;
2178 enum radv_cmd_flush_bits flush_bits = 0;
2179 bool flush_CB = true, flush_DB = true;
2180 bool image_is_coherent = false;
2181 uint32_t b;
2182
2183 if (image) {
2184 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2185 flush_CB = false;
2186 flush_DB = false;
2187 }
2188
2189 if (!radv_image_has_CB_metadata(image))
2190 flush_CB_meta = false;
2191 if (!radv_image_has_htile(image))
2192 flush_DB_meta = false;
2193
2194 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2195 if (image->info.samples == 1 &&
2196 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2197 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2198 !vk_format_is_stencil(image->vk_format)) {
2199 /* Single-sample color and single-sample depth
2200 * (not stencil) are coherent with shaders on
2201 * GFX9.
2202 */
2203 image_is_coherent = true;
2204 }
2205 }
2206 }
2207
2208 for_each_bit(b, dst_flags) {
2209 switch ((VkAccessFlagBits)(1 << b)) {
2210 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2211 case VK_ACCESS_INDEX_READ_BIT:
2212 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2213 break;
2214 case VK_ACCESS_UNIFORM_READ_BIT:
2215 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2216 break;
2217 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2218 case VK_ACCESS_TRANSFER_READ_BIT:
2219 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2220 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2221 RADV_CMD_FLAG_INV_GLOBAL_L2;
2222 break;
2223 case VK_ACCESS_SHADER_READ_BIT:
2224 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2225
2226 if (!image_is_coherent)
2227 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2228 break;
2229 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2230 if (flush_CB)
2231 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2232 if (flush_CB_meta)
2233 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2234 break;
2235 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2236 if (flush_DB)
2237 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2238 if (flush_DB_meta)
2239 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2240 break;
2241 default:
2242 break;
2243 }
2244 }
2245 return flush_bits;
2246 }
2247
2248 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2249 const struct radv_subpass_barrier *barrier)
2250 {
2251 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2252 NULL);
2253 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2254 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2255 NULL);
2256 }
2257
2258 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2259 struct radv_subpass_attachment att)
2260 {
2261 unsigned idx = att.attachment;
2262 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2263 VkImageSubresourceRange range;
2264 range.aspectMask = 0;
2265 range.baseMipLevel = view->base_mip;
2266 range.levelCount = 1;
2267 range.baseArrayLayer = view->base_layer;
2268 range.layerCount = cmd_buffer->state.framebuffer->layers;
2269
2270 radv_handle_image_transition(cmd_buffer,
2271 view->image,
2272 cmd_buffer->state.attachments[idx].current_layout,
2273 att.layout, 0, 0, &range,
2274 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2275
2276 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2277
2278
2279 }
2280
2281 void
2282 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2283 const struct radv_subpass *subpass, bool transitions)
2284 {
2285 if (transitions) {
2286 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2287
2288 for (unsigned i = 0; i < subpass->color_count; ++i) {
2289 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2290 radv_handle_subpass_image_transition(cmd_buffer,
2291 subpass->color_attachments[i]);
2292 }
2293
2294 for (unsigned i = 0; i < subpass->input_count; ++i) {
2295 radv_handle_subpass_image_transition(cmd_buffer,
2296 subpass->input_attachments[i]);
2297 }
2298
2299 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2300 radv_handle_subpass_image_transition(cmd_buffer,
2301 subpass->depth_stencil_attachment);
2302 }
2303 }
2304
2305 cmd_buffer->state.subpass = subpass;
2306
2307 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2308 }
2309
2310 static VkResult
2311 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2312 struct radv_render_pass *pass,
2313 const VkRenderPassBeginInfo *info)
2314 {
2315 struct radv_cmd_state *state = &cmd_buffer->state;
2316
2317 if (pass->attachment_count == 0) {
2318 state->attachments = NULL;
2319 return VK_SUCCESS;
2320 }
2321
2322 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2323 pass->attachment_count *
2324 sizeof(state->attachments[0]),
2325 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2326 if (state->attachments == NULL) {
2327 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2328 return cmd_buffer->record_result;
2329 }
2330
2331 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2332 struct radv_render_pass_attachment *att = &pass->attachments[i];
2333 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2334 VkImageAspectFlags clear_aspects = 0;
2335
2336 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2337 /* color attachment */
2338 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2339 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2340 }
2341 } else {
2342 /* depthstencil attachment */
2343 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2344 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2345 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2346 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2347 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2348 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2349 }
2350 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2351 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2352 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2353 }
2354 }
2355
2356 state->attachments[i].pending_clear_aspects = clear_aspects;
2357 state->attachments[i].cleared_views = 0;
2358 if (clear_aspects && info) {
2359 assert(info->clearValueCount > i);
2360 state->attachments[i].clear_value = info->pClearValues[i];
2361 }
2362
2363 state->attachments[i].current_layout = att->initial_layout;
2364 }
2365
2366 return VK_SUCCESS;
2367 }
2368
2369 VkResult radv_AllocateCommandBuffers(
2370 VkDevice _device,
2371 const VkCommandBufferAllocateInfo *pAllocateInfo,
2372 VkCommandBuffer *pCommandBuffers)
2373 {
2374 RADV_FROM_HANDLE(radv_device, device, _device);
2375 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2376
2377 VkResult result = VK_SUCCESS;
2378 uint32_t i;
2379
2380 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2381
2382 if (!list_empty(&pool->free_cmd_buffers)) {
2383 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2384
2385 list_del(&cmd_buffer->pool_link);
2386 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2387
2388 result = radv_reset_cmd_buffer(cmd_buffer);
2389 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2390 cmd_buffer->level = pAllocateInfo->level;
2391
2392 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2393 } else {
2394 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2395 &pCommandBuffers[i]);
2396 }
2397 if (result != VK_SUCCESS)
2398 break;
2399 }
2400
2401 if (result != VK_SUCCESS) {
2402 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2403 i, pCommandBuffers);
2404
2405 /* From the Vulkan 1.0.66 spec:
2406 *
2407 * "vkAllocateCommandBuffers can be used to create multiple
2408 * command buffers. If the creation of any of those command
2409 * buffers fails, the implementation must destroy all
2410 * successfully created command buffer objects from this
2411 * command, set all entries of the pCommandBuffers array to
2412 * NULL and return the error."
2413 */
2414 memset(pCommandBuffers, 0,
2415 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2416 }
2417
2418 return result;
2419 }
2420
2421 void radv_FreeCommandBuffers(
2422 VkDevice device,
2423 VkCommandPool commandPool,
2424 uint32_t commandBufferCount,
2425 const VkCommandBuffer *pCommandBuffers)
2426 {
2427 for (uint32_t i = 0; i < commandBufferCount; i++) {
2428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2429
2430 if (cmd_buffer) {
2431 if (cmd_buffer->pool) {
2432 list_del(&cmd_buffer->pool_link);
2433 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2434 } else
2435 radv_cmd_buffer_destroy(cmd_buffer);
2436
2437 }
2438 }
2439 }
2440
2441 VkResult radv_ResetCommandBuffer(
2442 VkCommandBuffer commandBuffer,
2443 VkCommandBufferResetFlags flags)
2444 {
2445 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2446 return radv_reset_cmd_buffer(cmd_buffer);
2447 }
2448
2449 VkResult radv_BeginCommandBuffer(
2450 VkCommandBuffer commandBuffer,
2451 const VkCommandBufferBeginInfo *pBeginInfo)
2452 {
2453 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2454 VkResult result = VK_SUCCESS;
2455
2456 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2457 /* If the command buffer has already been resetted with
2458 * vkResetCommandBuffer, no need to do it again.
2459 */
2460 result = radv_reset_cmd_buffer(cmd_buffer);
2461 if (result != VK_SUCCESS)
2462 return result;
2463 }
2464
2465 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2466 cmd_buffer->state.last_primitive_reset_en = -1;
2467 cmd_buffer->state.last_index_type = -1;
2468 cmd_buffer->state.last_num_instances = -1;
2469 cmd_buffer->state.last_vertex_offset = -1;
2470 cmd_buffer->state.last_first_instance = -1;
2471 cmd_buffer->state.predication_type = -1;
2472 cmd_buffer->usage_flags = pBeginInfo->flags;
2473
2474 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2475 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2476 assert(pBeginInfo->pInheritanceInfo);
2477 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2478 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2479
2480 struct radv_subpass *subpass =
2481 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2482
2483 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2484 if (result != VK_SUCCESS)
2485 return result;
2486
2487 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2488 }
2489
2490 if (unlikely(cmd_buffer->device->trace_bo)) {
2491 struct radv_device *device = cmd_buffer->device;
2492
2493 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2494 device->trace_bo);
2495
2496 radv_cmd_buffer_trace_emit(cmd_buffer);
2497 }
2498
2499 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2500
2501 return result;
2502 }
2503
2504 void radv_CmdBindVertexBuffers(
2505 VkCommandBuffer commandBuffer,
2506 uint32_t firstBinding,
2507 uint32_t bindingCount,
2508 const VkBuffer* pBuffers,
2509 const VkDeviceSize* pOffsets)
2510 {
2511 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2512 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2513 bool changed = false;
2514
2515 /* We have to defer setting up vertex buffer since we need the buffer
2516 * stride from the pipeline. */
2517
2518 assert(firstBinding + bindingCount <= MAX_VBS);
2519 for (uint32_t i = 0; i < bindingCount; i++) {
2520 uint32_t idx = firstBinding + i;
2521
2522 if (!changed &&
2523 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2524 vb[idx].offset != pOffsets[i])) {
2525 changed = true;
2526 }
2527
2528 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2529 vb[idx].offset = pOffsets[i];
2530
2531 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2532 vb[idx].buffer->bo);
2533 }
2534
2535 if (!changed) {
2536 /* No state changes. */
2537 return;
2538 }
2539
2540 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2541 }
2542
2543 void radv_CmdBindIndexBuffer(
2544 VkCommandBuffer commandBuffer,
2545 VkBuffer buffer,
2546 VkDeviceSize offset,
2547 VkIndexType indexType)
2548 {
2549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2550 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2551
2552 if (cmd_buffer->state.index_buffer == index_buffer &&
2553 cmd_buffer->state.index_offset == offset &&
2554 cmd_buffer->state.index_type == indexType) {
2555 /* No state changes. */
2556 return;
2557 }
2558
2559 cmd_buffer->state.index_buffer = index_buffer;
2560 cmd_buffer->state.index_offset = offset;
2561 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2562 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2563 cmd_buffer->state.index_va += index_buffer->offset + offset;
2564
2565 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2566 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2567 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2568 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2569 }
2570
2571
2572 static void
2573 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2574 VkPipelineBindPoint bind_point,
2575 struct radv_descriptor_set *set, unsigned idx)
2576 {
2577 struct radeon_winsys *ws = cmd_buffer->device->ws;
2578
2579 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2580
2581 assert(set);
2582 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2583
2584 if (!cmd_buffer->device->use_global_bo_list) {
2585 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2586 if (set->descriptors[j])
2587 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2588 }
2589
2590 if(set->bo)
2591 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2592 }
2593
2594 void radv_CmdBindDescriptorSets(
2595 VkCommandBuffer commandBuffer,
2596 VkPipelineBindPoint pipelineBindPoint,
2597 VkPipelineLayout _layout,
2598 uint32_t firstSet,
2599 uint32_t descriptorSetCount,
2600 const VkDescriptorSet* pDescriptorSets,
2601 uint32_t dynamicOffsetCount,
2602 const uint32_t* pDynamicOffsets)
2603 {
2604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2605 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2606 unsigned dyn_idx = 0;
2607
2608 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2609 struct radv_descriptor_state *descriptors_state =
2610 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2611
2612 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2613 unsigned idx = i + firstSet;
2614 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2615 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2616
2617 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2618 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2619 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2620 assert(dyn_idx < dynamicOffsetCount);
2621
2622 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2623 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2624 dst[0] = va;
2625 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2626 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2627 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2628 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2629 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2630 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2631 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2632 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2633 cmd_buffer->push_constant_stages |=
2634 set->layout->dynamic_shader_stages;
2635 }
2636 }
2637 }
2638
2639 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2640 struct radv_descriptor_set *set,
2641 struct radv_descriptor_set_layout *layout,
2642 VkPipelineBindPoint bind_point)
2643 {
2644 struct radv_descriptor_state *descriptors_state =
2645 radv_get_descriptors_state(cmd_buffer, bind_point);
2646 set->size = layout->size;
2647 set->layout = layout;
2648
2649 if (descriptors_state->push_set.capacity < set->size) {
2650 size_t new_size = MAX2(set->size, 1024);
2651 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2652 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2653
2654 free(set->mapped_ptr);
2655 set->mapped_ptr = malloc(new_size);
2656
2657 if (!set->mapped_ptr) {
2658 descriptors_state->push_set.capacity = 0;
2659 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2660 return false;
2661 }
2662
2663 descriptors_state->push_set.capacity = new_size;
2664 }
2665
2666 return true;
2667 }
2668
2669 void radv_meta_push_descriptor_set(
2670 struct radv_cmd_buffer* cmd_buffer,
2671 VkPipelineBindPoint pipelineBindPoint,
2672 VkPipelineLayout _layout,
2673 uint32_t set,
2674 uint32_t descriptorWriteCount,
2675 const VkWriteDescriptorSet* pDescriptorWrites)
2676 {
2677 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2678 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2679 unsigned bo_offset;
2680
2681 assert(set == 0);
2682 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2683
2684 push_set->size = layout->set[set].layout->size;
2685 push_set->layout = layout->set[set].layout;
2686
2687 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2688 &bo_offset,
2689 (void**) &push_set->mapped_ptr))
2690 return;
2691
2692 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2693 push_set->va += bo_offset;
2694
2695 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2696 radv_descriptor_set_to_handle(push_set),
2697 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2698
2699 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2700 }
2701
2702 void radv_CmdPushDescriptorSetKHR(
2703 VkCommandBuffer commandBuffer,
2704 VkPipelineBindPoint pipelineBindPoint,
2705 VkPipelineLayout _layout,
2706 uint32_t set,
2707 uint32_t descriptorWriteCount,
2708 const VkWriteDescriptorSet* pDescriptorWrites)
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2712 struct radv_descriptor_state *descriptors_state =
2713 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2714 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2715
2716 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2717
2718 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2719 layout->set[set].layout,
2720 pipelineBindPoint))
2721 return;
2722
2723 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2724 radv_descriptor_set_to_handle(push_set),
2725 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2726
2727 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2728 descriptors_state->push_dirty = true;
2729 }
2730
2731 void radv_CmdPushDescriptorSetWithTemplateKHR(
2732 VkCommandBuffer commandBuffer,
2733 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2734 VkPipelineLayout _layout,
2735 uint32_t set,
2736 const void* pData)
2737 {
2738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2739 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2740 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2741 struct radv_descriptor_state *descriptors_state =
2742 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2743 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2744
2745 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2746
2747 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2748 layout->set[set].layout,
2749 templ->bind_point))
2750 return;
2751
2752 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2753 descriptorUpdateTemplate, pData);
2754
2755 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2756 descriptors_state->push_dirty = true;
2757 }
2758
2759 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2760 VkPipelineLayout layout,
2761 VkShaderStageFlags stageFlags,
2762 uint32_t offset,
2763 uint32_t size,
2764 const void* pValues)
2765 {
2766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2767 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2768 cmd_buffer->push_constant_stages |= stageFlags;
2769 }
2770
2771 VkResult radv_EndCommandBuffer(
2772 VkCommandBuffer commandBuffer)
2773 {
2774 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2775
2776 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2777 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2778 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2779 si_emit_cache_flush(cmd_buffer);
2780 }
2781
2782 /* Make sure CP DMA is idle at the end of IBs because the kernel
2783 * doesn't wait for it.
2784 */
2785 si_cp_dma_wait_for_idle(cmd_buffer);
2786
2787 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2788
2789 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2790 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2791
2792 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2793
2794 return cmd_buffer->record_result;
2795 }
2796
2797 static void
2798 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2799 {
2800 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2801
2802 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2803 return;
2804
2805 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2806
2807 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2808 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2809
2810 cmd_buffer->compute_scratch_size_needed =
2811 MAX2(cmd_buffer->compute_scratch_size_needed,
2812 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2813
2814 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2815 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2816
2817 if (unlikely(cmd_buffer->device->trace_bo))
2818 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2819 }
2820
2821 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2822 VkPipelineBindPoint bind_point)
2823 {
2824 struct radv_descriptor_state *descriptors_state =
2825 radv_get_descriptors_state(cmd_buffer, bind_point);
2826
2827 descriptors_state->dirty |= descriptors_state->valid;
2828 }
2829
2830 void radv_CmdBindPipeline(
2831 VkCommandBuffer commandBuffer,
2832 VkPipelineBindPoint pipelineBindPoint,
2833 VkPipeline _pipeline)
2834 {
2835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2836 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2837
2838 switch (pipelineBindPoint) {
2839 case VK_PIPELINE_BIND_POINT_COMPUTE:
2840 if (cmd_buffer->state.compute_pipeline == pipeline)
2841 return;
2842 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2843
2844 cmd_buffer->state.compute_pipeline = pipeline;
2845 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2846 break;
2847 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2848 if (cmd_buffer->state.pipeline == pipeline)
2849 return;
2850 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2851
2852 cmd_buffer->state.pipeline = pipeline;
2853 if (!pipeline)
2854 break;
2855
2856 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2857 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2858
2859 /* the new vertex shader might not have the same user regs */
2860 cmd_buffer->state.last_first_instance = -1;
2861 cmd_buffer->state.last_vertex_offset = -1;
2862
2863 /* Prefetch all pipeline shaders at first draw time. */
2864 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2865
2866 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2867 radv_bind_streamout_state(cmd_buffer, pipeline);
2868
2869 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2870 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2871 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2872 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2873
2874 if (radv_pipeline_has_tess(pipeline))
2875 cmd_buffer->tess_rings_needed = true;
2876 break;
2877 default:
2878 assert(!"invalid bind point");
2879 break;
2880 }
2881 }
2882
2883 void radv_CmdSetViewport(
2884 VkCommandBuffer commandBuffer,
2885 uint32_t firstViewport,
2886 uint32_t viewportCount,
2887 const VkViewport* pViewports)
2888 {
2889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2890 struct radv_cmd_state *state = &cmd_buffer->state;
2891 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2892
2893 assert(firstViewport < MAX_VIEWPORTS);
2894 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2895
2896 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2897 viewportCount * sizeof(*pViewports));
2898
2899 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2900 }
2901
2902 void radv_CmdSetScissor(
2903 VkCommandBuffer commandBuffer,
2904 uint32_t firstScissor,
2905 uint32_t scissorCount,
2906 const VkRect2D* pScissors)
2907 {
2908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2909 struct radv_cmd_state *state = &cmd_buffer->state;
2910 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2911
2912 assert(firstScissor < MAX_SCISSORS);
2913 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2914
2915 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2916 scissorCount * sizeof(*pScissors));
2917
2918 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2919 }
2920
2921 void radv_CmdSetLineWidth(
2922 VkCommandBuffer commandBuffer,
2923 float lineWidth)
2924 {
2925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2926 cmd_buffer->state.dynamic.line_width = lineWidth;
2927 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2928 }
2929
2930 void radv_CmdSetDepthBias(
2931 VkCommandBuffer commandBuffer,
2932 float depthBiasConstantFactor,
2933 float depthBiasClamp,
2934 float depthBiasSlopeFactor)
2935 {
2936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2937
2938 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2939 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2940 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2941
2942 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2943 }
2944
2945 void radv_CmdSetBlendConstants(
2946 VkCommandBuffer commandBuffer,
2947 const float blendConstants[4])
2948 {
2949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2950
2951 memcpy(cmd_buffer->state.dynamic.blend_constants,
2952 blendConstants, sizeof(float) * 4);
2953
2954 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2955 }
2956
2957 void radv_CmdSetDepthBounds(
2958 VkCommandBuffer commandBuffer,
2959 float minDepthBounds,
2960 float maxDepthBounds)
2961 {
2962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2963
2964 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2965 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2966
2967 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2968 }
2969
2970 void radv_CmdSetStencilCompareMask(
2971 VkCommandBuffer commandBuffer,
2972 VkStencilFaceFlags faceMask,
2973 uint32_t compareMask)
2974 {
2975 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2976
2977 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2978 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2979 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2980 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2981
2982 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2983 }
2984
2985 void radv_CmdSetStencilWriteMask(
2986 VkCommandBuffer commandBuffer,
2987 VkStencilFaceFlags faceMask,
2988 uint32_t writeMask)
2989 {
2990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2991
2992 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2993 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2994 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2995 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2996
2997 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2998 }
2999
3000 void radv_CmdSetStencilReference(
3001 VkCommandBuffer commandBuffer,
3002 VkStencilFaceFlags faceMask,
3003 uint32_t reference)
3004 {
3005 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3006
3007 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3008 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3009 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3010 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3011
3012 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3013 }
3014
3015 void radv_CmdSetDiscardRectangleEXT(
3016 VkCommandBuffer commandBuffer,
3017 uint32_t firstDiscardRectangle,
3018 uint32_t discardRectangleCount,
3019 const VkRect2D* pDiscardRectangles)
3020 {
3021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3022 struct radv_cmd_state *state = &cmd_buffer->state;
3023 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3024
3025 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3026 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3027
3028 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3029 pDiscardRectangles, discardRectangleCount);
3030
3031 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3032 }
3033
3034 void radv_CmdExecuteCommands(
3035 VkCommandBuffer commandBuffer,
3036 uint32_t commandBufferCount,
3037 const VkCommandBuffer* pCmdBuffers)
3038 {
3039 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3040
3041 assert(commandBufferCount > 0);
3042
3043 /* Emit pending flushes on primary prior to executing secondary */
3044 si_emit_cache_flush(primary);
3045
3046 for (uint32_t i = 0; i < commandBufferCount; i++) {
3047 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3048
3049 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3050 secondary->scratch_size_needed);
3051 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3052 secondary->compute_scratch_size_needed);
3053
3054 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3055 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3056 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3057 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3058 if (secondary->tess_rings_needed)
3059 primary->tess_rings_needed = true;
3060 if (secondary->sample_positions_needed)
3061 primary->sample_positions_needed = true;
3062
3063 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3064
3065
3066 /* When the secondary command buffer is compute only we don't
3067 * need to re-emit the current graphics pipeline.
3068 */
3069 if (secondary->state.emitted_pipeline) {
3070 primary->state.emitted_pipeline =
3071 secondary->state.emitted_pipeline;
3072 }
3073
3074 /* When the secondary command buffer is graphics only we don't
3075 * need to re-emit the current compute pipeline.
3076 */
3077 if (secondary->state.emitted_compute_pipeline) {
3078 primary->state.emitted_compute_pipeline =
3079 secondary->state.emitted_compute_pipeline;
3080 }
3081
3082 /* Only re-emit the draw packets when needed. */
3083 if (secondary->state.last_primitive_reset_en != -1) {
3084 primary->state.last_primitive_reset_en =
3085 secondary->state.last_primitive_reset_en;
3086 }
3087
3088 if (secondary->state.last_primitive_reset_index) {
3089 primary->state.last_primitive_reset_index =
3090 secondary->state.last_primitive_reset_index;
3091 }
3092
3093 if (secondary->state.last_ia_multi_vgt_param) {
3094 primary->state.last_ia_multi_vgt_param =
3095 secondary->state.last_ia_multi_vgt_param;
3096 }
3097
3098 primary->state.last_first_instance = secondary->state.last_first_instance;
3099 primary->state.last_num_instances = secondary->state.last_num_instances;
3100 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3101
3102 if (secondary->state.last_index_type != -1) {
3103 primary->state.last_index_type =
3104 secondary->state.last_index_type;
3105 }
3106 }
3107
3108 /* After executing commands from secondary buffers we have to dirty
3109 * some states.
3110 */
3111 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3112 RADV_CMD_DIRTY_INDEX_BUFFER |
3113 RADV_CMD_DIRTY_DYNAMIC_ALL;
3114 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3115 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3116 }
3117
3118 VkResult radv_CreateCommandPool(
3119 VkDevice _device,
3120 const VkCommandPoolCreateInfo* pCreateInfo,
3121 const VkAllocationCallbacks* pAllocator,
3122 VkCommandPool* pCmdPool)
3123 {
3124 RADV_FROM_HANDLE(radv_device, device, _device);
3125 struct radv_cmd_pool *pool;
3126
3127 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3128 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3129 if (pool == NULL)
3130 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3131
3132 if (pAllocator)
3133 pool->alloc = *pAllocator;
3134 else
3135 pool->alloc = device->alloc;
3136
3137 list_inithead(&pool->cmd_buffers);
3138 list_inithead(&pool->free_cmd_buffers);
3139
3140 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3141
3142 *pCmdPool = radv_cmd_pool_to_handle(pool);
3143
3144 return VK_SUCCESS;
3145
3146 }
3147
3148 void radv_DestroyCommandPool(
3149 VkDevice _device,
3150 VkCommandPool commandPool,
3151 const VkAllocationCallbacks* pAllocator)
3152 {
3153 RADV_FROM_HANDLE(radv_device, device, _device);
3154 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3155
3156 if (!pool)
3157 return;
3158
3159 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3160 &pool->cmd_buffers, pool_link) {
3161 radv_cmd_buffer_destroy(cmd_buffer);
3162 }
3163
3164 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3165 &pool->free_cmd_buffers, pool_link) {
3166 radv_cmd_buffer_destroy(cmd_buffer);
3167 }
3168
3169 vk_free2(&device->alloc, pAllocator, pool);
3170 }
3171
3172 VkResult radv_ResetCommandPool(
3173 VkDevice device,
3174 VkCommandPool commandPool,
3175 VkCommandPoolResetFlags flags)
3176 {
3177 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3178 VkResult result;
3179
3180 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3181 &pool->cmd_buffers, pool_link) {
3182 result = radv_reset_cmd_buffer(cmd_buffer);
3183 if (result != VK_SUCCESS)
3184 return result;
3185 }
3186
3187 return VK_SUCCESS;
3188 }
3189
3190 void radv_TrimCommandPool(
3191 VkDevice device,
3192 VkCommandPool commandPool,
3193 VkCommandPoolTrimFlagsKHR flags)
3194 {
3195 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3196
3197 if (!pool)
3198 return;
3199
3200 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3201 &pool->free_cmd_buffers, pool_link) {
3202 radv_cmd_buffer_destroy(cmd_buffer);
3203 }
3204 }
3205
3206 void radv_CmdBeginRenderPass(
3207 VkCommandBuffer commandBuffer,
3208 const VkRenderPassBeginInfo* pRenderPassBegin,
3209 VkSubpassContents contents)
3210 {
3211 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3212 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3213 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3214
3215 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3216 cmd_buffer->cs, 2048);
3217 MAYBE_UNUSED VkResult result;
3218
3219 cmd_buffer->state.framebuffer = framebuffer;
3220 cmd_buffer->state.pass = pass;
3221 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3222
3223 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3224 if (result != VK_SUCCESS)
3225 return;
3226
3227 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3228 assert(cmd_buffer->cs->cdw <= cdw_max);
3229
3230 radv_cmd_buffer_clear_subpass(cmd_buffer);
3231 }
3232
3233 void radv_CmdBeginRenderPass2KHR(
3234 VkCommandBuffer commandBuffer,
3235 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3236 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3237 {
3238 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3239 pSubpassBeginInfo->contents);
3240 }
3241
3242 void radv_CmdNextSubpass(
3243 VkCommandBuffer commandBuffer,
3244 VkSubpassContents contents)
3245 {
3246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3247
3248 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3249
3250 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3251 2048);
3252
3253 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3254 radv_cmd_buffer_clear_subpass(cmd_buffer);
3255 }
3256
3257 void radv_CmdNextSubpass2KHR(
3258 VkCommandBuffer commandBuffer,
3259 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3260 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3261 {
3262 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3263 }
3264
3265 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3266 {
3267 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3268 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3269 if (!radv_get_shader(pipeline, stage))
3270 continue;
3271
3272 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3273 if (loc->sgpr_idx == -1)
3274 continue;
3275 uint32_t base_reg = pipeline->user_data_0[stage];
3276 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3277
3278 }
3279 if (pipeline->gs_copy_shader) {
3280 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3281 if (loc->sgpr_idx != -1) {
3282 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3283 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3284 }
3285 }
3286 }
3287
3288 static void
3289 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3290 uint32_t vertex_count,
3291 bool use_opaque)
3292 {
3293 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3294 radeon_emit(cmd_buffer->cs, vertex_count);
3295 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3296 S_0287F0_USE_OPAQUE(use_opaque));
3297 }
3298
3299 static void
3300 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3301 uint64_t index_va,
3302 uint32_t index_count)
3303 {
3304 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3305 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3306 radeon_emit(cmd_buffer->cs, index_va);
3307 radeon_emit(cmd_buffer->cs, index_va >> 32);
3308 radeon_emit(cmd_buffer->cs, index_count);
3309 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3310 }
3311
3312 static void
3313 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3314 bool indexed,
3315 uint32_t draw_count,
3316 uint64_t count_va,
3317 uint32_t stride)
3318 {
3319 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3320 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3321 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3322 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3323 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3324 bool predicating = cmd_buffer->state.predicating;
3325 assert(base_reg);
3326
3327 /* just reset draw state for vertex data */
3328 cmd_buffer->state.last_first_instance = -1;
3329 cmd_buffer->state.last_num_instances = -1;
3330 cmd_buffer->state.last_vertex_offset = -1;
3331
3332 if (draw_count == 1 && !count_va && !draw_id_enable) {
3333 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3334 PKT3_DRAW_INDIRECT, 3, predicating));
3335 radeon_emit(cs, 0);
3336 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3337 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3338 radeon_emit(cs, di_src_sel);
3339 } else {
3340 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3341 PKT3_DRAW_INDIRECT_MULTI,
3342 8, predicating));
3343 radeon_emit(cs, 0);
3344 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3345 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3346 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3347 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3348 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3349 radeon_emit(cs, draw_count); /* count */
3350 radeon_emit(cs, count_va); /* count_addr */
3351 radeon_emit(cs, count_va >> 32);
3352 radeon_emit(cs, stride); /* stride */
3353 radeon_emit(cs, di_src_sel);
3354 }
3355 }
3356
3357 struct radv_draw_info {
3358 /**
3359 * Number of vertices.
3360 */
3361 uint32_t count;
3362
3363 /**
3364 * Index of the first vertex.
3365 */
3366 int32_t vertex_offset;
3367
3368 /**
3369 * First instance id.
3370 */
3371 uint32_t first_instance;
3372
3373 /**
3374 * Number of instances.
3375 */
3376 uint32_t instance_count;
3377
3378 /**
3379 * First index (indexed draws only).
3380 */
3381 uint32_t first_index;
3382
3383 /**
3384 * Whether it's an indexed draw.
3385 */
3386 bool indexed;
3387
3388 /**
3389 * Indirect draw parameters resource.
3390 */
3391 struct radv_buffer *indirect;
3392 uint64_t indirect_offset;
3393 uint32_t stride;
3394
3395 /**
3396 * Draw count parameters resource.
3397 */
3398 struct radv_buffer *count_buffer;
3399 uint64_t count_buffer_offset;
3400
3401 /**
3402 * Stream output parameters resource.
3403 */
3404 struct radv_buffer *strmout_buffer;
3405 uint64_t strmout_buffer_offset;
3406 };
3407
3408 static void
3409 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3410 const struct radv_draw_info *info)
3411 {
3412 struct radv_cmd_state *state = &cmd_buffer->state;
3413 struct radeon_winsys *ws = cmd_buffer->device->ws;
3414 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3415
3416 if (info->strmout_buffer) {
3417 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3418
3419 va += info->strmout_buffer->offset +
3420 info->strmout_buffer_offset;
3421
3422 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3423 info->stride);
3424
3425 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3426 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3427 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3428 COPY_DATA_WR_CONFIRM);
3429 radeon_emit(cs, va);
3430 radeon_emit(cs, va >> 32);
3431 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3432 radeon_emit(cs, 0); /* unused */
3433
3434 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3435 }
3436
3437 if (info->indirect) {
3438 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3439 uint64_t count_va = 0;
3440
3441 va += info->indirect->offset + info->indirect_offset;
3442
3443 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3444
3445 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3446 radeon_emit(cs, 1);
3447 radeon_emit(cs, va);
3448 radeon_emit(cs, va >> 32);
3449
3450 if (info->count_buffer) {
3451 count_va = radv_buffer_get_va(info->count_buffer->bo);
3452 count_va += info->count_buffer->offset +
3453 info->count_buffer_offset;
3454
3455 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3456 }
3457
3458 if (!state->subpass->view_mask) {
3459 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3460 info->indexed,
3461 info->count,
3462 count_va,
3463 info->stride);
3464 } else {
3465 unsigned i;
3466 for_each_bit(i, state->subpass->view_mask) {
3467 radv_emit_view_index(cmd_buffer, i);
3468
3469 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3470 info->indexed,
3471 info->count,
3472 count_va,
3473 info->stride);
3474 }
3475 }
3476 } else {
3477 assert(state->pipeline->graphics.vtx_base_sgpr);
3478
3479 if (info->vertex_offset != state->last_vertex_offset ||
3480 info->first_instance != state->last_first_instance) {
3481 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3482 state->pipeline->graphics.vtx_emit_num);
3483
3484 radeon_emit(cs, info->vertex_offset);
3485 radeon_emit(cs, info->first_instance);
3486 if (state->pipeline->graphics.vtx_emit_num == 3)
3487 radeon_emit(cs, 0);
3488 state->last_first_instance = info->first_instance;
3489 state->last_vertex_offset = info->vertex_offset;
3490 }
3491
3492 if (state->last_num_instances != info->instance_count) {
3493 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3494 radeon_emit(cs, info->instance_count);
3495 state->last_num_instances = info->instance_count;
3496 }
3497
3498 if (info->indexed) {
3499 int index_size = state->index_type ? 4 : 2;
3500 uint64_t index_va;
3501
3502 index_va = state->index_va;
3503 index_va += info->first_index * index_size;
3504
3505 if (!state->subpass->view_mask) {
3506 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3507 index_va,
3508 info->count);
3509 } else {
3510 unsigned i;
3511 for_each_bit(i, state->subpass->view_mask) {
3512 radv_emit_view_index(cmd_buffer, i);
3513
3514 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3515 index_va,
3516 info->count);
3517 }
3518 }
3519 } else {
3520 if (!state->subpass->view_mask) {
3521 radv_cs_emit_draw_packet(cmd_buffer,
3522 info->count,
3523 !!info->strmout_buffer);
3524 } else {
3525 unsigned i;
3526 for_each_bit(i, state->subpass->view_mask) {
3527 radv_emit_view_index(cmd_buffer, i);
3528
3529 radv_cs_emit_draw_packet(cmd_buffer,
3530 info->count,
3531 !!info->strmout_buffer);
3532 }
3533 }
3534 }
3535 }
3536 }
3537
3538 /*
3539 * Vega and raven have a bug which triggers if there are multiple context
3540 * register contexts active at the same time with different scissor values.
3541 *
3542 * There are two possible workarounds:
3543 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3544 * there is only ever 1 active set of scissor values at the same time.
3545 *
3546 * 2) Whenever the hardware switches contexts we have to set the scissor
3547 * registers again even if it is a noop. That way the new context gets
3548 * the correct scissor values.
3549 *
3550 * This implements option 2. radv_need_late_scissor_emission needs to
3551 * return true on affected HW if radv_emit_all_graphics_states sets
3552 * any context registers.
3553 */
3554 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3555 bool indexed_draw)
3556 {
3557 struct radv_cmd_state *state = &cmd_buffer->state;
3558
3559 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3560 return false;
3561
3562 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3563
3564 /* Index, vertex and streamout buffers don't change context regs, and
3565 * pipeline is handled later.
3566 */
3567 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3568 RADV_CMD_DIRTY_VERTEX_BUFFER |
3569 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3570 RADV_CMD_DIRTY_PIPELINE);
3571
3572 /* Assume all state changes except these two can imply context rolls. */
3573 if (cmd_buffer->state.dirty & used_states)
3574 return true;
3575
3576 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3577 return true;
3578
3579 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3580 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3581 return true;
3582
3583 return false;
3584 }
3585
3586 static void
3587 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3588 const struct radv_draw_info *info)
3589 {
3590 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3591
3592 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3593 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3594 radv_emit_rbplus_state(cmd_buffer);
3595
3596 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3597 radv_emit_graphics_pipeline(cmd_buffer);
3598
3599 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3600 radv_emit_framebuffer_state(cmd_buffer);
3601
3602 if (info->indexed) {
3603 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3604 radv_emit_index_buffer(cmd_buffer);
3605 } else {
3606 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3607 * so the state must be re-emitted before the next indexed
3608 * draw.
3609 */
3610 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3611 cmd_buffer->state.last_index_type = -1;
3612 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3613 }
3614 }
3615
3616 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3617
3618 radv_emit_draw_registers(cmd_buffer, info->indexed,
3619 info->instance_count > 1, info->indirect,
3620 info->indirect ? 0 : info->count);
3621
3622 if (late_scissor_emission)
3623 radv_emit_scissor(cmd_buffer);
3624 }
3625
3626 static void
3627 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3628 const struct radv_draw_info *info)
3629 {
3630 struct radeon_info *rad_info =
3631 &cmd_buffer->device->physical_device->rad_info;
3632 bool has_prefetch =
3633 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3634 bool pipeline_is_dirty =
3635 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3636 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3637
3638 MAYBE_UNUSED unsigned cdw_max =
3639 radeon_check_space(cmd_buffer->device->ws,
3640 cmd_buffer->cs, 4096);
3641
3642 /* Use optimal packet order based on whether we need to sync the
3643 * pipeline.
3644 */
3645 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3646 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3647 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3648 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3649 /* If we have to wait for idle, set all states first, so that
3650 * all SET packets are processed in parallel with previous draw
3651 * calls. Then upload descriptors, set shader pointers, and
3652 * draw, and prefetch at the end. This ensures that the time
3653 * the CUs are idle is very short. (there are only SET_SH
3654 * packets between the wait and the draw)
3655 */
3656 radv_emit_all_graphics_states(cmd_buffer, info);
3657 si_emit_cache_flush(cmd_buffer);
3658 /* <-- CUs are idle here --> */
3659
3660 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3661
3662 radv_emit_draw_packets(cmd_buffer, info);
3663 /* <-- CUs are busy here --> */
3664
3665 /* Start prefetches after the draw has been started. Both will
3666 * run in parallel, but starting the draw first is more
3667 * important.
3668 */
3669 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3670 radv_emit_prefetch_L2(cmd_buffer,
3671 cmd_buffer->state.pipeline, false);
3672 }
3673 } else {
3674 /* If we don't wait for idle, start prefetches first, then set
3675 * states, and draw at the end.
3676 */
3677 si_emit_cache_flush(cmd_buffer);
3678
3679 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3680 /* Only prefetch the vertex shader and VBO descriptors
3681 * in order to start the draw as soon as possible.
3682 */
3683 radv_emit_prefetch_L2(cmd_buffer,
3684 cmd_buffer->state.pipeline, true);
3685 }
3686
3687 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3688
3689 radv_emit_all_graphics_states(cmd_buffer, info);
3690 radv_emit_draw_packets(cmd_buffer, info);
3691
3692 /* Prefetch the remaining shaders after the draw has been
3693 * started.
3694 */
3695 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3696 radv_emit_prefetch_L2(cmd_buffer,
3697 cmd_buffer->state.pipeline, false);
3698 }
3699 }
3700
3701 /* Workaround for a VGT hang when streamout is enabled.
3702 * It must be done after drawing.
3703 */
3704 if (cmd_buffer->state.streamout.streamout_enabled &&
3705 (rad_info->family == CHIP_HAWAII ||
3706 rad_info->family == CHIP_TONGA ||
3707 rad_info->family == CHIP_FIJI)) {
3708 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3709 }
3710
3711 assert(cmd_buffer->cs->cdw <= cdw_max);
3712 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3713 }
3714
3715 void radv_CmdDraw(
3716 VkCommandBuffer commandBuffer,
3717 uint32_t vertexCount,
3718 uint32_t instanceCount,
3719 uint32_t firstVertex,
3720 uint32_t firstInstance)
3721 {
3722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3723 struct radv_draw_info info = {};
3724
3725 info.count = vertexCount;
3726 info.instance_count = instanceCount;
3727 info.first_instance = firstInstance;
3728 info.vertex_offset = firstVertex;
3729
3730 radv_draw(cmd_buffer, &info);
3731 }
3732
3733 void radv_CmdDrawIndexed(
3734 VkCommandBuffer commandBuffer,
3735 uint32_t indexCount,
3736 uint32_t instanceCount,
3737 uint32_t firstIndex,
3738 int32_t vertexOffset,
3739 uint32_t firstInstance)
3740 {
3741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3742 struct radv_draw_info info = {};
3743
3744 info.indexed = true;
3745 info.count = indexCount;
3746 info.instance_count = instanceCount;
3747 info.first_index = firstIndex;
3748 info.vertex_offset = vertexOffset;
3749 info.first_instance = firstInstance;
3750
3751 radv_draw(cmd_buffer, &info);
3752 }
3753
3754 void radv_CmdDrawIndirect(
3755 VkCommandBuffer commandBuffer,
3756 VkBuffer _buffer,
3757 VkDeviceSize offset,
3758 uint32_t drawCount,
3759 uint32_t stride)
3760 {
3761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3762 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3763 struct radv_draw_info info = {};
3764
3765 info.count = drawCount;
3766 info.indirect = buffer;
3767 info.indirect_offset = offset;
3768 info.stride = stride;
3769
3770 radv_draw(cmd_buffer, &info);
3771 }
3772
3773 void radv_CmdDrawIndexedIndirect(
3774 VkCommandBuffer commandBuffer,
3775 VkBuffer _buffer,
3776 VkDeviceSize offset,
3777 uint32_t drawCount,
3778 uint32_t stride)
3779 {
3780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3781 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3782 struct radv_draw_info info = {};
3783
3784 info.indexed = true;
3785 info.count = drawCount;
3786 info.indirect = buffer;
3787 info.indirect_offset = offset;
3788 info.stride = stride;
3789
3790 radv_draw(cmd_buffer, &info);
3791 }
3792
3793 void radv_CmdDrawIndirectCountAMD(
3794 VkCommandBuffer commandBuffer,
3795 VkBuffer _buffer,
3796 VkDeviceSize offset,
3797 VkBuffer _countBuffer,
3798 VkDeviceSize countBufferOffset,
3799 uint32_t maxDrawCount,
3800 uint32_t stride)
3801 {
3802 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3803 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3804 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3805 struct radv_draw_info info = {};
3806
3807 info.count = maxDrawCount;
3808 info.indirect = buffer;
3809 info.indirect_offset = offset;
3810 info.count_buffer = count_buffer;
3811 info.count_buffer_offset = countBufferOffset;
3812 info.stride = stride;
3813
3814 radv_draw(cmd_buffer, &info);
3815 }
3816
3817 void radv_CmdDrawIndexedIndirectCountAMD(
3818 VkCommandBuffer commandBuffer,
3819 VkBuffer _buffer,
3820 VkDeviceSize offset,
3821 VkBuffer _countBuffer,
3822 VkDeviceSize countBufferOffset,
3823 uint32_t maxDrawCount,
3824 uint32_t stride)
3825 {
3826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3827 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3828 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3829 struct radv_draw_info info = {};
3830
3831 info.indexed = true;
3832 info.count = maxDrawCount;
3833 info.indirect = buffer;
3834 info.indirect_offset = offset;
3835 info.count_buffer = count_buffer;
3836 info.count_buffer_offset = countBufferOffset;
3837 info.stride = stride;
3838
3839 radv_draw(cmd_buffer, &info);
3840 }
3841
3842 void radv_CmdDrawIndirectCountKHR(
3843 VkCommandBuffer commandBuffer,
3844 VkBuffer _buffer,
3845 VkDeviceSize offset,
3846 VkBuffer _countBuffer,
3847 VkDeviceSize countBufferOffset,
3848 uint32_t maxDrawCount,
3849 uint32_t stride)
3850 {
3851 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3852 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3853 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3854 struct radv_draw_info info = {};
3855
3856 info.count = maxDrawCount;
3857 info.indirect = buffer;
3858 info.indirect_offset = offset;
3859 info.count_buffer = count_buffer;
3860 info.count_buffer_offset = countBufferOffset;
3861 info.stride = stride;
3862
3863 radv_draw(cmd_buffer, &info);
3864 }
3865
3866 void radv_CmdDrawIndexedIndirectCountKHR(
3867 VkCommandBuffer commandBuffer,
3868 VkBuffer _buffer,
3869 VkDeviceSize offset,
3870 VkBuffer _countBuffer,
3871 VkDeviceSize countBufferOffset,
3872 uint32_t maxDrawCount,
3873 uint32_t stride)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3877 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3878 struct radv_draw_info info = {};
3879
3880 info.indexed = true;
3881 info.count = maxDrawCount;
3882 info.indirect = buffer;
3883 info.indirect_offset = offset;
3884 info.count_buffer = count_buffer;
3885 info.count_buffer_offset = countBufferOffset;
3886 info.stride = stride;
3887
3888 radv_draw(cmd_buffer, &info);
3889 }
3890
3891 struct radv_dispatch_info {
3892 /**
3893 * Determine the layout of the grid (in block units) to be used.
3894 */
3895 uint32_t blocks[3];
3896
3897 /**
3898 * A starting offset for the grid. If unaligned is set, the offset
3899 * must still be aligned.
3900 */
3901 uint32_t offsets[3];
3902 /**
3903 * Whether it's an unaligned compute dispatch.
3904 */
3905 bool unaligned;
3906
3907 /**
3908 * Indirect compute parameters resource.
3909 */
3910 struct radv_buffer *indirect;
3911 uint64_t indirect_offset;
3912 };
3913
3914 static void
3915 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3916 const struct radv_dispatch_info *info)
3917 {
3918 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3919 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3920 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3921 struct radeon_winsys *ws = cmd_buffer->device->ws;
3922 bool predicating = cmd_buffer->state.predicating;
3923 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3924 struct radv_userdata_info *loc;
3925
3926 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3927 AC_UD_CS_GRID_SIZE);
3928
3929 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3930
3931 if (info->indirect) {
3932 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3933
3934 va += info->indirect->offset + info->indirect_offset;
3935
3936 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3937
3938 if (loc->sgpr_idx != -1) {
3939 for (unsigned i = 0; i < 3; ++i) {
3940 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3941 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3942 COPY_DATA_DST_SEL(COPY_DATA_REG));
3943 radeon_emit(cs, (va + 4 * i));
3944 radeon_emit(cs, (va + 4 * i) >> 32);
3945 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3946 + loc->sgpr_idx * 4) >> 2) + i);
3947 radeon_emit(cs, 0);
3948 }
3949 }
3950
3951 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3952 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3953 PKT3_SHADER_TYPE_S(1));
3954 radeon_emit(cs, va);
3955 radeon_emit(cs, va >> 32);
3956 radeon_emit(cs, dispatch_initiator);
3957 } else {
3958 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3959 PKT3_SHADER_TYPE_S(1));
3960 radeon_emit(cs, 1);
3961 radeon_emit(cs, va);
3962 radeon_emit(cs, va >> 32);
3963
3964 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3965 PKT3_SHADER_TYPE_S(1));
3966 radeon_emit(cs, 0);
3967 radeon_emit(cs, dispatch_initiator);
3968 }
3969 } else {
3970 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3971 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3972
3973 if (info->unaligned) {
3974 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3975 unsigned remainder[3];
3976
3977 /* If aligned, these should be an entire block size,
3978 * not 0.
3979 */
3980 remainder[0] = blocks[0] + cs_block_size[0] -
3981 align_u32_npot(blocks[0], cs_block_size[0]);
3982 remainder[1] = blocks[1] + cs_block_size[1] -
3983 align_u32_npot(blocks[1], cs_block_size[1]);
3984 remainder[2] = blocks[2] + cs_block_size[2] -
3985 align_u32_npot(blocks[2], cs_block_size[2]);
3986
3987 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3988 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3989 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3990
3991 for(unsigned i = 0; i < 3; ++i) {
3992 assert(offsets[i] % cs_block_size[i] == 0);
3993 offsets[i] /= cs_block_size[i];
3994 }
3995
3996 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3997 radeon_emit(cs,
3998 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3999 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4000 radeon_emit(cs,
4001 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4002 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4003 radeon_emit(cs,
4004 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4005 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4006
4007 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4008 }
4009
4010 if (loc->sgpr_idx != -1) {
4011 assert(!loc->indirect);
4012 assert(loc->num_sgprs == 3);
4013
4014 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4015 loc->sgpr_idx * 4, 3);
4016 radeon_emit(cs, blocks[0]);
4017 radeon_emit(cs, blocks[1]);
4018 radeon_emit(cs, blocks[2]);
4019 }
4020
4021 if (offsets[0] || offsets[1] || offsets[2]) {
4022 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4023 radeon_emit(cs, offsets[0]);
4024 radeon_emit(cs, offsets[1]);
4025 radeon_emit(cs, offsets[2]);
4026
4027 /* The blocks in the packet are not counts but end values. */
4028 for (unsigned i = 0; i < 3; ++i)
4029 blocks[i] += offsets[i];
4030 } else {
4031 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4032 }
4033
4034 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4035 PKT3_SHADER_TYPE_S(1));
4036 radeon_emit(cs, blocks[0]);
4037 radeon_emit(cs, blocks[1]);
4038 radeon_emit(cs, blocks[2]);
4039 radeon_emit(cs, dispatch_initiator);
4040 }
4041
4042 assert(cmd_buffer->cs->cdw <= cdw_max);
4043 }
4044
4045 static void
4046 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4047 {
4048 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4049 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4050 }
4051
4052 static void
4053 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4054 const struct radv_dispatch_info *info)
4055 {
4056 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4057 bool has_prefetch =
4058 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4059 bool pipeline_is_dirty = pipeline &&
4060 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4061
4062 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4063 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4064 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4065 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4066 /* If we have to wait for idle, set all states first, so that
4067 * all SET packets are processed in parallel with previous draw
4068 * calls. Then upload descriptors, set shader pointers, and
4069 * dispatch, and prefetch at the end. This ensures that the
4070 * time the CUs are idle is very short. (there are only SET_SH
4071 * packets between the wait and the draw)
4072 */
4073 radv_emit_compute_pipeline(cmd_buffer);
4074 si_emit_cache_flush(cmd_buffer);
4075 /* <-- CUs are idle here --> */
4076
4077 radv_upload_compute_shader_descriptors(cmd_buffer);
4078
4079 radv_emit_dispatch_packets(cmd_buffer, info);
4080 /* <-- CUs are busy here --> */
4081
4082 /* Start prefetches after the dispatch has been started. Both
4083 * will run in parallel, but starting the dispatch first is
4084 * more important.
4085 */
4086 if (has_prefetch && pipeline_is_dirty) {
4087 radv_emit_shader_prefetch(cmd_buffer,
4088 pipeline->shaders[MESA_SHADER_COMPUTE]);
4089 }
4090 } else {
4091 /* If we don't wait for idle, start prefetches first, then set
4092 * states, and dispatch at the end.
4093 */
4094 si_emit_cache_flush(cmd_buffer);
4095
4096 if (has_prefetch && pipeline_is_dirty) {
4097 radv_emit_shader_prefetch(cmd_buffer,
4098 pipeline->shaders[MESA_SHADER_COMPUTE]);
4099 }
4100
4101 radv_upload_compute_shader_descriptors(cmd_buffer);
4102
4103 radv_emit_compute_pipeline(cmd_buffer);
4104 radv_emit_dispatch_packets(cmd_buffer, info);
4105 }
4106
4107 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4108 }
4109
4110 void radv_CmdDispatchBase(
4111 VkCommandBuffer commandBuffer,
4112 uint32_t base_x,
4113 uint32_t base_y,
4114 uint32_t base_z,
4115 uint32_t x,
4116 uint32_t y,
4117 uint32_t z)
4118 {
4119 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4120 struct radv_dispatch_info info = {};
4121
4122 info.blocks[0] = x;
4123 info.blocks[1] = y;
4124 info.blocks[2] = z;
4125
4126 info.offsets[0] = base_x;
4127 info.offsets[1] = base_y;
4128 info.offsets[2] = base_z;
4129 radv_dispatch(cmd_buffer, &info);
4130 }
4131
4132 void radv_CmdDispatch(
4133 VkCommandBuffer commandBuffer,
4134 uint32_t x,
4135 uint32_t y,
4136 uint32_t z)
4137 {
4138 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4139 }
4140
4141 void radv_CmdDispatchIndirect(
4142 VkCommandBuffer commandBuffer,
4143 VkBuffer _buffer,
4144 VkDeviceSize offset)
4145 {
4146 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4147 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4148 struct radv_dispatch_info info = {};
4149
4150 info.indirect = buffer;
4151 info.indirect_offset = offset;
4152
4153 radv_dispatch(cmd_buffer, &info);
4154 }
4155
4156 void radv_unaligned_dispatch(
4157 struct radv_cmd_buffer *cmd_buffer,
4158 uint32_t x,
4159 uint32_t y,
4160 uint32_t z)
4161 {
4162 struct radv_dispatch_info info = {};
4163
4164 info.blocks[0] = x;
4165 info.blocks[1] = y;
4166 info.blocks[2] = z;
4167 info.unaligned = 1;
4168
4169 radv_dispatch(cmd_buffer, &info);
4170 }
4171
4172 void radv_CmdEndRenderPass(
4173 VkCommandBuffer commandBuffer)
4174 {
4175 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4176
4177 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4178
4179 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4180
4181 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4182 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4183 radv_handle_subpass_image_transition(cmd_buffer,
4184 (struct radv_subpass_attachment){i, layout});
4185 }
4186
4187 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4188
4189 cmd_buffer->state.pass = NULL;
4190 cmd_buffer->state.subpass = NULL;
4191 cmd_buffer->state.attachments = NULL;
4192 cmd_buffer->state.framebuffer = NULL;
4193 }
4194
4195 void radv_CmdEndRenderPass2KHR(
4196 VkCommandBuffer commandBuffer,
4197 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4198 {
4199 radv_CmdEndRenderPass(commandBuffer);
4200 }
4201
4202 /*
4203 * For HTILE we have the following interesting clear words:
4204 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4205 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4206 * 0xfffffff0: Clear depth to 1.0
4207 * 0x00000000: Clear depth to 0.0
4208 */
4209 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4210 struct radv_image *image,
4211 const VkImageSubresourceRange *range,
4212 uint32_t clear_word)
4213 {
4214 assert(range->baseMipLevel == 0);
4215 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4216 unsigned layer_count = radv_get_layerCount(image, range);
4217 uint64_t size = image->surface.htile_slice_size * layer_count;
4218 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4219 uint64_t offset = image->offset + image->htile_offset +
4220 image->surface.htile_slice_size * range->baseArrayLayer;
4221 struct radv_cmd_state *state = &cmd_buffer->state;
4222 VkClearDepthStencilValue value = {};
4223
4224 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4225 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4226
4227 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4228 size, clear_word);
4229
4230 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4231
4232 if (vk_format_is_stencil(image->vk_format))
4233 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4234
4235 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4236 }
4237
4238 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4239 struct radv_image *image,
4240 VkImageLayout src_layout,
4241 VkImageLayout dst_layout,
4242 unsigned src_queue_mask,
4243 unsigned dst_queue_mask,
4244 const VkImageSubresourceRange *range,
4245 VkImageAspectFlags pending_clears)
4246 {
4247 if (!radv_image_has_htile(image))
4248 return;
4249
4250 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4251 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4252 /* TODO: merge with the clear if applicable */
4253 radv_initialize_htile(cmd_buffer, image, range, 0);
4254 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4255 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4256 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4257 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4258 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4259 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4260 VkImageSubresourceRange local_range = *range;
4261 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4262 local_range.baseMipLevel = 0;
4263 local_range.levelCount = 1;
4264
4265 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4266 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4267
4268 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4269
4270 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4271 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4272 }
4273 }
4274
4275 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4276 struct radv_image *image, uint32_t value)
4277 {
4278 struct radv_cmd_state *state = &cmd_buffer->state;
4279
4280 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4281 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4282
4283 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4284
4285 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4286 }
4287
4288 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4289 struct radv_image *image, uint32_t value)
4290 {
4291 struct radv_cmd_state *state = &cmd_buffer->state;
4292
4293 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4294 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4295
4296 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4297
4298 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4299 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4300 }
4301
4302 /**
4303 * Initialize DCC/FMASK/CMASK metadata for a color image.
4304 */
4305 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4306 struct radv_image *image,
4307 VkImageLayout src_layout,
4308 VkImageLayout dst_layout,
4309 unsigned src_queue_mask,
4310 unsigned dst_queue_mask)
4311 {
4312 if (radv_image_has_cmask(image)) {
4313 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4314
4315 /* TODO: clarify this. */
4316 if (radv_image_has_fmask(image)) {
4317 value = 0xccccccccu;
4318 }
4319
4320 radv_initialise_cmask(cmd_buffer, image, value);
4321 }
4322
4323 if (radv_image_has_dcc(image)) {
4324 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4325 bool need_decompress_pass = false;
4326
4327 if (radv_layout_dcc_compressed(image, dst_layout,
4328 dst_queue_mask)) {
4329 value = 0x20202020u;
4330 need_decompress_pass = true;
4331 }
4332
4333 radv_initialize_dcc(cmd_buffer, image, value);
4334
4335 radv_update_fce_metadata(cmd_buffer, image,
4336 need_decompress_pass);
4337 }
4338
4339 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4340 uint32_t color_values[2] = {};
4341 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4342 }
4343 }
4344
4345 /**
4346 * Handle color image transitions for DCC/FMASK/CMASK.
4347 */
4348 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4349 struct radv_image *image,
4350 VkImageLayout src_layout,
4351 VkImageLayout dst_layout,
4352 unsigned src_queue_mask,
4353 unsigned dst_queue_mask,
4354 const VkImageSubresourceRange *range)
4355 {
4356 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4357 radv_init_color_image_metadata(cmd_buffer, image,
4358 src_layout, dst_layout,
4359 src_queue_mask, dst_queue_mask);
4360 return;
4361 }
4362
4363 if (radv_image_has_dcc(image)) {
4364 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4365 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4366 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4367 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4368 radv_decompress_dcc(cmd_buffer, image, range);
4369 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4370 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4371 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4372 }
4373 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4374 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4375 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4376 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4377 }
4378 }
4379 }
4380
4381 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4382 struct radv_image *image,
4383 VkImageLayout src_layout,
4384 VkImageLayout dst_layout,
4385 uint32_t src_family,
4386 uint32_t dst_family,
4387 const VkImageSubresourceRange *range,
4388 VkImageAspectFlags pending_clears)
4389 {
4390 if (image->exclusive && src_family != dst_family) {
4391 /* This is an acquire or a release operation and there will be
4392 * a corresponding release/acquire. Do the transition in the
4393 * most flexible queue. */
4394
4395 assert(src_family == cmd_buffer->queue_family_index ||
4396 dst_family == cmd_buffer->queue_family_index);
4397
4398 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4399 return;
4400
4401 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4402 (src_family == RADV_QUEUE_GENERAL ||
4403 dst_family == RADV_QUEUE_GENERAL))
4404 return;
4405 }
4406
4407 unsigned src_queue_mask =
4408 radv_image_queue_family_mask(image, src_family,
4409 cmd_buffer->queue_family_index);
4410 unsigned dst_queue_mask =
4411 radv_image_queue_family_mask(image, dst_family,
4412 cmd_buffer->queue_family_index);
4413
4414 if (vk_format_is_depth(image->vk_format)) {
4415 radv_handle_depth_image_transition(cmd_buffer, image,
4416 src_layout, dst_layout,
4417 src_queue_mask, dst_queue_mask,
4418 range, pending_clears);
4419 } else {
4420 radv_handle_color_image_transition(cmd_buffer, image,
4421 src_layout, dst_layout,
4422 src_queue_mask, dst_queue_mask,
4423 range);
4424 }
4425 }
4426
4427 struct radv_barrier_info {
4428 uint32_t eventCount;
4429 const VkEvent *pEvents;
4430 VkPipelineStageFlags srcStageMask;
4431 };
4432
4433 static void
4434 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4435 uint32_t memoryBarrierCount,
4436 const VkMemoryBarrier *pMemoryBarriers,
4437 uint32_t bufferMemoryBarrierCount,
4438 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4439 uint32_t imageMemoryBarrierCount,
4440 const VkImageMemoryBarrier *pImageMemoryBarriers,
4441 const struct radv_barrier_info *info)
4442 {
4443 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4444 enum radv_cmd_flush_bits src_flush_bits = 0;
4445 enum radv_cmd_flush_bits dst_flush_bits = 0;
4446
4447 for (unsigned i = 0; i < info->eventCount; ++i) {
4448 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4449 uint64_t va = radv_buffer_get_va(event->bo);
4450
4451 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4452
4453 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4454
4455 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4456 assert(cmd_buffer->cs->cdw <= cdw_max);
4457 }
4458
4459 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4460 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4461 NULL);
4462 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4463 NULL);
4464 }
4465
4466 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4467 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4468 NULL);
4469 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4470 NULL);
4471 }
4472
4473 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4474 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4475
4476 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4477 image);
4478 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4479 image);
4480 }
4481
4482 radv_stage_flush(cmd_buffer, info->srcStageMask);
4483 cmd_buffer->state.flush_bits |= src_flush_bits;
4484
4485 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4486 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4487 radv_handle_image_transition(cmd_buffer, image,
4488 pImageMemoryBarriers[i].oldLayout,
4489 pImageMemoryBarriers[i].newLayout,
4490 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4491 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4492 &pImageMemoryBarriers[i].subresourceRange,
4493 0);
4494 }
4495
4496 /* Make sure CP DMA is idle because the driver might have performed a
4497 * DMA operation for copying or filling buffers/images.
4498 */
4499 si_cp_dma_wait_for_idle(cmd_buffer);
4500
4501 cmd_buffer->state.flush_bits |= dst_flush_bits;
4502 }
4503
4504 void radv_CmdPipelineBarrier(
4505 VkCommandBuffer commandBuffer,
4506 VkPipelineStageFlags srcStageMask,
4507 VkPipelineStageFlags destStageMask,
4508 VkBool32 byRegion,
4509 uint32_t memoryBarrierCount,
4510 const VkMemoryBarrier* pMemoryBarriers,
4511 uint32_t bufferMemoryBarrierCount,
4512 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4513 uint32_t imageMemoryBarrierCount,
4514 const VkImageMemoryBarrier* pImageMemoryBarriers)
4515 {
4516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4517 struct radv_barrier_info info;
4518
4519 info.eventCount = 0;
4520 info.pEvents = NULL;
4521 info.srcStageMask = srcStageMask;
4522
4523 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4524 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4525 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4526 }
4527
4528
4529 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4530 struct radv_event *event,
4531 VkPipelineStageFlags stageMask,
4532 unsigned value)
4533 {
4534 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4535 uint64_t va = radv_buffer_get_va(event->bo);
4536
4537 si_emit_cache_flush(cmd_buffer);
4538
4539 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4540
4541 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4542
4543 /* Flags that only require a top-of-pipe event. */
4544 VkPipelineStageFlags top_of_pipe_flags =
4545 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4546
4547 /* Flags that only require a post-index-fetch event. */
4548 VkPipelineStageFlags post_index_fetch_flags =
4549 top_of_pipe_flags |
4550 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4551 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4552
4553 /* Make sure CP DMA is idle because the driver might have performed a
4554 * DMA operation for copying or filling buffers/images.
4555 */
4556 si_cp_dma_wait_for_idle(cmd_buffer);
4557
4558 /* TODO: Emit EOS events for syncing PS/CS stages. */
4559
4560 if (!(stageMask & ~top_of_pipe_flags)) {
4561 /* Just need to sync the PFP engine. */
4562 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4563 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4564 S_370_WR_CONFIRM(1) |
4565 S_370_ENGINE_SEL(V_370_PFP));
4566 radeon_emit(cs, va);
4567 radeon_emit(cs, va >> 32);
4568 radeon_emit(cs, value);
4569 } else if (!(stageMask & ~post_index_fetch_flags)) {
4570 /* Sync ME because PFP reads index and indirect buffers. */
4571 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4572 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4573 S_370_WR_CONFIRM(1) |
4574 S_370_ENGINE_SEL(V_370_ME));
4575 radeon_emit(cs, va);
4576 radeon_emit(cs, va >> 32);
4577 radeon_emit(cs, value);
4578 } else {
4579 /* Otherwise, sync all prior GPU work using an EOP event. */
4580 si_cs_emit_write_event_eop(cs,
4581 cmd_buffer->device->physical_device->rad_info.chip_class,
4582 radv_cmd_buffer_uses_mec(cmd_buffer),
4583 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4584 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4585 cmd_buffer->gfx9_eop_bug_va);
4586 }
4587
4588 assert(cmd_buffer->cs->cdw <= cdw_max);
4589 }
4590
4591 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4592 VkEvent _event,
4593 VkPipelineStageFlags stageMask)
4594 {
4595 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4596 RADV_FROM_HANDLE(radv_event, event, _event);
4597
4598 write_event(cmd_buffer, event, stageMask, 1);
4599 }
4600
4601 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4602 VkEvent _event,
4603 VkPipelineStageFlags stageMask)
4604 {
4605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4606 RADV_FROM_HANDLE(radv_event, event, _event);
4607
4608 write_event(cmd_buffer, event, stageMask, 0);
4609 }
4610
4611 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4612 uint32_t eventCount,
4613 const VkEvent* pEvents,
4614 VkPipelineStageFlags srcStageMask,
4615 VkPipelineStageFlags dstStageMask,
4616 uint32_t memoryBarrierCount,
4617 const VkMemoryBarrier* pMemoryBarriers,
4618 uint32_t bufferMemoryBarrierCount,
4619 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4620 uint32_t imageMemoryBarrierCount,
4621 const VkImageMemoryBarrier* pImageMemoryBarriers)
4622 {
4623 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4624 struct radv_barrier_info info;
4625
4626 info.eventCount = eventCount;
4627 info.pEvents = pEvents;
4628 info.srcStageMask = 0;
4629
4630 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4631 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4632 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4633 }
4634
4635
4636 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4637 uint32_t deviceMask)
4638 {
4639 /* No-op */
4640 }
4641
4642 /* VK_EXT_conditional_rendering */
4643 void radv_CmdBeginConditionalRenderingEXT(
4644 VkCommandBuffer commandBuffer,
4645 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4646 {
4647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4648 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4649 bool draw_visible = true;
4650 uint64_t va;
4651
4652 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4653
4654 /* By default, if the 32-bit value at offset in buffer memory is zero,
4655 * then the rendering commands are discarded, otherwise they are
4656 * executed as normal. If the inverted flag is set, all commands are
4657 * discarded if the value is non zero.
4658 */
4659 if (pConditionalRenderingBegin->flags &
4660 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4661 draw_visible = false;
4662 }
4663
4664 /* Enable predication for this command buffer. */
4665 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4666 cmd_buffer->state.predicating = true;
4667
4668 /* Store conditional rendering user info. */
4669 cmd_buffer->state.predication_type = draw_visible;
4670 cmd_buffer->state.predication_va = va;
4671 }
4672
4673 void radv_CmdEndConditionalRenderingEXT(
4674 VkCommandBuffer commandBuffer)
4675 {
4676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4677
4678 /* Disable predication for this command buffer. */
4679 si_emit_set_predication_state(cmd_buffer, false, 0);
4680 cmd_buffer->state.predicating = false;
4681
4682 /* Reset conditional rendering user info. */
4683 cmd_buffer->state.predication_type = -1;
4684 cmd_buffer->state.predication_va = 0;
4685 }
4686
4687 /* VK_EXT_transform_feedback */
4688 void radv_CmdBindTransformFeedbackBuffersEXT(
4689 VkCommandBuffer commandBuffer,
4690 uint32_t firstBinding,
4691 uint32_t bindingCount,
4692 const VkBuffer* pBuffers,
4693 const VkDeviceSize* pOffsets,
4694 const VkDeviceSize* pSizes)
4695 {
4696 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4697 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4698 uint8_t enabled_mask = 0;
4699
4700 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4701 for (uint32_t i = 0; i < bindingCount; i++) {
4702 uint32_t idx = firstBinding + i;
4703
4704 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4705 sb[idx].offset = pOffsets[i];
4706 sb[idx].size = pSizes[i];
4707
4708 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4709 sb[idx].buffer->bo);
4710
4711 enabled_mask |= 1 << idx;
4712 }
4713
4714 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4715
4716 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4717 }
4718
4719 static void
4720 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4721 {
4722 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4724
4725 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4726 radeon_emit(cs,
4727 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4728 S_028B94_RAST_STREAM(0) |
4729 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4730 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4731 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4732 radeon_emit(cs, so->hw_enabled_mask &
4733 so->enabled_stream_buffers_mask);
4734 }
4735
4736 static void
4737 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4738 {
4739 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4740 bool old_streamout_enabled = so->streamout_enabled;
4741 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4742
4743 so->streamout_enabled = enable;
4744
4745 so->hw_enabled_mask = so->enabled_mask |
4746 (so->enabled_mask << 4) |
4747 (so->enabled_mask << 8) |
4748 (so->enabled_mask << 12);
4749
4750 if ((old_streamout_enabled != so->streamout_enabled) ||
4751 (old_hw_enabled_mask != so->hw_enabled_mask))
4752 radv_emit_streamout_enable(cmd_buffer);
4753 }
4754
4755 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4756 {
4757 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4758 unsigned reg_strmout_cntl;
4759
4760 /* The register is at different places on different ASICs. */
4761 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4762 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4763 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4764 } else {
4765 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4766 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4767 }
4768
4769 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4770 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4771
4772 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4773 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4774 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4775 radeon_emit(cs, 0);
4776 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4777 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4778 radeon_emit(cs, 4); /* poll interval */
4779 }
4780
4781 void radv_CmdBeginTransformFeedbackEXT(
4782 VkCommandBuffer commandBuffer,
4783 uint32_t firstCounterBuffer,
4784 uint32_t counterBufferCount,
4785 const VkBuffer* pCounterBuffers,
4786 const VkDeviceSize* pCounterBufferOffsets)
4787 {
4788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4789 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4790 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4791 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4792 uint32_t i;
4793
4794 radv_flush_vgt_streamout(cmd_buffer);
4795
4796 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4797 for_each_bit(i, so->enabled_mask) {
4798 int32_t counter_buffer_idx = i - firstCounterBuffer;
4799 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4800 counter_buffer_idx = -1;
4801
4802 /* SI binds streamout buffers as shader resources.
4803 * VGT only counts primitives and tells the shader through
4804 * SGPRs what to do.
4805 */
4806 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4807 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4808 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4809
4810 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4811 /* The array of counter buffers is optional. */
4812 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4813 uint64_t va = radv_buffer_get_va(buffer->bo);
4814
4815 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4816
4817 /* Append */
4818 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4819 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4820 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4821 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4822 radeon_emit(cs, 0); /* unused */
4823 radeon_emit(cs, 0); /* unused */
4824 radeon_emit(cs, va); /* src address lo */
4825 radeon_emit(cs, va >> 32); /* src address hi */
4826
4827 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4828 } else {
4829 /* Start from the beginning. */
4830 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4831 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4832 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4833 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4834 radeon_emit(cs, 0); /* unused */
4835 radeon_emit(cs, 0); /* unused */
4836 radeon_emit(cs, 0); /* unused */
4837 radeon_emit(cs, 0); /* unused */
4838 }
4839 }
4840
4841 radv_set_streamout_enable(cmd_buffer, true);
4842 }
4843
4844 void radv_CmdEndTransformFeedbackEXT(
4845 VkCommandBuffer commandBuffer,
4846 uint32_t firstCounterBuffer,
4847 uint32_t counterBufferCount,
4848 const VkBuffer* pCounterBuffers,
4849 const VkDeviceSize* pCounterBufferOffsets)
4850 {
4851 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4852 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4853 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4854 uint32_t i;
4855
4856 radv_flush_vgt_streamout(cmd_buffer);
4857
4858 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4859 for_each_bit(i, so->enabled_mask) {
4860 int32_t counter_buffer_idx = i - firstCounterBuffer;
4861 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4862 counter_buffer_idx = -1;
4863
4864 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4865 /* The array of counters buffer is optional. */
4866 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4867 uint64_t va = radv_buffer_get_va(buffer->bo);
4868
4869 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4870
4871 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4872 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4873 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4874 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4875 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4876 radeon_emit(cs, va); /* dst address lo */
4877 radeon_emit(cs, va >> 32); /* dst address hi */
4878 radeon_emit(cs, 0); /* unused */
4879 radeon_emit(cs, 0); /* unused */
4880
4881 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4882 }
4883
4884 /* Deactivate transform feedback by zeroing the buffer size.
4885 * The counters (primitives generated, primitives emitted) may
4886 * be enabled even if there is not buffer bound. This ensures
4887 * that the primitives-emitted query won't increment.
4888 */
4889 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4890 }
4891
4892 radv_set_streamout_enable(cmd_buffer, false);
4893 }
4894
4895 void radv_CmdDrawIndirectByteCountEXT(
4896 VkCommandBuffer commandBuffer,
4897 uint32_t instanceCount,
4898 uint32_t firstInstance,
4899 VkBuffer _counterBuffer,
4900 VkDeviceSize counterBufferOffset,
4901 uint32_t counterOffset,
4902 uint32_t vertexStride)
4903 {
4904 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4905 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4906 struct radv_draw_info info = {};
4907
4908 info.instance_count = instanceCount;
4909 info.first_instance = firstInstance;
4910 info.strmout_buffer = counterBuffer;
4911 info.strmout_buffer_offset = counterBufferOffset;
4912 info.stride = vertexStride;
4913
4914 radv_draw(cmd_buffer, &info);
4915 }