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radv: check if DCC is enabled per mip not for the whole image
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image_view *iview,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249 struct radv_image *image = iview->image;
1250
1251 if (!radv_layout_dcc_compressed(image, layout,
1252 radv_image_queue_family_mask(image,
1253 cmd_buffer->queue_family_index,
1254 cmd_buffer->queue_family_index))) {
1255 cb_color_info &= C_028C70_DCC_ENABLE;
1256 }
1257
1258 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1259 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1260 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1261 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1262 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1263 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1264 radeon_emit(cmd_buffer->cs, cb_color_info);
1265 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1266 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1267 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1268 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1270 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1271
1272 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1273 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1274 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1275
1276 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1277 cb->cb_mrt_epitch);
1278 } else {
1279 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1282 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1283 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1284 radeon_emit(cmd_buffer->cs, cb_color_info);
1285 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1286 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1288 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1290 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1291
1292 if (is_vi) { /* DCC BASE */
1293 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1294 }
1295 }
1296
1297 if (radv_dcc_enabled(image, iview->base_mip)) {
1298 /* Drawing with DCC enabled also compresses colorbuffers. */
1299 VkImageSubresourceRange range = {
1300 .aspectMask = iview->aspect_mask,
1301 .baseMipLevel = iview->base_mip,
1302 .levelCount = iview->level_count,
1303 .baseArrayLayer = iview->base_layer,
1304 .layerCount = iview->layer_count,
1305 };
1306
1307 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1308 }
1309 }
1310
1311 static void
1312 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1313 struct radv_ds_buffer_info *ds,
1314 struct radv_image *image, VkImageLayout layout,
1315 bool requires_cond_exec)
1316 {
1317 uint32_t db_z_info = ds->db_z_info;
1318 uint32_t db_z_info_reg;
1319
1320 if (!radv_image_is_tc_compat_htile(image))
1321 return;
1322
1323 if (!radv_layout_has_htile(image, layout,
1324 radv_image_queue_family_mask(image,
1325 cmd_buffer->queue_family_index,
1326 cmd_buffer->queue_family_index))) {
1327 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1328 }
1329
1330 db_z_info &= C_028040_ZRANGE_PRECISION;
1331
1332 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1333 db_z_info_reg = R_028038_DB_Z_INFO;
1334 } else {
1335 db_z_info_reg = R_028040_DB_Z_INFO;
1336 }
1337
1338 /* When we don't know the last fast clear value we need to emit a
1339 * conditional packet that will eventually skip the following
1340 * SET_CONTEXT_REG packet.
1341 */
1342 if (requires_cond_exec) {
1343 uint64_t va = radv_buffer_get_va(image->bo);
1344 va += image->offset + image->tc_compat_zrange_offset;
1345
1346 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1347 radeon_emit(cmd_buffer->cs, va);
1348 radeon_emit(cmd_buffer->cs, va >> 32);
1349 radeon_emit(cmd_buffer->cs, 0);
1350 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1351 }
1352
1353 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1354 }
1355
1356 static void
1357 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1358 struct radv_ds_buffer_info *ds,
1359 struct radv_image *image,
1360 VkImageLayout layout)
1361 {
1362 uint32_t db_z_info = ds->db_z_info;
1363 uint32_t db_stencil_info = ds->db_stencil_info;
1364
1365 if (!radv_layout_has_htile(image, layout,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1370 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1371 }
1372
1373 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1374 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1375
1376
1377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1378 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1379 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1380 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1381 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1382
1383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1384 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1385 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1386 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1387 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1388 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1389 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1390 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1391 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1392 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1393 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1394
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1396 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1398 } else {
1399 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1400
1401 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1402 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1403 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1404 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1405 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1406 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1407 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1408 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1409 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1410 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1411
1412 }
1413
1414 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1415 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1416
1417 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1418 ds->pa_su_poly_offset_db_fmt_cntl);
1419 }
1420
1421 /**
1422 * Update the fast clear depth/stencil values if the image is bound as a
1423 * depth/stencil buffer.
1424 */
1425 static void
1426 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_image *image,
1428 VkClearDepthStencilValue ds_clear_value,
1429 VkImageAspectFlags aspects)
1430 {
1431 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1432 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1433 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1434 struct radv_attachment_info *att;
1435 uint32_t att_idx;
1436
1437 if (!framebuffer || !subpass)
1438 return;
1439
1440 if (!subpass->depth_stencil_attachment)
1441 return;
1442
1443 att_idx = subpass->depth_stencil_attachment->attachment;
1444 att = &framebuffer->attachments[att_idx];
1445 if (att->attachment->image != image)
1446 return;
1447
1448 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1449 radeon_emit(cs, ds_clear_value.stencil);
1450 radeon_emit(cs, fui(ds_clear_value.depth));
1451
1452 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1453 * only needed when clearing Z to 0.0.
1454 */
1455 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1456 ds_clear_value.depth == 0.0) {
1457 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1458
1459 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1460 layout, false);
1461 }
1462
1463 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1464 }
1465
1466 /**
1467 * Set the clear depth/stencil values to the image's metadata.
1468 */
1469 static void
1470 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1471 struct radv_image *image,
1472 VkClearDepthStencilValue ds_clear_value,
1473 VkImageAspectFlags aspects)
1474 {
1475 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1476 uint64_t va = radv_buffer_get_va(image->bo);
1477 unsigned reg_offset = 0, reg_count = 0;
1478
1479 va += image->offset + image->clear_value_offset;
1480
1481 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1482 ++reg_count;
1483 } else {
1484 ++reg_offset;
1485 va += 4;
1486 }
1487 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1488 ++reg_count;
1489
1490 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1491 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1492 S_370_WR_CONFIRM(1) |
1493 S_370_ENGINE_SEL(V_370_PFP));
1494 radeon_emit(cs, va);
1495 radeon_emit(cs, va >> 32);
1496 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1497 radeon_emit(cs, ds_clear_value.stencil);
1498 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1499 radeon_emit(cs, fui(ds_clear_value.depth));
1500 }
1501
1502 /**
1503 * Update the TC-compat metadata value for this image.
1504 */
1505 static void
1506 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1507 struct radv_image *image,
1508 uint32_t value)
1509 {
1510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1511 uint64_t va = radv_buffer_get_va(image->bo);
1512 va += image->offset + image->tc_compat_zrange_offset;
1513
1514 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1515 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1516 S_370_WR_CONFIRM(1) |
1517 S_370_ENGINE_SEL(V_370_PFP));
1518 radeon_emit(cs, va);
1519 radeon_emit(cs, va >> 32);
1520 radeon_emit(cs, value);
1521 }
1522
1523 static void
1524 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1525 struct radv_image *image,
1526 VkClearDepthStencilValue ds_clear_value)
1527 {
1528 uint64_t va = radv_buffer_get_va(image->bo);
1529 va += image->offset + image->tc_compat_zrange_offset;
1530 uint32_t cond_val;
1531
1532 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1533 * depth clear value is 0.0f.
1534 */
1535 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1536
1537 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1538 }
1539
1540 /**
1541 * Update the clear depth/stencil values for this image.
1542 */
1543 void
1544 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1545 struct radv_image *image,
1546 VkClearDepthStencilValue ds_clear_value,
1547 VkImageAspectFlags aspects)
1548 {
1549 assert(radv_image_has_htile(image));
1550
1551 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1552
1553 if (radv_image_is_tc_compat_htile(image) &&
1554 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1555 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1556 ds_clear_value);
1557 }
1558
1559 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1560 aspects);
1561 }
1562
1563 /**
1564 * Load the clear depth/stencil values from the image's metadata.
1565 */
1566 static void
1567 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_image *image)
1569 {
1570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1571 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1572 uint64_t va = radv_buffer_get_va(image->bo);
1573 unsigned reg_offset = 0, reg_count = 0;
1574
1575 va += image->offset + image->clear_value_offset;
1576
1577 if (!radv_image_has_htile(image))
1578 return;
1579
1580 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1581 ++reg_count;
1582 } else {
1583 ++reg_offset;
1584 va += 4;
1585 }
1586 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1587 ++reg_count;
1588
1589 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1590
1591 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1592 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1593 radeon_emit(cs, va);
1594 radeon_emit(cs, va >> 32);
1595 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1596 radeon_emit(cs, reg_count);
1597 } else {
1598 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1599 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1600 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1601 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1602 radeon_emit(cs, va);
1603 radeon_emit(cs, va >> 32);
1604 radeon_emit(cs, reg >> 2);
1605 radeon_emit(cs, 0);
1606
1607 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1608 radeon_emit(cs, 0);
1609 }
1610 }
1611
1612 /*
1613 * With DCC some colors don't require CMASK elimination before being
1614 * used as a texture. This sets a predicate value to determine if the
1615 * cmask eliminate is required.
1616 */
1617 void
1618 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1619 struct radv_image *image,
1620 const VkImageSubresourceRange *range, bool value)
1621 {
1622 uint64_t pred_val = value;
1623 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1624 uint32_t level_count = radv_get_levelCount(image, range);
1625 uint32_t count = 2 * level_count;
1626
1627 assert(radv_dcc_enabled(image, range->baseMipLevel));
1628
1629 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1630 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1631 S_370_WR_CONFIRM(1) |
1632 S_370_ENGINE_SEL(V_370_PFP));
1633 radeon_emit(cmd_buffer->cs, va);
1634 radeon_emit(cmd_buffer->cs, va >> 32);
1635
1636 for (uint32_t l = 0; l < level_count; l++) {
1637 radeon_emit(cmd_buffer->cs, pred_val);
1638 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1639 }
1640 }
1641
1642 /**
1643 * Update the DCC predicate to reflect the compression state.
1644 */
1645 void
1646 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1647 struct radv_image *image,
1648 const VkImageSubresourceRange *range, bool value)
1649 {
1650 uint64_t pred_val = value;
1651 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1652 uint32_t level_count = radv_get_levelCount(image, range);
1653 uint32_t count = 2 * level_count;
1654
1655 assert(radv_dcc_enabled(image, range->baseMipLevel));
1656
1657 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1658 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1659 S_370_WR_CONFIRM(1) |
1660 S_370_ENGINE_SEL(V_370_PFP));
1661 radeon_emit(cmd_buffer->cs, va);
1662 radeon_emit(cmd_buffer->cs, va >> 32);
1663
1664 for (uint32_t l = 0; l < level_count; l++) {
1665 radeon_emit(cmd_buffer->cs, pred_val);
1666 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1667 }
1668 }
1669
1670 /**
1671 * Update the fast clear color values if the image is bound as a color buffer.
1672 */
1673 static void
1674 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1675 struct radv_image *image,
1676 int cb_idx,
1677 uint32_t color_values[2])
1678 {
1679 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1680 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1681 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1682 struct radv_attachment_info *att;
1683 uint32_t att_idx;
1684
1685 if (!framebuffer || !subpass)
1686 return;
1687
1688 att_idx = subpass->color_attachments[cb_idx].attachment;
1689 if (att_idx == VK_ATTACHMENT_UNUSED)
1690 return;
1691
1692 att = &framebuffer->attachments[att_idx];
1693 if (att->attachment->image != image)
1694 return;
1695
1696 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1697 radeon_emit(cs, color_values[0]);
1698 radeon_emit(cs, color_values[1]);
1699
1700 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1701 }
1702
1703 /**
1704 * Set the clear color values to the image's metadata.
1705 */
1706 static void
1707 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1708 struct radv_image *image,
1709 const VkImageSubresourceRange *range,
1710 uint32_t color_values[2])
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1714 uint32_t level_count = radv_get_levelCount(image, range);
1715 uint32_t count = 2 * level_count;
1716
1717 assert(radv_image_has_cmask(image) ||
1718 radv_dcc_enabled(image, range->baseMipLevel));
1719
1720 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1721 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_PFP));
1724 radeon_emit(cs, va);
1725 radeon_emit(cs, va >> 32);
1726
1727 for (uint32_t l = 0; l < level_count; l++) {
1728 radeon_emit(cs, color_values[0]);
1729 radeon_emit(cs, color_values[1]);
1730 }
1731 }
1732
1733 /**
1734 * Update the clear color values for this image.
1735 */
1736 void
1737 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1738 const struct radv_image_view *iview,
1739 int cb_idx,
1740 uint32_t color_values[2])
1741 {
1742 struct radv_image *image = iview->image;
1743 VkImageSubresourceRange range = {
1744 .aspectMask = iview->aspect_mask,
1745 .baseMipLevel = iview->base_mip,
1746 .levelCount = iview->level_count,
1747 .baseArrayLayer = iview->base_layer,
1748 .layerCount = iview->layer_count,
1749 };
1750
1751 assert(radv_image_has_cmask(image) ||
1752 radv_dcc_enabled(image, iview->base_mip));
1753
1754 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1755
1756 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1757 color_values);
1758 }
1759
1760 /**
1761 * Load the clear color values from the image's metadata.
1762 */
1763 static void
1764 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1765 struct radv_image_view *iview,
1766 int cb_idx)
1767 {
1768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1769 struct radv_image *image = iview->image;
1770 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1771
1772 if (!radv_image_has_cmask(image) &&
1773 !radv_dcc_enabled(image, iview->base_mip))
1774 return;
1775
1776 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1777
1778 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1779 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1780 radeon_emit(cs, va);
1781 radeon_emit(cs, va >> 32);
1782 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1783 radeon_emit(cs, 2);
1784 } else {
1785 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1786 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1787 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1788 COPY_DATA_COUNT_SEL);
1789 radeon_emit(cs, va);
1790 radeon_emit(cs, va >> 32);
1791 radeon_emit(cs, reg >> 2);
1792 radeon_emit(cs, 0);
1793
1794 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1795 radeon_emit(cs, 0);
1796 }
1797 }
1798
1799 static void
1800 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1801 {
1802 int i;
1803 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1804 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1805 unsigned num_bpp64_colorbufs = 0;
1806
1807 /* this may happen for inherited secondary recording */
1808 if (!framebuffer)
1809 return;
1810
1811 for (i = 0; i < 8; ++i) {
1812 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1813 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1814 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1815 continue;
1816 }
1817
1818 int idx = subpass->color_attachments[i].attachment;
1819 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1820 struct radv_image_view *iview = att->attachment;
1821 struct radv_image *image = iview->image;
1822 VkImageLayout layout = subpass->color_attachments[i].layout;
1823
1824 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1825
1826 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1827 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1828 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1829
1830 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1831
1832 if (image->planes[0].surface.bpe >= 8)
1833 num_bpp64_colorbufs++;
1834 }
1835
1836 if (subpass->depth_stencil_attachment) {
1837 int idx = subpass->depth_stencil_attachment->attachment;
1838 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1839 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1840 struct radv_image *image = att->attachment->image;
1841 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1842 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1843 cmd_buffer->queue_family_index,
1844 cmd_buffer->queue_family_index);
1845 /* We currently don't support writing decompressed HTILE */
1846 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1847 radv_layout_is_htile_compressed(image, layout, queue_mask));
1848
1849 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1850
1851 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1852 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1853 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1854 }
1855 radv_load_ds_clear_metadata(cmd_buffer, image);
1856 } else {
1857 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1858 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1859 else
1860 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1861
1862 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1863 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1864 }
1865 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1866 S_028208_BR_X(framebuffer->width) |
1867 S_028208_BR_Y(framebuffer->height));
1868
1869 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1870 uint8_t watermark = 4; /* Default value for GFX8. */
1871
1872 /* For optimal DCC performance. */
1873 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1874 if (num_bpp64_colorbufs >= 5) {
1875 watermark = 8;
1876 } else {
1877 watermark = 6;
1878 }
1879 }
1880
1881 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1882 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1883 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1884 }
1885
1886 if (cmd_buffer->device->dfsm_allowed) {
1887 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1888 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1889 }
1890
1891 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1892 }
1893
1894 static void
1895 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1896 {
1897 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1898 struct radv_cmd_state *state = &cmd_buffer->state;
1899
1900 if (state->index_type != state->last_index_type) {
1901 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1902 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1903 2, state->index_type);
1904 } else {
1905 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1906 radeon_emit(cs, state->index_type);
1907 }
1908
1909 state->last_index_type = state->index_type;
1910 }
1911
1912 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1913 radeon_emit(cs, state->index_va);
1914 radeon_emit(cs, state->index_va >> 32);
1915
1916 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1917 radeon_emit(cs, state->max_index_count);
1918
1919 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1920 }
1921
1922 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1923 {
1924 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1925 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1926 uint32_t pa_sc_mode_cntl_1 =
1927 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1928 uint32_t db_count_control;
1929
1930 if(!cmd_buffer->state.active_occlusion_queries) {
1931 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1932 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1933 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1934 has_perfect_queries) {
1935 /* Re-enable out-of-order rasterization if the
1936 * bound pipeline supports it and if it's has
1937 * been disabled before starting any perfect
1938 * occlusion queries.
1939 */
1940 radeon_set_context_reg(cmd_buffer->cs,
1941 R_028A4C_PA_SC_MODE_CNTL_1,
1942 pa_sc_mode_cntl_1);
1943 }
1944 }
1945 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1946 } else {
1947 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1948 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1949
1950 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1951 db_count_control =
1952 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1953 S_028004_SAMPLE_RATE(sample_rate) |
1954 S_028004_ZPASS_ENABLE(1) |
1955 S_028004_SLICE_EVEN_ENABLE(1) |
1956 S_028004_SLICE_ODD_ENABLE(1);
1957
1958 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1959 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1960 has_perfect_queries) {
1961 /* If the bound pipeline has enabled
1962 * out-of-order rasterization, we should
1963 * disable it before starting any perfect
1964 * occlusion queries.
1965 */
1966 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1967
1968 radeon_set_context_reg(cmd_buffer->cs,
1969 R_028A4C_PA_SC_MODE_CNTL_1,
1970 pa_sc_mode_cntl_1);
1971 }
1972 } else {
1973 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1974 S_028004_SAMPLE_RATE(sample_rate);
1975 }
1976 }
1977
1978 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1979
1980 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1981 }
1982
1983 static void
1984 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1985 {
1986 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1987
1988 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1989 radv_emit_viewport(cmd_buffer);
1990
1991 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1992 !cmd_buffer->device->physical_device->has_scissor_bug)
1993 radv_emit_scissor(cmd_buffer);
1994
1995 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1996 radv_emit_line_width(cmd_buffer);
1997
1998 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1999 radv_emit_blend_constants(cmd_buffer);
2000
2001 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2002 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2003 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2004 radv_emit_stencil(cmd_buffer);
2005
2006 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2007 radv_emit_depth_bounds(cmd_buffer);
2008
2009 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2010 radv_emit_depth_bias(cmd_buffer);
2011
2012 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2013 radv_emit_discard_rectangle(cmd_buffer);
2014
2015 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2016 radv_emit_sample_locations(cmd_buffer);
2017
2018 cmd_buffer->state.dirty &= ~states;
2019 }
2020
2021 static void
2022 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2023 VkPipelineBindPoint bind_point)
2024 {
2025 struct radv_descriptor_state *descriptors_state =
2026 radv_get_descriptors_state(cmd_buffer, bind_point);
2027 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2028 unsigned bo_offset;
2029
2030 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2031 set->mapped_ptr,
2032 &bo_offset))
2033 return;
2034
2035 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2036 set->va += bo_offset;
2037 }
2038
2039 static void
2040 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2041 VkPipelineBindPoint bind_point)
2042 {
2043 struct radv_descriptor_state *descriptors_state =
2044 radv_get_descriptors_state(cmd_buffer, bind_point);
2045 uint32_t size = MAX_SETS * 4;
2046 uint32_t offset;
2047 void *ptr;
2048
2049 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2050 256, &offset, &ptr))
2051 return;
2052
2053 for (unsigned i = 0; i < MAX_SETS; i++) {
2054 uint32_t *uptr = ((uint32_t *)ptr) + i;
2055 uint64_t set_va = 0;
2056 struct radv_descriptor_set *set = descriptors_state->sets[i];
2057 if (descriptors_state->valid & (1u << i))
2058 set_va = set->va;
2059 uptr[0] = set_va & 0xffffffff;
2060 }
2061
2062 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2063 va += offset;
2064
2065 if (cmd_buffer->state.pipeline) {
2066 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2067 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2068 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2069
2070 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2071 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2072 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2073
2074 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2075 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2076 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2077
2078 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2079 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2080 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2081
2082 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2083 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2084 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2085 }
2086
2087 if (cmd_buffer->state.compute_pipeline)
2088 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2089 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2090 }
2091
2092 static void
2093 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2094 VkShaderStageFlags stages)
2095 {
2096 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2097 VK_PIPELINE_BIND_POINT_COMPUTE :
2098 VK_PIPELINE_BIND_POINT_GRAPHICS;
2099 struct radv_descriptor_state *descriptors_state =
2100 radv_get_descriptors_state(cmd_buffer, bind_point);
2101 struct radv_cmd_state *state = &cmd_buffer->state;
2102 bool flush_indirect_descriptors;
2103
2104 if (!descriptors_state->dirty)
2105 return;
2106
2107 if (descriptors_state->push_dirty)
2108 radv_flush_push_descriptors(cmd_buffer, bind_point);
2109
2110 flush_indirect_descriptors =
2111 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2112 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2113 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2114 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2115
2116 if (flush_indirect_descriptors)
2117 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2118
2119 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2120 cmd_buffer->cs,
2121 MAX_SETS * MESA_SHADER_STAGES * 4);
2122
2123 if (cmd_buffer->state.pipeline) {
2124 radv_foreach_stage(stage, stages) {
2125 if (!cmd_buffer->state.pipeline->shaders[stage])
2126 continue;
2127
2128 radv_emit_descriptor_pointers(cmd_buffer,
2129 cmd_buffer->state.pipeline,
2130 descriptors_state, stage);
2131 }
2132 }
2133
2134 if (cmd_buffer->state.compute_pipeline &&
2135 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2136 radv_emit_descriptor_pointers(cmd_buffer,
2137 cmd_buffer->state.compute_pipeline,
2138 descriptors_state,
2139 MESA_SHADER_COMPUTE);
2140 }
2141
2142 descriptors_state->dirty = 0;
2143 descriptors_state->push_dirty = false;
2144
2145 assert(cmd_buffer->cs->cdw <= cdw_max);
2146
2147 if (unlikely(cmd_buffer->device->trace_bo))
2148 radv_save_descriptors(cmd_buffer, bind_point);
2149 }
2150
2151 static void
2152 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2153 VkShaderStageFlags stages)
2154 {
2155 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2156 ? cmd_buffer->state.compute_pipeline
2157 : cmd_buffer->state.pipeline;
2158 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2159 VK_PIPELINE_BIND_POINT_COMPUTE :
2160 VK_PIPELINE_BIND_POINT_GRAPHICS;
2161 struct radv_descriptor_state *descriptors_state =
2162 radv_get_descriptors_state(cmd_buffer, bind_point);
2163 struct radv_pipeline_layout *layout = pipeline->layout;
2164 struct radv_shader_variant *shader, *prev_shader;
2165 bool need_push_constants = false;
2166 unsigned offset;
2167 void *ptr;
2168 uint64_t va;
2169
2170 stages &= cmd_buffer->push_constant_stages;
2171 if (!stages ||
2172 (!layout->push_constant_size && !layout->dynamic_offset_count))
2173 return;
2174
2175 radv_foreach_stage(stage, stages) {
2176 if (!pipeline->shaders[stage])
2177 continue;
2178
2179 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2180 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2181
2182 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2183 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2184
2185 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2186 AC_UD_INLINE_PUSH_CONSTANTS,
2187 count,
2188 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2189 }
2190
2191 if (need_push_constants) {
2192 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2193 16 * layout->dynamic_offset_count,
2194 256, &offset, &ptr))
2195 return;
2196
2197 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2198 memcpy((char*)ptr + layout->push_constant_size,
2199 descriptors_state->dynamic_buffers,
2200 16 * layout->dynamic_offset_count);
2201
2202 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2203 va += offset;
2204
2205 MAYBE_UNUSED unsigned cdw_max =
2206 radeon_check_space(cmd_buffer->device->ws,
2207 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2208
2209 prev_shader = NULL;
2210 radv_foreach_stage(stage, stages) {
2211 shader = radv_get_shader(pipeline, stage);
2212
2213 /* Avoid redundantly emitting the address for merged stages. */
2214 if (shader && shader != prev_shader) {
2215 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2216 AC_UD_PUSH_CONSTANTS, va);
2217
2218 prev_shader = shader;
2219 }
2220 }
2221 assert(cmd_buffer->cs->cdw <= cdw_max);
2222 }
2223
2224 cmd_buffer->push_constant_stages &= ~stages;
2225 }
2226
2227 static void
2228 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2229 bool pipeline_is_dirty)
2230 {
2231 if ((pipeline_is_dirty ||
2232 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2233 cmd_buffer->state.pipeline->num_vertex_bindings &&
2234 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2235 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2236 unsigned vb_offset;
2237 void *vb_ptr;
2238 uint32_t i = 0;
2239 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2240 uint64_t va;
2241
2242 /* allocate some descriptor state for vertex buffers */
2243 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2244 &vb_offset, &vb_ptr))
2245 return;
2246
2247 for (i = 0; i < count; i++) {
2248 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2249 uint32_t offset;
2250 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2251 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2252
2253 if (!buffer)
2254 continue;
2255
2256 va = radv_buffer_get_va(buffer->bo);
2257
2258 offset = cmd_buffer->vertex_bindings[i].offset;
2259 va += offset + buffer->offset;
2260 desc[0] = va;
2261 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2262 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2263 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2264 else
2265 desc[2] = buffer->size - offset;
2266 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2267 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2268 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2269 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2270 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2271 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2272 }
2273
2274 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2275 va += vb_offset;
2276
2277 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2278 AC_UD_VS_VERTEX_BUFFERS, va);
2279
2280 cmd_buffer->state.vb_va = va;
2281 cmd_buffer->state.vb_size = count * 16;
2282 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2283 }
2284 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2285 }
2286
2287 static void
2288 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2289 {
2290 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2291 struct radv_userdata_info *loc;
2292 uint32_t base_reg;
2293
2294 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2295 if (!radv_get_shader(pipeline, stage))
2296 continue;
2297
2298 loc = radv_lookup_user_sgpr(pipeline, stage,
2299 AC_UD_STREAMOUT_BUFFERS);
2300 if (loc->sgpr_idx == -1)
2301 continue;
2302
2303 base_reg = pipeline->user_data_0[stage];
2304
2305 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2306 base_reg + loc->sgpr_idx * 4, va, false);
2307 }
2308
2309 if (pipeline->gs_copy_shader) {
2310 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2311 if (loc->sgpr_idx != -1) {
2312 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2313
2314 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2315 base_reg + loc->sgpr_idx * 4, va, false);
2316 }
2317 }
2318 }
2319
2320 static void
2321 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2322 {
2323 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2324 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2325 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2326 unsigned so_offset;
2327 void *so_ptr;
2328 uint64_t va;
2329
2330 /* Allocate some descriptor state for streamout buffers. */
2331 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2332 MAX_SO_BUFFERS * 16, 256,
2333 &so_offset, &so_ptr))
2334 return;
2335
2336 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2337 struct radv_buffer *buffer = sb[i].buffer;
2338 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2339
2340 if (!(so->enabled_mask & (1 << i)))
2341 continue;
2342
2343 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2344
2345 va += sb[i].offset;
2346
2347 /* Set the descriptor.
2348 *
2349 * On GFX8, the format must be non-INVALID, otherwise
2350 * the buffer will be considered not bound and store
2351 * instructions will be no-ops.
2352 */
2353 desc[0] = va;
2354 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2355 desc[2] = 0xffffffff;
2356 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2357 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2358 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2359 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2360 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2361 }
2362
2363 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2364 va += so_offset;
2365
2366 radv_emit_streamout_buffers(cmd_buffer, va);
2367 }
2368
2369 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2370 }
2371
2372 static void
2373 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2374 {
2375 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2376 radv_flush_streamout_descriptors(cmd_buffer);
2377 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2378 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2379 }
2380
2381 struct radv_draw_info {
2382 /**
2383 * Number of vertices.
2384 */
2385 uint32_t count;
2386
2387 /**
2388 * Index of the first vertex.
2389 */
2390 int32_t vertex_offset;
2391
2392 /**
2393 * First instance id.
2394 */
2395 uint32_t first_instance;
2396
2397 /**
2398 * Number of instances.
2399 */
2400 uint32_t instance_count;
2401
2402 /**
2403 * First index (indexed draws only).
2404 */
2405 uint32_t first_index;
2406
2407 /**
2408 * Whether it's an indexed draw.
2409 */
2410 bool indexed;
2411
2412 /**
2413 * Indirect draw parameters resource.
2414 */
2415 struct radv_buffer *indirect;
2416 uint64_t indirect_offset;
2417 uint32_t stride;
2418
2419 /**
2420 * Draw count parameters resource.
2421 */
2422 struct radv_buffer *count_buffer;
2423 uint64_t count_buffer_offset;
2424
2425 /**
2426 * Stream output parameters resource.
2427 */
2428 struct radv_buffer *strmout_buffer;
2429 uint64_t strmout_buffer_offset;
2430 };
2431
2432 static void
2433 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2434 const struct radv_draw_info *draw_info)
2435 {
2436 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2437 struct radv_cmd_state *state = &cmd_buffer->state;
2438 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2439 uint32_t ia_multi_vgt_param;
2440 int32_t primitive_reset_en;
2441
2442 /* Draw state. */
2443 ia_multi_vgt_param =
2444 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2445 draw_info->indirect,
2446 !!draw_info->strmout_buffer,
2447 draw_info->indirect ? 0 : draw_info->count);
2448
2449 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2450 if (info->chip_class >= GFX9) {
2451 radeon_set_uconfig_reg_idx(cs,
2452 R_030960_IA_MULTI_VGT_PARAM,
2453 4, ia_multi_vgt_param);
2454 } else if (info->chip_class >= GFX7) {
2455 radeon_set_context_reg_idx(cs,
2456 R_028AA8_IA_MULTI_VGT_PARAM,
2457 1, ia_multi_vgt_param);
2458 } else {
2459 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2460 ia_multi_vgt_param);
2461 }
2462 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2463 }
2464
2465 /* Primitive restart. */
2466 primitive_reset_en =
2467 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2468
2469 if (primitive_reset_en != state->last_primitive_reset_en) {
2470 state->last_primitive_reset_en = primitive_reset_en;
2471 if (info->chip_class >= GFX9) {
2472 radeon_set_uconfig_reg(cs,
2473 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2474 primitive_reset_en);
2475 } else {
2476 radeon_set_context_reg(cs,
2477 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2478 primitive_reset_en);
2479 }
2480 }
2481
2482 if (primitive_reset_en) {
2483 uint32_t primitive_reset_index =
2484 state->index_type ? 0xffffffffu : 0xffffu;
2485
2486 if (primitive_reset_index != state->last_primitive_reset_index) {
2487 radeon_set_context_reg(cs,
2488 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2489 primitive_reset_index);
2490 state->last_primitive_reset_index = primitive_reset_index;
2491 }
2492 }
2493
2494 if (draw_info->strmout_buffer) {
2495 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2496
2497 va += draw_info->strmout_buffer->offset +
2498 draw_info->strmout_buffer_offset;
2499
2500 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2501 draw_info->stride);
2502
2503 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2504 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2505 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2506 COPY_DATA_WR_CONFIRM);
2507 radeon_emit(cs, va);
2508 radeon_emit(cs, va >> 32);
2509 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2510 radeon_emit(cs, 0); /* unused */
2511
2512 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2513 }
2514 }
2515
2516 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2517 VkPipelineStageFlags src_stage_mask)
2518 {
2519 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2520 VK_PIPELINE_STAGE_TRANSFER_BIT |
2521 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2522 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2523 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2524 }
2525
2526 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2527 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2528 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2529 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2530 VK_PIPELINE_STAGE_TRANSFER_BIT |
2531 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2532 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2533 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2534 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2535 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2536 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2537 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2538 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2539 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2540 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2541 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2542 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2543 }
2544 }
2545
2546 static enum radv_cmd_flush_bits
2547 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2548 VkAccessFlags src_flags,
2549 struct radv_image *image)
2550 {
2551 bool flush_CB_meta = true, flush_DB_meta = true;
2552 enum radv_cmd_flush_bits flush_bits = 0;
2553 uint32_t b;
2554
2555 if (image) {
2556 if (!radv_image_has_CB_metadata(image))
2557 flush_CB_meta = false;
2558 if (!radv_image_has_htile(image))
2559 flush_DB_meta = false;
2560 }
2561
2562 for_each_bit(b, src_flags) {
2563 switch ((VkAccessFlagBits)(1 << b)) {
2564 case VK_ACCESS_SHADER_WRITE_BIT:
2565 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2566 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2567 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2568 break;
2569 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2570 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2571 if (flush_CB_meta)
2572 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2573 break;
2574 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2575 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2576 if (flush_DB_meta)
2577 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2578 break;
2579 case VK_ACCESS_TRANSFER_WRITE_BIT:
2580 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2581 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2582 RADV_CMD_FLAG_INV_GLOBAL_L2;
2583
2584 if (flush_CB_meta)
2585 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2586 if (flush_DB_meta)
2587 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2588 break;
2589 default:
2590 break;
2591 }
2592 }
2593 return flush_bits;
2594 }
2595
2596 static enum radv_cmd_flush_bits
2597 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2598 VkAccessFlags dst_flags,
2599 struct radv_image *image)
2600 {
2601 bool flush_CB_meta = true, flush_DB_meta = true;
2602 enum radv_cmd_flush_bits flush_bits = 0;
2603 bool flush_CB = true, flush_DB = true;
2604 bool image_is_coherent = false;
2605 uint32_t b;
2606
2607 if (image) {
2608 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2609 flush_CB = false;
2610 flush_DB = false;
2611 }
2612
2613 if (!radv_image_has_CB_metadata(image))
2614 flush_CB_meta = false;
2615 if (!radv_image_has_htile(image))
2616 flush_DB_meta = false;
2617
2618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2619 if (image->info.samples == 1 &&
2620 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2621 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2622 !vk_format_is_stencil(image->vk_format)) {
2623 /* Single-sample color and single-sample depth
2624 * (not stencil) are coherent with shaders on
2625 * GFX9.
2626 */
2627 image_is_coherent = true;
2628 }
2629 }
2630 }
2631
2632 for_each_bit(b, dst_flags) {
2633 switch ((VkAccessFlagBits)(1 << b)) {
2634 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2635 case VK_ACCESS_INDEX_READ_BIT:
2636 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2637 break;
2638 case VK_ACCESS_UNIFORM_READ_BIT:
2639 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2640 break;
2641 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2642 case VK_ACCESS_TRANSFER_READ_BIT:
2643 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2644 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2645 RADV_CMD_FLAG_INV_GLOBAL_L2;
2646 break;
2647 case VK_ACCESS_SHADER_READ_BIT:
2648 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2649
2650 if (!image_is_coherent)
2651 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2652 break;
2653 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2654 if (flush_CB)
2655 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2656 if (flush_CB_meta)
2657 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2658 break;
2659 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2660 if (flush_DB)
2661 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2662 if (flush_DB_meta)
2663 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2664 break;
2665 default:
2666 break;
2667 }
2668 }
2669 return flush_bits;
2670 }
2671
2672 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2673 const struct radv_subpass_barrier *barrier)
2674 {
2675 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2676 NULL);
2677 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2678 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2679 NULL);
2680 }
2681
2682 static uint32_t
2683 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2684 {
2685 struct radv_cmd_state *state = &cmd_buffer->state;
2686 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2687
2688 /* The id of this subpass shouldn't exceed the number of subpasses in
2689 * this render pass minus 1.
2690 */
2691 assert(subpass_id < state->pass->subpass_count);
2692 return subpass_id;
2693 }
2694
2695 static struct radv_sample_locations_state *
2696 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2697 uint32_t att_idx,
2698 bool begin_subpass)
2699 {
2700 struct radv_cmd_state *state = &cmd_buffer->state;
2701 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2702 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2703
2704 if (view->image->info.samples == 1)
2705 return NULL;
2706
2707 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2708 /* Return the initial sample locations if this is the initial
2709 * layout transition of the given subpass attachemnt.
2710 */
2711 if (state->attachments[att_idx].sample_location.count > 0)
2712 return &state->attachments[att_idx].sample_location;
2713 } else {
2714 /* Otherwise return the subpass sample locations if defined. */
2715 if (state->subpass_sample_locs) {
2716 /* Because the driver sets the current subpass before
2717 * initial layout transitions, we should use the sample
2718 * locations from the previous subpass to avoid an
2719 * off-by-one problem. Otherwise, use the sample
2720 * locations for the current subpass for final layout
2721 * transitions.
2722 */
2723 if (begin_subpass)
2724 subpass_id--;
2725
2726 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2727 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2728 return &state->subpass_sample_locs[i].sample_location;
2729 }
2730 }
2731 }
2732
2733 return NULL;
2734 }
2735
2736 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2737 struct radv_subpass_attachment att,
2738 bool begin_subpass)
2739 {
2740 unsigned idx = att.attachment;
2741 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2742 struct radv_sample_locations_state *sample_locs;
2743 VkImageSubresourceRange range;
2744 range.aspectMask = 0;
2745 range.baseMipLevel = view->base_mip;
2746 range.levelCount = 1;
2747 range.baseArrayLayer = view->base_layer;
2748 range.layerCount = cmd_buffer->state.framebuffer->layers;
2749
2750 if (cmd_buffer->state.subpass->view_mask) {
2751 /* If the current subpass uses multiview, the driver might have
2752 * performed a fast color/depth clear to the whole image
2753 * (including all layers). To make sure the driver will
2754 * decompress the image correctly (if needed), we have to
2755 * account for the "real" number of layers. If the view mask is
2756 * sparse, this will decompress more layers than needed.
2757 */
2758 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2759 }
2760
2761 /* Get the subpass sample locations for the given attachment, if NULL
2762 * is returned the driver will use the default HW locations.
2763 */
2764 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2765 begin_subpass);
2766
2767 radv_handle_image_transition(cmd_buffer,
2768 view->image,
2769 cmd_buffer->state.attachments[idx].current_layout,
2770 att.layout, 0, 0, &range, sample_locs);
2771
2772 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2773
2774
2775 }
2776
2777 void
2778 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2779 const struct radv_subpass *subpass)
2780 {
2781 cmd_buffer->state.subpass = subpass;
2782
2783 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2784 }
2785
2786 static VkResult
2787 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2788 struct radv_render_pass *pass,
2789 const VkRenderPassBeginInfo *info)
2790 {
2791 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2792 vk_find_struct_const(info->pNext,
2793 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2794 struct radv_cmd_state *state = &cmd_buffer->state;
2795 struct radv_framebuffer *framebuffer = state->framebuffer;
2796
2797 if (!sample_locs) {
2798 state->subpass_sample_locs = NULL;
2799 return VK_SUCCESS;
2800 }
2801
2802 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2803 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2804 &sample_locs->pAttachmentInitialSampleLocations[i];
2805 uint32_t att_idx = att_sample_locs->attachmentIndex;
2806 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2807 struct radv_image *image = att->attachment->image;
2808
2809 assert(vk_format_is_depth_or_stencil(image->vk_format));
2810
2811 /* From the Vulkan spec 1.1.108:
2812 *
2813 * "If the image referenced by the framebuffer attachment at
2814 * index attachmentIndex was not created with
2815 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2816 * then the values specified in sampleLocationsInfo are
2817 * ignored."
2818 */
2819 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2820 continue;
2821
2822 const VkSampleLocationsInfoEXT *sample_locs_info =
2823 &att_sample_locs->sampleLocationsInfo;
2824
2825 state->attachments[att_idx].sample_location.per_pixel =
2826 sample_locs_info->sampleLocationsPerPixel;
2827 state->attachments[att_idx].sample_location.grid_size =
2828 sample_locs_info->sampleLocationGridSize;
2829 state->attachments[att_idx].sample_location.count =
2830 sample_locs_info->sampleLocationsCount;
2831 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2832 sample_locs_info->pSampleLocations,
2833 sample_locs_info->sampleLocationsCount);
2834 }
2835
2836 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2837 sample_locs->postSubpassSampleLocationsCount *
2838 sizeof(state->subpass_sample_locs[0]),
2839 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2840 if (state->subpass_sample_locs == NULL) {
2841 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2842 return cmd_buffer->record_result;
2843 }
2844
2845 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2846
2847 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2848 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2849 &sample_locs->pPostSubpassSampleLocations[i];
2850 const VkSampleLocationsInfoEXT *sample_locs_info =
2851 &subpass_sample_locs_info->sampleLocationsInfo;
2852
2853 state->subpass_sample_locs[i].subpass_idx =
2854 subpass_sample_locs_info->subpassIndex;
2855 state->subpass_sample_locs[i].sample_location.per_pixel =
2856 sample_locs_info->sampleLocationsPerPixel;
2857 state->subpass_sample_locs[i].sample_location.grid_size =
2858 sample_locs_info->sampleLocationGridSize;
2859 state->subpass_sample_locs[i].sample_location.count =
2860 sample_locs_info->sampleLocationsCount;
2861 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2862 sample_locs_info->pSampleLocations,
2863 sample_locs_info->sampleLocationsCount);
2864 }
2865
2866 return VK_SUCCESS;
2867 }
2868
2869 static VkResult
2870 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2871 struct radv_render_pass *pass,
2872 const VkRenderPassBeginInfo *info)
2873 {
2874 struct radv_cmd_state *state = &cmd_buffer->state;
2875
2876 if (pass->attachment_count == 0) {
2877 state->attachments = NULL;
2878 return VK_SUCCESS;
2879 }
2880
2881 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2882 pass->attachment_count *
2883 sizeof(state->attachments[0]),
2884 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2885 if (state->attachments == NULL) {
2886 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2887 return cmd_buffer->record_result;
2888 }
2889
2890 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2891 struct radv_render_pass_attachment *att = &pass->attachments[i];
2892 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2893 VkImageAspectFlags clear_aspects = 0;
2894
2895 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2896 /* color attachment */
2897 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2898 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2899 }
2900 } else {
2901 /* depthstencil attachment */
2902 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2903 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2904 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2905 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2906 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2907 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2908 }
2909 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2910 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2911 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2912 }
2913 }
2914
2915 state->attachments[i].pending_clear_aspects = clear_aspects;
2916 state->attachments[i].cleared_views = 0;
2917 if (clear_aspects && info) {
2918 assert(info->clearValueCount > i);
2919 state->attachments[i].clear_value = info->pClearValues[i];
2920 }
2921
2922 state->attachments[i].current_layout = att->initial_layout;
2923 state->attachments[i].sample_location.count = 0;
2924 }
2925
2926 return VK_SUCCESS;
2927 }
2928
2929 VkResult radv_AllocateCommandBuffers(
2930 VkDevice _device,
2931 const VkCommandBufferAllocateInfo *pAllocateInfo,
2932 VkCommandBuffer *pCommandBuffers)
2933 {
2934 RADV_FROM_HANDLE(radv_device, device, _device);
2935 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2936
2937 VkResult result = VK_SUCCESS;
2938 uint32_t i;
2939
2940 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2941
2942 if (!list_empty(&pool->free_cmd_buffers)) {
2943 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2944
2945 list_del(&cmd_buffer->pool_link);
2946 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2947
2948 result = radv_reset_cmd_buffer(cmd_buffer);
2949 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2950 cmd_buffer->level = pAllocateInfo->level;
2951
2952 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2953 } else {
2954 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2955 &pCommandBuffers[i]);
2956 }
2957 if (result != VK_SUCCESS)
2958 break;
2959 }
2960
2961 if (result != VK_SUCCESS) {
2962 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2963 i, pCommandBuffers);
2964
2965 /* From the Vulkan 1.0.66 spec:
2966 *
2967 * "vkAllocateCommandBuffers can be used to create multiple
2968 * command buffers. If the creation of any of those command
2969 * buffers fails, the implementation must destroy all
2970 * successfully created command buffer objects from this
2971 * command, set all entries of the pCommandBuffers array to
2972 * NULL and return the error."
2973 */
2974 memset(pCommandBuffers, 0,
2975 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2976 }
2977
2978 return result;
2979 }
2980
2981 void radv_FreeCommandBuffers(
2982 VkDevice device,
2983 VkCommandPool commandPool,
2984 uint32_t commandBufferCount,
2985 const VkCommandBuffer *pCommandBuffers)
2986 {
2987 for (uint32_t i = 0; i < commandBufferCount; i++) {
2988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2989
2990 if (cmd_buffer) {
2991 if (cmd_buffer->pool) {
2992 list_del(&cmd_buffer->pool_link);
2993 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2994 } else
2995 radv_cmd_buffer_destroy(cmd_buffer);
2996
2997 }
2998 }
2999 }
3000
3001 VkResult radv_ResetCommandBuffer(
3002 VkCommandBuffer commandBuffer,
3003 VkCommandBufferResetFlags flags)
3004 {
3005 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3006 return radv_reset_cmd_buffer(cmd_buffer);
3007 }
3008
3009 VkResult radv_BeginCommandBuffer(
3010 VkCommandBuffer commandBuffer,
3011 const VkCommandBufferBeginInfo *pBeginInfo)
3012 {
3013 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3014 VkResult result = VK_SUCCESS;
3015
3016 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3017 /* If the command buffer has already been resetted with
3018 * vkResetCommandBuffer, no need to do it again.
3019 */
3020 result = radv_reset_cmd_buffer(cmd_buffer);
3021 if (result != VK_SUCCESS)
3022 return result;
3023 }
3024
3025 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3026 cmd_buffer->state.last_primitive_reset_en = -1;
3027 cmd_buffer->state.last_index_type = -1;
3028 cmd_buffer->state.last_num_instances = -1;
3029 cmd_buffer->state.last_vertex_offset = -1;
3030 cmd_buffer->state.last_first_instance = -1;
3031 cmd_buffer->state.predication_type = -1;
3032 cmd_buffer->usage_flags = pBeginInfo->flags;
3033
3034 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3035 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3036 assert(pBeginInfo->pInheritanceInfo);
3037 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3038 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3039
3040 struct radv_subpass *subpass =
3041 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3042
3043 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3044 if (result != VK_SUCCESS)
3045 return result;
3046
3047 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3048 }
3049
3050 if (unlikely(cmd_buffer->device->trace_bo)) {
3051 struct radv_device *device = cmd_buffer->device;
3052
3053 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3054 device->trace_bo);
3055
3056 radv_cmd_buffer_trace_emit(cmd_buffer);
3057 }
3058
3059 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3060
3061 return result;
3062 }
3063
3064 void radv_CmdBindVertexBuffers(
3065 VkCommandBuffer commandBuffer,
3066 uint32_t firstBinding,
3067 uint32_t bindingCount,
3068 const VkBuffer* pBuffers,
3069 const VkDeviceSize* pOffsets)
3070 {
3071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3072 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3073 bool changed = false;
3074
3075 /* We have to defer setting up vertex buffer since we need the buffer
3076 * stride from the pipeline. */
3077
3078 assert(firstBinding + bindingCount <= MAX_VBS);
3079 for (uint32_t i = 0; i < bindingCount; i++) {
3080 uint32_t idx = firstBinding + i;
3081
3082 if (!changed &&
3083 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3084 vb[idx].offset != pOffsets[i])) {
3085 changed = true;
3086 }
3087
3088 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3089 vb[idx].offset = pOffsets[i];
3090
3091 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3092 vb[idx].buffer->bo);
3093 }
3094
3095 if (!changed) {
3096 /* No state changes. */
3097 return;
3098 }
3099
3100 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3101 }
3102
3103 void radv_CmdBindIndexBuffer(
3104 VkCommandBuffer commandBuffer,
3105 VkBuffer buffer,
3106 VkDeviceSize offset,
3107 VkIndexType indexType)
3108 {
3109 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3110 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3111
3112 if (cmd_buffer->state.index_buffer == index_buffer &&
3113 cmd_buffer->state.index_offset == offset &&
3114 cmd_buffer->state.index_type == indexType) {
3115 /* No state changes. */
3116 return;
3117 }
3118
3119 cmd_buffer->state.index_buffer = index_buffer;
3120 cmd_buffer->state.index_offset = offset;
3121 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3122 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3123 cmd_buffer->state.index_va += index_buffer->offset + offset;
3124
3125 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3126 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3127 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3128 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3129 }
3130
3131
3132 static void
3133 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3134 VkPipelineBindPoint bind_point,
3135 struct radv_descriptor_set *set, unsigned idx)
3136 {
3137 struct radeon_winsys *ws = cmd_buffer->device->ws;
3138
3139 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3140
3141 assert(set);
3142 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3143
3144 if (!cmd_buffer->device->use_global_bo_list) {
3145 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3146 if (set->descriptors[j])
3147 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3148 }
3149
3150 if(set->bo)
3151 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3152 }
3153
3154 void radv_CmdBindDescriptorSets(
3155 VkCommandBuffer commandBuffer,
3156 VkPipelineBindPoint pipelineBindPoint,
3157 VkPipelineLayout _layout,
3158 uint32_t firstSet,
3159 uint32_t descriptorSetCount,
3160 const VkDescriptorSet* pDescriptorSets,
3161 uint32_t dynamicOffsetCount,
3162 const uint32_t* pDynamicOffsets)
3163 {
3164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3165 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3166 unsigned dyn_idx = 0;
3167
3168 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3169 struct radv_descriptor_state *descriptors_state =
3170 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3171
3172 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3173 unsigned idx = i + firstSet;
3174 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3175 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3176
3177 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3178 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3179 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3180 assert(dyn_idx < dynamicOffsetCount);
3181
3182 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3183 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3184 dst[0] = va;
3185 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3186 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3187 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3188 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3189 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3190 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3191 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3193 cmd_buffer->push_constant_stages |=
3194 set->layout->dynamic_shader_stages;
3195 }
3196 }
3197 }
3198
3199 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3200 struct radv_descriptor_set *set,
3201 struct radv_descriptor_set_layout *layout,
3202 VkPipelineBindPoint bind_point)
3203 {
3204 struct radv_descriptor_state *descriptors_state =
3205 radv_get_descriptors_state(cmd_buffer, bind_point);
3206 set->size = layout->size;
3207 set->layout = layout;
3208
3209 if (descriptors_state->push_set.capacity < set->size) {
3210 size_t new_size = MAX2(set->size, 1024);
3211 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3212 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3213
3214 free(set->mapped_ptr);
3215 set->mapped_ptr = malloc(new_size);
3216
3217 if (!set->mapped_ptr) {
3218 descriptors_state->push_set.capacity = 0;
3219 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3220 return false;
3221 }
3222
3223 descriptors_state->push_set.capacity = new_size;
3224 }
3225
3226 return true;
3227 }
3228
3229 void radv_meta_push_descriptor_set(
3230 struct radv_cmd_buffer* cmd_buffer,
3231 VkPipelineBindPoint pipelineBindPoint,
3232 VkPipelineLayout _layout,
3233 uint32_t set,
3234 uint32_t descriptorWriteCount,
3235 const VkWriteDescriptorSet* pDescriptorWrites)
3236 {
3237 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3238 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3239 unsigned bo_offset;
3240
3241 assert(set == 0);
3242 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3243
3244 push_set->size = layout->set[set].layout->size;
3245 push_set->layout = layout->set[set].layout;
3246
3247 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3248 &bo_offset,
3249 (void**) &push_set->mapped_ptr))
3250 return;
3251
3252 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3253 push_set->va += bo_offset;
3254
3255 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3256 radv_descriptor_set_to_handle(push_set),
3257 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3258
3259 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3260 }
3261
3262 void radv_CmdPushDescriptorSetKHR(
3263 VkCommandBuffer commandBuffer,
3264 VkPipelineBindPoint pipelineBindPoint,
3265 VkPipelineLayout _layout,
3266 uint32_t set,
3267 uint32_t descriptorWriteCount,
3268 const VkWriteDescriptorSet* pDescriptorWrites)
3269 {
3270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3271 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3272 struct radv_descriptor_state *descriptors_state =
3273 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3274 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3275
3276 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3277
3278 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3279 layout->set[set].layout,
3280 pipelineBindPoint))
3281 return;
3282
3283 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3284 * because it is invalid, according to Vulkan spec.
3285 */
3286 for (int i = 0; i < descriptorWriteCount; i++) {
3287 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3288 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3289 }
3290
3291 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3292 radv_descriptor_set_to_handle(push_set),
3293 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3294
3295 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3296 descriptors_state->push_dirty = true;
3297 }
3298
3299 void radv_CmdPushDescriptorSetWithTemplateKHR(
3300 VkCommandBuffer commandBuffer,
3301 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3302 VkPipelineLayout _layout,
3303 uint32_t set,
3304 const void* pData)
3305 {
3306 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3307 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3308 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3309 struct radv_descriptor_state *descriptors_state =
3310 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3311 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3312
3313 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3314
3315 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3316 layout->set[set].layout,
3317 templ->bind_point))
3318 return;
3319
3320 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3321 descriptorUpdateTemplate, pData);
3322
3323 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3324 descriptors_state->push_dirty = true;
3325 }
3326
3327 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3328 VkPipelineLayout layout,
3329 VkShaderStageFlags stageFlags,
3330 uint32_t offset,
3331 uint32_t size,
3332 const void* pValues)
3333 {
3334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3335 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3336 cmd_buffer->push_constant_stages |= stageFlags;
3337 }
3338
3339 VkResult radv_EndCommandBuffer(
3340 VkCommandBuffer commandBuffer)
3341 {
3342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3343
3344 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3345 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3346 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3347
3348 /* Make sure to sync all pending active queries at the end of
3349 * command buffer.
3350 */
3351 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3352
3353 si_emit_cache_flush(cmd_buffer);
3354 }
3355
3356 /* Make sure CP DMA is idle at the end of IBs because the kernel
3357 * doesn't wait for it.
3358 */
3359 si_cp_dma_wait_for_idle(cmd_buffer);
3360
3361 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3362 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3363
3364 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3365 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3366
3367 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3368
3369 return cmd_buffer->record_result;
3370 }
3371
3372 static void
3373 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3374 {
3375 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3376
3377 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3378 return;
3379
3380 assert(!pipeline->ctx_cs.cdw);
3381
3382 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3383
3384 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3385 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3386
3387 cmd_buffer->compute_scratch_size_needed =
3388 MAX2(cmd_buffer->compute_scratch_size_needed,
3389 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3390
3391 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3392 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3393
3394 if (unlikely(cmd_buffer->device->trace_bo))
3395 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3396 }
3397
3398 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3399 VkPipelineBindPoint bind_point)
3400 {
3401 struct radv_descriptor_state *descriptors_state =
3402 radv_get_descriptors_state(cmd_buffer, bind_point);
3403
3404 descriptors_state->dirty |= descriptors_state->valid;
3405 }
3406
3407 void radv_CmdBindPipeline(
3408 VkCommandBuffer commandBuffer,
3409 VkPipelineBindPoint pipelineBindPoint,
3410 VkPipeline _pipeline)
3411 {
3412 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3413 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3414
3415 switch (pipelineBindPoint) {
3416 case VK_PIPELINE_BIND_POINT_COMPUTE:
3417 if (cmd_buffer->state.compute_pipeline == pipeline)
3418 return;
3419 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3420
3421 cmd_buffer->state.compute_pipeline = pipeline;
3422 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3423 break;
3424 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3425 if (cmd_buffer->state.pipeline == pipeline)
3426 return;
3427 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3428
3429 cmd_buffer->state.pipeline = pipeline;
3430 if (!pipeline)
3431 break;
3432
3433 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3434 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3435
3436 /* the new vertex shader might not have the same user regs */
3437 cmd_buffer->state.last_first_instance = -1;
3438 cmd_buffer->state.last_vertex_offset = -1;
3439
3440 /* Prefetch all pipeline shaders at first draw time. */
3441 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3442
3443 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3444 radv_bind_streamout_state(cmd_buffer, pipeline);
3445
3446 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3447 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3448 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3449 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3450
3451 if (radv_pipeline_has_tess(pipeline))
3452 cmd_buffer->tess_rings_needed = true;
3453 break;
3454 default:
3455 assert(!"invalid bind point");
3456 break;
3457 }
3458 }
3459
3460 void radv_CmdSetViewport(
3461 VkCommandBuffer commandBuffer,
3462 uint32_t firstViewport,
3463 uint32_t viewportCount,
3464 const VkViewport* pViewports)
3465 {
3466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3467 struct radv_cmd_state *state = &cmd_buffer->state;
3468 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3469
3470 assert(firstViewport < MAX_VIEWPORTS);
3471 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3472
3473 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3474 pViewports, viewportCount * sizeof(*pViewports))) {
3475 return;
3476 }
3477
3478 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3479 viewportCount * sizeof(*pViewports));
3480
3481 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3482 }
3483
3484 void radv_CmdSetScissor(
3485 VkCommandBuffer commandBuffer,
3486 uint32_t firstScissor,
3487 uint32_t scissorCount,
3488 const VkRect2D* pScissors)
3489 {
3490 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3491 struct radv_cmd_state *state = &cmd_buffer->state;
3492 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3493
3494 assert(firstScissor < MAX_SCISSORS);
3495 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3496
3497 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3498 scissorCount * sizeof(*pScissors))) {
3499 return;
3500 }
3501
3502 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3503 scissorCount * sizeof(*pScissors));
3504
3505 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3506 }
3507
3508 void radv_CmdSetLineWidth(
3509 VkCommandBuffer commandBuffer,
3510 float lineWidth)
3511 {
3512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3513
3514 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3515 return;
3516
3517 cmd_buffer->state.dynamic.line_width = lineWidth;
3518 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3519 }
3520
3521 void radv_CmdSetDepthBias(
3522 VkCommandBuffer commandBuffer,
3523 float depthBiasConstantFactor,
3524 float depthBiasClamp,
3525 float depthBiasSlopeFactor)
3526 {
3527 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3528 struct radv_cmd_state *state = &cmd_buffer->state;
3529
3530 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3531 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3532 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3533 return;
3534 }
3535
3536 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3537 state->dynamic.depth_bias.clamp = depthBiasClamp;
3538 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3539
3540 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3541 }
3542
3543 void radv_CmdSetBlendConstants(
3544 VkCommandBuffer commandBuffer,
3545 const float blendConstants[4])
3546 {
3547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3548 struct radv_cmd_state *state = &cmd_buffer->state;
3549
3550 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3551 return;
3552
3553 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3554
3555 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3556 }
3557
3558 void radv_CmdSetDepthBounds(
3559 VkCommandBuffer commandBuffer,
3560 float minDepthBounds,
3561 float maxDepthBounds)
3562 {
3563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3564 struct radv_cmd_state *state = &cmd_buffer->state;
3565
3566 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3567 state->dynamic.depth_bounds.max == maxDepthBounds) {
3568 return;
3569 }
3570
3571 state->dynamic.depth_bounds.min = minDepthBounds;
3572 state->dynamic.depth_bounds.max = maxDepthBounds;
3573
3574 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3575 }
3576
3577 void radv_CmdSetStencilCompareMask(
3578 VkCommandBuffer commandBuffer,
3579 VkStencilFaceFlags faceMask,
3580 uint32_t compareMask)
3581 {
3582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3583 struct radv_cmd_state *state = &cmd_buffer->state;
3584 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3585 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3586
3587 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3588 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3589 return;
3590 }
3591
3592 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3593 state->dynamic.stencil_compare_mask.front = compareMask;
3594 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3595 state->dynamic.stencil_compare_mask.back = compareMask;
3596
3597 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3598 }
3599
3600 void radv_CmdSetStencilWriteMask(
3601 VkCommandBuffer commandBuffer,
3602 VkStencilFaceFlags faceMask,
3603 uint32_t writeMask)
3604 {
3605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3606 struct radv_cmd_state *state = &cmd_buffer->state;
3607 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3608 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3609
3610 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3611 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3612 return;
3613 }
3614
3615 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3616 state->dynamic.stencil_write_mask.front = writeMask;
3617 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3618 state->dynamic.stencil_write_mask.back = writeMask;
3619
3620 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3621 }
3622
3623 void radv_CmdSetStencilReference(
3624 VkCommandBuffer commandBuffer,
3625 VkStencilFaceFlags faceMask,
3626 uint32_t reference)
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 struct radv_cmd_state *state = &cmd_buffer->state;
3630 bool front_same = state->dynamic.stencil_reference.front == reference;
3631 bool back_same = state->dynamic.stencil_reference.back == reference;
3632
3633 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3634 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3635 return;
3636 }
3637
3638 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3639 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3640 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3641 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3642
3643 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3644 }
3645
3646 void radv_CmdSetDiscardRectangleEXT(
3647 VkCommandBuffer commandBuffer,
3648 uint32_t firstDiscardRectangle,
3649 uint32_t discardRectangleCount,
3650 const VkRect2D* pDiscardRectangles)
3651 {
3652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3653 struct radv_cmd_state *state = &cmd_buffer->state;
3654 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3655
3656 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3657 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3658
3659 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3660 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3661 return;
3662 }
3663
3664 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3665 pDiscardRectangles, discardRectangleCount);
3666
3667 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3668 }
3669
3670 void radv_CmdSetSampleLocationsEXT(
3671 VkCommandBuffer commandBuffer,
3672 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3673 {
3674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3675 struct radv_cmd_state *state = &cmd_buffer->state;
3676
3677 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3678
3679 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3680 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3681 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3682 typed_memcpy(&state->dynamic.sample_location.locations[0],
3683 pSampleLocationsInfo->pSampleLocations,
3684 pSampleLocationsInfo->sampleLocationsCount);
3685
3686 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3687 }
3688
3689 void radv_CmdExecuteCommands(
3690 VkCommandBuffer commandBuffer,
3691 uint32_t commandBufferCount,
3692 const VkCommandBuffer* pCmdBuffers)
3693 {
3694 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3695
3696 assert(commandBufferCount > 0);
3697
3698 /* Emit pending flushes on primary prior to executing secondary */
3699 si_emit_cache_flush(primary);
3700
3701 for (uint32_t i = 0; i < commandBufferCount; i++) {
3702 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3703
3704 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3705 secondary->scratch_size_needed);
3706 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3707 secondary->compute_scratch_size_needed);
3708
3709 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3710 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3711 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3712 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3713 if (secondary->tess_rings_needed)
3714 primary->tess_rings_needed = true;
3715 if (secondary->sample_positions_needed)
3716 primary->sample_positions_needed = true;
3717
3718 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3719
3720
3721 /* When the secondary command buffer is compute only we don't
3722 * need to re-emit the current graphics pipeline.
3723 */
3724 if (secondary->state.emitted_pipeline) {
3725 primary->state.emitted_pipeline =
3726 secondary->state.emitted_pipeline;
3727 }
3728
3729 /* When the secondary command buffer is graphics only we don't
3730 * need to re-emit the current compute pipeline.
3731 */
3732 if (secondary->state.emitted_compute_pipeline) {
3733 primary->state.emitted_compute_pipeline =
3734 secondary->state.emitted_compute_pipeline;
3735 }
3736
3737 /* Only re-emit the draw packets when needed. */
3738 if (secondary->state.last_primitive_reset_en != -1) {
3739 primary->state.last_primitive_reset_en =
3740 secondary->state.last_primitive_reset_en;
3741 }
3742
3743 if (secondary->state.last_primitive_reset_index) {
3744 primary->state.last_primitive_reset_index =
3745 secondary->state.last_primitive_reset_index;
3746 }
3747
3748 if (secondary->state.last_ia_multi_vgt_param) {
3749 primary->state.last_ia_multi_vgt_param =
3750 secondary->state.last_ia_multi_vgt_param;
3751 }
3752
3753 primary->state.last_first_instance = secondary->state.last_first_instance;
3754 primary->state.last_num_instances = secondary->state.last_num_instances;
3755 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3756
3757 if (secondary->state.last_index_type != -1) {
3758 primary->state.last_index_type =
3759 secondary->state.last_index_type;
3760 }
3761 }
3762
3763 /* After executing commands from secondary buffers we have to dirty
3764 * some states.
3765 */
3766 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3767 RADV_CMD_DIRTY_INDEX_BUFFER |
3768 RADV_CMD_DIRTY_DYNAMIC_ALL;
3769 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3770 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3771 }
3772
3773 VkResult radv_CreateCommandPool(
3774 VkDevice _device,
3775 const VkCommandPoolCreateInfo* pCreateInfo,
3776 const VkAllocationCallbacks* pAllocator,
3777 VkCommandPool* pCmdPool)
3778 {
3779 RADV_FROM_HANDLE(radv_device, device, _device);
3780 struct radv_cmd_pool *pool;
3781
3782 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3783 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3784 if (pool == NULL)
3785 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3786
3787 if (pAllocator)
3788 pool->alloc = *pAllocator;
3789 else
3790 pool->alloc = device->alloc;
3791
3792 list_inithead(&pool->cmd_buffers);
3793 list_inithead(&pool->free_cmd_buffers);
3794
3795 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3796
3797 *pCmdPool = radv_cmd_pool_to_handle(pool);
3798
3799 return VK_SUCCESS;
3800
3801 }
3802
3803 void radv_DestroyCommandPool(
3804 VkDevice _device,
3805 VkCommandPool commandPool,
3806 const VkAllocationCallbacks* pAllocator)
3807 {
3808 RADV_FROM_HANDLE(radv_device, device, _device);
3809 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3810
3811 if (!pool)
3812 return;
3813
3814 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3815 &pool->cmd_buffers, pool_link) {
3816 radv_cmd_buffer_destroy(cmd_buffer);
3817 }
3818
3819 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3820 &pool->free_cmd_buffers, pool_link) {
3821 radv_cmd_buffer_destroy(cmd_buffer);
3822 }
3823
3824 vk_free2(&device->alloc, pAllocator, pool);
3825 }
3826
3827 VkResult radv_ResetCommandPool(
3828 VkDevice device,
3829 VkCommandPool commandPool,
3830 VkCommandPoolResetFlags flags)
3831 {
3832 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3833 VkResult result;
3834
3835 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3836 &pool->cmd_buffers, pool_link) {
3837 result = radv_reset_cmd_buffer(cmd_buffer);
3838 if (result != VK_SUCCESS)
3839 return result;
3840 }
3841
3842 return VK_SUCCESS;
3843 }
3844
3845 void radv_TrimCommandPool(
3846 VkDevice device,
3847 VkCommandPool commandPool,
3848 VkCommandPoolTrimFlags flags)
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3851
3852 if (!pool)
3853 return;
3854
3855 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3856 &pool->free_cmd_buffers, pool_link) {
3857 radv_cmd_buffer_destroy(cmd_buffer);
3858 }
3859 }
3860
3861 static void
3862 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3863 uint32_t subpass_id)
3864 {
3865 struct radv_cmd_state *state = &cmd_buffer->state;
3866 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3867
3868 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3869 cmd_buffer->cs, 4096);
3870
3871 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3872
3873 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3874
3875 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3876 const uint32_t a = subpass->attachments[i].attachment;
3877 if (a == VK_ATTACHMENT_UNUSED)
3878 continue;
3879
3880 radv_handle_subpass_image_transition(cmd_buffer,
3881 subpass->attachments[i],
3882 true);
3883 }
3884
3885 radv_cmd_buffer_clear_subpass(cmd_buffer);
3886
3887 assert(cmd_buffer->cs->cdw <= cdw_max);
3888 }
3889
3890 static void
3891 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3892 {
3893 struct radv_cmd_state *state = &cmd_buffer->state;
3894 const struct radv_subpass *subpass = state->subpass;
3895 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3896
3897 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3898
3899 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3900 const uint32_t a = subpass->attachments[i].attachment;
3901 if (a == VK_ATTACHMENT_UNUSED)
3902 continue;
3903
3904 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3905 continue;
3906
3907 VkImageLayout layout = state->pass->attachments[a].final_layout;
3908 struct radv_subpass_attachment att = { a, layout };
3909 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3910 }
3911 }
3912
3913 void radv_CmdBeginRenderPass(
3914 VkCommandBuffer commandBuffer,
3915 const VkRenderPassBeginInfo* pRenderPassBegin,
3916 VkSubpassContents contents)
3917 {
3918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3919 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3920 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3921 VkResult result;
3922
3923 cmd_buffer->state.framebuffer = framebuffer;
3924 cmd_buffer->state.pass = pass;
3925 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3926
3927 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3928 if (result != VK_SUCCESS)
3929 return;
3930
3931 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
3932 if (result != VK_SUCCESS)
3933 return;
3934
3935 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3936 }
3937
3938 void radv_CmdBeginRenderPass2KHR(
3939 VkCommandBuffer commandBuffer,
3940 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3941 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3942 {
3943 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3944 pSubpassBeginInfo->contents);
3945 }
3946
3947 void radv_CmdNextSubpass(
3948 VkCommandBuffer commandBuffer,
3949 VkSubpassContents contents)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3952
3953 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3954 radv_cmd_buffer_end_subpass(cmd_buffer);
3955 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3956 }
3957
3958 void radv_CmdNextSubpass2KHR(
3959 VkCommandBuffer commandBuffer,
3960 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3961 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3962 {
3963 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3964 }
3965
3966 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3967 {
3968 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3969 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3970 if (!radv_get_shader(pipeline, stage))
3971 continue;
3972
3973 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3974 if (loc->sgpr_idx == -1)
3975 continue;
3976 uint32_t base_reg = pipeline->user_data_0[stage];
3977 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3978
3979 }
3980 if (pipeline->gs_copy_shader) {
3981 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3982 if (loc->sgpr_idx != -1) {
3983 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3984 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3985 }
3986 }
3987 }
3988
3989 static void
3990 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3991 uint32_t vertex_count,
3992 bool use_opaque)
3993 {
3994 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3995 radeon_emit(cmd_buffer->cs, vertex_count);
3996 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3997 S_0287F0_USE_OPAQUE(use_opaque));
3998 }
3999
4000 static void
4001 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4002 uint64_t index_va,
4003 uint32_t index_count)
4004 {
4005 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4006 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4007 radeon_emit(cmd_buffer->cs, index_va);
4008 radeon_emit(cmd_buffer->cs, index_va >> 32);
4009 radeon_emit(cmd_buffer->cs, index_count);
4010 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4011 }
4012
4013 static void
4014 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4015 bool indexed,
4016 uint32_t draw_count,
4017 uint64_t count_va,
4018 uint32_t stride)
4019 {
4020 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4021 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4022 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4023 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4024 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4025 bool predicating = cmd_buffer->state.predicating;
4026 assert(base_reg);
4027
4028 /* just reset draw state for vertex data */
4029 cmd_buffer->state.last_first_instance = -1;
4030 cmd_buffer->state.last_num_instances = -1;
4031 cmd_buffer->state.last_vertex_offset = -1;
4032
4033 if (draw_count == 1 && !count_va && !draw_id_enable) {
4034 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4035 PKT3_DRAW_INDIRECT, 3, predicating));
4036 radeon_emit(cs, 0);
4037 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4038 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4039 radeon_emit(cs, di_src_sel);
4040 } else {
4041 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4042 PKT3_DRAW_INDIRECT_MULTI,
4043 8, predicating));
4044 radeon_emit(cs, 0);
4045 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4046 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4047 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4048 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4049 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4050 radeon_emit(cs, draw_count); /* count */
4051 radeon_emit(cs, count_va); /* count_addr */
4052 radeon_emit(cs, count_va >> 32);
4053 radeon_emit(cs, stride); /* stride */
4054 radeon_emit(cs, di_src_sel);
4055 }
4056 }
4057
4058 static void
4059 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4060 const struct radv_draw_info *info)
4061 {
4062 struct radv_cmd_state *state = &cmd_buffer->state;
4063 struct radeon_winsys *ws = cmd_buffer->device->ws;
4064 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4065
4066 if (info->indirect) {
4067 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4068 uint64_t count_va = 0;
4069
4070 va += info->indirect->offset + info->indirect_offset;
4071
4072 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4073
4074 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4075 radeon_emit(cs, 1);
4076 radeon_emit(cs, va);
4077 radeon_emit(cs, va >> 32);
4078
4079 if (info->count_buffer) {
4080 count_va = radv_buffer_get_va(info->count_buffer->bo);
4081 count_va += info->count_buffer->offset +
4082 info->count_buffer_offset;
4083
4084 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4085 }
4086
4087 if (!state->subpass->view_mask) {
4088 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4089 info->indexed,
4090 info->count,
4091 count_va,
4092 info->stride);
4093 } else {
4094 unsigned i;
4095 for_each_bit(i, state->subpass->view_mask) {
4096 radv_emit_view_index(cmd_buffer, i);
4097
4098 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4099 info->indexed,
4100 info->count,
4101 count_va,
4102 info->stride);
4103 }
4104 }
4105 } else {
4106 assert(state->pipeline->graphics.vtx_base_sgpr);
4107
4108 if (info->vertex_offset != state->last_vertex_offset ||
4109 info->first_instance != state->last_first_instance) {
4110 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4111 state->pipeline->graphics.vtx_emit_num);
4112
4113 radeon_emit(cs, info->vertex_offset);
4114 radeon_emit(cs, info->first_instance);
4115 if (state->pipeline->graphics.vtx_emit_num == 3)
4116 radeon_emit(cs, 0);
4117 state->last_first_instance = info->first_instance;
4118 state->last_vertex_offset = info->vertex_offset;
4119 }
4120
4121 if (state->last_num_instances != info->instance_count) {
4122 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4123 radeon_emit(cs, info->instance_count);
4124 state->last_num_instances = info->instance_count;
4125 }
4126
4127 if (info->indexed) {
4128 int index_size = state->index_type ? 4 : 2;
4129 uint64_t index_va;
4130
4131 index_va = state->index_va;
4132 index_va += info->first_index * index_size;
4133
4134 if (!state->subpass->view_mask) {
4135 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4136 index_va,
4137 info->count);
4138 } else {
4139 unsigned i;
4140 for_each_bit(i, state->subpass->view_mask) {
4141 radv_emit_view_index(cmd_buffer, i);
4142
4143 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4144 index_va,
4145 info->count);
4146 }
4147 }
4148 } else {
4149 if (!state->subpass->view_mask) {
4150 radv_cs_emit_draw_packet(cmd_buffer,
4151 info->count,
4152 !!info->strmout_buffer);
4153 } else {
4154 unsigned i;
4155 for_each_bit(i, state->subpass->view_mask) {
4156 radv_emit_view_index(cmd_buffer, i);
4157
4158 radv_cs_emit_draw_packet(cmd_buffer,
4159 info->count,
4160 !!info->strmout_buffer);
4161 }
4162 }
4163 }
4164 }
4165 }
4166
4167 /*
4168 * Vega and raven have a bug which triggers if there are multiple context
4169 * register contexts active at the same time with different scissor values.
4170 *
4171 * There are two possible workarounds:
4172 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4173 * there is only ever 1 active set of scissor values at the same time.
4174 *
4175 * 2) Whenever the hardware switches contexts we have to set the scissor
4176 * registers again even if it is a noop. That way the new context gets
4177 * the correct scissor values.
4178 *
4179 * This implements option 2. radv_need_late_scissor_emission needs to
4180 * return true on affected HW if radv_emit_all_graphics_states sets
4181 * any context registers.
4182 */
4183 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4184 const struct radv_draw_info *info)
4185 {
4186 struct radv_cmd_state *state = &cmd_buffer->state;
4187
4188 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4189 return false;
4190
4191 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4192 return true;
4193
4194 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4195
4196 /* Index, vertex and streamout buffers don't change context regs, and
4197 * pipeline is already handled.
4198 */
4199 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4200 RADV_CMD_DIRTY_VERTEX_BUFFER |
4201 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4202 RADV_CMD_DIRTY_PIPELINE);
4203
4204 if (cmd_buffer->state.dirty & used_states)
4205 return true;
4206
4207 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4208 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4209 return true;
4210
4211 return false;
4212 }
4213
4214 static void
4215 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4216 const struct radv_draw_info *info)
4217 {
4218 bool late_scissor_emission;
4219
4220 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4221 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4222 radv_emit_rbplus_state(cmd_buffer);
4223
4224 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4225 radv_emit_graphics_pipeline(cmd_buffer);
4226
4227 /* This should be before the cmd_buffer->state.dirty is cleared
4228 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4229 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4230 late_scissor_emission =
4231 radv_need_late_scissor_emission(cmd_buffer, info);
4232
4233 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4234 radv_emit_framebuffer_state(cmd_buffer);
4235
4236 if (info->indexed) {
4237 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4238 radv_emit_index_buffer(cmd_buffer);
4239 } else {
4240 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4241 * so the state must be re-emitted before the next indexed
4242 * draw.
4243 */
4244 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4245 cmd_buffer->state.last_index_type = -1;
4246 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4247 }
4248 }
4249
4250 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4251
4252 radv_emit_draw_registers(cmd_buffer, info);
4253
4254 if (late_scissor_emission)
4255 radv_emit_scissor(cmd_buffer);
4256 }
4257
4258 static void
4259 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4260 const struct radv_draw_info *info)
4261 {
4262 struct radeon_info *rad_info =
4263 &cmd_buffer->device->physical_device->rad_info;
4264 bool has_prefetch =
4265 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4266 bool pipeline_is_dirty =
4267 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4268 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4269
4270 MAYBE_UNUSED unsigned cdw_max =
4271 radeon_check_space(cmd_buffer->device->ws,
4272 cmd_buffer->cs, 4096);
4273
4274 if (likely(!info->indirect)) {
4275 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4276 * no workaround for indirect draws, but we can at least skip
4277 * direct draws.
4278 */
4279 if (unlikely(!info->instance_count))
4280 return;
4281
4282 /* Handle count == 0. */
4283 if (unlikely(!info->count && !info->strmout_buffer))
4284 return;
4285 }
4286
4287 /* Use optimal packet order based on whether we need to sync the
4288 * pipeline.
4289 */
4290 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4291 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4292 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4293 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4294 /* If we have to wait for idle, set all states first, so that
4295 * all SET packets are processed in parallel with previous draw
4296 * calls. Then upload descriptors, set shader pointers, and
4297 * draw, and prefetch at the end. This ensures that the time
4298 * the CUs are idle is very short. (there are only SET_SH
4299 * packets between the wait and the draw)
4300 */
4301 radv_emit_all_graphics_states(cmd_buffer, info);
4302 si_emit_cache_flush(cmd_buffer);
4303 /* <-- CUs are idle here --> */
4304
4305 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4306
4307 radv_emit_draw_packets(cmd_buffer, info);
4308 /* <-- CUs are busy here --> */
4309
4310 /* Start prefetches after the draw has been started. Both will
4311 * run in parallel, but starting the draw first is more
4312 * important.
4313 */
4314 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4315 radv_emit_prefetch_L2(cmd_buffer,
4316 cmd_buffer->state.pipeline, false);
4317 }
4318 } else {
4319 /* If we don't wait for idle, start prefetches first, then set
4320 * states, and draw at the end.
4321 */
4322 si_emit_cache_flush(cmd_buffer);
4323
4324 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4325 /* Only prefetch the vertex shader and VBO descriptors
4326 * in order to start the draw as soon as possible.
4327 */
4328 radv_emit_prefetch_L2(cmd_buffer,
4329 cmd_buffer->state.pipeline, true);
4330 }
4331
4332 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4333
4334 radv_emit_all_graphics_states(cmd_buffer, info);
4335 radv_emit_draw_packets(cmd_buffer, info);
4336
4337 /* Prefetch the remaining shaders after the draw has been
4338 * started.
4339 */
4340 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4341 radv_emit_prefetch_L2(cmd_buffer,
4342 cmd_buffer->state.pipeline, false);
4343 }
4344 }
4345
4346 /* Workaround for a VGT hang when streamout is enabled.
4347 * It must be done after drawing.
4348 */
4349 if (cmd_buffer->state.streamout.streamout_enabled &&
4350 (rad_info->family == CHIP_HAWAII ||
4351 rad_info->family == CHIP_TONGA ||
4352 rad_info->family == CHIP_FIJI)) {
4353 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4354 }
4355
4356 assert(cmd_buffer->cs->cdw <= cdw_max);
4357 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4358 }
4359
4360 void radv_CmdDraw(
4361 VkCommandBuffer commandBuffer,
4362 uint32_t vertexCount,
4363 uint32_t instanceCount,
4364 uint32_t firstVertex,
4365 uint32_t firstInstance)
4366 {
4367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4368 struct radv_draw_info info = {};
4369
4370 info.count = vertexCount;
4371 info.instance_count = instanceCount;
4372 info.first_instance = firstInstance;
4373 info.vertex_offset = firstVertex;
4374
4375 radv_draw(cmd_buffer, &info);
4376 }
4377
4378 void radv_CmdDrawIndexed(
4379 VkCommandBuffer commandBuffer,
4380 uint32_t indexCount,
4381 uint32_t instanceCount,
4382 uint32_t firstIndex,
4383 int32_t vertexOffset,
4384 uint32_t firstInstance)
4385 {
4386 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4387 struct radv_draw_info info = {};
4388
4389 info.indexed = true;
4390 info.count = indexCount;
4391 info.instance_count = instanceCount;
4392 info.first_index = firstIndex;
4393 info.vertex_offset = vertexOffset;
4394 info.first_instance = firstInstance;
4395
4396 radv_draw(cmd_buffer, &info);
4397 }
4398
4399 void radv_CmdDrawIndirect(
4400 VkCommandBuffer commandBuffer,
4401 VkBuffer _buffer,
4402 VkDeviceSize offset,
4403 uint32_t drawCount,
4404 uint32_t stride)
4405 {
4406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4407 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4408 struct radv_draw_info info = {};
4409
4410 info.count = drawCount;
4411 info.indirect = buffer;
4412 info.indirect_offset = offset;
4413 info.stride = stride;
4414
4415 radv_draw(cmd_buffer, &info);
4416 }
4417
4418 void radv_CmdDrawIndexedIndirect(
4419 VkCommandBuffer commandBuffer,
4420 VkBuffer _buffer,
4421 VkDeviceSize offset,
4422 uint32_t drawCount,
4423 uint32_t stride)
4424 {
4425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4426 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4427 struct radv_draw_info info = {};
4428
4429 info.indexed = true;
4430 info.count = drawCount;
4431 info.indirect = buffer;
4432 info.indirect_offset = offset;
4433 info.stride = stride;
4434
4435 radv_draw(cmd_buffer, &info);
4436 }
4437
4438 void radv_CmdDrawIndirectCountKHR(
4439 VkCommandBuffer commandBuffer,
4440 VkBuffer _buffer,
4441 VkDeviceSize offset,
4442 VkBuffer _countBuffer,
4443 VkDeviceSize countBufferOffset,
4444 uint32_t maxDrawCount,
4445 uint32_t stride)
4446 {
4447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4448 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4449 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4450 struct radv_draw_info info = {};
4451
4452 info.count = maxDrawCount;
4453 info.indirect = buffer;
4454 info.indirect_offset = offset;
4455 info.count_buffer = count_buffer;
4456 info.count_buffer_offset = countBufferOffset;
4457 info.stride = stride;
4458
4459 radv_draw(cmd_buffer, &info);
4460 }
4461
4462 void radv_CmdDrawIndexedIndirectCountKHR(
4463 VkCommandBuffer commandBuffer,
4464 VkBuffer _buffer,
4465 VkDeviceSize offset,
4466 VkBuffer _countBuffer,
4467 VkDeviceSize countBufferOffset,
4468 uint32_t maxDrawCount,
4469 uint32_t stride)
4470 {
4471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4472 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4473 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4474 struct radv_draw_info info = {};
4475
4476 info.indexed = true;
4477 info.count = maxDrawCount;
4478 info.indirect = buffer;
4479 info.indirect_offset = offset;
4480 info.count_buffer = count_buffer;
4481 info.count_buffer_offset = countBufferOffset;
4482 info.stride = stride;
4483
4484 radv_draw(cmd_buffer, &info);
4485 }
4486
4487 struct radv_dispatch_info {
4488 /**
4489 * Determine the layout of the grid (in block units) to be used.
4490 */
4491 uint32_t blocks[3];
4492
4493 /**
4494 * A starting offset for the grid. If unaligned is set, the offset
4495 * must still be aligned.
4496 */
4497 uint32_t offsets[3];
4498 /**
4499 * Whether it's an unaligned compute dispatch.
4500 */
4501 bool unaligned;
4502
4503 /**
4504 * Indirect compute parameters resource.
4505 */
4506 struct radv_buffer *indirect;
4507 uint64_t indirect_offset;
4508 };
4509
4510 static void
4511 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4512 const struct radv_dispatch_info *info)
4513 {
4514 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4515 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4516 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4517 struct radeon_winsys *ws = cmd_buffer->device->ws;
4518 bool predicating = cmd_buffer->state.predicating;
4519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4520 struct radv_userdata_info *loc;
4521
4522 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4523 AC_UD_CS_GRID_SIZE);
4524
4525 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4526
4527 if (info->indirect) {
4528 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4529
4530 va += info->indirect->offset + info->indirect_offset;
4531
4532 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4533
4534 if (loc->sgpr_idx != -1) {
4535 for (unsigned i = 0; i < 3; ++i) {
4536 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4537 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4538 COPY_DATA_DST_SEL(COPY_DATA_REG));
4539 radeon_emit(cs, (va + 4 * i));
4540 radeon_emit(cs, (va + 4 * i) >> 32);
4541 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4542 + loc->sgpr_idx * 4) >> 2) + i);
4543 radeon_emit(cs, 0);
4544 }
4545 }
4546
4547 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4548 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4549 PKT3_SHADER_TYPE_S(1));
4550 radeon_emit(cs, va);
4551 radeon_emit(cs, va >> 32);
4552 radeon_emit(cs, dispatch_initiator);
4553 } else {
4554 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4555 PKT3_SHADER_TYPE_S(1));
4556 radeon_emit(cs, 1);
4557 radeon_emit(cs, va);
4558 radeon_emit(cs, va >> 32);
4559
4560 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4561 PKT3_SHADER_TYPE_S(1));
4562 radeon_emit(cs, 0);
4563 radeon_emit(cs, dispatch_initiator);
4564 }
4565 } else {
4566 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4567 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4568
4569 if (info->unaligned) {
4570 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4571 unsigned remainder[3];
4572
4573 /* If aligned, these should be an entire block size,
4574 * not 0.
4575 */
4576 remainder[0] = blocks[0] + cs_block_size[0] -
4577 align_u32_npot(blocks[0], cs_block_size[0]);
4578 remainder[1] = blocks[1] + cs_block_size[1] -
4579 align_u32_npot(blocks[1], cs_block_size[1]);
4580 remainder[2] = blocks[2] + cs_block_size[2] -
4581 align_u32_npot(blocks[2], cs_block_size[2]);
4582
4583 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4584 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4585 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4586
4587 for(unsigned i = 0; i < 3; ++i) {
4588 assert(offsets[i] % cs_block_size[i] == 0);
4589 offsets[i] /= cs_block_size[i];
4590 }
4591
4592 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4593 radeon_emit(cs,
4594 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4595 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4596 radeon_emit(cs,
4597 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4598 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4599 radeon_emit(cs,
4600 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4601 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4602
4603 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4604 }
4605
4606 if (loc->sgpr_idx != -1) {
4607 assert(loc->num_sgprs == 3);
4608
4609 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4610 loc->sgpr_idx * 4, 3);
4611 radeon_emit(cs, blocks[0]);
4612 radeon_emit(cs, blocks[1]);
4613 radeon_emit(cs, blocks[2]);
4614 }
4615
4616 if (offsets[0] || offsets[1] || offsets[2]) {
4617 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4618 radeon_emit(cs, offsets[0]);
4619 radeon_emit(cs, offsets[1]);
4620 radeon_emit(cs, offsets[2]);
4621
4622 /* The blocks in the packet are not counts but end values. */
4623 for (unsigned i = 0; i < 3; ++i)
4624 blocks[i] += offsets[i];
4625 } else {
4626 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4627 }
4628
4629 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4630 PKT3_SHADER_TYPE_S(1));
4631 radeon_emit(cs, blocks[0]);
4632 radeon_emit(cs, blocks[1]);
4633 radeon_emit(cs, blocks[2]);
4634 radeon_emit(cs, dispatch_initiator);
4635 }
4636
4637 assert(cmd_buffer->cs->cdw <= cdw_max);
4638 }
4639
4640 static void
4641 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4642 {
4643 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4644 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4645 }
4646
4647 static void
4648 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4649 const struct radv_dispatch_info *info)
4650 {
4651 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4652 bool has_prefetch =
4653 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4654 bool pipeline_is_dirty = pipeline &&
4655 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4656
4657 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4658 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4659 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4660 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4661 /* If we have to wait for idle, set all states first, so that
4662 * all SET packets are processed in parallel with previous draw
4663 * calls. Then upload descriptors, set shader pointers, and
4664 * dispatch, and prefetch at the end. This ensures that the
4665 * time the CUs are idle is very short. (there are only SET_SH
4666 * packets between the wait and the draw)
4667 */
4668 radv_emit_compute_pipeline(cmd_buffer);
4669 si_emit_cache_flush(cmd_buffer);
4670 /* <-- CUs are idle here --> */
4671
4672 radv_upload_compute_shader_descriptors(cmd_buffer);
4673
4674 radv_emit_dispatch_packets(cmd_buffer, info);
4675 /* <-- CUs are busy here --> */
4676
4677 /* Start prefetches after the dispatch has been started. Both
4678 * will run in parallel, but starting the dispatch first is
4679 * more important.
4680 */
4681 if (has_prefetch && pipeline_is_dirty) {
4682 radv_emit_shader_prefetch(cmd_buffer,
4683 pipeline->shaders[MESA_SHADER_COMPUTE]);
4684 }
4685 } else {
4686 /* If we don't wait for idle, start prefetches first, then set
4687 * states, and dispatch at the end.
4688 */
4689 si_emit_cache_flush(cmd_buffer);
4690
4691 if (has_prefetch && pipeline_is_dirty) {
4692 radv_emit_shader_prefetch(cmd_buffer,
4693 pipeline->shaders[MESA_SHADER_COMPUTE]);
4694 }
4695
4696 radv_upload_compute_shader_descriptors(cmd_buffer);
4697
4698 radv_emit_compute_pipeline(cmd_buffer);
4699 radv_emit_dispatch_packets(cmd_buffer, info);
4700 }
4701
4702 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4703 }
4704
4705 void radv_CmdDispatchBase(
4706 VkCommandBuffer commandBuffer,
4707 uint32_t base_x,
4708 uint32_t base_y,
4709 uint32_t base_z,
4710 uint32_t x,
4711 uint32_t y,
4712 uint32_t z)
4713 {
4714 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4715 struct radv_dispatch_info info = {};
4716
4717 info.blocks[0] = x;
4718 info.blocks[1] = y;
4719 info.blocks[2] = z;
4720
4721 info.offsets[0] = base_x;
4722 info.offsets[1] = base_y;
4723 info.offsets[2] = base_z;
4724 radv_dispatch(cmd_buffer, &info);
4725 }
4726
4727 void radv_CmdDispatch(
4728 VkCommandBuffer commandBuffer,
4729 uint32_t x,
4730 uint32_t y,
4731 uint32_t z)
4732 {
4733 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4734 }
4735
4736 void radv_CmdDispatchIndirect(
4737 VkCommandBuffer commandBuffer,
4738 VkBuffer _buffer,
4739 VkDeviceSize offset)
4740 {
4741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4742 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4743 struct radv_dispatch_info info = {};
4744
4745 info.indirect = buffer;
4746 info.indirect_offset = offset;
4747
4748 radv_dispatch(cmd_buffer, &info);
4749 }
4750
4751 void radv_unaligned_dispatch(
4752 struct radv_cmd_buffer *cmd_buffer,
4753 uint32_t x,
4754 uint32_t y,
4755 uint32_t z)
4756 {
4757 struct radv_dispatch_info info = {};
4758
4759 info.blocks[0] = x;
4760 info.blocks[1] = y;
4761 info.blocks[2] = z;
4762 info.unaligned = 1;
4763
4764 radv_dispatch(cmd_buffer, &info);
4765 }
4766
4767 void radv_CmdEndRenderPass(
4768 VkCommandBuffer commandBuffer)
4769 {
4770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4771
4772 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4773
4774 radv_cmd_buffer_end_subpass(cmd_buffer);
4775
4776 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4777 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4778
4779 cmd_buffer->state.pass = NULL;
4780 cmd_buffer->state.subpass = NULL;
4781 cmd_buffer->state.attachments = NULL;
4782 cmd_buffer->state.framebuffer = NULL;
4783 cmd_buffer->state.subpass_sample_locs = NULL;
4784 }
4785
4786 void radv_CmdEndRenderPass2KHR(
4787 VkCommandBuffer commandBuffer,
4788 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4789 {
4790 radv_CmdEndRenderPass(commandBuffer);
4791 }
4792
4793 /*
4794 * For HTILE we have the following interesting clear words:
4795 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4796 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4797 * 0xfffffff0: Clear depth to 1.0
4798 * 0x00000000: Clear depth to 0.0
4799 */
4800 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4801 struct radv_image *image,
4802 const VkImageSubresourceRange *range,
4803 uint32_t clear_word)
4804 {
4805 assert(range->baseMipLevel == 0);
4806 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4807 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4808 struct radv_cmd_state *state = &cmd_buffer->state;
4809 VkClearDepthStencilValue value = {};
4810
4811 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4812 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4813
4814 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4815
4816 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4817
4818 if (vk_format_is_stencil(image->vk_format))
4819 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4820
4821 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4822
4823 if (radv_image_is_tc_compat_htile(image)) {
4824 /* Initialize the TC-compat metada value to 0 because by
4825 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4826 * need have to conditionally update its value when performing
4827 * a fast depth clear.
4828 */
4829 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4830 }
4831 }
4832
4833 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4834 struct radv_image *image,
4835 VkImageLayout src_layout,
4836 VkImageLayout dst_layout,
4837 unsigned src_queue_mask,
4838 unsigned dst_queue_mask,
4839 const VkImageSubresourceRange *range,
4840 struct radv_sample_locations_state *sample_locs)
4841 {
4842 if (!radv_image_has_htile(image))
4843 return;
4844
4845 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4846 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4847
4848 if (radv_layout_is_htile_compressed(image, dst_layout,
4849 dst_queue_mask)) {
4850 clear_value = 0;
4851 }
4852
4853 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4854 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4855 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4856 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4857 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4858 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4859 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4860 VkImageSubresourceRange local_range = *range;
4861 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4862 local_range.baseMipLevel = 0;
4863 local_range.levelCount = 1;
4864
4865 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4866 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4867
4868 radv_decompress_depth_image_inplace(cmd_buffer, image,
4869 &local_range, sample_locs);
4870
4871 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4872 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4873 }
4874 }
4875
4876 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4877 struct radv_image *image, uint32_t value)
4878 {
4879 struct radv_cmd_state *state = &cmd_buffer->state;
4880
4881 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4882 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4883
4884 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4885
4886 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4887 }
4888
4889 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4890 struct radv_image *image)
4891 {
4892 struct radv_cmd_state *state = &cmd_buffer->state;
4893 static const uint32_t fmask_clear_values[4] = {
4894 0x00000000,
4895 0x02020202,
4896 0xE4E4E4E4,
4897 0x76543210
4898 };
4899 uint32_t log2_samples = util_logbase2(image->info.samples);
4900 uint32_t value = fmask_clear_values[log2_samples];
4901
4902 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4903 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4904
4905 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4906
4907 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4908 }
4909
4910 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4911 struct radv_image *image,
4912 const VkImageSubresourceRange *range, uint32_t value)
4913 {
4914 struct radv_cmd_state *state = &cmd_buffer->state;
4915
4916 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4917 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4918
4919 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
4920
4921 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4922 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4923 }
4924
4925 /**
4926 * Initialize DCC/FMASK/CMASK metadata for a color image.
4927 */
4928 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4929 struct radv_image *image,
4930 VkImageLayout src_layout,
4931 VkImageLayout dst_layout,
4932 unsigned src_queue_mask,
4933 unsigned dst_queue_mask,
4934 const VkImageSubresourceRange *range)
4935 {
4936 if (radv_image_has_cmask(image)) {
4937 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4938
4939 /* TODO: clarify this. */
4940 if (radv_image_has_fmask(image)) {
4941 value = 0xccccccccu;
4942 }
4943
4944 radv_initialise_cmask(cmd_buffer, image, value);
4945 }
4946
4947 if (radv_image_has_fmask(image)) {
4948 radv_initialize_fmask(cmd_buffer, image);
4949 }
4950
4951 if (radv_dcc_enabled(image, range->baseMipLevel)) {
4952 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4953 bool need_decompress_pass = false;
4954
4955 if (radv_layout_dcc_compressed(image, dst_layout,
4956 dst_queue_mask)) {
4957 value = 0x20202020u;
4958 need_decompress_pass = true;
4959 }
4960
4961 radv_initialize_dcc(cmd_buffer, image, range, value);
4962
4963 radv_update_fce_metadata(cmd_buffer, image, range,
4964 need_decompress_pass);
4965 }
4966
4967 if (radv_image_has_cmask(image) ||
4968 radv_dcc_enabled(image, range->baseMipLevel)) {
4969 uint32_t color_values[2] = {};
4970 radv_set_color_clear_metadata(cmd_buffer, image, range,
4971 color_values);
4972 }
4973 }
4974
4975 /**
4976 * Handle color image transitions for DCC/FMASK/CMASK.
4977 */
4978 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4979 struct radv_image *image,
4980 VkImageLayout src_layout,
4981 VkImageLayout dst_layout,
4982 unsigned src_queue_mask,
4983 unsigned dst_queue_mask,
4984 const VkImageSubresourceRange *range)
4985 {
4986 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4987 radv_init_color_image_metadata(cmd_buffer, image,
4988 src_layout, dst_layout,
4989 src_queue_mask, dst_queue_mask,
4990 range);
4991 return;
4992 }
4993
4994 if (radv_dcc_enabled(image, range->baseMipLevel)) {
4995 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4996 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
4997 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4998 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4999 radv_decompress_dcc(cmd_buffer, image, range);
5000 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5001 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5002 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5003 }
5004 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5005 bool fce_eliminate = false, fmask_expand = false;
5006
5007 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5008 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5009 fce_eliminate = true;
5010 }
5011
5012 if (radv_image_has_fmask(image)) {
5013 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5014 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5015 /* A FMASK decompress is required before doing
5016 * a MSAA decompress using FMASK.
5017 */
5018 fmask_expand = true;
5019 }
5020 }
5021
5022 if (fce_eliminate || fmask_expand)
5023 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5024
5025 if (fmask_expand)
5026 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5027 }
5028 }
5029
5030 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5031 struct radv_image *image,
5032 VkImageLayout src_layout,
5033 VkImageLayout dst_layout,
5034 uint32_t src_family,
5035 uint32_t dst_family,
5036 const VkImageSubresourceRange *range,
5037 struct radv_sample_locations_state *sample_locs)
5038 {
5039 if (image->exclusive && src_family != dst_family) {
5040 /* This is an acquire or a release operation and there will be
5041 * a corresponding release/acquire. Do the transition in the
5042 * most flexible queue. */
5043
5044 assert(src_family == cmd_buffer->queue_family_index ||
5045 dst_family == cmd_buffer->queue_family_index);
5046
5047 if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
5048 return;
5049
5050 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5051 return;
5052
5053 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5054 (src_family == RADV_QUEUE_GENERAL ||
5055 dst_family == RADV_QUEUE_GENERAL))
5056 return;
5057 }
5058
5059 if (src_layout == dst_layout)
5060 return;
5061
5062 unsigned src_queue_mask =
5063 radv_image_queue_family_mask(image, src_family,
5064 cmd_buffer->queue_family_index);
5065 unsigned dst_queue_mask =
5066 radv_image_queue_family_mask(image, dst_family,
5067 cmd_buffer->queue_family_index);
5068
5069 if (vk_format_is_depth(image->vk_format)) {
5070 radv_handle_depth_image_transition(cmd_buffer, image,
5071 src_layout, dst_layout,
5072 src_queue_mask, dst_queue_mask,
5073 range, sample_locs);
5074 } else {
5075 radv_handle_color_image_transition(cmd_buffer, image,
5076 src_layout, dst_layout,
5077 src_queue_mask, dst_queue_mask,
5078 range);
5079 }
5080 }
5081
5082 struct radv_barrier_info {
5083 uint32_t eventCount;
5084 const VkEvent *pEvents;
5085 VkPipelineStageFlags srcStageMask;
5086 VkPipelineStageFlags dstStageMask;
5087 };
5088
5089 static void
5090 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5091 uint32_t memoryBarrierCount,
5092 const VkMemoryBarrier *pMemoryBarriers,
5093 uint32_t bufferMemoryBarrierCount,
5094 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5095 uint32_t imageMemoryBarrierCount,
5096 const VkImageMemoryBarrier *pImageMemoryBarriers,
5097 const struct radv_barrier_info *info)
5098 {
5099 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5100 enum radv_cmd_flush_bits src_flush_bits = 0;
5101 enum radv_cmd_flush_bits dst_flush_bits = 0;
5102
5103 for (unsigned i = 0; i < info->eventCount; ++i) {
5104 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5105 uint64_t va = radv_buffer_get_va(event->bo);
5106
5107 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5108
5109 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5110
5111 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5112 assert(cmd_buffer->cs->cdw <= cdw_max);
5113 }
5114
5115 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5116 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5117 NULL);
5118 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5119 NULL);
5120 }
5121
5122 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5123 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5124 NULL);
5125 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5126 NULL);
5127 }
5128
5129 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5130 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5131
5132 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5133 image);
5134 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5135 image);
5136 }
5137
5138 /* The Vulkan spec 1.1.98 says:
5139 *
5140 * "An execution dependency with only
5141 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5142 * will only prevent that stage from executing in subsequently
5143 * submitted commands. As this stage does not perform any actual
5144 * execution, this is not observable - in effect, it does not delay
5145 * processing of subsequent commands. Similarly an execution dependency
5146 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5147 * will effectively not wait for any prior commands to complete."
5148 */
5149 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5150 radv_stage_flush(cmd_buffer, info->srcStageMask);
5151 cmd_buffer->state.flush_bits |= src_flush_bits;
5152
5153 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5154 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5155
5156 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5157 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5158 SAMPLE_LOCATIONS_INFO_EXT);
5159 struct radv_sample_locations_state sample_locations = {};
5160
5161 if (sample_locs_info) {
5162 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5163 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5164 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5165 sample_locations.count = sample_locs_info->sampleLocationsCount;
5166 typed_memcpy(&sample_locations.locations[0],
5167 sample_locs_info->pSampleLocations,
5168 sample_locs_info->sampleLocationsCount);
5169 }
5170
5171 radv_handle_image_transition(cmd_buffer, image,
5172 pImageMemoryBarriers[i].oldLayout,
5173 pImageMemoryBarriers[i].newLayout,
5174 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5175 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5176 &pImageMemoryBarriers[i].subresourceRange,
5177 sample_locs_info ? &sample_locations : NULL);
5178 }
5179
5180 /* Make sure CP DMA is idle because the driver might have performed a
5181 * DMA operation for copying or filling buffers/images.
5182 */
5183 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5184 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5185 si_cp_dma_wait_for_idle(cmd_buffer);
5186
5187 cmd_buffer->state.flush_bits |= dst_flush_bits;
5188 }
5189
5190 void radv_CmdPipelineBarrier(
5191 VkCommandBuffer commandBuffer,
5192 VkPipelineStageFlags srcStageMask,
5193 VkPipelineStageFlags destStageMask,
5194 VkBool32 byRegion,
5195 uint32_t memoryBarrierCount,
5196 const VkMemoryBarrier* pMemoryBarriers,
5197 uint32_t bufferMemoryBarrierCount,
5198 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5199 uint32_t imageMemoryBarrierCount,
5200 const VkImageMemoryBarrier* pImageMemoryBarriers)
5201 {
5202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5203 struct radv_barrier_info info;
5204
5205 info.eventCount = 0;
5206 info.pEvents = NULL;
5207 info.srcStageMask = srcStageMask;
5208 info.dstStageMask = destStageMask;
5209
5210 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5211 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5212 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5213 }
5214
5215
5216 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5217 struct radv_event *event,
5218 VkPipelineStageFlags stageMask,
5219 unsigned value)
5220 {
5221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5222 uint64_t va = radv_buffer_get_va(event->bo);
5223
5224 si_emit_cache_flush(cmd_buffer);
5225
5226 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5227
5228 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5229
5230 /* Flags that only require a top-of-pipe event. */
5231 VkPipelineStageFlags top_of_pipe_flags =
5232 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5233
5234 /* Flags that only require a post-index-fetch event. */
5235 VkPipelineStageFlags post_index_fetch_flags =
5236 top_of_pipe_flags |
5237 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5238 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5239
5240 /* Make sure CP DMA is idle because the driver might have performed a
5241 * DMA operation for copying or filling buffers/images.
5242 */
5243 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5244 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5245 si_cp_dma_wait_for_idle(cmd_buffer);
5246
5247 /* TODO: Emit EOS events for syncing PS/CS stages. */
5248
5249 if (!(stageMask & ~top_of_pipe_flags)) {
5250 /* Just need to sync the PFP engine. */
5251 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5252 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5253 S_370_WR_CONFIRM(1) |
5254 S_370_ENGINE_SEL(V_370_PFP));
5255 radeon_emit(cs, va);
5256 radeon_emit(cs, va >> 32);
5257 radeon_emit(cs, value);
5258 } else if (!(stageMask & ~post_index_fetch_flags)) {
5259 /* Sync ME because PFP reads index and indirect buffers. */
5260 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5261 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5262 S_370_WR_CONFIRM(1) |
5263 S_370_ENGINE_SEL(V_370_ME));
5264 radeon_emit(cs, va);
5265 radeon_emit(cs, va >> 32);
5266 radeon_emit(cs, value);
5267 } else {
5268 /* Otherwise, sync all prior GPU work using an EOP event. */
5269 si_cs_emit_write_event_eop(cs,
5270 cmd_buffer->device->physical_device->rad_info.chip_class,
5271 radv_cmd_buffer_uses_mec(cmd_buffer),
5272 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5273 EOP_DATA_SEL_VALUE_32BIT, va, value,
5274 cmd_buffer->gfx9_eop_bug_va);
5275 }
5276
5277 assert(cmd_buffer->cs->cdw <= cdw_max);
5278 }
5279
5280 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5281 VkEvent _event,
5282 VkPipelineStageFlags stageMask)
5283 {
5284 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5285 RADV_FROM_HANDLE(radv_event, event, _event);
5286
5287 write_event(cmd_buffer, event, stageMask, 1);
5288 }
5289
5290 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5291 VkEvent _event,
5292 VkPipelineStageFlags stageMask)
5293 {
5294 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5295 RADV_FROM_HANDLE(radv_event, event, _event);
5296
5297 write_event(cmd_buffer, event, stageMask, 0);
5298 }
5299
5300 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5301 uint32_t eventCount,
5302 const VkEvent* pEvents,
5303 VkPipelineStageFlags srcStageMask,
5304 VkPipelineStageFlags dstStageMask,
5305 uint32_t memoryBarrierCount,
5306 const VkMemoryBarrier* pMemoryBarriers,
5307 uint32_t bufferMemoryBarrierCount,
5308 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5309 uint32_t imageMemoryBarrierCount,
5310 const VkImageMemoryBarrier* pImageMemoryBarriers)
5311 {
5312 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5313 struct radv_barrier_info info;
5314
5315 info.eventCount = eventCount;
5316 info.pEvents = pEvents;
5317 info.srcStageMask = 0;
5318
5319 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5320 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5321 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5322 }
5323
5324
5325 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5326 uint32_t deviceMask)
5327 {
5328 /* No-op */
5329 }
5330
5331 /* VK_EXT_conditional_rendering */
5332 void radv_CmdBeginConditionalRenderingEXT(
5333 VkCommandBuffer commandBuffer,
5334 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5335 {
5336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5337 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5338 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5339 bool draw_visible = true;
5340 uint64_t pred_value = 0;
5341 uint64_t va, new_va;
5342 unsigned pred_offset;
5343
5344 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5345
5346 /* By default, if the 32-bit value at offset in buffer memory is zero,
5347 * then the rendering commands are discarded, otherwise they are
5348 * executed as normal. If the inverted flag is set, all commands are
5349 * discarded if the value is non zero.
5350 */
5351 if (pConditionalRenderingBegin->flags &
5352 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5353 draw_visible = false;
5354 }
5355
5356 si_emit_cache_flush(cmd_buffer);
5357
5358 /* From the Vulkan spec 1.1.107:
5359 *
5360 * "If the 32-bit value at offset in buffer memory is zero, then the
5361 * rendering commands are discarded, otherwise they are executed as
5362 * normal. If the value of the predicate in buffer memory changes while
5363 * conditional rendering is active, the rendering commands may be
5364 * discarded in an implementation-dependent way. Some implementations
5365 * may latch the value of the predicate upon beginning conditional
5366 * rendering while others may read it before every rendering command."
5367 *
5368 * But, the AMD hardware treats the predicate as a 64-bit value which
5369 * means we need a workaround in the driver. Luckily, it's not required
5370 * to support if the value changes when predication is active.
5371 *
5372 * The workaround is as follows:
5373 * 1) allocate a 64-value in the upload BO and initialize it to 0
5374 * 2) copy the 32-bit predicate value to the upload BO
5375 * 3) use the new allocated VA address for predication
5376 *
5377 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5378 * in ME (+ sync PFP) instead of PFP.
5379 */
5380 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5381
5382 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5383
5384 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5385 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5386 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5387 COPY_DATA_WR_CONFIRM);
5388 radeon_emit(cs, va);
5389 radeon_emit(cs, va >> 32);
5390 radeon_emit(cs, new_va);
5391 radeon_emit(cs, new_va >> 32);
5392
5393 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5394 radeon_emit(cs, 0);
5395
5396 /* Enable predication for this command buffer. */
5397 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5398 cmd_buffer->state.predicating = true;
5399
5400 /* Store conditional rendering user info. */
5401 cmd_buffer->state.predication_type = draw_visible;
5402 cmd_buffer->state.predication_va = new_va;
5403 }
5404
5405 void radv_CmdEndConditionalRenderingEXT(
5406 VkCommandBuffer commandBuffer)
5407 {
5408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5409
5410 /* Disable predication for this command buffer. */
5411 si_emit_set_predication_state(cmd_buffer, false, 0);
5412 cmd_buffer->state.predicating = false;
5413
5414 /* Reset conditional rendering user info. */
5415 cmd_buffer->state.predication_type = -1;
5416 cmd_buffer->state.predication_va = 0;
5417 }
5418
5419 /* VK_EXT_transform_feedback */
5420 void radv_CmdBindTransformFeedbackBuffersEXT(
5421 VkCommandBuffer commandBuffer,
5422 uint32_t firstBinding,
5423 uint32_t bindingCount,
5424 const VkBuffer* pBuffers,
5425 const VkDeviceSize* pOffsets,
5426 const VkDeviceSize* pSizes)
5427 {
5428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5429 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5430 uint8_t enabled_mask = 0;
5431
5432 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5433 for (uint32_t i = 0; i < bindingCount; i++) {
5434 uint32_t idx = firstBinding + i;
5435
5436 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5437 sb[idx].offset = pOffsets[i];
5438 sb[idx].size = pSizes[i];
5439
5440 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5441 sb[idx].buffer->bo);
5442
5443 enabled_mask |= 1 << idx;
5444 }
5445
5446 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5447
5448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5449 }
5450
5451 static void
5452 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5453 {
5454 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5455 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5456
5457 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5458 radeon_emit(cs,
5459 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5460 S_028B94_RAST_STREAM(0) |
5461 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5462 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5463 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5464 radeon_emit(cs, so->hw_enabled_mask &
5465 so->enabled_stream_buffers_mask);
5466
5467 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5468 }
5469
5470 static void
5471 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5472 {
5473 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5474 bool old_streamout_enabled = so->streamout_enabled;
5475 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5476
5477 so->streamout_enabled = enable;
5478
5479 so->hw_enabled_mask = so->enabled_mask |
5480 (so->enabled_mask << 4) |
5481 (so->enabled_mask << 8) |
5482 (so->enabled_mask << 12);
5483
5484 if ((old_streamout_enabled != so->streamout_enabled) ||
5485 (old_hw_enabled_mask != so->hw_enabled_mask))
5486 radv_emit_streamout_enable(cmd_buffer);
5487 }
5488
5489 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5490 {
5491 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5492 unsigned reg_strmout_cntl;
5493
5494 /* The register is at different places on different ASICs. */
5495 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5496 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5497 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5498 } else {
5499 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5500 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5501 }
5502
5503 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5504 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5505
5506 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5507 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5508 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5509 radeon_emit(cs, 0);
5510 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5511 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5512 radeon_emit(cs, 4); /* poll interval */
5513 }
5514
5515 void radv_CmdBeginTransformFeedbackEXT(
5516 VkCommandBuffer commandBuffer,
5517 uint32_t firstCounterBuffer,
5518 uint32_t counterBufferCount,
5519 const VkBuffer* pCounterBuffers,
5520 const VkDeviceSize* pCounterBufferOffsets)
5521 {
5522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5523 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5524 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5525 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5526 uint32_t i;
5527
5528 radv_flush_vgt_streamout(cmd_buffer);
5529
5530 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5531 for_each_bit(i, so->enabled_mask) {
5532 int32_t counter_buffer_idx = i - firstCounterBuffer;
5533 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5534 counter_buffer_idx = -1;
5535
5536 /* AMD GCN binds streamout buffers as shader resources.
5537 * VGT only counts primitives and tells the shader through
5538 * SGPRs what to do.
5539 */
5540 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5541 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5542 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5543
5544 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5545
5546 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5547 /* The array of counter buffers is optional. */
5548 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5549 uint64_t va = radv_buffer_get_va(buffer->bo);
5550
5551 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5552
5553 /* Append */
5554 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5555 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5556 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5557 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5558 radeon_emit(cs, 0); /* unused */
5559 radeon_emit(cs, 0); /* unused */
5560 radeon_emit(cs, va); /* src address lo */
5561 radeon_emit(cs, va >> 32); /* src address hi */
5562
5563 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5564 } else {
5565 /* Start from the beginning. */
5566 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5567 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5568 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5569 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5570 radeon_emit(cs, 0); /* unused */
5571 radeon_emit(cs, 0); /* unused */
5572 radeon_emit(cs, 0); /* unused */
5573 radeon_emit(cs, 0); /* unused */
5574 }
5575 }
5576
5577 radv_set_streamout_enable(cmd_buffer, true);
5578 }
5579
5580 void radv_CmdEndTransformFeedbackEXT(
5581 VkCommandBuffer commandBuffer,
5582 uint32_t firstCounterBuffer,
5583 uint32_t counterBufferCount,
5584 const VkBuffer* pCounterBuffers,
5585 const VkDeviceSize* pCounterBufferOffsets)
5586 {
5587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5588 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5589 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5590 uint32_t i;
5591
5592 radv_flush_vgt_streamout(cmd_buffer);
5593
5594 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5595 for_each_bit(i, so->enabled_mask) {
5596 int32_t counter_buffer_idx = i - firstCounterBuffer;
5597 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5598 counter_buffer_idx = -1;
5599
5600 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5601 /* The array of counters buffer is optional. */
5602 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5603 uint64_t va = radv_buffer_get_va(buffer->bo);
5604
5605 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5606
5607 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5608 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5609 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5610 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5611 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5612 radeon_emit(cs, va); /* dst address lo */
5613 radeon_emit(cs, va >> 32); /* dst address hi */
5614 radeon_emit(cs, 0); /* unused */
5615 radeon_emit(cs, 0); /* unused */
5616
5617 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5618 }
5619
5620 /* Deactivate transform feedback by zeroing the buffer size.
5621 * The counters (primitives generated, primitives emitted) may
5622 * be enabled even if there is not buffer bound. This ensures
5623 * that the primitives-emitted query won't increment.
5624 */
5625 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5626
5627 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5628 }
5629
5630 radv_set_streamout_enable(cmd_buffer, false);
5631 }
5632
5633 void radv_CmdDrawIndirectByteCountEXT(
5634 VkCommandBuffer commandBuffer,
5635 uint32_t instanceCount,
5636 uint32_t firstInstance,
5637 VkBuffer _counterBuffer,
5638 VkDeviceSize counterBufferOffset,
5639 uint32_t counterOffset,
5640 uint32_t vertexStride)
5641 {
5642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5643 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5644 struct radv_draw_info info = {};
5645
5646 info.instance_count = instanceCount;
5647 info.first_instance = firstInstance;
5648 info.strmout_buffer = counterBuffer;
5649 info.strmout_buffer_offset = counterBufferOffset;
5650 info.stride = vertexStride;
5651
5652 radv_draw(cmd_buffer, &info);
5653 }