2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
83 const struct radv_dynamic_state
*src
)
85 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
86 uint32_t copy_mask
= src
->mask
;
87 uint32_t dest_mask
= 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest
->viewport
.count
= src
->viewport
.count
;
93 dest
->scissor
.count
= src
->scissor
.count
;
95 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
96 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
97 src
->viewport
.count
* sizeof(VkViewport
))) {
98 typed_memcpy(dest
->viewport
.viewports
,
99 src
->viewport
.viewports
,
100 src
->viewport
.count
);
101 dest_mask
|= 1 << VK_DYNAMIC_STATE_VIEWPORT
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
106 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
107 src
->scissor
.count
* sizeof(VkRect2D
))) {
108 typed_memcpy(dest
->scissor
.scissors
,
109 src
->scissor
.scissors
, src
->scissor
.count
);
110 dest_mask
|= 1 << VK_DYNAMIC_STATE_SCISSOR
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
115 if (dest
->line_width
!= src
->line_width
) {
116 dest
->line_width
= src
->line_width
;
117 dest_mask
|= 1 << VK_DYNAMIC_STATE_LINE_WIDTH
;
121 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
122 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
123 sizeof(src
->depth_bias
))) {
124 dest
->depth_bias
= src
->depth_bias
;
125 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS
;
129 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
130 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
131 sizeof(src
->blend_constants
))) {
132 typed_memcpy(dest
->blend_constants
,
133 src
->blend_constants
, 4);
134 dest_mask
|= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
;
138 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
139 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
140 sizeof(src
->depth_bounds
))) {
141 dest
->depth_bounds
= src
->depth_bounds
;
142 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
;
146 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
147 if (memcmp(&dest
->stencil_compare_mask
,
148 &src
->stencil_compare_mask
,
149 sizeof(src
->stencil_compare_mask
))) {
150 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
151 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
;
155 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
156 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
157 sizeof(src
->stencil_write_mask
))) {
158 dest
->stencil_write_mask
= src
->stencil_write_mask
;
159 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
;
163 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
164 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
165 sizeof(src
->stencil_reference
))) {
166 dest
->stencil_reference
= src
->stencil_reference
;
167 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
;
171 cmd_buffer
->state
.dirty
|= dest_mask
;
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
176 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
177 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
180 enum ring_type
radv_queue_family_to_ring(int f
) {
182 case RADV_QUEUE_GENERAL
:
184 case RADV_QUEUE_COMPUTE
:
186 case RADV_QUEUE_TRANSFER
:
189 unreachable("Unknown queue family");
193 static VkResult
radv_create_cmd_buffer(
194 struct radv_device
* device
,
195 struct radv_cmd_pool
* pool
,
196 VkCommandBufferLevel level
,
197 VkCommandBuffer
* pCommandBuffer
)
199 struct radv_cmd_buffer
*cmd_buffer
;
201 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
203 if (cmd_buffer
== NULL
)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
206 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
207 cmd_buffer
->device
= device
;
208 cmd_buffer
->pool
= pool
;
209 cmd_buffer
->level
= level
;
212 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
213 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
216 /* Init the pool_link so we can safefly call list_del when we destroy
219 list_inithead(&cmd_buffer
->pool_link
);
220 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
223 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
225 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
226 if (!cmd_buffer
->cs
) {
227 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
231 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
233 list_inithead(&cmd_buffer
->upload
.list
);
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
241 list_del(&cmd_buffer
->pool_link
);
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
244 &cmd_buffer
->upload
.list
, list
) {
245 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
250 if (cmd_buffer
->upload
.upload_bo
)
251 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
252 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
253 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
254 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
258 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
261 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
264 &cmd_buffer
->upload
.list
, list
) {
265 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
270 cmd_buffer
->push_constant_stages
= 0;
271 cmd_buffer
->scratch_size_needed
= 0;
272 cmd_buffer
->compute_scratch_size_needed
= 0;
273 cmd_buffer
->esgs_ring_size_needed
= 0;
274 cmd_buffer
->gsvs_ring_size_needed
= 0;
275 cmd_buffer
->tess_rings_needed
= false;
276 cmd_buffer
->sample_positions_needed
= false;
278 if (cmd_buffer
->upload
.upload_bo
)
279 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
280 cmd_buffer
->upload
.upload_bo
, 8);
281 cmd_buffer
->upload
.offset
= 0;
283 cmd_buffer
->record_result
= VK_SUCCESS
;
285 cmd_buffer
->ring_offsets_idx
= -1;
287 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
289 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
290 &cmd_buffer
->gfx9_fence_offset
,
292 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
295 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
297 return cmd_buffer
->record_result
;
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
305 struct radeon_winsys_bo
*bo
;
306 struct radv_cmd_buffer_upload
*upload
;
307 struct radv_device
*device
= cmd_buffer
->device
;
309 new_size
= MAX2(min_needed
, 16 * 1024);
310 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
312 bo
= device
->ws
->buffer_create(device
->ws
,
315 RADEON_FLAG_CPU_ACCESS
|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
319 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
323 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
, 8);
324 if (cmd_buffer
->upload
.upload_bo
) {
325 upload
= malloc(sizeof(*upload
));
328 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
329 device
->ws
->buffer_destroy(bo
);
333 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
334 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
337 cmd_buffer
->upload
.upload_bo
= bo
;
338 cmd_buffer
->upload
.size
= new_size
;
339 cmd_buffer
->upload
.offset
= 0;
340 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
342 if (!cmd_buffer
->upload
.map
) {
343 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
354 unsigned *out_offset
,
357 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
358 if (offset
+ size
> cmd_buffer
->upload
.size
) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
364 *out_offset
= offset
;
365 *ptr
= cmd_buffer
->upload
.map
+ offset
;
367 cmd_buffer
->upload
.offset
= offset
+ size
;
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
373 unsigned size
, unsigned alignment
,
374 const void *data
, unsigned *out_offset
)
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
379 out_offset
, (void **)&ptr
))
383 memcpy(ptr
, data
, size
);
389 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
390 unsigned count
, const uint32_t *data
)
392 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
393 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME
));
397 radeon_emit(cs
, va
>> 32);
398 radeon_emit_array(cs
, data
, count
);
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
403 struct radv_device
*device
= cmd_buffer
->device
;
404 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
407 va
= radv_buffer_get_va(device
->trace_bo
);
408 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
411 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
413 ++cmd_buffer
->state
.trace_id
;
414 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
415 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
416 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
417 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
423 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
424 enum radv_cmd_flush_bits flags
;
426 /* Force wait for graphics/compute engines to be idle. */
427 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
430 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
431 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
433 radv_cmd_buffer_uses_mec(cmd_buffer
),
437 if (unlikely(cmd_buffer
->device
->trace_bo
))
438 radv_cmd_buffer_trace_emit(cmd_buffer
);
442 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
443 struct radv_pipeline
*pipeline
, enum ring_type ring
)
445 struct radv_device
*device
= cmd_buffer
->device
;
446 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
450 va
= radv_buffer_get_va(device
->trace_bo
);
460 assert(!"invalid ring type");
463 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
466 data
[0] = (uintptr_t)pipeline
;
467 data
[1] = (uintptr_t)pipeline
>> 32;
469 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
470 radv_emit_write_data_packet(cs
, va
, 2, data
);
473 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
474 struct radv_descriptor_set
*set
,
477 cmd_buffer
->descriptors
[idx
] = set
;
479 cmd_buffer
->state
.valid_descriptors
|= (1u << idx
);
481 cmd_buffer
->state
.valid_descriptors
&= ~(1u << idx
);
482 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
487 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
489 struct radv_device
*device
= cmd_buffer
->device
;
490 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
491 uint32_t data
[MAX_SETS
* 2] = {};
494 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
496 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
497 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
499 for_each_bit(i
, cmd_buffer
->state
.valid_descriptors
) {
500 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
501 data
[i
* 2] = (uintptr_t)set
;
502 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
505 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
506 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
511 struct radv_pipeline
*pipeline
)
513 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
514 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
516 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
517 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
519 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
521 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
522 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
524 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
525 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
533 struct radv_pipeline
*pipeline
)
535 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
536 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
537 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
539 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
540 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
543 struct ac_userdata_info
*
544 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
545 gl_shader_stage stage
,
548 if (stage
== MESA_SHADER_VERTEX
) {
549 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
550 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.user_sgprs_locs
.shader_data
[idx
];
551 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
552 return &pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.user_sgprs_locs
.shader_data
[idx
];
553 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
554 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
555 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
556 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
557 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.user_sgprs_locs
.shader_data
[idx
];
558 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
559 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
561 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
565 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
566 struct radv_pipeline
*pipeline
,
567 gl_shader_stage stage
,
568 int idx
, uint64_t va
)
570 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
571 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
572 if (loc
->sgpr_idx
== -1)
574 assert(loc
->num_sgprs
== 2);
575 assert(!loc
->indirect
);
576 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
577 radeon_emit(cmd_buffer
->cs
, va
);
578 radeon_emit(cmd_buffer
->cs
, va
>> 32);
582 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
583 struct radv_pipeline
*pipeline
)
585 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
586 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
587 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
589 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
590 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
591 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
593 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
594 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
596 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
599 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
600 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
601 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
603 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
605 /* GFX9: Flush DFSM when the AA mode changes. */
606 if (cmd_buffer
->device
->dfsm_allowed
) {
607 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
608 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
610 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
612 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
613 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_FRAGMENT
];
614 if (loc
->sgpr_idx
== -1)
616 assert(loc
->num_sgprs
== 1);
617 assert(!loc
->indirect
);
618 switch (num_samples
) {
636 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
637 cmd_buffer
->sample_positions_needed
= true;
642 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
643 struct radv_pipeline
*pipeline
)
645 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
647 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
648 raster
->pa_cl_clip_cntl
);
649 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
650 raster
->spi_interp_control
);
651 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
652 raster
->pa_su_vtx_cntl
);
653 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
654 raster
->pa_su_sc_mode_cntl
);
658 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
661 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
662 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
666 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer
*cmd_buffer
)
668 if (cmd_buffer
->state
.vb_prefetch_dirty
) {
669 radv_emit_prefetch_TC_L2_async(cmd_buffer
,
670 cmd_buffer
->state
.vb_va
,
671 cmd_buffer
->state
.vb_size
);
672 cmd_buffer
->state
.vb_prefetch_dirty
= false;
677 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
678 struct radv_shader_variant
*shader
)
680 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
681 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
687 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
689 radv_cs_add_buffer(ws
, cs
, shader
->bo
, 8);
690 radv_emit_prefetch_TC_L2_async(cmd_buffer
, va
, shader
->code_size
);
694 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
695 struct radv_pipeline
*pipeline
)
697 radv_emit_shader_prefetch(cmd_buffer
,
698 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
699 radv_emit_VBO_descriptors_prefetch(cmd_buffer
);
700 radv_emit_shader_prefetch(cmd_buffer
,
701 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
702 radv_emit_shader_prefetch(cmd_buffer
,
703 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
704 radv_emit_shader_prefetch(cmd_buffer
,
705 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
706 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
707 radv_emit_shader_prefetch(cmd_buffer
,
708 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
712 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
713 struct radv_pipeline
*pipeline
,
714 struct radv_shader_variant
*shader
)
716 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
718 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
719 pipeline
->graphics
.vs
.spi_vs_out_config
);
721 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
722 pipeline
->graphics
.vs
.spi_shader_pos_format
);
724 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
725 radeon_emit(cmd_buffer
->cs
, va
>> 8);
726 radeon_emit(cmd_buffer
->cs
, va
>> 40);
727 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
728 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
730 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
731 S_028818_VTX_W0_FMT(1) |
732 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
733 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
734 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
737 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
738 pipeline
->graphics
.vs
.pa_cl_vs_out_cntl
);
740 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
741 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
742 pipeline
->graphics
.vs
.vgt_reuse_off
);
746 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
747 struct radv_pipeline
*pipeline
,
748 struct radv_shader_variant
*shader
)
750 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
752 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
753 radeon_emit(cmd_buffer
->cs
, va
>> 8);
754 radeon_emit(cmd_buffer
->cs
, va
>> 40);
755 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
756 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
760 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
761 struct radv_shader_variant
*shader
)
763 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
764 uint32_t rsrc2
= shader
->rsrc2
;
766 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
767 radeon_emit(cmd_buffer
->cs
, va
>> 8);
768 radeon_emit(cmd_buffer
->cs
, va
>> 40);
770 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
771 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
772 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
773 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
775 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
776 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
777 radeon_emit(cmd_buffer
->cs
, rsrc2
);
781 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
782 struct radv_shader_variant
*shader
)
784 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
786 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
787 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
788 radeon_emit(cmd_buffer
->cs
, va
>> 8);
789 radeon_emit(cmd_buffer
->cs
, va
>> 40);
791 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
792 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
793 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
|
794 S_00B42C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
));
796 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
797 radeon_emit(cmd_buffer
->cs
, va
>> 8);
798 radeon_emit(cmd_buffer
->cs
, va
>> 40);
799 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
800 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
805 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
806 struct radv_pipeline
*pipeline
)
808 struct radv_shader_variant
*vs
;
810 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
812 /* Skip shaders merged into HS/GS */
813 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
817 if (vs
->info
.vs
.as_ls
)
818 radv_emit_hw_ls(cmd_buffer
, vs
);
819 else if (vs
->info
.vs
.as_es
)
820 radv_emit_hw_es(cmd_buffer
, pipeline
, vs
);
822 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
);
827 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
828 struct radv_pipeline
*pipeline
)
830 if (!radv_pipeline_has_tess(pipeline
))
833 struct radv_shader_variant
*tes
, *tcs
;
835 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
836 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
839 if (tes
->info
.tes
.as_es
)
840 radv_emit_hw_es(cmd_buffer
, pipeline
, tes
);
842 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
);
845 radv_emit_hw_hs(cmd_buffer
, tcs
);
847 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
848 pipeline
->graphics
.tess
.tf_param
);
850 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
851 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
852 pipeline
->graphics
.tess
.ls_hs_config
);
854 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
855 pipeline
->graphics
.tess
.ls_hs_config
);
857 struct ac_userdata_info
*loc
;
859 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
860 if (loc
->sgpr_idx
!= -1) {
861 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_CTRL
];
862 assert(loc
->num_sgprs
== 4);
863 assert(!loc
->indirect
);
864 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
865 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
866 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
867 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
868 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
869 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
872 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
873 if (loc
->sgpr_idx
!= -1) {
874 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_EVAL
];
875 assert(loc
->num_sgprs
== 1);
876 assert(!loc
->indirect
);
878 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
879 pipeline
->graphics
.tess
.offchip_layout
);
882 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
883 if (loc
->sgpr_idx
!= -1) {
884 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
885 assert(loc
->num_sgprs
== 1);
886 assert(!loc
->indirect
);
888 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
889 pipeline
->graphics
.tess
.tcs_in_layout
);
894 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
895 struct radv_pipeline
*pipeline
)
897 struct radv_shader_variant
*gs
;
900 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
902 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
906 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
908 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
909 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
910 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
911 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
913 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
915 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
917 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
918 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
919 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
920 radeon_emit(cmd_buffer
->cs
, 0);
921 radeon_emit(cmd_buffer
->cs
, 0);
922 radeon_emit(cmd_buffer
->cs
, 0);
924 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
925 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
926 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
927 S_028B90_ENABLE(gs_num_invocations
> 0));
929 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
930 pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
932 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
934 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
935 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
936 radeon_emit(cmd_buffer
->cs
, va
>> 8);
937 radeon_emit(cmd_buffer
->cs
, va
>> 40);
939 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
940 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
941 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
|
942 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
944 radeon_set_context_reg(cmd_buffer
->cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
945 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
947 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
948 radeon_emit(cmd_buffer
->cs
, va
>> 8);
949 radeon_emit(cmd_buffer
->cs
, va
>> 40);
950 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
951 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
954 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
);
956 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
957 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
958 if (loc
->sgpr_idx
!= -1) {
959 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
960 uint32_t num_entries
= 64;
961 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
964 num_entries
*= stride
;
966 stride
= S_008F04_STRIDE(stride
);
967 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
968 radeon_emit(cmd_buffer
->cs
, stride
);
969 radeon_emit(cmd_buffer
->cs
, num_entries
);
974 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
975 struct radv_pipeline
*pipeline
)
977 struct radv_shader_variant
*ps
;
979 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
980 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
981 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
983 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
984 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
986 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
987 radeon_emit(cmd_buffer
->cs
, va
>> 8);
988 radeon_emit(cmd_buffer
->cs
, va
>> 40);
989 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
990 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
992 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
993 pipeline
->graphics
.db_shader_control
);
995 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
996 ps
->config
.spi_ps_input_ena
);
998 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
999 ps
->config
.spi_ps_input_addr
);
1001 if (ps
->info
.info
.ps
.force_persample
)
1002 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1004 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
1005 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
1007 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1009 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
1010 pipeline
->graphics
.shader_z_format
);
1012 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
1014 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
1015 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
1017 if (cmd_buffer
->device
->dfsm_allowed
) {
1018 /* optimise this? */
1019 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1020 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
1023 if (pipeline
->graphics
.ps_input_cntl_num
) {
1024 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
1025 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
1026 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
1032 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
1033 struct radv_pipeline
*pipeline
)
1035 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1037 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
1040 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1041 pipeline
->graphics
.vtx_reuse_depth
);
1045 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1047 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1049 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1052 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
1053 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
1054 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
1055 radv_update_multisample_state(cmd_buffer
, pipeline
);
1056 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
1057 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
1058 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
1059 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
1060 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
1062 cmd_buffer
->scratch_size_needed
=
1063 MAX2(cmd_buffer
->scratch_size_needed
,
1064 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1066 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
1067 S_0286E8_WAVES(pipeline
->max_waves
) |
1068 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
1070 if (!cmd_buffer
->state
.emitted_pipeline
||
1071 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1072 pipeline
->graphics
.can_use_guardband
)
1073 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1075 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1077 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1078 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
1080 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
1082 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
1084 if (unlikely(cmd_buffer
->device
->trace_bo
))
1085 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1087 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1089 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1093 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1095 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1096 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1100 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1102 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1104 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1105 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1106 si_emit_cache_flush(cmd_buffer
);
1108 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1109 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1110 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1111 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1112 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1113 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1117 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1119 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1121 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1122 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1126 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1128 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1130 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1131 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1135 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1137 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1139 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1140 R_028430_DB_STENCILREFMASK
, 2);
1141 radeon_emit(cmd_buffer
->cs
,
1142 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1143 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1144 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1145 S_028430_STENCILOPVAL(1));
1146 radeon_emit(cmd_buffer
->cs
,
1147 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1148 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1149 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1150 S_028434_STENCILOPVAL_BF(1));
1154 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1156 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1158 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1159 fui(d
->depth_bounds
.min
));
1160 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1161 fui(d
->depth_bounds
.max
));
1165 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1167 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1168 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1169 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1170 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1172 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1173 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1174 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1175 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1176 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1177 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1178 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1179 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1184 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1186 struct radv_attachment_info
*att
)
1188 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1189 struct radv_color_buffer_info
*cb
= &att
->cb
;
1191 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1192 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1193 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1194 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1195 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1196 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1197 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1198 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1199 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1200 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1201 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1202 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1203 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1205 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1206 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1207 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1209 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1210 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1212 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1213 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1214 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1215 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1216 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1217 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1218 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1219 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1220 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1221 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1222 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1223 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1225 if (is_vi
) { /* DCC BASE */
1226 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1232 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1233 struct radv_ds_buffer_info
*ds
,
1234 struct radv_image
*image
,
1235 VkImageLayout layout
)
1237 uint32_t db_z_info
= ds
->db_z_info
;
1238 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1240 if (!radv_layout_has_htile(image
, layout
,
1241 radv_image_queue_family_mask(image
,
1242 cmd_buffer
->queue_family_index
,
1243 cmd_buffer
->queue_family_index
))) {
1244 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1245 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1248 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1249 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1252 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1253 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1254 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1255 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1256 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1258 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1259 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1260 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1261 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1262 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1263 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1264 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1265 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1266 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1267 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1268 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1270 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1271 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1272 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1274 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1276 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1277 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1278 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1279 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1280 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1281 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1282 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1283 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1284 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1285 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1289 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1290 ds
->pa_su_poly_offset_db_fmt_cntl
);
1294 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1295 struct radv_image
*image
,
1296 VkClearDepthStencilValue ds_clear_value
,
1297 VkImageAspectFlags aspects
)
1299 uint64_t va
= radv_buffer_get_va(image
->bo
);
1300 va
+= image
->offset
+ image
->clear_value_offset
;
1301 unsigned reg_offset
= 0, reg_count
= 0;
1303 assert(image
->surface
.htile_size
);
1305 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1311 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1314 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1315 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP
));
1318 radeon_emit(cmd_buffer
->cs
, va
);
1319 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1320 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1321 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1322 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1323 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1325 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1326 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1327 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1328 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1329 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1333 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1334 struct radv_image
*image
)
1336 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1337 uint64_t va
= radv_buffer_get_va(image
->bo
);
1338 va
+= image
->offset
+ image
->clear_value_offset
;
1339 unsigned reg_offset
= 0, reg_count
= 0;
1341 if (!image
->surface
.htile_size
)
1344 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1350 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1353 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1354 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1355 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1356 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1357 radeon_emit(cmd_buffer
->cs
, va
);
1358 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1359 radeon_emit(cmd_buffer
->cs
, (R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
) >> 2);
1360 radeon_emit(cmd_buffer
->cs
, 0);
1362 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1363 radeon_emit(cmd_buffer
->cs
, 0);
1367 *with DCC some colors don't require CMASK elimiation before being
1368 * used as a texture. This sets a predicate value to determine if the
1369 * cmask eliminate is required.
1372 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1373 struct radv_image
*image
,
1376 uint64_t pred_val
= value
;
1377 uint64_t va
= radv_buffer_get_va(image
->bo
);
1378 va
+= image
->offset
+ image
->dcc_pred_offset
;
1380 assert(image
->surface
.dcc_size
);
1382 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1383 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1384 S_370_WR_CONFIRM(1) |
1385 S_370_ENGINE_SEL(V_370_PFP
));
1386 radeon_emit(cmd_buffer
->cs
, va
);
1387 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1388 radeon_emit(cmd_buffer
->cs
, pred_val
);
1389 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1393 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1394 struct radv_image
*image
,
1396 uint32_t color_values
[2])
1398 uint64_t va
= radv_buffer_get_va(image
->bo
);
1399 va
+= image
->offset
+ image
->clear_value_offset
;
1401 assert(image
->cmask
.size
|| image
->surface
.dcc_size
);
1403 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1404 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1405 S_370_WR_CONFIRM(1) |
1406 S_370_ENGINE_SEL(V_370_PFP
));
1407 radeon_emit(cmd_buffer
->cs
, va
);
1408 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1409 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1410 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1412 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1413 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1414 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1418 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1419 struct radv_image
*image
,
1422 uint64_t va
= radv_buffer_get_va(image
->bo
);
1423 va
+= image
->offset
+ image
->clear_value_offset
;
1425 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1428 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1430 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1431 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1432 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1433 COPY_DATA_COUNT_SEL
);
1434 radeon_emit(cmd_buffer
->cs
, va
);
1435 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1436 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1437 radeon_emit(cmd_buffer
->cs
, 0);
1439 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1440 radeon_emit(cmd_buffer
->cs
, 0);
1444 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1447 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1448 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1450 /* this may happen for inherited secondary recording */
1454 for (i
= 0; i
< 8; ++i
) {
1455 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1456 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1457 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1461 int idx
= subpass
->color_attachments
[i
].attachment
;
1462 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1464 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1466 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1467 radv_emit_fb_color_state(cmd_buffer
, i
, att
);
1469 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1472 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1473 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1474 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1475 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1476 struct radv_image
*image
= att
->attachment
->image
;
1477 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1478 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1479 cmd_buffer
->queue_family_index
,
1480 cmd_buffer
->queue_family_index
);
1481 /* We currently don't support writing decompressed HTILE */
1482 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1483 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1485 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1487 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1488 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1489 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1491 radv_load_depth_clear_regs(cmd_buffer
, image
);
1493 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1494 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1496 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1498 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1499 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1501 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1502 S_028208_BR_X(framebuffer
->width
) |
1503 S_028208_BR_Y(framebuffer
->height
));
1505 if (cmd_buffer
->device
->dfsm_allowed
) {
1506 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1507 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1510 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1514 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1516 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1517 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1519 if (state
->index_type
!= state
->last_index_type
) {
1520 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1521 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1522 2, state
->index_type
);
1524 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1525 radeon_emit(cs
, state
->index_type
);
1528 state
->last_index_type
= state
->index_type
;
1531 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1532 radeon_emit(cs
, state
->index_va
);
1533 radeon_emit(cs
, state
->index_va
>> 32);
1535 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1536 radeon_emit(cs
, state
->max_index_count
);
1538 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1541 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1543 uint32_t db_count_control
;
1545 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1546 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1547 db_count_control
= 0;
1549 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1552 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1553 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1554 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1555 S_028004_ZPASS_ENABLE(1) |
1556 S_028004_SLICE_EVEN_ENABLE(1) |
1557 S_028004_SLICE_ODD_ENABLE(1);
1559 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1560 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1564 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1568 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1570 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1573 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1574 radv_emit_viewport(cmd_buffer
);
1576 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1577 radv_emit_scissor(cmd_buffer
);
1579 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1580 radv_emit_line_width(cmd_buffer
);
1582 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1583 radv_emit_blend_constants(cmd_buffer
);
1585 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1586 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1587 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1588 radv_emit_stencil(cmd_buffer
);
1590 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1591 radv_emit_depth_bounds(cmd_buffer
);
1593 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1594 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1595 radv_emit_depth_biais(cmd_buffer
);
1597 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
1601 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1602 struct radv_pipeline
*pipeline
,
1605 gl_shader_stage stage
)
1607 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1608 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
1610 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1613 assert(!desc_set_loc
->indirect
);
1614 assert(desc_set_loc
->num_sgprs
== 2);
1615 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1616 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1617 radeon_emit(cmd_buffer
->cs
, va
);
1618 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1622 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1623 VkShaderStageFlags stages
,
1624 struct radv_descriptor_set
*set
,
1627 if (cmd_buffer
->state
.pipeline
) {
1628 radv_foreach_stage(stage
, stages
) {
1629 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1630 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1636 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1637 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1639 MESA_SHADER_COMPUTE
);
1643 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1645 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1648 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1653 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1654 set
->va
+= bo_offset
;
1658 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1660 uint32_t size
= MAX_SETS
* 2 * 4;
1664 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1665 256, &offset
, &ptr
))
1668 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1669 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1670 uint64_t set_va
= 0;
1671 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1672 if (cmd_buffer
->state
.valid_descriptors
& (1u << i
))
1674 uptr
[0] = set_va
& 0xffffffff;
1675 uptr
[1] = set_va
>> 32;
1678 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1681 if (cmd_buffer
->state
.pipeline
) {
1682 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1683 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1686 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1687 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1688 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1690 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1691 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1694 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1695 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1698 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1699 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1703 if (cmd_buffer
->state
.compute_pipeline
)
1704 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1705 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1709 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1710 VkShaderStageFlags stages
)
1714 if (!cmd_buffer
->state
.descriptors_dirty
)
1717 if (cmd_buffer
->state
.push_descriptors_dirty
)
1718 radv_flush_push_descriptors(cmd_buffer
);
1720 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1721 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1722 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1725 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1727 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1729 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1730 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1731 if (!(cmd_buffer
->state
.valid_descriptors
& (1u << i
)))
1734 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1736 cmd_buffer
->state
.descriptors_dirty
= 0;
1737 cmd_buffer
->state
.push_descriptors_dirty
= false;
1739 if (unlikely(cmd_buffer
->device
->trace_bo
))
1740 radv_save_descriptors(cmd_buffer
);
1742 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1746 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1747 struct radv_pipeline
*pipeline
,
1748 VkShaderStageFlags stages
)
1750 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1755 stages
&= cmd_buffer
->push_constant_stages
;
1757 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1760 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1761 16 * layout
->dynamic_offset_count
,
1762 256, &offset
, &ptr
))
1765 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1766 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1767 16 * layout
->dynamic_offset_count
);
1769 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1772 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1773 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1775 radv_foreach_stage(stage
, stages
) {
1776 if (pipeline
->shaders
[stage
]) {
1777 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1778 AC_UD_PUSH_CONSTANTS
, va
);
1782 cmd_buffer
->push_constant_stages
&= ~stages
;
1783 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1787 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1789 if ((pipeline_is_dirty
||
1790 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1791 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1792 radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.has_vertex_buffers
) {
1793 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1797 uint32_t count
= velems
->count
;
1800 /* allocate some descriptor state for vertex buffers */
1801 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1802 &vb_offset
, &vb_ptr
))
1805 for (i
= 0; i
< count
; i
++) {
1806 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1808 int vb
= velems
->binding
[i
];
1809 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1810 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1812 va
= radv_buffer_get_va(buffer
->bo
);
1814 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1815 va
+= offset
+ buffer
->offset
;
1817 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1818 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1819 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1821 desc
[2] = buffer
->size
- offset
;
1822 desc
[3] = velems
->rsrc_word3
[i
];
1825 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1828 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1829 AC_UD_VS_VERTEX_BUFFERS
, va
);
1831 cmd_buffer
->state
.vb_va
= va
;
1832 cmd_buffer
->state
.vb_size
= count
* 16;
1833 cmd_buffer
->state
.vb_prefetch_dirty
= true;
1835 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1841 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1843 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
))
1846 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1847 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1848 VK_SHADER_STAGE_ALL_GRAPHICS
);
1854 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1855 bool instanced_draw
, bool indirect_draw
,
1856 uint32_t draw_vertex_count
)
1858 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1859 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1860 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1861 uint32_t ia_multi_vgt_param
;
1862 int32_t primitive_reset_en
;
1865 ia_multi_vgt_param
=
1866 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1867 indirect_draw
, draw_vertex_count
);
1869 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1870 if (info
->chip_class
>= GFX9
) {
1871 radeon_set_uconfig_reg_idx(cs
,
1872 R_030960_IA_MULTI_VGT_PARAM
,
1873 4, ia_multi_vgt_param
);
1874 } else if (info
->chip_class
>= CIK
) {
1875 radeon_set_context_reg_idx(cs
,
1876 R_028AA8_IA_MULTI_VGT_PARAM
,
1877 1, ia_multi_vgt_param
);
1879 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1880 ia_multi_vgt_param
);
1882 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1885 /* Primitive restart. */
1886 primitive_reset_en
=
1887 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1889 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1890 state
->last_primitive_reset_en
= primitive_reset_en
;
1891 if (info
->chip_class
>= GFX9
) {
1892 radeon_set_uconfig_reg(cs
,
1893 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1894 primitive_reset_en
);
1896 radeon_set_context_reg(cs
,
1897 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1898 primitive_reset_en
);
1902 if (primitive_reset_en
) {
1903 uint32_t primitive_reset_index
=
1904 state
->index_type
? 0xffffffffu
: 0xffffu
;
1906 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1907 radeon_set_context_reg(cs
,
1908 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1909 primitive_reset_index
);
1910 state
->last_primitive_reset_index
= primitive_reset_index
;
1915 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1916 VkPipelineStageFlags src_stage_mask
)
1918 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1919 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1920 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1921 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1922 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1925 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1926 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1927 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1928 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1929 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1930 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1931 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1932 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1933 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1934 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1935 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1936 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1937 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1938 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1939 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1940 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1944 static enum radv_cmd_flush_bits
1945 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1946 VkAccessFlags src_flags
)
1948 enum radv_cmd_flush_bits flush_bits
= 0;
1950 for_each_bit(b
, src_flags
) {
1951 switch ((VkAccessFlagBits
)(1 << b
)) {
1952 case VK_ACCESS_SHADER_WRITE_BIT
:
1953 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1955 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1956 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1957 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1959 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1960 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1961 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1963 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1964 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1965 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1966 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1967 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1968 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1977 static enum radv_cmd_flush_bits
1978 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1979 VkAccessFlags dst_flags
,
1980 struct radv_image
*image
)
1982 enum radv_cmd_flush_bits flush_bits
= 0;
1984 for_each_bit(b
, dst_flags
) {
1985 switch ((VkAccessFlagBits
)(1 << b
)) {
1986 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1987 case VK_ACCESS_INDEX_READ_BIT
:
1988 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1990 case VK_ACCESS_UNIFORM_READ_BIT
:
1991 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1993 case VK_ACCESS_SHADER_READ_BIT
:
1994 case VK_ACCESS_TRANSFER_READ_BIT
:
1995 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1996 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1997 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1999 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2000 /* TODO: change to image && when the image gets passed
2001 * through from the subpass. */
2002 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2003 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2004 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2006 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2007 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2008 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2009 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2018 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2020 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
2021 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2022 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2026 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2027 VkAttachmentReference att
)
2029 unsigned idx
= att
.attachment
;
2030 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2031 VkImageSubresourceRange range
;
2032 range
.aspectMask
= 0;
2033 range
.baseMipLevel
= view
->base_mip
;
2034 range
.levelCount
= 1;
2035 range
.baseArrayLayer
= view
->base_layer
;
2036 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2038 radv_handle_image_transition(cmd_buffer
,
2040 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2041 att
.layout
, 0, 0, &range
,
2042 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2044 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2050 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2051 const struct radv_subpass
*subpass
, bool transitions
)
2054 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2056 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2057 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2058 radv_handle_subpass_image_transition(cmd_buffer
,
2059 subpass
->color_attachments
[i
]);
2062 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2063 radv_handle_subpass_image_transition(cmd_buffer
,
2064 subpass
->input_attachments
[i
]);
2067 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2068 radv_handle_subpass_image_transition(cmd_buffer
,
2069 subpass
->depth_stencil_attachment
);
2073 cmd_buffer
->state
.subpass
= subpass
;
2075 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2079 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2080 struct radv_render_pass
*pass
,
2081 const VkRenderPassBeginInfo
*info
)
2083 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2085 if (pass
->attachment_count
== 0) {
2086 state
->attachments
= NULL
;
2090 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2091 pass
->attachment_count
*
2092 sizeof(state
->attachments
[0]),
2093 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2094 if (state
->attachments
== NULL
) {
2095 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2096 return cmd_buffer
->record_result
;
2099 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2100 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2101 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2102 VkImageAspectFlags clear_aspects
= 0;
2104 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2105 /* color attachment */
2106 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2107 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2110 /* depthstencil attachment */
2111 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2112 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2113 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2114 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2115 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2116 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2118 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2119 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2120 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2124 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2125 state
->attachments
[i
].cleared_views
= 0;
2126 if (clear_aspects
&& info
) {
2127 assert(info
->clearValueCount
> i
);
2128 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2131 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2137 VkResult
radv_AllocateCommandBuffers(
2139 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2140 VkCommandBuffer
*pCommandBuffers
)
2142 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2143 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2145 VkResult result
= VK_SUCCESS
;
2148 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2150 if (!list_empty(&pool
->free_cmd_buffers
)) {
2151 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2153 list_del(&cmd_buffer
->pool_link
);
2154 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2156 result
= radv_reset_cmd_buffer(cmd_buffer
);
2157 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2158 cmd_buffer
->level
= pAllocateInfo
->level
;
2160 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2162 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2163 &pCommandBuffers
[i
]);
2165 if (result
!= VK_SUCCESS
)
2169 if (result
!= VK_SUCCESS
) {
2170 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2171 i
, pCommandBuffers
);
2173 /* From the Vulkan 1.0.66 spec:
2175 * "vkAllocateCommandBuffers can be used to create multiple
2176 * command buffers. If the creation of any of those command
2177 * buffers fails, the implementation must destroy all
2178 * successfully created command buffer objects from this
2179 * command, set all entries of the pCommandBuffers array to
2180 * NULL and return the error."
2182 memset(pCommandBuffers
, 0,
2183 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2189 void radv_FreeCommandBuffers(
2191 VkCommandPool commandPool
,
2192 uint32_t commandBufferCount
,
2193 const VkCommandBuffer
*pCommandBuffers
)
2195 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2196 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2199 if (cmd_buffer
->pool
) {
2200 list_del(&cmd_buffer
->pool_link
);
2201 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2203 radv_cmd_buffer_destroy(cmd_buffer
);
2209 VkResult
radv_ResetCommandBuffer(
2210 VkCommandBuffer commandBuffer
,
2211 VkCommandBufferResetFlags flags
)
2213 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2214 return radv_reset_cmd_buffer(cmd_buffer
);
2217 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2219 struct radv_device
*device
= cmd_buffer
->device
;
2220 if (device
->gfx_init
) {
2221 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2222 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, device
->gfx_init
, 8);
2223 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2224 radeon_emit(cmd_buffer
->cs
, va
);
2225 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2226 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2228 si_init_config(cmd_buffer
);
2231 VkResult
radv_BeginCommandBuffer(
2232 VkCommandBuffer commandBuffer
,
2233 const VkCommandBufferBeginInfo
*pBeginInfo
)
2235 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2236 VkResult result
= VK_SUCCESS
;
2238 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2239 /* If the command buffer has already been resetted with
2240 * vkResetCommandBuffer, no need to do it again.
2242 result
= radv_reset_cmd_buffer(cmd_buffer
);
2243 if (result
!= VK_SUCCESS
)
2247 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2248 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2249 cmd_buffer
->state
.last_index_type
= -1;
2250 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2252 /* setup initial configuration into command buffer */
2253 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2254 switch (cmd_buffer
->queue_family_index
) {
2255 case RADV_QUEUE_GENERAL
:
2256 emit_gfx_buffer_state(cmd_buffer
);
2258 case RADV_QUEUE_COMPUTE
:
2259 si_init_compute(cmd_buffer
);
2261 case RADV_QUEUE_TRANSFER
:
2267 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2268 assert(pBeginInfo
->pInheritanceInfo
);
2269 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2270 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2272 struct radv_subpass
*subpass
=
2273 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2275 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2276 if (result
!= VK_SUCCESS
)
2279 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2282 if (unlikely(cmd_buffer
->device
->trace_bo
))
2283 radv_cmd_buffer_trace_emit(cmd_buffer
);
2285 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2290 void radv_CmdBindVertexBuffers(
2291 VkCommandBuffer commandBuffer
,
2292 uint32_t firstBinding
,
2293 uint32_t bindingCount
,
2294 const VkBuffer
* pBuffers
,
2295 const VkDeviceSize
* pOffsets
)
2297 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2298 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2299 bool changed
= false;
2301 /* We have to defer setting up vertex buffer since we need the buffer
2302 * stride from the pipeline. */
2304 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2305 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2306 uint32_t idx
= firstBinding
+ i
;
2309 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2310 vb
[idx
].offset
!= pOffsets
[i
])) {
2314 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2315 vb
[idx
].offset
= pOffsets
[i
];
2317 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2318 vb
[idx
].buffer
->bo
, 8);
2322 /* No state changes. */
2326 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2329 void radv_CmdBindIndexBuffer(
2330 VkCommandBuffer commandBuffer
,
2332 VkDeviceSize offset
,
2333 VkIndexType indexType
)
2335 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2336 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2338 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2339 cmd_buffer
->state
.index_offset
== offset
&&
2340 cmd_buffer
->state
.index_type
== indexType
) {
2341 /* No state changes. */
2345 cmd_buffer
->state
.index_buffer
= index_buffer
;
2346 cmd_buffer
->state
.index_offset
= offset
;
2347 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2348 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2349 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2351 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2352 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2353 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2354 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
, 8);
2359 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2360 struct radv_descriptor_set
*set
, unsigned idx
)
2362 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2364 radv_set_descriptor_set(cmd_buffer
, set
, idx
);
2368 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2370 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2371 if (set
->descriptors
[j
])
2372 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2375 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
, 8);
2378 void radv_CmdBindDescriptorSets(
2379 VkCommandBuffer commandBuffer
,
2380 VkPipelineBindPoint pipelineBindPoint
,
2381 VkPipelineLayout _layout
,
2383 uint32_t descriptorSetCount
,
2384 const VkDescriptorSet
* pDescriptorSets
,
2385 uint32_t dynamicOffsetCount
,
2386 const uint32_t* pDynamicOffsets
)
2388 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2389 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2390 unsigned dyn_idx
= 0;
2392 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2393 unsigned idx
= i
+ firstSet
;
2394 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2395 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2397 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2398 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2399 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2400 assert(dyn_idx
< dynamicOffsetCount
);
2402 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2403 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2405 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2406 dst
[2] = range
->size
;
2407 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2411 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2412 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2413 cmd_buffer
->push_constant_stages
|=
2414 set
->layout
->dynamic_shader_stages
;
2419 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2420 struct radv_descriptor_set
*set
,
2421 struct radv_descriptor_set_layout
*layout
)
2423 set
->size
= layout
->size
;
2424 set
->layout
= layout
;
2426 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2427 size_t new_size
= MAX2(set
->size
, 1024);
2428 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2429 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2431 free(set
->mapped_ptr
);
2432 set
->mapped_ptr
= malloc(new_size
);
2434 if (!set
->mapped_ptr
) {
2435 cmd_buffer
->push_descriptors
.capacity
= 0;
2436 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2440 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2446 void radv_meta_push_descriptor_set(
2447 struct radv_cmd_buffer
* cmd_buffer
,
2448 VkPipelineBindPoint pipelineBindPoint
,
2449 VkPipelineLayout _layout
,
2451 uint32_t descriptorWriteCount
,
2452 const VkWriteDescriptorSet
* pDescriptorWrites
)
2454 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2455 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2459 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2461 push_set
->size
= layout
->set
[set
].layout
->size
;
2462 push_set
->layout
= layout
->set
[set
].layout
;
2464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2466 (void**) &push_set
->mapped_ptr
))
2469 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2470 push_set
->va
+= bo_offset
;
2472 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2473 radv_descriptor_set_to_handle(push_set
),
2474 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2476 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2479 void radv_CmdPushDescriptorSetKHR(
2480 VkCommandBuffer commandBuffer
,
2481 VkPipelineBindPoint pipelineBindPoint
,
2482 VkPipelineLayout _layout
,
2484 uint32_t descriptorWriteCount
,
2485 const VkWriteDescriptorSet
* pDescriptorWrites
)
2487 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2488 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2489 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2491 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2493 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2496 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2497 radv_descriptor_set_to_handle(push_set
),
2498 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2500 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2501 cmd_buffer
->state
.push_descriptors_dirty
= true;
2504 void radv_CmdPushDescriptorSetWithTemplateKHR(
2505 VkCommandBuffer commandBuffer
,
2506 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2507 VkPipelineLayout _layout
,
2511 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2512 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2513 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2515 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2517 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2520 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2521 descriptorUpdateTemplate
, pData
);
2523 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2524 cmd_buffer
->state
.push_descriptors_dirty
= true;
2527 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2528 VkPipelineLayout layout
,
2529 VkShaderStageFlags stageFlags
,
2532 const void* pValues
)
2534 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2535 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2536 cmd_buffer
->push_constant_stages
|= stageFlags
;
2539 VkResult
radv_EndCommandBuffer(
2540 VkCommandBuffer commandBuffer
)
2542 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2544 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2545 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2546 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2547 si_emit_cache_flush(cmd_buffer
);
2550 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2552 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2553 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2555 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2557 return cmd_buffer
->record_result
;
2561 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2563 struct radv_shader_variant
*compute_shader
;
2564 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2565 struct radv_device
*device
= cmd_buffer
->device
;
2566 unsigned compute_resource_limits
;
2567 unsigned waves_per_threadgroup
;
2570 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2573 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2575 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2576 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2578 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2579 cmd_buffer
->cs
, 19);
2581 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2582 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2583 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2585 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2586 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2587 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2590 cmd_buffer
->compute_scratch_size_needed
=
2591 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2592 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2594 /* change these once we have scratch support */
2595 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2596 S_00B860_WAVES(pipeline
->max_waves
) |
2597 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2599 /* Calculate best compute resource limits. */
2600 waves_per_threadgroup
=
2601 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
2602 compute_shader
->info
.cs
.block_size
[1] *
2603 compute_shader
->info
.cs
.block_size
[2], 64);
2604 compute_resource_limits
=
2605 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
2607 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2608 unsigned num_cu_per_se
=
2609 device
->physical_device
->rad_info
.num_good_compute_units
/
2610 device
->physical_device
->rad_info
.max_se
;
2612 /* Force even distribution on all SIMDs in CU if the workgroup
2613 * size is 64. This has shown some good improvements if # of
2614 * CUs per SE is not a multiple of 4.
2616 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
2617 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
2620 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
2621 compute_resource_limits
);
2623 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2624 radeon_emit(cmd_buffer
->cs
,
2625 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2626 radeon_emit(cmd_buffer
->cs
,
2627 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2628 radeon_emit(cmd_buffer
->cs
,
2629 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2631 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2633 if (unlikely(cmd_buffer
->device
->trace_bo
))
2634 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2637 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2639 cmd_buffer
->state
.descriptors_dirty
|= cmd_buffer
->state
.valid_descriptors
;
2642 void radv_CmdBindPipeline(
2643 VkCommandBuffer commandBuffer
,
2644 VkPipelineBindPoint pipelineBindPoint
,
2645 VkPipeline _pipeline
)
2647 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2648 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2650 switch (pipelineBindPoint
) {
2651 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2652 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2654 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2656 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2657 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2659 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2660 if (cmd_buffer
->state
.pipeline
== pipeline
)
2662 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2664 cmd_buffer
->state
.pipeline
= pipeline
;
2668 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2669 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2671 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2673 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2674 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2675 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2676 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2678 if (radv_pipeline_has_tess(pipeline
))
2679 cmd_buffer
->tess_rings_needed
= true;
2681 if (radv_pipeline_has_gs(pipeline
)) {
2682 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2683 AC_UD_SCRATCH_RING_OFFSETS
);
2684 if (cmd_buffer
->ring_offsets_idx
== -1)
2685 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2686 else if (loc
->sgpr_idx
!= -1)
2687 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2691 assert(!"invalid bind point");
2696 void radv_CmdSetViewport(
2697 VkCommandBuffer commandBuffer
,
2698 uint32_t firstViewport
,
2699 uint32_t viewportCount
,
2700 const VkViewport
* pViewports
)
2702 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2703 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2705 assert(firstViewport
< MAX_VIEWPORTS
);
2706 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2708 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2709 pViewports
, viewportCount
* sizeof(*pViewports
));
2711 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2714 void radv_CmdSetScissor(
2715 VkCommandBuffer commandBuffer
,
2716 uint32_t firstScissor
,
2717 uint32_t scissorCount
,
2718 const VkRect2D
* pScissors
)
2720 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2721 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2723 assert(firstScissor
< MAX_SCISSORS
);
2724 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2726 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2727 pScissors
, scissorCount
* sizeof(*pScissors
));
2728 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2731 void radv_CmdSetLineWidth(
2732 VkCommandBuffer commandBuffer
,
2735 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2736 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2737 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2740 void radv_CmdSetDepthBias(
2741 VkCommandBuffer commandBuffer
,
2742 float depthBiasConstantFactor
,
2743 float depthBiasClamp
,
2744 float depthBiasSlopeFactor
)
2746 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2748 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2749 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2750 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2752 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2755 void radv_CmdSetBlendConstants(
2756 VkCommandBuffer commandBuffer
,
2757 const float blendConstants
[4])
2759 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2761 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2762 blendConstants
, sizeof(float) * 4);
2764 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2767 void radv_CmdSetDepthBounds(
2768 VkCommandBuffer commandBuffer
,
2769 float minDepthBounds
,
2770 float maxDepthBounds
)
2772 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2774 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2775 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2777 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2780 void radv_CmdSetStencilCompareMask(
2781 VkCommandBuffer commandBuffer
,
2782 VkStencilFaceFlags faceMask
,
2783 uint32_t compareMask
)
2785 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2787 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2788 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2789 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2790 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2792 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2795 void radv_CmdSetStencilWriteMask(
2796 VkCommandBuffer commandBuffer
,
2797 VkStencilFaceFlags faceMask
,
2800 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2802 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2803 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2804 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2805 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2807 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2810 void radv_CmdSetStencilReference(
2811 VkCommandBuffer commandBuffer
,
2812 VkStencilFaceFlags faceMask
,
2815 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2817 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2818 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2819 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2820 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2822 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2825 void radv_CmdExecuteCommands(
2826 VkCommandBuffer commandBuffer
,
2827 uint32_t commandBufferCount
,
2828 const VkCommandBuffer
* pCmdBuffers
)
2830 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2832 assert(commandBufferCount
> 0);
2834 /* Emit pending flushes on primary prior to executing secondary */
2835 si_emit_cache_flush(primary
);
2837 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2838 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2840 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2841 secondary
->scratch_size_needed
);
2842 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2843 secondary
->compute_scratch_size_needed
);
2845 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2846 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2847 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2848 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2849 if (secondary
->tess_rings_needed
)
2850 primary
->tess_rings_needed
= true;
2851 if (secondary
->sample_positions_needed
)
2852 primary
->sample_positions_needed
= true;
2854 if (secondary
->ring_offsets_idx
!= -1) {
2855 if (primary
->ring_offsets_idx
== -1)
2856 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2858 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2860 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2863 /* When the secondary command buffer is compute only we don't
2864 * need to re-emit the current graphics pipeline.
2866 if (secondary
->state
.emitted_pipeline
) {
2867 primary
->state
.emitted_pipeline
=
2868 secondary
->state
.emitted_pipeline
;
2871 /* When the secondary command buffer is graphics only we don't
2872 * need to re-emit the current compute pipeline.
2874 if (secondary
->state
.emitted_compute_pipeline
) {
2875 primary
->state
.emitted_compute_pipeline
=
2876 secondary
->state
.emitted_compute_pipeline
;
2879 /* Only re-emit the draw packets when needed. */
2880 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2881 primary
->state
.last_primitive_reset_en
=
2882 secondary
->state
.last_primitive_reset_en
;
2885 if (secondary
->state
.last_primitive_reset_index
) {
2886 primary
->state
.last_primitive_reset_index
=
2887 secondary
->state
.last_primitive_reset_index
;
2890 if (secondary
->state
.last_ia_multi_vgt_param
) {
2891 primary
->state
.last_ia_multi_vgt_param
=
2892 secondary
->state
.last_ia_multi_vgt_param
;
2895 if (secondary
->state
.last_index_type
!= -1) {
2896 primary
->state
.last_index_type
=
2897 secondary
->state
.last_index_type
;
2901 /* After executing commands from secondary buffers we have to dirty
2904 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2905 RADV_CMD_DIRTY_INDEX_BUFFER
|
2906 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2907 radv_mark_descriptor_sets_dirty(primary
);
2910 VkResult
radv_CreateCommandPool(
2912 const VkCommandPoolCreateInfo
* pCreateInfo
,
2913 const VkAllocationCallbacks
* pAllocator
,
2914 VkCommandPool
* pCmdPool
)
2916 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2917 struct radv_cmd_pool
*pool
;
2919 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2920 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2922 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2925 pool
->alloc
= *pAllocator
;
2927 pool
->alloc
= device
->alloc
;
2929 list_inithead(&pool
->cmd_buffers
);
2930 list_inithead(&pool
->free_cmd_buffers
);
2932 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2934 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2940 void radv_DestroyCommandPool(
2942 VkCommandPool commandPool
,
2943 const VkAllocationCallbacks
* pAllocator
)
2945 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2946 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2951 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2952 &pool
->cmd_buffers
, pool_link
) {
2953 radv_cmd_buffer_destroy(cmd_buffer
);
2956 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2957 &pool
->free_cmd_buffers
, pool_link
) {
2958 radv_cmd_buffer_destroy(cmd_buffer
);
2961 vk_free2(&device
->alloc
, pAllocator
, pool
);
2964 VkResult
radv_ResetCommandPool(
2966 VkCommandPool commandPool
,
2967 VkCommandPoolResetFlags flags
)
2969 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2972 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2973 &pool
->cmd_buffers
, pool_link
) {
2974 result
= radv_reset_cmd_buffer(cmd_buffer
);
2975 if (result
!= VK_SUCCESS
)
2982 void radv_TrimCommandPoolKHR(
2984 VkCommandPool commandPool
,
2985 VkCommandPoolTrimFlagsKHR flags
)
2987 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2992 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2993 &pool
->free_cmd_buffers
, pool_link
) {
2994 radv_cmd_buffer_destroy(cmd_buffer
);
2998 void radv_CmdBeginRenderPass(
2999 VkCommandBuffer commandBuffer
,
3000 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3001 VkSubpassContents contents
)
3003 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3004 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3005 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3007 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3008 cmd_buffer
->cs
, 2048);
3009 MAYBE_UNUSED VkResult result
;
3011 cmd_buffer
->state
.framebuffer
= framebuffer
;
3012 cmd_buffer
->state
.pass
= pass
;
3013 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3015 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3016 if (result
!= VK_SUCCESS
)
3019 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3020 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3022 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3025 void radv_CmdNextSubpass(
3026 VkCommandBuffer commandBuffer
,
3027 VkSubpassContents contents
)
3029 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3031 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3033 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3036 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3037 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3040 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3042 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3043 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3044 if (!pipeline
->shaders
[stage
])
3046 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3047 if (loc
->sgpr_idx
== -1)
3049 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3050 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3053 if (pipeline
->gs_copy_shader
) {
3054 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3055 if (loc
->sgpr_idx
!= -1) {
3056 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3057 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3063 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3064 uint32_t vertex_count
)
3066 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3067 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3068 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3069 S_0287F0_USE_OPAQUE(0));
3073 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3075 uint32_t index_count
)
3077 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
3078 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3079 radeon_emit(cmd_buffer
->cs
, index_va
);
3080 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3081 radeon_emit(cmd_buffer
->cs
, index_count
);
3082 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3086 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3088 uint32_t draw_count
,
3092 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3093 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3094 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3095 bool draw_id_enable
= radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.needs_draw_id
;
3096 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3099 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3100 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3101 PKT3_DRAW_INDIRECT
, 3, false));
3103 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3104 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3105 radeon_emit(cs
, di_src_sel
);
3107 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3108 PKT3_DRAW_INDIRECT_MULTI
,
3111 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3112 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3113 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3114 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3115 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3116 radeon_emit(cs
, draw_count
); /* count */
3117 radeon_emit(cs
, count_va
); /* count_addr */
3118 radeon_emit(cs
, count_va
>> 32);
3119 radeon_emit(cs
, stride
); /* stride */
3120 radeon_emit(cs
, di_src_sel
);
3124 struct radv_draw_info
{
3126 * Number of vertices.
3131 * Index of the first vertex.
3133 int32_t vertex_offset
;
3136 * First instance id.
3138 uint32_t first_instance
;
3141 * Number of instances.
3143 uint32_t instance_count
;
3146 * First index (indexed draws only).
3148 uint32_t first_index
;
3151 * Whether it's an indexed draw.
3156 * Indirect draw parameters resource.
3158 struct radv_buffer
*indirect
;
3159 uint64_t indirect_offset
;
3163 * Draw count parameters resource.
3165 struct radv_buffer
*count_buffer
;
3166 uint64_t count_buffer_offset
;
3170 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3171 const struct radv_draw_info
*info
)
3173 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3174 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3175 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3177 if (info
->indirect
) {
3178 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3179 uint64_t count_va
= 0;
3181 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3183 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3185 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3187 radeon_emit(cs
, va
);
3188 radeon_emit(cs
, va
>> 32);
3190 if (info
->count_buffer
) {
3191 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3192 count_va
+= info
->count_buffer
->offset
+
3193 info
->count_buffer_offset
;
3195 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
, 8);
3198 if (!state
->subpass
->view_mask
) {
3199 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3206 for_each_bit(i
, state
->subpass
->view_mask
) {
3207 radv_emit_view_index(cmd_buffer
, i
);
3209 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3217 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3218 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3219 state
->pipeline
->graphics
.vtx_emit_num
);
3220 radeon_emit(cs
, info
->vertex_offset
);
3221 radeon_emit(cs
, info
->first_instance
);
3222 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3225 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, state
->predicating
));
3226 radeon_emit(cs
, info
->instance_count
);
3228 if (info
->indexed
) {
3229 int index_size
= state
->index_type
? 4 : 2;
3232 index_va
= state
->index_va
;
3233 index_va
+= info
->first_index
* index_size
;
3235 if (!state
->subpass
->view_mask
) {
3236 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3241 for_each_bit(i
, state
->subpass
->view_mask
) {
3242 radv_emit_view_index(cmd_buffer
, i
);
3244 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3250 if (!state
->subpass
->view_mask
) {
3251 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3254 for_each_bit(i
, state
->subpass
->view_mask
) {
3255 radv_emit_view_index(cmd_buffer
, i
);
3257 radv_cs_emit_draw_packet(cmd_buffer
,
3266 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3267 const struct radv_draw_info
*info
)
3269 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3270 radv_emit_graphics_pipeline(cmd_buffer
);
3272 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3273 radv_emit_framebuffer_state(cmd_buffer
);
3275 if (info
->indexed
) {
3276 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3277 radv_emit_index_buffer(cmd_buffer
);
3279 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3280 * so the state must be re-emitted before the next indexed
3283 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3284 cmd_buffer
->state
.last_index_type
= -1;
3285 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3289 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3291 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3292 info
->instance_count
> 1, info
->indirect
,
3293 info
->indirect
? 0 : info
->count
);
3297 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3298 const struct radv_draw_info
*info
)
3300 bool pipeline_is_dirty
=
3301 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3302 cmd_buffer
->state
.pipeline
&&
3303 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3305 MAYBE_UNUSED
unsigned cdw_max
=
3306 radeon_check_space(cmd_buffer
->device
->ws
,
3307 cmd_buffer
->cs
, 4096);
3309 /* Use optimal packet order based on whether we need to sync the
3312 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3313 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3314 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3315 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3316 /* If we have to wait for idle, set all states first, so that
3317 * all SET packets are processed in parallel with previous draw
3318 * calls. Then upload descriptors, set shader pointers, and
3319 * draw, and prefetch at the end. This ensures that the time
3320 * the CUs are idle is very short. (there are only SET_SH
3321 * packets between the wait and the draw)
3323 radv_emit_all_graphics_states(cmd_buffer
, info
);
3324 si_emit_cache_flush(cmd_buffer
);
3325 /* <-- CUs are idle here --> */
3327 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3330 radv_emit_draw_packets(cmd_buffer
, info
);
3331 /* <-- CUs are busy here --> */
3333 /* Start prefetches after the draw has been started. Both will
3334 * run in parallel, but starting the draw first is more
3337 if (pipeline_is_dirty
) {
3338 radv_emit_prefetch(cmd_buffer
,
3339 cmd_buffer
->state
.pipeline
);
3342 /* If we don't wait for idle, start prefetches first, then set
3343 * states, and draw at the end.
3345 si_emit_cache_flush(cmd_buffer
);
3347 if (pipeline_is_dirty
) {
3348 radv_emit_prefetch(cmd_buffer
,
3349 cmd_buffer
->state
.pipeline
);
3352 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3355 radv_emit_all_graphics_states(cmd_buffer
, info
);
3356 radv_emit_draw_packets(cmd_buffer
, info
);
3359 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3360 radv_cmd_buffer_after_draw(cmd_buffer
);
3364 VkCommandBuffer commandBuffer
,
3365 uint32_t vertexCount
,
3366 uint32_t instanceCount
,
3367 uint32_t firstVertex
,
3368 uint32_t firstInstance
)
3370 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3371 struct radv_draw_info info
= {};
3373 info
.count
= vertexCount
;
3374 info
.instance_count
= instanceCount
;
3375 info
.first_instance
= firstInstance
;
3376 info
.vertex_offset
= firstVertex
;
3378 radv_draw(cmd_buffer
, &info
);
3381 void radv_CmdDrawIndexed(
3382 VkCommandBuffer commandBuffer
,
3383 uint32_t indexCount
,
3384 uint32_t instanceCount
,
3385 uint32_t firstIndex
,
3386 int32_t vertexOffset
,
3387 uint32_t firstInstance
)
3389 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3390 struct radv_draw_info info
= {};
3392 info
.indexed
= true;
3393 info
.count
= indexCount
;
3394 info
.instance_count
= instanceCount
;
3395 info
.first_index
= firstIndex
;
3396 info
.vertex_offset
= vertexOffset
;
3397 info
.first_instance
= firstInstance
;
3399 radv_draw(cmd_buffer
, &info
);
3402 void radv_CmdDrawIndirect(
3403 VkCommandBuffer commandBuffer
,
3405 VkDeviceSize offset
,
3409 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3410 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3411 struct radv_draw_info info
= {};
3413 info
.count
= drawCount
;
3414 info
.indirect
= buffer
;
3415 info
.indirect_offset
= offset
;
3416 info
.stride
= stride
;
3418 radv_draw(cmd_buffer
, &info
);
3421 void radv_CmdDrawIndexedIndirect(
3422 VkCommandBuffer commandBuffer
,
3424 VkDeviceSize offset
,
3428 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3429 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3430 struct radv_draw_info info
= {};
3432 info
.indexed
= true;
3433 info
.count
= drawCount
;
3434 info
.indirect
= buffer
;
3435 info
.indirect_offset
= offset
;
3436 info
.stride
= stride
;
3438 radv_draw(cmd_buffer
, &info
);
3441 void radv_CmdDrawIndirectCountAMD(
3442 VkCommandBuffer commandBuffer
,
3444 VkDeviceSize offset
,
3445 VkBuffer _countBuffer
,
3446 VkDeviceSize countBufferOffset
,
3447 uint32_t maxDrawCount
,
3450 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3451 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3452 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3453 struct radv_draw_info info
= {};
3455 info
.count
= maxDrawCount
;
3456 info
.indirect
= buffer
;
3457 info
.indirect_offset
= offset
;
3458 info
.count_buffer
= count_buffer
;
3459 info
.count_buffer_offset
= countBufferOffset
;
3460 info
.stride
= stride
;
3462 radv_draw(cmd_buffer
, &info
);
3465 void radv_CmdDrawIndexedIndirectCountAMD(
3466 VkCommandBuffer commandBuffer
,
3468 VkDeviceSize offset
,
3469 VkBuffer _countBuffer
,
3470 VkDeviceSize countBufferOffset
,
3471 uint32_t maxDrawCount
,
3474 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3475 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3476 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3477 struct radv_draw_info info
= {};
3479 info
.indexed
= true;
3480 info
.count
= maxDrawCount
;
3481 info
.indirect
= buffer
;
3482 info
.indirect_offset
= offset
;
3483 info
.count_buffer
= count_buffer
;
3484 info
.count_buffer_offset
= countBufferOffset
;
3485 info
.stride
= stride
;
3487 radv_draw(cmd_buffer
, &info
);
3490 struct radv_dispatch_info
{
3492 * Determine the layout of the grid (in block units) to be used.
3497 * Whether it's an unaligned compute dispatch.
3502 * Indirect compute parameters resource.
3504 struct radv_buffer
*indirect
;
3505 uint64_t indirect_offset
;
3509 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3510 const struct radv_dispatch_info
*info
)
3512 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3513 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3514 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3515 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3516 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3517 struct ac_userdata_info
*loc
;
3519 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3520 AC_UD_CS_GRID_SIZE
);
3522 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3524 if (info
->indirect
) {
3525 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3527 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3529 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3531 if (loc
->sgpr_idx
!= -1) {
3532 for (unsigned i
= 0; i
< 3; ++i
) {
3533 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3534 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3535 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3536 radeon_emit(cs
, (va
+ 4 * i
));
3537 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3538 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3539 + loc
->sgpr_idx
* 4) >> 2) + i
);
3544 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3545 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3546 PKT3_SHADER_TYPE_S(1));
3547 radeon_emit(cs
, va
);
3548 radeon_emit(cs
, va
>> 32);
3549 radeon_emit(cs
, dispatch_initiator
);
3551 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3552 PKT3_SHADER_TYPE_S(1));
3554 radeon_emit(cs
, va
);
3555 radeon_emit(cs
, va
>> 32);
3557 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3558 PKT3_SHADER_TYPE_S(1));
3560 radeon_emit(cs
, dispatch_initiator
);
3563 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3565 if (info
->unaligned
) {
3566 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3567 unsigned remainder
[3];
3569 /* If aligned, these should be an entire block size,
3572 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3573 align_u32_npot(blocks
[0], cs_block_size
[0]);
3574 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3575 align_u32_npot(blocks
[1], cs_block_size
[1]);
3576 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3577 align_u32_npot(blocks
[2], cs_block_size
[2]);
3579 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3580 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3581 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3583 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3585 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3586 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3588 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3589 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3591 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3592 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3594 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3597 if (loc
->sgpr_idx
!= -1) {
3598 assert(!loc
->indirect
);
3599 assert(loc
->num_sgprs
== 3);
3601 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3602 loc
->sgpr_idx
* 4, 3);
3603 radeon_emit(cs
, blocks
[0]);
3604 radeon_emit(cs
, blocks
[1]);
3605 radeon_emit(cs
, blocks
[2]);
3608 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3609 PKT3_SHADER_TYPE_S(1));
3610 radeon_emit(cs
, blocks
[0]);
3611 radeon_emit(cs
, blocks
[1]);
3612 radeon_emit(cs
, blocks
[2]);
3613 radeon_emit(cs
, dispatch_initiator
);
3616 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3620 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
3622 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3623 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3624 VK_SHADER_STAGE_COMPUTE_BIT
);
3628 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3629 const struct radv_dispatch_info
*info
)
3631 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3632 bool pipeline_is_dirty
= pipeline
&&
3633 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
3635 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3636 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3637 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3638 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3639 /* If we have to wait for idle, set all states first, so that
3640 * all SET packets are processed in parallel with previous draw
3641 * calls. Then upload descriptors, set shader pointers, and
3642 * dispatch, and prefetch at the end. This ensures that the
3643 * time the CUs are idle is very short. (there are only SET_SH
3644 * packets between the wait and the draw)
3646 radv_emit_compute_pipeline(cmd_buffer
);
3647 si_emit_cache_flush(cmd_buffer
);
3648 /* <-- CUs are idle here --> */
3650 radv_upload_compute_shader_descriptors(cmd_buffer
);
3652 radv_emit_dispatch_packets(cmd_buffer
, info
);
3653 /* <-- CUs are busy here --> */
3655 /* Start prefetches after the dispatch has been started. Both
3656 * will run in parallel, but starting the dispatch first is
3659 if (pipeline_is_dirty
) {
3660 radv_emit_shader_prefetch(cmd_buffer
,
3661 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3664 /* If we don't wait for idle, start prefetches first, then set
3665 * states, and dispatch at the end.
3667 si_emit_cache_flush(cmd_buffer
);
3669 if (pipeline_is_dirty
) {
3670 radv_emit_shader_prefetch(cmd_buffer
,
3671 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3674 radv_upload_compute_shader_descriptors(cmd_buffer
);
3676 radv_emit_compute_pipeline(cmd_buffer
);
3677 radv_emit_dispatch_packets(cmd_buffer
, info
);
3680 radv_cmd_buffer_after_draw(cmd_buffer
);
3683 void radv_CmdDispatch(
3684 VkCommandBuffer commandBuffer
,
3689 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3690 struct radv_dispatch_info info
= {};
3696 radv_dispatch(cmd_buffer
, &info
);
3699 void radv_CmdDispatchIndirect(
3700 VkCommandBuffer commandBuffer
,
3702 VkDeviceSize offset
)
3704 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3705 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3706 struct radv_dispatch_info info
= {};
3708 info
.indirect
= buffer
;
3709 info
.indirect_offset
= offset
;
3711 radv_dispatch(cmd_buffer
, &info
);
3714 void radv_unaligned_dispatch(
3715 struct radv_cmd_buffer
*cmd_buffer
,
3720 struct radv_dispatch_info info
= {};
3727 radv_dispatch(cmd_buffer
, &info
);
3730 void radv_CmdEndRenderPass(
3731 VkCommandBuffer commandBuffer
)
3733 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3735 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3737 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3739 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3740 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3741 radv_handle_subpass_image_transition(cmd_buffer
,
3742 (VkAttachmentReference
){i
, layout
});
3745 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3747 cmd_buffer
->state
.pass
= NULL
;
3748 cmd_buffer
->state
.subpass
= NULL
;
3749 cmd_buffer
->state
.attachments
= NULL
;
3750 cmd_buffer
->state
.framebuffer
= NULL
;
3754 * For HTILE we have the following interesting clear words:
3755 * 0x0000030f: Uncompressed.
3756 * 0xfffffff0: Clear depth to 1.0
3757 * 0x00000000: Clear depth to 0.0
3759 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3760 struct radv_image
*image
,
3761 const VkImageSubresourceRange
*range
,
3762 uint32_t clear_word
)
3764 assert(range
->baseMipLevel
== 0);
3765 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3766 unsigned layer_count
= radv_get_layerCount(image
, range
);
3767 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3768 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3769 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3770 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3772 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3773 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3775 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
3778 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3781 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3782 struct radv_image
*image
,
3783 VkImageLayout src_layout
,
3784 VkImageLayout dst_layout
,
3785 unsigned src_queue_mask
,
3786 unsigned dst_queue_mask
,
3787 const VkImageSubresourceRange
*range
,
3788 VkImageAspectFlags pending_clears
)
3790 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3791 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3792 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3793 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3794 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3795 /* The clear will initialize htile. */
3797 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3798 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3799 /* TODO: merge with the clear if applicable */
3800 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3801 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3802 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3803 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3804 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3805 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3806 VkImageSubresourceRange local_range
= *range
;
3807 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3808 local_range
.baseMipLevel
= 0;
3809 local_range
.levelCount
= 1;
3811 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3812 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3814 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3816 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3817 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3821 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3822 struct radv_image
*image
, uint32_t value
)
3824 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3826 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3827 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3829 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3830 image
->offset
+ image
->cmask
.offset
,
3831 image
->cmask
.size
, value
);
3833 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3836 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3837 struct radv_image
*image
,
3838 VkImageLayout src_layout
,
3839 VkImageLayout dst_layout
,
3840 unsigned src_queue_mask
,
3841 unsigned dst_queue_mask
,
3842 const VkImageSubresourceRange
*range
)
3844 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3845 if (image
->fmask
.size
)
3846 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3848 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3849 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3850 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3851 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3855 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3856 struct radv_image
*image
, uint32_t value
)
3858 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3860 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3861 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3863 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3864 image
->offset
+ image
->dcc_offset
,
3865 image
->surface
.dcc_size
, value
);
3867 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3868 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3871 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3872 struct radv_image
*image
,
3873 VkImageLayout src_layout
,
3874 VkImageLayout dst_layout
,
3875 unsigned src_queue_mask
,
3876 unsigned dst_queue_mask
,
3877 const VkImageSubresourceRange
*range
)
3879 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3880 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3881 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3882 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3883 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3887 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3888 struct radv_image
*image
,
3889 VkImageLayout src_layout
,
3890 VkImageLayout dst_layout
,
3891 uint32_t src_family
,
3892 uint32_t dst_family
,
3893 const VkImageSubresourceRange
*range
,
3894 VkImageAspectFlags pending_clears
)
3896 if (image
->exclusive
&& src_family
!= dst_family
) {
3897 /* This is an acquire or a release operation and there will be
3898 * a corresponding release/acquire. Do the transition in the
3899 * most flexible queue. */
3901 assert(src_family
== cmd_buffer
->queue_family_index
||
3902 dst_family
== cmd_buffer
->queue_family_index
);
3904 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3907 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3908 (src_family
== RADV_QUEUE_GENERAL
||
3909 dst_family
== RADV_QUEUE_GENERAL
))
3913 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3914 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3916 if (image
->surface
.htile_size
)
3917 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3918 dst_layout
, src_queue_mask
,
3919 dst_queue_mask
, range
,
3922 if (image
->cmask
.size
|| image
->fmask
.size
)
3923 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3924 dst_layout
, src_queue_mask
,
3925 dst_queue_mask
, range
);
3927 if (image
->surface
.dcc_size
)
3928 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3929 dst_layout
, src_queue_mask
,
3930 dst_queue_mask
, range
);
3933 void radv_CmdPipelineBarrier(
3934 VkCommandBuffer commandBuffer
,
3935 VkPipelineStageFlags srcStageMask
,
3936 VkPipelineStageFlags destStageMask
,
3938 uint32_t memoryBarrierCount
,
3939 const VkMemoryBarrier
* pMemoryBarriers
,
3940 uint32_t bufferMemoryBarrierCount
,
3941 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3942 uint32_t imageMemoryBarrierCount
,
3943 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3945 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3946 enum radv_cmd_flush_bits src_flush_bits
= 0;
3947 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3949 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3950 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3951 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3955 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3956 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3957 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3961 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3962 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3963 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3964 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3968 radv_stage_flush(cmd_buffer
, srcStageMask
);
3969 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3971 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3972 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3973 radv_handle_image_transition(cmd_buffer
, image
,
3974 pImageMemoryBarriers
[i
].oldLayout
,
3975 pImageMemoryBarriers
[i
].newLayout
,
3976 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3977 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3978 &pImageMemoryBarriers
[i
].subresourceRange
,
3982 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3986 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3987 struct radv_event
*event
,
3988 VkPipelineStageFlags stageMask
,
3991 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3992 uint64_t va
= radv_buffer_get_va(event
->bo
);
3994 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
3996 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3998 /* TODO: this is overkill. Probably should figure something out from
3999 * the stage mask. */
4001 si_cs_emit_write_event_eop(cs
,
4002 cmd_buffer
->state
.predicating
,
4003 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4005 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4008 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4011 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4013 VkPipelineStageFlags stageMask
)
4015 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4016 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4018 write_event(cmd_buffer
, event
, stageMask
, 1);
4021 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4023 VkPipelineStageFlags stageMask
)
4025 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4026 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4028 write_event(cmd_buffer
, event
, stageMask
, 0);
4031 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4032 uint32_t eventCount
,
4033 const VkEvent
* pEvents
,
4034 VkPipelineStageFlags srcStageMask
,
4035 VkPipelineStageFlags dstStageMask
,
4036 uint32_t memoryBarrierCount
,
4037 const VkMemoryBarrier
* pMemoryBarriers
,
4038 uint32_t bufferMemoryBarrierCount
,
4039 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4040 uint32_t imageMemoryBarrierCount
,
4041 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4043 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4044 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
4046 for (unsigned i
= 0; i
< eventCount
; ++i
) {
4047 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
4048 uint64_t va
= radv_buffer_get_va(event
->bo
);
4050 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
4052 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4054 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
4055 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4059 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4060 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4062 radv_handle_image_transition(cmd_buffer
, image
,
4063 pImageMemoryBarriers
[i
].oldLayout
,
4064 pImageMemoryBarriers
[i
].newLayout
,
4065 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4066 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4067 &pImageMemoryBarriers
[i
].subresourceRange
,
4071 /* TODO: figure out how to do memory barriers without waiting */
4072 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
4073 RADV_CMD_FLAG_INV_GLOBAL_L2
|
4074 RADV_CMD_FLAG_INV_VMEM_L1
|
4075 RADV_CMD_FLAG_INV_SMEM_L1
;