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radv: fixup tess eval shader when combined.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 if (stage == MESA_SHADER_VERTEX) {
497 if (pipeline->shaders[MESA_SHADER_VERTEX])
498 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
499 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
500 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
501 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
502 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
503 } else if (stage == MESA_SHADER_TESS_EVAL) {
504 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
505 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
506 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
507 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
508 }
509 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
510 }
511
512 static void
513 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
514 struct radv_pipeline *pipeline,
515 gl_shader_stage stage,
516 int idx, uint64_t va)
517 {
518 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
519 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
520 if (loc->sgpr_idx == -1)
521 return;
522 assert(loc->num_sgprs == 2);
523 assert(!loc->indirect);
524 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
525 radeon_emit(cmd_buffer->cs, va);
526 radeon_emit(cmd_buffer->cs, va >> 32);
527 }
528
529 static void
530 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 int num_samples = pipeline->graphics.ms.num_samples;
534 struct radv_multisample_state *ms = &pipeline->graphics.ms;
535 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
536
537 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
538 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
539 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
540
541 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
542 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
543
544 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
545 return;
546
547 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
548 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
549 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
550
551 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
552
553 /* GFX9: Flush DFSM when the AA mode changes. */
554 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
555 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
556 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
557 }
558 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
559 uint32_t offset;
560 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
561 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
562 if (loc->sgpr_idx == -1)
563 return;
564 assert(loc->num_sgprs == 1);
565 assert(!loc->indirect);
566 switch (num_samples) {
567 default:
568 offset = 0;
569 break;
570 case 2:
571 offset = 1;
572 break;
573 case 4:
574 offset = 3;
575 break;
576 case 8:
577 offset = 7;
578 break;
579 case 16:
580 offset = 15;
581 break;
582 }
583
584 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
585 cmd_buffer->sample_positions_needed = true;
586 }
587 }
588
589 static void
590 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline)
592 {
593 struct radv_raster_state *raster = &pipeline->graphics.raster;
594
595 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
596 raster->pa_cl_clip_cntl);
597 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
598 raster->spi_interp_control);
599 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
600 raster->pa_su_vtx_cntl);
601 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
602 raster->pa_su_sc_mode_cntl);
603 }
604
605 static inline void
606 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
607 unsigned size)
608 {
609 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
610 si_cp_dma_prefetch(cmd_buffer, va, size);
611 }
612
613 static void
614 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline,
616 struct radv_shader_variant *shader,
617 struct ac_vs_output_info *outinfo)
618 {
619 struct radeon_winsys *ws = cmd_buffer->device->ws;
620 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
621 unsigned export_count;
622
623 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
624 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
625
626 export_count = MAX2(1, outinfo->param_exports);
627 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
628 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
629
630 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
631 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
632 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
633 V_02870C_SPI_SHADER_4COMP :
634 V_02870C_SPI_SHADER_NONE) |
635 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
636 V_02870C_SPI_SHADER_4COMP :
637 V_02870C_SPI_SHADER_NONE) |
638 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
639 V_02870C_SPI_SHADER_4COMP :
640 V_02870C_SPI_SHADER_NONE));
641
642
643 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
644 radeon_emit(cmd_buffer->cs, va >> 8);
645 radeon_emit(cmd_buffer->cs, va >> 40);
646 radeon_emit(cmd_buffer->cs, shader->rsrc1);
647 radeon_emit(cmd_buffer->cs, shader->rsrc2);
648
649 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
650 S_028818_VTX_W0_FMT(1) |
651 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
652 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
653 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
654
655
656 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
657 pipeline->graphics.pa_cl_vs_out_cntl);
658
659 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
660 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
661 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
662 }
663
664 static void
665 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
666 struct radv_shader_variant *shader,
667 struct ac_es_output_info *outinfo)
668 {
669 struct radeon_winsys *ws = cmd_buffer->device->ws;
670 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
671
672 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
673 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
674
675 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
676 outinfo->esgs_itemsize / 4);
677 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
678 radeon_emit(cmd_buffer->cs, va >> 8);
679 radeon_emit(cmd_buffer->cs, va >> 40);
680 radeon_emit(cmd_buffer->cs, shader->rsrc1);
681 radeon_emit(cmd_buffer->cs, shader->rsrc2);
682 }
683
684 static void
685 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
686 struct radv_shader_variant *shader)
687 {
688 struct radeon_winsys *ws = cmd_buffer->device->ws;
689 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
690 uint32_t rsrc2 = shader->rsrc2;
691
692 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
693 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
694
695 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
696 radeon_emit(cmd_buffer->cs, va >> 8);
697 radeon_emit(cmd_buffer->cs, va >> 40);
698
699 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
700 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
701 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
702 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
703
704 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
705 radeon_emit(cmd_buffer->cs, shader->rsrc1);
706 radeon_emit(cmd_buffer->cs, rsrc2);
707 }
708
709 static void
710 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
711 struct radv_shader_variant *shader)
712 {
713 struct radeon_winsys *ws = cmd_buffer->device->ws;
714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
715
716 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
717 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
718
719 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
720 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
721 radeon_emit(cmd_buffer->cs, va >> 8);
722 radeon_emit(cmd_buffer->cs, va >> 40);
723
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
727 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
728 } else {
729 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
730 radeon_emit(cmd_buffer->cs, va >> 8);
731 radeon_emit(cmd_buffer->cs, va >> 40);
732 radeon_emit(cmd_buffer->cs, shader->rsrc1);
733 radeon_emit(cmd_buffer->cs, shader->rsrc2);
734 }
735 }
736
737 static void
738 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
739 struct radv_pipeline *pipeline)
740 {
741 struct radv_shader_variant *vs;
742
743 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
744
745 /* Skip shaders merged into HS/GS */
746 vs = pipeline->shaders[MESA_SHADER_VERTEX];
747 if (!vs)
748 return;
749
750 if (vs->info.vs.as_ls)
751 radv_emit_hw_ls(cmd_buffer, vs);
752 else if (vs->info.vs.as_es)
753 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
754 else
755 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
756 }
757
758
759 static void
760 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_pipeline *pipeline)
762 {
763 if (!radv_pipeline_has_tess(pipeline))
764 return;
765
766 struct radv_shader_variant *tes, *tcs;
767
768 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
769 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
770
771 if (tes->info.tes.as_es)
772 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
773 else
774 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
775
776 radv_emit_hw_hs(cmd_buffer, tcs);
777
778 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
779 pipeline->graphics.tess.tf_param);
780
781 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
782 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
783 pipeline->graphics.tess.ls_hs_config);
784 else
785 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
786 pipeline->graphics.tess.ls_hs_config);
787
788 struct ac_userdata_info *loc;
789
790 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
791 if (loc->sgpr_idx != -1) {
792 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
793 assert(loc->num_sgprs == 4);
794 assert(!loc->indirect);
795 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
796 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
797 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
798 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
799 pipeline->graphics.tess.num_tcs_input_cp << 26);
800 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
801 }
802
803 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
804 if (loc->sgpr_idx != -1) {
805 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
806 assert(loc->num_sgprs == 1);
807 assert(!loc->indirect);
808
809 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
810 pipeline->graphics.tess.offchip_layout);
811 }
812
813 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
814 if (loc->sgpr_idx != -1) {
815 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
816 assert(loc->num_sgprs == 1);
817 assert(!loc->indirect);
818
819 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
820 pipeline->graphics.tess.tcs_in_layout);
821 }
822 }
823
824 static void
825 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
826 struct radv_pipeline *pipeline)
827 {
828 struct radeon_winsys *ws = cmd_buffer->device->ws;
829 struct radv_shader_variant *gs;
830 uint64_t va;
831
832 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
833
834 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
835 if (!gs)
836 return;
837
838 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
839
840 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
841 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
842 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
843 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
844
845 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
848
849 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
850 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
851 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
852 radeon_emit(cmd_buffer->cs, 0);
853 radeon_emit(cmd_buffer->cs, 0);
854 radeon_emit(cmd_buffer->cs, 0);
855
856 uint32_t gs_num_invocations = gs->info.gs.invocations;
857 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
858 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
859 S_028B90_ENABLE(gs_num_invocations > 0));
860
861 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
862 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
863 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
864
865 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
866 radeon_emit(cmd_buffer->cs, va >> 8);
867 radeon_emit(cmd_buffer->cs, va >> 40);
868 radeon_emit(cmd_buffer->cs, gs->rsrc1);
869 radeon_emit(cmd_buffer->cs, gs->rsrc2);
870
871 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
872
873 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
874 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
875 if (loc->sgpr_idx != -1) {
876 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
877 uint32_t num_entries = 64;
878 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
879
880 if (is_vi)
881 num_entries *= stride;
882
883 stride = S_008F04_STRIDE(stride);
884 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
885 radeon_emit(cmd_buffer->cs, stride);
886 radeon_emit(cmd_buffer->cs, num_entries);
887 }
888 }
889
890 static void
891 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
892 struct radv_pipeline *pipeline)
893 {
894 struct radeon_winsys *ws = cmd_buffer->device->ws;
895 struct radv_shader_variant *ps;
896 uint64_t va;
897 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
898 struct radv_blend_state *blend = &pipeline->graphics.blend;
899 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
900
901 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
902 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
903 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
904 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
905
906 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
907 radeon_emit(cmd_buffer->cs, va >> 8);
908 radeon_emit(cmd_buffer->cs, va >> 40);
909 radeon_emit(cmd_buffer->cs, ps->rsrc1);
910 radeon_emit(cmd_buffer->cs, ps->rsrc2);
911
912 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
913 pipeline->graphics.db_shader_control);
914
915 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
916 ps->config.spi_ps_input_ena);
917
918 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
919 ps->config.spi_ps_input_addr);
920
921 if (ps->info.info.ps.force_persample)
922 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
923
924 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
925 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
926
927 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
930 pipeline->graphics.shader_z_format);
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
933
934 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
935 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
936
937 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
938 /* optimise this? */
939 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
940 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
941 }
942
943 if (pipeline->graphics.ps_input_cntl_num) {
944 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
945 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
946 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
947 }
948 }
949 }
950
951 static void
952 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
953 struct radv_pipeline *pipeline)
954 {
955 struct radeon_winsys_cs *cs = cmd_buffer->cs;
956
957 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
958 return;
959
960 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
961 pipeline->graphics.vtx_reuse_depth);
962 }
963
964 static void
965 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
968
969 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
970 return;
971
972 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
973 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
974 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
975 radv_update_multisample_state(cmd_buffer, pipeline);
976 radv_emit_vertex_shader(cmd_buffer, pipeline);
977 radv_emit_tess_shaders(cmd_buffer, pipeline);
978 radv_emit_geometry_shader(cmd_buffer, pipeline);
979 radv_emit_fragment_shader(cmd_buffer, pipeline);
980 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
981
982 cmd_buffer->scratch_size_needed =
983 MAX2(cmd_buffer->scratch_size_needed,
984 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
985
986 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
987 S_0286E8_WAVES(pipeline->max_waves) |
988 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
989
990 if (!cmd_buffer->state.emitted_pipeline ||
991 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
992 pipeline->graphics.can_use_guardband)
993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
994
995 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
996
997 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
998 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
999 } else {
1000 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1001 }
1002 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1003
1004 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1005
1006 cmd_buffer->state.emitted_pipeline = pipeline;
1007 }
1008
1009 static void
1010 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1011 {
1012 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1013 cmd_buffer->state.dynamic.viewport.viewports);
1014 }
1015
1016 static void
1017 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1018 {
1019 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1020
1021 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1022 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1023 si_emit_cache_flush(cmd_buffer);
1024 }
1025 si_write_scissors(cmd_buffer->cs, 0, count,
1026 cmd_buffer->state.dynamic.scissor.scissors,
1027 cmd_buffer->state.dynamic.viewport.viewports,
1028 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1029 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1030 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1031 }
1032
1033 static void
1034 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1035 {
1036 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1037
1038 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1039 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1040 }
1041
1042 static void
1043 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1044 {
1045 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1046
1047 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1048 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1049 }
1050
1051 static void
1052 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1053 {
1054 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1055
1056 radeon_set_context_reg_seq(cmd_buffer->cs,
1057 R_028430_DB_STENCILREFMASK, 2);
1058 radeon_emit(cmd_buffer->cs,
1059 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1060 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1061 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1062 S_028430_STENCILOPVAL(1));
1063 radeon_emit(cmd_buffer->cs,
1064 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1065 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1066 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1067 S_028434_STENCILOPVAL_BF(1));
1068 }
1069
1070 static void
1071 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1072 {
1073 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1074
1075 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1076 fui(d->depth_bounds.min));
1077 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1078 fui(d->depth_bounds.max));
1079 }
1080
1081 static void
1082 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1083 {
1084 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1085 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1086 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1087 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1088
1089 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1090 radeon_set_context_reg_seq(cmd_buffer->cs,
1091 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1092 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1093 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1094 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1095 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1096 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1097 }
1098 }
1099
1100 static void
1101 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1102 int index,
1103 struct radv_color_buffer_info *cb)
1104 {
1105 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1106
1107 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1108 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1109 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1110 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1111 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1112 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1115 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1116 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1117 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1118 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1119 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1120
1121 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1122 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1123 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1124
1125 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1126 cb->gfx9_epitch);
1127 } else {
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1129 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1130 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1131 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1132 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1133 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1134 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1135 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1136 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1137 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1138 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1139 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1140
1141 if (is_vi) { /* DCC BASE */
1142 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1143 }
1144 }
1145 }
1146
1147 static void
1148 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1149 struct radv_ds_buffer_info *ds,
1150 struct radv_image *image,
1151 VkImageLayout layout)
1152 {
1153 uint32_t db_z_info = ds->db_z_info;
1154 uint32_t db_stencil_info = ds->db_stencil_info;
1155
1156 if (!radv_layout_has_htile(image, layout,
1157 radv_image_queue_family_mask(image,
1158 cmd_buffer->queue_family_index,
1159 cmd_buffer->queue_family_index))) {
1160 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1161 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1162 }
1163
1164 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1165 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1166
1167
1168 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1169 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1170 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1171 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1172 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1173
1174 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1175 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1176 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1177 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1179 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1181 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1185
1186 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1187 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1188 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1189 } else {
1190 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1191
1192 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1193 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1194 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1195 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1196 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1197 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1198 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1199 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1200 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1201 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1202
1203 }
1204
1205 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1206 ds->pa_su_poly_offset_db_fmt_cntl);
1207 }
1208
1209 void
1210 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1211 struct radv_image *image,
1212 VkClearDepthStencilValue ds_clear_value,
1213 VkImageAspectFlags aspects)
1214 {
1215 uint64_t va = radv_buffer_get_va(image->bo);
1216 va += image->offset + image->clear_value_offset;
1217 unsigned reg_offset = 0, reg_count = 0;
1218
1219 if (!image->surface.htile_size || !aspects)
1220 return;
1221
1222 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1223 ++reg_count;
1224 } else {
1225 ++reg_offset;
1226 va += 4;
1227 }
1228 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1229 ++reg_count;
1230
1231 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1232
1233 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1234 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1235 S_370_WR_CONFIRM(1) |
1236 S_370_ENGINE_SEL(V_370_PFP));
1237 radeon_emit(cmd_buffer->cs, va);
1238 radeon_emit(cmd_buffer->cs, va >> 32);
1239 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1240 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1241 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1242 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1243
1244 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1245 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1246 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1247 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1248 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1249 }
1250
1251 static void
1252 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1253 struct radv_image *image)
1254 {
1255 uint64_t va = radv_buffer_get_va(image->bo);
1256 va += image->offset + image->clear_value_offset;
1257
1258 if (!image->surface.htile_size)
1259 return;
1260
1261 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1262
1263 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1264 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1265 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1266 COPY_DATA_COUNT_SEL);
1267 radeon_emit(cmd_buffer->cs, va);
1268 radeon_emit(cmd_buffer->cs, va >> 32);
1269 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1270 radeon_emit(cmd_buffer->cs, 0);
1271
1272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1273 radeon_emit(cmd_buffer->cs, 0);
1274 }
1275
1276 /*
1277 *with DCC some colors don't require CMASK elimiation before being
1278 * used as a texture. This sets a predicate value to determine if the
1279 * cmask eliminate is required.
1280 */
1281 void
1282 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1283 struct radv_image *image,
1284 bool value)
1285 {
1286 uint64_t pred_val = value;
1287 uint64_t va = radv_buffer_get_va(image->bo);
1288 va += image->offset + image->dcc_pred_offset;
1289
1290 if (!image->surface.dcc_size)
1291 return;
1292
1293 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1294
1295 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1296 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1297 S_370_WR_CONFIRM(1) |
1298 S_370_ENGINE_SEL(V_370_PFP));
1299 radeon_emit(cmd_buffer->cs, va);
1300 radeon_emit(cmd_buffer->cs, va >> 32);
1301 radeon_emit(cmd_buffer->cs, pred_val);
1302 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1303 }
1304
1305 void
1306 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1307 struct radv_image *image,
1308 int idx,
1309 uint32_t color_values[2])
1310 {
1311 uint64_t va = radv_buffer_get_va(image->bo);
1312 va += image->offset + image->clear_value_offset;
1313
1314 if (!image->cmask.size && !image->surface.dcc_size)
1315 return;
1316
1317 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1318
1319 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1320 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1321 S_370_WR_CONFIRM(1) |
1322 S_370_ENGINE_SEL(V_370_PFP));
1323 radeon_emit(cmd_buffer->cs, va);
1324 radeon_emit(cmd_buffer->cs, va >> 32);
1325 radeon_emit(cmd_buffer->cs, color_values[0]);
1326 radeon_emit(cmd_buffer->cs, color_values[1]);
1327
1328 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1329 radeon_emit(cmd_buffer->cs, color_values[0]);
1330 radeon_emit(cmd_buffer->cs, color_values[1]);
1331 }
1332
1333 static void
1334 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1335 struct radv_image *image,
1336 int idx)
1337 {
1338 uint64_t va = radv_buffer_get_va(image->bo);
1339 va += image->offset + image->clear_value_offset;
1340
1341 if (!image->cmask.size && !image->surface.dcc_size)
1342 return;
1343
1344 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1345 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1346
1347 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1348 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1349 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1350 COPY_DATA_COUNT_SEL);
1351 radeon_emit(cmd_buffer->cs, va);
1352 radeon_emit(cmd_buffer->cs, va >> 32);
1353 radeon_emit(cmd_buffer->cs, reg >> 2);
1354 radeon_emit(cmd_buffer->cs, 0);
1355
1356 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1357 radeon_emit(cmd_buffer->cs, 0);
1358 }
1359
1360 void
1361 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1362 {
1363 int i;
1364 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1365 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1366
1367 /* this may happen for inherited secondary recording */
1368 if (!framebuffer)
1369 return;
1370
1371 for (i = 0; i < 8; ++i) {
1372 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1373 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1374 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1375 continue;
1376 }
1377
1378 int idx = subpass->color_attachments[i].attachment;
1379 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1380
1381 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1382
1383 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1384 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1385
1386 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1387 }
1388
1389 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1390 int idx = subpass->depth_stencil_attachment.attachment;
1391 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1392 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1393 struct radv_image *image = att->attachment->image;
1394 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1395 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1396 cmd_buffer->queue_family_index,
1397 cmd_buffer->queue_family_index);
1398 /* We currently don't support writing decompressed HTILE */
1399 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1400 radv_layout_is_htile_compressed(image, layout, queue_mask));
1401
1402 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1403
1404 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1405 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1406 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1407 }
1408 radv_load_depth_clear_regs(cmd_buffer, image);
1409 } else {
1410 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1411 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1412 else
1413 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1414
1415 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1416 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1417 }
1418 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1419 S_028208_BR_X(framebuffer->width) |
1420 S_028208_BR_Y(framebuffer->height));
1421
1422 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1423 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1424 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1425 }
1426 }
1427
1428 static void
1429 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1430 {
1431 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1432
1433 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1434 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1435 2, cmd_buffer->state.index_type);
1436 } else {
1437 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1438 radeon_emit(cs, cmd_buffer->state.index_type);
1439 }
1440
1441 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1442 radeon_emit(cs, cmd_buffer->state.index_va);
1443 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1444
1445 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1446 radeon_emit(cs, cmd_buffer->state.max_index_count);
1447 }
1448
1449 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1450 {
1451 uint32_t db_count_control;
1452
1453 if(!cmd_buffer->state.active_occlusion_queries) {
1454 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1455 db_count_control = 0;
1456 } else {
1457 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1458 }
1459 } else {
1460 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1461 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1462 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1463 S_028004_ZPASS_ENABLE(1) |
1464 S_028004_SLICE_EVEN_ENABLE(1) |
1465 S_028004_SLICE_ODD_ENABLE(1);
1466 } else {
1467 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1468 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1469 }
1470 }
1471
1472 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1473 }
1474
1475 static void
1476 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1477 {
1478 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1479 return;
1480
1481 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1482 radv_emit_viewport(cmd_buffer);
1483
1484 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1485 radv_emit_scissor(cmd_buffer);
1486
1487 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1488 radv_emit_line_width(cmd_buffer);
1489
1490 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1491 radv_emit_blend_constants(cmd_buffer);
1492
1493 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1494 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1495 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1496 radv_emit_stencil(cmd_buffer);
1497
1498 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1499 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1500 radv_emit_depth_bounds(cmd_buffer);
1501
1502 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1503 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1504 radv_emit_depth_biais(cmd_buffer);
1505 }
1506
1507 static void
1508 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1509 struct radv_pipeline *pipeline,
1510 int idx,
1511 uint64_t va,
1512 gl_shader_stage stage)
1513 {
1514 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1515 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1516
1517 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1518 return;
1519
1520 assert(!desc_set_loc->indirect);
1521 assert(desc_set_loc->num_sgprs == 2);
1522 radeon_set_sh_reg_seq(cmd_buffer->cs,
1523 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1524 radeon_emit(cmd_buffer->cs, va);
1525 radeon_emit(cmd_buffer->cs, va >> 32);
1526 }
1527
1528 static void
1529 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1530 VkShaderStageFlags stages,
1531 struct radv_descriptor_set *set,
1532 unsigned idx)
1533 {
1534 if (cmd_buffer->state.pipeline) {
1535 radv_foreach_stage(stage, stages) {
1536 if (cmd_buffer->state.pipeline->shaders[stage])
1537 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1538 idx, set->va,
1539 stage);
1540 }
1541 }
1542
1543 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1544 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1545 idx, set->va,
1546 MESA_SHADER_COMPUTE);
1547 }
1548
1549 static void
1550 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1551 {
1552 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1553 unsigned bo_offset;
1554
1555 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1556 set->mapped_ptr,
1557 &bo_offset))
1558 return;
1559
1560 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1561 set->va += bo_offset;
1562 }
1563
1564 static void
1565 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1566 {
1567 uint32_t size = MAX_SETS * 2 * 4;
1568 uint32_t offset;
1569 void *ptr;
1570
1571 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1572 256, &offset, &ptr))
1573 return;
1574
1575 for (unsigned i = 0; i < MAX_SETS; i++) {
1576 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1577 uint64_t set_va = 0;
1578 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1579 if (set)
1580 set_va = set->va;
1581 uptr[0] = set_va & 0xffffffff;
1582 uptr[1] = set_va >> 32;
1583 }
1584
1585 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1586 va += offset;
1587
1588 if (cmd_buffer->state.pipeline) {
1589 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1590 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1591 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1592
1593 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1594 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1595 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1596
1597 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1598 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1599 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1600
1601 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1602 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1603 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1604
1605 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1606 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1607 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1608 }
1609
1610 if (cmd_buffer->state.compute_pipeline)
1611 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1612 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1613 }
1614
1615 static void
1616 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1617 VkShaderStageFlags stages)
1618 {
1619 unsigned i;
1620
1621 if (!cmd_buffer->state.descriptors_dirty)
1622 return;
1623
1624 if (cmd_buffer->state.push_descriptors_dirty)
1625 radv_flush_push_descriptors(cmd_buffer);
1626
1627 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1628 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1629 radv_flush_indirect_descriptor_sets(cmd_buffer);
1630 }
1631
1632 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1633 cmd_buffer->cs,
1634 MAX_SETS * MESA_SHADER_STAGES * 4);
1635
1636 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1637 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1638 if (!set)
1639 continue;
1640
1641 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1642 }
1643 cmd_buffer->state.descriptors_dirty = 0;
1644 cmd_buffer->state.push_descriptors_dirty = false;
1645
1646 radv_save_descriptors(cmd_buffer);
1647
1648 assert(cmd_buffer->cs->cdw <= cdw_max);
1649 }
1650
1651 static void
1652 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1653 struct radv_pipeline *pipeline,
1654 VkShaderStageFlags stages)
1655 {
1656 struct radv_pipeline_layout *layout = pipeline->layout;
1657 unsigned offset;
1658 void *ptr;
1659 uint64_t va;
1660
1661 stages &= cmd_buffer->push_constant_stages;
1662 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1663 return;
1664
1665 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1666 16 * layout->dynamic_offset_count,
1667 256, &offset, &ptr))
1668 return;
1669
1670 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1671 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1672 16 * layout->dynamic_offset_count);
1673
1674 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1675 va += offset;
1676
1677 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1678 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1679
1680 radv_foreach_stage(stage, stages) {
1681 if (pipeline->shaders[stage]) {
1682 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1683 AC_UD_PUSH_CONSTANTS, va);
1684 }
1685 }
1686
1687 cmd_buffer->push_constant_stages &= ~stages;
1688 assert(cmd_buffer->cs->cdw <= cdw_max);
1689 }
1690
1691 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1692 bool indexed_draw)
1693 {
1694 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1695
1696 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1697 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1699 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1700 primitive_reset_en);
1701 } else {
1702 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1703 primitive_reset_en);
1704 }
1705 }
1706
1707 if (primitive_reset_en) {
1708 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1709
1710 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1711 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1712 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1713 primitive_reset_index);
1714 }
1715 }
1716 }
1717
1718 static bool
1719 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1720 {
1721 struct radv_device *device = cmd_buffer->device;
1722
1723 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1724 cmd_buffer->state.pipeline->vertex_elements.count &&
1725 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1726 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1727 unsigned vb_offset;
1728 void *vb_ptr;
1729 uint32_t i = 0;
1730 uint32_t count = velems->count;
1731 uint64_t va;
1732
1733 /* allocate some descriptor state for vertex buffers */
1734 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1735 &vb_offset, &vb_ptr))
1736 return false;
1737
1738 for (i = 0; i < count; i++) {
1739 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1740 uint32_t offset;
1741 int vb = velems->binding[i];
1742 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1743 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1744
1745 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1746 va = radv_buffer_get_va(buffer->bo);
1747
1748 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1749 va += offset + buffer->offset;
1750 desc[0] = va;
1751 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1752 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1753 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1754 else
1755 desc[2] = buffer->size - offset;
1756 desc[3] = velems->rsrc_word3[i];
1757 }
1758
1759 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1760 va += vb_offset;
1761
1762 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1763 AC_UD_VS_VERTEX_BUFFERS, va);
1764 }
1765 cmd_buffer->state.vb_dirty = false;
1766
1767 return true;
1768 }
1769
1770 static void
1771 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1772 bool indexed_draw, bool instanced_draw,
1773 bool indirect_draw,
1774 uint32_t draw_vertex_count)
1775 {
1776 uint32_t ia_multi_vgt_param;
1777
1778 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1779 cmd_buffer->cs, 4096);
1780
1781 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1782 return;
1783
1784 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1785 radv_emit_graphics_pipeline(cmd_buffer);
1786
1787 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1788 radv_emit_framebuffer_state(cmd_buffer);
1789
1790 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
1791 radv_emit_index_buffer(cmd_buffer);
1792
1793 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1794 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1795 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1796 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1797 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1798 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1799 else
1800 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1801 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1802 }
1803
1804 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1805
1806 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1807
1808 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1809 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1810 VK_SHADER_STAGE_ALL_GRAPHICS);
1811
1812 assert(cmd_buffer->cs->cdw <= cdw_max);
1813
1814 si_emit_cache_flush(cmd_buffer);
1815
1816 cmd_buffer->state.dirty = 0;
1817 }
1818
1819 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1820 VkPipelineStageFlags src_stage_mask)
1821 {
1822 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1823 VK_PIPELINE_STAGE_TRANSFER_BIT |
1824 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1825 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1826 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1827 }
1828
1829 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1830 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1831 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1832 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1833 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1834 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1835 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1836 VK_PIPELINE_STAGE_TRANSFER_BIT |
1837 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1838 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1839 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1840 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1841 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1842 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1843 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1844 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1845 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1846 }
1847 }
1848
1849 static enum radv_cmd_flush_bits
1850 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1851 VkAccessFlags src_flags)
1852 {
1853 enum radv_cmd_flush_bits flush_bits = 0;
1854 uint32_t b;
1855 for_each_bit(b, src_flags) {
1856 switch ((VkAccessFlagBits)(1 << b)) {
1857 case VK_ACCESS_SHADER_WRITE_BIT:
1858 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1859 break;
1860 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1861 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1862 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1863 break;
1864 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1865 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1866 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1867 break;
1868 case VK_ACCESS_TRANSFER_WRITE_BIT:
1869 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1870 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1871 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1872 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1873 RADV_CMD_FLAG_INV_GLOBAL_L2;
1874 break;
1875 default:
1876 break;
1877 }
1878 }
1879 return flush_bits;
1880 }
1881
1882 static enum radv_cmd_flush_bits
1883 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1884 VkAccessFlags dst_flags,
1885 struct radv_image *image)
1886 {
1887 enum radv_cmd_flush_bits flush_bits = 0;
1888 uint32_t b;
1889 for_each_bit(b, dst_flags) {
1890 switch ((VkAccessFlagBits)(1 << b)) {
1891 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1892 case VK_ACCESS_INDEX_READ_BIT:
1893 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1894 break;
1895 case VK_ACCESS_UNIFORM_READ_BIT:
1896 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1897 break;
1898 case VK_ACCESS_SHADER_READ_BIT:
1899 case VK_ACCESS_TRANSFER_READ_BIT:
1900 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1901 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1902 RADV_CMD_FLAG_INV_GLOBAL_L2;
1903 break;
1904 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1905 /* TODO: change to image && when the image gets passed
1906 * through from the subpass. */
1907 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1908 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1909 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1910 break;
1911 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1912 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1913 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1914 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1915 break;
1916 default:
1917 break;
1918 }
1919 }
1920 return flush_bits;
1921 }
1922
1923 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1924 {
1925 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1926 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1927 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1928 NULL);
1929 }
1930
1931 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1932 VkAttachmentReference att)
1933 {
1934 unsigned idx = att.attachment;
1935 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1936 VkImageSubresourceRange range;
1937 range.aspectMask = 0;
1938 range.baseMipLevel = view->base_mip;
1939 range.levelCount = 1;
1940 range.baseArrayLayer = view->base_layer;
1941 range.layerCount = cmd_buffer->state.framebuffer->layers;
1942
1943 radv_handle_image_transition(cmd_buffer,
1944 view->image,
1945 cmd_buffer->state.attachments[idx].current_layout,
1946 att.layout, 0, 0, &range,
1947 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1948
1949 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1950
1951
1952 }
1953
1954 void
1955 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1956 const struct radv_subpass *subpass, bool transitions)
1957 {
1958 if (transitions) {
1959 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1960
1961 for (unsigned i = 0; i < subpass->color_count; ++i) {
1962 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1963 radv_handle_subpass_image_transition(cmd_buffer,
1964 subpass->color_attachments[i]);
1965 }
1966
1967 for (unsigned i = 0; i < subpass->input_count; ++i) {
1968 radv_handle_subpass_image_transition(cmd_buffer,
1969 subpass->input_attachments[i]);
1970 }
1971
1972 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1973 radv_handle_subpass_image_transition(cmd_buffer,
1974 subpass->depth_stencil_attachment);
1975 }
1976 }
1977
1978 cmd_buffer->state.subpass = subpass;
1979
1980 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1981 }
1982
1983 static VkResult
1984 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_render_pass *pass,
1986 const VkRenderPassBeginInfo *info)
1987 {
1988 struct radv_cmd_state *state = &cmd_buffer->state;
1989
1990 if (pass->attachment_count == 0) {
1991 state->attachments = NULL;
1992 return VK_SUCCESS;
1993 }
1994
1995 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1996 pass->attachment_count *
1997 sizeof(state->attachments[0]),
1998 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1999 if (state->attachments == NULL) {
2000 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2001 return cmd_buffer->record_result;
2002 }
2003
2004 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2005 struct radv_render_pass_attachment *att = &pass->attachments[i];
2006 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2007 VkImageAspectFlags clear_aspects = 0;
2008
2009 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2010 /* color attachment */
2011 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2012 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2013 }
2014 } else {
2015 /* depthstencil attachment */
2016 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2017 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2018 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2019 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2020 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2021 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2022 }
2023 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2024 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2025 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2026 }
2027 }
2028
2029 state->attachments[i].pending_clear_aspects = clear_aspects;
2030 state->attachments[i].cleared_views = 0;
2031 if (clear_aspects && info) {
2032 assert(info->clearValueCount > i);
2033 state->attachments[i].clear_value = info->pClearValues[i];
2034 }
2035
2036 state->attachments[i].current_layout = att->initial_layout;
2037 }
2038
2039 return VK_SUCCESS;
2040 }
2041
2042 VkResult radv_AllocateCommandBuffers(
2043 VkDevice _device,
2044 const VkCommandBufferAllocateInfo *pAllocateInfo,
2045 VkCommandBuffer *pCommandBuffers)
2046 {
2047 RADV_FROM_HANDLE(radv_device, device, _device);
2048 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2049
2050 VkResult result = VK_SUCCESS;
2051 uint32_t i;
2052
2053 memset(pCommandBuffers, 0,
2054 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2055
2056 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2057
2058 if (!list_empty(&pool->free_cmd_buffers)) {
2059 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2060
2061 list_del(&cmd_buffer->pool_link);
2062 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2063
2064 result = radv_reset_cmd_buffer(cmd_buffer);
2065 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2066 cmd_buffer->level = pAllocateInfo->level;
2067
2068 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2069 } else {
2070 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2071 &pCommandBuffers[i]);
2072 }
2073 if (result != VK_SUCCESS)
2074 break;
2075 }
2076
2077 if (result != VK_SUCCESS)
2078 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2079 i, pCommandBuffers);
2080
2081 return result;
2082 }
2083
2084 void radv_FreeCommandBuffers(
2085 VkDevice device,
2086 VkCommandPool commandPool,
2087 uint32_t commandBufferCount,
2088 const VkCommandBuffer *pCommandBuffers)
2089 {
2090 for (uint32_t i = 0; i < commandBufferCount; i++) {
2091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2092
2093 if (cmd_buffer) {
2094 if (cmd_buffer->pool) {
2095 list_del(&cmd_buffer->pool_link);
2096 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2097 } else
2098 radv_cmd_buffer_destroy(cmd_buffer);
2099
2100 }
2101 }
2102 }
2103
2104 VkResult radv_ResetCommandBuffer(
2105 VkCommandBuffer commandBuffer,
2106 VkCommandBufferResetFlags flags)
2107 {
2108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2109 return radv_reset_cmd_buffer(cmd_buffer);
2110 }
2111
2112 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2113 {
2114 struct radv_device *device = cmd_buffer->device;
2115 if (device->gfx_init) {
2116 uint64_t va = radv_buffer_get_va(device->gfx_init);
2117 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2118 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2119 radeon_emit(cmd_buffer->cs, va);
2120 radeon_emit(cmd_buffer->cs, va >> 32);
2121 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2122 } else
2123 si_init_config(cmd_buffer);
2124 }
2125
2126 VkResult radv_BeginCommandBuffer(
2127 VkCommandBuffer commandBuffer,
2128 const VkCommandBufferBeginInfo *pBeginInfo)
2129 {
2130 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2131 VkResult result;
2132
2133 result = radv_reset_cmd_buffer(cmd_buffer);
2134 if (result != VK_SUCCESS)
2135 return result;
2136
2137 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2138 cmd_buffer->state.last_primitive_reset_en = -1;
2139 cmd_buffer->usage_flags = pBeginInfo->flags;
2140
2141 /* setup initial configuration into command buffer */
2142 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2143 switch (cmd_buffer->queue_family_index) {
2144 case RADV_QUEUE_GENERAL:
2145 emit_gfx_buffer_state(cmd_buffer);
2146 radv_set_db_count_control(cmd_buffer);
2147 break;
2148 case RADV_QUEUE_COMPUTE:
2149 si_init_compute(cmd_buffer);
2150 break;
2151 case RADV_QUEUE_TRANSFER:
2152 default:
2153 break;
2154 }
2155 }
2156
2157 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2158 assert(pBeginInfo->pInheritanceInfo);
2159 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2160 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2161
2162 struct radv_subpass *subpass =
2163 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2164
2165 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2166 if (result != VK_SUCCESS)
2167 return result;
2168
2169 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2170 }
2171
2172 radv_cmd_buffer_trace_emit(cmd_buffer);
2173 return result;
2174 }
2175
2176 void radv_CmdBindVertexBuffers(
2177 VkCommandBuffer commandBuffer,
2178 uint32_t firstBinding,
2179 uint32_t bindingCount,
2180 const VkBuffer* pBuffers,
2181 const VkDeviceSize* pOffsets)
2182 {
2183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2184 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2185
2186 /* We have to defer setting up vertex buffer since we need the buffer
2187 * stride from the pipeline. */
2188
2189 assert(firstBinding + bindingCount <= MAX_VBS);
2190 for (uint32_t i = 0; i < bindingCount; i++) {
2191 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2192 vb[firstBinding + i].offset = pOffsets[i];
2193 }
2194
2195 cmd_buffer->state.vb_dirty = true;
2196 }
2197
2198 void radv_CmdBindIndexBuffer(
2199 VkCommandBuffer commandBuffer,
2200 VkBuffer buffer,
2201 VkDeviceSize offset,
2202 VkIndexType indexType)
2203 {
2204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2205 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2206
2207 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2208 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2209 cmd_buffer->state.index_va += index_buffer->offset + offset;
2210
2211 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2212 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2213 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2214 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2215 }
2216
2217
2218 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2219 struct radv_descriptor_set *set,
2220 unsigned idx)
2221 {
2222 struct radeon_winsys *ws = cmd_buffer->device->ws;
2223
2224 cmd_buffer->state.descriptors[idx] = set;
2225 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2226 if (!set)
2227 return;
2228
2229 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2230
2231 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2232 if (set->descriptors[j])
2233 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2234
2235 if(set->bo)
2236 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2237 }
2238
2239 void radv_CmdBindDescriptorSets(
2240 VkCommandBuffer commandBuffer,
2241 VkPipelineBindPoint pipelineBindPoint,
2242 VkPipelineLayout _layout,
2243 uint32_t firstSet,
2244 uint32_t descriptorSetCount,
2245 const VkDescriptorSet* pDescriptorSets,
2246 uint32_t dynamicOffsetCount,
2247 const uint32_t* pDynamicOffsets)
2248 {
2249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2250 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2251 unsigned dyn_idx = 0;
2252
2253 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2254 unsigned idx = i + firstSet;
2255 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2256 radv_bind_descriptor_set(cmd_buffer, set, idx);
2257
2258 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2259 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2260 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2261 assert(dyn_idx < dynamicOffsetCount);
2262
2263 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2264 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2265 dst[0] = va;
2266 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2267 dst[2] = range->size;
2268 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2269 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2270 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2271 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2272 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2273 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2274 cmd_buffer->push_constant_stages |=
2275 set->layout->dynamic_shader_stages;
2276 }
2277 }
2278 }
2279
2280 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2281 struct radv_descriptor_set *set,
2282 struct radv_descriptor_set_layout *layout)
2283 {
2284 set->size = layout->size;
2285 set->layout = layout;
2286
2287 if (cmd_buffer->push_descriptors.capacity < set->size) {
2288 size_t new_size = MAX2(set->size, 1024);
2289 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2290 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2291
2292 free(set->mapped_ptr);
2293 set->mapped_ptr = malloc(new_size);
2294
2295 if (!set->mapped_ptr) {
2296 cmd_buffer->push_descriptors.capacity = 0;
2297 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2298 return false;
2299 }
2300
2301 cmd_buffer->push_descriptors.capacity = new_size;
2302 }
2303
2304 return true;
2305 }
2306
2307 void radv_meta_push_descriptor_set(
2308 struct radv_cmd_buffer* cmd_buffer,
2309 VkPipelineBindPoint pipelineBindPoint,
2310 VkPipelineLayout _layout,
2311 uint32_t set,
2312 uint32_t descriptorWriteCount,
2313 const VkWriteDescriptorSet* pDescriptorWrites)
2314 {
2315 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2316 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2317 unsigned bo_offset;
2318
2319 assert(set == 0);
2320 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2321
2322 push_set->size = layout->set[set].layout->size;
2323 push_set->layout = layout->set[set].layout;
2324
2325 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2326 &bo_offset,
2327 (void**) &push_set->mapped_ptr))
2328 return;
2329
2330 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2331 push_set->va += bo_offset;
2332
2333 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2334 radv_descriptor_set_to_handle(push_set),
2335 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2336
2337 cmd_buffer->state.descriptors[set] = push_set;
2338 cmd_buffer->state.descriptors_dirty |= (1u << set);
2339 }
2340
2341 void radv_CmdPushDescriptorSetKHR(
2342 VkCommandBuffer commandBuffer,
2343 VkPipelineBindPoint pipelineBindPoint,
2344 VkPipelineLayout _layout,
2345 uint32_t set,
2346 uint32_t descriptorWriteCount,
2347 const VkWriteDescriptorSet* pDescriptorWrites)
2348 {
2349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2350 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2351 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2352
2353 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2354
2355 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2356 return;
2357
2358 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2359 radv_descriptor_set_to_handle(push_set),
2360 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2361
2362 cmd_buffer->state.descriptors[set] = push_set;
2363 cmd_buffer->state.descriptors_dirty |= (1u << set);
2364 cmd_buffer->state.push_descriptors_dirty = true;
2365 }
2366
2367 void radv_CmdPushDescriptorSetWithTemplateKHR(
2368 VkCommandBuffer commandBuffer,
2369 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2370 VkPipelineLayout _layout,
2371 uint32_t set,
2372 const void* pData)
2373 {
2374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2375 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2376 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2377
2378 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2379
2380 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2381 return;
2382
2383 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2384 descriptorUpdateTemplate, pData);
2385
2386 cmd_buffer->state.descriptors[set] = push_set;
2387 cmd_buffer->state.descriptors_dirty |= (1u << set);
2388 cmd_buffer->state.push_descriptors_dirty = true;
2389 }
2390
2391 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2392 VkPipelineLayout layout,
2393 VkShaderStageFlags stageFlags,
2394 uint32_t offset,
2395 uint32_t size,
2396 const void* pValues)
2397 {
2398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2400 cmd_buffer->push_constant_stages |= stageFlags;
2401 }
2402
2403 VkResult radv_EndCommandBuffer(
2404 VkCommandBuffer commandBuffer)
2405 {
2406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2407
2408 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2409 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2410 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2411 si_emit_cache_flush(cmd_buffer);
2412 }
2413
2414 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2415 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2416
2417 return cmd_buffer->record_result;
2418 }
2419
2420 static void
2421 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2422 {
2423 struct radeon_winsys *ws = cmd_buffer->device->ws;
2424 struct radv_shader_variant *compute_shader;
2425 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2426 uint64_t va;
2427
2428 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2429 return;
2430
2431 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2432
2433 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2434 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2435
2436 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2437 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2438
2439 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2440 cmd_buffer->cs, 16);
2441
2442 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2443 radeon_emit(cmd_buffer->cs, va >> 8);
2444 radeon_emit(cmd_buffer->cs, va >> 40);
2445
2446 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2447 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2448 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2449
2450
2451 cmd_buffer->compute_scratch_size_needed =
2452 MAX2(cmd_buffer->compute_scratch_size_needed,
2453 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2454
2455 /* change these once we have scratch support */
2456 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2457 S_00B860_WAVES(pipeline->max_waves) |
2458 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2459
2460 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2461 radeon_emit(cmd_buffer->cs,
2462 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2463 radeon_emit(cmd_buffer->cs,
2464 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2465 radeon_emit(cmd_buffer->cs,
2466 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2467
2468 assert(cmd_buffer->cs->cdw <= cdw_max);
2469 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2470 }
2471
2472 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2473 {
2474 for (unsigned i = 0; i < MAX_SETS; i++) {
2475 if (cmd_buffer->state.descriptors[i])
2476 cmd_buffer->state.descriptors_dirty |= (1u << i);
2477 }
2478 }
2479
2480 void radv_CmdBindPipeline(
2481 VkCommandBuffer commandBuffer,
2482 VkPipelineBindPoint pipelineBindPoint,
2483 VkPipeline _pipeline)
2484 {
2485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2486 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2487
2488 switch (pipelineBindPoint) {
2489 case VK_PIPELINE_BIND_POINT_COMPUTE:
2490 if (cmd_buffer->state.compute_pipeline == pipeline)
2491 return;
2492 radv_mark_descriptor_sets_dirty(cmd_buffer);
2493
2494 cmd_buffer->state.compute_pipeline = pipeline;
2495 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2496 break;
2497 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2498 if (cmd_buffer->state.pipeline == pipeline)
2499 return;
2500 radv_mark_descriptor_sets_dirty(cmd_buffer);
2501
2502 cmd_buffer->state.pipeline = pipeline;
2503 if (!pipeline)
2504 break;
2505
2506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2507 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2508
2509 /* Apply the dynamic state from the pipeline */
2510 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2511 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2512 &pipeline->dynamic_state,
2513 pipeline->dynamic_state_mask);
2514
2515 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2516 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2517 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2518 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2519
2520 if (radv_pipeline_has_tess(pipeline))
2521 cmd_buffer->tess_rings_needed = true;
2522
2523 if (radv_pipeline_has_gs(pipeline)) {
2524 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2525 AC_UD_SCRATCH_RING_OFFSETS);
2526 if (cmd_buffer->ring_offsets_idx == -1)
2527 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2528 else if (loc->sgpr_idx != -1)
2529 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2530 }
2531 break;
2532 default:
2533 assert(!"invalid bind point");
2534 break;
2535 }
2536 }
2537
2538 void radv_CmdSetViewport(
2539 VkCommandBuffer commandBuffer,
2540 uint32_t firstViewport,
2541 uint32_t viewportCount,
2542 const VkViewport* pViewports)
2543 {
2544 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2545 const uint32_t total_count = firstViewport + viewportCount;
2546
2547 assert(firstViewport < MAX_VIEWPORTS);
2548 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2549
2550 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2551 pViewports, viewportCount * sizeof(*pViewports));
2552
2553 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2554 }
2555
2556 void radv_CmdSetScissor(
2557 VkCommandBuffer commandBuffer,
2558 uint32_t firstScissor,
2559 uint32_t scissorCount,
2560 const VkRect2D* pScissors)
2561 {
2562 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2563 const uint32_t total_count = firstScissor + scissorCount;
2564
2565 assert(firstScissor < MAX_SCISSORS);
2566 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2567
2568 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2569 pScissors, scissorCount * sizeof(*pScissors));
2570 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2571 }
2572
2573 void radv_CmdSetLineWidth(
2574 VkCommandBuffer commandBuffer,
2575 float lineWidth)
2576 {
2577 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2578 cmd_buffer->state.dynamic.line_width = lineWidth;
2579 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2580 }
2581
2582 void radv_CmdSetDepthBias(
2583 VkCommandBuffer commandBuffer,
2584 float depthBiasConstantFactor,
2585 float depthBiasClamp,
2586 float depthBiasSlopeFactor)
2587 {
2588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2589
2590 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2591 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2592 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2593
2594 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2595 }
2596
2597 void radv_CmdSetBlendConstants(
2598 VkCommandBuffer commandBuffer,
2599 const float blendConstants[4])
2600 {
2601 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2602
2603 memcpy(cmd_buffer->state.dynamic.blend_constants,
2604 blendConstants, sizeof(float) * 4);
2605
2606 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2607 }
2608
2609 void radv_CmdSetDepthBounds(
2610 VkCommandBuffer commandBuffer,
2611 float minDepthBounds,
2612 float maxDepthBounds)
2613 {
2614 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2615
2616 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2617 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2618
2619 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2620 }
2621
2622 void radv_CmdSetStencilCompareMask(
2623 VkCommandBuffer commandBuffer,
2624 VkStencilFaceFlags faceMask,
2625 uint32_t compareMask)
2626 {
2627 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2628
2629 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2630 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2631 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2632 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2633
2634 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2635 }
2636
2637 void radv_CmdSetStencilWriteMask(
2638 VkCommandBuffer commandBuffer,
2639 VkStencilFaceFlags faceMask,
2640 uint32_t writeMask)
2641 {
2642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2643
2644 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2645 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2646 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2647 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2648
2649 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2650 }
2651
2652 void radv_CmdSetStencilReference(
2653 VkCommandBuffer commandBuffer,
2654 VkStencilFaceFlags faceMask,
2655 uint32_t reference)
2656 {
2657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2658
2659 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2660 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2661 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2662 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2663
2664 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2665 }
2666
2667 void radv_CmdExecuteCommands(
2668 VkCommandBuffer commandBuffer,
2669 uint32_t commandBufferCount,
2670 const VkCommandBuffer* pCmdBuffers)
2671 {
2672 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2673
2674 assert(commandBufferCount > 0);
2675
2676 /* Emit pending flushes on primary prior to executing secondary */
2677 si_emit_cache_flush(primary);
2678
2679 for (uint32_t i = 0; i < commandBufferCount; i++) {
2680 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2681
2682 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2683 secondary->scratch_size_needed);
2684 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2685 secondary->compute_scratch_size_needed);
2686
2687 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2688 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2689 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2690 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2691 if (secondary->tess_rings_needed)
2692 primary->tess_rings_needed = true;
2693 if (secondary->sample_positions_needed)
2694 primary->sample_positions_needed = true;
2695
2696 if (secondary->ring_offsets_idx != -1) {
2697 if (primary->ring_offsets_idx == -1)
2698 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2699 else
2700 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2701 }
2702 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2703
2704
2705 /* When the secondary command buffer is compute only we don't
2706 * need to re-emit the current graphics pipeline.
2707 */
2708 if (secondary->state.emitted_pipeline) {
2709 primary->state.emitted_pipeline =
2710 secondary->state.emitted_pipeline;
2711 }
2712
2713 /* When the secondary command buffer is graphics only we don't
2714 * need to re-emit the current compute pipeline.
2715 */
2716 if (secondary->state.emitted_compute_pipeline) {
2717 primary->state.emitted_compute_pipeline =
2718 secondary->state.emitted_compute_pipeline;
2719 }
2720
2721 /* Only re-emit the draw packets when needed. */
2722 if (secondary->state.last_primitive_reset_en != -1) {
2723 primary->state.last_primitive_reset_en =
2724 secondary->state.last_primitive_reset_en;
2725 }
2726
2727 if (secondary->state.last_primitive_reset_index) {
2728 primary->state.last_primitive_reset_index =
2729 secondary->state.last_primitive_reset_index;
2730 }
2731
2732 if (secondary->state.last_ia_multi_vgt_param) {
2733 primary->state.last_ia_multi_vgt_param =
2734 secondary->state.last_ia_multi_vgt_param;
2735 }
2736 }
2737
2738 /* After executing commands from secondary buffers we have to dirty
2739 * some states.
2740 */
2741 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2742 RADV_CMD_DIRTY_INDEX_BUFFER |
2743 RADV_CMD_DIRTY_DYNAMIC_ALL;
2744 radv_mark_descriptor_sets_dirty(primary);
2745 }
2746
2747 VkResult radv_CreateCommandPool(
2748 VkDevice _device,
2749 const VkCommandPoolCreateInfo* pCreateInfo,
2750 const VkAllocationCallbacks* pAllocator,
2751 VkCommandPool* pCmdPool)
2752 {
2753 RADV_FROM_HANDLE(radv_device, device, _device);
2754 struct radv_cmd_pool *pool;
2755
2756 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2757 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2758 if (pool == NULL)
2759 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2760
2761 if (pAllocator)
2762 pool->alloc = *pAllocator;
2763 else
2764 pool->alloc = device->alloc;
2765
2766 list_inithead(&pool->cmd_buffers);
2767 list_inithead(&pool->free_cmd_buffers);
2768
2769 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2770
2771 *pCmdPool = radv_cmd_pool_to_handle(pool);
2772
2773 return VK_SUCCESS;
2774
2775 }
2776
2777 void radv_DestroyCommandPool(
2778 VkDevice _device,
2779 VkCommandPool commandPool,
2780 const VkAllocationCallbacks* pAllocator)
2781 {
2782 RADV_FROM_HANDLE(radv_device, device, _device);
2783 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2784
2785 if (!pool)
2786 return;
2787
2788 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2789 &pool->cmd_buffers, pool_link) {
2790 radv_cmd_buffer_destroy(cmd_buffer);
2791 }
2792
2793 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2794 &pool->free_cmd_buffers, pool_link) {
2795 radv_cmd_buffer_destroy(cmd_buffer);
2796 }
2797
2798 vk_free2(&device->alloc, pAllocator, pool);
2799 }
2800
2801 VkResult radv_ResetCommandPool(
2802 VkDevice device,
2803 VkCommandPool commandPool,
2804 VkCommandPoolResetFlags flags)
2805 {
2806 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2807 VkResult result;
2808
2809 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2810 &pool->cmd_buffers, pool_link) {
2811 result = radv_reset_cmd_buffer(cmd_buffer);
2812 if (result != VK_SUCCESS)
2813 return result;
2814 }
2815
2816 return VK_SUCCESS;
2817 }
2818
2819 void radv_TrimCommandPoolKHR(
2820 VkDevice device,
2821 VkCommandPool commandPool,
2822 VkCommandPoolTrimFlagsKHR flags)
2823 {
2824 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2825
2826 if (!pool)
2827 return;
2828
2829 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2830 &pool->free_cmd_buffers, pool_link) {
2831 radv_cmd_buffer_destroy(cmd_buffer);
2832 }
2833 }
2834
2835 void radv_CmdBeginRenderPass(
2836 VkCommandBuffer commandBuffer,
2837 const VkRenderPassBeginInfo* pRenderPassBegin,
2838 VkSubpassContents contents)
2839 {
2840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2841 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2842 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2843
2844 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2845 cmd_buffer->cs, 2048);
2846 MAYBE_UNUSED VkResult result;
2847
2848 cmd_buffer->state.framebuffer = framebuffer;
2849 cmd_buffer->state.pass = pass;
2850 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2851
2852 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2853 if (result != VK_SUCCESS)
2854 return;
2855
2856 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2857 assert(cmd_buffer->cs->cdw <= cdw_max);
2858
2859 radv_cmd_buffer_clear_subpass(cmd_buffer);
2860 }
2861
2862 void radv_CmdNextSubpass(
2863 VkCommandBuffer commandBuffer,
2864 VkSubpassContents contents)
2865 {
2866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2867
2868 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2869
2870 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2871 2048);
2872
2873 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2874 radv_cmd_buffer_clear_subpass(cmd_buffer);
2875 }
2876
2877 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2878 {
2879 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2880 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2881 if (!pipeline->shaders[stage])
2882 continue;
2883 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2884 if (loc->sgpr_idx == -1)
2885 continue;
2886 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2887 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2888
2889 }
2890 if (pipeline->gs_copy_shader) {
2891 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2892 if (loc->sgpr_idx != -1) {
2893 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2894 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2895 }
2896 }
2897 }
2898
2899 static void
2900 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2901 uint32_t vertex_count)
2902 {
2903 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2904 radeon_emit(cmd_buffer->cs, vertex_count);
2905 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2906 S_0287F0_USE_OPAQUE(0));
2907 }
2908
2909 void radv_CmdDraw(
2910 VkCommandBuffer commandBuffer,
2911 uint32_t vertexCount,
2912 uint32_t instanceCount,
2913 uint32_t firstVertex,
2914 uint32_t firstInstance)
2915 {
2916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2917
2918 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2919
2920 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2921
2922 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2923 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2924 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2925 radeon_emit(cmd_buffer->cs, firstVertex);
2926 radeon_emit(cmd_buffer->cs, firstInstance);
2927 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2928 radeon_emit(cmd_buffer->cs, 0);
2929
2930 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2931 radeon_emit(cmd_buffer->cs, instanceCount);
2932
2933 if (!cmd_buffer->state.subpass->view_mask) {
2934 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2935 } else {
2936 unsigned i;
2937 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2938 radv_emit_view_index(cmd_buffer, i);
2939
2940 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2941 }
2942 }
2943
2944 assert(cmd_buffer->cs->cdw <= cdw_max);
2945
2946 radv_cmd_buffer_after_draw(cmd_buffer);
2947 }
2948
2949
2950 static void
2951 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2952 uint64_t index_va,
2953 uint32_t index_count)
2954 {
2955 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2956 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2957 radeon_emit(cmd_buffer->cs, index_va);
2958 radeon_emit(cmd_buffer->cs, index_va >> 32);
2959 radeon_emit(cmd_buffer->cs, index_count);
2960 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2961 }
2962
2963 void radv_CmdDrawIndexed(
2964 VkCommandBuffer commandBuffer,
2965 uint32_t indexCount,
2966 uint32_t instanceCount,
2967 uint32_t firstIndex,
2968 int32_t vertexOffset,
2969 uint32_t firstInstance)
2970 {
2971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2972 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2973 uint64_t index_va;
2974
2975 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2976
2977 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2978
2979 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2980 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2981 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2982 radeon_emit(cmd_buffer->cs, vertexOffset);
2983 radeon_emit(cmd_buffer->cs, firstInstance);
2984 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2985 radeon_emit(cmd_buffer->cs, 0);
2986
2987 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2988 radeon_emit(cmd_buffer->cs, instanceCount);
2989
2990 index_va = cmd_buffer->state.index_va;
2991 index_va += firstIndex * index_size;
2992 if (!cmd_buffer->state.subpass->view_mask) {
2993 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2994 } else {
2995 unsigned i;
2996 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2997 radv_emit_view_index(cmd_buffer, i);
2998
2999 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
3000 }
3001 }
3002
3003 assert(cmd_buffer->cs->cdw <= cdw_max);
3004 radv_cmd_buffer_after_draw(cmd_buffer);
3005 }
3006
3007 static void
3008 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3009 bool indexed,
3010 uint32_t draw_count,
3011 uint64_t count_va,
3012 uint32_t stride)
3013 {
3014 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3015 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3016 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3017 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3018 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3019 assert(base_reg);
3020
3021 if (draw_count == 1 && !count_va && !draw_id_enable) {
3022 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3023 PKT3_DRAW_INDIRECT, 3, false));
3024 radeon_emit(cs, 0);
3025 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3026 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3027 radeon_emit(cs, di_src_sel);
3028 } else {
3029 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3030 PKT3_DRAW_INDIRECT_MULTI,
3031 8, false));
3032 radeon_emit(cs, 0);
3033 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3034 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3035 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3036 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3037 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3038 radeon_emit(cs, draw_count); /* count */
3039 radeon_emit(cs, count_va); /* count_addr */
3040 radeon_emit(cs, count_va >> 32);
3041 radeon_emit(cs, stride); /* stride */
3042 radeon_emit(cs, di_src_sel);
3043 }
3044 }
3045
3046 static void
3047 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
3048 VkBuffer _buffer,
3049 VkDeviceSize offset,
3050 VkBuffer _count_buffer,
3051 VkDeviceSize count_offset,
3052 uint32_t draw_count,
3053 uint32_t stride,
3054 bool indexed)
3055 {
3056 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3057 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
3058 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3059
3060 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
3061 indirect_va += offset + buffer->offset;
3062 uint64_t count_va = 0;
3063
3064 if (count_buffer) {
3065 count_va = radv_buffer_get_va(count_buffer->bo);
3066 count_va += count_offset + count_buffer->offset;
3067
3068 cmd_buffer->device->ws->cs_add_buffer(cs, count_buffer->bo, 8);
3069 }
3070
3071 if (!draw_count)
3072 return;
3073
3074 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3075
3076 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3077 radeon_emit(cs, 1);
3078 radeon_emit(cs, indirect_va);
3079 radeon_emit(cs, indirect_va >> 32);
3080
3081 if (!cmd_buffer->state.subpass->view_mask) {
3082 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3083 } else {
3084 unsigned i;
3085 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3086 radv_emit_view_index(cmd_buffer, i);
3087
3088 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3089 }
3090 }
3091 radv_cmd_buffer_after_draw(cmd_buffer);
3092 }
3093
3094 static void
3095 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3096 VkBuffer buffer,
3097 VkDeviceSize offset,
3098 VkBuffer countBuffer,
3099 VkDeviceSize countBufferOffset,
3100 uint32_t maxDrawCount,
3101 uint32_t stride)
3102 {
3103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3104 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3105
3106 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3107 cmd_buffer->cs, 24 * MAX_VIEWS);
3108
3109 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3110 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3111
3112 assert(cmd_buffer->cs->cdw <= cdw_max);
3113 }
3114
3115 static void
3116 radv_cmd_draw_indexed_indirect_count(
3117 VkCommandBuffer commandBuffer,
3118 VkBuffer buffer,
3119 VkDeviceSize offset,
3120 VkBuffer countBuffer,
3121 VkDeviceSize countBufferOffset,
3122 uint32_t maxDrawCount,
3123 uint32_t stride)
3124 {
3125 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3126
3127 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3128
3129 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3130
3131 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3132 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3133
3134 assert(cmd_buffer->cs->cdw <= cdw_max);
3135 }
3136
3137 void radv_CmdDrawIndirect(
3138 VkCommandBuffer commandBuffer,
3139 VkBuffer buffer,
3140 VkDeviceSize offset,
3141 uint32_t drawCount,
3142 uint32_t stride)
3143 {
3144 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3145 VK_NULL_HANDLE, 0, drawCount, stride);
3146 }
3147
3148 void radv_CmdDrawIndexedIndirect(
3149 VkCommandBuffer commandBuffer,
3150 VkBuffer buffer,
3151 VkDeviceSize offset,
3152 uint32_t drawCount,
3153 uint32_t stride)
3154 {
3155 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3156 VK_NULL_HANDLE, 0, drawCount, stride);
3157 }
3158
3159 void radv_CmdDrawIndirectCountAMD(
3160 VkCommandBuffer commandBuffer,
3161 VkBuffer buffer,
3162 VkDeviceSize offset,
3163 VkBuffer countBuffer,
3164 VkDeviceSize countBufferOffset,
3165 uint32_t maxDrawCount,
3166 uint32_t stride)
3167 {
3168 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3169 countBuffer, countBufferOffset,
3170 maxDrawCount, stride);
3171 }
3172
3173 void radv_CmdDrawIndexedIndirectCountAMD(
3174 VkCommandBuffer commandBuffer,
3175 VkBuffer buffer,
3176 VkDeviceSize offset,
3177 VkBuffer countBuffer,
3178 VkDeviceSize countBufferOffset,
3179 uint32_t maxDrawCount,
3180 uint32_t stride)
3181 {
3182 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3183 countBuffer, countBufferOffset,
3184 maxDrawCount, stride);
3185 }
3186
3187 struct radv_dispatch_info {
3188 /**
3189 * Determine the layout of the grid (in block units) to be used.
3190 */
3191 uint32_t blocks[3];
3192
3193 /**
3194 * Whether it's an unaligned compute dispatch.
3195 */
3196 bool unaligned;
3197
3198 /**
3199 * Indirect compute parameters resource.
3200 */
3201 struct radv_buffer *indirect;
3202 uint64_t indirect_offset;
3203 };
3204
3205 static void
3206 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3207 const struct radv_dispatch_info *info)
3208 {
3209 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3210 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3211 struct radeon_winsys *ws = cmd_buffer->device->ws;
3212 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3213 struct ac_userdata_info *loc;
3214 unsigned dispatch_initiator;
3215 uint8_t grid_used;
3216
3217 grid_used = compute_shader->info.info.cs.grid_components_used;
3218
3219 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3220 AC_UD_CS_GRID_SIZE);
3221
3222 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3223
3224 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3225 S_00B800_FORCE_START_AT_000(1);
3226
3227 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3228 /* If the KMD allows it (there is a KMD hw register for it),
3229 * allow launching waves out-of-order.
3230 */
3231 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3232 }
3233
3234 if (info->indirect) {
3235 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3236
3237 va += info->indirect->offset + info->indirect_offset;
3238
3239 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3240
3241 if (loc->sgpr_idx != -1) {
3242 for (unsigned i = 0; i < grid_used; ++i) {
3243 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3244 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3245 COPY_DATA_DST_SEL(COPY_DATA_REG));
3246 radeon_emit(cs, (va + 4 * i));
3247 radeon_emit(cs, (va + 4 * i) >> 32);
3248 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3249 + loc->sgpr_idx * 4) >> 2) + i);
3250 radeon_emit(cs, 0);
3251 }
3252 }
3253
3254 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3255 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3256 PKT3_SHADER_TYPE_S(1));
3257 radeon_emit(cs, va);
3258 radeon_emit(cs, va >> 32);
3259 radeon_emit(cs, dispatch_initiator);
3260 } else {
3261 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3262 PKT3_SHADER_TYPE_S(1));
3263 radeon_emit(cs, 1);
3264 radeon_emit(cs, va);
3265 radeon_emit(cs, va >> 32);
3266
3267 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3268 PKT3_SHADER_TYPE_S(1));
3269 radeon_emit(cs, 0);
3270 radeon_emit(cs, dispatch_initiator);
3271 }
3272 } else {
3273 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3274
3275 if (info->unaligned) {
3276 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3277 unsigned remainder[3];
3278
3279 /* If aligned, these should be an entire block size,
3280 * not 0.
3281 */
3282 remainder[0] = blocks[0] + cs_block_size[0] -
3283 align_u32_npot(blocks[0], cs_block_size[0]);
3284 remainder[1] = blocks[1] + cs_block_size[1] -
3285 align_u32_npot(blocks[1], cs_block_size[1]);
3286 remainder[2] = blocks[2] + cs_block_size[2] -
3287 align_u32_npot(blocks[2], cs_block_size[2]);
3288
3289 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3290 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3291 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3292
3293 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3294 radeon_emit(cs,
3295 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3296 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3297 radeon_emit(cs,
3298 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3299 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3300 radeon_emit(cs,
3301 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3302 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3303
3304 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3305 }
3306
3307 if (loc->sgpr_idx != -1) {
3308 assert(!loc->indirect);
3309 assert(loc->num_sgprs == grid_used);
3310
3311 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3312 loc->sgpr_idx * 4, grid_used);
3313 radeon_emit(cs, blocks[0]);
3314 if (grid_used > 1)
3315 radeon_emit(cs, blocks[1]);
3316 if (grid_used > 2)
3317 radeon_emit(cs, blocks[2]);
3318 }
3319
3320 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3321 PKT3_SHADER_TYPE_S(1));
3322 radeon_emit(cs, blocks[0]);
3323 radeon_emit(cs, blocks[1]);
3324 radeon_emit(cs, blocks[2]);
3325 radeon_emit(cs, dispatch_initiator);
3326 }
3327
3328 assert(cmd_buffer->cs->cdw <= cdw_max);
3329 }
3330
3331 static void
3332 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3333 const struct radv_dispatch_info *info)
3334 {
3335 radv_emit_compute_pipeline(cmd_buffer);
3336
3337 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3338 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3339 VK_SHADER_STAGE_COMPUTE_BIT);
3340
3341 si_emit_cache_flush(cmd_buffer);
3342
3343 radv_emit_dispatch_packets(cmd_buffer, info);
3344
3345 radv_cmd_buffer_after_draw(cmd_buffer);
3346 }
3347
3348 void radv_CmdDispatch(
3349 VkCommandBuffer commandBuffer,
3350 uint32_t x,
3351 uint32_t y,
3352 uint32_t z)
3353 {
3354 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3355 struct radv_dispatch_info info = {};
3356
3357 info.blocks[0] = x;
3358 info.blocks[1] = y;
3359 info.blocks[2] = z;
3360
3361 radv_dispatch(cmd_buffer, &info);
3362 }
3363
3364 void radv_CmdDispatchIndirect(
3365 VkCommandBuffer commandBuffer,
3366 VkBuffer _buffer,
3367 VkDeviceSize offset)
3368 {
3369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3370 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3371 struct radv_dispatch_info info = {};
3372
3373 info.indirect = buffer;
3374 info.indirect_offset = offset;
3375
3376 radv_dispatch(cmd_buffer, &info);
3377 }
3378
3379 void radv_unaligned_dispatch(
3380 struct radv_cmd_buffer *cmd_buffer,
3381 uint32_t x,
3382 uint32_t y,
3383 uint32_t z)
3384 {
3385 struct radv_dispatch_info info = {};
3386
3387 info.blocks[0] = x;
3388 info.blocks[1] = y;
3389 info.blocks[2] = z;
3390 info.unaligned = 1;
3391
3392 radv_dispatch(cmd_buffer, &info);
3393 }
3394
3395 void radv_CmdEndRenderPass(
3396 VkCommandBuffer commandBuffer)
3397 {
3398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3399
3400 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3401
3402 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3403
3404 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3405 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3406 radv_handle_subpass_image_transition(cmd_buffer,
3407 (VkAttachmentReference){i, layout});
3408 }
3409
3410 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3411
3412 cmd_buffer->state.pass = NULL;
3413 cmd_buffer->state.subpass = NULL;
3414 cmd_buffer->state.attachments = NULL;
3415 cmd_buffer->state.framebuffer = NULL;
3416 }
3417
3418 /*
3419 * For HTILE we have the following interesting clear words:
3420 * 0x0000030f: Uncompressed.
3421 * 0xfffffff0: Clear depth to 1.0
3422 * 0x00000000: Clear depth to 0.0
3423 */
3424 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3425 struct radv_image *image,
3426 const VkImageSubresourceRange *range,
3427 uint32_t clear_word)
3428 {
3429 assert(range->baseMipLevel == 0);
3430 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3431 unsigned layer_count = radv_get_layerCount(image, range);
3432 uint64_t size = image->surface.htile_slice_size * layer_count;
3433 uint64_t offset = image->offset + image->htile_offset +
3434 image->surface.htile_slice_size * range->baseArrayLayer;
3435
3436 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3437 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3438
3439 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3440
3441 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3442 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3443 RADV_CMD_FLAG_INV_VMEM_L1 |
3444 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3445 }
3446
3447 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3448 struct radv_image *image,
3449 VkImageLayout src_layout,
3450 VkImageLayout dst_layout,
3451 unsigned src_queue_mask,
3452 unsigned dst_queue_mask,
3453 const VkImageSubresourceRange *range,
3454 VkImageAspectFlags pending_clears)
3455 {
3456 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3457 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3458 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3459 cmd_buffer->state.render_area.extent.width == image->info.width &&
3460 cmd_buffer->state.render_area.extent.height == image->info.height) {
3461 /* The clear will initialize htile. */
3462 return;
3463 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3464 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3465 /* TODO: merge with the clear if applicable */
3466 radv_initialize_htile(cmd_buffer, image, range, 0);
3467 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3468 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3469 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3470 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3471 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3472 VkImageSubresourceRange local_range = *range;
3473 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3474 local_range.baseMipLevel = 0;
3475 local_range.levelCount = 1;
3476
3477 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3478 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3479
3480 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3481
3482 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3483 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3484 }
3485 }
3486
3487 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3488 struct radv_image *image, uint32_t value)
3489 {
3490 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3491 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3492
3493 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3494 image->cmask.size, value);
3495
3496 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3497 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3498 RADV_CMD_FLAG_INV_VMEM_L1 |
3499 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3500 }
3501
3502 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3503 struct radv_image *image,
3504 VkImageLayout src_layout,
3505 VkImageLayout dst_layout,
3506 unsigned src_queue_mask,
3507 unsigned dst_queue_mask,
3508 const VkImageSubresourceRange *range)
3509 {
3510 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3511 if (image->fmask.size)
3512 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3513 else
3514 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3515 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3516 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3517 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3518 }
3519 }
3520
3521 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3522 struct radv_image *image, uint32_t value)
3523 {
3524
3525 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3526 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3527
3528 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3529 image->surface.dcc_size, value);
3530
3531 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3532 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3533 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3534 RADV_CMD_FLAG_INV_VMEM_L1 |
3535 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3536 }
3537
3538 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3539 struct radv_image *image,
3540 VkImageLayout src_layout,
3541 VkImageLayout dst_layout,
3542 unsigned src_queue_mask,
3543 unsigned dst_queue_mask,
3544 const VkImageSubresourceRange *range)
3545 {
3546 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3547 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3548 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3549 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3550 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3551 }
3552 }
3553
3554 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3555 struct radv_image *image,
3556 VkImageLayout src_layout,
3557 VkImageLayout dst_layout,
3558 uint32_t src_family,
3559 uint32_t dst_family,
3560 const VkImageSubresourceRange *range,
3561 VkImageAspectFlags pending_clears)
3562 {
3563 if (image->exclusive && src_family != dst_family) {
3564 /* This is an acquire or a release operation and there will be
3565 * a corresponding release/acquire. Do the transition in the
3566 * most flexible queue. */
3567
3568 assert(src_family == cmd_buffer->queue_family_index ||
3569 dst_family == cmd_buffer->queue_family_index);
3570
3571 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3572 return;
3573
3574 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3575 (src_family == RADV_QUEUE_GENERAL ||
3576 dst_family == RADV_QUEUE_GENERAL))
3577 return;
3578 }
3579
3580 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3581 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3582
3583 if (image->surface.htile_size)
3584 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3585 dst_layout, src_queue_mask,
3586 dst_queue_mask, range,
3587 pending_clears);
3588
3589 if (image->cmask.size || image->fmask.size)
3590 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3591 dst_layout, src_queue_mask,
3592 dst_queue_mask, range);
3593
3594 if (image->surface.dcc_size)
3595 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3596 dst_layout, src_queue_mask,
3597 dst_queue_mask, range);
3598 }
3599
3600 void radv_CmdPipelineBarrier(
3601 VkCommandBuffer commandBuffer,
3602 VkPipelineStageFlags srcStageMask,
3603 VkPipelineStageFlags destStageMask,
3604 VkBool32 byRegion,
3605 uint32_t memoryBarrierCount,
3606 const VkMemoryBarrier* pMemoryBarriers,
3607 uint32_t bufferMemoryBarrierCount,
3608 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3609 uint32_t imageMemoryBarrierCount,
3610 const VkImageMemoryBarrier* pImageMemoryBarriers)
3611 {
3612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3613 enum radv_cmd_flush_bits src_flush_bits = 0;
3614 enum radv_cmd_flush_bits dst_flush_bits = 0;
3615
3616 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3617 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3618 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3619 NULL);
3620 }
3621
3622 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3623 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3624 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3625 NULL);
3626 }
3627
3628 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3629 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3630 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3631 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3632 image);
3633 }
3634
3635 radv_stage_flush(cmd_buffer, srcStageMask);
3636 cmd_buffer->state.flush_bits |= src_flush_bits;
3637
3638 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3639 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3640 radv_handle_image_transition(cmd_buffer, image,
3641 pImageMemoryBarriers[i].oldLayout,
3642 pImageMemoryBarriers[i].newLayout,
3643 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3644 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3645 &pImageMemoryBarriers[i].subresourceRange,
3646 0);
3647 }
3648
3649 cmd_buffer->state.flush_bits |= dst_flush_bits;
3650 }
3651
3652
3653 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3654 struct radv_event *event,
3655 VkPipelineStageFlags stageMask,
3656 unsigned value)
3657 {
3658 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3659 uint64_t va = radv_buffer_get_va(event->bo);
3660
3661 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3662
3663 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3664
3665 /* TODO: this is overkill. Probably should figure something out from
3666 * the stage mask. */
3667
3668 si_cs_emit_write_event_eop(cs,
3669 cmd_buffer->state.predicating,
3670 cmd_buffer->device->physical_device->rad_info.chip_class,
3671 false,
3672 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3673 1, va, 2, value);
3674
3675 assert(cmd_buffer->cs->cdw <= cdw_max);
3676 }
3677
3678 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3679 VkEvent _event,
3680 VkPipelineStageFlags stageMask)
3681 {
3682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3683 RADV_FROM_HANDLE(radv_event, event, _event);
3684
3685 write_event(cmd_buffer, event, stageMask, 1);
3686 }
3687
3688 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3689 VkEvent _event,
3690 VkPipelineStageFlags stageMask)
3691 {
3692 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3693 RADV_FROM_HANDLE(radv_event, event, _event);
3694
3695 write_event(cmd_buffer, event, stageMask, 0);
3696 }
3697
3698 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3699 uint32_t eventCount,
3700 const VkEvent* pEvents,
3701 VkPipelineStageFlags srcStageMask,
3702 VkPipelineStageFlags dstStageMask,
3703 uint32_t memoryBarrierCount,
3704 const VkMemoryBarrier* pMemoryBarriers,
3705 uint32_t bufferMemoryBarrierCount,
3706 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3707 uint32_t imageMemoryBarrierCount,
3708 const VkImageMemoryBarrier* pImageMemoryBarriers)
3709 {
3710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3711 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3712
3713 for (unsigned i = 0; i < eventCount; ++i) {
3714 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3715 uint64_t va = radv_buffer_get_va(event->bo);
3716
3717 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3718
3719 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3720
3721 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3722 assert(cmd_buffer->cs->cdw <= cdw_max);
3723 }
3724
3725
3726 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3727 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3728
3729 radv_handle_image_transition(cmd_buffer, image,
3730 pImageMemoryBarriers[i].oldLayout,
3731 pImageMemoryBarriers[i].newLayout,
3732 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3733 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3734 &pImageMemoryBarriers[i].subresourceRange,
3735 0);
3736 }
3737
3738 /* TODO: figure out how to do memory barriers without waiting */
3739 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3740 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3741 RADV_CMD_FLAG_INV_VMEM_L1 |
3742 RADV_CMD_FLAG_INV_SMEM_L1;
3743 }