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a8359ac092fc511715ac0bf2e620832aba9575d7
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING);
351
352 if (!bo) {
353 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
354 return false;
355 }
356
357 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
358 if (cmd_buffer->upload.upload_bo) {
359 upload = malloc(sizeof(*upload));
360
361 if (!upload) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
363 device->ws->buffer_destroy(bo);
364 return false;
365 }
366
367 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
368 list_add(&upload->list, &cmd_buffer->upload.list);
369 }
370
371 cmd_buffer->upload.upload_bo = bo;
372 cmd_buffer->upload.size = new_size;
373 cmd_buffer->upload.offset = 0;
374 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
375
376 if (!cmd_buffer->upload.map) {
377 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
378 return false;
379 }
380
381 return true;
382 }
383
384 bool
385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
386 unsigned size,
387 unsigned alignment,
388 unsigned *out_offset,
389 void **ptr)
390 {
391 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
392 if (offset + size > cmd_buffer->upload.size) {
393 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
394 return false;
395 offset = 0;
396 }
397
398 *out_offset = offset;
399 *ptr = cmd_buffer->upload.map + offset;
400
401 cmd_buffer->upload.offset = offset + size;
402 return true;
403 }
404
405 bool
406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
407 unsigned size, unsigned alignment,
408 const void *data, unsigned *out_offset)
409 {
410 uint8_t *ptr;
411
412 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
413 out_offset, (void **)&ptr))
414 return false;
415
416 if (ptr)
417 memcpy(ptr, data, size);
418
419 return true;
420 }
421
422 static void
423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
424 unsigned count, const uint32_t *data)
425 {
426 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
427 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
428 S_370_WR_CONFIRM(1) |
429 S_370_ENGINE_SEL(V_370_ME));
430 radeon_emit(cs, va);
431 radeon_emit(cs, va >> 32);
432 radeon_emit_array(cs, data, count);
433 }
434
435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
436 {
437 struct radv_device *device = cmd_buffer->device;
438 struct radeon_winsys_cs *cs = cmd_buffer->cs;
439 uint64_t va;
440
441 va = radv_buffer_get_va(device->trace_bo);
442 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
443 va += 4;
444
445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
446
447 ++cmd_buffer->state.trace_id;
448 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
449 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
451 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
452 }
453
454 static void
455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
456 enum radv_cmd_flush_bits flags)
457 {
458 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
459 uint32_t *ptr = NULL;
460 uint64_t va = 0;
461
462 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
464
465 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
466 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
467 cmd_buffer->gfx9_fence_offset;
468 ptr = &cmd_buffer->gfx9_fence_idx;
469 }
470
471 /* Force wait for graphics or compute engines to be idle. */
472 si_cs_emit_cache_flush(cmd_buffer->cs,
473 cmd_buffer->device->physical_device->rad_info.chip_class,
474 ptr, va,
475 radv_cmd_buffer_uses_mec(cmd_buffer),
476 flags);
477 }
478
479 if (unlikely(cmd_buffer->device->trace_bo))
480 radv_cmd_buffer_trace_emit(cmd_buffer);
481 }
482
483 static void
484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
485 struct radv_pipeline *pipeline, enum ring_type ring)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[2];
490 uint64_t va;
491
492 va = radv_buffer_get_va(device->trace_bo);
493
494 switch (ring) {
495 case RING_GFX:
496 va += 8;
497 break;
498 case RING_COMPUTE:
499 va += 16;
500 break;
501 default:
502 assert(!"invalid ring type");
503 }
504
505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
506 cmd_buffer->cs, 6);
507
508 data[0] = (uintptr_t)pipeline;
509 data[1] = (uintptr_t)pipeline >> 32;
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, 2, data);
513 }
514
515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
516 VkPipelineBindPoint bind_point,
517 struct radv_descriptor_set *set,
518 unsigned idx)
519 {
520 struct radv_descriptor_state *descriptors_state =
521 radv_get_descriptors_state(cmd_buffer, bind_point);
522
523 descriptors_state->sets[idx] = set;
524 if (set)
525 descriptors_state->valid |= (1u << idx);
526 else
527 descriptors_state->valid &= ~(1u << idx);
528 descriptors_state->dirty |= (1u << idx);
529 }
530
531 static void
532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
533 VkPipelineBindPoint bind_point)
534 {
535 struct radv_descriptor_state *descriptors_state =
536 radv_get_descriptors_state(cmd_buffer, bind_point);
537 struct radv_device *device = cmd_buffer->device;
538 struct radeon_winsys_cs *cs = cmd_buffer->cs;
539 uint32_t data[MAX_SETS * 2] = {};
540 uint64_t va;
541 unsigned i;
542 va = radv_buffer_get_va(device->trace_bo) + 24;
543
544 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
545 cmd_buffer->cs, 4 + MAX_SETS * 2);
546
547 for_each_bit(i, descriptors_state->valid) {
548 struct radv_descriptor_set *set = descriptors_state->sets[i];
549 data[i * 2] = (uintptr_t)set;
550 data[i * 2 + 1] = (uintptr_t)set >> 32;
551 }
552
553 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
554 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
555 }
556
557 struct radv_userdata_info *
558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
559 gl_shader_stage stage,
560 int idx)
561 {
562 if (stage == MESA_SHADER_VERTEX) {
563 if (pipeline->shaders[MESA_SHADER_VERTEX])
564 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
565 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
566 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
567 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
568 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
569 } else if (stage == MESA_SHADER_TESS_EVAL) {
570 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
571 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 }
575 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
576 }
577
578 static void
579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
580 struct radv_pipeline *pipeline,
581 gl_shader_stage stage,
582 int idx, uint64_t va)
583 {
584 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
585 uint32_t base_reg = pipeline->user_data_0[stage];
586 if (loc->sgpr_idx == -1)
587 return;
588 assert(loc->num_sgprs == 2);
589 assert(!loc->indirect);
590
591 radv_emit_shader_pointer(cmd_buffer->cs,
592 base_reg + loc->sgpr_idx * 4, va);
593 }
594
595 static void
596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
597 struct radv_pipeline *pipeline)
598 {
599 int num_samples = pipeline->graphics.ms.num_samples;
600 struct radv_multisample_state *ms = &pipeline->graphics.ms;
601 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
602
603 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
604 cmd_buffer->sample_positions_needed = true;
605
606 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
607 return;
608
609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
611 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
614
615 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
616
617 /* GFX9: Flush DFSM when the AA mode changes. */
618 if (cmd_buffer->device->dfsm_allowed) {
619 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
620 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
621 }
622 }
623
624 static void
625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
626 struct radv_shader_variant *shader)
627 {
628 uint64_t va;
629
630 if (!shader)
631 return;
632
633 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
634
635 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
636 }
637
638 static void
639 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_pipeline *pipeline,
641 bool vertex_stage_only)
642 {
643 struct radv_cmd_state *state = &cmd_buffer->state;
644 uint32_t mask = state->prefetch_L2_mask;
645
646 if (vertex_stage_only) {
647 /* Fast prefetch path for starting draws as soon as possible.
648 */
649 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
650 RADV_PREFETCH_VBO_DESCRIPTORS);
651 }
652
653 if (mask & RADV_PREFETCH_VS)
654 radv_emit_shader_prefetch(cmd_buffer,
655 pipeline->shaders[MESA_SHADER_VERTEX]);
656
657 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
658 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
659
660 if (mask & RADV_PREFETCH_TCS)
661 radv_emit_shader_prefetch(cmd_buffer,
662 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
663
664 if (mask & RADV_PREFETCH_TES)
665 radv_emit_shader_prefetch(cmd_buffer,
666 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
667
668 if (mask & RADV_PREFETCH_GS) {
669 radv_emit_shader_prefetch(cmd_buffer,
670 pipeline->shaders[MESA_SHADER_GEOMETRY]);
671 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
672 }
673
674 if (mask & RADV_PREFETCH_PS)
675 radv_emit_shader_prefetch(cmd_buffer,
676 pipeline->shaders[MESA_SHADER_FRAGMENT]);
677
678 state->prefetch_L2_mask &= ~mask;
679 }
680
681 static void
682 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
683 {
684 if (!cmd_buffer->device->physical_device->rbplus_allowed)
685 return;
686
687 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
688 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
689 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
690
691 unsigned sx_ps_downconvert = 0;
692 unsigned sx_blend_opt_epsilon = 0;
693 unsigned sx_blend_opt_control = 0;
694
695 for (unsigned i = 0; i < subpass->color_count; ++i) {
696 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
697 continue;
698
699 int idx = subpass->color_attachments[i].attachment;
700 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
701
702 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
703 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
704 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
705 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
706
707 bool has_alpha, has_rgb;
708
709 /* Set if RGB and A are present. */
710 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
711
712 if (format == V_028C70_COLOR_8 ||
713 format == V_028C70_COLOR_16 ||
714 format == V_028C70_COLOR_32)
715 has_rgb = !has_alpha;
716 else
717 has_rgb = true;
718
719 /* Check the colormask and export format. */
720 if (!(colormask & 0x7))
721 has_rgb = false;
722 if (!(colormask & 0x8))
723 has_alpha = false;
724
725 if (spi_format == V_028714_SPI_SHADER_ZERO) {
726 has_rgb = false;
727 has_alpha = false;
728 }
729
730 /* Disable value checking for disabled channels. */
731 if (!has_rgb)
732 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
733 if (!has_alpha)
734 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
735
736 /* Enable down-conversion for 32bpp and smaller formats. */
737 switch (format) {
738 case V_028C70_COLOR_8:
739 case V_028C70_COLOR_8_8:
740 case V_028C70_COLOR_8_8_8_8:
741 /* For 1 and 2-channel formats, use the superset thereof. */
742 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
743 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
744 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
745 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
746 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
747 }
748 break;
749
750 case V_028C70_COLOR_5_6_5:
751 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
752 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
753 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
754 }
755 break;
756
757 case V_028C70_COLOR_1_5_5_5:
758 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
759 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
760 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
761 }
762 break;
763
764 case V_028C70_COLOR_4_4_4_4:
765 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
766 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
767 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
768 }
769 break;
770
771 case V_028C70_COLOR_32:
772 if (swap == V_028C70_SWAP_STD &&
773 spi_format == V_028714_SPI_SHADER_32_R)
774 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
775 else if (swap == V_028C70_SWAP_ALT_REV &&
776 spi_format == V_028714_SPI_SHADER_32_AR)
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
778 break;
779
780 case V_028C70_COLOR_16:
781 case V_028C70_COLOR_16_16:
782 /* For 1-channel formats, use the superset thereof. */
783 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
784 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
785 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
786 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
787 if (swap == V_028C70_SWAP_STD ||
788 swap == V_028C70_SWAP_STD_REV)
789 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
790 else
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_10_11_11:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_2_10_10_10:
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
804 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
805 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
806 }
807 break;
808 }
809 }
810
811 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
812 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
813 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
814 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
815 }
816
817 static void
818 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
819 {
820 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
821
822 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
823 return;
824
825 radv_update_multisample_state(cmd_buffer, pipeline);
826
827 cmd_buffer->scratch_size_needed =
828 MAX2(cmd_buffer->scratch_size_needed,
829 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
830
831 if (!cmd_buffer->state.emitted_pipeline ||
832 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
833 pipeline->graphics.can_use_guardband)
834 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
835
836 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
837
838 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
839 if (!pipeline->shaders[i])
840 continue;
841
842 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
843 pipeline->shaders[i]->bo, 8);
844 }
845
846 if (radv_pipeline_has_gs(pipeline))
847 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
848 pipeline->gs_copy_shader->bo, 8);
849
850 if (unlikely(cmd_buffer->device->trace_bo))
851 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
852
853 cmd_buffer->state.emitted_pipeline = pipeline;
854
855 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
856 }
857
858 static void
859 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
860 {
861 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
862 cmd_buffer->state.dynamic.viewport.viewports);
863 }
864
865 static void
866 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
867 {
868 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
869
870 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
871 * scissor registers are changed. There is also a more efficient but
872 * more involved alternative workaround.
873 */
874 if (cmd_buffer->device->physical_device->has_scissor_bug) {
875 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
876 si_emit_cache_flush(cmd_buffer);
877 }
878 si_write_scissors(cmd_buffer->cs, 0, count,
879 cmd_buffer->state.dynamic.scissor.scissors,
880 cmd_buffer->state.dynamic.viewport.viewports,
881 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
882 }
883
884 static void
885 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
886 {
887 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
888 return;
889
890 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
891 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
892 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
893 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
894 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
895 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
896 S_028214_BR_Y(rect.offset.y + rect.extent.height));
897 }
898 }
899
900 static void
901 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
902 {
903 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
904
905 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
906 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
907 }
908
909 static void
910 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
911 {
912 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
915 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
916 }
917
918 static void
919 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
920 {
921 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
922
923 radeon_set_context_reg_seq(cmd_buffer->cs,
924 R_028430_DB_STENCILREFMASK, 2);
925 radeon_emit(cmd_buffer->cs,
926 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
927 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
928 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
929 S_028430_STENCILOPVAL(1));
930 radeon_emit(cmd_buffer->cs,
931 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
932 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
933 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
934 S_028434_STENCILOPVAL_BF(1));
935 }
936
937 static void
938 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
939 {
940 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
941
942 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
943 fui(d->depth_bounds.min));
944 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
945 fui(d->depth_bounds.max));
946 }
947
948 static void
949 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
950 {
951 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
952 unsigned slope = fui(d->depth_bias.slope * 16.0f);
953 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
954
955
956 radeon_set_context_reg_seq(cmd_buffer->cs,
957 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
958 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
959 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
960 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
961 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
962 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
963 }
964
965 static void
966 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
967 int index,
968 struct radv_attachment_info *att,
969 struct radv_image *image,
970 VkImageLayout layout)
971 {
972 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
973 struct radv_color_buffer_info *cb = &att->cb;
974 uint32_t cb_color_info = cb->cb_color_info;
975
976 if (!radv_layout_dcc_compressed(image, layout,
977 radv_image_queue_family_mask(image,
978 cmd_buffer->queue_family_index,
979 cmd_buffer->queue_family_index))) {
980 cb_color_info &= C_028C70_DCC_ENABLE;
981 }
982
983 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
984 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
985 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
986 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
987 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
988 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
989 radeon_emit(cmd_buffer->cs, cb_color_info);
990 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
991 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
992 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
993 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
994 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
995 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
996
997 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
998 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
999 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1000
1001 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1002 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1003 } else {
1004 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1005 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1006 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1007 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1008 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1009 radeon_emit(cmd_buffer->cs, cb_color_info);
1010 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1011 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1013 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1015 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1016
1017 if (is_vi) { /* DCC BASE */
1018 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1019 }
1020 }
1021 }
1022
1023 static void
1024 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1025 struct radv_ds_buffer_info *ds,
1026 struct radv_image *image,
1027 VkImageLayout layout)
1028 {
1029 uint32_t db_z_info = ds->db_z_info;
1030 uint32_t db_stencil_info = ds->db_stencil_info;
1031
1032 if (!radv_layout_has_htile(image, layout,
1033 radv_image_queue_family_mask(image,
1034 cmd_buffer->queue_family_index,
1035 cmd_buffer->queue_family_index))) {
1036 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1037 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1038 }
1039
1040 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1041 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1042
1043
1044 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1045 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1046 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1047 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1048 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1049
1050 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1051 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1052 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1053 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1054 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1055 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1056 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1057 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1058 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1059 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1060 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1061
1062 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1063 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1064 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1065 } else {
1066 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1067
1068 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1069 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1070 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1071 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1072 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1073 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1074 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1075 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1076 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1077 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1078
1079 }
1080
1081 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1082 ds->pa_su_poly_offset_db_fmt_cntl);
1083 }
1084
1085 void
1086 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1087 struct radv_image *image,
1088 VkClearDepthStencilValue ds_clear_value,
1089 VkImageAspectFlags aspects)
1090 {
1091 uint64_t va = radv_buffer_get_va(image->bo);
1092 va += image->offset + image->clear_value_offset;
1093 unsigned reg_offset = 0, reg_count = 0;
1094
1095 assert(radv_image_has_htile(image));
1096
1097 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1098 ++reg_count;
1099 } else {
1100 ++reg_offset;
1101 va += 4;
1102 }
1103 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1104 ++reg_count;
1105
1106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1107 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1108 S_370_WR_CONFIRM(1) |
1109 S_370_ENGINE_SEL(V_370_PFP));
1110 radeon_emit(cmd_buffer->cs, va);
1111 radeon_emit(cmd_buffer->cs, va >> 32);
1112 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1113 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1114 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1115 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1116
1117 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1118 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1119 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1120 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1121 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1122 }
1123
1124 static void
1125 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1126 struct radv_image *image)
1127 {
1128 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1129 uint64_t va = radv_buffer_get_va(image->bo);
1130 va += image->offset + image->clear_value_offset;
1131 unsigned reg_offset = 0, reg_count = 0;
1132
1133 if (!radv_image_has_htile(image))
1134 return;
1135
1136 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1137 ++reg_count;
1138 } else {
1139 ++reg_offset;
1140 va += 4;
1141 }
1142 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1143 ++reg_count;
1144
1145 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1146 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1147 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1148 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1149 radeon_emit(cmd_buffer->cs, va);
1150 radeon_emit(cmd_buffer->cs, va >> 32);
1151 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1152 radeon_emit(cmd_buffer->cs, 0);
1153
1154 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1155 radeon_emit(cmd_buffer->cs, 0);
1156 }
1157
1158 /*
1159 * With DCC some colors don't require CMASK elimination before being
1160 * used as a texture. This sets a predicate value to determine if the
1161 * cmask eliminate is required.
1162 */
1163 void
1164 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1165 struct radv_image *image,
1166 bool value)
1167 {
1168 uint64_t pred_val = value;
1169 uint64_t va = radv_buffer_get_va(image->bo);
1170 va += image->offset + image->dcc_pred_offset;
1171
1172 assert(radv_image_has_dcc(image));
1173
1174 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1175 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1176 S_370_WR_CONFIRM(1) |
1177 S_370_ENGINE_SEL(V_370_PFP));
1178 radeon_emit(cmd_buffer->cs, va);
1179 radeon_emit(cmd_buffer->cs, va >> 32);
1180 radeon_emit(cmd_buffer->cs, pred_val);
1181 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1182 }
1183
1184 void
1185 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1186 struct radv_image *image,
1187 int idx,
1188 uint32_t color_values[2])
1189 {
1190 uint64_t va = radv_buffer_get_va(image->bo);
1191 va += image->offset + image->clear_value_offset;
1192
1193 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1194
1195 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1196 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1197 S_370_WR_CONFIRM(1) |
1198 S_370_ENGINE_SEL(V_370_PFP));
1199 radeon_emit(cmd_buffer->cs, va);
1200 radeon_emit(cmd_buffer->cs, va >> 32);
1201 radeon_emit(cmd_buffer->cs, color_values[0]);
1202 radeon_emit(cmd_buffer->cs, color_values[1]);
1203
1204 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1205 radeon_emit(cmd_buffer->cs, color_values[0]);
1206 radeon_emit(cmd_buffer->cs, color_values[1]);
1207 }
1208
1209 static void
1210 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1211 struct radv_image *image,
1212 int idx)
1213 {
1214 uint64_t va = radv_buffer_get_va(image->bo);
1215 va += image->offset + image->clear_value_offset;
1216
1217 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1218 return;
1219
1220 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1221
1222 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1223 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1224 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1225 COPY_DATA_COUNT_SEL);
1226 radeon_emit(cmd_buffer->cs, va);
1227 radeon_emit(cmd_buffer->cs, va >> 32);
1228 radeon_emit(cmd_buffer->cs, reg >> 2);
1229 radeon_emit(cmd_buffer->cs, 0);
1230
1231 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1232 radeon_emit(cmd_buffer->cs, 0);
1233 }
1234
1235 static void
1236 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1237 {
1238 int i;
1239 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1240 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1241
1242 /* this may happen for inherited secondary recording */
1243 if (!framebuffer)
1244 return;
1245
1246 for (i = 0; i < 8; ++i) {
1247 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1248 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1249 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1250 continue;
1251 }
1252
1253 int idx = subpass->color_attachments[i].attachment;
1254 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1255 struct radv_image *image = att->attachment->image;
1256 VkImageLayout layout = subpass->color_attachments[i].layout;
1257
1258 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1259
1260 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1261 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1262
1263 radv_load_color_clear_regs(cmd_buffer, image, i);
1264 }
1265
1266 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1267 int idx = subpass->depth_stencil_attachment.attachment;
1268 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1269 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1270 struct radv_image *image = att->attachment->image;
1271 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1272 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1273 cmd_buffer->queue_family_index,
1274 cmd_buffer->queue_family_index);
1275 /* We currently don't support writing decompressed HTILE */
1276 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1277 radv_layout_is_htile_compressed(image, layout, queue_mask));
1278
1279 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1280
1281 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1282 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1283 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1284 }
1285 radv_load_depth_clear_regs(cmd_buffer, image);
1286 } else {
1287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1288 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1289 else
1290 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1291
1292 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1293 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1294 }
1295 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1296 S_028208_BR_X(framebuffer->width) |
1297 S_028208_BR_Y(framebuffer->height));
1298
1299 if (cmd_buffer->device->dfsm_allowed) {
1300 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1301 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1302 }
1303
1304 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1305 }
1306
1307 static void
1308 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1309 {
1310 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1311 struct radv_cmd_state *state = &cmd_buffer->state;
1312
1313 if (state->index_type != state->last_index_type) {
1314 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1315 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1316 2, state->index_type);
1317 } else {
1318 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1319 radeon_emit(cs, state->index_type);
1320 }
1321
1322 state->last_index_type = state->index_type;
1323 }
1324
1325 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1326 radeon_emit(cs, state->index_va);
1327 radeon_emit(cs, state->index_va >> 32);
1328
1329 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1330 radeon_emit(cs, state->max_index_count);
1331
1332 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1333 }
1334
1335 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1336 {
1337 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1338 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1339 uint32_t pa_sc_mode_cntl_1 =
1340 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1341 uint32_t db_count_control;
1342
1343 if(!cmd_buffer->state.active_occlusion_queries) {
1344 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1345 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1346 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1347 has_perfect_queries) {
1348 /* Re-enable out-of-order rasterization if the
1349 * bound pipeline supports it and if it's has
1350 * been disabled before starting any perfect
1351 * occlusion queries.
1352 */
1353 radeon_set_context_reg(cmd_buffer->cs,
1354 R_028A4C_PA_SC_MODE_CNTL_1,
1355 pa_sc_mode_cntl_1);
1356 }
1357 db_count_control = 0;
1358 } else {
1359 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1360 }
1361 } else {
1362 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1363 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1364
1365 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1366 db_count_control =
1367 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1368 S_028004_SAMPLE_RATE(sample_rate) |
1369 S_028004_ZPASS_ENABLE(1) |
1370 S_028004_SLICE_EVEN_ENABLE(1) |
1371 S_028004_SLICE_ODD_ENABLE(1);
1372
1373 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1374 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1375 has_perfect_queries) {
1376 /* If the bound pipeline has enabled
1377 * out-of-order rasterization, we should
1378 * disable it before starting any perfect
1379 * occlusion queries.
1380 */
1381 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1382
1383 radeon_set_context_reg(cmd_buffer->cs,
1384 R_028A4C_PA_SC_MODE_CNTL_1,
1385 pa_sc_mode_cntl_1);
1386 }
1387 } else {
1388 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1389 S_028004_SAMPLE_RATE(sample_rate);
1390 }
1391 }
1392
1393 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1394 }
1395
1396 static void
1397 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1400
1401 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1402 radv_emit_viewport(cmd_buffer);
1403
1404 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1405 radv_emit_scissor(cmd_buffer);
1406
1407 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1408 radv_emit_line_width(cmd_buffer);
1409
1410 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1411 radv_emit_blend_constants(cmd_buffer);
1412
1413 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1414 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1415 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1416 radv_emit_stencil(cmd_buffer);
1417
1418 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1419 radv_emit_depth_bounds(cmd_buffer);
1420
1421 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1422 radv_emit_depth_bias(cmd_buffer);
1423
1424 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1425 radv_emit_discard_rectangle(cmd_buffer);
1426
1427 cmd_buffer->state.dirty &= ~states;
1428 }
1429
1430 static void
1431 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1432 struct radv_pipeline *pipeline,
1433 int idx,
1434 uint64_t va,
1435 gl_shader_stage stage)
1436 {
1437 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1438 uint32_t base_reg = pipeline->user_data_0[stage];
1439
1440 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1441 return;
1442
1443 assert(!desc_set_loc->indirect);
1444 assert(desc_set_loc->num_sgprs == 2);
1445
1446 radv_emit_shader_pointer(cmd_buffer->cs,
1447 base_reg + desc_set_loc->sgpr_idx * 4, va);
1448 }
1449
1450 static void
1451 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1452 VkShaderStageFlags stages,
1453 struct radv_descriptor_set *set,
1454 unsigned idx)
1455 {
1456 if (cmd_buffer->state.pipeline) {
1457 radv_foreach_stage(stage, stages) {
1458 if (cmd_buffer->state.pipeline->shaders[stage])
1459 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1460 idx, set->va,
1461 stage);
1462 }
1463 }
1464
1465 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1466 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1467 idx, set->va,
1468 MESA_SHADER_COMPUTE);
1469 }
1470
1471 static void
1472 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1473 VkPipelineBindPoint bind_point)
1474 {
1475 struct radv_descriptor_state *descriptors_state =
1476 radv_get_descriptors_state(cmd_buffer, bind_point);
1477 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1478 unsigned bo_offset;
1479
1480 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1481 set->mapped_ptr,
1482 &bo_offset))
1483 return;
1484
1485 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1486 set->va += bo_offset;
1487 }
1488
1489 static void
1490 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1491 VkPipelineBindPoint bind_point)
1492 {
1493 struct radv_descriptor_state *descriptors_state =
1494 radv_get_descriptors_state(cmd_buffer, bind_point);
1495 uint32_t size = MAX_SETS * 2 * 4;
1496 uint32_t offset;
1497 void *ptr;
1498
1499 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1500 256, &offset, &ptr))
1501 return;
1502
1503 for (unsigned i = 0; i < MAX_SETS; i++) {
1504 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1505 uint64_t set_va = 0;
1506 struct radv_descriptor_set *set = descriptors_state->sets[i];
1507 if (descriptors_state->valid & (1u << i))
1508 set_va = set->va;
1509 uptr[0] = set_va & 0xffffffff;
1510 uptr[1] = set_va >> 32;
1511 }
1512
1513 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1514 va += offset;
1515
1516 if (cmd_buffer->state.pipeline) {
1517 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1518 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1519 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1520
1521 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1522 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1523 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1524
1525 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1526 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1527 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1528
1529 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1530 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1531 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1532
1533 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1534 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1535 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1536 }
1537
1538 if (cmd_buffer->state.compute_pipeline)
1539 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1540 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1541 }
1542
1543 static void
1544 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1545 VkShaderStageFlags stages)
1546 {
1547 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1548 VK_PIPELINE_BIND_POINT_COMPUTE :
1549 VK_PIPELINE_BIND_POINT_GRAPHICS;
1550 struct radv_descriptor_state *descriptors_state =
1551 radv_get_descriptors_state(cmd_buffer, bind_point);
1552 unsigned i;
1553
1554 if (!descriptors_state->dirty)
1555 return;
1556
1557 if (descriptors_state->push_dirty)
1558 radv_flush_push_descriptors(cmd_buffer, bind_point);
1559
1560 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1561 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1562 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1563 }
1564
1565 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1566 cmd_buffer->cs,
1567 MAX_SETS * MESA_SHADER_STAGES * 4);
1568
1569 for_each_bit(i, descriptors_state->dirty) {
1570 struct radv_descriptor_set *set = descriptors_state->sets[i];
1571 if (!(descriptors_state->valid & (1u << i)))
1572 continue;
1573
1574 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1575 }
1576 descriptors_state->dirty = 0;
1577 descriptors_state->push_dirty = false;
1578
1579 if (unlikely(cmd_buffer->device->trace_bo))
1580 radv_save_descriptors(cmd_buffer, bind_point);
1581
1582 assert(cmd_buffer->cs->cdw <= cdw_max);
1583 }
1584
1585 static void
1586 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1587 VkShaderStageFlags stages)
1588 {
1589 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1590 ? cmd_buffer->state.compute_pipeline
1591 : cmd_buffer->state.pipeline;
1592 struct radv_pipeline_layout *layout = pipeline->layout;
1593 unsigned offset;
1594 void *ptr;
1595 uint64_t va;
1596
1597 stages &= cmd_buffer->push_constant_stages;
1598 if (!stages ||
1599 (!layout->push_constant_size && !layout->dynamic_offset_count))
1600 return;
1601
1602 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1603 16 * layout->dynamic_offset_count,
1604 256, &offset, &ptr))
1605 return;
1606
1607 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1608 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1609 16 * layout->dynamic_offset_count);
1610
1611 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1612 va += offset;
1613
1614 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1615 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1616
1617 radv_foreach_stage(stage, stages) {
1618 if (pipeline->shaders[stage]) {
1619 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1620 AC_UD_PUSH_CONSTANTS, va);
1621 }
1622 }
1623
1624 cmd_buffer->push_constant_stages &= ~stages;
1625 assert(cmd_buffer->cs->cdw <= cdw_max);
1626 }
1627
1628 static void
1629 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1630 bool pipeline_is_dirty)
1631 {
1632 if ((pipeline_is_dirty ||
1633 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1634 cmd_buffer->state.pipeline->vertex_elements.count &&
1635 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1636 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1637 unsigned vb_offset;
1638 void *vb_ptr;
1639 uint32_t i = 0;
1640 uint32_t count = velems->count;
1641 uint64_t va;
1642
1643 /* allocate some descriptor state for vertex buffers */
1644 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1645 &vb_offset, &vb_ptr))
1646 return;
1647
1648 for (i = 0; i < count; i++) {
1649 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1650 uint32_t offset;
1651 int vb = velems->binding[i];
1652 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1653 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1654
1655 va = radv_buffer_get_va(buffer->bo);
1656
1657 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1658 va += offset + buffer->offset;
1659 desc[0] = va;
1660 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1661 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1662 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1663 else
1664 desc[2] = buffer->size - offset;
1665 desc[3] = velems->rsrc_word3[i];
1666 }
1667
1668 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1669 va += vb_offset;
1670
1671 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1672 AC_UD_VS_VERTEX_BUFFERS, va);
1673
1674 cmd_buffer->state.vb_va = va;
1675 cmd_buffer->state.vb_size = count * 16;
1676 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1677 }
1678 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1679 }
1680
1681 static void
1682 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1683 {
1684 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1685 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1686 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1687 }
1688
1689 static void
1690 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1691 bool instanced_draw, bool indirect_draw,
1692 uint32_t draw_vertex_count)
1693 {
1694 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1695 struct radv_cmd_state *state = &cmd_buffer->state;
1696 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1697 uint32_t ia_multi_vgt_param;
1698 int32_t primitive_reset_en;
1699
1700 /* Draw state. */
1701 ia_multi_vgt_param =
1702 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1703 indirect_draw, draw_vertex_count);
1704
1705 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1706 if (info->chip_class >= GFX9) {
1707 radeon_set_uconfig_reg_idx(cs,
1708 R_030960_IA_MULTI_VGT_PARAM,
1709 4, ia_multi_vgt_param);
1710 } else if (info->chip_class >= CIK) {
1711 radeon_set_context_reg_idx(cs,
1712 R_028AA8_IA_MULTI_VGT_PARAM,
1713 1, ia_multi_vgt_param);
1714 } else {
1715 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1716 ia_multi_vgt_param);
1717 }
1718 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1719 }
1720
1721 /* Primitive restart. */
1722 primitive_reset_en =
1723 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1724
1725 if (primitive_reset_en != state->last_primitive_reset_en) {
1726 state->last_primitive_reset_en = primitive_reset_en;
1727 if (info->chip_class >= GFX9) {
1728 radeon_set_uconfig_reg(cs,
1729 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1730 primitive_reset_en);
1731 } else {
1732 radeon_set_context_reg(cs,
1733 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1734 primitive_reset_en);
1735 }
1736 }
1737
1738 if (primitive_reset_en) {
1739 uint32_t primitive_reset_index =
1740 state->index_type ? 0xffffffffu : 0xffffu;
1741
1742 if (primitive_reset_index != state->last_primitive_reset_index) {
1743 radeon_set_context_reg(cs,
1744 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1745 primitive_reset_index);
1746 state->last_primitive_reset_index = primitive_reset_index;
1747 }
1748 }
1749 }
1750
1751 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1752 VkPipelineStageFlags src_stage_mask)
1753 {
1754 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1755 VK_PIPELINE_STAGE_TRANSFER_BIT |
1756 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1757 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1758 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1759 }
1760
1761 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1762 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1763 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1764 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1765 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1766 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1767 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1768 VK_PIPELINE_STAGE_TRANSFER_BIT |
1769 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1770 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1771 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1772 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1773 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1774 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1775 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1776 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1777 }
1778 }
1779
1780 static enum radv_cmd_flush_bits
1781 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1782 VkAccessFlags src_flags)
1783 {
1784 enum radv_cmd_flush_bits flush_bits = 0;
1785 uint32_t b;
1786 for_each_bit(b, src_flags) {
1787 switch ((VkAccessFlagBits)(1 << b)) {
1788 case VK_ACCESS_SHADER_WRITE_BIT:
1789 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1790 break;
1791 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1792 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1793 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1794 break;
1795 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1796 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1797 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1798 break;
1799 case VK_ACCESS_TRANSFER_WRITE_BIT:
1800 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1801 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1802 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1803 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1804 RADV_CMD_FLAG_INV_GLOBAL_L2;
1805 break;
1806 default:
1807 break;
1808 }
1809 }
1810 return flush_bits;
1811 }
1812
1813 static enum radv_cmd_flush_bits
1814 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1815 VkAccessFlags dst_flags,
1816 struct radv_image *image)
1817 {
1818 enum radv_cmd_flush_bits flush_bits = 0;
1819 uint32_t b;
1820 for_each_bit(b, dst_flags) {
1821 switch ((VkAccessFlagBits)(1 << b)) {
1822 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1823 case VK_ACCESS_INDEX_READ_BIT:
1824 break;
1825 case VK_ACCESS_UNIFORM_READ_BIT:
1826 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1827 break;
1828 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1829 case VK_ACCESS_SHADER_READ_BIT:
1830 case VK_ACCESS_TRANSFER_READ_BIT:
1831 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1832 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1833 RADV_CMD_FLAG_INV_GLOBAL_L2;
1834 break;
1835 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1836 /* TODO: change to image && when the image gets passed
1837 * through from the subpass. */
1838 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1839 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1840 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1841 break;
1842 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1843 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1844 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1845 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1846 break;
1847 default:
1848 break;
1849 }
1850 }
1851 return flush_bits;
1852 }
1853
1854 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1855 {
1856 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1857 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1858 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1859 NULL);
1860 }
1861
1862 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1863 VkAttachmentReference att)
1864 {
1865 unsigned idx = att.attachment;
1866 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1867 VkImageSubresourceRange range;
1868 range.aspectMask = 0;
1869 range.baseMipLevel = view->base_mip;
1870 range.levelCount = 1;
1871 range.baseArrayLayer = view->base_layer;
1872 range.layerCount = cmd_buffer->state.framebuffer->layers;
1873
1874 radv_handle_image_transition(cmd_buffer,
1875 view->image,
1876 cmd_buffer->state.attachments[idx].current_layout,
1877 att.layout, 0, 0, &range,
1878 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1879
1880 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1881
1882
1883 }
1884
1885 void
1886 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1887 const struct radv_subpass *subpass, bool transitions)
1888 {
1889 if (transitions) {
1890 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1891
1892 for (unsigned i = 0; i < subpass->color_count; ++i) {
1893 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1894 radv_handle_subpass_image_transition(cmd_buffer,
1895 subpass->color_attachments[i]);
1896 }
1897
1898 for (unsigned i = 0; i < subpass->input_count; ++i) {
1899 radv_handle_subpass_image_transition(cmd_buffer,
1900 subpass->input_attachments[i]);
1901 }
1902
1903 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1904 radv_handle_subpass_image_transition(cmd_buffer,
1905 subpass->depth_stencil_attachment);
1906 }
1907 }
1908
1909 cmd_buffer->state.subpass = subpass;
1910
1911 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1912 }
1913
1914 static VkResult
1915 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1916 struct radv_render_pass *pass,
1917 const VkRenderPassBeginInfo *info)
1918 {
1919 struct radv_cmd_state *state = &cmd_buffer->state;
1920
1921 if (pass->attachment_count == 0) {
1922 state->attachments = NULL;
1923 return VK_SUCCESS;
1924 }
1925
1926 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1927 pass->attachment_count *
1928 sizeof(state->attachments[0]),
1929 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1930 if (state->attachments == NULL) {
1931 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1932 return cmd_buffer->record_result;
1933 }
1934
1935 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1936 struct radv_render_pass_attachment *att = &pass->attachments[i];
1937 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1938 VkImageAspectFlags clear_aspects = 0;
1939
1940 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1941 /* color attachment */
1942 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1943 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1944 }
1945 } else {
1946 /* depthstencil attachment */
1947 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1948 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1949 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1950 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1951 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1952 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1953 }
1954 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1955 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1956 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1957 }
1958 }
1959
1960 state->attachments[i].pending_clear_aspects = clear_aspects;
1961 state->attachments[i].cleared_views = 0;
1962 if (clear_aspects && info) {
1963 assert(info->clearValueCount > i);
1964 state->attachments[i].clear_value = info->pClearValues[i];
1965 }
1966
1967 state->attachments[i].current_layout = att->initial_layout;
1968 }
1969
1970 return VK_SUCCESS;
1971 }
1972
1973 VkResult radv_AllocateCommandBuffers(
1974 VkDevice _device,
1975 const VkCommandBufferAllocateInfo *pAllocateInfo,
1976 VkCommandBuffer *pCommandBuffers)
1977 {
1978 RADV_FROM_HANDLE(radv_device, device, _device);
1979 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1980
1981 VkResult result = VK_SUCCESS;
1982 uint32_t i;
1983
1984 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1985
1986 if (!list_empty(&pool->free_cmd_buffers)) {
1987 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1988
1989 list_del(&cmd_buffer->pool_link);
1990 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1991
1992 result = radv_reset_cmd_buffer(cmd_buffer);
1993 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1994 cmd_buffer->level = pAllocateInfo->level;
1995
1996 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1997 } else {
1998 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1999 &pCommandBuffers[i]);
2000 }
2001 if (result != VK_SUCCESS)
2002 break;
2003 }
2004
2005 if (result != VK_SUCCESS) {
2006 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2007 i, pCommandBuffers);
2008
2009 /* From the Vulkan 1.0.66 spec:
2010 *
2011 * "vkAllocateCommandBuffers can be used to create multiple
2012 * command buffers. If the creation of any of those command
2013 * buffers fails, the implementation must destroy all
2014 * successfully created command buffer objects from this
2015 * command, set all entries of the pCommandBuffers array to
2016 * NULL and return the error."
2017 */
2018 memset(pCommandBuffers, 0,
2019 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2020 }
2021
2022 return result;
2023 }
2024
2025 void radv_FreeCommandBuffers(
2026 VkDevice device,
2027 VkCommandPool commandPool,
2028 uint32_t commandBufferCount,
2029 const VkCommandBuffer *pCommandBuffers)
2030 {
2031 for (uint32_t i = 0; i < commandBufferCount; i++) {
2032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2033
2034 if (cmd_buffer) {
2035 if (cmd_buffer->pool) {
2036 list_del(&cmd_buffer->pool_link);
2037 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2038 } else
2039 radv_cmd_buffer_destroy(cmd_buffer);
2040
2041 }
2042 }
2043 }
2044
2045 VkResult radv_ResetCommandBuffer(
2046 VkCommandBuffer commandBuffer,
2047 VkCommandBufferResetFlags flags)
2048 {
2049 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2050 return radv_reset_cmd_buffer(cmd_buffer);
2051 }
2052
2053 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2054 {
2055 struct radv_device *device = cmd_buffer->device;
2056 if (device->gfx_init) {
2057 uint64_t va = radv_buffer_get_va(device->gfx_init);
2058 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2059 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2060 radeon_emit(cmd_buffer->cs, va);
2061 radeon_emit(cmd_buffer->cs, va >> 32);
2062 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2063 } else
2064 si_init_config(cmd_buffer);
2065 }
2066
2067 VkResult radv_BeginCommandBuffer(
2068 VkCommandBuffer commandBuffer,
2069 const VkCommandBufferBeginInfo *pBeginInfo)
2070 {
2071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2072 VkResult result = VK_SUCCESS;
2073
2074 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2075 /* If the command buffer has already been resetted with
2076 * vkResetCommandBuffer, no need to do it again.
2077 */
2078 result = radv_reset_cmd_buffer(cmd_buffer);
2079 if (result != VK_SUCCESS)
2080 return result;
2081 }
2082
2083 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2084 cmd_buffer->state.last_primitive_reset_en = -1;
2085 cmd_buffer->state.last_index_type = -1;
2086 cmd_buffer->state.last_num_instances = -1;
2087 cmd_buffer->state.last_vertex_offset = -1;
2088 cmd_buffer->state.last_first_instance = -1;
2089 cmd_buffer->usage_flags = pBeginInfo->flags;
2090
2091 /* setup initial configuration into command buffer */
2092 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2093 switch (cmd_buffer->queue_family_index) {
2094 case RADV_QUEUE_GENERAL:
2095 emit_gfx_buffer_state(cmd_buffer);
2096 break;
2097 case RADV_QUEUE_COMPUTE:
2098 si_init_compute(cmd_buffer);
2099 break;
2100 case RADV_QUEUE_TRANSFER:
2101 default:
2102 break;
2103 }
2104 }
2105
2106 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2107 assert(pBeginInfo->pInheritanceInfo);
2108 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2109 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2110
2111 struct radv_subpass *subpass =
2112 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2113
2114 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2115 if (result != VK_SUCCESS)
2116 return result;
2117
2118 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2119 }
2120
2121 if (unlikely(cmd_buffer->device->trace_bo))
2122 radv_cmd_buffer_trace_emit(cmd_buffer);
2123
2124 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2125
2126 return result;
2127 }
2128
2129 void radv_CmdBindVertexBuffers(
2130 VkCommandBuffer commandBuffer,
2131 uint32_t firstBinding,
2132 uint32_t bindingCount,
2133 const VkBuffer* pBuffers,
2134 const VkDeviceSize* pOffsets)
2135 {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2137 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2138 bool changed = false;
2139
2140 /* We have to defer setting up vertex buffer since we need the buffer
2141 * stride from the pipeline. */
2142
2143 assert(firstBinding + bindingCount <= MAX_VBS);
2144 for (uint32_t i = 0; i < bindingCount; i++) {
2145 uint32_t idx = firstBinding + i;
2146
2147 if (!changed &&
2148 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2149 vb[idx].offset != pOffsets[i])) {
2150 changed = true;
2151 }
2152
2153 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2154 vb[idx].offset = pOffsets[i];
2155
2156 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2157 vb[idx].buffer->bo, 8);
2158 }
2159
2160 if (!changed) {
2161 /* No state changes. */
2162 return;
2163 }
2164
2165 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2166 }
2167
2168 void radv_CmdBindIndexBuffer(
2169 VkCommandBuffer commandBuffer,
2170 VkBuffer buffer,
2171 VkDeviceSize offset,
2172 VkIndexType indexType)
2173 {
2174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2175 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2176
2177 if (cmd_buffer->state.index_buffer == index_buffer &&
2178 cmd_buffer->state.index_offset == offset &&
2179 cmd_buffer->state.index_type == indexType) {
2180 /* No state changes. */
2181 return;
2182 }
2183
2184 cmd_buffer->state.index_buffer = index_buffer;
2185 cmd_buffer->state.index_offset = offset;
2186 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2187 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2188 cmd_buffer->state.index_va += index_buffer->offset + offset;
2189
2190 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2191 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2192 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2193 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2194 }
2195
2196
2197 static void
2198 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2199 VkPipelineBindPoint bind_point,
2200 struct radv_descriptor_set *set, unsigned idx)
2201 {
2202 struct radeon_winsys *ws = cmd_buffer->device->ws;
2203
2204 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2205 if (!set)
2206 return;
2207
2208 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2209
2210 if (!cmd_buffer->device->use_global_bo_list) {
2211 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2212 if (set->descriptors[j])
2213 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2214 }
2215
2216 if(set->bo)
2217 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2218 }
2219
2220 void radv_CmdBindDescriptorSets(
2221 VkCommandBuffer commandBuffer,
2222 VkPipelineBindPoint pipelineBindPoint,
2223 VkPipelineLayout _layout,
2224 uint32_t firstSet,
2225 uint32_t descriptorSetCount,
2226 const VkDescriptorSet* pDescriptorSets,
2227 uint32_t dynamicOffsetCount,
2228 const uint32_t* pDynamicOffsets)
2229 {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2231 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2232 unsigned dyn_idx = 0;
2233
2234 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2235
2236 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2237 unsigned idx = i + firstSet;
2238 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2239 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2240
2241 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2242 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2243 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2244 assert(dyn_idx < dynamicOffsetCount);
2245
2246 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2247 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2248 dst[0] = va;
2249 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2250 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2251 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2252 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2253 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2254 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2255 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2257 cmd_buffer->push_constant_stages |=
2258 set->layout->dynamic_shader_stages;
2259 }
2260 }
2261 }
2262
2263 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2264 struct radv_descriptor_set *set,
2265 struct radv_descriptor_set_layout *layout,
2266 VkPipelineBindPoint bind_point)
2267 {
2268 struct radv_descriptor_state *descriptors_state =
2269 radv_get_descriptors_state(cmd_buffer, bind_point);
2270 set->size = layout->size;
2271 set->layout = layout;
2272
2273 if (descriptors_state->push_set.capacity < set->size) {
2274 size_t new_size = MAX2(set->size, 1024);
2275 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2276 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2277
2278 free(set->mapped_ptr);
2279 set->mapped_ptr = malloc(new_size);
2280
2281 if (!set->mapped_ptr) {
2282 descriptors_state->push_set.capacity = 0;
2283 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2284 return false;
2285 }
2286
2287 descriptors_state->push_set.capacity = new_size;
2288 }
2289
2290 return true;
2291 }
2292
2293 void radv_meta_push_descriptor_set(
2294 struct radv_cmd_buffer* cmd_buffer,
2295 VkPipelineBindPoint pipelineBindPoint,
2296 VkPipelineLayout _layout,
2297 uint32_t set,
2298 uint32_t descriptorWriteCount,
2299 const VkWriteDescriptorSet* pDescriptorWrites)
2300 {
2301 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2302 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2303 unsigned bo_offset;
2304
2305 assert(set == 0);
2306 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2307
2308 push_set->size = layout->set[set].layout->size;
2309 push_set->layout = layout->set[set].layout;
2310
2311 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2312 &bo_offset,
2313 (void**) &push_set->mapped_ptr))
2314 return;
2315
2316 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2317 push_set->va += bo_offset;
2318
2319 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2320 radv_descriptor_set_to_handle(push_set),
2321 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2322
2323 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2324 }
2325
2326 void radv_CmdPushDescriptorSetKHR(
2327 VkCommandBuffer commandBuffer,
2328 VkPipelineBindPoint pipelineBindPoint,
2329 VkPipelineLayout _layout,
2330 uint32_t set,
2331 uint32_t descriptorWriteCount,
2332 const VkWriteDescriptorSet* pDescriptorWrites)
2333 {
2334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2335 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2336 struct radv_descriptor_state *descriptors_state =
2337 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2338 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2339
2340 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2341
2342 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2343 layout->set[set].layout,
2344 pipelineBindPoint))
2345 return;
2346
2347 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2348 radv_descriptor_set_to_handle(push_set),
2349 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2350
2351 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2352 descriptors_state->push_dirty = true;
2353 }
2354
2355 void radv_CmdPushDescriptorSetWithTemplateKHR(
2356 VkCommandBuffer commandBuffer,
2357 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2358 VkPipelineLayout _layout,
2359 uint32_t set,
2360 const void* pData)
2361 {
2362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2363 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2364 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2365 struct radv_descriptor_state *descriptors_state =
2366 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2367 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2368
2369 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2370
2371 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2372 layout->set[set].layout,
2373 templ->bind_point))
2374 return;
2375
2376 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2377 descriptorUpdateTemplate, pData);
2378
2379 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2380 descriptors_state->push_dirty = true;
2381 }
2382
2383 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2384 VkPipelineLayout layout,
2385 VkShaderStageFlags stageFlags,
2386 uint32_t offset,
2387 uint32_t size,
2388 const void* pValues)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2392 cmd_buffer->push_constant_stages |= stageFlags;
2393 }
2394
2395 VkResult radv_EndCommandBuffer(
2396 VkCommandBuffer commandBuffer)
2397 {
2398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399
2400 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2401 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2402 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2403 si_emit_cache_flush(cmd_buffer);
2404 }
2405
2406 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2407
2408 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2409 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2410
2411 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2412
2413 return cmd_buffer->record_result;
2414 }
2415
2416 static void
2417 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2418 {
2419 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2420
2421 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2422 return;
2423
2424 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2425
2426 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2427 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2428
2429 cmd_buffer->compute_scratch_size_needed =
2430 MAX2(cmd_buffer->compute_scratch_size_needed,
2431 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2432
2433 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2434 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2435
2436 if (unlikely(cmd_buffer->device->trace_bo))
2437 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2438 }
2439
2440 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2441 VkPipelineBindPoint bind_point)
2442 {
2443 struct radv_descriptor_state *descriptors_state =
2444 radv_get_descriptors_state(cmd_buffer, bind_point);
2445
2446 descriptors_state->dirty |= descriptors_state->valid;
2447 }
2448
2449 void radv_CmdBindPipeline(
2450 VkCommandBuffer commandBuffer,
2451 VkPipelineBindPoint pipelineBindPoint,
2452 VkPipeline _pipeline)
2453 {
2454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2455 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2456
2457 switch (pipelineBindPoint) {
2458 case VK_PIPELINE_BIND_POINT_COMPUTE:
2459 if (cmd_buffer->state.compute_pipeline == pipeline)
2460 return;
2461 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2462
2463 cmd_buffer->state.compute_pipeline = pipeline;
2464 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2465 break;
2466 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2467 if (cmd_buffer->state.pipeline == pipeline)
2468 return;
2469 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2470
2471 cmd_buffer->state.pipeline = pipeline;
2472 if (!pipeline)
2473 break;
2474
2475 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2476 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2477
2478 /* the new vertex shader might not have the same user regs */
2479 cmd_buffer->state.last_first_instance = -1;
2480 cmd_buffer->state.last_vertex_offset = -1;
2481
2482 /* Prefetch all pipeline shaders at first draw time. */
2483 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2484
2485 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2486
2487 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2488 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2489 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2490 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2491
2492 if (radv_pipeline_has_tess(pipeline))
2493 cmd_buffer->tess_rings_needed = true;
2494
2495 if (radv_pipeline_has_gs(pipeline)) {
2496 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2497 AC_UD_SCRATCH_RING_OFFSETS);
2498 if (cmd_buffer->ring_offsets_idx == -1)
2499 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2500 else if (loc->sgpr_idx != -1)
2501 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2502 }
2503 break;
2504 default:
2505 assert(!"invalid bind point");
2506 break;
2507 }
2508 }
2509
2510 void radv_CmdSetViewport(
2511 VkCommandBuffer commandBuffer,
2512 uint32_t firstViewport,
2513 uint32_t viewportCount,
2514 const VkViewport* pViewports)
2515 {
2516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2517 struct radv_cmd_state *state = &cmd_buffer->state;
2518 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2519
2520 assert(firstViewport < MAX_VIEWPORTS);
2521 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2522
2523 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2524 /* Try to skip unnecessary PS partial flushes when the viewports
2525 * don't change.
2526 */
2527 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2528 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2529 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2530 pViewports, viewportCount * sizeof(*pViewports))) {
2531 return;
2532 }
2533 }
2534
2535 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2536 viewportCount * sizeof(*pViewports));
2537
2538 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2539 }
2540
2541 void radv_CmdSetScissor(
2542 VkCommandBuffer commandBuffer,
2543 uint32_t firstScissor,
2544 uint32_t scissorCount,
2545 const VkRect2D* pScissors)
2546 {
2547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2548 struct radv_cmd_state *state = &cmd_buffer->state;
2549 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2550
2551 assert(firstScissor < MAX_SCISSORS);
2552 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2553
2554 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2555 /* Try to skip unnecessary PS partial flushes when the scissors
2556 * don't change.
2557 */
2558 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2559 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2560 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2561 pScissors, scissorCount * sizeof(*pScissors))) {
2562 return;
2563 }
2564 }
2565
2566 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2567 scissorCount * sizeof(*pScissors));
2568
2569 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2570 }
2571
2572 void radv_CmdSetLineWidth(
2573 VkCommandBuffer commandBuffer,
2574 float lineWidth)
2575 {
2576 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2577 cmd_buffer->state.dynamic.line_width = lineWidth;
2578 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2579 }
2580
2581 void radv_CmdSetDepthBias(
2582 VkCommandBuffer commandBuffer,
2583 float depthBiasConstantFactor,
2584 float depthBiasClamp,
2585 float depthBiasSlopeFactor)
2586 {
2587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2588
2589 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2590 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2591 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2592
2593 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2594 }
2595
2596 void radv_CmdSetBlendConstants(
2597 VkCommandBuffer commandBuffer,
2598 const float blendConstants[4])
2599 {
2600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2601
2602 memcpy(cmd_buffer->state.dynamic.blend_constants,
2603 blendConstants, sizeof(float) * 4);
2604
2605 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2606 }
2607
2608 void radv_CmdSetDepthBounds(
2609 VkCommandBuffer commandBuffer,
2610 float minDepthBounds,
2611 float maxDepthBounds)
2612 {
2613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2614
2615 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2616 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2617
2618 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2619 }
2620
2621 void radv_CmdSetStencilCompareMask(
2622 VkCommandBuffer commandBuffer,
2623 VkStencilFaceFlags faceMask,
2624 uint32_t compareMask)
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627
2628 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2629 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2630 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2631 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2632
2633 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2634 }
2635
2636 void radv_CmdSetStencilWriteMask(
2637 VkCommandBuffer commandBuffer,
2638 VkStencilFaceFlags faceMask,
2639 uint32_t writeMask)
2640 {
2641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2642
2643 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2644 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2645 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2646 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2647
2648 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2649 }
2650
2651 void radv_CmdSetStencilReference(
2652 VkCommandBuffer commandBuffer,
2653 VkStencilFaceFlags faceMask,
2654 uint32_t reference)
2655 {
2656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2657
2658 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2659 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2660 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2661 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2662
2663 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2664 }
2665
2666 void radv_CmdSetDiscardRectangleEXT(
2667 VkCommandBuffer commandBuffer,
2668 uint32_t firstDiscardRectangle,
2669 uint32_t discardRectangleCount,
2670 const VkRect2D* pDiscardRectangles)
2671 {
2672 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2673 struct radv_cmd_state *state = &cmd_buffer->state;
2674 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2675
2676 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2677 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2678
2679 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2680 pDiscardRectangles, discardRectangleCount);
2681
2682 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2683 }
2684
2685 void radv_CmdExecuteCommands(
2686 VkCommandBuffer commandBuffer,
2687 uint32_t commandBufferCount,
2688 const VkCommandBuffer* pCmdBuffers)
2689 {
2690 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2691
2692 assert(commandBufferCount > 0);
2693
2694 /* Emit pending flushes on primary prior to executing secondary */
2695 si_emit_cache_flush(primary);
2696
2697 for (uint32_t i = 0; i < commandBufferCount; i++) {
2698 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2699
2700 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2701 secondary->scratch_size_needed);
2702 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2703 secondary->compute_scratch_size_needed);
2704
2705 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2706 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2707 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2708 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2709 if (secondary->tess_rings_needed)
2710 primary->tess_rings_needed = true;
2711 if (secondary->sample_positions_needed)
2712 primary->sample_positions_needed = true;
2713
2714 if (secondary->ring_offsets_idx != -1) {
2715 if (primary->ring_offsets_idx == -1)
2716 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2717 else
2718 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2719 }
2720 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2721
2722
2723 /* When the secondary command buffer is compute only we don't
2724 * need to re-emit the current graphics pipeline.
2725 */
2726 if (secondary->state.emitted_pipeline) {
2727 primary->state.emitted_pipeline =
2728 secondary->state.emitted_pipeline;
2729 }
2730
2731 /* When the secondary command buffer is graphics only we don't
2732 * need to re-emit the current compute pipeline.
2733 */
2734 if (secondary->state.emitted_compute_pipeline) {
2735 primary->state.emitted_compute_pipeline =
2736 secondary->state.emitted_compute_pipeline;
2737 }
2738
2739 /* Only re-emit the draw packets when needed. */
2740 if (secondary->state.last_primitive_reset_en != -1) {
2741 primary->state.last_primitive_reset_en =
2742 secondary->state.last_primitive_reset_en;
2743 }
2744
2745 if (secondary->state.last_primitive_reset_index) {
2746 primary->state.last_primitive_reset_index =
2747 secondary->state.last_primitive_reset_index;
2748 }
2749
2750 if (secondary->state.last_ia_multi_vgt_param) {
2751 primary->state.last_ia_multi_vgt_param =
2752 secondary->state.last_ia_multi_vgt_param;
2753 }
2754
2755 primary->state.last_first_instance = secondary->state.last_first_instance;
2756 primary->state.last_num_instances = secondary->state.last_num_instances;
2757 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2758
2759 if (secondary->state.last_index_type != -1) {
2760 primary->state.last_index_type =
2761 secondary->state.last_index_type;
2762 }
2763 }
2764
2765 /* After executing commands from secondary buffers we have to dirty
2766 * some states.
2767 */
2768 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2769 RADV_CMD_DIRTY_INDEX_BUFFER |
2770 RADV_CMD_DIRTY_DYNAMIC_ALL;
2771 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2772 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2773 }
2774
2775 VkResult radv_CreateCommandPool(
2776 VkDevice _device,
2777 const VkCommandPoolCreateInfo* pCreateInfo,
2778 const VkAllocationCallbacks* pAllocator,
2779 VkCommandPool* pCmdPool)
2780 {
2781 RADV_FROM_HANDLE(radv_device, device, _device);
2782 struct radv_cmd_pool *pool;
2783
2784 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2785 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2786 if (pool == NULL)
2787 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2788
2789 if (pAllocator)
2790 pool->alloc = *pAllocator;
2791 else
2792 pool->alloc = device->alloc;
2793
2794 list_inithead(&pool->cmd_buffers);
2795 list_inithead(&pool->free_cmd_buffers);
2796
2797 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2798
2799 *pCmdPool = radv_cmd_pool_to_handle(pool);
2800
2801 return VK_SUCCESS;
2802
2803 }
2804
2805 void radv_DestroyCommandPool(
2806 VkDevice _device,
2807 VkCommandPool commandPool,
2808 const VkAllocationCallbacks* pAllocator)
2809 {
2810 RADV_FROM_HANDLE(radv_device, device, _device);
2811 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2812
2813 if (!pool)
2814 return;
2815
2816 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2817 &pool->cmd_buffers, pool_link) {
2818 radv_cmd_buffer_destroy(cmd_buffer);
2819 }
2820
2821 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2822 &pool->free_cmd_buffers, pool_link) {
2823 radv_cmd_buffer_destroy(cmd_buffer);
2824 }
2825
2826 vk_free2(&device->alloc, pAllocator, pool);
2827 }
2828
2829 VkResult radv_ResetCommandPool(
2830 VkDevice device,
2831 VkCommandPool commandPool,
2832 VkCommandPoolResetFlags flags)
2833 {
2834 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2835 VkResult result;
2836
2837 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2838 &pool->cmd_buffers, pool_link) {
2839 result = radv_reset_cmd_buffer(cmd_buffer);
2840 if (result != VK_SUCCESS)
2841 return result;
2842 }
2843
2844 return VK_SUCCESS;
2845 }
2846
2847 void radv_TrimCommandPool(
2848 VkDevice device,
2849 VkCommandPool commandPool,
2850 VkCommandPoolTrimFlagsKHR flags)
2851 {
2852 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2853
2854 if (!pool)
2855 return;
2856
2857 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2858 &pool->free_cmd_buffers, pool_link) {
2859 radv_cmd_buffer_destroy(cmd_buffer);
2860 }
2861 }
2862
2863 void radv_CmdBeginRenderPass(
2864 VkCommandBuffer commandBuffer,
2865 const VkRenderPassBeginInfo* pRenderPassBegin,
2866 VkSubpassContents contents)
2867 {
2868 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2869 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2870 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2871
2872 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2873 cmd_buffer->cs, 2048);
2874 MAYBE_UNUSED VkResult result;
2875
2876 cmd_buffer->state.framebuffer = framebuffer;
2877 cmd_buffer->state.pass = pass;
2878 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2879
2880 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2881 if (result != VK_SUCCESS)
2882 return;
2883
2884 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2885 assert(cmd_buffer->cs->cdw <= cdw_max);
2886
2887 radv_cmd_buffer_clear_subpass(cmd_buffer);
2888 }
2889
2890 void radv_CmdNextSubpass(
2891 VkCommandBuffer commandBuffer,
2892 VkSubpassContents contents)
2893 {
2894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2895
2896 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2897
2898 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2899 2048);
2900
2901 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2902 radv_cmd_buffer_clear_subpass(cmd_buffer);
2903 }
2904
2905 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2906 {
2907 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2908 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2909 if (!pipeline->shaders[stage])
2910 continue;
2911 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2912 if (loc->sgpr_idx == -1)
2913 continue;
2914 uint32_t base_reg = pipeline->user_data_0[stage];
2915 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2916
2917 }
2918 if (pipeline->gs_copy_shader) {
2919 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2920 if (loc->sgpr_idx != -1) {
2921 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2922 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2923 }
2924 }
2925 }
2926
2927 static void
2928 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2929 uint32_t vertex_count)
2930 {
2931 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2932 radeon_emit(cmd_buffer->cs, vertex_count);
2933 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2934 S_0287F0_USE_OPAQUE(0));
2935 }
2936
2937 static void
2938 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2939 uint64_t index_va,
2940 uint32_t index_count)
2941 {
2942 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2943 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2944 radeon_emit(cmd_buffer->cs, index_va);
2945 radeon_emit(cmd_buffer->cs, index_va >> 32);
2946 radeon_emit(cmd_buffer->cs, index_count);
2947 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2948 }
2949
2950 static void
2951 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2952 bool indexed,
2953 uint32_t draw_count,
2954 uint64_t count_va,
2955 uint32_t stride)
2956 {
2957 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2958 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2959 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2960 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2961 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2962 assert(base_reg);
2963
2964 /* just reset draw state for vertex data */
2965 cmd_buffer->state.last_first_instance = -1;
2966 cmd_buffer->state.last_num_instances = -1;
2967 cmd_buffer->state.last_vertex_offset = -1;
2968
2969 if (draw_count == 1 && !count_va && !draw_id_enable) {
2970 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2971 PKT3_DRAW_INDIRECT, 3, false));
2972 radeon_emit(cs, 0);
2973 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2974 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2975 radeon_emit(cs, di_src_sel);
2976 } else {
2977 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2978 PKT3_DRAW_INDIRECT_MULTI,
2979 8, false));
2980 radeon_emit(cs, 0);
2981 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2982 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2983 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2984 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2985 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2986 radeon_emit(cs, draw_count); /* count */
2987 radeon_emit(cs, count_va); /* count_addr */
2988 radeon_emit(cs, count_va >> 32);
2989 radeon_emit(cs, stride); /* stride */
2990 radeon_emit(cs, di_src_sel);
2991 }
2992 }
2993
2994 struct radv_draw_info {
2995 /**
2996 * Number of vertices.
2997 */
2998 uint32_t count;
2999
3000 /**
3001 * Index of the first vertex.
3002 */
3003 int32_t vertex_offset;
3004
3005 /**
3006 * First instance id.
3007 */
3008 uint32_t first_instance;
3009
3010 /**
3011 * Number of instances.
3012 */
3013 uint32_t instance_count;
3014
3015 /**
3016 * First index (indexed draws only).
3017 */
3018 uint32_t first_index;
3019
3020 /**
3021 * Whether it's an indexed draw.
3022 */
3023 bool indexed;
3024
3025 /**
3026 * Indirect draw parameters resource.
3027 */
3028 struct radv_buffer *indirect;
3029 uint64_t indirect_offset;
3030 uint32_t stride;
3031
3032 /**
3033 * Draw count parameters resource.
3034 */
3035 struct radv_buffer *count_buffer;
3036 uint64_t count_buffer_offset;
3037 };
3038
3039 static void
3040 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3041 const struct radv_draw_info *info)
3042 {
3043 struct radv_cmd_state *state = &cmd_buffer->state;
3044 struct radeon_winsys *ws = cmd_buffer->device->ws;
3045 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3046
3047 if (info->indirect) {
3048 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3049 uint64_t count_va = 0;
3050
3051 va += info->indirect->offset + info->indirect_offset;
3052
3053 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3054
3055 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3056 radeon_emit(cs, 1);
3057 radeon_emit(cs, va);
3058 radeon_emit(cs, va >> 32);
3059
3060 if (info->count_buffer) {
3061 count_va = radv_buffer_get_va(info->count_buffer->bo);
3062 count_va += info->count_buffer->offset +
3063 info->count_buffer_offset;
3064
3065 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3066 }
3067
3068 if (!state->subpass->view_mask) {
3069 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3070 info->indexed,
3071 info->count,
3072 count_va,
3073 info->stride);
3074 } else {
3075 unsigned i;
3076 for_each_bit(i, state->subpass->view_mask) {
3077 radv_emit_view_index(cmd_buffer, i);
3078
3079 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3080 info->indexed,
3081 info->count,
3082 count_va,
3083 info->stride);
3084 }
3085 }
3086 } else {
3087 assert(state->pipeline->graphics.vtx_base_sgpr);
3088
3089 if (info->vertex_offset != state->last_vertex_offset ||
3090 info->first_instance != state->last_first_instance) {
3091 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3092 state->pipeline->graphics.vtx_emit_num);
3093
3094 radeon_emit(cs, info->vertex_offset);
3095 radeon_emit(cs, info->first_instance);
3096 if (state->pipeline->graphics.vtx_emit_num == 3)
3097 radeon_emit(cs, 0);
3098 state->last_first_instance = info->first_instance;
3099 state->last_vertex_offset = info->vertex_offset;
3100 }
3101
3102 if (state->last_num_instances != info->instance_count) {
3103 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3104 radeon_emit(cs, info->instance_count);
3105 state->last_num_instances = info->instance_count;
3106 }
3107
3108 if (info->indexed) {
3109 int index_size = state->index_type ? 4 : 2;
3110 uint64_t index_va;
3111
3112 index_va = state->index_va;
3113 index_va += info->first_index * index_size;
3114
3115 if (!state->subpass->view_mask) {
3116 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3117 index_va,
3118 info->count);
3119 } else {
3120 unsigned i;
3121 for_each_bit(i, state->subpass->view_mask) {
3122 radv_emit_view_index(cmd_buffer, i);
3123
3124 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3125 index_va,
3126 info->count);
3127 }
3128 }
3129 } else {
3130 if (!state->subpass->view_mask) {
3131 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3132 } else {
3133 unsigned i;
3134 for_each_bit(i, state->subpass->view_mask) {
3135 radv_emit_view_index(cmd_buffer, i);
3136
3137 radv_cs_emit_draw_packet(cmd_buffer,
3138 info->count);
3139 }
3140 }
3141 }
3142 }
3143 }
3144
3145 static void
3146 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3147 const struct radv_draw_info *info)
3148 {
3149 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3150 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3151 radv_emit_rbplus_state(cmd_buffer);
3152
3153 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3154 radv_emit_graphics_pipeline(cmd_buffer);
3155
3156 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3157 radv_emit_framebuffer_state(cmd_buffer);
3158
3159 if (info->indexed) {
3160 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3161 radv_emit_index_buffer(cmd_buffer);
3162 } else {
3163 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3164 * so the state must be re-emitted before the next indexed
3165 * draw.
3166 */
3167 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3168 cmd_buffer->state.last_index_type = -1;
3169 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3170 }
3171 }
3172
3173 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3174
3175 radv_emit_draw_registers(cmd_buffer, info->indexed,
3176 info->instance_count > 1, info->indirect,
3177 info->indirect ? 0 : info->count);
3178 }
3179
3180 static void
3181 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3182 const struct radv_draw_info *info)
3183 {
3184 bool has_prefetch =
3185 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3186 bool pipeline_is_dirty =
3187 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3188 cmd_buffer->state.pipeline &&
3189 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3190
3191 MAYBE_UNUSED unsigned cdw_max =
3192 radeon_check_space(cmd_buffer->device->ws,
3193 cmd_buffer->cs, 4096);
3194
3195 /* Use optimal packet order based on whether we need to sync the
3196 * pipeline.
3197 */
3198 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3199 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3200 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3201 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3202 /* If we have to wait for idle, set all states first, so that
3203 * all SET packets are processed in parallel with previous draw
3204 * calls. Then upload descriptors, set shader pointers, and
3205 * draw, and prefetch at the end. This ensures that the time
3206 * the CUs are idle is very short. (there are only SET_SH
3207 * packets between the wait and the draw)
3208 */
3209 radv_emit_all_graphics_states(cmd_buffer, info);
3210 si_emit_cache_flush(cmd_buffer);
3211 /* <-- CUs are idle here --> */
3212
3213 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3214
3215 radv_emit_draw_packets(cmd_buffer, info);
3216 /* <-- CUs are busy here --> */
3217
3218 /* Start prefetches after the draw has been started. Both will
3219 * run in parallel, but starting the draw first is more
3220 * important.
3221 */
3222 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3223 radv_emit_prefetch_L2(cmd_buffer,
3224 cmd_buffer->state.pipeline, false);
3225 }
3226 } else {
3227 /* If we don't wait for idle, start prefetches first, then set
3228 * states, and draw at the end.
3229 */
3230 si_emit_cache_flush(cmd_buffer);
3231
3232 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3233 /* Only prefetch the vertex shader and VBO descriptors
3234 * in order to start the draw as soon as possible.
3235 */
3236 radv_emit_prefetch_L2(cmd_buffer,
3237 cmd_buffer->state.pipeline, true);
3238 }
3239
3240 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3241
3242 radv_emit_all_graphics_states(cmd_buffer, info);
3243 radv_emit_draw_packets(cmd_buffer, info);
3244
3245 /* Prefetch the remaining shaders after the draw has been
3246 * started.
3247 */
3248 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3249 radv_emit_prefetch_L2(cmd_buffer,
3250 cmd_buffer->state.pipeline, false);
3251 }
3252 }
3253
3254 assert(cmd_buffer->cs->cdw <= cdw_max);
3255 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3256 }
3257
3258 void radv_CmdDraw(
3259 VkCommandBuffer commandBuffer,
3260 uint32_t vertexCount,
3261 uint32_t instanceCount,
3262 uint32_t firstVertex,
3263 uint32_t firstInstance)
3264 {
3265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3266 struct radv_draw_info info = {};
3267
3268 info.count = vertexCount;
3269 info.instance_count = instanceCount;
3270 info.first_instance = firstInstance;
3271 info.vertex_offset = firstVertex;
3272
3273 radv_draw(cmd_buffer, &info);
3274 }
3275
3276 void radv_CmdDrawIndexed(
3277 VkCommandBuffer commandBuffer,
3278 uint32_t indexCount,
3279 uint32_t instanceCount,
3280 uint32_t firstIndex,
3281 int32_t vertexOffset,
3282 uint32_t firstInstance)
3283 {
3284 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3285 struct radv_draw_info info = {};
3286
3287 info.indexed = true;
3288 info.count = indexCount;
3289 info.instance_count = instanceCount;
3290 info.first_index = firstIndex;
3291 info.vertex_offset = vertexOffset;
3292 info.first_instance = firstInstance;
3293
3294 radv_draw(cmd_buffer, &info);
3295 }
3296
3297 void radv_CmdDrawIndirect(
3298 VkCommandBuffer commandBuffer,
3299 VkBuffer _buffer,
3300 VkDeviceSize offset,
3301 uint32_t drawCount,
3302 uint32_t stride)
3303 {
3304 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3305 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3306 struct radv_draw_info info = {};
3307
3308 info.count = drawCount;
3309 info.indirect = buffer;
3310 info.indirect_offset = offset;
3311 info.stride = stride;
3312
3313 radv_draw(cmd_buffer, &info);
3314 }
3315
3316 void radv_CmdDrawIndexedIndirect(
3317 VkCommandBuffer commandBuffer,
3318 VkBuffer _buffer,
3319 VkDeviceSize offset,
3320 uint32_t drawCount,
3321 uint32_t stride)
3322 {
3323 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3324 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3325 struct radv_draw_info info = {};
3326
3327 info.indexed = true;
3328 info.count = drawCount;
3329 info.indirect = buffer;
3330 info.indirect_offset = offset;
3331 info.stride = stride;
3332
3333 radv_draw(cmd_buffer, &info);
3334 }
3335
3336 void radv_CmdDrawIndirectCountAMD(
3337 VkCommandBuffer commandBuffer,
3338 VkBuffer _buffer,
3339 VkDeviceSize offset,
3340 VkBuffer _countBuffer,
3341 VkDeviceSize countBufferOffset,
3342 uint32_t maxDrawCount,
3343 uint32_t stride)
3344 {
3345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3346 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3347 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3348 struct radv_draw_info info = {};
3349
3350 info.count = maxDrawCount;
3351 info.indirect = buffer;
3352 info.indirect_offset = offset;
3353 info.count_buffer = count_buffer;
3354 info.count_buffer_offset = countBufferOffset;
3355 info.stride = stride;
3356
3357 radv_draw(cmd_buffer, &info);
3358 }
3359
3360 void radv_CmdDrawIndexedIndirectCountAMD(
3361 VkCommandBuffer commandBuffer,
3362 VkBuffer _buffer,
3363 VkDeviceSize offset,
3364 VkBuffer _countBuffer,
3365 VkDeviceSize countBufferOffset,
3366 uint32_t maxDrawCount,
3367 uint32_t stride)
3368 {
3369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3370 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3371 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3372 struct radv_draw_info info = {};
3373
3374 info.indexed = true;
3375 info.count = maxDrawCount;
3376 info.indirect = buffer;
3377 info.indirect_offset = offset;
3378 info.count_buffer = count_buffer;
3379 info.count_buffer_offset = countBufferOffset;
3380 info.stride = stride;
3381
3382 radv_draw(cmd_buffer, &info);
3383 }
3384
3385 struct radv_dispatch_info {
3386 /**
3387 * Determine the layout of the grid (in block units) to be used.
3388 */
3389 uint32_t blocks[3];
3390
3391 /**
3392 * A starting offset for the grid. If unaligned is set, the offset
3393 * must still be aligned.
3394 */
3395 uint32_t offsets[3];
3396 /**
3397 * Whether it's an unaligned compute dispatch.
3398 */
3399 bool unaligned;
3400
3401 /**
3402 * Indirect compute parameters resource.
3403 */
3404 struct radv_buffer *indirect;
3405 uint64_t indirect_offset;
3406 };
3407
3408 static void
3409 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3410 const struct radv_dispatch_info *info)
3411 {
3412 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3413 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3414 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3415 struct radeon_winsys *ws = cmd_buffer->device->ws;
3416 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3417 struct radv_userdata_info *loc;
3418
3419 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3420 AC_UD_CS_GRID_SIZE);
3421
3422 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3423
3424 if (info->indirect) {
3425 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3426
3427 va += info->indirect->offset + info->indirect_offset;
3428
3429 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3430
3431 if (loc->sgpr_idx != -1) {
3432 for (unsigned i = 0; i < 3; ++i) {
3433 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3434 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3435 COPY_DATA_DST_SEL(COPY_DATA_REG));
3436 radeon_emit(cs, (va + 4 * i));
3437 radeon_emit(cs, (va + 4 * i) >> 32);
3438 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3439 + loc->sgpr_idx * 4) >> 2) + i);
3440 radeon_emit(cs, 0);
3441 }
3442 }
3443
3444 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3445 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3446 PKT3_SHADER_TYPE_S(1));
3447 radeon_emit(cs, va);
3448 radeon_emit(cs, va >> 32);
3449 radeon_emit(cs, dispatch_initiator);
3450 } else {
3451 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3452 PKT3_SHADER_TYPE_S(1));
3453 radeon_emit(cs, 1);
3454 radeon_emit(cs, va);
3455 radeon_emit(cs, va >> 32);
3456
3457 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3458 PKT3_SHADER_TYPE_S(1));
3459 radeon_emit(cs, 0);
3460 radeon_emit(cs, dispatch_initiator);
3461 }
3462 } else {
3463 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3464 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3465
3466 if (info->unaligned) {
3467 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3468 unsigned remainder[3];
3469
3470 /* If aligned, these should be an entire block size,
3471 * not 0.
3472 */
3473 remainder[0] = blocks[0] + cs_block_size[0] -
3474 align_u32_npot(blocks[0], cs_block_size[0]);
3475 remainder[1] = blocks[1] + cs_block_size[1] -
3476 align_u32_npot(blocks[1], cs_block_size[1]);
3477 remainder[2] = blocks[2] + cs_block_size[2] -
3478 align_u32_npot(blocks[2], cs_block_size[2]);
3479
3480 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3481 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3482 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3483
3484 for(unsigned i = 0; i < 3; ++i) {
3485 assert(offsets[i] % cs_block_size[i] == 0);
3486 offsets[i] /= cs_block_size[i];
3487 }
3488
3489 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3490 radeon_emit(cs,
3491 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3492 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3493 radeon_emit(cs,
3494 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3495 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3496 radeon_emit(cs,
3497 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3498 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3499
3500 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3501 }
3502
3503 if (loc->sgpr_idx != -1) {
3504 assert(!loc->indirect);
3505 assert(loc->num_sgprs == 3);
3506
3507 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3508 loc->sgpr_idx * 4, 3);
3509 radeon_emit(cs, blocks[0]);
3510 radeon_emit(cs, blocks[1]);
3511 radeon_emit(cs, blocks[2]);
3512 }
3513
3514 if (offsets[0] || offsets[1] || offsets[2]) {
3515 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3516 radeon_emit(cs, offsets[0]);
3517 radeon_emit(cs, offsets[1]);
3518 radeon_emit(cs, offsets[2]);
3519
3520 /* The blocks in the packet are not counts but end values. */
3521 for (unsigned i = 0; i < 3; ++i)
3522 blocks[i] += offsets[i];
3523 } else {
3524 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3525 }
3526
3527 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3528 PKT3_SHADER_TYPE_S(1));
3529 radeon_emit(cs, blocks[0]);
3530 radeon_emit(cs, blocks[1]);
3531 radeon_emit(cs, blocks[2]);
3532 radeon_emit(cs, dispatch_initiator);
3533 }
3534
3535 assert(cmd_buffer->cs->cdw <= cdw_max);
3536 }
3537
3538 static void
3539 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3540 {
3541 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3542 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3543 }
3544
3545 static void
3546 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3547 const struct radv_dispatch_info *info)
3548 {
3549 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3550 bool has_prefetch =
3551 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3552 bool pipeline_is_dirty = pipeline &&
3553 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3554
3555 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3556 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3557 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3558 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3559 /* If we have to wait for idle, set all states first, so that
3560 * all SET packets are processed in parallel with previous draw
3561 * calls. Then upload descriptors, set shader pointers, and
3562 * dispatch, and prefetch at the end. This ensures that the
3563 * time the CUs are idle is very short. (there are only SET_SH
3564 * packets between the wait and the draw)
3565 */
3566 radv_emit_compute_pipeline(cmd_buffer);
3567 si_emit_cache_flush(cmd_buffer);
3568 /* <-- CUs are idle here --> */
3569
3570 radv_upload_compute_shader_descriptors(cmd_buffer);
3571
3572 radv_emit_dispatch_packets(cmd_buffer, info);
3573 /* <-- CUs are busy here --> */
3574
3575 /* Start prefetches after the dispatch has been started. Both
3576 * will run in parallel, but starting the dispatch first is
3577 * more important.
3578 */
3579 if (has_prefetch && pipeline_is_dirty) {
3580 radv_emit_shader_prefetch(cmd_buffer,
3581 pipeline->shaders[MESA_SHADER_COMPUTE]);
3582 }
3583 } else {
3584 /* If we don't wait for idle, start prefetches first, then set
3585 * states, and dispatch at the end.
3586 */
3587 si_emit_cache_flush(cmd_buffer);
3588
3589 if (has_prefetch && pipeline_is_dirty) {
3590 radv_emit_shader_prefetch(cmd_buffer,
3591 pipeline->shaders[MESA_SHADER_COMPUTE]);
3592 }
3593
3594 radv_upload_compute_shader_descriptors(cmd_buffer);
3595
3596 radv_emit_compute_pipeline(cmd_buffer);
3597 radv_emit_dispatch_packets(cmd_buffer, info);
3598 }
3599
3600 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3601 }
3602
3603 void radv_CmdDispatchBase(
3604 VkCommandBuffer commandBuffer,
3605 uint32_t base_x,
3606 uint32_t base_y,
3607 uint32_t base_z,
3608 uint32_t x,
3609 uint32_t y,
3610 uint32_t z)
3611 {
3612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3613 struct radv_dispatch_info info = {};
3614
3615 info.blocks[0] = x;
3616 info.blocks[1] = y;
3617 info.blocks[2] = z;
3618
3619 info.offsets[0] = base_x;
3620 info.offsets[1] = base_y;
3621 info.offsets[2] = base_z;
3622 radv_dispatch(cmd_buffer, &info);
3623 }
3624
3625 void radv_CmdDispatch(
3626 VkCommandBuffer commandBuffer,
3627 uint32_t x,
3628 uint32_t y,
3629 uint32_t z)
3630 {
3631 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3632 }
3633
3634 void radv_CmdDispatchIndirect(
3635 VkCommandBuffer commandBuffer,
3636 VkBuffer _buffer,
3637 VkDeviceSize offset)
3638 {
3639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3640 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3641 struct radv_dispatch_info info = {};
3642
3643 info.indirect = buffer;
3644 info.indirect_offset = offset;
3645
3646 radv_dispatch(cmd_buffer, &info);
3647 }
3648
3649 void radv_unaligned_dispatch(
3650 struct radv_cmd_buffer *cmd_buffer,
3651 uint32_t x,
3652 uint32_t y,
3653 uint32_t z)
3654 {
3655 struct radv_dispatch_info info = {};
3656
3657 info.blocks[0] = x;
3658 info.blocks[1] = y;
3659 info.blocks[2] = z;
3660 info.unaligned = 1;
3661
3662 radv_dispatch(cmd_buffer, &info);
3663 }
3664
3665 void radv_CmdEndRenderPass(
3666 VkCommandBuffer commandBuffer)
3667 {
3668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3669
3670 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3671
3672 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3673
3674 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3675 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3676 radv_handle_subpass_image_transition(cmd_buffer,
3677 (VkAttachmentReference){i, layout});
3678 }
3679
3680 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3681
3682 cmd_buffer->state.pass = NULL;
3683 cmd_buffer->state.subpass = NULL;
3684 cmd_buffer->state.attachments = NULL;
3685 cmd_buffer->state.framebuffer = NULL;
3686 }
3687
3688 /*
3689 * For HTILE we have the following interesting clear words:
3690 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3691 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3692 * 0xfffffff0: Clear depth to 1.0
3693 * 0x00000000: Clear depth to 0.0
3694 */
3695 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3696 struct radv_image *image,
3697 const VkImageSubresourceRange *range,
3698 uint32_t clear_word)
3699 {
3700 assert(range->baseMipLevel == 0);
3701 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3702 unsigned layer_count = radv_get_layerCount(image, range);
3703 uint64_t size = image->surface.htile_slice_size * layer_count;
3704 uint64_t offset = image->offset + image->htile_offset +
3705 image->surface.htile_slice_size * range->baseArrayLayer;
3706 struct radv_cmd_state *state = &cmd_buffer->state;
3707
3708 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3709 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3710
3711 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3712 size, clear_word);
3713
3714 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3715 }
3716
3717 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3718 struct radv_image *image,
3719 VkImageLayout src_layout,
3720 VkImageLayout dst_layout,
3721 unsigned src_queue_mask,
3722 unsigned dst_queue_mask,
3723 const VkImageSubresourceRange *range,
3724 VkImageAspectFlags pending_clears)
3725 {
3726 if (!radv_image_has_htile(image))
3727 return;
3728
3729 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3730 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3731 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3732 cmd_buffer->state.render_area.extent.width == image->info.width &&
3733 cmd_buffer->state.render_area.extent.height == image->info.height) {
3734 /* The clear will initialize htile. */
3735 return;
3736 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3737 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3738 /* TODO: merge with the clear if applicable */
3739 radv_initialize_htile(cmd_buffer, image, range, 0);
3740 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3741 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3742 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3743 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3744 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3745 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3746 VkImageSubresourceRange local_range = *range;
3747 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3748 local_range.baseMipLevel = 0;
3749 local_range.levelCount = 1;
3750
3751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3752 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3753
3754 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3755
3756 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3757 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3758 }
3759 }
3760
3761 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3762 struct radv_image *image, uint32_t value)
3763 {
3764 struct radv_cmd_state *state = &cmd_buffer->state;
3765
3766 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3767 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3768
3769 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3770
3771 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3772 }
3773
3774 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3775 struct radv_image *image, uint32_t value)
3776 {
3777 struct radv_cmd_state *state = &cmd_buffer->state;
3778
3779 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3780 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3781
3782 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3783
3784 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3785 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3786 }
3787
3788 /**
3789 * Initialize DCC/FMASK/CMASK metadata for a color image.
3790 */
3791 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
3792 struct radv_image *image,
3793 VkImageLayout src_layout,
3794 VkImageLayout dst_layout,
3795 unsigned src_queue_mask,
3796 unsigned dst_queue_mask)
3797 {
3798 if (radv_image_has_cmask(image)) {
3799 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3800
3801 /* TODO: clarify this. */
3802 if (radv_image_has_fmask(image)) {
3803 value = 0xccccccccu;
3804 }
3805
3806 radv_initialise_cmask(cmd_buffer, image, value);
3807 }
3808
3809 if (radv_image_has_dcc(image)) {
3810 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3811
3812 if (radv_layout_dcc_compressed(image, dst_layout,
3813 dst_queue_mask)) {
3814 value = 0x20202020u;
3815 }
3816
3817 radv_initialize_dcc(cmd_buffer, image, value);
3818 }
3819 }
3820
3821 /**
3822 * Handle color image transitions for DCC/FMASK/CMASK.
3823 */
3824 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3825 struct radv_image *image,
3826 VkImageLayout src_layout,
3827 VkImageLayout dst_layout,
3828 unsigned src_queue_mask,
3829 unsigned dst_queue_mask,
3830 const VkImageSubresourceRange *range)
3831 {
3832 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3833 radv_init_color_image_metadata(cmd_buffer, image,
3834 src_layout, dst_layout,
3835 src_queue_mask, dst_queue_mask);
3836 return;
3837 }
3838
3839 if (radv_image_has_dcc(image)) {
3840 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3841 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3842 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3843 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3844 radv_decompress_dcc(cmd_buffer, image, range);
3845 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3846 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3847 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3848 }
3849 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
3850 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3851 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3852 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3853 }
3854 }
3855 }
3856
3857 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3858 struct radv_image *image,
3859 VkImageLayout src_layout,
3860 VkImageLayout dst_layout,
3861 uint32_t src_family,
3862 uint32_t dst_family,
3863 const VkImageSubresourceRange *range,
3864 VkImageAspectFlags pending_clears)
3865 {
3866 if (image->exclusive && src_family != dst_family) {
3867 /* This is an acquire or a release operation and there will be
3868 * a corresponding release/acquire. Do the transition in the
3869 * most flexible queue. */
3870
3871 assert(src_family == cmd_buffer->queue_family_index ||
3872 dst_family == cmd_buffer->queue_family_index);
3873
3874 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3875 return;
3876
3877 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3878 (src_family == RADV_QUEUE_GENERAL ||
3879 dst_family == RADV_QUEUE_GENERAL))
3880 return;
3881 }
3882
3883 unsigned src_queue_mask =
3884 radv_image_queue_family_mask(image, src_family,
3885 cmd_buffer->queue_family_index);
3886 unsigned dst_queue_mask =
3887 radv_image_queue_family_mask(image, dst_family,
3888 cmd_buffer->queue_family_index);
3889
3890 if (vk_format_is_depth(image->vk_format)) {
3891 radv_handle_depth_image_transition(cmd_buffer, image,
3892 src_layout, dst_layout,
3893 src_queue_mask, dst_queue_mask,
3894 range, pending_clears);
3895 } else {
3896 radv_handle_color_image_transition(cmd_buffer, image,
3897 src_layout, dst_layout,
3898 src_queue_mask, dst_queue_mask,
3899 range);
3900 }
3901 }
3902
3903 void radv_CmdPipelineBarrier(
3904 VkCommandBuffer commandBuffer,
3905 VkPipelineStageFlags srcStageMask,
3906 VkPipelineStageFlags destStageMask,
3907 VkBool32 byRegion,
3908 uint32_t memoryBarrierCount,
3909 const VkMemoryBarrier* pMemoryBarriers,
3910 uint32_t bufferMemoryBarrierCount,
3911 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3912 uint32_t imageMemoryBarrierCount,
3913 const VkImageMemoryBarrier* pImageMemoryBarriers)
3914 {
3915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3916 enum radv_cmd_flush_bits src_flush_bits = 0;
3917 enum radv_cmd_flush_bits dst_flush_bits = 0;
3918
3919 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3920 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3921 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3922 NULL);
3923 }
3924
3925 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3926 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3927 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3928 NULL);
3929 }
3930
3931 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3932 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3933 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3934 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3935 image);
3936 }
3937
3938 radv_stage_flush(cmd_buffer, srcStageMask);
3939 cmd_buffer->state.flush_bits |= src_flush_bits;
3940
3941 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3942 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3943 radv_handle_image_transition(cmd_buffer, image,
3944 pImageMemoryBarriers[i].oldLayout,
3945 pImageMemoryBarriers[i].newLayout,
3946 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3947 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3948 &pImageMemoryBarriers[i].subresourceRange,
3949 0);
3950 }
3951
3952 cmd_buffer->state.flush_bits |= dst_flush_bits;
3953 }
3954
3955
3956 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3957 struct radv_event *event,
3958 VkPipelineStageFlags stageMask,
3959 unsigned value)
3960 {
3961 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3962 uint64_t va = radv_buffer_get_va(event->bo);
3963
3964 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3965
3966 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3967
3968 /* TODO: this is overkill. Probably should figure something out from
3969 * the stage mask. */
3970
3971 si_cs_emit_write_event_eop(cs,
3972 cmd_buffer->state.predicating,
3973 cmd_buffer->device->physical_device->rad_info.chip_class,
3974 radv_cmd_buffer_uses_mec(cmd_buffer),
3975 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3976 1, va, 2, value);
3977
3978 assert(cmd_buffer->cs->cdw <= cdw_max);
3979 }
3980
3981 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3982 VkEvent _event,
3983 VkPipelineStageFlags stageMask)
3984 {
3985 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3986 RADV_FROM_HANDLE(radv_event, event, _event);
3987
3988 write_event(cmd_buffer, event, stageMask, 1);
3989 }
3990
3991 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3992 VkEvent _event,
3993 VkPipelineStageFlags stageMask)
3994 {
3995 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3996 RADV_FROM_HANDLE(radv_event, event, _event);
3997
3998 write_event(cmd_buffer, event, stageMask, 0);
3999 }
4000
4001 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4002 uint32_t eventCount,
4003 const VkEvent* pEvents,
4004 VkPipelineStageFlags srcStageMask,
4005 VkPipelineStageFlags dstStageMask,
4006 uint32_t memoryBarrierCount,
4007 const VkMemoryBarrier* pMemoryBarriers,
4008 uint32_t bufferMemoryBarrierCount,
4009 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4010 uint32_t imageMemoryBarrierCount,
4011 const VkImageMemoryBarrier* pImageMemoryBarriers)
4012 {
4013 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4014 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4015
4016 for (unsigned i = 0; i < eventCount; ++i) {
4017 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4018 uint64_t va = radv_buffer_get_va(event->bo);
4019
4020 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4021
4022 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4023
4024 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4025 assert(cmd_buffer->cs->cdw <= cdw_max);
4026 }
4027
4028
4029 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4030 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4031
4032 radv_handle_image_transition(cmd_buffer, image,
4033 pImageMemoryBarriers[i].oldLayout,
4034 pImageMemoryBarriers[i].newLayout,
4035 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4036 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4037 &pImageMemoryBarriers[i].subresourceRange,
4038 0);
4039 }
4040
4041 /* TODO: figure out how to do memory barriers without waiting */
4042 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4043 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4044 RADV_CMD_FLAG_INV_VMEM_L1 |
4045 RADV_CMD_FLAG_INV_SMEM_L1;
4046 }
4047
4048
4049 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4050 uint32_t deviceMask)
4051 {
4052 /* No-op */
4053 }