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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
497 }
498
499 static void
500 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
501 struct radv_pipeline *pipeline,
502 gl_shader_stage stage,
503 int idx, uint64_t va)
504 {
505 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
506 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
507 if (loc->sgpr_idx == -1)
508 return;
509 assert(loc->num_sgprs == 2);
510 assert(!loc->indirect);
511 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
512 radeon_emit(cmd_buffer->cs, va);
513 radeon_emit(cmd_buffer->cs, va >> 32);
514 }
515
516 static void
517 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
518 struct radv_pipeline *pipeline)
519 {
520 int num_samples = pipeline->graphics.ms.num_samples;
521 struct radv_multisample_state *ms = &pipeline->graphics.ms;
522 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
525 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
526 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
527
528 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
529 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
530
531 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
532 return;
533
534 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
535 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
536 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
537
538 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
539
540 /* GFX9: Flush DFSM when the AA mode changes. */
541 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
542 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
543 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
544 }
545 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
546 uint32_t offset;
547 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
548 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
549 if (loc->sgpr_idx == -1)
550 return;
551 assert(loc->num_sgprs == 1);
552 assert(!loc->indirect);
553 switch (num_samples) {
554 default:
555 offset = 0;
556 break;
557 case 2:
558 offset = 1;
559 break;
560 case 4:
561 offset = 3;
562 break;
563 case 8:
564 offset = 7;
565 break;
566 case 16:
567 offset = 15;
568 break;
569 }
570
571 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
572 cmd_buffer->sample_positions_needed = true;
573 }
574 }
575
576 static void
577 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
578 struct radv_pipeline *pipeline)
579 {
580 struct radv_raster_state *raster = &pipeline->graphics.raster;
581
582 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
583 raster->pa_cl_clip_cntl);
584 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
585 raster->spi_interp_control);
586 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
587 raster->pa_su_vtx_cntl);
588 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
589 raster->pa_su_sc_mode_cntl);
590 }
591
592 static inline void
593 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
594 unsigned size)
595 {
596 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
597 si_cp_dma_prefetch(cmd_buffer, va, size);
598 }
599
600 static void
601 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
602 struct radv_pipeline *pipeline,
603 struct radv_shader_variant *shader,
604 struct ac_vs_output_info *outinfo)
605 {
606 struct radeon_winsys *ws = cmd_buffer->device->ws;
607 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
608 unsigned export_count;
609
610 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
611 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
612
613 export_count = MAX2(1, outinfo->param_exports);
614 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
615 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
616
617 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
618 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
619 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
620 V_02870C_SPI_SHADER_4COMP :
621 V_02870C_SPI_SHADER_NONE) |
622 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
623 V_02870C_SPI_SHADER_4COMP :
624 V_02870C_SPI_SHADER_NONE) |
625 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
626 V_02870C_SPI_SHADER_4COMP :
627 V_02870C_SPI_SHADER_NONE));
628
629
630 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
631 radeon_emit(cmd_buffer->cs, va >> 8);
632 radeon_emit(cmd_buffer->cs, va >> 40);
633 radeon_emit(cmd_buffer->cs, shader->rsrc1);
634 radeon_emit(cmd_buffer->cs, shader->rsrc2);
635
636 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
637 S_028818_VTX_W0_FMT(1) |
638 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
639 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
640 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
641
642
643 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
644 pipeline->graphics.pa_cl_vs_out_cntl);
645
646 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
647 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
648 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
649 }
650
651 static void
652 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_shader_variant *shader,
654 struct ac_es_output_info *outinfo)
655 {
656 struct radeon_winsys *ws = cmd_buffer->device->ws;
657 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
658
659 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
660 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
661
662 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
663 outinfo->esgs_itemsize / 4);
664 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
665 radeon_emit(cmd_buffer->cs, va >> 8);
666 radeon_emit(cmd_buffer->cs, va >> 40);
667 radeon_emit(cmd_buffer->cs, shader->rsrc1);
668 radeon_emit(cmd_buffer->cs, shader->rsrc2);
669 }
670
671 static void
672 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 struct radeon_winsys *ws = cmd_buffer->device->ws;
676 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
677 uint32_t rsrc2 = shader->rsrc2;
678
679 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
680 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
681
682 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
683 radeon_emit(cmd_buffer->cs, va >> 8);
684 radeon_emit(cmd_buffer->cs, va >> 40);
685
686 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
687 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
688 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
689 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
690
691 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
692 radeon_emit(cmd_buffer->cs, shader->rsrc1);
693 radeon_emit(cmd_buffer->cs, rsrc2);
694 }
695
696 static void
697 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
698 struct radv_shader_variant *shader)
699 {
700 struct radeon_winsys *ws = cmd_buffer->device->ws;
701 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
702
703 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
704 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
705
706 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
707 radeon_emit(cmd_buffer->cs, va >> 8);
708 radeon_emit(cmd_buffer->cs, va >> 40);
709 radeon_emit(cmd_buffer->cs, shader->rsrc1);
710 radeon_emit(cmd_buffer->cs, shader->rsrc2);
711 }
712
713 static void
714 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
715 struct radv_pipeline *pipeline)
716 {
717 struct radv_shader_variant *vs;
718
719 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
720
721 vs = pipeline->shaders[MESA_SHADER_VERTEX];
722
723 if (vs->info.vs.as_ls)
724 radv_emit_hw_ls(cmd_buffer, vs);
725 else if (vs->info.vs.as_es)
726 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
727 else
728 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
731 }
732
733
734 static void
735 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
736 struct radv_pipeline *pipeline)
737 {
738 if (!radv_pipeline_has_tess(pipeline))
739 return;
740
741 struct radv_shader_variant *tes, *tcs;
742
743 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
744 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
745
746 if (tes->info.tes.as_es)
747 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
748 else
749 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
750
751 radv_emit_hw_hs(cmd_buffer, tcs);
752
753 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
754 pipeline->graphics.tess.tf_param);
755
756 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
757 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
758 pipeline->graphics.tess.ls_hs_config);
759 else
760 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
761 pipeline->graphics.tess.ls_hs_config);
762
763 struct ac_userdata_info *loc;
764
765 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
766 if (loc->sgpr_idx != -1) {
767 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
768 assert(loc->num_sgprs == 4);
769 assert(!loc->indirect);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
771 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
772 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
773 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
774 pipeline->graphics.tess.num_tcs_input_cp << 26);
775 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
776 }
777
778 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
779 if (loc->sgpr_idx != -1) {
780 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
781 assert(loc->num_sgprs == 1);
782 assert(!loc->indirect);
783
784 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
785 pipeline->graphics.tess.offchip_layout);
786 }
787
788 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
789 if (loc->sgpr_idx != -1) {
790 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
791 assert(loc->num_sgprs == 1);
792 assert(!loc->indirect);
793
794 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
795 pipeline->graphics.tess.tcs_in_layout);
796 }
797 }
798
799 static void
800 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
801 struct radv_pipeline *pipeline)
802 {
803 struct radeon_winsys *ws = cmd_buffer->device->ws;
804 struct radv_shader_variant *gs;
805 uint64_t va;
806
807 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
808
809 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
810 if (!gs)
811 return;
812
813 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
814
815 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
816 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
817 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
818 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
819
820 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
821
822 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
823
824 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
826 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
827 radeon_emit(cmd_buffer->cs, 0);
828 radeon_emit(cmd_buffer->cs, 0);
829 radeon_emit(cmd_buffer->cs, 0);
830
831 uint32_t gs_num_invocations = gs->info.gs.invocations;
832 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
833 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
834 S_028B90_ENABLE(gs_num_invocations > 0));
835
836 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
837 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
838 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
839
840 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
841 radeon_emit(cmd_buffer->cs, va >> 8);
842 radeon_emit(cmd_buffer->cs, va >> 40);
843 radeon_emit(cmd_buffer->cs, gs->rsrc1);
844 radeon_emit(cmd_buffer->cs, gs->rsrc2);
845
846 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
847
848 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
849 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
850 if (loc->sgpr_idx != -1) {
851 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
852 uint32_t num_entries = 64;
853 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
854
855 if (is_vi)
856 num_entries *= stride;
857
858 stride = S_008F04_STRIDE(stride);
859 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
860 radeon_emit(cmd_buffer->cs, stride);
861 radeon_emit(cmd_buffer->cs, num_entries);
862 }
863 }
864
865 static void
866 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
867 struct radv_pipeline *pipeline)
868 {
869 struct radeon_winsys *ws = cmd_buffer->device->ws;
870 struct radv_shader_variant *ps;
871 uint64_t va;
872 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
873 struct radv_blend_state *blend = &pipeline->graphics.blend;
874 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
875
876 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
877 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
878 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
879 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
880
881 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
882 radeon_emit(cmd_buffer->cs, va >> 8);
883 radeon_emit(cmd_buffer->cs, va >> 40);
884 radeon_emit(cmd_buffer->cs, ps->rsrc1);
885 radeon_emit(cmd_buffer->cs, ps->rsrc2);
886
887 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
888 pipeline->graphics.db_shader_control);
889
890 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
891 ps->config.spi_ps_input_ena);
892
893 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
894 ps->config.spi_ps_input_addr);
895
896 if (ps->info.info.ps.force_persample)
897 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
898
899 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
900 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
901
902 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
903
904 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
905 pipeline->graphics.shader_z_format);
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
908
909 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
910 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
911
912 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
913 /* optimise this? */
914 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
916 }
917
918 if (pipeline->graphics.ps_input_cntl_num) {
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
920 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
921 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
922 }
923 }
924 }
925
926 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
927 struct radv_pipeline *pipeline)
928 {
929 uint32_t vtx_reuse_depth = 30;
930 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
931 return;
932
933 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
934 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
935 vtx_reuse_depth = 14;
936 }
937 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
938 vtx_reuse_depth);
939 }
940
941 static void
942 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
943 {
944 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
945
946 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
947 return;
948
949 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
950 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
951 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
952 radv_update_multisample_state(cmd_buffer, pipeline);
953 radv_emit_vertex_shader(cmd_buffer, pipeline);
954 radv_emit_tess_shaders(cmd_buffer, pipeline);
955 radv_emit_geometry_shader(cmd_buffer, pipeline);
956 radv_emit_fragment_shader(cmd_buffer, pipeline);
957 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
958
959 cmd_buffer->scratch_size_needed =
960 MAX2(cmd_buffer->scratch_size_needed,
961 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
962
963 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
964 S_0286E8_WAVES(pipeline->max_waves) |
965 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
966
967 if (!cmd_buffer->state.emitted_pipeline ||
968 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
969 pipeline->graphics.can_use_guardband)
970 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
971
972 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
973
974 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
975 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
976 } else {
977 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
978 }
979 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
980
981 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
982
983 cmd_buffer->state.emitted_pipeline = pipeline;
984 }
985
986 static void
987 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
988 {
989 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
990 cmd_buffer->state.dynamic.viewport.viewports);
991 }
992
993 static void
994 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
995 {
996 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
997
998 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
999 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1000 si_emit_cache_flush(cmd_buffer);
1001 }
1002 si_write_scissors(cmd_buffer->cs, 0, count,
1003 cmd_buffer->state.dynamic.scissor.scissors,
1004 cmd_buffer->state.dynamic.viewport.viewports,
1005 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1006 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1007 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1008 }
1009
1010 static void
1011 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1012 {
1013 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1014
1015 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1016 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1017 }
1018
1019 static void
1020 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1021 {
1022 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1025 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1026 }
1027
1028 static void
1029 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1030 {
1031 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1032
1033 radeon_set_context_reg_seq(cmd_buffer->cs,
1034 R_028430_DB_STENCILREFMASK, 2);
1035 radeon_emit(cmd_buffer->cs,
1036 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1037 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1038 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1039 S_028430_STENCILOPVAL(1));
1040 radeon_emit(cmd_buffer->cs,
1041 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1042 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1043 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1044 S_028434_STENCILOPVAL_BF(1));
1045 }
1046
1047 static void
1048 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1049 {
1050 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1051
1052 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1053 fui(d->depth_bounds.min));
1054 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1055 fui(d->depth_bounds.max));
1056 }
1057
1058 static void
1059 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1060 {
1061 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1062 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1063 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1064 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1065
1066 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1067 radeon_set_context_reg_seq(cmd_buffer->cs,
1068 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1069 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1070 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1071 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1072 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1073 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1074 }
1075 }
1076
1077 static void
1078 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1079 int index,
1080 struct radv_color_buffer_info *cb)
1081 {
1082 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1083
1084 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1085 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1086 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1087 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1088 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1089 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1090 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1091 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1092 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1093 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1094 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1095 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1096 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1097
1098 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1099 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1100 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1101
1102 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1103 cb->gfx9_epitch);
1104 } else {
1105 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1106 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1107 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1108 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1109 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1110 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1111 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1112 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1115 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1116 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1117
1118 if (is_vi) { /* DCC BASE */
1119 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1120 }
1121 }
1122 }
1123
1124 static void
1125 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1126 struct radv_ds_buffer_info *ds,
1127 struct radv_image *image,
1128 VkImageLayout layout)
1129 {
1130 uint32_t db_z_info = ds->db_z_info;
1131 uint32_t db_stencil_info = ds->db_stencil_info;
1132
1133 if (!radv_layout_has_htile(image, layout,
1134 radv_image_queue_family_mask(image,
1135 cmd_buffer->queue_family_index,
1136 cmd_buffer->queue_family_index))) {
1137 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1138 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1139 }
1140
1141 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1142 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1143
1144
1145 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1146 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1147 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1148 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1149 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1152 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1153 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1154 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1155 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1156 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1157 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1160 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1162
1163 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1164 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1165 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1166 } else {
1167 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1168
1169 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1170 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1171 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1172 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1173 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1174 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1178 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1179
1180 }
1181
1182 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1183 ds->pa_su_poly_offset_db_fmt_cntl);
1184 }
1185
1186 void
1187 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1188 struct radv_image *image,
1189 VkClearDepthStencilValue ds_clear_value,
1190 VkImageAspectFlags aspects)
1191 {
1192 uint64_t va = radv_buffer_get_va(image->bo);
1193 va += image->offset + image->clear_value_offset;
1194 unsigned reg_offset = 0, reg_count = 0;
1195
1196 if (!image->surface.htile_size || !aspects)
1197 return;
1198
1199 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1200 ++reg_count;
1201 } else {
1202 ++reg_offset;
1203 va += 4;
1204 }
1205 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1206 ++reg_count;
1207
1208 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1209
1210 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1211 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1212 S_370_WR_CONFIRM(1) |
1213 S_370_ENGINE_SEL(V_370_PFP));
1214 radeon_emit(cmd_buffer->cs, va);
1215 radeon_emit(cmd_buffer->cs, va >> 32);
1216 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1217 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1218 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1219 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1220
1221 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1222 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1223 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1224 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1225 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1226 }
1227
1228 static void
1229 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1230 struct radv_image *image)
1231 {
1232 uint64_t va = radv_buffer_get_va(image->bo);
1233 va += image->offset + image->clear_value_offset;
1234
1235 if (!image->surface.htile_size)
1236 return;
1237
1238 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1239
1240 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1241 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1242 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1243 COPY_DATA_COUNT_SEL);
1244 radeon_emit(cmd_buffer->cs, va);
1245 radeon_emit(cmd_buffer->cs, va >> 32);
1246 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1247 radeon_emit(cmd_buffer->cs, 0);
1248
1249 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1250 radeon_emit(cmd_buffer->cs, 0);
1251 }
1252
1253 /*
1254 *with DCC some colors don't require CMASK elimiation before being
1255 * used as a texture. This sets a predicate value to determine if the
1256 * cmask eliminate is required.
1257 */
1258 void
1259 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1260 struct radv_image *image,
1261 bool value)
1262 {
1263 uint64_t pred_val = value;
1264 uint64_t va = radv_buffer_get_va(image->bo);
1265 va += image->offset + image->dcc_pred_offset;
1266
1267 if (!image->surface.dcc_size)
1268 return;
1269
1270 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1271
1272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1273 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1274 S_370_WR_CONFIRM(1) |
1275 S_370_ENGINE_SEL(V_370_PFP));
1276 radeon_emit(cmd_buffer->cs, va);
1277 radeon_emit(cmd_buffer->cs, va >> 32);
1278 radeon_emit(cmd_buffer->cs, pred_val);
1279 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1280 }
1281
1282 void
1283 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1284 struct radv_image *image,
1285 int idx,
1286 uint32_t color_values[2])
1287 {
1288 uint64_t va = radv_buffer_get_va(image->bo);
1289 va += image->offset + image->clear_value_offset;
1290
1291 if (!image->cmask.size && !image->surface.dcc_size)
1292 return;
1293
1294 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1295
1296 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1297 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1298 S_370_WR_CONFIRM(1) |
1299 S_370_ENGINE_SEL(V_370_PFP));
1300 radeon_emit(cmd_buffer->cs, va);
1301 radeon_emit(cmd_buffer->cs, va >> 32);
1302 radeon_emit(cmd_buffer->cs, color_values[0]);
1303 radeon_emit(cmd_buffer->cs, color_values[1]);
1304
1305 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1306 radeon_emit(cmd_buffer->cs, color_values[0]);
1307 radeon_emit(cmd_buffer->cs, color_values[1]);
1308 }
1309
1310 static void
1311 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1312 struct radv_image *image,
1313 int idx)
1314 {
1315 uint64_t va = radv_buffer_get_va(image->bo);
1316 va += image->offset + image->clear_value_offset;
1317
1318 if (!image->cmask.size && !image->surface.dcc_size)
1319 return;
1320
1321 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1322 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1323
1324 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1325 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1326 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1327 COPY_DATA_COUNT_SEL);
1328 radeon_emit(cmd_buffer->cs, va);
1329 radeon_emit(cmd_buffer->cs, va >> 32);
1330 radeon_emit(cmd_buffer->cs, reg >> 2);
1331 radeon_emit(cmd_buffer->cs, 0);
1332
1333 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1334 radeon_emit(cmd_buffer->cs, 0);
1335 }
1336
1337 void
1338 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1339 {
1340 int i;
1341 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1342 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1343
1344 /* this may happen for inherited secondary recording */
1345 if (!framebuffer)
1346 return;
1347
1348 for (i = 0; i < 8; ++i) {
1349 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1350 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1351 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1352 continue;
1353 }
1354
1355 int idx = subpass->color_attachments[i].attachment;
1356 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1357
1358 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1359
1360 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1361 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1362
1363 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1364 }
1365
1366 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1367 int idx = subpass->depth_stencil_attachment.attachment;
1368 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1369 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1370 struct radv_image *image = att->attachment->image;
1371 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1372 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1373 cmd_buffer->queue_family_index,
1374 cmd_buffer->queue_family_index);
1375 /* We currently don't support writing decompressed HTILE */
1376 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1377 radv_layout_is_htile_compressed(image, layout, queue_mask));
1378
1379 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1380
1381 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1382 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1383 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1384 }
1385 radv_load_depth_clear_regs(cmd_buffer, image);
1386 } else {
1387 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1388 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1389 else
1390 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1391
1392 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1393 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1394 }
1395 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1396 S_028208_BR_X(framebuffer->width) |
1397 S_028208_BR_Y(framebuffer->height));
1398
1399 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1400 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1401 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1402 }
1403 }
1404
1405 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1406 {
1407 uint32_t db_count_control;
1408
1409 if(!cmd_buffer->state.active_occlusion_queries) {
1410 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1411 db_count_control = 0;
1412 } else {
1413 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1414 }
1415 } else {
1416 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1417 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1418 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1419 S_028004_ZPASS_ENABLE(1) |
1420 S_028004_SLICE_EVEN_ENABLE(1) |
1421 S_028004_SLICE_ODD_ENABLE(1);
1422 } else {
1423 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1424 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1425 }
1426 }
1427
1428 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1429 }
1430
1431 static void
1432 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1433 {
1434 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1435 return;
1436
1437 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1438 radv_emit_viewport(cmd_buffer);
1439
1440 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1441 radv_emit_scissor(cmd_buffer);
1442
1443 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1444 radv_emit_line_width(cmd_buffer);
1445
1446 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1447 radv_emit_blend_constants(cmd_buffer);
1448
1449 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1450 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1451 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1452 radv_emit_stencil(cmd_buffer);
1453
1454 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1455 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1456 radv_emit_depth_bounds(cmd_buffer);
1457
1458 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1459 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1460 radv_emit_depth_biais(cmd_buffer);
1461
1462 cmd_buffer->state.dirty = 0;
1463 }
1464
1465 static void
1466 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1467 struct radv_pipeline *pipeline,
1468 int idx,
1469 uint64_t va,
1470 gl_shader_stage stage)
1471 {
1472 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1473 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1474
1475 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1476 return;
1477
1478 assert(!desc_set_loc->indirect);
1479 assert(desc_set_loc->num_sgprs == 2);
1480 radeon_set_sh_reg_seq(cmd_buffer->cs,
1481 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1482 radeon_emit(cmd_buffer->cs, va);
1483 radeon_emit(cmd_buffer->cs, va >> 32);
1484 }
1485
1486 static void
1487 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1488 VkShaderStageFlags stages,
1489 struct radv_descriptor_set *set,
1490 unsigned idx)
1491 {
1492 if (cmd_buffer->state.pipeline) {
1493 radv_foreach_stage(stage, stages) {
1494 if (cmd_buffer->state.pipeline->shaders[stage])
1495 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1496 idx, set->va,
1497 stage);
1498 }
1499 }
1500
1501 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1502 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1503 idx, set->va,
1504 MESA_SHADER_COMPUTE);
1505 }
1506
1507 static void
1508 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1509 {
1510 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1511 unsigned bo_offset;
1512
1513 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1514 set->mapped_ptr,
1515 &bo_offset))
1516 return;
1517
1518 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1519 set->va += bo_offset;
1520 }
1521
1522 static void
1523 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1524 {
1525 uint32_t size = MAX_SETS * 2 * 4;
1526 uint32_t offset;
1527 void *ptr;
1528
1529 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1530 256, &offset, &ptr))
1531 return;
1532
1533 for (unsigned i = 0; i < MAX_SETS; i++) {
1534 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1535 uint64_t set_va = 0;
1536 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1537 if (set)
1538 set_va = set->va;
1539 uptr[0] = set_va & 0xffffffff;
1540 uptr[1] = set_va >> 32;
1541 }
1542
1543 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1544 va += offset;
1545
1546 if (cmd_buffer->state.pipeline) {
1547 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1548 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1549 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1550
1551 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1552 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1553 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1554
1555 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1556 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1557 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1558
1559 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1560 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1561 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1562
1563 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1564 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1565 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1566 }
1567
1568 if (cmd_buffer->state.compute_pipeline)
1569 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1570 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1571 }
1572
1573 static void
1574 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1575 VkShaderStageFlags stages)
1576 {
1577 unsigned i;
1578
1579 if (!cmd_buffer->state.descriptors_dirty)
1580 return;
1581
1582 if (cmd_buffer->state.push_descriptors_dirty)
1583 radv_flush_push_descriptors(cmd_buffer);
1584
1585 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1586 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1587 radv_flush_indirect_descriptor_sets(cmd_buffer);
1588 }
1589
1590 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1591 cmd_buffer->cs,
1592 MAX_SETS * MESA_SHADER_STAGES * 4);
1593
1594 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1595 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1596 if (!set)
1597 continue;
1598
1599 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1600 }
1601 cmd_buffer->state.descriptors_dirty = 0;
1602 cmd_buffer->state.push_descriptors_dirty = false;
1603
1604 radv_save_descriptors(cmd_buffer);
1605
1606 assert(cmd_buffer->cs->cdw <= cdw_max);
1607 }
1608
1609 static void
1610 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1611 struct radv_pipeline *pipeline,
1612 VkShaderStageFlags stages)
1613 {
1614 struct radv_pipeline_layout *layout = pipeline->layout;
1615 unsigned offset;
1616 void *ptr;
1617 uint64_t va;
1618
1619 stages &= cmd_buffer->push_constant_stages;
1620 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1621 return;
1622
1623 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1624 16 * layout->dynamic_offset_count,
1625 256, &offset, &ptr))
1626 return;
1627
1628 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1629 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1630 16 * layout->dynamic_offset_count);
1631
1632 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1633 va += offset;
1634
1635 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1636 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1637
1638 radv_foreach_stage(stage, stages) {
1639 if (pipeline->shaders[stage]) {
1640 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1641 AC_UD_PUSH_CONSTANTS, va);
1642 }
1643 }
1644
1645 cmd_buffer->push_constant_stages &= ~stages;
1646 assert(cmd_buffer->cs->cdw <= cdw_max);
1647 }
1648
1649 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1650 bool indexed_draw)
1651 {
1652 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1653
1654 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1655 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1656 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1657 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1658 primitive_reset_en);
1659 } else {
1660 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1661 primitive_reset_en);
1662 }
1663 }
1664
1665 if (primitive_reset_en) {
1666 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1667
1668 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1669 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1670 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1671 primitive_reset_index);
1672 }
1673 }
1674 }
1675
1676 static bool
1677 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1678 {
1679 struct radv_device *device = cmd_buffer->device;
1680
1681 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1682 cmd_buffer->state.pipeline->vertex_elements.count &&
1683 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1684 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1685 unsigned vb_offset;
1686 void *vb_ptr;
1687 uint32_t i = 0;
1688 uint32_t count = velems->count;
1689 uint64_t va;
1690
1691 /* allocate some descriptor state for vertex buffers */
1692 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1693 &vb_offset, &vb_ptr))
1694 return false;
1695
1696 for (i = 0; i < count; i++) {
1697 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1698 uint32_t offset;
1699 int vb = velems->binding[i];
1700 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1701 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1702
1703 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1704 va = radv_buffer_get_va(buffer->bo);
1705
1706 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1707 va += offset + buffer->offset;
1708 desc[0] = va;
1709 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1710 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1711 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1712 else
1713 desc[2] = buffer->size - offset;
1714 desc[3] = velems->rsrc_word3[i];
1715 }
1716
1717 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1718 va += vb_offset;
1719
1720 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1721 AC_UD_VS_VERTEX_BUFFERS, va);
1722 }
1723 cmd_buffer->state.vb_dirty = false;
1724
1725 return true;
1726 }
1727
1728 static void
1729 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1730 bool indexed_draw, bool instanced_draw,
1731 bool indirect_draw,
1732 uint32_t draw_vertex_count)
1733 {
1734 uint32_t ia_multi_vgt_param;
1735
1736 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1737 cmd_buffer->cs, 4096);
1738
1739 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1740 return;
1741
1742 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1743 radv_emit_graphics_pipeline(cmd_buffer);
1744
1745 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1746 radv_emit_framebuffer_state(cmd_buffer);
1747
1748 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1749 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1750 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1751 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1752 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1753 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1754 else
1755 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1756 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1757 }
1758
1759 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1760
1761 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1762
1763 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1764 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1765 VK_SHADER_STAGE_ALL_GRAPHICS);
1766
1767 assert(cmd_buffer->cs->cdw <= cdw_max);
1768
1769 si_emit_cache_flush(cmd_buffer);
1770 }
1771
1772 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1773 VkPipelineStageFlags src_stage_mask)
1774 {
1775 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1776 VK_PIPELINE_STAGE_TRANSFER_BIT |
1777 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1778 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1779 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1780 }
1781
1782 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1783 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1784 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1785 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1786 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1787 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1788 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1789 VK_PIPELINE_STAGE_TRANSFER_BIT |
1790 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1791 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1792 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1793 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1794 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1795 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1796 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1797 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1798 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1799 }
1800 }
1801
1802 static enum radv_cmd_flush_bits
1803 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1804 VkAccessFlags src_flags)
1805 {
1806 enum radv_cmd_flush_bits flush_bits = 0;
1807 uint32_t b;
1808 for_each_bit(b, src_flags) {
1809 switch ((VkAccessFlagBits)(1 << b)) {
1810 case VK_ACCESS_SHADER_WRITE_BIT:
1811 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1812 break;
1813 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1814 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1815 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1816 break;
1817 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1818 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1819 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1820 break;
1821 case VK_ACCESS_TRANSFER_WRITE_BIT:
1822 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1823 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1824 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1825 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1826 RADV_CMD_FLAG_INV_GLOBAL_L2;
1827 break;
1828 default:
1829 break;
1830 }
1831 }
1832 return flush_bits;
1833 }
1834
1835 static enum radv_cmd_flush_bits
1836 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1837 VkAccessFlags dst_flags,
1838 struct radv_image *image)
1839 {
1840 enum radv_cmd_flush_bits flush_bits = 0;
1841 uint32_t b;
1842 for_each_bit(b, dst_flags) {
1843 switch ((VkAccessFlagBits)(1 << b)) {
1844 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1845 case VK_ACCESS_INDEX_READ_BIT:
1846 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1847 break;
1848 case VK_ACCESS_UNIFORM_READ_BIT:
1849 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1850 break;
1851 case VK_ACCESS_SHADER_READ_BIT:
1852 case VK_ACCESS_TRANSFER_READ_BIT:
1853 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1854 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1855 RADV_CMD_FLAG_INV_GLOBAL_L2;
1856 break;
1857 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1858 /* TODO: change to image && when the image gets passed
1859 * through from the subpass. */
1860 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1861 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1862 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1863 break;
1864 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1865 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1866 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1867 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1868 break;
1869 default:
1870 break;
1871 }
1872 }
1873 return flush_bits;
1874 }
1875
1876 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1877 {
1878 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1879 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1880 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1881 NULL);
1882 }
1883
1884 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1885 VkAttachmentReference att)
1886 {
1887 unsigned idx = att.attachment;
1888 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1889 VkImageSubresourceRange range;
1890 range.aspectMask = 0;
1891 range.baseMipLevel = view->base_mip;
1892 range.levelCount = 1;
1893 range.baseArrayLayer = view->base_layer;
1894 range.layerCount = cmd_buffer->state.framebuffer->layers;
1895
1896 radv_handle_image_transition(cmd_buffer,
1897 view->image,
1898 cmd_buffer->state.attachments[idx].current_layout,
1899 att.layout, 0, 0, &range,
1900 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1901
1902 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1903
1904
1905 }
1906
1907 void
1908 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1909 const struct radv_subpass *subpass, bool transitions)
1910 {
1911 if (transitions) {
1912 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1913
1914 for (unsigned i = 0; i < subpass->color_count; ++i) {
1915 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1916 radv_handle_subpass_image_transition(cmd_buffer,
1917 subpass->color_attachments[i]);
1918 }
1919
1920 for (unsigned i = 0; i < subpass->input_count; ++i) {
1921 radv_handle_subpass_image_transition(cmd_buffer,
1922 subpass->input_attachments[i]);
1923 }
1924
1925 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1926 radv_handle_subpass_image_transition(cmd_buffer,
1927 subpass->depth_stencil_attachment);
1928 }
1929 }
1930
1931 cmd_buffer->state.subpass = subpass;
1932
1933 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1934 }
1935
1936 static VkResult
1937 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1938 struct radv_render_pass *pass,
1939 const VkRenderPassBeginInfo *info)
1940 {
1941 struct radv_cmd_state *state = &cmd_buffer->state;
1942
1943 if (pass->attachment_count == 0) {
1944 state->attachments = NULL;
1945 return VK_SUCCESS;
1946 }
1947
1948 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1949 pass->attachment_count *
1950 sizeof(state->attachments[0]),
1951 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1952 if (state->attachments == NULL) {
1953 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1954 return cmd_buffer->record_result;
1955 }
1956
1957 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1958 struct radv_render_pass_attachment *att = &pass->attachments[i];
1959 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1960 VkImageAspectFlags clear_aspects = 0;
1961
1962 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1963 /* color attachment */
1964 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1965 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1966 }
1967 } else {
1968 /* depthstencil attachment */
1969 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1970 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1971 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1972 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1973 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1974 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1975 }
1976 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1977 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1978 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1979 }
1980 }
1981
1982 state->attachments[i].pending_clear_aspects = clear_aspects;
1983 state->attachments[i].cleared_views = 0;
1984 if (clear_aspects && info) {
1985 assert(info->clearValueCount > i);
1986 state->attachments[i].clear_value = info->pClearValues[i];
1987 }
1988
1989 state->attachments[i].current_layout = att->initial_layout;
1990 }
1991
1992 return VK_SUCCESS;
1993 }
1994
1995 VkResult radv_AllocateCommandBuffers(
1996 VkDevice _device,
1997 const VkCommandBufferAllocateInfo *pAllocateInfo,
1998 VkCommandBuffer *pCommandBuffers)
1999 {
2000 RADV_FROM_HANDLE(radv_device, device, _device);
2001 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2002
2003 VkResult result = VK_SUCCESS;
2004 uint32_t i;
2005
2006 memset(pCommandBuffers, 0,
2007 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2008
2009 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2010
2011 if (!list_empty(&pool->free_cmd_buffers)) {
2012 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2013
2014 list_del(&cmd_buffer->pool_link);
2015 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2016
2017 result = radv_reset_cmd_buffer(cmd_buffer);
2018 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2019 cmd_buffer->level = pAllocateInfo->level;
2020
2021 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2022 } else {
2023 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2024 &pCommandBuffers[i]);
2025 }
2026 if (result != VK_SUCCESS)
2027 break;
2028 }
2029
2030 if (result != VK_SUCCESS)
2031 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2032 i, pCommandBuffers);
2033
2034 return result;
2035 }
2036
2037 void radv_FreeCommandBuffers(
2038 VkDevice device,
2039 VkCommandPool commandPool,
2040 uint32_t commandBufferCount,
2041 const VkCommandBuffer *pCommandBuffers)
2042 {
2043 for (uint32_t i = 0; i < commandBufferCount; i++) {
2044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2045
2046 if (cmd_buffer) {
2047 if (cmd_buffer->pool) {
2048 list_del(&cmd_buffer->pool_link);
2049 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2050 } else
2051 radv_cmd_buffer_destroy(cmd_buffer);
2052
2053 }
2054 }
2055 }
2056
2057 VkResult radv_ResetCommandBuffer(
2058 VkCommandBuffer commandBuffer,
2059 VkCommandBufferResetFlags flags)
2060 {
2061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2062 return radv_reset_cmd_buffer(cmd_buffer);
2063 }
2064
2065 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2066 {
2067 struct radv_device *device = cmd_buffer->device;
2068 if (device->gfx_init) {
2069 uint64_t va = radv_buffer_get_va(device->gfx_init);
2070 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2071 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2072 radeon_emit(cmd_buffer->cs, va);
2073 radeon_emit(cmd_buffer->cs, va >> 32);
2074 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2075 } else
2076 si_init_config(cmd_buffer);
2077 }
2078
2079 VkResult radv_BeginCommandBuffer(
2080 VkCommandBuffer commandBuffer,
2081 const VkCommandBufferBeginInfo *pBeginInfo)
2082 {
2083 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2084 VkResult result;
2085
2086 result = radv_reset_cmd_buffer(cmd_buffer);
2087 if (result != VK_SUCCESS)
2088 return result;
2089
2090 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2091 cmd_buffer->state.last_primitive_reset_en = -1;
2092 cmd_buffer->usage_flags = pBeginInfo->flags;
2093
2094 /* setup initial configuration into command buffer */
2095 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2096 switch (cmd_buffer->queue_family_index) {
2097 case RADV_QUEUE_GENERAL:
2098 emit_gfx_buffer_state(cmd_buffer);
2099 radv_set_db_count_control(cmd_buffer);
2100 break;
2101 case RADV_QUEUE_COMPUTE:
2102 si_init_compute(cmd_buffer);
2103 break;
2104 case RADV_QUEUE_TRANSFER:
2105 default:
2106 break;
2107 }
2108 }
2109
2110 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2111 assert(pBeginInfo->pInheritanceInfo);
2112 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2113 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2114
2115 struct radv_subpass *subpass =
2116 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2117
2118 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2119 if (result != VK_SUCCESS)
2120 return result;
2121
2122 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2123 }
2124
2125 radv_cmd_buffer_trace_emit(cmd_buffer);
2126 return result;
2127 }
2128
2129 void radv_CmdBindVertexBuffers(
2130 VkCommandBuffer commandBuffer,
2131 uint32_t firstBinding,
2132 uint32_t bindingCount,
2133 const VkBuffer* pBuffers,
2134 const VkDeviceSize* pOffsets)
2135 {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2137 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2138
2139 /* We have to defer setting up vertex buffer since we need the buffer
2140 * stride from the pipeline. */
2141
2142 assert(firstBinding + bindingCount <= MAX_VBS);
2143 for (uint32_t i = 0; i < bindingCount; i++) {
2144 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2145 vb[firstBinding + i].offset = pOffsets[i];
2146 }
2147
2148 cmd_buffer->state.vb_dirty = true;
2149 }
2150
2151 void radv_CmdBindIndexBuffer(
2152 VkCommandBuffer commandBuffer,
2153 VkBuffer buffer,
2154 VkDeviceSize offset,
2155 VkIndexType indexType)
2156 {
2157 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2158 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2159
2160 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2161 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2162 cmd_buffer->state.index_va += index_buffer->offset + offset;
2163
2164 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2165 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2166 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2167 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2168 }
2169
2170
2171 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2172 struct radv_descriptor_set *set,
2173 unsigned idx)
2174 {
2175 struct radeon_winsys *ws = cmd_buffer->device->ws;
2176
2177 cmd_buffer->state.descriptors[idx] = set;
2178 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2179 if (!set)
2180 return;
2181
2182 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2183
2184 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2185 if (set->descriptors[j])
2186 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2187
2188 if(set->bo)
2189 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2190 }
2191
2192 void radv_CmdBindDescriptorSets(
2193 VkCommandBuffer commandBuffer,
2194 VkPipelineBindPoint pipelineBindPoint,
2195 VkPipelineLayout _layout,
2196 uint32_t firstSet,
2197 uint32_t descriptorSetCount,
2198 const VkDescriptorSet* pDescriptorSets,
2199 uint32_t dynamicOffsetCount,
2200 const uint32_t* pDynamicOffsets)
2201 {
2202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2203 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2204 unsigned dyn_idx = 0;
2205
2206 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2207 unsigned idx = i + firstSet;
2208 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2209 radv_bind_descriptor_set(cmd_buffer, set, idx);
2210
2211 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2212 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2213 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2214 assert(dyn_idx < dynamicOffsetCount);
2215
2216 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2217 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2218 dst[0] = va;
2219 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2220 dst[2] = range->size;
2221 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2222 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2223 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2224 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2225 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2227 cmd_buffer->push_constant_stages |=
2228 set->layout->dynamic_shader_stages;
2229 }
2230 }
2231 }
2232
2233 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2234 struct radv_descriptor_set *set,
2235 struct radv_descriptor_set_layout *layout)
2236 {
2237 set->size = layout->size;
2238 set->layout = layout;
2239
2240 if (cmd_buffer->push_descriptors.capacity < set->size) {
2241 size_t new_size = MAX2(set->size, 1024);
2242 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2243 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2244
2245 free(set->mapped_ptr);
2246 set->mapped_ptr = malloc(new_size);
2247
2248 if (!set->mapped_ptr) {
2249 cmd_buffer->push_descriptors.capacity = 0;
2250 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2251 return false;
2252 }
2253
2254 cmd_buffer->push_descriptors.capacity = new_size;
2255 }
2256
2257 return true;
2258 }
2259
2260 void radv_meta_push_descriptor_set(
2261 struct radv_cmd_buffer* cmd_buffer,
2262 VkPipelineBindPoint pipelineBindPoint,
2263 VkPipelineLayout _layout,
2264 uint32_t set,
2265 uint32_t descriptorWriteCount,
2266 const VkWriteDescriptorSet* pDescriptorWrites)
2267 {
2268 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2269 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2270 unsigned bo_offset;
2271
2272 assert(set == 0);
2273 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2274
2275 push_set->size = layout->set[set].layout->size;
2276 push_set->layout = layout->set[set].layout;
2277
2278 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2279 &bo_offset,
2280 (void**) &push_set->mapped_ptr))
2281 return;
2282
2283 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2284 push_set->va += bo_offset;
2285
2286 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2287 radv_descriptor_set_to_handle(push_set),
2288 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2289
2290 cmd_buffer->state.descriptors[set] = push_set;
2291 cmd_buffer->state.descriptors_dirty |= (1u << set);
2292 }
2293
2294 void radv_CmdPushDescriptorSetKHR(
2295 VkCommandBuffer commandBuffer,
2296 VkPipelineBindPoint pipelineBindPoint,
2297 VkPipelineLayout _layout,
2298 uint32_t set,
2299 uint32_t descriptorWriteCount,
2300 const VkWriteDescriptorSet* pDescriptorWrites)
2301 {
2302 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2303 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2304 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2305
2306 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2307
2308 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2309 return;
2310
2311 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2312 radv_descriptor_set_to_handle(push_set),
2313 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2314
2315 cmd_buffer->state.descriptors[set] = push_set;
2316 cmd_buffer->state.descriptors_dirty |= (1u << set);
2317 cmd_buffer->state.push_descriptors_dirty = true;
2318 }
2319
2320 void radv_CmdPushDescriptorSetWithTemplateKHR(
2321 VkCommandBuffer commandBuffer,
2322 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2323 VkPipelineLayout _layout,
2324 uint32_t set,
2325 const void* pData)
2326 {
2327 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2328 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2329 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2330
2331 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2332
2333 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2334 return;
2335
2336 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2337 descriptorUpdateTemplate, pData);
2338
2339 cmd_buffer->state.descriptors[set] = push_set;
2340 cmd_buffer->state.descriptors_dirty |= (1u << set);
2341 cmd_buffer->state.push_descriptors_dirty = true;
2342 }
2343
2344 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2345 VkPipelineLayout layout,
2346 VkShaderStageFlags stageFlags,
2347 uint32_t offset,
2348 uint32_t size,
2349 const void* pValues)
2350 {
2351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2352 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2353 cmd_buffer->push_constant_stages |= stageFlags;
2354 }
2355
2356 VkResult radv_EndCommandBuffer(
2357 VkCommandBuffer commandBuffer)
2358 {
2359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2360
2361 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2362 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2363 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2364 si_emit_cache_flush(cmd_buffer);
2365 }
2366
2367 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2368 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2369
2370 return cmd_buffer->record_result;
2371 }
2372
2373 static void
2374 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2375 {
2376 struct radeon_winsys *ws = cmd_buffer->device->ws;
2377 struct radv_shader_variant *compute_shader;
2378 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2379 uint64_t va;
2380
2381 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2382 return;
2383
2384 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2385
2386 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2387 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2388
2389 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2390 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2391
2392 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2393 cmd_buffer->cs, 16);
2394
2395 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2396 radeon_emit(cmd_buffer->cs, va >> 8);
2397 radeon_emit(cmd_buffer->cs, va >> 40);
2398
2399 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2400 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2401 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2402
2403
2404 cmd_buffer->compute_scratch_size_needed =
2405 MAX2(cmd_buffer->compute_scratch_size_needed,
2406 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2407
2408 /* change these once we have scratch support */
2409 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2410 S_00B860_WAVES(pipeline->max_waves) |
2411 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2412
2413 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2414 radeon_emit(cmd_buffer->cs,
2415 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2416 radeon_emit(cmd_buffer->cs,
2417 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2418 radeon_emit(cmd_buffer->cs,
2419 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2420
2421 assert(cmd_buffer->cs->cdw <= cdw_max);
2422 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2423 }
2424
2425 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2426 {
2427 for (unsigned i = 0; i < MAX_SETS; i++) {
2428 if (cmd_buffer->state.descriptors[i])
2429 cmd_buffer->state.descriptors_dirty |= (1u << i);
2430 }
2431 }
2432
2433 void radv_CmdBindPipeline(
2434 VkCommandBuffer commandBuffer,
2435 VkPipelineBindPoint pipelineBindPoint,
2436 VkPipeline _pipeline)
2437 {
2438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2439 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2440
2441 switch (pipelineBindPoint) {
2442 case VK_PIPELINE_BIND_POINT_COMPUTE:
2443 if (cmd_buffer->state.compute_pipeline == pipeline)
2444 return;
2445 radv_mark_descriptor_sets_dirty(cmd_buffer);
2446
2447 cmd_buffer->state.compute_pipeline = pipeline;
2448 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2449 break;
2450 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2451 if (cmd_buffer->state.pipeline == pipeline)
2452 return;
2453 radv_mark_descriptor_sets_dirty(cmd_buffer);
2454
2455 cmd_buffer->state.pipeline = pipeline;
2456 if (!pipeline)
2457 break;
2458
2459 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2460 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2461
2462 /* Apply the dynamic state from the pipeline */
2463 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2464 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2465 &pipeline->dynamic_state,
2466 pipeline->dynamic_state_mask);
2467
2468 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2469 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2470 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2471 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2472
2473 if (radv_pipeline_has_tess(pipeline))
2474 cmd_buffer->tess_rings_needed = true;
2475
2476 if (radv_pipeline_has_gs(pipeline)) {
2477 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2478 AC_UD_SCRATCH_RING_OFFSETS);
2479 if (cmd_buffer->ring_offsets_idx == -1)
2480 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2481 else if (loc->sgpr_idx != -1)
2482 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2483 }
2484 break;
2485 default:
2486 assert(!"invalid bind point");
2487 break;
2488 }
2489 }
2490
2491 void radv_CmdSetViewport(
2492 VkCommandBuffer commandBuffer,
2493 uint32_t firstViewport,
2494 uint32_t viewportCount,
2495 const VkViewport* pViewports)
2496 {
2497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2498 const uint32_t total_count = firstViewport + viewportCount;
2499
2500 assert(firstViewport < MAX_VIEWPORTS);
2501 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2502
2503 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2504 pViewports, viewportCount * sizeof(*pViewports));
2505
2506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2507 }
2508
2509 void radv_CmdSetScissor(
2510 VkCommandBuffer commandBuffer,
2511 uint32_t firstScissor,
2512 uint32_t scissorCount,
2513 const VkRect2D* pScissors)
2514 {
2515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2516 const uint32_t total_count = firstScissor + scissorCount;
2517
2518 assert(firstScissor < MAX_SCISSORS);
2519 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2520
2521 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2522 pScissors, scissorCount * sizeof(*pScissors));
2523 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2524 }
2525
2526 void radv_CmdSetLineWidth(
2527 VkCommandBuffer commandBuffer,
2528 float lineWidth)
2529 {
2530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2531 cmd_buffer->state.dynamic.line_width = lineWidth;
2532 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2533 }
2534
2535 void radv_CmdSetDepthBias(
2536 VkCommandBuffer commandBuffer,
2537 float depthBiasConstantFactor,
2538 float depthBiasClamp,
2539 float depthBiasSlopeFactor)
2540 {
2541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2542
2543 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2544 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2545 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2546
2547 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2548 }
2549
2550 void radv_CmdSetBlendConstants(
2551 VkCommandBuffer commandBuffer,
2552 const float blendConstants[4])
2553 {
2554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2555
2556 memcpy(cmd_buffer->state.dynamic.blend_constants,
2557 blendConstants, sizeof(float) * 4);
2558
2559 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2560 }
2561
2562 void radv_CmdSetDepthBounds(
2563 VkCommandBuffer commandBuffer,
2564 float minDepthBounds,
2565 float maxDepthBounds)
2566 {
2567 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2568
2569 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2570 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2571
2572 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2573 }
2574
2575 void radv_CmdSetStencilCompareMask(
2576 VkCommandBuffer commandBuffer,
2577 VkStencilFaceFlags faceMask,
2578 uint32_t compareMask)
2579 {
2580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2581
2582 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2583 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2584 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2585 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2586
2587 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2588 }
2589
2590 void radv_CmdSetStencilWriteMask(
2591 VkCommandBuffer commandBuffer,
2592 VkStencilFaceFlags faceMask,
2593 uint32_t writeMask)
2594 {
2595 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2596
2597 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2598 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2599 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2600 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2601
2602 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2603 }
2604
2605 void radv_CmdSetStencilReference(
2606 VkCommandBuffer commandBuffer,
2607 VkStencilFaceFlags faceMask,
2608 uint32_t reference)
2609 {
2610 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2611
2612 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2613 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2614 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2615 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2616
2617 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2618 }
2619
2620 void radv_CmdExecuteCommands(
2621 VkCommandBuffer commandBuffer,
2622 uint32_t commandBufferCount,
2623 const VkCommandBuffer* pCmdBuffers)
2624 {
2625 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2626
2627 /* Emit pending flushes on primary prior to executing secondary */
2628 si_emit_cache_flush(primary);
2629
2630 for (uint32_t i = 0; i < commandBufferCount; i++) {
2631 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2632
2633 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2634 secondary->scratch_size_needed);
2635 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2636 secondary->compute_scratch_size_needed);
2637
2638 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2639 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2640 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2641 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2642 if (secondary->tess_rings_needed)
2643 primary->tess_rings_needed = true;
2644 if (secondary->sample_positions_needed)
2645 primary->sample_positions_needed = true;
2646
2647 if (secondary->ring_offsets_idx != -1) {
2648 if (primary->ring_offsets_idx == -1)
2649 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2650 else
2651 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2652 }
2653 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2654
2655 primary->state.emitted_pipeline = secondary->state.emitted_pipeline;
2656 primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
2657 primary->state.last_primitive_reset_en = secondary->state.last_primitive_reset_en;
2658 primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
2659 }
2660
2661 /* if we execute secondary we need to mark some stuff to reset dirty */
2662 if (commandBufferCount) {
2663 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2664 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2665 radv_mark_descriptor_sets_dirty(primary);
2666 }
2667 }
2668
2669 VkResult radv_CreateCommandPool(
2670 VkDevice _device,
2671 const VkCommandPoolCreateInfo* pCreateInfo,
2672 const VkAllocationCallbacks* pAllocator,
2673 VkCommandPool* pCmdPool)
2674 {
2675 RADV_FROM_HANDLE(radv_device, device, _device);
2676 struct radv_cmd_pool *pool;
2677
2678 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2679 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2680 if (pool == NULL)
2681 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2682
2683 if (pAllocator)
2684 pool->alloc = *pAllocator;
2685 else
2686 pool->alloc = device->alloc;
2687
2688 list_inithead(&pool->cmd_buffers);
2689 list_inithead(&pool->free_cmd_buffers);
2690
2691 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2692
2693 *pCmdPool = radv_cmd_pool_to_handle(pool);
2694
2695 return VK_SUCCESS;
2696
2697 }
2698
2699 void radv_DestroyCommandPool(
2700 VkDevice _device,
2701 VkCommandPool commandPool,
2702 const VkAllocationCallbacks* pAllocator)
2703 {
2704 RADV_FROM_HANDLE(radv_device, device, _device);
2705 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2706
2707 if (!pool)
2708 return;
2709
2710 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2711 &pool->cmd_buffers, pool_link) {
2712 radv_cmd_buffer_destroy(cmd_buffer);
2713 }
2714
2715 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2716 &pool->free_cmd_buffers, pool_link) {
2717 radv_cmd_buffer_destroy(cmd_buffer);
2718 }
2719
2720 vk_free2(&device->alloc, pAllocator, pool);
2721 }
2722
2723 VkResult radv_ResetCommandPool(
2724 VkDevice device,
2725 VkCommandPool commandPool,
2726 VkCommandPoolResetFlags flags)
2727 {
2728 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2729 VkResult result;
2730
2731 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2732 &pool->cmd_buffers, pool_link) {
2733 result = radv_reset_cmd_buffer(cmd_buffer);
2734 if (result != VK_SUCCESS)
2735 return result;
2736 }
2737
2738 return VK_SUCCESS;
2739 }
2740
2741 void radv_TrimCommandPoolKHR(
2742 VkDevice device,
2743 VkCommandPool commandPool,
2744 VkCommandPoolTrimFlagsKHR flags)
2745 {
2746 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2747
2748 if (!pool)
2749 return;
2750
2751 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2752 &pool->free_cmd_buffers, pool_link) {
2753 radv_cmd_buffer_destroy(cmd_buffer);
2754 }
2755 }
2756
2757 void radv_CmdBeginRenderPass(
2758 VkCommandBuffer commandBuffer,
2759 const VkRenderPassBeginInfo* pRenderPassBegin,
2760 VkSubpassContents contents)
2761 {
2762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2763 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2764 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2765
2766 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2767 cmd_buffer->cs, 2048);
2768 MAYBE_UNUSED VkResult result;
2769
2770 cmd_buffer->state.framebuffer = framebuffer;
2771 cmd_buffer->state.pass = pass;
2772 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2773
2774 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2775 if (result != VK_SUCCESS)
2776 return;
2777
2778 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2779 assert(cmd_buffer->cs->cdw <= cdw_max);
2780
2781 radv_cmd_buffer_clear_subpass(cmd_buffer);
2782 }
2783
2784 void radv_CmdNextSubpass(
2785 VkCommandBuffer commandBuffer,
2786 VkSubpassContents contents)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789
2790 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2791
2792 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2793 2048);
2794
2795 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2796 radv_cmd_buffer_clear_subpass(cmd_buffer);
2797 }
2798
2799 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2800 {
2801 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2802 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2803 if (!pipeline->shaders[stage])
2804 continue;
2805 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2806 if (loc->sgpr_idx == -1)
2807 continue;
2808 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2809 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2810
2811 }
2812 if (pipeline->gs_copy_shader) {
2813 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2814 if (loc->sgpr_idx != -1) {
2815 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2816 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2817 }
2818 }
2819 }
2820
2821 static void
2822 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2823 uint32_t vertex_count)
2824 {
2825 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2826 radeon_emit(cmd_buffer->cs, vertex_count);
2827 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2828 S_0287F0_USE_OPAQUE(0));
2829 }
2830
2831 void radv_CmdDraw(
2832 VkCommandBuffer commandBuffer,
2833 uint32_t vertexCount,
2834 uint32_t instanceCount,
2835 uint32_t firstVertex,
2836 uint32_t firstInstance)
2837 {
2838 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2839
2840 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2841
2842 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2843
2844 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2845 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2846 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2847 radeon_emit(cmd_buffer->cs, firstVertex);
2848 radeon_emit(cmd_buffer->cs, firstInstance);
2849 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2850 radeon_emit(cmd_buffer->cs, 0);
2851
2852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2853 radeon_emit(cmd_buffer->cs, instanceCount);
2854
2855 if (!cmd_buffer->state.subpass->view_mask) {
2856 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2857 } else {
2858 unsigned i;
2859 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2860 radv_emit_view_index(cmd_buffer, i);
2861
2862 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2863 }
2864 }
2865
2866 assert(cmd_buffer->cs->cdw <= cdw_max);
2867
2868 radv_cmd_buffer_after_draw(cmd_buffer);
2869 }
2870
2871
2872 static void
2873 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2874 uint64_t index_va,
2875 uint32_t index_count)
2876 {
2877 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2878 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2879 radeon_emit(cmd_buffer->cs, index_va);
2880 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2881 radeon_emit(cmd_buffer->cs, index_count);
2882 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2883 }
2884
2885 void radv_CmdDrawIndexed(
2886 VkCommandBuffer commandBuffer,
2887 uint32_t indexCount,
2888 uint32_t instanceCount,
2889 uint32_t firstIndex,
2890 int32_t vertexOffset,
2891 uint32_t firstInstance)
2892 {
2893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2894 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2895 uint64_t index_va;
2896
2897 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2898
2899 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2900
2901 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2902 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2903 2, cmd_buffer->state.index_type);
2904 } else {
2905 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2906 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2907 }
2908
2909 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2910 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2911 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2912 radeon_emit(cmd_buffer->cs, vertexOffset);
2913 radeon_emit(cmd_buffer->cs, firstInstance);
2914 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2915 radeon_emit(cmd_buffer->cs, 0);
2916
2917 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2918 radeon_emit(cmd_buffer->cs, instanceCount);
2919
2920 index_va = cmd_buffer->state.index_va;
2921 index_va += firstIndex * index_size;
2922 if (!cmd_buffer->state.subpass->view_mask) {
2923 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2924 } else {
2925 unsigned i;
2926 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2927 radv_emit_view_index(cmd_buffer, i);
2928
2929 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2930 }
2931 }
2932
2933 assert(cmd_buffer->cs->cdw <= cdw_max);
2934 radv_cmd_buffer_after_draw(cmd_buffer);
2935 }
2936
2937 static void
2938 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2939 bool indexed,
2940 uint32_t draw_count,
2941 uint64_t count_va,
2942 uint32_t stride)
2943 {
2944 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2945 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2946 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2947 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2948 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2949 assert(base_reg);
2950
2951 if (draw_count == 1 && !count_va && !draw_id_enable) {
2952 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2953 PKT3_DRAW_INDIRECT, 3, false));
2954 radeon_emit(cs, 0);
2955 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2956 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2957 radeon_emit(cs, di_src_sel);
2958 } else {
2959 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2960 PKT3_DRAW_INDIRECT_MULTI,
2961 8, false));
2962 radeon_emit(cs, 0);
2963 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2964 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2965 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2966 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2967 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2968 radeon_emit(cs, draw_count); /* count */
2969 radeon_emit(cs, count_va); /* count_addr */
2970 radeon_emit(cs, count_va >> 32);
2971 radeon_emit(cs, stride); /* stride */
2972 radeon_emit(cs, di_src_sel);
2973 }
2974 }
2975
2976 static void
2977 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2978 VkBuffer _buffer,
2979 VkDeviceSize offset,
2980 VkBuffer _count_buffer,
2981 VkDeviceSize count_offset,
2982 uint32_t draw_count,
2983 uint32_t stride,
2984 bool indexed)
2985 {
2986 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2987 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2988 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2989
2990 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
2991 indirect_va += offset + buffer->offset;
2992 uint64_t count_va = 0;
2993
2994 if (count_buffer) {
2995 count_va = radv_buffer_get_va(count_buffer->bo);
2996 count_va += count_offset + count_buffer->offset;
2997 }
2998
2999 if (!draw_count)
3000 return;
3001
3002 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3003
3004 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3005 radeon_emit(cs, 1);
3006 radeon_emit(cs, indirect_va);
3007 radeon_emit(cs, indirect_va >> 32);
3008
3009 if (!cmd_buffer->state.subpass->view_mask) {
3010 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3011 } else {
3012 unsigned i;
3013 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3014 radv_emit_view_index(cmd_buffer, i);
3015
3016 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3017 }
3018 }
3019 radv_cmd_buffer_after_draw(cmd_buffer);
3020 }
3021
3022 static void
3023 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3024 VkBuffer buffer,
3025 VkDeviceSize offset,
3026 VkBuffer countBuffer,
3027 VkDeviceSize countBufferOffset,
3028 uint32_t maxDrawCount,
3029 uint32_t stride)
3030 {
3031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3032 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3033
3034 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3035 cmd_buffer->cs, 24 * MAX_VIEWS);
3036
3037 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3038 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3039
3040 assert(cmd_buffer->cs->cdw <= cdw_max);
3041 }
3042
3043 static void
3044 radv_cmd_draw_indexed_indirect_count(
3045 VkCommandBuffer commandBuffer,
3046 VkBuffer buffer,
3047 VkDeviceSize offset,
3048 VkBuffer countBuffer,
3049 VkDeviceSize countBufferOffset,
3050 uint32_t maxDrawCount,
3051 uint32_t stride)
3052 {
3053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3054 uint64_t index_va;
3055 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3056
3057 index_va = cmd_buffer->state.index_va;
3058
3059 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3060
3061 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
3062 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
3063
3064 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
3065 radeon_emit(cmd_buffer->cs, index_va);
3066 radeon_emit(cmd_buffer->cs, index_va >> 32);
3067
3068 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
3069 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3070
3071 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3072 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3073
3074 assert(cmd_buffer->cs->cdw <= cdw_max);
3075 }
3076
3077 void radv_CmdDrawIndirect(
3078 VkCommandBuffer commandBuffer,
3079 VkBuffer buffer,
3080 VkDeviceSize offset,
3081 uint32_t drawCount,
3082 uint32_t stride)
3083 {
3084 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3085 VK_NULL_HANDLE, 0, drawCount, stride);
3086 }
3087
3088 void radv_CmdDrawIndexedIndirect(
3089 VkCommandBuffer commandBuffer,
3090 VkBuffer buffer,
3091 VkDeviceSize offset,
3092 uint32_t drawCount,
3093 uint32_t stride)
3094 {
3095 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3096 VK_NULL_HANDLE, 0, drawCount, stride);
3097 }
3098
3099 void radv_CmdDrawIndirectCountAMD(
3100 VkCommandBuffer commandBuffer,
3101 VkBuffer buffer,
3102 VkDeviceSize offset,
3103 VkBuffer countBuffer,
3104 VkDeviceSize countBufferOffset,
3105 uint32_t maxDrawCount,
3106 uint32_t stride)
3107 {
3108 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3109 countBuffer, countBufferOffset,
3110 maxDrawCount, stride);
3111 }
3112
3113 void radv_CmdDrawIndexedIndirectCountAMD(
3114 VkCommandBuffer commandBuffer,
3115 VkBuffer buffer,
3116 VkDeviceSize offset,
3117 VkBuffer countBuffer,
3118 VkDeviceSize countBufferOffset,
3119 uint32_t maxDrawCount,
3120 uint32_t stride)
3121 {
3122 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3123 countBuffer, countBufferOffset,
3124 maxDrawCount, stride);
3125 }
3126
3127 struct radv_dispatch_info {
3128 /**
3129 * Determine the layout of the grid (in block units) to be used.
3130 */
3131 uint32_t blocks[3];
3132
3133 /**
3134 * Whether it's an unaligned compute dispatch.
3135 */
3136 bool unaligned;
3137
3138 /**
3139 * Indirect compute parameters resource.
3140 */
3141 struct radv_buffer *indirect;
3142 uint64_t indirect_offset;
3143 };
3144
3145 static void
3146 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3147 const struct radv_dispatch_info *info)
3148 {
3149 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3150 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3151 struct radeon_winsys *ws = cmd_buffer->device->ws;
3152 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3153 struct ac_userdata_info *loc;
3154 uint8_t grid_used;
3155
3156 grid_used = compute_shader->info.info.cs.grid_components_used;
3157
3158 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3159 AC_UD_CS_GRID_SIZE);
3160
3161 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3162
3163 if (info->indirect) {
3164 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3165
3166 va += info->indirect->offset + info->indirect_offset;
3167
3168 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3169
3170 if (loc->sgpr_idx != -1) {
3171 for (unsigned i = 0; i < grid_used; ++i) {
3172 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3173 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3174 COPY_DATA_DST_SEL(COPY_DATA_REG));
3175 radeon_emit(cs, (va + 4 * i));
3176 radeon_emit(cs, (va + 4 * i) >> 32);
3177 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3178 + loc->sgpr_idx * 4) >> 2) + i);
3179 radeon_emit(cs, 0);
3180 }
3181 }
3182
3183 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3184 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3185 PKT3_SHADER_TYPE_S(1));
3186 radeon_emit(cs, va);
3187 radeon_emit(cs, va >> 32);
3188 radeon_emit(cs, 1);
3189 } else {
3190 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3191 PKT3_SHADER_TYPE_S(1));
3192 radeon_emit(cs, 1);
3193 radeon_emit(cs, va);
3194 radeon_emit(cs, va >> 32);
3195
3196 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3197 PKT3_SHADER_TYPE_S(1));
3198 radeon_emit(cs, 0);
3199 radeon_emit(cs, 1);
3200 }
3201 } else {
3202 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3203 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3204 S_00B800_FORCE_START_AT_000(1);
3205
3206 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3207 /* If the KMD allows it (there is a KMD hw register for
3208 * it), allow launching waves out-of-order.
3209 */
3210 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3211 }
3212
3213 if (info->unaligned) {
3214 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3215 unsigned remainder[3];
3216
3217 /* If aligned, these should be an entire block size,
3218 * not 0.
3219 */
3220 remainder[0] = blocks[0] + cs_block_size[0] -
3221 align_u32_npot(blocks[0], cs_block_size[0]);
3222 remainder[1] = blocks[1] + cs_block_size[1] -
3223 align_u32_npot(blocks[1], cs_block_size[1]);
3224 remainder[2] = blocks[2] + cs_block_size[2] -
3225 align_u32_npot(blocks[2], cs_block_size[2]);
3226
3227 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3228 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3229 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3230
3231 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3232 radeon_emit(cs,
3233 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3234 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3235 radeon_emit(cs,
3236 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3237 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3238 radeon_emit(cs,
3239 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3240 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3241
3242 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3243 }
3244
3245 if (loc->sgpr_idx != -1) {
3246 assert(!loc->indirect);
3247 assert(loc->num_sgprs == grid_used);
3248
3249 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3250 loc->sgpr_idx * 4, grid_used);
3251 radeon_emit(cs, blocks[0]);
3252 if (grid_used > 1)
3253 radeon_emit(cs, blocks[1]);
3254 if (grid_used > 2)
3255 radeon_emit(cs, blocks[2]);
3256 }
3257
3258 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3259 PKT3_SHADER_TYPE_S(1));
3260 radeon_emit(cs, blocks[0]);
3261 radeon_emit(cs, blocks[1]);
3262 radeon_emit(cs, blocks[2]);
3263 radeon_emit(cs, dispatch_initiator);
3264 }
3265
3266 assert(cmd_buffer->cs->cdw <= cdw_max);
3267 }
3268
3269 static void
3270 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3271 const struct radv_dispatch_info *info)
3272 {
3273 radv_emit_compute_pipeline(cmd_buffer);
3274
3275 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3276 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3277 VK_SHADER_STAGE_COMPUTE_BIT);
3278
3279 si_emit_cache_flush(cmd_buffer);
3280
3281 radv_emit_dispatch_packets(cmd_buffer, info);
3282
3283 radv_cmd_buffer_after_draw(cmd_buffer);
3284 }
3285
3286 void radv_CmdDispatch(
3287 VkCommandBuffer commandBuffer,
3288 uint32_t x,
3289 uint32_t y,
3290 uint32_t z)
3291 {
3292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3293 struct radv_dispatch_info info = {};
3294
3295 info.blocks[0] = x;
3296 info.blocks[1] = y;
3297 info.blocks[2] = z;
3298
3299 radv_dispatch(cmd_buffer, &info);
3300 }
3301
3302 void radv_CmdDispatchIndirect(
3303 VkCommandBuffer commandBuffer,
3304 VkBuffer _buffer,
3305 VkDeviceSize offset)
3306 {
3307 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3308 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3309 struct radv_dispatch_info info = {};
3310
3311 info.indirect = buffer;
3312 info.indirect_offset = offset;
3313
3314 radv_dispatch(cmd_buffer, &info);
3315 }
3316
3317 void radv_unaligned_dispatch(
3318 struct radv_cmd_buffer *cmd_buffer,
3319 uint32_t x,
3320 uint32_t y,
3321 uint32_t z)
3322 {
3323 struct radv_dispatch_info info = {};
3324
3325 info.blocks[0] = x;
3326 info.blocks[1] = y;
3327 info.blocks[2] = z;
3328 info.unaligned = 1;
3329
3330 radv_dispatch(cmd_buffer, &info);
3331 }
3332
3333 void radv_CmdEndRenderPass(
3334 VkCommandBuffer commandBuffer)
3335 {
3336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3337
3338 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3339
3340 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3341
3342 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3343 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3344 radv_handle_subpass_image_transition(cmd_buffer,
3345 (VkAttachmentReference){i, layout});
3346 }
3347
3348 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3349
3350 cmd_buffer->state.pass = NULL;
3351 cmd_buffer->state.subpass = NULL;
3352 cmd_buffer->state.attachments = NULL;
3353 cmd_buffer->state.framebuffer = NULL;
3354 }
3355
3356 /*
3357 * For HTILE we have the following interesting clear words:
3358 * 0x0000030f: Uncompressed.
3359 * 0xfffffff0: Clear depth to 1.0
3360 * 0x00000000: Clear depth to 0.0
3361 */
3362 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3363 struct radv_image *image,
3364 const VkImageSubresourceRange *range,
3365 uint32_t clear_word)
3366 {
3367 assert(range->baseMipLevel == 0);
3368 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3369 unsigned layer_count = radv_get_layerCount(image, range);
3370 uint64_t size = image->surface.htile_slice_size * layer_count;
3371 uint64_t offset = image->offset + image->htile_offset +
3372 image->surface.htile_slice_size * range->baseArrayLayer;
3373
3374 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3375 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3376
3377 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3378
3379 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3380 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3381 RADV_CMD_FLAG_INV_VMEM_L1 |
3382 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3383 }
3384
3385 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3386 struct radv_image *image,
3387 VkImageLayout src_layout,
3388 VkImageLayout dst_layout,
3389 unsigned src_queue_mask,
3390 unsigned dst_queue_mask,
3391 const VkImageSubresourceRange *range,
3392 VkImageAspectFlags pending_clears)
3393 {
3394 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3395 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3396 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3397 cmd_buffer->state.render_area.extent.width == image->info.width &&
3398 cmd_buffer->state.render_area.extent.height == image->info.height) {
3399 /* The clear will initialize htile. */
3400 return;
3401 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3402 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3403 /* TODO: merge with the clear if applicable */
3404 radv_initialize_htile(cmd_buffer, image, range, 0);
3405 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3406 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3407 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3408 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3409 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3410 VkImageSubresourceRange local_range = *range;
3411 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3412 local_range.baseMipLevel = 0;
3413 local_range.levelCount = 1;
3414
3415 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3416 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3417
3418 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3419
3420 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3421 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3422 }
3423 }
3424
3425 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3426 struct radv_image *image, uint32_t value)
3427 {
3428 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3429 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3430
3431 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3432 image->cmask.size, value);
3433
3434 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3435 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3436 RADV_CMD_FLAG_INV_VMEM_L1 |
3437 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3438 }
3439
3440 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3441 struct radv_image *image,
3442 VkImageLayout src_layout,
3443 VkImageLayout dst_layout,
3444 unsigned src_queue_mask,
3445 unsigned dst_queue_mask,
3446 const VkImageSubresourceRange *range)
3447 {
3448 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3449 if (image->fmask.size)
3450 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3451 else
3452 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3453 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3454 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3455 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3456 }
3457 }
3458
3459 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3460 struct radv_image *image, uint32_t value)
3461 {
3462
3463 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3464 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3465
3466 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3467 image->surface.dcc_size, value);
3468
3469 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3470 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3472 RADV_CMD_FLAG_INV_VMEM_L1 |
3473 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3474 }
3475
3476 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3477 struct radv_image *image,
3478 VkImageLayout src_layout,
3479 VkImageLayout dst_layout,
3480 unsigned src_queue_mask,
3481 unsigned dst_queue_mask,
3482 const VkImageSubresourceRange *range)
3483 {
3484 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3485 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3486 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3487 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3488 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3489 }
3490 }
3491
3492 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3493 struct radv_image *image,
3494 VkImageLayout src_layout,
3495 VkImageLayout dst_layout,
3496 uint32_t src_family,
3497 uint32_t dst_family,
3498 const VkImageSubresourceRange *range,
3499 VkImageAspectFlags pending_clears)
3500 {
3501 if (image->exclusive && src_family != dst_family) {
3502 /* This is an acquire or a release operation and there will be
3503 * a corresponding release/acquire. Do the transition in the
3504 * most flexible queue. */
3505
3506 assert(src_family == cmd_buffer->queue_family_index ||
3507 dst_family == cmd_buffer->queue_family_index);
3508
3509 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3510 return;
3511
3512 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3513 (src_family == RADV_QUEUE_GENERAL ||
3514 dst_family == RADV_QUEUE_GENERAL))
3515 return;
3516 }
3517
3518 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3519 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3520
3521 if (image->surface.htile_size)
3522 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3523 dst_layout, src_queue_mask,
3524 dst_queue_mask, range,
3525 pending_clears);
3526
3527 if (image->cmask.size)
3528 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3529 dst_layout, src_queue_mask,
3530 dst_queue_mask, range);
3531
3532 if (image->surface.dcc_size)
3533 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3534 dst_layout, src_queue_mask,
3535 dst_queue_mask, range);
3536 }
3537
3538 void radv_CmdPipelineBarrier(
3539 VkCommandBuffer commandBuffer,
3540 VkPipelineStageFlags srcStageMask,
3541 VkPipelineStageFlags destStageMask,
3542 VkBool32 byRegion,
3543 uint32_t memoryBarrierCount,
3544 const VkMemoryBarrier* pMemoryBarriers,
3545 uint32_t bufferMemoryBarrierCount,
3546 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3547 uint32_t imageMemoryBarrierCount,
3548 const VkImageMemoryBarrier* pImageMemoryBarriers)
3549 {
3550 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3551 enum radv_cmd_flush_bits src_flush_bits = 0;
3552 enum radv_cmd_flush_bits dst_flush_bits = 0;
3553
3554 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3555 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3556 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3557 NULL);
3558 }
3559
3560 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3561 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3562 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3563 NULL);
3564 }
3565
3566 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3567 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3568 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3569 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3570 image);
3571 }
3572
3573 radv_stage_flush(cmd_buffer, srcStageMask);
3574 cmd_buffer->state.flush_bits |= src_flush_bits;
3575
3576 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3577 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3578 radv_handle_image_transition(cmd_buffer, image,
3579 pImageMemoryBarriers[i].oldLayout,
3580 pImageMemoryBarriers[i].newLayout,
3581 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3582 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3583 &pImageMemoryBarriers[i].subresourceRange,
3584 0);
3585 }
3586
3587 cmd_buffer->state.flush_bits |= dst_flush_bits;
3588 }
3589
3590
3591 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3592 struct radv_event *event,
3593 VkPipelineStageFlags stageMask,
3594 unsigned value)
3595 {
3596 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3597 uint64_t va = radv_buffer_get_va(event->bo);
3598
3599 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3600
3601 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3602
3603 /* TODO: this is overkill. Probably should figure something out from
3604 * the stage mask. */
3605
3606 si_cs_emit_write_event_eop(cs,
3607 cmd_buffer->state.predicating,
3608 cmd_buffer->device->physical_device->rad_info.chip_class,
3609 false,
3610 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3611 1, va, 2, value);
3612
3613 assert(cmd_buffer->cs->cdw <= cdw_max);
3614 }
3615
3616 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3617 VkEvent _event,
3618 VkPipelineStageFlags stageMask)
3619 {
3620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3621 RADV_FROM_HANDLE(radv_event, event, _event);
3622
3623 write_event(cmd_buffer, event, stageMask, 1);
3624 }
3625
3626 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3627 VkEvent _event,
3628 VkPipelineStageFlags stageMask)
3629 {
3630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3631 RADV_FROM_HANDLE(radv_event, event, _event);
3632
3633 write_event(cmd_buffer, event, stageMask, 0);
3634 }
3635
3636 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3637 uint32_t eventCount,
3638 const VkEvent* pEvents,
3639 VkPipelineStageFlags srcStageMask,
3640 VkPipelineStageFlags dstStageMask,
3641 uint32_t memoryBarrierCount,
3642 const VkMemoryBarrier* pMemoryBarriers,
3643 uint32_t bufferMemoryBarrierCount,
3644 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3645 uint32_t imageMemoryBarrierCount,
3646 const VkImageMemoryBarrier* pImageMemoryBarriers)
3647 {
3648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3649 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3650
3651 for (unsigned i = 0; i < eventCount; ++i) {
3652 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3653 uint64_t va = radv_buffer_get_va(event->bo);
3654
3655 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3656
3657 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3658
3659 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3660 assert(cmd_buffer->cs->cdw <= cdw_max);
3661 }
3662
3663
3664 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3665 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3666
3667 radv_handle_image_transition(cmd_buffer, image,
3668 pImageMemoryBarriers[i].oldLayout,
3669 pImageMemoryBarriers[i].newLayout,
3670 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3671 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3672 &pImageMemoryBarriers[i].subresourceRange,
3673 0);
3674 }
3675
3676 /* TODO: figure out how to do memory barriers without waiting */
3677 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3678 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3679 RADV_CMD_FLAG_INV_VMEM_L1 |
3680 RADV_CMD_FLAG_INV_SMEM_L1;
3681 }