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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_winsys_cs *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_winsys_cs *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_winsys_cs *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
564 return &shader->info.user_sgprs_locs.shader_data[idx];
565 }
566
567 static void
568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
569 struct radv_pipeline *pipeline,
570 gl_shader_stage stage,
571 int idx, uint64_t va)
572 {
573 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
574 uint32_t base_reg = pipeline->user_data_0[stage];
575 if (loc->sgpr_idx == -1)
576 return;
577
578 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
579 assert(!loc->indirect);
580
581 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
582 base_reg + loc->sgpr_idx * 4, va, false);
583 }
584
585 static void
586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_pipeline *pipeline,
588 struct radv_descriptor_state *descriptors_state,
589 gl_shader_stage stage)
590 {
591 struct radv_device *device = cmd_buffer->device;
592 struct radeon_winsys_cs *cs = cmd_buffer->cs;
593 uint32_t sh_base = pipeline->user_data_0[stage];
594 struct radv_userdata_locations *locs =
595 &pipeline->shaders[stage]->info.user_sgprs_locs;
596 unsigned mask;
597
598 mask = descriptors_state->dirty & descriptors_state->valid;
599
600 for (int i = 0; i < MAX_SETS; i++) {
601 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
602 if (loc->sgpr_idx != -1 && !loc->indirect)
603 continue;
604 mask &= ~(1 << i);
605 }
606
607 while (mask) {
608 int start, count;
609
610 u_bit_scan_consecutive_range(&mask, &start, &count);
611
612 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
613 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
614
615 radv_emit_shader_pointer_head(cs, sh_offset, count,
616 HAVE_32BIT_POINTERS);
617 for (int i = 0; i < count; i++) {
618 struct radv_descriptor_set *set =
619 descriptors_state->sets[start + i];
620
621 radv_emit_shader_pointer_body(device, cs, set->va,
622 HAVE_32BIT_POINTERS);
623 }
624 }
625 }
626
627 static void
628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 int num_samples = pipeline->graphics.ms.num_samples;
632 struct radv_multisample_state *ms = &pipeline->graphics.ms;
633 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
634
635 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
636 cmd_buffer->sample_positions_needed = true;
637
638 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
639 return;
640
641 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
642 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
643 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
646
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
648
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer->device->dfsm_allowed) {
651 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
652 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
653 }
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 uint64_t va;
661
662 if (!shader)
663 return;
664
665 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
668 }
669
670 static void
671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
672 struct radv_pipeline *pipeline,
673 bool vertex_stage_only)
674 {
675 struct radv_cmd_state *state = &cmd_buffer->state;
676 uint32_t mask = state->prefetch_L2_mask;
677
678 if (vertex_stage_only) {
679 /* Fast prefetch path for starting draws as soon as possible.
680 */
681 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
682 RADV_PREFETCH_VBO_DESCRIPTORS);
683 }
684
685 if (mask & RADV_PREFETCH_VS)
686 radv_emit_shader_prefetch(cmd_buffer,
687 pipeline->shaders[MESA_SHADER_VERTEX]);
688
689 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
690 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
691
692 if (mask & RADV_PREFETCH_TCS)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
695
696 if (mask & RADV_PREFETCH_TES)
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
699
700 if (mask & RADV_PREFETCH_GS) {
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_GEOMETRY]);
703 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
704 }
705
706 if (mask & RADV_PREFETCH_PS)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709
710 state->prefetch_L2_mask &= ~mask;
711 }
712
713 static void
714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
715 {
716 if (!cmd_buffer->device->physical_device->rbplus_allowed)
717 return;
718
719 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
720 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722
723 unsigned sx_ps_downconvert = 0;
724 unsigned sx_blend_opt_epsilon = 0;
725 unsigned sx_blend_opt_control = 0;
726
727 for (unsigned i = 0; i < subpass->color_count; ++i) {
728 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
729 continue;
730
731 int idx = subpass->color_attachments[i].attachment;
732 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
733
734 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
735 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
736 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
737 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
738
739 bool has_alpha, has_rgb;
740
741 /* Set if RGB and A are present. */
742 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
743
744 if (format == V_028C70_COLOR_8 ||
745 format == V_028C70_COLOR_16 ||
746 format == V_028C70_COLOR_32)
747 has_rgb = !has_alpha;
748 else
749 has_rgb = true;
750
751 /* Check the colormask and export format. */
752 if (!(colormask & 0x7))
753 has_rgb = false;
754 if (!(colormask & 0x8))
755 has_alpha = false;
756
757 if (spi_format == V_028714_SPI_SHADER_ZERO) {
758 has_rgb = false;
759 has_alpha = false;
760 }
761
762 /* Disable value checking for disabled channels. */
763 if (!has_rgb)
764 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
765 if (!has_alpha)
766 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
767
768 /* Enable down-conversion for 32bpp and smaller formats. */
769 switch (format) {
770 case V_028C70_COLOR_8:
771 case V_028C70_COLOR_8_8:
772 case V_028C70_COLOR_8_8_8_8:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
776 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
778 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
779 }
780 break;
781
782 case V_028C70_COLOR_5_6_5:
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
784 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
785 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
786 }
787 break;
788
789 case V_028C70_COLOR_1_5_5_5:
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
792 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
793 }
794 break;
795
796 case V_028C70_COLOR_4_4_4_4:
797 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
798 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
799 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
800 }
801 break;
802
803 case V_028C70_COLOR_32:
804 if (swap == V_028C70_SWAP_STD &&
805 spi_format == V_028714_SPI_SHADER_32_R)
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
807 else if (swap == V_028C70_SWAP_ALT_REV &&
808 spi_format == V_028714_SPI_SHADER_32_AR)
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
810 break;
811
812 case V_028C70_COLOR_16:
813 case V_028C70_COLOR_16_16:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
818 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
819 if (swap == V_028C70_SWAP_STD ||
820 swap == V_028C70_SWAP_STD_REV)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
822 else
823 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
824 }
825 break;
826
827 case V_028C70_COLOR_10_11_11:
828 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
830 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
831 }
832 break;
833
834 case V_028C70_COLOR_2_10_10_10:
835 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
837 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
838 }
839 break;
840 }
841 }
842
843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
844 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
845 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
846 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
847 }
848
849 static void
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
851 {
852 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
853
854 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
855 return;
856
857 radv_update_multisample_state(cmd_buffer, pipeline);
858
859 cmd_buffer->scratch_size_needed =
860 MAX2(cmd_buffer->scratch_size_needed,
861 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
862
863 if (!cmd_buffer->state.emitted_pipeline ||
864 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
865 pipeline->graphics.can_use_guardband)
866 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
867
868 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
869
870 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
871 if (!pipeline->shaders[i])
872 continue;
873
874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
875 pipeline->shaders[i]->bo, 8);
876 }
877
878 if (radv_pipeline_has_gs(pipeline))
879 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
880 pipeline->gs_copy_shader->bo, 8);
881
882 if (unlikely(cmd_buffer->device->trace_bo))
883 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
884
885 cmd_buffer->state.emitted_pipeline = pipeline;
886
887 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
888 }
889
890 static void
891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
892 {
893 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
894 cmd_buffer->state.dynamic.viewport.viewports);
895 }
896
897 static void
898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
899 {
900 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
901
902 si_write_scissors(cmd_buffer->cs, 0, count,
903 cmd_buffer->state.dynamic.scissor.scissors,
904 cmd_buffer->state.dynamic.viewport.viewports,
905 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
906 }
907
908 static void
909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
910 {
911 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
912 return;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
915 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
916 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
917 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
918 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
919 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
920 S_028214_BR_Y(rect.offset.y + rect.extent.height));
921 }
922 }
923
924 static void
925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
926 {
927 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
930 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
931 }
932
933 static void
934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
935 {
936 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
937
938 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
939 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
940 }
941
942 static void
943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs,
948 R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cmd_buffer->cs,
950 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
951 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
952 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer->cs,
955 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
956 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
957 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
958 S_028434_STENCILOPVAL_BF(1));
959 }
960
961 static void
962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
967 fui(d->depth_bounds.min));
968 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
969 fui(d->depth_bounds.max));
970 }
971
972 static void
973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
974 {
975 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
976 unsigned slope = fui(d->depth_bias.slope * 16.0f);
977 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
978
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
982 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
983 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
986 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
987 }
988
989 static void
990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
991 int index,
992 struct radv_attachment_info *att,
993 struct radv_image *image,
994 VkImageLayout layout)
995 {
996 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
997 struct radv_color_buffer_info *cb = &att->cb;
998 uint32_t cb_color_info = cb->cb_color_info;
999
1000 if (!radv_layout_dcc_compressed(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 cb_color_info &= C_028C70_DCC_ENABLE;
1005 }
1006
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013 radeon_emit(cmd_buffer->cs, cb_color_info);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041 if (is_vi) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043 }
1044 }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_ds_buffer_info *ds,
1050 struct radv_image *image, VkImageLayout layout,
1051 bool requires_cond_write)
1052 {
1053 uint32_t db_z_info = ds->db_z_info;
1054 uint32_t db_z_info_reg;
1055
1056 if (!radv_image_is_tc_compat_htile(image))
1057 return;
1058
1059 if (!radv_layout_has_htile(image, layout,
1060 radv_image_queue_family_mask(image,
1061 cmd_buffer->queue_family_index,
1062 cmd_buffer->queue_family_index))) {
1063 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064 }
1065
1066 db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069 db_z_info_reg = R_028038_DB_Z_INFO;
1070 } else {
1071 db_z_info_reg = R_028040_DB_Z_INFO;
1072 }
1073
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1076 */
1077 if (requires_cond_write) {
1078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080 const uint32_t write_space = 0 << 8; /* register */
1081 const uint32_t poll_space = 1 << 4; /* memory */
1082 const uint32_t function = 3 << 0; /* equal to the reference */
1083 const uint32_t options = write_space | poll_space | function;
1084 radeon_emit(cmd_buffer->cs, options);
1085
1086 /* poll address - location of the depth clear value */
1087 uint64_t va = radv_buffer_get_va(image->bo);
1088 va += image->offset + image->clear_value_offset;
1089
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1092 */
1093 if (vk_format_is_stencil(image->vk_format))
1094 va += 4;
1095
1096 radeon_emit(cmd_buffer->cs, va);
1097 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1100 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1103 radeon_emit(cmd_buffer->cs, db_z_info);
1104 } else {
1105 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106 }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1177 */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 VkClearDepthStencilValue ds_clear_value)
1182 {
1183 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1184 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1185 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1186 struct radv_attachment_info *att;
1187 uint32_t att_idx;
1188
1189 if (!framebuffer || !subpass)
1190 return;
1191
1192 att_idx = subpass->depth_stencil_attachment.attachment;
1193 if (att_idx == VK_ATTACHMENT_UNUSED)
1194 return;
1195
1196 att = &framebuffer->attachments[att_idx];
1197 if (att->attachment->image != image)
1198 return;
1199
1200 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1201 radeon_emit(cs, ds_clear_value.stencil);
1202 radeon_emit(cs, fui(ds_clear_value.depth));
1203 }
1204
1205 void
1206 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1207 struct radv_image *image,
1208 VkClearDepthStencilValue ds_clear_value,
1209 VkImageAspectFlags aspects)
1210 {
1211 uint64_t va = radv_buffer_get_va(image->bo);
1212 va += image->offset + image->clear_value_offset;
1213 unsigned reg_offset = 0, reg_count = 0;
1214
1215 assert(radv_image_has_htile(image));
1216
1217 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1218 ++reg_count;
1219 } else {
1220 ++reg_offset;
1221 va += 4;
1222 }
1223 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1224 ++reg_count;
1225
1226 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1227 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1228 S_370_WR_CONFIRM(1) |
1229 S_370_ENGINE_SEL(V_370_PFP));
1230 radeon_emit(cmd_buffer->cs, va);
1231 radeon_emit(cmd_buffer->cs, va >> 32);
1232 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1233 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1234 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1235 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1236
1237 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value);
1238
1239 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1240 * only needed when clearing Z to 0.0.
1241 */
1242 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1243 ds_clear_value.depth == 0.0) {
1244 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1245 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1246
1247 if (!framebuffer || !subpass)
1248 return;
1249
1250 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1251 return;
1252
1253 int idx = subpass->depth_stencil_attachment.attachment;
1254 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1255 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1256 struct radv_image *image = att->attachment->image;
1257
1258 /* Only needed if the image is currently bound as the depth
1259 * surface.
1260 */
1261 if (att->attachment->image != image)
1262 return;
1263
1264 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1265 layout, false);
1266 }
1267 }
1268
1269 static void
1270 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1271 struct radv_image *image)
1272 {
1273 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1274 uint64_t va = radv_buffer_get_va(image->bo);
1275 va += image->offset + image->clear_value_offset;
1276 unsigned reg_offset = 0, reg_count = 0;
1277
1278 if (!radv_image_has_htile(image))
1279 return;
1280
1281 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1282 ++reg_count;
1283 } else {
1284 ++reg_offset;
1285 va += 4;
1286 }
1287 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1288 ++reg_count;
1289
1290 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1291 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1292 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1293 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1294 radeon_emit(cmd_buffer->cs, va);
1295 radeon_emit(cmd_buffer->cs, va >> 32);
1296 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1297 radeon_emit(cmd_buffer->cs, 0);
1298
1299 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1300 radeon_emit(cmd_buffer->cs, 0);
1301 }
1302
1303 /*
1304 * With DCC some colors don't require CMASK elimination before being
1305 * used as a texture. This sets a predicate value to determine if the
1306 * cmask eliminate is required.
1307 */
1308 void
1309 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1310 struct radv_image *image,
1311 bool value)
1312 {
1313 uint64_t pred_val = value;
1314 uint64_t va = radv_buffer_get_va(image->bo);
1315 va += image->offset + image->dcc_pred_offset;
1316
1317 assert(radv_image_has_dcc(image));
1318
1319 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1320 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1321 S_370_WR_CONFIRM(1) |
1322 S_370_ENGINE_SEL(V_370_PFP));
1323 radeon_emit(cmd_buffer->cs, va);
1324 radeon_emit(cmd_buffer->cs, va >> 32);
1325 radeon_emit(cmd_buffer->cs, pred_val);
1326 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1327 }
1328
1329 /**
1330 * Update the fast clear color values if the image is bound as a color buffer.
1331 */
1332 static void
1333 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1334 struct radv_image *image,
1335 int cb_idx,
1336 uint32_t color_values[2])
1337 {
1338 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1339 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1340 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1341 struct radv_attachment_info *att;
1342 uint32_t att_idx;
1343
1344 if (!framebuffer || !subpass)
1345 return;
1346
1347 att_idx = subpass->color_attachments[cb_idx].attachment;
1348 if (att_idx == VK_ATTACHMENT_UNUSED)
1349 return;
1350
1351 att = &framebuffer->attachments[att_idx];
1352 if (att->attachment->image != image)
1353 return;
1354
1355 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1356 radeon_emit(cs, color_values[0]);
1357 radeon_emit(cs, color_values[1]);
1358 }
1359
1360 /**
1361 * Set the clear color values to the image's metadata.
1362 */
1363 void
1364 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1365 struct radv_image *image,
1366 int cb_idx,
1367 uint32_t color_values[2])
1368 {
1369 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1370 uint64_t va = radv_buffer_get_va(image->bo);
1371
1372 va += image->offset + image->clear_value_offset;
1373
1374 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1375
1376 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1377 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1378 S_370_WR_CONFIRM(1) |
1379 S_370_ENGINE_SEL(V_370_PFP));
1380 radeon_emit(cs, va);
1381 radeon_emit(cs, va >> 32);
1382 radeon_emit(cs, color_values[0]);
1383 radeon_emit(cs, color_values[1]);
1384
1385 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1386 color_values);
1387 }
1388
1389 /**
1390 * Load the clear color values from the image's metadata.
1391 */
1392 static void
1393 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int cb_idx)
1396 {
1397 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1398 uint64_t va = radv_buffer_get_va(image->bo);
1399
1400 va += image->offset + image->clear_value_offset;
1401
1402 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1403 return;
1404
1405 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1406
1407 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1408 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1409 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1410 COPY_DATA_COUNT_SEL);
1411 radeon_emit(cs, va);
1412 radeon_emit(cs, va >> 32);
1413 radeon_emit(cs, reg >> 2);
1414 radeon_emit(cs, 0);
1415
1416 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1417 radeon_emit(cs, 0);
1418 }
1419
1420 static void
1421 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1422 {
1423 int i;
1424 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1425 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1426
1427 /* this may happen for inherited secondary recording */
1428 if (!framebuffer)
1429 return;
1430
1431 for (i = 0; i < 8; ++i) {
1432 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1433 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1434 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1435 continue;
1436 }
1437
1438 int idx = subpass->color_attachments[i].attachment;
1439 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1440 struct radv_image *image = att->attachment->image;
1441 VkImageLayout layout = subpass->color_attachments[i].layout;
1442
1443 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1444
1445 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1446 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1447
1448 radv_load_color_clear_metadata(cmd_buffer, image, i);
1449 }
1450
1451 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1452 int idx = subpass->depth_stencil_attachment.attachment;
1453 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1454 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1455 struct radv_image *image = att->attachment->image;
1456 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1457 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1458 cmd_buffer->queue_family_index,
1459 cmd_buffer->queue_family_index);
1460 /* We currently don't support writing decompressed HTILE */
1461 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1462 radv_layout_is_htile_compressed(image, layout, queue_mask));
1463
1464 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1465
1466 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1467 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1468 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1469 }
1470 radv_load_depth_clear_regs(cmd_buffer, image);
1471 } else {
1472 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1473 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1474 else
1475 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1476
1477 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1478 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1479 }
1480 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1481 S_028208_BR_X(framebuffer->width) |
1482 S_028208_BR_Y(framebuffer->height));
1483
1484 if (cmd_buffer->device->dfsm_allowed) {
1485 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1486 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1487 }
1488
1489 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1490 }
1491
1492 static void
1493 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1494 {
1495 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1496 struct radv_cmd_state *state = &cmd_buffer->state;
1497
1498 if (state->index_type != state->last_index_type) {
1499 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1500 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1501 2, state->index_type);
1502 } else {
1503 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1504 radeon_emit(cs, state->index_type);
1505 }
1506
1507 state->last_index_type = state->index_type;
1508 }
1509
1510 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1511 radeon_emit(cs, state->index_va);
1512 radeon_emit(cs, state->index_va >> 32);
1513
1514 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1515 radeon_emit(cs, state->max_index_count);
1516
1517 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1518 }
1519
1520 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1521 {
1522 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1523 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1524 uint32_t pa_sc_mode_cntl_1 =
1525 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1526 uint32_t db_count_control;
1527
1528 if(!cmd_buffer->state.active_occlusion_queries) {
1529 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1530 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1531 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1532 has_perfect_queries) {
1533 /* Re-enable out-of-order rasterization if the
1534 * bound pipeline supports it and if it's has
1535 * been disabled before starting any perfect
1536 * occlusion queries.
1537 */
1538 radeon_set_context_reg(cmd_buffer->cs,
1539 R_028A4C_PA_SC_MODE_CNTL_1,
1540 pa_sc_mode_cntl_1);
1541 }
1542 db_count_control = 0;
1543 } else {
1544 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1545 }
1546 } else {
1547 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1548 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1549
1550 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1551 db_count_control =
1552 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1553 S_028004_SAMPLE_RATE(sample_rate) |
1554 S_028004_ZPASS_ENABLE(1) |
1555 S_028004_SLICE_EVEN_ENABLE(1) |
1556 S_028004_SLICE_ODD_ENABLE(1);
1557
1558 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1559 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1560 has_perfect_queries) {
1561 /* If the bound pipeline has enabled
1562 * out-of-order rasterization, we should
1563 * disable it before starting any perfect
1564 * occlusion queries.
1565 */
1566 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1567
1568 radeon_set_context_reg(cmd_buffer->cs,
1569 R_028A4C_PA_SC_MODE_CNTL_1,
1570 pa_sc_mode_cntl_1);
1571 }
1572 } else {
1573 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1574 S_028004_SAMPLE_RATE(sample_rate);
1575 }
1576 }
1577
1578 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1579 }
1580
1581 static void
1582 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1583 {
1584 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1585
1586 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1587 radv_emit_viewport(cmd_buffer);
1588
1589 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1590 !cmd_buffer->device->physical_device->has_scissor_bug)
1591 radv_emit_scissor(cmd_buffer);
1592
1593 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1594 radv_emit_line_width(cmd_buffer);
1595
1596 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1597 radv_emit_blend_constants(cmd_buffer);
1598
1599 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1600 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1601 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1602 radv_emit_stencil(cmd_buffer);
1603
1604 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1605 radv_emit_depth_bounds(cmd_buffer);
1606
1607 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1608 radv_emit_depth_bias(cmd_buffer);
1609
1610 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1611 radv_emit_discard_rectangle(cmd_buffer);
1612
1613 cmd_buffer->state.dirty &= ~states;
1614 }
1615
1616 static void
1617 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1618 VkPipelineBindPoint bind_point)
1619 {
1620 struct radv_descriptor_state *descriptors_state =
1621 radv_get_descriptors_state(cmd_buffer, bind_point);
1622 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1623 unsigned bo_offset;
1624
1625 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1626 set->mapped_ptr,
1627 &bo_offset))
1628 return;
1629
1630 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1631 set->va += bo_offset;
1632 }
1633
1634 static void
1635 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1636 VkPipelineBindPoint bind_point)
1637 {
1638 struct radv_descriptor_state *descriptors_state =
1639 radv_get_descriptors_state(cmd_buffer, bind_point);
1640 uint32_t size = MAX_SETS * 2 * 4;
1641 uint32_t offset;
1642 void *ptr;
1643
1644 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1645 256, &offset, &ptr))
1646 return;
1647
1648 for (unsigned i = 0; i < MAX_SETS; i++) {
1649 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1650 uint64_t set_va = 0;
1651 struct radv_descriptor_set *set = descriptors_state->sets[i];
1652 if (descriptors_state->valid & (1u << i))
1653 set_va = set->va;
1654 uptr[0] = set_va & 0xffffffff;
1655 uptr[1] = set_va >> 32;
1656 }
1657
1658 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1659 va += offset;
1660
1661 if (cmd_buffer->state.pipeline) {
1662 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1663 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1664 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1665
1666 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1667 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1668 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1669
1670 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1671 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1672 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1673
1674 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1675 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1676 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1677
1678 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1679 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1680 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1681 }
1682
1683 if (cmd_buffer->state.compute_pipeline)
1684 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1685 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1686 }
1687
1688 static void
1689 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1690 VkShaderStageFlags stages)
1691 {
1692 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1693 VK_PIPELINE_BIND_POINT_COMPUTE :
1694 VK_PIPELINE_BIND_POINT_GRAPHICS;
1695 struct radv_descriptor_state *descriptors_state =
1696 radv_get_descriptors_state(cmd_buffer, bind_point);
1697
1698 if (!descriptors_state->dirty)
1699 return;
1700
1701 if (descriptors_state->push_dirty)
1702 radv_flush_push_descriptors(cmd_buffer, bind_point);
1703
1704 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1705 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1706 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1707 }
1708
1709 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1710 cmd_buffer->cs,
1711 MAX_SETS * MESA_SHADER_STAGES * 4);
1712
1713 if (cmd_buffer->state.pipeline) {
1714 radv_foreach_stage(stage, stages) {
1715 if (!cmd_buffer->state.pipeline->shaders[stage])
1716 continue;
1717
1718 radv_emit_descriptor_pointers(cmd_buffer,
1719 cmd_buffer->state.pipeline,
1720 descriptors_state, stage);
1721 }
1722 }
1723
1724 if (cmd_buffer->state.compute_pipeline &&
1725 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1726 radv_emit_descriptor_pointers(cmd_buffer,
1727 cmd_buffer->state.compute_pipeline,
1728 descriptors_state,
1729 MESA_SHADER_COMPUTE);
1730 }
1731
1732 descriptors_state->dirty = 0;
1733 descriptors_state->push_dirty = false;
1734
1735 if (unlikely(cmd_buffer->device->trace_bo))
1736 radv_save_descriptors(cmd_buffer, bind_point);
1737
1738 assert(cmd_buffer->cs->cdw <= cdw_max);
1739 }
1740
1741 static void
1742 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1743 VkShaderStageFlags stages)
1744 {
1745 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1746 ? cmd_buffer->state.compute_pipeline
1747 : cmd_buffer->state.pipeline;
1748 struct radv_pipeline_layout *layout = pipeline->layout;
1749 struct radv_shader_variant *shader, *prev_shader;
1750 unsigned offset;
1751 void *ptr;
1752 uint64_t va;
1753
1754 stages &= cmd_buffer->push_constant_stages;
1755 if (!stages ||
1756 (!layout->push_constant_size && !layout->dynamic_offset_count))
1757 return;
1758
1759 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1760 16 * layout->dynamic_offset_count,
1761 256, &offset, &ptr))
1762 return;
1763
1764 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1765 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1766 16 * layout->dynamic_offset_count);
1767
1768 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1769 va += offset;
1770
1771 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1772 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1773
1774 prev_shader = NULL;
1775 radv_foreach_stage(stage, stages) {
1776 shader = radv_get_shader(pipeline, stage);
1777
1778 /* Avoid redundantly emitting the address for merged stages. */
1779 if (shader && shader != prev_shader) {
1780 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1781 AC_UD_PUSH_CONSTANTS, va);
1782
1783 prev_shader = shader;
1784 }
1785 }
1786
1787 cmd_buffer->push_constant_stages &= ~stages;
1788 assert(cmd_buffer->cs->cdw <= cdw_max);
1789 }
1790
1791 static void
1792 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1793 bool pipeline_is_dirty)
1794 {
1795 if ((pipeline_is_dirty ||
1796 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1797 cmd_buffer->state.pipeline->vertex_elements.count &&
1798 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1799 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1800 unsigned vb_offset;
1801 void *vb_ptr;
1802 uint32_t i = 0;
1803 uint32_t count = velems->count;
1804 uint64_t va;
1805
1806 /* allocate some descriptor state for vertex buffers */
1807 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1808 &vb_offset, &vb_ptr))
1809 return;
1810
1811 for (i = 0; i < count; i++) {
1812 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1813 uint32_t offset;
1814 int vb = velems->binding[i];
1815 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1816 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1817
1818 va = radv_buffer_get_va(buffer->bo);
1819
1820 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1821 va += offset + buffer->offset;
1822 desc[0] = va;
1823 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1824 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1825 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1826 else
1827 desc[2] = buffer->size - offset;
1828 desc[3] = velems->rsrc_word3[i];
1829 }
1830
1831 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1832 va += vb_offset;
1833
1834 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1835 AC_UD_VS_VERTEX_BUFFERS, va);
1836
1837 cmd_buffer->state.vb_va = va;
1838 cmd_buffer->state.vb_size = count * 16;
1839 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1840 }
1841 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1842 }
1843
1844 static void
1845 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1846 {
1847 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1848 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1849 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1850 }
1851
1852 static void
1853 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1854 bool instanced_draw, bool indirect_draw,
1855 uint32_t draw_vertex_count)
1856 {
1857 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1858 struct radv_cmd_state *state = &cmd_buffer->state;
1859 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1860 uint32_t ia_multi_vgt_param;
1861 int32_t primitive_reset_en;
1862
1863 /* Draw state. */
1864 ia_multi_vgt_param =
1865 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1866 indirect_draw, draw_vertex_count);
1867
1868 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1869 if (info->chip_class >= GFX9) {
1870 radeon_set_uconfig_reg_idx(cs,
1871 R_030960_IA_MULTI_VGT_PARAM,
1872 4, ia_multi_vgt_param);
1873 } else if (info->chip_class >= CIK) {
1874 radeon_set_context_reg_idx(cs,
1875 R_028AA8_IA_MULTI_VGT_PARAM,
1876 1, ia_multi_vgt_param);
1877 } else {
1878 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1879 ia_multi_vgt_param);
1880 }
1881 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1882 }
1883
1884 /* Primitive restart. */
1885 primitive_reset_en =
1886 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1887
1888 if (primitive_reset_en != state->last_primitive_reset_en) {
1889 state->last_primitive_reset_en = primitive_reset_en;
1890 if (info->chip_class >= GFX9) {
1891 radeon_set_uconfig_reg(cs,
1892 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1893 primitive_reset_en);
1894 } else {
1895 radeon_set_context_reg(cs,
1896 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1897 primitive_reset_en);
1898 }
1899 }
1900
1901 if (primitive_reset_en) {
1902 uint32_t primitive_reset_index =
1903 state->index_type ? 0xffffffffu : 0xffffu;
1904
1905 if (primitive_reset_index != state->last_primitive_reset_index) {
1906 radeon_set_context_reg(cs,
1907 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1908 primitive_reset_index);
1909 state->last_primitive_reset_index = primitive_reset_index;
1910 }
1911 }
1912 }
1913
1914 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1915 VkPipelineStageFlags src_stage_mask)
1916 {
1917 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1918 VK_PIPELINE_STAGE_TRANSFER_BIT |
1919 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1920 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1921 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1922 }
1923
1924 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1925 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1926 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1927 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1928 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1929 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1930 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1931 VK_PIPELINE_STAGE_TRANSFER_BIT |
1932 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1933 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1934 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1936 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1937 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1938 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1939 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1940 }
1941 }
1942
1943 static enum radv_cmd_flush_bits
1944 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1945 VkAccessFlags src_flags)
1946 {
1947 enum radv_cmd_flush_bits flush_bits = 0;
1948 uint32_t b;
1949 for_each_bit(b, src_flags) {
1950 switch ((VkAccessFlagBits)(1 << b)) {
1951 case VK_ACCESS_SHADER_WRITE_BIT:
1952 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1953 break;
1954 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1955 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1957 break;
1958 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1959 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1960 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1961 break;
1962 case VK_ACCESS_TRANSFER_WRITE_BIT:
1963 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1964 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1965 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1967 RADV_CMD_FLAG_INV_GLOBAL_L2;
1968 break;
1969 default:
1970 break;
1971 }
1972 }
1973 return flush_bits;
1974 }
1975
1976 static enum radv_cmd_flush_bits
1977 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1978 VkAccessFlags dst_flags,
1979 struct radv_image *image)
1980 {
1981 enum radv_cmd_flush_bits flush_bits = 0;
1982 uint32_t b;
1983 for_each_bit(b, dst_flags) {
1984 switch ((VkAccessFlagBits)(1 << b)) {
1985 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1986 case VK_ACCESS_INDEX_READ_BIT:
1987 break;
1988 case VK_ACCESS_UNIFORM_READ_BIT:
1989 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1990 break;
1991 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1992 case VK_ACCESS_SHADER_READ_BIT:
1993 case VK_ACCESS_TRANSFER_READ_BIT:
1994 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1995 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1996 RADV_CMD_FLAG_INV_GLOBAL_L2;
1997 break;
1998 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1999 /* TODO: change to image && when the image gets passed
2000 * through from the subpass. */
2001 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2002 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2004 break;
2005 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2006 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2007 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2008 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2009 break;
2010 default:
2011 break;
2012 }
2013 }
2014 return flush_bits;
2015 }
2016
2017 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2018 {
2019 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2020 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2021 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2022 NULL);
2023 }
2024
2025 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2026 VkAttachmentReference att)
2027 {
2028 unsigned idx = att.attachment;
2029 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2030 VkImageSubresourceRange range;
2031 range.aspectMask = 0;
2032 range.baseMipLevel = view->base_mip;
2033 range.levelCount = 1;
2034 range.baseArrayLayer = view->base_layer;
2035 range.layerCount = cmd_buffer->state.framebuffer->layers;
2036
2037 radv_handle_image_transition(cmd_buffer,
2038 view->image,
2039 cmd_buffer->state.attachments[idx].current_layout,
2040 att.layout, 0, 0, &range,
2041 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2042
2043 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2044
2045
2046 }
2047
2048 void
2049 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2050 const struct radv_subpass *subpass, bool transitions)
2051 {
2052 if (transitions) {
2053 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2054
2055 for (unsigned i = 0; i < subpass->color_count; ++i) {
2056 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2057 radv_handle_subpass_image_transition(cmd_buffer,
2058 subpass->color_attachments[i]);
2059 }
2060
2061 for (unsigned i = 0; i < subpass->input_count; ++i) {
2062 radv_handle_subpass_image_transition(cmd_buffer,
2063 subpass->input_attachments[i]);
2064 }
2065
2066 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2067 radv_handle_subpass_image_transition(cmd_buffer,
2068 subpass->depth_stencil_attachment);
2069 }
2070 }
2071
2072 cmd_buffer->state.subpass = subpass;
2073
2074 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2075 }
2076
2077 static VkResult
2078 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2079 struct radv_render_pass *pass,
2080 const VkRenderPassBeginInfo *info)
2081 {
2082 struct radv_cmd_state *state = &cmd_buffer->state;
2083
2084 if (pass->attachment_count == 0) {
2085 state->attachments = NULL;
2086 return VK_SUCCESS;
2087 }
2088
2089 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2090 pass->attachment_count *
2091 sizeof(state->attachments[0]),
2092 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2093 if (state->attachments == NULL) {
2094 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2095 return cmd_buffer->record_result;
2096 }
2097
2098 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2099 struct radv_render_pass_attachment *att = &pass->attachments[i];
2100 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2101 VkImageAspectFlags clear_aspects = 0;
2102
2103 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2104 /* color attachment */
2105 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2106 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2107 }
2108 } else {
2109 /* depthstencil attachment */
2110 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2111 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2112 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2113 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2114 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2115 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2116 }
2117 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2118 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2119 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2120 }
2121 }
2122
2123 state->attachments[i].pending_clear_aspects = clear_aspects;
2124 state->attachments[i].cleared_views = 0;
2125 if (clear_aspects && info) {
2126 assert(info->clearValueCount > i);
2127 state->attachments[i].clear_value = info->pClearValues[i];
2128 }
2129
2130 state->attachments[i].current_layout = att->initial_layout;
2131 }
2132
2133 return VK_SUCCESS;
2134 }
2135
2136 VkResult radv_AllocateCommandBuffers(
2137 VkDevice _device,
2138 const VkCommandBufferAllocateInfo *pAllocateInfo,
2139 VkCommandBuffer *pCommandBuffers)
2140 {
2141 RADV_FROM_HANDLE(radv_device, device, _device);
2142 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2143
2144 VkResult result = VK_SUCCESS;
2145 uint32_t i;
2146
2147 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2148
2149 if (!list_empty(&pool->free_cmd_buffers)) {
2150 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2151
2152 list_del(&cmd_buffer->pool_link);
2153 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2154
2155 result = radv_reset_cmd_buffer(cmd_buffer);
2156 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2157 cmd_buffer->level = pAllocateInfo->level;
2158
2159 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2160 } else {
2161 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2162 &pCommandBuffers[i]);
2163 }
2164 if (result != VK_SUCCESS)
2165 break;
2166 }
2167
2168 if (result != VK_SUCCESS) {
2169 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2170 i, pCommandBuffers);
2171
2172 /* From the Vulkan 1.0.66 spec:
2173 *
2174 * "vkAllocateCommandBuffers can be used to create multiple
2175 * command buffers. If the creation of any of those command
2176 * buffers fails, the implementation must destroy all
2177 * successfully created command buffer objects from this
2178 * command, set all entries of the pCommandBuffers array to
2179 * NULL and return the error."
2180 */
2181 memset(pCommandBuffers, 0,
2182 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2183 }
2184
2185 return result;
2186 }
2187
2188 void radv_FreeCommandBuffers(
2189 VkDevice device,
2190 VkCommandPool commandPool,
2191 uint32_t commandBufferCount,
2192 const VkCommandBuffer *pCommandBuffers)
2193 {
2194 for (uint32_t i = 0; i < commandBufferCount; i++) {
2195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2196
2197 if (cmd_buffer) {
2198 if (cmd_buffer->pool) {
2199 list_del(&cmd_buffer->pool_link);
2200 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2201 } else
2202 radv_cmd_buffer_destroy(cmd_buffer);
2203
2204 }
2205 }
2206 }
2207
2208 VkResult radv_ResetCommandBuffer(
2209 VkCommandBuffer commandBuffer,
2210 VkCommandBufferResetFlags flags)
2211 {
2212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2213 return radv_reset_cmd_buffer(cmd_buffer);
2214 }
2215
2216 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2217 {
2218 struct radv_device *device = cmd_buffer->device;
2219 if (device->gfx_init) {
2220 uint64_t va = radv_buffer_get_va(device->gfx_init);
2221 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2222 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2223 radeon_emit(cmd_buffer->cs, va);
2224 radeon_emit(cmd_buffer->cs, va >> 32);
2225 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2226 } else
2227 si_init_config(cmd_buffer);
2228 }
2229
2230 VkResult radv_BeginCommandBuffer(
2231 VkCommandBuffer commandBuffer,
2232 const VkCommandBufferBeginInfo *pBeginInfo)
2233 {
2234 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2235 VkResult result = VK_SUCCESS;
2236
2237 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2238 /* If the command buffer has already been resetted with
2239 * vkResetCommandBuffer, no need to do it again.
2240 */
2241 result = radv_reset_cmd_buffer(cmd_buffer);
2242 if (result != VK_SUCCESS)
2243 return result;
2244 }
2245
2246 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2247 cmd_buffer->state.last_primitive_reset_en = -1;
2248 cmd_buffer->state.last_index_type = -1;
2249 cmd_buffer->state.last_num_instances = -1;
2250 cmd_buffer->state.last_vertex_offset = -1;
2251 cmd_buffer->state.last_first_instance = -1;
2252 cmd_buffer->usage_flags = pBeginInfo->flags;
2253
2254 /* setup initial configuration into command buffer */
2255 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2256 switch (cmd_buffer->queue_family_index) {
2257 case RADV_QUEUE_GENERAL:
2258 emit_gfx_buffer_state(cmd_buffer);
2259 break;
2260 case RADV_QUEUE_COMPUTE:
2261 si_init_compute(cmd_buffer);
2262 break;
2263 case RADV_QUEUE_TRANSFER:
2264 default:
2265 break;
2266 }
2267 }
2268
2269 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2270 assert(pBeginInfo->pInheritanceInfo);
2271 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2272 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2273
2274 struct radv_subpass *subpass =
2275 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2276
2277 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2278 if (result != VK_SUCCESS)
2279 return result;
2280
2281 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2282 }
2283
2284 if (unlikely(cmd_buffer->device->trace_bo))
2285 radv_cmd_buffer_trace_emit(cmd_buffer);
2286
2287 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2288
2289 return result;
2290 }
2291
2292 void radv_CmdBindVertexBuffers(
2293 VkCommandBuffer commandBuffer,
2294 uint32_t firstBinding,
2295 uint32_t bindingCount,
2296 const VkBuffer* pBuffers,
2297 const VkDeviceSize* pOffsets)
2298 {
2299 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2300 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2301 bool changed = false;
2302
2303 /* We have to defer setting up vertex buffer since we need the buffer
2304 * stride from the pipeline. */
2305
2306 assert(firstBinding + bindingCount <= MAX_VBS);
2307 for (uint32_t i = 0; i < bindingCount; i++) {
2308 uint32_t idx = firstBinding + i;
2309
2310 if (!changed &&
2311 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2312 vb[idx].offset != pOffsets[i])) {
2313 changed = true;
2314 }
2315
2316 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2317 vb[idx].offset = pOffsets[i];
2318
2319 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2320 vb[idx].buffer->bo, 8);
2321 }
2322
2323 if (!changed) {
2324 /* No state changes. */
2325 return;
2326 }
2327
2328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2329 }
2330
2331 void radv_CmdBindIndexBuffer(
2332 VkCommandBuffer commandBuffer,
2333 VkBuffer buffer,
2334 VkDeviceSize offset,
2335 VkIndexType indexType)
2336 {
2337 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2338 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2339
2340 if (cmd_buffer->state.index_buffer == index_buffer &&
2341 cmd_buffer->state.index_offset == offset &&
2342 cmd_buffer->state.index_type == indexType) {
2343 /* No state changes. */
2344 return;
2345 }
2346
2347 cmd_buffer->state.index_buffer = index_buffer;
2348 cmd_buffer->state.index_offset = offset;
2349 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2350 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2351 cmd_buffer->state.index_va += index_buffer->offset + offset;
2352
2353 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2354 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2355 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2356 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2357 }
2358
2359
2360 static void
2361 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2362 VkPipelineBindPoint bind_point,
2363 struct radv_descriptor_set *set, unsigned idx)
2364 {
2365 struct radeon_winsys *ws = cmd_buffer->device->ws;
2366
2367 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2368 if (!set)
2369 return;
2370
2371 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2372
2373 if (!cmd_buffer->device->use_global_bo_list) {
2374 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2375 if (set->descriptors[j])
2376 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2377 }
2378
2379 if(set->bo)
2380 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2381 }
2382
2383 void radv_CmdBindDescriptorSets(
2384 VkCommandBuffer commandBuffer,
2385 VkPipelineBindPoint pipelineBindPoint,
2386 VkPipelineLayout _layout,
2387 uint32_t firstSet,
2388 uint32_t descriptorSetCount,
2389 const VkDescriptorSet* pDescriptorSets,
2390 uint32_t dynamicOffsetCount,
2391 const uint32_t* pDynamicOffsets)
2392 {
2393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2394 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2395 unsigned dyn_idx = 0;
2396
2397 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2398
2399 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2400 unsigned idx = i + firstSet;
2401 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2402 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2403
2404 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2405 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2406 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2407 assert(dyn_idx < dynamicOffsetCount);
2408
2409 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2410 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2411 dst[0] = va;
2412 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2413 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2414 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2415 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2416 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2417 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2418 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2419 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2420 cmd_buffer->push_constant_stages |=
2421 set->layout->dynamic_shader_stages;
2422 }
2423 }
2424 }
2425
2426 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2427 struct radv_descriptor_set *set,
2428 struct radv_descriptor_set_layout *layout,
2429 VkPipelineBindPoint bind_point)
2430 {
2431 struct radv_descriptor_state *descriptors_state =
2432 radv_get_descriptors_state(cmd_buffer, bind_point);
2433 set->size = layout->size;
2434 set->layout = layout;
2435
2436 if (descriptors_state->push_set.capacity < set->size) {
2437 size_t new_size = MAX2(set->size, 1024);
2438 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2439 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2440
2441 free(set->mapped_ptr);
2442 set->mapped_ptr = malloc(new_size);
2443
2444 if (!set->mapped_ptr) {
2445 descriptors_state->push_set.capacity = 0;
2446 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2447 return false;
2448 }
2449
2450 descriptors_state->push_set.capacity = new_size;
2451 }
2452
2453 return true;
2454 }
2455
2456 void radv_meta_push_descriptor_set(
2457 struct radv_cmd_buffer* cmd_buffer,
2458 VkPipelineBindPoint pipelineBindPoint,
2459 VkPipelineLayout _layout,
2460 uint32_t set,
2461 uint32_t descriptorWriteCount,
2462 const VkWriteDescriptorSet* pDescriptorWrites)
2463 {
2464 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2465 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2466 unsigned bo_offset;
2467
2468 assert(set == 0);
2469 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2470
2471 push_set->size = layout->set[set].layout->size;
2472 push_set->layout = layout->set[set].layout;
2473
2474 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2475 &bo_offset,
2476 (void**) &push_set->mapped_ptr))
2477 return;
2478
2479 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2480 push_set->va += bo_offset;
2481
2482 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2483 radv_descriptor_set_to_handle(push_set),
2484 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2485
2486 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2487 }
2488
2489 void radv_CmdPushDescriptorSetKHR(
2490 VkCommandBuffer commandBuffer,
2491 VkPipelineBindPoint pipelineBindPoint,
2492 VkPipelineLayout _layout,
2493 uint32_t set,
2494 uint32_t descriptorWriteCount,
2495 const VkWriteDescriptorSet* pDescriptorWrites)
2496 {
2497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2498 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2499 struct radv_descriptor_state *descriptors_state =
2500 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2501 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2502
2503 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2504
2505 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2506 layout->set[set].layout,
2507 pipelineBindPoint))
2508 return;
2509
2510 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2511 radv_descriptor_set_to_handle(push_set),
2512 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2513
2514 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2515 descriptors_state->push_dirty = true;
2516 }
2517
2518 void radv_CmdPushDescriptorSetWithTemplateKHR(
2519 VkCommandBuffer commandBuffer,
2520 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2521 VkPipelineLayout _layout,
2522 uint32_t set,
2523 const void* pData)
2524 {
2525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2526 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2527 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2528 struct radv_descriptor_state *descriptors_state =
2529 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2530 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2531
2532 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2533
2534 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2535 layout->set[set].layout,
2536 templ->bind_point))
2537 return;
2538
2539 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2540 descriptorUpdateTemplate, pData);
2541
2542 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2543 descriptors_state->push_dirty = true;
2544 }
2545
2546 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2547 VkPipelineLayout layout,
2548 VkShaderStageFlags stageFlags,
2549 uint32_t offset,
2550 uint32_t size,
2551 const void* pValues)
2552 {
2553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2554 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2555 cmd_buffer->push_constant_stages |= stageFlags;
2556 }
2557
2558 VkResult radv_EndCommandBuffer(
2559 VkCommandBuffer commandBuffer)
2560 {
2561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2562
2563 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2564 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2565 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2566 si_emit_cache_flush(cmd_buffer);
2567 }
2568
2569 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2570
2571 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2572 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2573
2574 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2575
2576 return cmd_buffer->record_result;
2577 }
2578
2579 static void
2580 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2581 {
2582 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2583
2584 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2585 return;
2586
2587 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2588
2589 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2590 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2591
2592 cmd_buffer->compute_scratch_size_needed =
2593 MAX2(cmd_buffer->compute_scratch_size_needed,
2594 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2595
2596 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2597 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2598
2599 if (unlikely(cmd_buffer->device->trace_bo))
2600 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2601 }
2602
2603 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2604 VkPipelineBindPoint bind_point)
2605 {
2606 struct radv_descriptor_state *descriptors_state =
2607 radv_get_descriptors_state(cmd_buffer, bind_point);
2608
2609 descriptors_state->dirty |= descriptors_state->valid;
2610 }
2611
2612 void radv_CmdBindPipeline(
2613 VkCommandBuffer commandBuffer,
2614 VkPipelineBindPoint pipelineBindPoint,
2615 VkPipeline _pipeline)
2616 {
2617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2618 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2619
2620 switch (pipelineBindPoint) {
2621 case VK_PIPELINE_BIND_POINT_COMPUTE:
2622 if (cmd_buffer->state.compute_pipeline == pipeline)
2623 return;
2624 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2625
2626 cmd_buffer->state.compute_pipeline = pipeline;
2627 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2628 break;
2629 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2630 if (cmd_buffer->state.pipeline == pipeline)
2631 return;
2632 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2633
2634 cmd_buffer->state.pipeline = pipeline;
2635 if (!pipeline)
2636 break;
2637
2638 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2639 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2640
2641 /* the new vertex shader might not have the same user regs */
2642 cmd_buffer->state.last_first_instance = -1;
2643 cmd_buffer->state.last_vertex_offset = -1;
2644
2645 /* Prefetch all pipeline shaders at first draw time. */
2646 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2647
2648 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2649
2650 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2651 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2652 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2653 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2654
2655 if (radv_pipeline_has_tess(pipeline))
2656 cmd_buffer->tess_rings_needed = true;
2657
2658 if (radv_pipeline_has_gs(pipeline)) {
2659 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2660 AC_UD_SCRATCH_RING_OFFSETS);
2661 if (cmd_buffer->ring_offsets_idx == -1)
2662 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2663 else if (loc->sgpr_idx != -1)
2664 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2665 }
2666 break;
2667 default:
2668 assert(!"invalid bind point");
2669 break;
2670 }
2671 }
2672
2673 void radv_CmdSetViewport(
2674 VkCommandBuffer commandBuffer,
2675 uint32_t firstViewport,
2676 uint32_t viewportCount,
2677 const VkViewport* pViewports)
2678 {
2679 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2680 struct radv_cmd_state *state = &cmd_buffer->state;
2681 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2682
2683 assert(firstViewport < MAX_VIEWPORTS);
2684 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2685
2686 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2687 viewportCount * sizeof(*pViewports));
2688
2689 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2690 }
2691
2692 void radv_CmdSetScissor(
2693 VkCommandBuffer commandBuffer,
2694 uint32_t firstScissor,
2695 uint32_t scissorCount,
2696 const VkRect2D* pScissors)
2697 {
2698 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2699 struct radv_cmd_state *state = &cmd_buffer->state;
2700 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2701
2702 assert(firstScissor < MAX_SCISSORS);
2703 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2704
2705 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2706 scissorCount * sizeof(*pScissors));
2707
2708 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2709 }
2710
2711 void radv_CmdSetLineWidth(
2712 VkCommandBuffer commandBuffer,
2713 float lineWidth)
2714 {
2715 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2716 cmd_buffer->state.dynamic.line_width = lineWidth;
2717 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2718 }
2719
2720 void radv_CmdSetDepthBias(
2721 VkCommandBuffer commandBuffer,
2722 float depthBiasConstantFactor,
2723 float depthBiasClamp,
2724 float depthBiasSlopeFactor)
2725 {
2726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2727
2728 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2729 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2730 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2731
2732 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2733 }
2734
2735 void radv_CmdSetBlendConstants(
2736 VkCommandBuffer commandBuffer,
2737 const float blendConstants[4])
2738 {
2739 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2740
2741 memcpy(cmd_buffer->state.dynamic.blend_constants,
2742 blendConstants, sizeof(float) * 4);
2743
2744 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2745 }
2746
2747 void radv_CmdSetDepthBounds(
2748 VkCommandBuffer commandBuffer,
2749 float minDepthBounds,
2750 float maxDepthBounds)
2751 {
2752 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2753
2754 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2755 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2756
2757 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2758 }
2759
2760 void radv_CmdSetStencilCompareMask(
2761 VkCommandBuffer commandBuffer,
2762 VkStencilFaceFlags faceMask,
2763 uint32_t compareMask)
2764 {
2765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2766
2767 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2768 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2769 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2770 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2771
2772 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2773 }
2774
2775 void radv_CmdSetStencilWriteMask(
2776 VkCommandBuffer commandBuffer,
2777 VkStencilFaceFlags faceMask,
2778 uint32_t writeMask)
2779 {
2780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2781
2782 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2783 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2784 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2785 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2786
2787 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2788 }
2789
2790 void radv_CmdSetStencilReference(
2791 VkCommandBuffer commandBuffer,
2792 VkStencilFaceFlags faceMask,
2793 uint32_t reference)
2794 {
2795 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2796
2797 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2798 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2799 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2800 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2801
2802 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2803 }
2804
2805 void radv_CmdSetDiscardRectangleEXT(
2806 VkCommandBuffer commandBuffer,
2807 uint32_t firstDiscardRectangle,
2808 uint32_t discardRectangleCount,
2809 const VkRect2D* pDiscardRectangles)
2810 {
2811 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2812 struct radv_cmd_state *state = &cmd_buffer->state;
2813 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2814
2815 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2816 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2817
2818 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2819 pDiscardRectangles, discardRectangleCount);
2820
2821 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2822 }
2823
2824 void radv_CmdExecuteCommands(
2825 VkCommandBuffer commandBuffer,
2826 uint32_t commandBufferCount,
2827 const VkCommandBuffer* pCmdBuffers)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2830
2831 assert(commandBufferCount > 0);
2832
2833 /* Emit pending flushes on primary prior to executing secondary */
2834 si_emit_cache_flush(primary);
2835
2836 for (uint32_t i = 0; i < commandBufferCount; i++) {
2837 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2838
2839 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2840 secondary->scratch_size_needed);
2841 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2842 secondary->compute_scratch_size_needed);
2843
2844 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2845 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2846 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2847 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2848 if (secondary->tess_rings_needed)
2849 primary->tess_rings_needed = true;
2850 if (secondary->sample_positions_needed)
2851 primary->sample_positions_needed = true;
2852
2853 if (secondary->ring_offsets_idx != -1) {
2854 if (primary->ring_offsets_idx == -1)
2855 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2856 else
2857 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2858 }
2859 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2860
2861
2862 /* When the secondary command buffer is compute only we don't
2863 * need to re-emit the current graphics pipeline.
2864 */
2865 if (secondary->state.emitted_pipeline) {
2866 primary->state.emitted_pipeline =
2867 secondary->state.emitted_pipeline;
2868 }
2869
2870 /* When the secondary command buffer is graphics only we don't
2871 * need to re-emit the current compute pipeline.
2872 */
2873 if (secondary->state.emitted_compute_pipeline) {
2874 primary->state.emitted_compute_pipeline =
2875 secondary->state.emitted_compute_pipeline;
2876 }
2877
2878 /* Only re-emit the draw packets when needed. */
2879 if (secondary->state.last_primitive_reset_en != -1) {
2880 primary->state.last_primitive_reset_en =
2881 secondary->state.last_primitive_reset_en;
2882 }
2883
2884 if (secondary->state.last_primitive_reset_index) {
2885 primary->state.last_primitive_reset_index =
2886 secondary->state.last_primitive_reset_index;
2887 }
2888
2889 if (secondary->state.last_ia_multi_vgt_param) {
2890 primary->state.last_ia_multi_vgt_param =
2891 secondary->state.last_ia_multi_vgt_param;
2892 }
2893
2894 primary->state.last_first_instance = secondary->state.last_first_instance;
2895 primary->state.last_num_instances = secondary->state.last_num_instances;
2896 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2897
2898 if (secondary->state.last_index_type != -1) {
2899 primary->state.last_index_type =
2900 secondary->state.last_index_type;
2901 }
2902 }
2903
2904 /* After executing commands from secondary buffers we have to dirty
2905 * some states.
2906 */
2907 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2908 RADV_CMD_DIRTY_INDEX_BUFFER |
2909 RADV_CMD_DIRTY_DYNAMIC_ALL;
2910 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2911 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2912 }
2913
2914 VkResult radv_CreateCommandPool(
2915 VkDevice _device,
2916 const VkCommandPoolCreateInfo* pCreateInfo,
2917 const VkAllocationCallbacks* pAllocator,
2918 VkCommandPool* pCmdPool)
2919 {
2920 RADV_FROM_HANDLE(radv_device, device, _device);
2921 struct radv_cmd_pool *pool;
2922
2923 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2924 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2925 if (pool == NULL)
2926 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2927
2928 if (pAllocator)
2929 pool->alloc = *pAllocator;
2930 else
2931 pool->alloc = device->alloc;
2932
2933 list_inithead(&pool->cmd_buffers);
2934 list_inithead(&pool->free_cmd_buffers);
2935
2936 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2937
2938 *pCmdPool = radv_cmd_pool_to_handle(pool);
2939
2940 return VK_SUCCESS;
2941
2942 }
2943
2944 void radv_DestroyCommandPool(
2945 VkDevice _device,
2946 VkCommandPool commandPool,
2947 const VkAllocationCallbacks* pAllocator)
2948 {
2949 RADV_FROM_HANDLE(radv_device, device, _device);
2950 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2951
2952 if (!pool)
2953 return;
2954
2955 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2956 &pool->cmd_buffers, pool_link) {
2957 radv_cmd_buffer_destroy(cmd_buffer);
2958 }
2959
2960 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2961 &pool->free_cmd_buffers, pool_link) {
2962 radv_cmd_buffer_destroy(cmd_buffer);
2963 }
2964
2965 vk_free2(&device->alloc, pAllocator, pool);
2966 }
2967
2968 VkResult radv_ResetCommandPool(
2969 VkDevice device,
2970 VkCommandPool commandPool,
2971 VkCommandPoolResetFlags flags)
2972 {
2973 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2974 VkResult result;
2975
2976 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2977 &pool->cmd_buffers, pool_link) {
2978 result = radv_reset_cmd_buffer(cmd_buffer);
2979 if (result != VK_SUCCESS)
2980 return result;
2981 }
2982
2983 return VK_SUCCESS;
2984 }
2985
2986 void radv_TrimCommandPool(
2987 VkDevice device,
2988 VkCommandPool commandPool,
2989 VkCommandPoolTrimFlagsKHR flags)
2990 {
2991 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2992
2993 if (!pool)
2994 return;
2995
2996 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2997 &pool->free_cmd_buffers, pool_link) {
2998 radv_cmd_buffer_destroy(cmd_buffer);
2999 }
3000 }
3001
3002 void radv_CmdBeginRenderPass(
3003 VkCommandBuffer commandBuffer,
3004 const VkRenderPassBeginInfo* pRenderPassBegin,
3005 VkSubpassContents contents)
3006 {
3007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3008 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3009 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3010
3011 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3012 cmd_buffer->cs, 2048);
3013 MAYBE_UNUSED VkResult result;
3014
3015 cmd_buffer->state.framebuffer = framebuffer;
3016 cmd_buffer->state.pass = pass;
3017 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3018
3019 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3020 if (result != VK_SUCCESS)
3021 return;
3022
3023 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3024 assert(cmd_buffer->cs->cdw <= cdw_max);
3025
3026 radv_cmd_buffer_clear_subpass(cmd_buffer);
3027 }
3028
3029 void radv_CmdNextSubpass(
3030 VkCommandBuffer commandBuffer,
3031 VkSubpassContents contents)
3032 {
3033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3034
3035 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3036
3037 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3038 2048);
3039
3040 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3041 radv_cmd_buffer_clear_subpass(cmd_buffer);
3042 }
3043
3044 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3045 {
3046 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3047 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3048 if (!pipeline->shaders[stage])
3049 continue;
3050 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3051 if (loc->sgpr_idx == -1)
3052 continue;
3053 uint32_t base_reg = pipeline->user_data_0[stage];
3054 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3055
3056 }
3057 if (pipeline->gs_copy_shader) {
3058 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3059 if (loc->sgpr_idx != -1) {
3060 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3061 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3062 }
3063 }
3064 }
3065
3066 static void
3067 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3068 uint32_t vertex_count)
3069 {
3070 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3071 radeon_emit(cmd_buffer->cs, vertex_count);
3072 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3073 S_0287F0_USE_OPAQUE(0));
3074 }
3075
3076 static void
3077 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3078 uint64_t index_va,
3079 uint32_t index_count)
3080 {
3081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3082 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3083 radeon_emit(cmd_buffer->cs, index_va);
3084 radeon_emit(cmd_buffer->cs, index_va >> 32);
3085 radeon_emit(cmd_buffer->cs, index_count);
3086 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3087 }
3088
3089 static void
3090 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3091 bool indexed,
3092 uint32_t draw_count,
3093 uint64_t count_va,
3094 uint32_t stride)
3095 {
3096 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3097 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3098 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3099 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3100 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3101 assert(base_reg);
3102
3103 /* just reset draw state for vertex data */
3104 cmd_buffer->state.last_first_instance = -1;
3105 cmd_buffer->state.last_num_instances = -1;
3106 cmd_buffer->state.last_vertex_offset = -1;
3107
3108 if (draw_count == 1 && !count_va && !draw_id_enable) {
3109 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3110 PKT3_DRAW_INDIRECT, 3, false));
3111 radeon_emit(cs, 0);
3112 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3113 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3114 radeon_emit(cs, di_src_sel);
3115 } else {
3116 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3117 PKT3_DRAW_INDIRECT_MULTI,
3118 8, false));
3119 radeon_emit(cs, 0);
3120 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3121 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3122 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3123 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3124 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3125 radeon_emit(cs, draw_count); /* count */
3126 radeon_emit(cs, count_va); /* count_addr */
3127 radeon_emit(cs, count_va >> 32);
3128 radeon_emit(cs, stride); /* stride */
3129 radeon_emit(cs, di_src_sel);
3130 }
3131 }
3132
3133 struct radv_draw_info {
3134 /**
3135 * Number of vertices.
3136 */
3137 uint32_t count;
3138
3139 /**
3140 * Index of the first vertex.
3141 */
3142 int32_t vertex_offset;
3143
3144 /**
3145 * First instance id.
3146 */
3147 uint32_t first_instance;
3148
3149 /**
3150 * Number of instances.
3151 */
3152 uint32_t instance_count;
3153
3154 /**
3155 * First index (indexed draws only).
3156 */
3157 uint32_t first_index;
3158
3159 /**
3160 * Whether it's an indexed draw.
3161 */
3162 bool indexed;
3163
3164 /**
3165 * Indirect draw parameters resource.
3166 */
3167 struct radv_buffer *indirect;
3168 uint64_t indirect_offset;
3169 uint32_t stride;
3170
3171 /**
3172 * Draw count parameters resource.
3173 */
3174 struct radv_buffer *count_buffer;
3175 uint64_t count_buffer_offset;
3176 };
3177
3178 static void
3179 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3180 const struct radv_draw_info *info)
3181 {
3182 struct radv_cmd_state *state = &cmd_buffer->state;
3183 struct radeon_winsys *ws = cmd_buffer->device->ws;
3184 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3185
3186 if (info->indirect) {
3187 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3188 uint64_t count_va = 0;
3189
3190 va += info->indirect->offset + info->indirect_offset;
3191
3192 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3193
3194 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3195 radeon_emit(cs, 1);
3196 radeon_emit(cs, va);
3197 radeon_emit(cs, va >> 32);
3198
3199 if (info->count_buffer) {
3200 count_va = radv_buffer_get_va(info->count_buffer->bo);
3201 count_va += info->count_buffer->offset +
3202 info->count_buffer_offset;
3203
3204 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3205 }
3206
3207 if (!state->subpass->view_mask) {
3208 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3209 info->indexed,
3210 info->count,
3211 count_va,
3212 info->stride);
3213 } else {
3214 unsigned i;
3215 for_each_bit(i, state->subpass->view_mask) {
3216 radv_emit_view_index(cmd_buffer, i);
3217
3218 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3219 info->indexed,
3220 info->count,
3221 count_va,
3222 info->stride);
3223 }
3224 }
3225 } else {
3226 assert(state->pipeline->graphics.vtx_base_sgpr);
3227
3228 if (info->vertex_offset != state->last_vertex_offset ||
3229 info->first_instance != state->last_first_instance) {
3230 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3231 state->pipeline->graphics.vtx_emit_num);
3232
3233 radeon_emit(cs, info->vertex_offset);
3234 radeon_emit(cs, info->first_instance);
3235 if (state->pipeline->graphics.vtx_emit_num == 3)
3236 radeon_emit(cs, 0);
3237 state->last_first_instance = info->first_instance;
3238 state->last_vertex_offset = info->vertex_offset;
3239 }
3240
3241 if (state->last_num_instances != info->instance_count) {
3242 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3243 radeon_emit(cs, info->instance_count);
3244 state->last_num_instances = info->instance_count;
3245 }
3246
3247 if (info->indexed) {
3248 int index_size = state->index_type ? 4 : 2;
3249 uint64_t index_va;
3250
3251 index_va = state->index_va;
3252 index_va += info->first_index * index_size;
3253
3254 if (!state->subpass->view_mask) {
3255 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3256 index_va,
3257 info->count);
3258 } else {
3259 unsigned i;
3260 for_each_bit(i, state->subpass->view_mask) {
3261 radv_emit_view_index(cmd_buffer, i);
3262
3263 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3264 index_va,
3265 info->count);
3266 }
3267 }
3268 } else {
3269 if (!state->subpass->view_mask) {
3270 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3271 } else {
3272 unsigned i;
3273 for_each_bit(i, state->subpass->view_mask) {
3274 radv_emit_view_index(cmd_buffer, i);
3275
3276 radv_cs_emit_draw_packet(cmd_buffer,
3277 info->count);
3278 }
3279 }
3280 }
3281 }
3282 }
3283
3284 /*
3285 * Vega and raven have a bug which triggers if there are multiple context
3286 * register contexts active at the same time with different scissor values.
3287 *
3288 * There are two possible workarounds:
3289 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3290 * there is only ever 1 active set of scissor values at the same time.
3291 *
3292 * 2) Whenever the hardware switches contexts we have to set the scissor
3293 * registers again even if it is a noop. That way the new context gets
3294 * the correct scissor values.
3295 *
3296 * This implements option 2. radv_need_late_scissor_emission needs to
3297 * return true on affected HW if radv_emit_all_graphics_states sets
3298 * any context registers.
3299 */
3300 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3301 bool indexed_draw)
3302 {
3303 struct radv_cmd_state *state = &cmd_buffer->state;
3304
3305 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3306 return false;
3307
3308 /* Assume all state changes except these two can imply context rolls. */
3309 if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3310 RADV_CMD_DIRTY_VERTEX_BUFFER |
3311 RADV_CMD_DIRTY_PIPELINE))
3312 return true;
3313
3314 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3315 return true;
3316
3317 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3318 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3319 return true;
3320
3321 return false;
3322 }
3323
3324 static void
3325 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3326 const struct radv_draw_info *info)
3327 {
3328 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3329
3330 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3331 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3332 radv_emit_rbplus_state(cmd_buffer);
3333
3334 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3335 radv_emit_graphics_pipeline(cmd_buffer);
3336
3337 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3338 radv_emit_framebuffer_state(cmd_buffer);
3339
3340 if (info->indexed) {
3341 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3342 radv_emit_index_buffer(cmd_buffer);
3343 } else {
3344 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3345 * so the state must be re-emitted before the next indexed
3346 * draw.
3347 */
3348 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3349 cmd_buffer->state.last_index_type = -1;
3350 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3351 }
3352 }
3353
3354 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3355
3356 radv_emit_draw_registers(cmd_buffer, info->indexed,
3357 info->instance_count > 1, info->indirect,
3358 info->indirect ? 0 : info->count);
3359
3360 if (late_scissor_emission)
3361 radv_emit_scissor(cmd_buffer);
3362 }
3363
3364 static void
3365 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3366 const struct radv_draw_info *info)
3367 {
3368 bool has_prefetch =
3369 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3370 bool pipeline_is_dirty =
3371 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3372 cmd_buffer->state.pipeline &&
3373 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3374
3375 MAYBE_UNUSED unsigned cdw_max =
3376 radeon_check_space(cmd_buffer->device->ws,
3377 cmd_buffer->cs, 4096);
3378
3379 /* Use optimal packet order based on whether we need to sync the
3380 * pipeline.
3381 */
3382 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3383 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3384 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3385 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3386 /* If we have to wait for idle, set all states first, so that
3387 * all SET packets are processed in parallel with previous draw
3388 * calls. Then upload descriptors, set shader pointers, and
3389 * draw, and prefetch at the end. This ensures that the time
3390 * the CUs are idle is very short. (there are only SET_SH
3391 * packets between the wait and the draw)
3392 */
3393 radv_emit_all_graphics_states(cmd_buffer, info);
3394 si_emit_cache_flush(cmd_buffer);
3395 /* <-- CUs are idle here --> */
3396
3397 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3398
3399 radv_emit_draw_packets(cmd_buffer, info);
3400 /* <-- CUs are busy here --> */
3401
3402 /* Start prefetches after the draw has been started. Both will
3403 * run in parallel, but starting the draw first is more
3404 * important.
3405 */
3406 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3407 radv_emit_prefetch_L2(cmd_buffer,
3408 cmd_buffer->state.pipeline, false);
3409 }
3410 } else {
3411 /* If we don't wait for idle, start prefetches first, then set
3412 * states, and draw at the end.
3413 */
3414 si_emit_cache_flush(cmd_buffer);
3415
3416 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3417 /* Only prefetch the vertex shader and VBO descriptors
3418 * in order to start the draw as soon as possible.
3419 */
3420 radv_emit_prefetch_L2(cmd_buffer,
3421 cmd_buffer->state.pipeline, true);
3422 }
3423
3424 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3425
3426 radv_emit_all_graphics_states(cmd_buffer, info);
3427 radv_emit_draw_packets(cmd_buffer, info);
3428
3429 /* Prefetch the remaining shaders after the draw has been
3430 * started.
3431 */
3432 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3433 radv_emit_prefetch_L2(cmd_buffer,
3434 cmd_buffer->state.pipeline, false);
3435 }
3436 }
3437
3438 assert(cmd_buffer->cs->cdw <= cdw_max);
3439 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3440 }
3441
3442 void radv_CmdDraw(
3443 VkCommandBuffer commandBuffer,
3444 uint32_t vertexCount,
3445 uint32_t instanceCount,
3446 uint32_t firstVertex,
3447 uint32_t firstInstance)
3448 {
3449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3450 struct radv_draw_info info = {};
3451
3452 info.count = vertexCount;
3453 info.instance_count = instanceCount;
3454 info.first_instance = firstInstance;
3455 info.vertex_offset = firstVertex;
3456
3457 radv_draw(cmd_buffer, &info);
3458 }
3459
3460 void radv_CmdDrawIndexed(
3461 VkCommandBuffer commandBuffer,
3462 uint32_t indexCount,
3463 uint32_t instanceCount,
3464 uint32_t firstIndex,
3465 int32_t vertexOffset,
3466 uint32_t firstInstance)
3467 {
3468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3469 struct radv_draw_info info = {};
3470
3471 info.indexed = true;
3472 info.count = indexCount;
3473 info.instance_count = instanceCount;
3474 info.first_index = firstIndex;
3475 info.vertex_offset = vertexOffset;
3476 info.first_instance = firstInstance;
3477
3478 radv_draw(cmd_buffer, &info);
3479 }
3480
3481 void radv_CmdDrawIndirect(
3482 VkCommandBuffer commandBuffer,
3483 VkBuffer _buffer,
3484 VkDeviceSize offset,
3485 uint32_t drawCount,
3486 uint32_t stride)
3487 {
3488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3489 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3490 struct radv_draw_info info = {};
3491
3492 info.count = drawCount;
3493 info.indirect = buffer;
3494 info.indirect_offset = offset;
3495 info.stride = stride;
3496
3497 radv_draw(cmd_buffer, &info);
3498 }
3499
3500 void radv_CmdDrawIndexedIndirect(
3501 VkCommandBuffer commandBuffer,
3502 VkBuffer _buffer,
3503 VkDeviceSize offset,
3504 uint32_t drawCount,
3505 uint32_t stride)
3506 {
3507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3508 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3509 struct radv_draw_info info = {};
3510
3511 info.indexed = true;
3512 info.count = drawCount;
3513 info.indirect = buffer;
3514 info.indirect_offset = offset;
3515 info.stride = stride;
3516
3517 radv_draw(cmd_buffer, &info);
3518 }
3519
3520 void radv_CmdDrawIndirectCountAMD(
3521 VkCommandBuffer commandBuffer,
3522 VkBuffer _buffer,
3523 VkDeviceSize offset,
3524 VkBuffer _countBuffer,
3525 VkDeviceSize countBufferOffset,
3526 uint32_t maxDrawCount,
3527 uint32_t stride)
3528 {
3529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3530 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3531 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3532 struct radv_draw_info info = {};
3533
3534 info.count = maxDrawCount;
3535 info.indirect = buffer;
3536 info.indirect_offset = offset;
3537 info.count_buffer = count_buffer;
3538 info.count_buffer_offset = countBufferOffset;
3539 info.stride = stride;
3540
3541 radv_draw(cmd_buffer, &info);
3542 }
3543
3544 void radv_CmdDrawIndexedIndirectCountAMD(
3545 VkCommandBuffer commandBuffer,
3546 VkBuffer _buffer,
3547 VkDeviceSize offset,
3548 VkBuffer _countBuffer,
3549 VkDeviceSize countBufferOffset,
3550 uint32_t maxDrawCount,
3551 uint32_t stride)
3552 {
3553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3554 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3555 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3556 struct radv_draw_info info = {};
3557
3558 info.indexed = true;
3559 info.count = maxDrawCount;
3560 info.indirect = buffer;
3561 info.indirect_offset = offset;
3562 info.count_buffer = count_buffer;
3563 info.count_buffer_offset = countBufferOffset;
3564 info.stride = stride;
3565
3566 radv_draw(cmd_buffer, &info);
3567 }
3568
3569 void radv_CmdDrawIndirectCountKHR(
3570 VkCommandBuffer commandBuffer,
3571 VkBuffer _buffer,
3572 VkDeviceSize offset,
3573 VkBuffer _countBuffer,
3574 VkDeviceSize countBufferOffset,
3575 uint32_t maxDrawCount,
3576 uint32_t stride)
3577 {
3578 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3579 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3580 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3581 struct radv_draw_info info = {};
3582
3583 info.count = maxDrawCount;
3584 info.indirect = buffer;
3585 info.indirect_offset = offset;
3586 info.count_buffer = count_buffer;
3587 info.count_buffer_offset = countBufferOffset;
3588 info.stride = stride;
3589
3590 radv_draw(cmd_buffer, &info);
3591 }
3592
3593 void radv_CmdDrawIndexedIndirectCountKHR(
3594 VkCommandBuffer commandBuffer,
3595 VkBuffer _buffer,
3596 VkDeviceSize offset,
3597 VkBuffer _countBuffer,
3598 VkDeviceSize countBufferOffset,
3599 uint32_t maxDrawCount,
3600 uint32_t stride)
3601 {
3602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3603 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3604 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3605 struct radv_draw_info info = {};
3606
3607 info.indexed = true;
3608 info.count = maxDrawCount;
3609 info.indirect = buffer;
3610 info.indirect_offset = offset;
3611 info.count_buffer = count_buffer;
3612 info.count_buffer_offset = countBufferOffset;
3613 info.stride = stride;
3614
3615 radv_draw(cmd_buffer, &info);
3616 }
3617
3618 struct radv_dispatch_info {
3619 /**
3620 * Determine the layout of the grid (in block units) to be used.
3621 */
3622 uint32_t blocks[3];
3623
3624 /**
3625 * A starting offset for the grid. If unaligned is set, the offset
3626 * must still be aligned.
3627 */
3628 uint32_t offsets[3];
3629 /**
3630 * Whether it's an unaligned compute dispatch.
3631 */
3632 bool unaligned;
3633
3634 /**
3635 * Indirect compute parameters resource.
3636 */
3637 struct radv_buffer *indirect;
3638 uint64_t indirect_offset;
3639 };
3640
3641 static void
3642 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3643 const struct radv_dispatch_info *info)
3644 {
3645 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3646 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3647 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3648 struct radeon_winsys *ws = cmd_buffer->device->ws;
3649 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3650 struct radv_userdata_info *loc;
3651
3652 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3653 AC_UD_CS_GRID_SIZE);
3654
3655 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3656
3657 if (info->indirect) {
3658 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3659
3660 va += info->indirect->offset + info->indirect_offset;
3661
3662 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3663
3664 if (loc->sgpr_idx != -1) {
3665 for (unsigned i = 0; i < 3; ++i) {
3666 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3667 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3668 COPY_DATA_DST_SEL(COPY_DATA_REG));
3669 radeon_emit(cs, (va + 4 * i));
3670 radeon_emit(cs, (va + 4 * i) >> 32);
3671 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3672 + loc->sgpr_idx * 4) >> 2) + i);
3673 radeon_emit(cs, 0);
3674 }
3675 }
3676
3677 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3678 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3679 PKT3_SHADER_TYPE_S(1));
3680 radeon_emit(cs, va);
3681 radeon_emit(cs, va >> 32);
3682 radeon_emit(cs, dispatch_initiator);
3683 } else {
3684 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3685 PKT3_SHADER_TYPE_S(1));
3686 radeon_emit(cs, 1);
3687 radeon_emit(cs, va);
3688 radeon_emit(cs, va >> 32);
3689
3690 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3691 PKT3_SHADER_TYPE_S(1));
3692 radeon_emit(cs, 0);
3693 radeon_emit(cs, dispatch_initiator);
3694 }
3695 } else {
3696 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3697 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3698
3699 if (info->unaligned) {
3700 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3701 unsigned remainder[3];
3702
3703 /* If aligned, these should be an entire block size,
3704 * not 0.
3705 */
3706 remainder[0] = blocks[0] + cs_block_size[0] -
3707 align_u32_npot(blocks[0], cs_block_size[0]);
3708 remainder[1] = blocks[1] + cs_block_size[1] -
3709 align_u32_npot(blocks[1], cs_block_size[1]);
3710 remainder[2] = blocks[2] + cs_block_size[2] -
3711 align_u32_npot(blocks[2], cs_block_size[2]);
3712
3713 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3714 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3715 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3716
3717 for(unsigned i = 0; i < 3; ++i) {
3718 assert(offsets[i] % cs_block_size[i] == 0);
3719 offsets[i] /= cs_block_size[i];
3720 }
3721
3722 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3723 radeon_emit(cs,
3724 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3725 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3726 radeon_emit(cs,
3727 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3728 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3729 radeon_emit(cs,
3730 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3731 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3732
3733 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3734 }
3735
3736 if (loc->sgpr_idx != -1) {
3737 assert(!loc->indirect);
3738 assert(loc->num_sgprs == 3);
3739
3740 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3741 loc->sgpr_idx * 4, 3);
3742 radeon_emit(cs, blocks[0]);
3743 radeon_emit(cs, blocks[1]);
3744 radeon_emit(cs, blocks[2]);
3745 }
3746
3747 if (offsets[0] || offsets[1] || offsets[2]) {
3748 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3749 radeon_emit(cs, offsets[0]);
3750 radeon_emit(cs, offsets[1]);
3751 radeon_emit(cs, offsets[2]);
3752
3753 /* The blocks in the packet are not counts but end values. */
3754 for (unsigned i = 0; i < 3; ++i)
3755 blocks[i] += offsets[i];
3756 } else {
3757 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3758 }
3759
3760 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3761 PKT3_SHADER_TYPE_S(1));
3762 radeon_emit(cs, blocks[0]);
3763 radeon_emit(cs, blocks[1]);
3764 radeon_emit(cs, blocks[2]);
3765 radeon_emit(cs, dispatch_initiator);
3766 }
3767
3768 assert(cmd_buffer->cs->cdw <= cdw_max);
3769 }
3770
3771 static void
3772 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3773 {
3774 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3775 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3776 }
3777
3778 static void
3779 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3780 const struct radv_dispatch_info *info)
3781 {
3782 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3783 bool has_prefetch =
3784 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3785 bool pipeline_is_dirty = pipeline &&
3786 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3787
3788 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3789 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3790 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3791 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3792 /* If we have to wait for idle, set all states first, so that
3793 * all SET packets are processed in parallel with previous draw
3794 * calls. Then upload descriptors, set shader pointers, and
3795 * dispatch, and prefetch at the end. This ensures that the
3796 * time the CUs are idle is very short. (there are only SET_SH
3797 * packets between the wait and the draw)
3798 */
3799 radv_emit_compute_pipeline(cmd_buffer);
3800 si_emit_cache_flush(cmd_buffer);
3801 /* <-- CUs are idle here --> */
3802
3803 radv_upload_compute_shader_descriptors(cmd_buffer);
3804
3805 radv_emit_dispatch_packets(cmd_buffer, info);
3806 /* <-- CUs are busy here --> */
3807
3808 /* Start prefetches after the dispatch has been started. Both
3809 * will run in parallel, but starting the dispatch first is
3810 * more important.
3811 */
3812 if (has_prefetch && pipeline_is_dirty) {
3813 radv_emit_shader_prefetch(cmd_buffer,
3814 pipeline->shaders[MESA_SHADER_COMPUTE]);
3815 }
3816 } else {
3817 /* If we don't wait for idle, start prefetches first, then set
3818 * states, and dispatch at the end.
3819 */
3820 si_emit_cache_flush(cmd_buffer);
3821
3822 if (has_prefetch && pipeline_is_dirty) {
3823 radv_emit_shader_prefetch(cmd_buffer,
3824 pipeline->shaders[MESA_SHADER_COMPUTE]);
3825 }
3826
3827 radv_upload_compute_shader_descriptors(cmd_buffer);
3828
3829 radv_emit_compute_pipeline(cmd_buffer);
3830 radv_emit_dispatch_packets(cmd_buffer, info);
3831 }
3832
3833 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3834 }
3835
3836 void radv_CmdDispatchBase(
3837 VkCommandBuffer commandBuffer,
3838 uint32_t base_x,
3839 uint32_t base_y,
3840 uint32_t base_z,
3841 uint32_t x,
3842 uint32_t y,
3843 uint32_t z)
3844 {
3845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3846 struct radv_dispatch_info info = {};
3847
3848 info.blocks[0] = x;
3849 info.blocks[1] = y;
3850 info.blocks[2] = z;
3851
3852 info.offsets[0] = base_x;
3853 info.offsets[1] = base_y;
3854 info.offsets[2] = base_z;
3855 radv_dispatch(cmd_buffer, &info);
3856 }
3857
3858 void radv_CmdDispatch(
3859 VkCommandBuffer commandBuffer,
3860 uint32_t x,
3861 uint32_t y,
3862 uint32_t z)
3863 {
3864 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3865 }
3866
3867 void radv_CmdDispatchIndirect(
3868 VkCommandBuffer commandBuffer,
3869 VkBuffer _buffer,
3870 VkDeviceSize offset)
3871 {
3872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3873 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3874 struct radv_dispatch_info info = {};
3875
3876 info.indirect = buffer;
3877 info.indirect_offset = offset;
3878
3879 radv_dispatch(cmd_buffer, &info);
3880 }
3881
3882 void radv_unaligned_dispatch(
3883 struct radv_cmd_buffer *cmd_buffer,
3884 uint32_t x,
3885 uint32_t y,
3886 uint32_t z)
3887 {
3888 struct radv_dispatch_info info = {};
3889
3890 info.blocks[0] = x;
3891 info.blocks[1] = y;
3892 info.blocks[2] = z;
3893 info.unaligned = 1;
3894
3895 radv_dispatch(cmd_buffer, &info);
3896 }
3897
3898 void radv_CmdEndRenderPass(
3899 VkCommandBuffer commandBuffer)
3900 {
3901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3902
3903 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3904
3905 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3906
3907 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3908 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3909 radv_handle_subpass_image_transition(cmd_buffer,
3910 (VkAttachmentReference){i, layout});
3911 }
3912
3913 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3914
3915 cmd_buffer->state.pass = NULL;
3916 cmd_buffer->state.subpass = NULL;
3917 cmd_buffer->state.attachments = NULL;
3918 cmd_buffer->state.framebuffer = NULL;
3919 }
3920
3921 /*
3922 * For HTILE we have the following interesting clear words:
3923 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3924 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3925 * 0xfffffff0: Clear depth to 1.0
3926 * 0x00000000: Clear depth to 0.0
3927 */
3928 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3929 struct radv_image *image,
3930 const VkImageSubresourceRange *range,
3931 uint32_t clear_word)
3932 {
3933 assert(range->baseMipLevel == 0);
3934 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3935 unsigned layer_count = radv_get_layerCount(image, range);
3936 uint64_t size = image->surface.htile_slice_size * layer_count;
3937 uint64_t offset = image->offset + image->htile_offset +
3938 image->surface.htile_slice_size * range->baseArrayLayer;
3939 struct radv_cmd_state *state = &cmd_buffer->state;
3940
3941 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3942 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3943
3944 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3945 size, clear_word);
3946
3947 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3948
3949 /* Initialize the depth clear registers and update the ZRANGE_PRECISION
3950 * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
3951 * default). This is only needed whean clearing Z to 0.0f.
3952 */
3953 if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
3954 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3955 VkClearDepthStencilValue value = {};
3956
3957 if (vk_format_is_stencil(image->vk_format))
3958 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3959
3960 radv_set_depth_clear_regs(cmd_buffer, image, value, aspects);
3961 }
3962 }
3963
3964 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3965 struct radv_image *image,
3966 VkImageLayout src_layout,
3967 VkImageLayout dst_layout,
3968 unsigned src_queue_mask,
3969 unsigned dst_queue_mask,
3970 const VkImageSubresourceRange *range,
3971 VkImageAspectFlags pending_clears)
3972 {
3973 if (!radv_image_has_htile(image))
3974 return;
3975
3976 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3977 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3978 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3979 cmd_buffer->state.render_area.extent.width == image->info.width &&
3980 cmd_buffer->state.render_area.extent.height == image->info.height) {
3981 /* The clear will initialize htile. */
3982 return;
3983 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3984 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3985 /* TODO: merge with the clear if applicable */
3986 radv_initialize_htile(cmd_buffer, image, range, 0);
3987 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3988 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3989 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3990 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3991 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3992 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3993 VkImageSubresourceRange local_range = *range;
3994 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3995 local_range.baseMipLevel = 0;
3996 local_range.levelCount = 1;
3997
3998 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3999 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4000
4001 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4002
4003 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4004 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4005 }
4006 }
4007
4008 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4009 struct radv_image *image, uint32_t value)
4010 {
4011 struct radv_cmd_state *state = &cmd_buffer->state;
4012
4013 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4014 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4015
4016 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4017
4018 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4019 }
4020
4021 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4022 struct radv_image *image, uint32_t value)
4023 {
4024 struct radv_cmd_state *state = &cmd_buffer->state;
4025
4026 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4027 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4028
4029 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4030
4031 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4032 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4033 }
4034
4035 /**
4036 * Initialize DCC/FMASK/CMASK metadata for a color image.
4037 */
4038 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4039 struct radv_image *image,
4040 VkImageLayout src_layout,
4041 VkImageLayout dst_layout,
4042 unsigned src_queue_mask,
4043 unsigned dst_queue_mask)
4044 {
4045 if (radv_image_has_cmask(image)) {
4046 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4047
4048 /* TODO: clarify this. */
4049 if (radv_image_has_fmask(image)) {
4050 value = 0xccccccccu;
4051 }
4052
4053 radv_initialise_cmask(cmd_buffer, image, value);
4054 }
4055
4056 if (radv_image_has_dcc(image)) {
4057 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4058
4059 if (radv_layout_dcc_compressed(image, dst_layout,
4060 dst_queue_mask)) {
4061 value = 0x20202020u;
4062 }
4063
4064 radv_initialize_dcc(cmd_buffer, image, value);
4065 }
4066 }
4067
4068 /**
4069 * Handle color image transitions for DCC/FMASK/CMASK.
4070 */
4071 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4072 struct radv_image *image,
4073 VkImageLayout src_layout,
4074 VkImageLayout dst_layout,
4075 unsigned src_queue_mask,
4076 unsigned dst_queue_mask,
4077 const VkImageSubresourceRange *range)
4078 {
4079 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4080 radv_init_color_image_metadata(cmd_buffer, image,
4081 src_layout, dst_layout,
4082 src_queue_mask, dst_queue_mask);
4083 return;
4084 }
4085
4086 if (radv_image_has_dcc(image)) {
4087 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4088 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4089 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4090 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4091 radv_decompress_dcc(cmd_buffer, image, range);
4092 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4093 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4094 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4095 }
4096 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4097 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4098 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4099 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4100 }
4101 }
4102 }
4103
4104 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4105 struct radv_image *image,
4106 VkImageLayout src_layout,
4107 VkImageLayout dst_layout,
4108 uint32_t src_family,
4109 uint32_t dst_family,
4110 const VkImageSubresourceRange *range,
4111 VkImageAspectFlags pending_clears)
4112 {
4113 if (image->exclusive && src_family != dst_family) {
4114 /* This is an acquire or a release operation and there will be
4115 * a corresponding release/acquire. Do the transition in the
4116 * most flexible queue. */
4117
4118 assert(src_family == cmd_buffer->queue_family_index ||
4119 dst_family == cmd_buffer->queue_family_index);
4120
4121 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4122 return;
4123
4124 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4125 (src_family == RADV_QUEUE_GENERAL ||
4126 dst_family == RADV_QUEUE_GENERAL))
4127 return;
4128 }
4129
4130 unsigned src_queue_mask =
4131 radv_image_queue_family_mask(image, src_family,
4132 cmd_buffer->queue_family_index);
4133 unsigned dst_queue_mask =
4134 radv_image_queue_family_mask(image, dst_family,
4135 cmd_buffer->queue_family_index);
4136
4137 if (vk_format_is_depth(image->vk_format)) {
4138 radv_handle_depth_image_transition(cmd_buffer, image,
4139 src_layout, dst_layout,
4140 src_queue_mask, dst_queue_mask,
4141 range, pending_clears);
4142 } else {
4143 radv_handle_color_image_transition(cmd_buffer, image,
4144 src_layout, dst_layout,
4145 src_queue_mask, dst_queue_mask,
4146 range);
4147 }
4148 }
4149
4150 void radv_CmdPipelineBarrier(
4151 VkCommandBuffer commandBuffer,
4152 VkPipelineStageFlags srcStageMask,
4153 VkPipelineStageFlags destStageMask,
4154 VkBool32 byRegion,
4155 uint32_t memoryBarrierCount,
4156 const VkMemoryBarrier* pMemoryBarriers,
4157 uint32_t bufferMemoryBarrierCount,
4158 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4159 uint32_t imageMemoryBarrierCount,
4160 const VkImageMemoryBarrier* pImageMemoryBarriers)
4161 {
4162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4163 enum radv_cmd_flush_bits src_flush_bits = 0;
4164 enum radv_cmd_flush_bits dst_flush_bits = 0;
4165
4166 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4167 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4168 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4169 NULL);
4170 }
4171
4172 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4173 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4174 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4175 NULL);
4176 }
4177
4178 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4179 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4180 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4181 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4182 image);
4183 }
4184
4185 radv_stage_flush(cmd_buffer, srcStageMask);
4186 cmd_buffer->state.flush_bits |= src_flush_bits;
4187
4188 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4189 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4190 radv_handle_image_transition(cmd_buffer, image,
4191 pImageMemoryBarriers[i].oldLayout,
4192 pImageMemoryBarriers[i].newLayout,
4193 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4194 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4195 &pImageMemoryBarriers[i].subresourceRange,
4196 0);
4197 }
4198
4199 cmd_buffer->state.flush_bits |= dst_flush_bits;
4200 }
4201
4202
4203 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4204 struct radv_event *event,
4205 VkPipelineStageFlags stageMask,
4206 unsigned value)
4207 {
4208 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4209 uint64_t va = radv_buffer_get_va(event->bo);
4210
4211 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4212
4213 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4214
4215 /* TODO: this is overkill. Probably should figure something out from
4216 * the stage mask. */
4217
4218 si_cs_emit_write_event_eop(cs,
4219 cmd_buffer->state.predicating,
4220 cmd_buffer->device->physical_device->rad_info.chip_class,
4221 radv_cmd_buffer_uses_mec(cmd_buffer),
4222 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4223 1, va, 2, value);
4224
4225 assert(cmd_buffer->cs->cdw <= cdw_max);
4226 }
4227
4228 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4229 VkEvent _event,
4230 VkPipelineStageFlags stageMask)
4231 {
4232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4233 RADV_FROM_HANDLE(radv_event, event, _event);
4234
4235 write_event(cmd_buffer, event, stageMask, 1);
4236 }
4237
4238 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4239 VkEvent _event,
4240 VkPipelineStageFlags stageMask)
4241 {
4242 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4243 RADV_FROM_HANDLE(radv_event, event, _event);
4244
4245 write_event(cmd_buffer, event, stageMask, 0);
4246 }
4247
4248 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4249 uint32_t eventCount,
4250 const VkEvent* pEvents,
4251 VkPipelineStageFlags srcStageMask,
4252 VkPipelineStageFlags dstStageMask,
4253 uint32_t memoryBarrierCount,
4254 const VkMemoryBarrier* pMemoryBarriers,
4255 uint32_t bufferMemoryBarrierCount,
4256 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4257 uint32_t imageMemoryBarrierCount,
4258 const VkImageMemoryBarrier* pImageMemoryBarriers)
4259 {
4260 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4261 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4262
4263 for (unsigned i = 0; i < eventCount; ++i) {
4264 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4265 uint64_t va = radv_buffer_get_va(event->bo);
4266
4267 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4268
4269 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4270
4271 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4272 assert(cmd_buffer->cs->cdw <= cdw_max);
4273 }
4274
4275
4276 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4277 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4278
4279 radv_handle_image_transition(cmd_buffer, image,
4280 pImageMemoryBarriers[i].oldLayout,
4281 pImageMemoryBarriers[i].newLayout,
4282 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4283 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4284 &pImageMemoryBarriers[i].subresourceRange,
4285 0);
4286 }
4287
4288 /* TODO: figure out how to do memory barriers without waiting */
4289 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4290 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4291 RADV_CMD_FLAG_INV_VMEM_L1 |
4292 RADV_CMD_FLAG_INV_SMEM_L1;
4293 }
4294
4295
4296 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4297 uint32_t deviceMask)
4298 {
4299 /* No-op */
4300 }