2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
);
62 const struct radv_dynamic_state default_dynamic_state
= {
75 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
80 .stencil_compare_mask
= {
84 .stencil_write_mask
= {
88 .stencil_reference
= {
95 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
96 const struct radv_dynamic_state
*src
)
98 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
99 uint32_t copy_mask
= src
->mask
;
100 uint32_t dest_mask
= 0;
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
105 dest
->viewport
.count
= src
->viewport
.count
;
106 dest
->scissor
.count
= src
->scissor
.count
;
107 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
110 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
111 src
->viewport
.count
* sizeof(VkViewport
))) {
112 typed_memcpy(dest
->viewport
.viewports
,
113 src
->viewport
.viewports
,
114 src
->viewport
.count
);
115 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
119 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
120 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
121 src
->scissor
.count
* sizeof(VkRect2D
))) {
122 typed_memcpy(dest
->scissor
.scissors
,
123 src
->scissor
.scissors
, src
->scissor
.count
);
124 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
128 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
129 if (dest
->line_width
!= src
->line_width
) {
130 dest
->line_width
= src
->line_width
;
131 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
135 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
136 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
137 sizeof(src
->depth_bias
))) {
138 dest
->depth_bias
= src
->depth_bias
;
139 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
143 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
144 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
145 sizeof(src
->blend_constants
))) {
146 typed_memcpy(dest
->blend_constants
,
147 src
->blend_constants
, 4);
148 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
152 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
153 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
154 sizeof(src
->depth_bounds
))) {
155 dest
->depth_bounds
= src
->depth_bounds
;
156 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
160 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
161 if (memcmp(&dest
->stencil_compare_mask
,
162 &src
->stencil_compare_mask
,
163 sizeof(src
->stencil_compare_mask
))) {
164 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
165 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
169 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
170 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
171 sizeof(src
->stencil_write_mask
))) {
172 dest
->stencil_write_mask
= src
->stencil_write_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
178 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
179 sizeof(src
->stencil_reference
))) {
180 dest
->stencil_reference
= src
->stencil_reference
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
185 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
186 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
187 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
188 typed_memcpy(dest
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.count
);
191 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
195 cmd_buffer
->state
.dirty
|= dest_mask
;
199 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
200 struct radv_pipeline
*pipeline
)
202 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
203 struct radv_shader_info
*info
;
205 if (!pipeline
->streamout_shader
)
208 info
= &pipeline
->streamout_shader
->info
.info
;
209 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
210 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
212 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
217 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
218 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
221 enum ring_type
radv_queue_family_to_ring(int f
) {
223 case RADV_QUEUE_GENERAL
:
225 case RADV_QUEUE_COMPUTE
:
227 case RADV_QUEUE_TRANSFER
:
230 unreachable("Unknown queue family");
234 static VkResult
radv_create_cmd_buffer(
235 struct radv_device
* device
,
236 struct radv_cmd_pool
* pool
,
237 VkCommandBufferLevel level
,
238 VkCommandBuffer
* pCommandBuffer
)
240 struct radv_cmd_buffer
*cmd_buffer
;
242 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
244 if (cmd_buffer
== NULL
)
245 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
247 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
248 cmd_buffer
->device
= device
;
249 cmd_buffer
->pool
= pool
;
250 cmd_buffer
->level
= level
;
253 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
254 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
257 /* Init the pool_link so we can safely call list_del when we destroy
260 list_inithead(&cmd_buffer
->pool_link
);
261 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
264 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
266 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
267 if (!cmd_buffer
->cs
) {
268 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
269 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
272 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
274 list_inithead(&cmd_buffer
->upload
.list
);
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
282 list_del(&cmd_buffer
->pool_link
);
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
285 &cmd_buffer
->upload
.list
, list
) {
286 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
291 if (cmd_buffer
->upload
.upload_bo
)
292 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
293 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
295 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
296 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
298 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
305 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
308 &cmd_buffer
->upload
.list
, list
) {
309 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
314 cmd_buffer
->push_constant_stages
= 0;
315 cmd_buffer
->scratch_size_needed
= 0;
316 cmd_buffer
->compute_scratch_size_needed
= 0;
317 cmd_buffer
->esgs_ring_size_needed
= 0;
318 cmd_buffer
->gsvs_ring_size_needed
= 0;
319 cmd_buffer
->tess_rings_needed
= false;
320 cmd_buffer
->sample_positions_needed
= false;
322 if (cmd_buffer
->upload
.upload_bo
)
323 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
324 cmd_buffer
->upload
.upload_bo
);
325 cmd_buffer
->upload
.offset
= 0;
327 cmd_buffer
->record_result
= VK_SUCCESS
;
329 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
330 cmd_buffer
->descriptors
[i
].dirty
= 0;
331 cmd_buffer
->descriptors
[i
].valid
= 0;
332 cmd_buffer
->descriptors
[i
].push_dirty
= false;
335 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
336 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
337 unsigned eop_bug_offset
;
340 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
341 &cmd_buffer
->gfx9_fence_offset
,
343 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
347 &eop_bug_offset
, &fence_ptr
);
348 cmd_buffer
->gfx9_eop_bug_va
=
349 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
350 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
353 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
355 return cmd_buffer
->record_result
;
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
363 struct radeon_winsys_bo
*bo
;
364 struct radv_cmd_buffer_upload
*upload
;
365 struct radv_device
*device
= cmd_buffer
->device
;
367 new_size
= MAX2(min_needed
, 16 * 1024);
368 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
370 bo
= device
->ws
->buffer_create(device
->ws
,
373 RADEON_FLAG_CPU_ACCESS
|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
378 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
382 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
383 if (cmd_buffer
->upload
.upload_bo
) {
384 upload
= malloc(sizeof(*upload
));
387 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
388 device
->ws
->buffer_destroy(bo
);
392 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
393 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
396 cmd_buffer
->upload
.upload_bo
= bo
;
397 cmd_buffer
->upload
.size
= new_size
;
398 cmd_buffer
->upload
.offset
= 0;
399 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
401 if (!cmd_buffer
->upload
.map
) {
402 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
413 unsigned *out_offset
,
416 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
417 if (offset
+ size
> cmd_buffer
->upload
.size
) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
423 *out_offset
= offset
;
424 *ptr
= cmd_buffer
->upload
.map
+ offset
;
426 cmd_buffer
->upload
.offset
= offset
+ size
;
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
432 unsigned size
, unsigned alignment
,
433 const void *data
, unsigned *out_offset
)
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
438 out_offset
, (void **)&ptr
))
442 memcpy(ptr
, data
, size
);
448 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
449 unsigned count
, const uint32_t *data
)
451 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
453 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
455 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
456 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME
));
460 radeon_emit(cs
, va
>> 32);
461 radeon_emit_array(cs
, data
, count
);
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
466 struct radv_device
*device
= cmd_buffer
->device
;
467 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
470 va
= radv_buffer_get_va(device
->trace_bo
);
471 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
474 ++cmd_buffer
->state
.trace_id
;
475 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
476 &cmd_buffer
->state
.trace_id
);
478 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
480 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
481 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
486 enum radv_cmd_flush_bits flags
)
488 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
489 uint32_t *ptr
= NULL
;
492 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
495 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
496 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
497 cmd_buffer
->gfx9_fence_offset
;
498 ptr
= &cmd_buffer
->gfx9_fence_idx
;
501 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer
->cs
,
505 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
507 radv_cmd_buffer_uses_mec(cmd_buffer
),
508 flags
, cmd_buffer
->gfx9_eop_bug_va
);
511 if (unlikely(cmd_buffer
->device
->trace_bo
))
512 radv_cmd_buffer_trace_emit(cmd_buffer
);
516 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
517 struct radv_pipeline
*pipeline
, enum ring_type ring
)
519 struct radv_device
*device
= cmd_buffer
->device
;
523 va
= radv_buffer_get_va(device
->trace_bo
);
533 assert(!"invalid ring type");
536 data
[0] = (uintptr_t)pipeline
;
537 data
[1] = (uintptr_t)pipeline
>> 32;
539 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
542 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
543 VkPipelineBindPoint bind_point
,
544 struct radv_descriptor_set
*set
,
547 struct radv_descriptor_state
*descriptors_state
=
548 radv_get_descriptors_state(cmd_buffer
, bind_point
);
550 descriptors_state
->sets
[idx
] = set
;
552 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
553 descriptors_state
->dirty
|= (1u << idx
);
557 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
558 VkPipelineBindPoint bind_point
)
560 struct radv_descriptor_state
*descriptors_state
=
561 radv_get_descriptors_state(cmd_buffer
, bind_point
);
562 struct radv_device
*device
= cmd_buffer
->device
;
563 uint32_t data
[MAX_SETS
* 2] = {};
566 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
568 for_each_bit(i
, descriptors_state
->valid
) {
569 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
570 data
[i
* 2] = (uintptr_t)set
;
571 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
574 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
577 struct radv_userdata_info
*
578 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
579 gl_shader_stage stage
,
582 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
583 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
587 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
588 struct radv_pipeline
*pipeline
,
589 gl_shader_stage stage
,
590 int idx
, uint64_t va
)
592 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
593 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
594 if (loc
->sgpr_idx
== -1)
597 assert(loc
->num_sgprs
== 1);
598 assert(!loc
->indirect
);
600 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
601 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
606 struct radv_pipeline
*pipeline
,
607 struct radv_descriptor_state
*descriptors_state
,
608 gl_shader_stage stage
)
610 struct radv_device
*device
= cmd_buffer
->device
;
611 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
612 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
613 struct radv_userdata_locations
*locs
=
614 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
615 unsigned mask
= locs
->descriptor_sets_enabled
;
617 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
622 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
624 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
625 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
627 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
628 for (int i
= 0; i
< count
; i
++) {
629 struct radv_descriptor_set
*set
=
630 descriptors_state
->sets
[start
+ i
];
632 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
638 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
639 struct radv_pipeline
*pipeline
)
641 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
642 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
643 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
645 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
646 cmd_buffer
->sample_positions_needed
= true;
648 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
651 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
652 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
653 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
655 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer
->device
->dfsm_allowed
) {
661 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
662 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
667 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
668 struct radv_shader_variant
*shader
)
675 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
677 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
681 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
682 struct radv_pipeline
*pipeline
,
683 bool vertex_stage_only
)
685 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
686 uint32_t mask
= state
->prefetch_L2_mask
;
688 if (vertex_stage_only
) {
689 /* Fast prefetch path for starting draws as soon as possible.
691 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
692 RADV_PREFETCH_VBO_DESCRIPTORS
);
695 if (mask
& RADV_PREFETCH_VS
)
696 radv_emit_shader_prefetch(cmd_buffer
,
697 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
699 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
700 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
702 if (mask
& RADV_PREFETCH_TCS
)
703 radv_emit_shader_prefetch(cmd_buffer
,
704 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
706 if (mask
& RADV_PREFETCH_TES
)
707 radv_emit_shader_prefetch(cmd_buffer
,
708 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
710 if (mask
& RADV_PREFETCH_GS
) {
711 radv_emit_shader_prefetch(cmd_buffer
,
712 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
713 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
716 if (mask
& RADV_PREFETCH_PS
)
717 radv_emit_shader_prefetch(cmd_buffer
,
718 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
720 state
->prefetch_L2_mask
&= ~mask
;
724 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
726 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
729 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
730 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
731 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
733 unsigned sx_ps_downconvert
= 0;
734 unsigned sx_blend_opt_epsilon
= 0;
735 unsigned sx_blend_opt_control
= 0;
737 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
738 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
739 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
740 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
744 int idx
= subpass
->color_attachments
[i
].attachment
;
745 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
747 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
748 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
749 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
750 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
752 bool has_alpha
, has_rgb
;
754 /* Set if RGB and A are present. */
755 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
757 if (format
== V_028C70_COLOR_8
||
758 format
== V_028C70_COLOR_16
||
759 format
== V_028C70_COLOR_32
)
760 has_rgb
= !has_alpha
;
764 /* Check the colormask and export format. */
765 if (!(colormask
& 0x7))
767 if (!(colormask
& 0x8))
770 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
775 /* Disable value checking for disabled channels. */
777 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
779 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
781 /* Enable down-conversion for 32bpp and smaller formats. */
783 case V_028C70_COLOR_8
:
784 case V_028C70_COLOR_8_8
:
785 case V_028C70_COLOR_8_8_8_8
:
786 /* For 1 and 2-channel formats, use the superset thereof. */
787 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
788 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
789 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
790 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
791 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
795 case V_028C70_COLOR_5_6_5
:
796 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
797 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
798 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
802 case V_028C70_COLOR_1_5_5_5
:
803 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
804 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
805 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
809 case V_028C70_COLOR_4_4_4_4
:
810 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
811 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
812 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
816 case V_028C70_COLOR_32
:
817 if (swap
== V_028C70_SWAP_STD
&&
818 spi_format
== V_028714_SPI_SHADER_32_R
)
819 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
820 else if (swap
== V_028C70_SWAP_ALT_REV
&&
821 spi_format
== V_028714_SPI_SHADER_32_AR
)
822 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
825 case V_028C70_COLOR_16
:
826 case V_028C70_COLOR_16_16
:
827 /* For 1-channel formats, use the superset thereof. */
828 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
829 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
830 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
831 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
832 if (swap
== V_028C70_SWAP_STD
||
833 swap
== V_028C70_SWAP_STD_REV
)
834 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
836 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
840 case V_028C70_COLOR_10_11_11
:
841 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
842 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
843 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
847 case V_028C70_COLOR_2_10_10_10
:
848 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
849 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
850 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
856 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
857 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
858 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
860 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
861 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
862 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
863 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
867 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
869 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
871 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
874 radv_update_multisample_state(cmd_buffer
, pipeline
);
876 cmd_buffer
->scratch_size_needed
=
877 MAX2(cmd_buffer
->scratch_size_needed
,
878 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
880 if (!cmd_buffer
->state
.emitted_pipeline
||
881 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
882 pipeline
->graphics
.can_use_guardband
)
883 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
885 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
887 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
888 if (!pipeline
->shaders
[i
])
891 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
892 pipeline
->shaders
[i
]->bo
);
895 if (radv_pipeline_has_gs(pipeline
))
896 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
897 pipeline
->gs_copy_shader
->bo
);
899 if (unlikely(cmd_buffer
->device
->trace_bo
))
900 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
902 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
904 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
908 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
910 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
911 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
915 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
917 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
919 si_write_scissors(cmd_buffer
->cs
, 0, count
,
920 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
921 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
922 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
926 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
928 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
931 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
932 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
933 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
934 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
935 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
936 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
937 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
942 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
944 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
946 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
947 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
951 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
953 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
955 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
956 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
960 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
962 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
964 radeon_set_context_reg_seq(cmd_buffer
->cs
,
965 R_028430_DB_STENCILREFMASK
, 2);
966 radeon_emit(cmd_buffer
->cs
,
967 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
968 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
969 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
970 S_028430_STENCILOPVAL(1));
971 radeon_emit(cmd_buffer
->cs
,
972 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
973 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
974 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
975 S_028434_STENCILOPVAL_BF(1));
979 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
981 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
983 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
984 fui(d
->depth_bounds
.min
));
985 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
986 fui(d
->depth_bounds
.max
));
990 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
992 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
993 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
994 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
997 radeon_set_context_reg_seq(cmd_buffer
->cs
,
998 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
999 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1000 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1001 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1002 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1003 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1007 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1009 struct radv_attachment_info
*att
,
1010 struct radv_image
*image
,
1011 VkImageLayout layout
)
1013 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1014 struct radv_color_buffer_info
*cb
= &att
->cb
;
1015 uint32_t cb_color_info
= cb
->cb_color_info
;
1017 if (!radv_layout_dcc_compressed(image
, layout
,
1018 radv_image_queue_family_mask(image
,
1019 cmd_buffer
->queue_family_index
,
1020 cmd_buffer
->queue_family_index
))) {
1021 cb_color_info
&= C_028C70_DCC_ENABLE
;
1024 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1025 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1026 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1027 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1028 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1029 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1030 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1031 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1032 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1033 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1034 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1035 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1036 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1038 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1039 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1040 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1042 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1043 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1045 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1046 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1047 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1048 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1049 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1050 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1051 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1052 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1053 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1054 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1055 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1056 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1058 if (is_vi
) { /* DCC BASE */
1059 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1063 if (radv_image_has_dcc(image
)) {
1064 /* Drawing with DCC enabled also compresses colorbuffers. */
1065 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1070 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1071 struct radv_ds_buffer_info
*ds
,
1072 struct radv_image
*image
, VkImageLayout layout
,
1073 bool requires_cond_exec
)
1075 uint32_t db_z_info
= ds
->db_z_info
;
1076 uint32_t db_z_info_reg
;
1078 if (!radv_image_is_tc_compat_htile(image
))
1081 if (!radv_layout_has_htile(image
, layout
,
1082 radv_image_queue_family_mask(image
,
1083 cmd_buffer
->queue_family_index
,
1084 cmd_buffer
->queue_family_index
))) {
1085 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1088 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1090 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1091 db_z_info_reg
= R_028038_DB_Z_INFO
;
1093 db_z_info_reg
= R_028040_DB_Z_INFO
;
1096 /* When we don't know the last fast clear value we need to emit a
1097 * conditional packet that will eventually skip the following
1098 * SET_CONTEXT_REG packet.
1100 if (requires_cond_exec
) {
1101 uint64_t va
= radv_buffer_get_va(image
->bo
);
1102 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1104 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1105 radeon_emit(cmd_buffer
->cs
, va
);
1106 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1107 radeon_emit(cmd_buffer
->cs
, 0);
1108 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1111 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1115 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1116 struct radv_ds_buffer_info
*ds
,
1117 struct radv_image
*image
,
1118 VkImageLayout layout
)
1120 uint32_t db_z_info
= ds
->db_z_info
;
1121 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1123 if (!radv_layout_has_htile(image
, layout
,
1124 radv_image_queue_family_mask(image
,
1125 cmd_buffer
->queue_family_index
,
1126 cmd_buffer
->queue_family_index
))) {
1127 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1128 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1131 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1132 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1135 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1136 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1137 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1138 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1139 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1141 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1142 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1143 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1144 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1145 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1146 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1147 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1148 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1149 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1150 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1151 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1153 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1157 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1159 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1160 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1161 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1162 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1164 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1165 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1167 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1168 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1172 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1173 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1175 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1176 ds
->pa_su_poly_offset_db_fmt_cntl
);
1180 * Update the fast clear depth/stencil values if the image is bound as a
1181 * depth/stencil buffer.
1184 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1185 struct radv_image
*image
,
1186 VkClearDepthStencilValue ds_clear_value
,
1187 VkImageAspectFlags aspects
)
1189 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1190 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1191 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1192 struct radv_attachment_info
*att
;
1195 if (!framebuffer
|| !subpass
)
1198 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1199 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1202 att
= &framebuffer
->attachments
[att_idx
];
1203 if (att
->attachment
->image
!= image
)
1206 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1207 radeon_emit(cs
, ds_clear_value
.stencil
);
1208 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1210 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1211 * only needed when clearing Z to 0.0.
1213 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1214 ds_clear_value
.depth
== 0.0) {
1215 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1217 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1223 * Set the clear depth/stencil values to the image's metadata.
1226 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1227 struct radv_image
*image
,
1228 VkClearDepthStencilValue ds_clear_value
,
1229 VkImageAspectFlags aspects
)
1231 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1232 uint64_t va
= radv_buffer_get_va(image
->bo
);
1233 unsigned reg_offset
= 0, reg_count
= 0;
1235 va
+= image
->offset
+ image
->clear_value_offset
;
1237 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1243 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1246 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1247 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1248 S_370_WR_CONFIRM(1) |
1249 S_370_ENGINE_SEL(V_370_PFP
));
1250 radeon_emit(cs
, va
);
1251 radeon_emit(cs
, va
>> 32);
1252 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1253 radeon_emit(cs
, ds_clear_value
.stencil
);
1254 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1255 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1259 * Update the TC-compat metadata value for this image.
1262 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1263 struct radv_image
*image
,
1266 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1267 uint64_t va
= radv_buffer_get_va(image
->bo
);
1268 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1270 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1271 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1272 S_370_WR_CONFIRM(1) |
1273 S_370_ENGINE_SEL(V_370_PFP
));
1274 radeon_emit(cs
, va
);
1275 radeon_emit(cs
, va
>> 32);
1276 radeon_emit(cs
, value
);
1280 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1281 struct radv_image
*image
,
1282 VkClearDepthStencilValue ds_clear_value
)
1284 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1285 uint64_t va
= radv_buffer_get_va(image
->bo
);
1286 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1289 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1290 * depth clear value is 0.0f.
1292 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1294 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1298 * Update the clear depth/stencil values for this image.
1301 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1302 struct radv_image
*image
,
1303 VkClearDepthStencilValue ds_clear_value
,
1304 VkImageAspectFlags aspects
)
1306 assert(radv_image_has_htile(image
));
1308 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1310 if (radv_image_is_tc_compat_htile(image
) &&
1311 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1312 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1316 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1321 * Load the clear depth/stencil values from the image's metadata.
1324 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1325 struct radv_image
*image
)
1327 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1328 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1329 uint64_t va
= radv_buffer_get_va(image
->bo
);
1330 unsigned reg_offset
= 0, reg_count
= 0;
1332 va
+= image
->offset
+ image
->clear_value_offset
;
1334 if (!radv_image_has_htile(image
))
1337 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1343 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1346 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1348 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1349 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1350 radeon_emit(cs
, va
);
1351 radeon_emit(cs
, va
>> 32);
1352 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1353 radeon_emit(cs
, reg_count
);
1355 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1356 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1357 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1358 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1359 radeon_emit(cs
, va
);
1360 radeon_emit(cs
, va
>> 32);
1361 radeon_emit(cs
, reg
>> 2);
1364 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1370 * With DCC some colors don't require CMASK elimination before being
1371 * used as a texture. This sets a predicate value to determine if the
1372 * cmask eliminate is required.
1375 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1376 struct radv_image
*image
, bool value
)
1378 uint64_t pred_val
= value
;
1379 uint64_t va
= radv_buffer_get_va(image
->bo
);
1380 va
+= image
->offset
+ image
->fce_pred_offset
;
1382 assert(radv_image_has_dcc(image
));
1384 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1385 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP
));
1388 radeon_emit(cmd_buffer
->cs
, va
);
1389 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1390 radeon_emit(cmd_buffer
->cs
, pred_val
);
1391 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1395 * Update the DCC predicate to reflect the compression state.
1398 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1399 struct radv_image
*image
, bool value
)
1401 uint64_t pred_val
= value
;
1402 uint64_t va
= radv_buffer_get_va(image
->bo
);
1403 va
+= image
->offset
+ image
->dcc_pred_offset
;
1405 assert(radv_image_has_dcc(image
));
1407 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1408 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1409 S_370_WR_CONFIRM(1) |
1410 S_370_ENGINE_SEL(V_370_PFP
));
1411 radeon_emit(cmd_buffer
->cs
, va
);
1412 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1413 radeon_emit(cmd_buffer
->cs
, pred_val
);
1414 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1418 * Update the fast clear color values if the image is bound as a color buffer.
1421 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1422 struct radv_image
*image
,
1424 uint32_t color_values
[2])
1426 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1427 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1428 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1429 struct radv_attachment_info
*att
;
1432 if (!framebuffer
|| !subpass
)
1435 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1436 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1439 att
= &framebuffer
->attachments
[att_idx
];
1440 if (att
->attachment
->image
!= image
)
1443 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1444 radeon_emit(cs
, color_values
[0]);
1445 radeon_emit(cs
, color_values
[1]);
1449 * Set the clear color values to the image's metadata.
1452 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1453 struct radv_image
*image
,
1454 uint32_t color_values
[2])
1456 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1457 uint64_t va
= radv_buffer_get_va(image
->bo
);
1459 va
+= image
->offset
+ image
->clear_value_offset
;
1461 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1463 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1464 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1465 S_370_WR_CONFIRM(1) |
1466 S_370_ENGINE_SEL(V_370_PFP
));
1467 radeon_emit(cs
, va
);
1468 radeon_emit(cs
, va
>> 32);
1469 radeon_emit(cs
, color_values
[0]);
1470 radeon_emit(cs
, color_values
[1]);
1474 * Update the clear color values for this image.
1477 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1478 struct radv_image
*image
,
1480 uint32_t color_values
[2])
1482 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1484 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1486 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1491 * Load the clear color values from the image's metadata.
1494 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1495 struct radv_image
*image
,
1498 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1499 uint64_t va
= radv_buffer_get_va(image
->bo
);
1501 va
+= image
->offset
+ image
->clear_value_offset
;
1503 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1506 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1508 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1509 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1510 radeon_emit(cs
, va
);
1511 radeon_emit(cs
, va
>> 32);
1512 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1515 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1516 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1517 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1518 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1519 COPY_DATA_COUNT_SEL
);
1520 radeon_emit(cs
, va
);
1521 radeon_emit(cs
, va
>> 32);
1522 radeon_emit(cs
, reg
>> 2);
1525 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1531 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1534 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1535 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1536 unsigned num_bpp64_colorbufs
= 0;
1538 /* this may happen for inherited secondary recording */
1542 for (i
= 0; i
< 8; ++i
) {
1543 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1544 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1545 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1549 int idx
= subpass
->color_attachments
[i
].attachment
;
1550 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1551 struct radv_image
*image
= att
->attachment
->image
;
1552 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1554 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1556 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1557 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1559 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1561 if (image
->surface
.bpe
>= 8)
1562 num_bpp64_colorbufs
++;
1565 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1566 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1567 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1568 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1569 struct radv_image
*image
= att
->attachment
->image
;
1570 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1571 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1572 cmd_buffer
->queue_family_index
,
1573 cmd_buffer
->queue_family_index
);
1574 /* We currently don't support writing decompressed HTILE */
1575 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1576 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1578 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1580 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1581 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1582 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1584 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1586 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1587 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1589 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1591 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1592 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1594 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1595 S_028208_BR_X(framebuffer
->width
) |
1596 S_028208_BR_Y(framebuffer
->height
));
1598 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
) {
1599 uint8_t watermark
= 4; /* Default value for VI. */
1601 /* For optimal DCC performance. */
1602 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1603 if (num_bpp64_colorbufs
>= 5) {
1610 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1611 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1612 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1615 if (cmd_buffer
->device
->dfsm_allowed
) {
1616 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1617 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1620 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1624 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1626 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1627 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1629 if (state
->index_type
!= state
->last_index_type
) {
1630 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1631 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1632 2, state
->index_type
);
1634 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1635 radeon_emit(cs
, state
->index_type
);
1638 state
->last_index_type
= state
->index_type
;
1641 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1642 radeon_emit(cs
, state
->index_va
);
1643 radeon_emit(cs
, state
->index_va
>> 32);
1645 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1646 radeon_emit(cs
, state
->max_index_count
);
1648 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1651 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1653 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1654 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1655 uint32_t pa_sc_mode_cntl_1
=
1656 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1657 uint32_t db_count_control
;
1659 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1660 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1661 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1662 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1663 has_perfect_queries
) {
1664 /* Re-enable out-of-order rasterization if the
1665 * bound pipeline supports it and if it's has
1666 * been disabled before starting any perfect
1667 * occlusion queries.
1669 radeon_set_context_reg(cmd_buffer
->cs
,
1670 R_028A4C_PA_SC_MODE_CNTL_1
,
1674 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1676 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1677 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1679 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1681 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1682 S_028004_SAMPLE_RATE(sample_rate
) |
1683 S_028004_ZPASS_ENABLE(1) |
1684 S_028004_SLICE_EVEN_ENABLE(1) |
1685 S_028004_SLICE_ODD_ENABLE(1);
1687 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1688 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1689 has_perfect_queries
) {
1690 /* If the bound pipeline has enabled
1691 * out-of-order rasterization, we should
1692 * disable it before starting any perfect
1693 * occlusion queries.
1695 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1697 radeon_set_context_reg(cmd_buffer
->cs
,
1698 R_028A4C_PA_SC_MODE_CNTL_1
,
1702 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1703 S_028004_SAMPLE_RATE(sample_rate
);
1707 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1711 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1713 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1715 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1716 radv_emit_viewport(cmd_buffer
);
1718 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1719 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1720 radv_emit_scissor(cmd_buffer
);
1722 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1723 radv_emit_line_width(cmd_buffer
);
1725 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1726 radv_emit_blend_constants(cmd_buffer
);
1728 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1729 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1730 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1731 radv_emit_stencil(cmd_buffer
);
1733 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1734 radv_emit_depth_bounds(cmd_buffer
);
1736 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1737 radv_emit_depth_bias(cmd_buffer
);
1739 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1740 radv_emit_discard_rectangle(cmd_buffer
);
1742 cmd_buffer
->state
.dirty
&= ~states
;
1746 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1747 VkPipelineBindPoint bind_point
)
1749 struct radv_descriptor_state
*descriptors_state
=
1750 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1751 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1754 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1759 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1760 set
->va
+= bo_offset
;
1764 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1765 VkPipelineBindPoint bind_point
)
1767 struct radv_descriptor_state
*descriptors_state
=
1768 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1769 uint32_t size
= MAX_SETS
* 4;
1773 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1774 256, &offset
, &ptr
))
1777 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1778 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
1779 uint64_t set_va
= 0;
1780 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1781 if (descriptors_state
->valid
& (1u << i
))
1783 uptr
[0] = set_va
& 0xffffffff;
1786 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1789 if (cmd_buffer
->state
.pipeline
) {
1790 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1791 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1792 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1794 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1795 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1796 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1798 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1799 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1800 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1802 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1803 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1804 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1806 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1807 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1808 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1811 if (cmd_buffer
->state
.compute_pipeline
)
1812 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1813 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1817 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1818 VkShaderStageFlags stages
)
1820 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1821 VK_PIPELINE_BIND_POINT_COMPUTE
:
1822 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1823 struct radv_descriptor_state
*descriptors_state
=
1824 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1825 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1826 bool flush_indirect_descriptors
;
1828 if (!descriptors_state
->dirty
)
1831 if (descriptors_state
->push_dirty
)
1832 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1834 flush_indirect_descriptors
=
1835 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
1836 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
1837 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
1838 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
1840 if (flush_indirect_descriptors
)
1841 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1843 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1845 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1847 if (cmd_buffer
->state
.pipeline
) {
1848 radv_foreach_stage(stage
, stages
) {
1849 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1852 radv_emit_descriptor_pointers(cmd_buffer
,
1853 cmd_buffer
->state
.pipeline
,
1854 descriptors_state
, stage
);
1858 if (cmd_buffer
->state
.compute_pipeline
&&
1859 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1860 radv_emit_descriptor_pointers(cmd_buffer
,
1861 cmd_buffer
->state
.compute_pipeline
,
1863 MESA_SHADER_COMPUTE
);
1866 descriptors_state
->dirty
= 0;
1867 descriptors_state
->push_dirty
= false;
1869 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1871 if (unlikely(cmd_buffer
->device
->trace_bo
))
1872 radv_save_descriptors(cmd_buffer
, bind_point
);
1876 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1877 VkShaderStageFlags stages
)
1879 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1880 ? cmd_buffer
->state
.compute_pipeline
1881 : cmd_buffer
->state
.pipeline
;
1882 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1883 VK_PIPELINE_BIND_POINT_COMPUTE
:
1884 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1885 struct radv_descriptor_state
*descriptors_state
=
1886 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1887 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1888 struct radv_shader_variant
*shader
, *prev_shader
;
1893 stages
&= cmd_buffer
->push_constant_stages
;
1895 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1898 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1899 16 * layout
->dynamic_offset_count
,
1900 256, &offset
, &ptr
))
1903 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1904 memcpy((char*)ptr
+ layout
->push_constant_size
,
1905 descriptors_state
->dynamic_buffers
,
1906 16 * layout
->dynamic_offset_count
);
1908 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1911 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1912 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1915 radv_foreach_stage(stage
, stages
) {
1916 shader
= radv_get_shader(pipeline
, stage
);
1918 /* Avoid redundantly emitting the address for merged stages. */
1919 if (shader
&& shader
!= prev_shader
) {
1920 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1921 AC_UD_PUSH_CONSTANTS
, va
);
1923 prev_shader
= shader
;
1927 cmd_buffer
->push_constant_stages
&= ~stages
;
1928 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1932 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1933 bool pipeline_is_dirty
)
1935 if ((pipeline_is_dirty
||
1936 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1937 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1938 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1939 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1943 uint32_t count
= velems
->count
;
1946 /* allocate some descriptor state for vertex buffers */
1947 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1948 &vb_offset
, &vb_ptr
))
1951 for (i
= 0; i
< count
; i
++) {
1952 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1954 int vb
= velems
->binding
[i
];
1955 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1956 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1958 va
= radv_buffer_get_va(buffer
->bo
);
1960 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1961 va
+= offset
+ buffer
->offset
;
1963 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1964 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1965 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1967 desc
[2] = buffer
->size
- offset
;
1968 desc
[3] = velems
->rsrc_word3
[i
];
1971 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1974 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1975 AC_UD_VS_VERTEX_BUFFERS
, va
);
1977 cmd_buffer
->state
.vb_va
= va
;
1978 cmd_buffer
->state
.vb_size
= count
* 16;
1979 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
1981 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1985 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
1987 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1988 struct radv_userdata_info
*loc
;
1991 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
1992 if (!radv_get_shader(pipeline
, stage
))
1995 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
1996 AC_UD_STREAMOUT_BUFFERS
);
1997 if (loc
->sgpr_idx
== -1)
2000 base_reg
= pipeline
->user_data_0
[stage
];
2002 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2003 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2006 if (pipeline
->gs_copy_shader
) {
2007 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2008 if (loc
->sgpr_idx
!= -1) {
2009 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2011 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2012 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2018 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2020 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2021 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2022 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2027 /* Allocate some descriptor state for streamout buffers. */
2028 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2029 MAX_SO_BUFFERS
* 16, 256,
2030 &so_offset
, &so_ptr
))
2033 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2034 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2035 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2037 if (!(so
->enabled_mask
& (1 << i
)))
2040 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2044 /* Set the descriptor.
2046 * On VI, the format must be non-INVALID, otherwise
2047 * the buffer will be considered not bound and store
2048 * instructions will be no-ops.
2051 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2052 desc
[2] = 0xffffffff;
2053 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2054 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2055 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2056 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2057 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2060 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2063 radv_emit_streamout_buffers(cmd_buffer
, va
);
2066 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2070 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2072 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2073 radv_flush_streamout_descriptors(cmd_buffer
);
2074 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2075 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2079 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
2080 bool instanced_draw
, bool indirect_draw
,
2081 uint32_t draw_vertex_count
)
2083 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2084 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2085 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2086 uint32_t ia_multi_vgt_param
;
2087 int32_t primitive_reset_en
;
2090 ia_multi_vgt_param
=
2091 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2092 indirect_draw
, draw_vertex_count
);
2094 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2095 if (info
->chip_class
>= GFX9
) {
2096 radeon_set_uconfig_reg_idx(cs
,
2097 R_030960_IA_MULTI_VGT_PARAM
,
2098 4, ia_multi_vgt_param
);
2099 } else if (info
->chip_class
>= CIK
) {
2100 radeon_set_context_reg_idx(cs
,
2101 R_028AA8_IA_MULTI_VGT_PARAM
,
2102 1, ia_multi_vgt_param
);
2104 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2105 ia_multi_vgt_param
);
2107 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2110 /* Primitive restart. */
2111 primitive_reset_en
=
2112 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
2114 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2115 state
->last_primitive_reset_en
= primitive_reset_en
;
2116 if (info
->chip_class
>= GFX9
) {
2117 radeon_set_uconfig_reg(cs
,
2118 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2119 primitive_reset_en
);
2121 radeon_set_context_reg(cs
,
2122 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2123 primitive_reset_en
);
2127 if (primitive_reset_en
) {
2128 uint32_t primitive_reset_index
=
2129 state
->index_type
? 0xffffffffu
: 0xffffu
;
2131 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2132 radeon_set_context_reg(cs
,
2133 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2134 primitive_reset_index
);
2135 state
->last_primitive_reset_index
= primitive_reset_index
;
2140 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2141 VkPipelineStageFlags src_stage_mask
)
2143 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2144 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2145 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2146 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2147 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2150 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2151 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2152 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2153 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2154 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2155 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2156 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2157 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2158 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2159 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2160 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2161 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2162 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2163 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2164 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2165 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2166 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2170 static enum radv_cmd_flush_bits
2171 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2172 VkAccessFlags src_flags
,
2173 struct radv_image
*image
)
2175 bool flush_CB_meta
= true, flush_DB_meta
= true;
2176 enum radv_cmd_flush_bits flush_bits
= 0;
2180 if (!radv_image_has_CB_metadata(image
))
2181 flush_CB_meta
= false;
2182 if (!radv_image_has_htile(image
))
2183 flush_DB_meta
= false;
2186 for_each_bit(b
, src_flags
) {
2187 switch ((VkAccessFlagBits
)(1 << b
)) {
2188 case VK_ACCESS_SHADER_WRITE_BIT
:
2189 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2190 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2191 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2193 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2194 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2196 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2198 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2199 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2201 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2203 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2204 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2205 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2206 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2209 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2211 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2220 static enum radv_cmd_flush_bits
2221 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2222 VkAccessFlags dst_flags
,
2223 struct radv_image
*image
)
2225 bool flush_CB_meta
= true, flush_DB_meta
= true;
2226 enum radv_cmd_flush_bits flush_bits
= 0;
2227 bool flush_CB
= true, flush_DB
= true;
2228 bool image_is_coherent
= false;
2232 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2237 if (!radv_image_has_CB_metadata(image
))
2238 flush_CB_meta
= false;
2239 if (!radv_image_has_htile(image
))
2240 flush_DB_meta
= false;
2242 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2243 if (image
->info
.samples
== 1 &&
2244 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2245 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2246 !vk_format_is_stencil(image
->vk_format
)) {
2247 /* Single-sample color and single-sample depth
2248 * (not stencil) are coherent with shaders on
2251 image_is_coherent
= true;
2256 for_each_bit(b
, dst_flags
) {
2257 switch ((VkAccessFlagBits
)(1 << b
)) {
2258 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2259 case VK_ACCESS_INDEX_READ_BIT
:
2260 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2262 case VK_ACCESS_UNIFORM_READ_BIT
:
2263 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2265 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2266 case VK_ACCESS_TRANSFER_READ_BIT
:
2267 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2268 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2269 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2271 case VK_ACCESS_SHADER_READ_BIT
:
2272 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2274 if (!image_is_coherent
)
2275 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2277 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2279 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2281 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2283 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2285 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2287 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2296 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2297 const struct radv_subpass_barrier
*barrier
)
2299 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2301 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2302 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2306 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2307 struct radv_subpass_attachment att
)
2309 unsigned idx
= att
.attachment
;
2310 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2311 VkImageSubresourceRange range
;
2312 range
.aspectMask
= 0;
2313 range
.baseMipLevel
= view
->base_mip
;
2314 range
.levelCount
= 1;
2315 range
.baseArrayLayer
= view
->base_layer
;
2316 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2318 radv_handle_image_transition(cmd_buffer
,
2320 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2321 att
.layout
, 0, 0, &range
);
2323 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2329 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2330 const struct radv_subpass
*subpass
, bool transitions
)
2333 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2335 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2336 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2337 radv_handle_subpass_image_transition(cmd_buffer
,
2338 subpass
->color_attachments
[i
]);
2341 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2342 radv_handle_subpass_image_transition(cmd_buffer
,
2343 subpass
->input_attachments
[i
]);
2346 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2347 radv_handle_subpass_image_transition(cmd_buffer
,
2348 subpass
->depth_stencil_attachment
);
2352 cmd_buffer
->state
.subpass
= subpass
;
2354 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2358 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2359 struct radv_render_pass
*pass
,
2360 const VkRenderPassBeginInfo
*info
)
2362 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2364 if (pass
->attachment_count
== 0) {
2365 state
->attachments
= NULL
;
2369 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2370 pass
->attachment_count
*
2371 sizeof(state
->attachments
[0]),
2372 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2373 if (state
->attachments
== NULL
) {
2374 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2375 return cmd_buffer
->record_result
;
2378 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2379 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2380 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2381 VkImageAspectFlags clear_aspects
= 0;
2383 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2384 /* color attachment */
2385 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2386 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2389 /* depthstencil attachment */
2390 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2391 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2392 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2393 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2394 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2395 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2397 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2398 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2399 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2403 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2404 state
->attachments
[i
].cleared_views
= 0;
2405 if (clear_aspects
&& info
) {
2406 assert(info
->clearValueCount
> i
);
2407 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2410 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2416 VkResult
radv_AllocateCommandBuffers(
2418 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2419 VkCommandBuffer
*pCommandBuffers
)
2421 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2422 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2424 VkResult result
= VK_SUCCESS
;
2427 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2429 if (!list_empty(&pool
->free_cmd_buffers
)) {
2430 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2432 list_del(&cmd_buffer
->pool_link
);
2433 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2435 result
= radv_reset_cmd_buffer(cmd_buffer
);
2436 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2437 cmd_buffer
->level
= pAllocateInfo
->level
;
2439 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2441 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2442 &pCommandBuffers
[i
]);
2444 if (result
!= VK_SUCCESS
)
2448 if (result
!= VK_SUCCESS
) {
2449 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2450 i
, pCommandBuffers
);
2452 /* From the Vulkan 1.0.66 spec:
2454 * "vkAllocateCommandBuffers can be used to create multiple
2455 * command buffers. If the creation of any of those command
2456 * buffers fails, the implementation must destroy all
2457 * successfully created command buffer objects from this
2458 * command, set all entries of the pCommandBuffers array to
2459 * NULL and return the error."
2461 memset(pCommandBuffers
, 0,
2462 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2468 void radv_FreeCommandBuffers(
2470 VkCommandPool commandPool
,
2471 uint32_t commandBufferCount
,
2472 const VkCommandBuffer
*pCommandBuffers
)
2474 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2475 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2478 if (cmd_buffer
->pool
) {
2479 list_del(&cmd_buffer
->pool_link
);
2480 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2482 radv_cmd_buffer_destroy(cmd_buffer
);
2488 VkResult
radv_ResetCommandBuffer(
2489 VkCommandBuffer commandBuffer
,
2490 VkCommandBufferResetFlags flags
)
2492 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2493 return radv_reset_cmd_buffer(cmd_buffer
);
2496 VkResult
radv_BeginCommandBuffer(
2497 VkCommandBuffer commandBuffer
,
2498 const VkCommandBufferBeginInfo
*pBeginInfo
)
2500 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2501 VkResult result
= VK_SUCCESS
;
2503 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2504 /* If the command buffer has already been resetted with
2505 * vkResetCommandBuffer, no need to do it again.
2507 result
= radv_reset_cmd_buffer(cmd_buffer
);
2508 if (result
!= VK_SUCCESS
)
2512 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2513 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2514 cmd_buffer
->state
.last_index_type
= -1;
2515 cmd_buffer
->state
.last_num_instances
= -1;
2516 cmd_buffer
->state
.last_vertex_offset
= -1;
2517 cmd_buffer
->state
.last_first_instance
= -1;
2518 cmd_buffer
->state
.predication_type
= -1;
2519 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2521 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2522 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2523 assert(pBeginInfo
->pInheritanceInfo
);
2524 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2525 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2527 struct radv_subpass
*subpass
=
2528 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2530 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2531 if (result
!= VK_SUCCESS
)
2534 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2537 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2538 struct radv_device
*device
= cmd_buffer
->device
;
2540 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2543 radv_cmd_buffer_trace_emit(cmd_buffer
);
2546 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2551 void radv_CmdBindVertexBuffers(
2552 VkCommandBuffer commandBuffer
,
2553 uint32_t firstBinding
,
2554 uint32_t bindingCount
,
2555 const VkBuffer
* pBuffers
,
2556 const VkDeviceSize
* pOffsets
)
2558 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2559 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2560 bool changed
= false;
2562 /* We have to defer setting up vertex buffer since we need the buffer
2563 * stride from the pipeline. */
2565 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2566 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2567 uint32_t idx
= firstBinding
+ i
;
2570 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2571 vb
[idx
].offset
!= pOffsets
[i
])) {
2575 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2576 vb
[idx
].offset
= pOffsets
[i
];
2578 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2579 vb
[idx
].buffer
->bo
);
2583 /* No state changes. */
2587 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2590 void radv_CmdBindIndexBuffer(
2591 VkCommandBuffer commandBuffer
,
2593 VkDeviceSize offset
,
2594 VkIndexType indexType
)
2596 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2597 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2599 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2600 cmd_buffer
->state
.index_offset
== offset
&&
2601 cmd_buffer
->state
.index_type
== indexType
) {
2602 /* No state changes. */
2606 cmd_buffer
->state
.index_buffer
= index_buffer
;
2607 cmd_buffer
->state
.index_offset
= offset
;
2608 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2609 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2610 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2612 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2613 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2614 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2615 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2620 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2621 VkPipelineBindPoint bind_point
,
2622 struct radv_descriptor_set
*set
, unsigned idx
)
2624 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2626 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2629 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2631 if (!cmd_buffer
->device
->use_global_bo_list
) {
2632 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2633 if (set
->descriptors
[j
])
2634 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2638 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2641 void radv_CmdBindDescriptorSets(
2642 VkCommandBuffer commandBuffer
,
2643 VkPipelineBindPoint pipelineBindPoint
,
2644 VkPipelineLayout _layout
,
2646 uint32_t descriptorSetCount
,
2647 const VkDescriptorSet
* pDescriptorSets
,
2648 uint32_t dynamicOffsetCount
,
2649 const uint32_t* pDynamicOffsets
)
2651 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2652 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2653 unsigned dyn_idx
= 0;
2655 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2656 struct radv_descriptor_state
*descriptors_state
=
2657 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2659 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2660 unsigned idx
= i
+ firstSet
;
2661 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2662 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2664 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2665 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2666 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2667 assert(dyn_idx
< dynamicOffsetCount
);
2669 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2670 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2672 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2673 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2674 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2675 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2676 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2677 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2678 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2679 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2680 cmd_buffer
->push_constant_stages
|=
2681 set
->layout
->dynamic_shader_stages
;
2686 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2687 struct radv_descriptor_set
*set
,
2688 struct radv_descriptor_set_layout
*layout
,
2689 VkPipelineBindPoint bind_point
)
2691 struct radv_descriptor_state
*descriptors_state
=
2692 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2693 set
->size
= layout
->size
;
2694 set
->layout
= layout
;
2696 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2697 size_t new_size
= MAX2(set
->size
, 1024);
2698 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2699 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2701 free(set
->mapped_ptr
);
2702 set
->mapped_ptr
= malloc(new_size
);
2704 if (!set
->mapped_ptr
) {
2705 descriptors_state
->push_set
.capacity
= 0;
2706 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2710 descriptors_state
->push_set
.capacity
= new_size
;
2716 void radv_meta_push_descriptor_set(
2717 struct radv_cmd_buffer
* cmd_buffer
,
2718 VkPipelineBindPoint pipelineBindPoint
,
2719 VkPipelineLayout _layout
,
2721 uint32_t descriptorWriteCount
,
2722 const VkWriteDescriptorSet
* pDescriptorWrites
)
2724 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2725 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2729 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2731 push_set
->size
= layout
->set
[set
].layout
->size
;
2732 push_set
->layout
= layout
->set
[set
].layout
;
2734 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2736 (void**) &push_set
->mapped_ptr
))
2739 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2740 push_set
->va
+= bo_offset
;
2742 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2743 radv_descriptor_set_to_handle(push_set
),
2744 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2746 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2749 void radv_CmdPushDescriptorSetKHR(
2750 VkCommandBuffer commandBuffer
,
2751 VkPipelineBindPoint pipelineBindPoint
,
2752 VkPipelineLayout _layout
,
2754 uint32_t descriptorWriteCount
,
2755 const VkWriteDescriptorSet
* pDescriptorWrites
)
2757 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2758 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2759 struct radv_descriptor_state
*descriptors_state
=
2760 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2761 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2763 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2765 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2766 layout
->set
[set
].layout
,
2770 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2771 radv_descriptor_set_to_handle(push_set
),
2772 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2774 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2775 descriptors_state
->push_dirty
= true;
2778 void radv_CmdPushDescriptorSetWithTemplateKHR(
2779 VkCommandBuffer commandBuffer
,
2780 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2781 VkPipelineLayout _layout
,
2785 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2786 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2787 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2788 struct radv_descriptor_state
*descriptors_state
=
2789 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2790 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2792 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2794 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2795 layout
->set
[set
].layout
,
2799 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2800 descriptorUpdateTemplate
, pData
);
2802 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2803 descriptors_state
->push_dirty
= true;
2806 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2807 VkPipelineLayout layout
,
2808 VkShaderStageFlags stageFlags
,
2811 const void* pValues
)
2813 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2814 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2815 cmd_buffer
->push_constant_stages
|= stageFlags
;
2818 VkResult
radv_EndCommandBuffer(
2819 VkCommandBuffer commandBuffer
)
2821 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2823 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2824 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2825 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2826 si_emit_cache_flush(cmd_buffer
);
2829 /* Make sure CP DMA is idle at the end of IBs because the kernel
2830 * doesn't wait for it.
2832 si_cp_dma_wait_for_idle(cmd_buffer
);
2834 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2836 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2837 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2839 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2841 return cmd_buffer
->record_result
;
2845 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2847 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2849 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2852 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2854 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2855 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2857 cmd_buffer
->compute_scratch_size_needed
=
2858 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2859 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2861 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2862 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2864 if (unlikely(cmd_buffer
->device
->trace_bo
))
2865 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2868 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2869 VkPipelineBindPoint bind_point
)
2871 struct radv_descriptor_state
*descriptors_state
=
2872 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2874 descriptors_state
->dirty
|= descriptors_state
->valid
;
2877 void radv_CmdBindPipeline(
2878 VkCommandBuffer commandBuffer
,
2879 VkPipelineBindPoint pipelineBindPoint
,
2880 VkPipeline _pipeline
)
2882 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2883 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2885 switch (pipelineBindPoint
) {
2886 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2887 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2889 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2891 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2892 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2894 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2895 if (cmd_buffer
->state
.pipeline
== pipeline
)
2897 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2899 cmd_buffer
->state
.pipeline
= pipeline
;
2903 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2904 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2906 /* the new vertex shader might not have the same user regs */
2907 cmd_buffer
->state
.last_first_instance
= -1;
2908 cmd_buffer
->state
.last_vertex_offset
= -1;
2910 /* Prefetch all pipeline shaders at first draw time. */
2911 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
2913 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2914 radv_bind_streamout_state(cmd_buffer
, pipeline
);
2916 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2917 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2918 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2919 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2921 if (radv_pipeline_has_tess(pipeline
))
2922 cmd_buffer
->tess_rings_needed
= true;
2925 assert(!"invalid bind point");
2930 void radv_CmdSetViewport(
2931 VkCommandBuffer commandBuffer
,
2932 uint32_t firstViewport
,
2933 uint32_t viewportCount
,
2934 const VkViewport
* pViewports
)
2936 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2937 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2938 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2940 assert(firstViewport
< MAX_VIEWPORTS
);
2941 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2943 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
2944 viewportCount
* sizeof(*pViewports
));
2946 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2949 void radv_CmdSetScissor(
2950 VkCommandBuffer commandBuffer
,
2951 uint32_t firstScissor
,
2952 uint32_t scissorCount
,
2953 const VkRect2D
* pScissors
)
2955 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2956 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2957 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2959 assert(firstScissor
< MAX_SCISSORS
);
2960 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2962 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
2963 scissorCount
* sizeof(*pScissors
));
2965 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2968 void radv_CmdSetLineWidth(
2969 VkCommandBuffer commandBuffer
,
2972 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2973 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2974 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2977 void radv_CmdSetDepthBias(
2978 VkCommandBuffer commandBuffer
,
2979 float depthBiasConstantFactor
,
2980 float depthBiasClamp
,
2981 float depthBiasSlopeFactor
)
2983 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2985 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2986 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2987 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2989 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2992 void radv_CmdSetBlendConstants(
2993 VkCommandBuffer commandBuffer
,
2994 const float blendConstants
[4])
2996 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2998 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2999 blendConstants
, sizeof(float) * 4);
3001 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3004 void radv_CmdSetDepthBounds(
3005 VkCommandBuffer commandBuffer
,
3006 float minDepthBounds
,
3007 float maxDepthBounds
)
3009 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3011 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
3012 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
3014 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3017 void radv_CmdSetStencilCompareMask(
3018 VkCommandBuffer commandBuffer
,
3019 VkStencilFaceFlags faceMask
,
3020 uint32_t compareMask
)
3022 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3024 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3025 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
3026 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3027 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
3029 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3032 void radv_CmdSetStencilWriteMask(
3033 VkCommandBuffer commandBuffer
,
3034 VkStencilFaceFlags faceMask
,
3037 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3039 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3040 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
3041 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3042 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
3044 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3047 void radv_CmdSetStencilReference(
3048 VkCommandBuffer commandBuffer
,
3049 VkStencilFaceFlags faceMask
,
3052 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3054 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3055 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3056 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3057 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3059 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3062 void radv_CmdSetDiscardRectangleEXT(
3063 VkCommandBuffer commandBuffer
,
3064 uint32_t firstDiscardRectangle
,
3065 uint32_t discardRectangleCount
,
3066 const VkRect2D
* pDiscardRectangles
)
3068 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3069 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3070 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3072 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3073 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3075 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3076 pDiscardRectangles
, discardRectangleCount
);
3078 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3081 void radv_CmdExecuteCommands(
3082 VkCommandBuffer commandBuffer
,
3083 uint32_t commandBufferCount
,
3084 const VkCommandBuffer
* pCmdBuffers
)
3086 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3088 assert(commandBufferCount
> 0);
3090 /* Emit pending flushes on primary prior to executing secondary */
3091 si_emit_cache_flush(primary
);
3093 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3094 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3096 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3097 secondary
->scratch_size_needed
);
3098 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3099 secondary
->compute_scratch_size_needed
);
3101 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3102 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3103 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3104 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3105 if (secondary
->tess_rings_needed
)
3106 primary
->tess_rings_needed
= true;
3107 if (secondary
->sample_positions_needed
)
3108 primary
->sample_positions_needed
= true;
3110 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3113 /* When the secondary command buffer is compute only we don't
3114 * need to re-emit the current graphics pipeline.
3116 if (secondary
->state
.emitted_pipeline
) {
3117 primary
->state
.emitted_pipeline
=
3118 secondary
->state
.emitted_pipeline
;
3121 /* When the secondary command buffer is graphics only we don't
3122 * need to re-emit the current compute pipeline.
3124 if (secondary
->state
.emitted_compute_pipeline
) {
3125 primary
->state
.emitted_compute_pipeline
=
3126 secondary
->state
.emitted_compute_pipeline
;
3129 /* Only re-emit the draw packets when needed. */
3130 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3131 primary
->state
.last_primitive_reset_en
=
3132 secondary
->state
.last_primitive_reset_en
;
3135 if (secondary
->state
.last_primitive_reset_index
) {
3136 primary
->state
.last_primitive_reset_index
=
3137 secondary
->state
.last_primitive_reset_index
;
3140 if (secondary
->state
.last_ia_multi_vgt_param
) {
3141 primary
->state
.last_ia_multi_vgt_param
=
3142 secondary
->state
.last_ia_multi_vgt_param
;
3145 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3146 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3147 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3149 if (secondary
->state
.last_index_type
!= -1) {
3150 primary
->state
.last_index_type
=
3151 secondary
->state
.last_index_type
;
3155 /* After executing commands from secondary buffers we have to dirty
3158 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3159 RADV_CMD_DIRTY_INDEX_BUFFER
|
3160 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3161 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3162 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3165 VkResult
radv_CreateCommandPool(
3167 const VkCommandPoolCreateInfo
* pCreateInfo
,
3168 const VkAllocationCallbacks
* pAllocator
,
3169 VkCommandPool
* pCmdPool
)
3171 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3172 struct radv_cmd_pool
*pool
;
3174 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3175 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3177 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3180 pool
->alloc
= *pAllocator
;
3182 pool
->alloc
= device
->alloc
;
3184 list_inithead(&pool
->cmd_buffers
);
3185 list_inithead(&pool
->free_cmd_buffers
);
3187 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3189 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3195 void radv_DestroyCommandPool(
3197 VkCommandPool commandPool
,
3198 const VkAllocationCallbacks
* pAllocator
)
3200 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3201 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3206 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3207 &pool
->cmd_buffers
, pool_link
) {
3208 radv_cmd_buffer_destroy(cmd_buffer
);
3211 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3212 &pool
->free_cmd_buffers
, pool_link
) {
3213 radv_cmd_buffer_destroy(cmd_buffer
);
3216 vk_free2(&device
->alloc
, pAllocator
, pool
);
3219 VkResult
radv_ResetCommandPool(
3221 VkCommandPool commandPool
,
3222 VkCommandPoolResetFlags flags
)
3224 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3227 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3228 &pool
->cmd_buffers
, pool_link
) {
3229 result
= radv_reset_cmd_buffer(cmd_buffer
);
3230 if (result
!= VK_SUCCESS
)
3237 void radv_TrimCommandPool(
3239 VkCommandPool commandPool
,
3240 VkCommandPoolTrimFlagsKHR flags
)
3242 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3247 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3248 &pool
->free_cmd_buffers
, pool_link
) {
3249 radv_cmd_buffer_destroy(cmd_buffer
);
3253 void radv_CmdBeginRenderPass(
3254 VkCommandBuffer commandBuffer
,
3255 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3256 VkSubpassContents contents
)
3258 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3259 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3260 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3262 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3263 cmd_buffer
->cs
, 2048);
3264 MAYBE_UNUSED VkResult result
;
3266 cmd_buffer
->state
.framebuffer
= framebuffer
;
3267 cmd_buffer
->state
.pass
= pass
;
3268 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3270 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3271 if (result
!= VK_SUCCESS
)
3274 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3275 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3277 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3280 void radv_CmdBeginRenderPass2KHR(
3281 VkCommandBuffer commandBuffer
,
3282 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3283 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3285 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3286 pSubpassBeginInfo
->contents
);
3289 void radv_CmdNextSubpass(
3290 VkCommandBuffer commandBuffer
,
3291 VkSubpassContents contents
)
3293 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3295 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3297 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3300 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3301 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3304 void radv_CmdNextSubpass2KHR(
3305 VkCommandBuffer commandBuffer
,
3306 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3307 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3309 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3312 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3314 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3315 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3316 if (!radv_get_shader(pipeline
, stage
))
3319 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3320 if (loc
->sgpr_idx
== -1)
3322 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3323 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3326 if (pipeline
->gs_copy_shader
) {
3327 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3328 if (loc
->sgpr_idx
!= -1) {
3329 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3330 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3336 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3337 uint32_t vertex_count
,
3340 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3341 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3342 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3343 S_0287F0_USE_OPAQUE(use_opaque
));
3347 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3349 uint32_t index_count
)
3351 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3352 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3353 radeon_emit(cmd_buffer
->cs
, index_va
);
3354 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3355 radeon_emit(cmd_buffer
->cs
, index_count
);
3356 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3360 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3362 uint32_t draw_count
,
3366 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3367 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3368 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3369 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3370 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3371 bool predicating
= cmd_buffer
->state
.predicating
;
3374 /* just reset draw state for vertex data */
3375 cmd_buffer
->state
.last_first_instance
= -1;
3376 cmd_buffer
->state
.last_num_instances
= -1;
3377 cmd_buffer
->state
.last_vertex_offset
= -1;
3379 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3380 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3381 PKT3_DRAW_INDIRECT
, 3, predicating
));
3383 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3384 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3385 radeon_emit(cs
, di_src_sel
);
3387 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3388 PKT3_DRAW_INDIRECT_MULTI
,
3391 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3392 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3393 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3394 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3395 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3396 radeon_emit(cs
, draw_count
); /* count */
3397 radeon_emit(cs
, count_va
); /* count_addr */
3398 radeon_emit(cs
, count_va
>> 32);
3399 radeon_emit(cs
, stride
); /* stride */
3400 radeon_emit(cs
, di_src_sel
);
3404 struct radv_draw_info
{
3406 * Number of vertices.
3411 * Index of the first vertex.
3413 int32_t vertex_offset
;
3416 * First instance id.
3418 uint32_t first_instance
;
3421 * Number of instances.
3423 uint32_t instance_count
;
3426 * First index (indexed draws only).
3428 uint32_t first_index
;
3431 * Whether it's an indexed draw.
3436 * Indirect draw parameters resource.
3438 struct radv_buffer
*indirect
;
3439 uint64_t indirect_offset
;
3443 * Draw count parameters resource.
3445 struct radv_buffer
*count_buffer
;
3446 uint64_t count_buffer_offset
;
3449 * Stream output parameters resource.
3451 struct radv_buffer
*strmout_buffer
;
3452 uint64_t strmout_buffer_offset
;
3456 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3457 const struct radv_draw_info
*info
)
3459 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3460 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3461 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3463 if (info
->strmout_buffer
) {
3464 uint64_t va
= radv_buffer_get_va(info
->strmout_buffer
->bo
);
3466 va
+= info
->strmout_buffer
->offset
+
3467 info
->strmout_buffer_offset
;
3469 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
3472 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3473 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3474 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
3475 COPY_DATA_WR_CONFIRM
);
3476 radeon_emit(cs
, va
);
3477 radeon_emit(cs
, va
>> 32);
3478 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
3479 radeon_emit(cs
, 0); /* unused */
3481 radv_cs_add_buffer(ws
, cs
, info
->strmout_buffer
->bo
);
3484 if (info
->indirect
) {
3485 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3486 uint64_t count_va
= 0;
3488 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3490 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3492 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3494 radeon_emit(cs
, va
);
3495 radeon_emit(cs
, va
>> 32);
3497 if (info
->count_buffer
) {
3498 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3499 count_va
+= info
->count_buffer
->offset
+
3500 info
->count_buffer_offset
;
3502 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3505 if (!state
->subpass
->view_mask
) {
3506 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3513 for_each_bit(i
, state
->subpass
->view_mask
) {
3514 radv_emit_view_index(cmd_buffer
, i
);
3516 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3524 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3526 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3527 info
->first_instance
!= state
->last_first_instance
) {
3528 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3529 state
->pipeline
->graphics
.vtx_emit_num
);
3531 radeon_emit(cs
, info
->vertex_offset
);
3532 radeon_emit(cs
, info
->first_instance
);
3533 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3535 state
->last_first_instance
= info
->first_instance
;
3536 state
->last_vertex_offset
= info
->vertex_offset
;
3539 if (state
->last_num_instances
!= info
->instance_count
) {
3540 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3541 radeon_emit(cs
, info
->instance_count
);
3542 state
->last_num_instances
= info
->instance_count
;
3545 if (info
->indexed
) {
3546 int index_size
= state
->index_type
? 4 : 2;
3549 index_va
= state
->index_va
;
3550 index_va
+= info
->first_index
* index_size
;
3552 if (!state
->subpass
->view_mask
) {
3553 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3558 for_each_bit(i
, state
->subpass
->view_mask
) {
3559 radv_emit_view_index(cmd_buffer
, i
);
3561 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3567 if (!state
->subpass
->view_mask
) {
3568 radv_cs_emit_draw_packet(cmd_buffer
,
3570 !!info
->strmout_buffer
);
3573 for_each_bit(i
, state
->subpass
->view_mask
) {
3574 radv_emit_view_index(cmd_buffer
, i
);
3576 radv_cs_emit_draw_packet(cmd_buffer
,
3578 !!info
->strmout_buffer
);
3586 * Vega and raven have a bug which triggers if there are multiple context
3587 * register contexts active at the same time with different scissor values.
3589 * There are two possible workarounds:
3590 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3591 * there is only ever 1 active set of scissor values at the same time.
3593 * 2) Whenever the hardware switches contexts we have to set the scissor
3594 * registers again even if it is a noop. That way the new context gets
3595 * the correct scissor values.
3597 * This implements option 2. radv_need_late_scissor_emission needs to
3598 * return true on affected HW if radv_emit_all_graphics_states sets
3599 * any context registers.
3601 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3604 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3606 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3609 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3611 /* Index, vertex and streamout buffers don't change context regs, and
3612 * pipeline is handled later.
3614 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
3615 RADV_CMD_DIRTY_VERTEX_BUFFER
|
3616 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
3617 RADV_CMD_DIRTY_PIPELINE
);
3619 /* Assume all state changes except these two can imply context rolls. */
3620 if (cmd_buffer
->state
.dirty
& used_states
)
3623 if (cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3626 if (indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3627 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3634 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3635 const struct radv_draw_info
*info
)
3637 bool late_scissor_emission
= radv_need_late_scissor_emission(cmd_buffer
, info
->indexed
);
3639 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3640 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3641 radv_emit_rbplus_state(cmd_buffer
);
3643 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3644 radv_emit_graphics_pipeline(cmd_buffer
);
3646 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3647 radv_emit_framebuffer_state(cmd_buffer
);
3649 if (info
->indexed
) {
3650 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3651 radv_emit_index_buffer(cmd_buffer
);
3653 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3654 * so the state must be re-emitted before the next indexed
3657 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3658 cmd_buffer
->state
.last_index_type
= -1;
3659 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3663 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3665 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3666 info
->instance_count
> 1, info
->indirect
,
3667 info
->indirect
? 0 : info
->count
);
3669 if (late_scissor_emission
)
3670 radv_emit_scissor(cmd_buffer
);
3674 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3675 const struct radv_draw_info
*info
)
3677 struct radeon_info
*rad_info
=
3678 &cmd_buffer
->device
->physical_device
->rad_info
;
3680 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3681 bool pipeline_is_dirty
=
3682 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3683 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3685 MAYBE_UNUSED
unsigned cdw_max
=
3686 radeon_check_space(cmd_buffer
->device
->ws
,
3687 cmd_buffer
->cs
, 4096);
3689 /* Use optimal packet order based on whether we need to sync the
3692 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3693 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3694 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3695 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3696 /* If we have to wait for idle, set all states first, so that
3697 * all SET packets are processed in parallel with previous draw
3698 * calls. Then upload descriptors, set shader pointers, and
3699 * draw, and prefetch at the end. This ensures that the time
3700 * the CUs are idle is very short. (there are only SET_SH
3701 * packets between the wait and the draw)
3703 radv_emit_all_graphics_states(cmd_buffer
, info
);
3704 si_emit_cache_flush(cmd_buffer
);
3705 /* <-- CUs are idle here --> */
3707 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3709 radv_emit_draw_packets(cmd_buffer
, info
);
3710 /* <-- CUs are busy here --> */
3712 /* Start prefetches after the draw has been started. Both will
3713 * run in parallel, but starting the draw first is more
3716 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3717 radv_emit_prefetch_L2(cmd_buffer
,
3718 cmd_buffer
->state
.pipeline
, false);
3721 /* If we don't wait for idle, start prefetches first, then set
3722 * states, and draw at the end.
3724 si_emit_cache_flush(cmd_buffer
);
3726 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3727 /* Only prefetch the vertex shader and VBO descriptors
3728 * in order to start the draw as soon as possible.
3730 radv_emit_prefetch_L2(cmd_buffer
,
3731 cmd_buffer
->state
.pipeline
, true);
3734 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3736 radv_emit_all_graphics_states(cmd_buffer
, info
);
3737 radv_emit_draw_packets(cmd_buffer
, info
);
3739 /* Prefetch the remaining shaders after the draw has been
3742 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3743 radv_emit_prefetch_L2(cmd_buffer
,
3744 cmd_buffer
->state
.pipeline
, false);
3748 /* Workaround for a VGT hang when streamout is enabled.
3749 * It must be done after drawing.
3751 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
3752 (rad_info
->family
== CHIP_HAWAII
||
3753 rad_info
->family
== CHIP_TONGA
||
3754 rad_info
->family
== CHIP_FIJI
)) {
3755 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
3758 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3759 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3763 VkCommandBuffer commandBuffer
,
3764 uint32_t vertexCount
,
3765 uint32_t instanceCount
,
3766 uint32_t firstVertex
,
3767 uint32_t firstInstance
)
3769 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3770 struct radv_draw_info info
= {};
3772 info
.count
= vertexCount
;
3773 info
.instance_count
= instanceCount
;
3774 info
.first_instance
= firstInstance
;
3775 info
.vertex_offset
= firstVertex
;
3777 radv_draw(cmd_buffer
, &info
);
3780 void radv_CmdDrawIndexed(
3781 VkCommandBuffer commandBuffer
,
3782 uint32_t indexCount
,
3783 uint32_t instanceCount
,
3784 uint32_t firstIndex
,
3785 int32_t vertexOffset
,
3786 uint32_t firstInstance
)
3788 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3789 struct radv_draw_info info
= {};
3791 info
.indexed
= true;
3792 info
.count
= indexCount
;
3793 info
.instance_count
= instanceCount
;
3794 info
.first_index
= firstIndex
;
3795 info
.vertex_offset
= vertexOffset
;
3796 info
.first_instance
= firstInstance
;
3798 radv_draw(cmd_buffer
, &info
);
3801 void radv_CmdDrawIndirect(
3802 VkCommandBuffer commandBuffer
,
3804 VkDeviceSize offset
,
3808 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3809 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3810 struct radv_draw_info info
= {};
3812 info
.count
= drawCount
;
3813 info
.indirect
= buffer
;
3814 info
.indirect_offset
= offset
;
3815 info
.stride
= stride
;
3817 radv_draw(cmd_buffer
, &info
);
3820 void radv_CmdDrawIndexedIndirect(
3821 VkCommandBuffer commandBuffer
,
3823 VkDeviceSize offset
,
3827 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3828 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3829 struct radv_draw_info info
= {};
3831 info
.indexed
= true;
3832 info
.count
= drawCount
;
3833 info
.indirect
= buffer
;
3834 info
.indirect_offset
= offset
;
3835 info
.stride
= stride
;
3837 radv_draw(cmd_buffer
, &info
);
3840 void radv_CmdDrawIndirectCountAMD(
3841 VkCommandBuffer commandBuffer
,
3843 VkDeviceSize offset
,
3844 VkBuffer _countBuffer
,
3845 VkDeviceSize countBufferOffset
,
3846 uint32_t maxDrawCount
,
3849 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3850 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3851 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3852 struct radv_draw_info info
= {};
3854 info
.count
= maxDrawCount
;
3855 info
.indirect
= buffer
;
3856 info
.indirect_offset
= offset
;
3857 info
.count_buffer
= count_buffer
;
3858 info
.count_buffer_offset
= countBufferOffset
;
3859 info
.stride
= stride
;
3861 radv_draw(cmd_buffer
, &info
);
3864 void radv_CmdDrawIndexedIndirectCountAMD(
3865 VkCommandBuffer commandBuffer
,
3867 VkDeviceSize offset
,
3868 VkBuffer _countBuffer
,
3869 VkDeviceSize countBufferOffset
,
3870 uint32_t maxDrawCount
,
3873 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3874 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3875 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3876 struct radv_draw_info info
= {};
3878 info
.indexed
= true;
3879 info
.count
= maxDrawCount
;
3880 info
.indirect
= buffer
;
3881 info
.indirect_offset
= offset
;
3882 info
.count_buffer
= count_buffer
;
3883 info
.count_buffer_offset
= countBufferOffset
;
3884 info
.stride
= stride
;
3886 radv_draw(cmd_buffer
, &info
);
3889 void radv_CmdDrawIndirectCountKHR(
3890 VkCommandBuffer commandBuffer
,
3892 VkDeviceSize offset
,
3893 VkBuffer _countBuffer
,
3894 VkDeviceSize countBufferOffset
,
3895 uint32_t maxDrawCount
,
3898 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3899 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3900 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3901 struct radv_draw_info info
= {};
3903 info
.count
= maxDrawCount
;
3904 info
.indirect
= buffer
;
3905 info
.indirect_offset
= offset
;
3906 info
.count_buffer
= count_buffer
;
3907 info
.count_buffer_offset
= countBufferOffset
;
3908 info
.stride
= stride
;
3910 radv_draw(cmd_buffer
, &info
);
3913 void radv_CmdDrawIndexedIndirectCountKHR(
3914 VkCommandBuffer commandBuffer
,
3916 VkDeviceSize offset
,
3917 VkBuffer _countBuffer
,
3918 VkDeviceSize countBufferOffset
,
3919 uint32_t maxDrawCount
,
3922 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3923 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3924 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3925 struct radv_draw_info info
= {};
3927 info
.indexed
= true;
3928 info
.count
= maxDrawCount
;
3929 info
.indirect
= buffer
;
3930 info
.indirect_offset
= offset
;
3931 info
.count_buffer
= count_buffer
;
3932 info
.count_buffer_offset
= countBufferOffset
;
3933 info
.stride
= stride
;
3935 radv_draw(cmd_buffer
, &info
);
3938 struct radv_dispatch_info
{
3940 * Determine the layout of the grid (in block units) to be used.
3945 * A starting offset for the grid. If unaligned is set, the offset
3946 * must still be aligned.
3948 uint32_t offsets
[3];
3950 * Whether it's an unaligned compute dispatch.
3955 * Indirect compute parameters resource.
3957 struct radv_buffer
*indirect
;
3958 uint64_t indirect_offset
;
3962 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3963 const struct radv_dispatch_info
*info
)
3965 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3966 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3967 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3968 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3969 bool predicating
= cmd_buffer
->state
.predicating
;
3970 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3971 struct radv_userdata_info
*loc
;
3973 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3974 AC_UD_CS_GRID_SIZE
);
3976 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3978 if (info
->indirect
) {
3979 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3981 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3983 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3985 if (loc
->sgpr_idx
!= -1) {
3986 for (unsigned i
= 0; i
< 3; ++i
) {
3987 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3988 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3989 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3990 radeon_emit(cs
, (va
+ 4 * i
));
3991 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3992 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3993 + loc
->sgpr_idx
* 4) >> 2) + i
);
3998 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3999 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4000 PKT3_SHADER_TYPE_S(1));
4001 radeon_emit(cs
, va
);
4002 radeon_emit(cs
, va
>> 32);
4003 radeon_emit(cs
, dispatch_initiator
);
4005 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4006 PKT3_SHADER_TYPE_S(1));
4008 radeon_emit(cs
, va
);
4009 radeon_emit(cs
, va
>> 32);
4011 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4012 PKT3_SHADER_TYPE_S(1));
4014 radeon_emit(cs
, dispatch_initiator
);
4017 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4018 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4020 if (info
->unaligned
) {
4021 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4022 unsigned remainder
[3];
4024 /* If aligned, these should be an entire block size,
4027 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4028 align_u32_npot(blocks
[0], cs_block_size
[0]);
4029 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4030 align_u32_npot(blocks
[1], cs_block_size
[1]);
4031 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4032 align_u32_npot(blocks
[2], cs_block_size
[2]);
4034 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4035 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4036 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4038 for(unsigned i
= 0; i
< 3; ++i
) {
4039 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4040 offsets
[i
] /= cs_block_size
[i
];
4043 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4045 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4046 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4048 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4049 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4051 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4052 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4054 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4057 if (loc
->sgpr_idx
!= -1) {
4058 assert(!loc
->indirect
);
4059 assert(loc
->num_sgprs
== 3);
4061 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4062 loc
->sgpr_idx
* 4, 3);
4063 radeon_emit(cs
, blocks
[0]);
4064 radeon_emit(cs
, blocks
[1]);
4065 radeon_emit(cs
, blocks
[2]);
4068 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4069 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4070 radeon_emit(cs
, offsets
[0]);
4071 radeon_emit(cs
, offsets
[1]);
4072 radeon_emit(cs
, offsets
[2]);
4074 /* The blocks in the packet are not counts but end values. */
4075 for (unsigned i
= 0; i
< 3; ++i
)
4076 blocks
[i
] += offsets
[i
];
4078 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4081 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4082 PKT3_SHADER_TYPE_S(1));
4083 radeon_emit(cs
, blocks
[0]);
4084 radeon_emit(cs
, blocks
[1]);
4085 radeon_emit(cs
, blocks
[2]);
4086 radeon_emit(cs
, dispatch_initiator
);
4089 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4093 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4095 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4096 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4100 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4101 const struct radv_dispatch_info
*info
)
4103 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4105 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
4106 bool pipeline_is_dirty
= pipeline
&&
4107 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4109 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4110 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4111 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4112 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4113 /* If we have to wait for idle, set all states first, so that
4114 * all SET packets are processed in parallel with previous draw
4115 * calls. Then upload descriptors, set shader pointers, and
4116 * dispatch, and prefetch at the end. This ensures that the
4117 * time the CUs are idle is very short. (there are only SET_SH
4118 * packets between the wait and the draw)
4120 radv_emit_compute_pipeline(cmd_buffer
);
4121 si_emit_cache_flush(cmd_buffer
);
4122 /* <-- CUs are idle here --> */
4124 radv_upload_compute_shader_descriptors(cmd_buffer
);
4126 radv_emit_dispatch_packets(cmd_buffer
, info
);
4127 /* <-- CUs are busy here --> */
4129 /* Start prefetches after the dispatch has been started. Both
4130 * will run in parallel, but starting the dispatch first is
4133 if (has_prefetch
&& pipeline_is_dirty
) {
4134 radv_emit_shader_prefetch(cmd_buffer
,
4135 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4138 /* If we don't wait for idle, start prefetches first, then set
4139 * states, and dispatch at the end.
4141 si_emit_cache_flush(cmd_buffer
);
4143 if (has_prefetch
&& pipeline_is_dirty
) {
4144 radv_emit_shader_prefetch(cmd_buffer
,
4145 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4148 radv_upload_compute_shader_descriptors(cmd_buffer
);
4150 radv_emit_compute_pipeline(cmd_buffer
);
4151 radv_emit_dispatch_packets(cmd_buffer
, info
);
4154 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4157 void radv_CmdDispatchBase(
4158 VkCommandBuffer commandBuffer
,
4166 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4167 struct radv_dispatch_info info
= {};
4173 info
.offsets
[0] = base_x
;
4174 info
.offsets
[1] = base_y
;
4175 info
.offsets
[2] = base_z
;
4176 radv_dispatch(cmd_buffer
, &info
);
4179 void radv_CmdDispatch(
4180 VkCommandBuffer commandBuffer
,
4185 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4188 void radv_CmdDispatchIndirect(
4189 VkCommandBuffer commandBuffer
,
4191 VkDeviceSize offset
)
4193 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4194 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4195 struct radv_dispatch_info info
= {};
4197 info
.indirect
= buffer
;
4198 info
.indirect_offset
= offset
;
4200 radv_dispatch(cmd_buffer
, &info
);
4203 void radv_unaligned_dispatch(
4204 struct radv_cmd_buffer
*cmd_buffer
,
4209 struct radv_dispatch_info info
= {};
4216 radv_dispatch(cmd_buffer
, &info
);
4219 void radv_CmdEndRenderPass(
4220 VkCommandBuffer commandBuffer
)
4222 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4224 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4226 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4228 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
4229 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
4230 radv_handle_subpass_image_transition(cmd_buffer
,
4231 (struct radv_subpass_attachment
){i
, layout
});
4234 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4236 cmd_buffer
->state
.pass
= NULL
;
4237 cmd_buffer
->state
.subpass
= NULL
;
4238 cmd_buffer
->state
.attachments
= NULL
;
4239 cmd_buffer
->state
.framebuffer
= NULL
;
4242 void radv_CmdEndRenderPass2KHR(
4243 VkCommandBuffer commandBuffer
,
4244 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4246 radv_CmdEndRenderPass(commandBuffer
);
4250 * For HTILE we have the following interesting clear words:
4251 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4252 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4253 * 0xfffffff0: Clear depth to 1.0
4254 * 0x00000000: Clear depth to 0.0
4256 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4257 struct radv_image
*image
,
4258 const VkImageSubresourceRange
*range
,
4259 uint32_t clear_word
)
4261 assert(range
->baseMipLevel
== 0);
4262 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4263 unsigned layer_count
= radv_get_layerCount(image
, range
);
4264 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
4265 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4266 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4267 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4268 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4269 VkClearDepthStencilValue value
= {};
4271 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4272 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4274 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4277 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4279 if (vk_format_is_stencil(image
->vk_format
))
4280 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4282 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4284 if (radv_image_is_tc_compat_htile(image
)) {
4285 /* Initialize the TC-compat metada value to 0 because by
4286 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4287 * need have to conditionally update its value when performing
4288 * a fast depth clear.
4290 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4294 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4295 struct radv_image
*image
,
4296 VkImageLayout src_layout
,
4297 VkImageLayout dst_layout
,
4298 unsigned src_queue_mask
,
4299 unsigned dst_queue_mask
,
4300 const VkImageSubresourceRange
*range
)
4302 if (!radv_image_has_htile(image
))
4305 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4306 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4307 /* TODO: merge with the clear if applicable */
4308 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4309 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4310 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4311 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4312 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4313 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4314 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4315 VkImageSubresourceRange local_range
= *range
;
4316 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4317 local_range
.baseMipLevel
= 0;
4318 local_range
.levelCount
= 1;
4320 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4321 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4323 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4325 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4326 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4330 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4331 struct radv_image
*image
, uint32_t value
)
4333 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4335 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4336 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4338 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4340 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4343 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4344 struct radv_image
*image
, uint32_t value
)
4346 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4348 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4349 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4351 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4353 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4354 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4358 * Initialize DCC/FMASK/CMASK metadata for a color image.
4360 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4361 struct radv_image
*image
,
4362 VkImageLayout src_layout
,
4363 VkImageLayout dst_layout
,
4364 unsigned src_queue_mask
,
4365 unsigned dst_queue_mask
)
4367 if (radv_image_has_cmask(image
)) {
4368 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4370 /* TODO: clarify this. */
4371 if (radv_image_has_fmask(image
)) {
4372 value
= 0xccccccccu
;
4375 radv_initialise_cmask(cmd_buffer
, image
, value
);
4378 if (radv_image_has_dcc(image
)) {
4379 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4380 bool need_decompress_pass
= false;
4382 if (radv_layout_dcc_compressed(image
, dst_layout
,
4384 value
= 0x20202020u
;
4385 need_decompress_pass
= true;
4388 radv_initialize_dcc(cmd_buffer
, image
, value
);
4390 radv_update_fce_metadata(cmd_buffer
, image
,
4391 need_decompress_pass
);
4394 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4395 uint32_t color_values
[2] = {};
4396 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4401 * Handle color image transitions for DCC/FMASK/CMASK.
4403 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4404 struct radv_image
*image
,
4405 VkImageLayout src_layout
,
4406 VkImageLayout dst_layout
,
4407 unsigned src_queue_mask
,
4408 unsigned dst_queue_mask
,
4409 const VkImageSubresourceRange
*range
)
4411 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4412 radv_init_color_image_metadata(cmd_buffer
, image
,
4413 src_layout
, dst_layout
,
4414 src_queue_mask
, dst_queue_mask
);
4418 if (radv_image_has_dcc(image
)) {
4419 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4420 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4421 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4422 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4423 radv_decompress_dcc(cmd_buffer
, image
, range
);
4424 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4425 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4426 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4428 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4429 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4430 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4431 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4436 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4437 struct radv_image
*image
,
4438 VkImageLayout src_layout
,
4439 VkImageLayout dst_layout
,
4440 uint32_t src_family
,
4441 uint32_t dst_family
,
4442 const VkImageSubresourceRange
*range
)
4444 if (image
->exclusive
&& src_family
!= dst_family
) {
4445 /* This is an acquire or a release operation and there will be
4446 * a corresponding release/acquire. Do the transition in the
4447 * most flexible queue. */
4449 assert(src_family
== cmd_buffer
->queue_family_index
||
4450 dst_family
== cmd_buffer
->queue_family_index
);
4452 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4455 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4456 (src_family
== RADV_QUEUE_GENERAL
||
4457 dst_family
== RADV_QUEUE_GENERAL
))
4461 unsigned src_queue_mask
=
4462 radv_image_queue_family_mask(image
, src_family
,
4463 cmd_buffer
->queue_family_index
);
4464 unsigned dst_queue_mask
=
4465 radv_image_queue_family_mask(image
, dst_family
,
4466 cmd_buffer
->queue_family_index
);
4468 if (vk_format_is_depth(image
->vk_format
)) {
4469 radv_handle_depth_image_transition(cmd_buffer
, image
,
4470 src_layout
, dst_layout
,
4471 src_queue_mask
, dst_queue_mask
,
4474 radv_handle_color_image_transition(cmd_buffer
, image
,
4475 src_layout
, dst_layout
,
4476 src_queue_mask
, dst_queue_mask
,
4481 struct radv_barrier_info
{
4482 uint32_t eventCount
;
4483 const VkEvent
*pEvents
;
4484 VkPipelineStageFlags srcStageMask
;
4488 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4489 uint32_t memoryBarrierCount
,
4490 const VkMemoryBarrier
*pMemoryBarriers
,
4491 uint32_t bufferMemoryBarrierCount
,
4492 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4493 uint32_t imageMemoryBarrierCount
,
4494 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4495 const struct radv_barrier_info
*info
)
4497 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4498 enum radv_cmd_flush_bits src_flush_bits
= 0;
4499 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4501 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4502 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4503 uint64_t va
= radv_buffer_get_va(event
->bo
);
4505 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4507 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4509 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4510 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4513 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4514 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4516 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4520 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4521 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4523 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4527 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4528 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4530 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4532 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4536 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4537 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4539 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4540 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4541 radv_handle_image_transition(cmd_buffer
, image
,
4542 pImageMemoryBarriers
[i
].oldLayout
,
4543 pImageMemoryBarriers
[i
].newLayout
,
4544 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4545 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4546 &pImageMemoryBarriers
[i
].subresourceRange
);
4549 /* Make sure CP DMA is idle because the driver might have performed a
4550 * DMA operation for copying or filling buffers/images.
4552 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4553 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4554 si_cp_dma_wait_for_idle(cmd_buffer
);
4556 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4559 void radv_CmdPipelineBarrier(
4560 VkCommandBuffer commandBuffer
,
4561 VkPipelineStageFlags srcStageMask
,
4562 VkPipelineStageFlags destStageMask
,
4564 uint32_t memoryBarrierCount
,
4565 const VkMemoryBarrier
* pMemoryBarriers
,
4566 uint32_t bufferMemoryBarrierCount
,
4567 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4568 uint32_t imageMemoryBarrierCount
,
4569 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4571 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4572 struct radv_barrier_info info
;
4574 info
.eventCount
= 0;
4575 info
.pEvents
= NULL
;
4576 info
.srcStageMask
= srcStageMask
;
4578 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4579 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4580 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4584 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4585 struct radv_event
*event
,
4586 VkPipelineStageFlags stageMask
,
4589 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4590 uint64_t va
= radv_buffer_get_va(event
->bo
);
4592 si_emit_cache_flush(cmd_buffer
);
4594 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4596 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4598 /* Flags that only require a top-of-pipe event. */
4599 VkPipelineStageFlags top_of_pipe_flags
=
4600 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4602 /* Flags that only require a post-index-fetch event. */
4603 VkPipelineStageFlags post_index_fetch_flags
=
4605 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4606 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4608 /* Make sure CP DMA is idle because the driver might have performed a
4609 * DMA operation for copying or filling buffers/images.
4611 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4612 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4613 si_cp_dma_wait_for_idle(cmd_buffer
);
4615 /* TODO: Emit EOS events for syncing PS/CS stages. */
4617 if (!(stageMask
& ~top_of_pipe_flags
)) {
4618 /* Just need to sync the PFP engine. */
4619 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4620 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4621 S_370_WR_CONFIRM(1) |
4622 S_370_ENGINE_SEL(V_370_PFP
));
4623 radeon_emit(cs
, va
);
4624 radeon_emit(cs
, va
>> 32);
4625 radeon_emit(cs
, value
);
4626 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4627 /* Sync ME because PFP reads index and indirect buffers. */
4628 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4629 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4630 S_370_WR_CONFIRM(1) |
4631 S_370_ENGINE_SEL(V_370_ME
));
4632 radeon_emit(cs
, va
);
4633 radeon_emit(cs
, va
>> 32);
4634 radeon_emit(cs
, value
);
4636 /* Otherwise, sync all prior GPU work using an EOP event. */
4637 si_cs_emit_write_event_eop(cs
,
4638 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4639 radv_cmd_buffer_uses_mec(cmd_buffer
),
4640 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4641 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4642 cmd_buffer
->gfx9_eop_bug_va
);
4645 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4648 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4650 VkPipelineStageFlags stageMask
)
4652 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4653 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4655 write_event(cmd_buffer
, event
, stageMask
, 1);
4658 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4660 VkPipelineStageFlags stageMask
)
4662 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4663 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4665 write_event(cmd_buffer
, event
, stageMask
, 0);
4668 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4669 uint32_t eventCount
,
4670 const VkEvent
* pEvents
,
4671 VkPipelineStageFlags srcStageMask
,
4672 VkPipelineStageFlags dstStageMask
,
4673 uint32_t memoryBarrierCount
,
4674 const VkMemoryBarrier
* pMemoryBarriers
,
4675 uint32_t bufferMemoryBarrierCount
,
4676 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4677 uint32_t imageMemoryBarrierCount
,
4678 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4680 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4681 struct radv_barrier_info info
;
4683 info
.eventCount
= eventCount
;
4684 info
.pEvents
= pEvents
;
4685 info
.srcStageMask
= 0;
4687 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4688 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4689 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4693 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4694 uint32_t deviceMask
)
4699 /* VK_EXT_conditional_rendering */
4700 void radv_CmdBeginConditionalRenderingEXT(
4701 VkCommandBuffer commandBuffer
,
4702 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4704 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4705 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4706 bool draw_visible
= true;
4709 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
4711 /* By default, if the 32-bit value at offset in buffer memory is zero,
4712 * then the rendering commands are discarded, otherwise they are
4713 * executed as normal. If the inverted flag is set, all commands are
4714 * discarded if the value is non zero.
4716 if (pConditionalRenderingBegin
->flags
&
4717 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
4718 draw_visible
= false;
4721 /* Enable predication for this command buffer. */
4722 si_emit_set_predication_state(cmd_buffer
, draw_visible
, va
);
4723 cmd_buffer
->state
.predicating
= true;
4725 /* Store conditional rendering user info. */
4726 cmd_buffer
->state
.predication_type
= draw_visible
;
4727 cmd_buffer
->state
.predication_va
= va
;
4730 void radv_CmdEndConditionalRenderingEXT(
4731 VkCommandBuffer commandBuffer
)
4733 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4735 /* Disable predication for this command buffer. */
4736 si_emit_set_predication_state(cmd_buffer
, false, 0);
4737 cmd_buffer
->state
.predicating
= false;
4739 /* Reset conditional rendering user info. */
4740 cmd_buffer
->state
.predication_type
= -1;
4741 cmd_buffer
->state
.predication_va
= 0;
4744 /* VK_EXT_transform_feedback */
4745 void radv_CmdBindTransformFeedbackBuffersEXT(
4746 VkCommandBuffer commandBuffer
,
4747 uint32_t firstBinding
,
4748 uint32_t bindingCount
,
4749 const VkBuffer
* pBuffers
,
4750 const VkDeviceSize
* pOffsets
,
4751 const VkDeviceSize
* pSizes
)
4753 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4754 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4755 uint8_t enabled_mask
= 0;
4757 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
4758 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
4759 uint32_t idx
= firstBinding
+ i
;
4761 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
4762 sb
[idx
].offset
= pOffsets
[i
];
4763 sb
[idx
].size
= pSizes
[i
];
4765 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4766 sb
[idx
].buffer
->bo
);
4768 enabled_mask
|= 1 << idx
;
4771 cmd_buffer
->state
.streamout
.enabled_mask
= enabled_mask
;
4773 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
4777 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
4779 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4780 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4782 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
4784 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
4785 S_028B94_RAST_STREAM(0) |
4786 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
4787 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
4788 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
4789 radeon_emit(cs
, so
->hw_enabled_mask
&
4790 so
->enabled_stream_buffers_mask
);
4794 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
4796 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4797 bool old_streamout_enabled
= so
->streamout_enabled
;
4798 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
4800 so
->streamout_enabled
= enable
;
4802 so
->hw_enabled_mask
= so
->enabled_mask
|
4803 (so
->enabled_mask
<< 4) |
4804 (so
->enabled_mask
<< 8) |
4805 (so
->enabled_mask
<< 12);
4807 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
4808 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
4809 radv_emit_streamout_enable(cmd_buffer
);
4812 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
4814 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4815 unsigned reg_strmout_cntl
;
4817 /* The register is at different places on different ASICs. */
4818 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4819 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
4820 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
4822 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
4823 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
4826 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4827 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
4829 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
4830 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
4831 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
4833 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4834 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4835 radeon_emit(cs
, 4); /* poll interval */
4838 void radv_CmdBeginTransformFeedbackEXT(
4839 VkCommandBuffer commandBuffer
,
4840 uint32_t firstCounterBuffer
,
4841 uint32_t counterBufferCount
,
4842 const VkBuffer
* pCounterBuffers
,
4843 const VkDeviceSize
* pCounterBufferOffsets
)
4845 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4846 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4847 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4848 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4851 radv_flush_vgt_streamout(cmd_buffer
);
4853 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4854 for_each_bit(i
, so
->enabled_mask
) {
4855 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4856 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
4857 counter_buffer_idx
= -1;
4859 /* SI binds streamout buffers as shader resources.
4860 * VGT only counts primitives and tells the shader through
4863 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
4864 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
4865 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
4867 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4868 /* The array of counter buffers is optional. */
4869 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4870 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4872 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4875 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4876 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4877 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4878 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
4879 radeon_emit(cs
, 0); /* unused */
4880 radeon_emit(cs
, 0); /* unused */
4881 radeon_emit(cs
, va
); /* src address lo */
4882 radeon_emit(cs
, va
>> 32); /* src address hi */
4884 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4886 /* Start from the beginning. */
4887 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4888 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4889 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4890 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
4891 radeon_emit(cs
, 0); /* unused */
4892 radeon_emit(cs
, 0); /* unused */
4893 radeon_emit(cs
, 0); /* unused */
4894 radeon_emit(cs
, 0); /* unused */
4898 radv_set_streamout_enable(cmd_buffer
, true);
4901 void radv_CmdEndTransformFeedbackEXT(
4902 VkCommandBuffer commandBuffer
,
4903 uint32_t firstCounterBuffer
,
4904 uint32_t counterBufferCount
,
4905 const VkBuffer
* pCounterBuffers
,
4906 const VkDeviceSize
* pCounterBufferOffsets
)
4908 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4909 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4910 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4913 radv_flush_vgt_streamout(cmd_buffer
);
4915 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4916 for_each_bit(i
, so
->enabled_mask
) {
4917 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4918 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
4919 counter_buffer_idx
= -1;
4921 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4922 /* The array of counters buffer is optional. */
4923 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4924 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4926 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4928 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4929 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4930 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4931 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
4932 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
4933 radeon_emit(cs
, va
); /* dst address lo */
4934 radeon_emit(cs
, va
>> 32); /* dst address hi */
4935 radeon_emit(cs
, 0); /* unused */
4936 radeon_emit(cs
, 0); /* unused */
4938 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4941 /* Deactivate transform feedback by zeroing the buffer size.
4942 * The counters (primitives generated, primitives emitted) may
4943 * be enabled even if there is not buffer bound. This ensures
4944 * that the primitives-emitted query won't increment.
4946 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
4949 radv_set_streamout_enable(cmd_buffer
, false);
4952 void radv_CmdDrawIndirectByteCountEXT(
4953 VkCommandBuffer commandBuffer
,
4954 uint32_t instanceCount
,
4955 uint32_t firstInstance
,
4956 VkBuffer _counterBuffer
,
4957 VkDeviceSize counterBufferOffset
,
4958 uint32_t counterOffset
,
4959 uint32_t vertexStride
)
4961 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4962 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
4963 struct radv_draw_info info
= {};
4965 info
.instance_count
= instanceCount
;
4966 info
.first_instance
= firstInstance
;
4967 info
.strmout_buffer
= counterBuffer
;
4968 info
.strmout_buffer_offset
= counterBufferOffset
;
4969 info
.stride
= vertexStride
;
4971 radv_draw(cmd_buffer
, &info
);