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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108 dest->sample_location.count = src->sample_location.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
197 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
198 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
199 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
200 memcmp(&dest->sample_location.locations,
201 &src->sample_location.locations,
202 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
203 dest->sample_location.per_pixel = src->sample_location.per_pixel;
204 dest->sample_location.grid_size = src->sample_location.grid_size;
205 typed_memcpy(dest->sample_location.locations,
206 src->sample_location.locations,
207 src->sample_location.count);
208 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
209 }
210 }
211
212 cmd_buffer->state.dirty |= dest_mask;
213 }
214
215 static void
216 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
217 struct radv_pipeline *pipeline)
218 {
219 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
220 struct radv_shader_info *info;
221
222 if (!pipeline->streamout_shader)
223 return;
224
225 info = &pipeline->streamout_shader->info.info;
226 for (int i = 0; i < MAX_SO_BUFFERS; i++)
227 so->stride_in_dw[i] = info->so.strides[i];
228
229 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
230 }
231
232 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
233 {
234 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
235 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
236 }
237
238 enum ring_type radv_queue_family_to_ring(int f) {
239 switch (f) {
240 case RADV_QUEUE_GENERAL:
241 return RING_GFX;
242 case RADV_QUEUE_COMPUTE:
243 return RING_COMPUTE;
244 case RADV_QUEUE_TRANSFER:
245 return RING_DMA;
246 default:
247 unreachable("Unknown queue family");
248 }
249 }
250
251 static VkResult radv_create_cmd_buffer(
252 struct radv_device * device,
253 struct radv_cmd_pool * pool,
254 VkCommandBufferLevel level,
255 VkCommandBuffer* pCommandBuffer)
256 {
257 struct radv_cmd_buffer *cmd_buffer;
258 unsigned ring;
259 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
260 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
261 if (cmd_buffer == NULL)
262 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
263
264 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
265 cmd_buffer->device = device;
266 cmd_buffer->pool = pool;
267 cmd_buffer->level = level;
268
269 if (pool) {
270 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
271 cmd_buffer->queue_family_index = pool->queue_family_index;
272
273 } else {
274 /* Init the pool_link so we can safely call list_del when we destroy
275 * the command buffer
276 */
277 list_inithead(&cmd_buffer->pool_link);
278 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
279 }
280
281 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
282
283 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
284 if (!cmd_buffer->cs) {
285 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
286 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
287 }
288
289 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
290
291 list_inithead(&cmd_buffer->upload.list);
292
293 return VK_SUCCESS;
294 }
295
296 static void
297 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
298 {
299 list_del(&cmd_buffer->pool_link);
300
301 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
302 &cmd_buffer->upload.list, list) {
303 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
304 list_del(&up->list);
305 free(up);
306 }
307
308 if (cmd_buffer->upload.upload_bo)
309 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
310 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
311
312 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
313 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
314
315 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
316 }
317
318 static VkResult
319 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
320 {
321 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
322
323 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
324 &cmd_buffer->upload.list, list) {
325 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
326 list_del(&up->list);
327 free(up);
328 }
329
330 cmd_buffer->push_constant_stages = 0;
331 cmd_buffer->scratch_size_needed = 0;
332 cmd_buffer->compute_scratch_size_needed = 0;
333 cmd_buffer->esgs_ring_size_needed = 0;
334 cmd_buffer->gsvs_ring_size_needed = 0;
335 cmd_buffer->tess_rings_needed = false;
336 cmd_buffer->sample_positions_needed = false;
337
338 if (cmd_buffer->upload.upload_bo)
339 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
340 cmd_buffer->upload.upload_bo);
341 cmd_buffer->upload.offset = 0;
342
343 cmd_buffer->record_result = VK_SUCCESS;
344
345 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
346
347 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
348 cmd_buffer->descriptors[i].dirty = 0;
349 cmd_buffer->descriptors[i].valid = 0;
350 cmd_buffer->descriptors[i].push_dirty = false;
351 }
352
353 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
354 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
355 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
356 unsigned fence_offset, eop_bug_offset;
357 void *fence_ptr;
358
359 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
360 &fence_ptr);
361
362 cmd_buffer->gfx9_fence_va =
363 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
364 cmd_buffer->gfx9_fence_va += fence_offset;
365
366 /* Allocate a buffer for the EOP bug on GFX9. */
367 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
368 &eop_bug_offset, &fence_ptr);
369 cmd_buffer->gfx9_eop_bug_va =
370 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
371 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
372 }
373
374 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
375
376 return cmd_buffer->record_result;
377 }
378
379 static bool
380 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
381 uint64_t min_needed)
382 {
383 uint64_t new_size;
384 struct radeon_winsys_bo *bo;
385 struct radv_cmd_buffer_upload *upload;
386 struct radv_device *device = cmd_buffer->device;
387
388 new_size = MAX2(min_needed, 16 * 1024);
389 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
390
391 bo = device->ws->buffer_create(device->ws,
392 new_size, 4096,
393 RADEON_DOMAIN_GTT,
394 RADEON_FLAG_CPU_ACCESS|
395 RADEON_FLAG_NO_INTERPROCESS_SHARING |
396 RADEON_FLAG_32BIT,
397 RADV_BO_PRIORITY_UPLOAD_BUFFER);
398
399 if (!bo) {
400 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
401 return false;
402 }
403
404 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
405 if (cmd_buffer->upload.upload_bo) {
406 upload = malloc(sizeof(*upload));
407
408 if (!upload) {
409 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
410 device->ws->buffer_destroy(bo);
411 return false;
412 }
413
414 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
415 list_add(&upload->list, &cmd_buffer->upload.list);
416 }
417
418 cmd_buffer->upload.upload_bo = bo;
419 cmd_buffer->upload.size = new_size;
420 cmd_buffer->upload.offset = 0;
421 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
422
423 if (!cmd_buffer->upload.map) {
424 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
425 return false;
426 }
427
428 return true;
429 }
430
431 bool
432 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
433 unsigned size,
434 unsigned alignment,
435 unsigned *out_offset,
436 void **ptr)
437 {
438 assert(util_is_power_of_two_nonzero(alignment));
439
440 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
441 if (offset + size > cmd_buffer->upload.size) {
442 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
443 return false;
444 offset = 0;
445 }
446
447 *out_offset = offset;
448 *ptr = cmd_buffer->upload.map + offset;
449
450 cmd_buffer->upload.offset = offset + size;
451 return true;
452 }
453
454 bool
455 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
456 unsigned size, unsigned alignment,
457 const void *data, unsigned *out_offset)
458 {
459 uint8_t *ptr;
460
461 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
462 out_offset, (void **)&ptr))
463 return false;
464
465 if (ptr)
466 memcpy(ptr, data, size);
467
468 return true;
469 }
470
471 static void
472 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
473 unsigned count, const uint32_t *data)
474 {
475 struct radeon_cmdbuf *cs = cmd_buffer->cs;
476
477 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
478
479 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
480 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
481 S_370_WR_CONFIRM(1) |
482 S_370_ENGINE_SEL(V_370_ME));
483 radeon_emit(cs, va);
484 radeon_emit(cs, va >> 32);
485 radeon_emit_array(cs, data, count);
486 }
487
488 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
489 {
490 struct radv_device *device = cmd_buffer->device;
491 struct radeon_cmdbuf *cs = cmd_buffer->cs;
492 uint64_t va;
493
494 va = radv_buffer_get_va(device->trace_bo);
495 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
496 va += 4;
497
498 ++cmd_buffer->state.trace_id;
499 radv_emit_write_data_packet(cmd_buffer, va, 1,
500 &cmd_buffer->state.trace_id);
501
502 radeon_check_space(cmd_buffer->device->ws, cs, 2);
503
504 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
505 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
506 }
507
508 static void
509 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
510 enum radv_cmd_flush_bits flags)
511 {
512 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
513 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
514 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
515
516 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
517
518 /* Force wait for graphics or compute engines to be idle. */
519 si_cs_emit_cache_flush(cmd_buffer->cs,
520 cmd_buffer->device->physical_device->rad_info.chip_class,
521 &cmd_buffer->gfx9_fence_idx,
522 cmd_buffer->gfx9_fence_va,
523 radv_cmd_buffer_uses_mec(cmd_buffer),
524 flags, cmd_buffer->gfx9_eop_bug_va);
525 }
526
527 if (unlikely(cmd_buffer->device->trace_bo))
528 radv_cmd_buffer_trace_emit(cmd_buffer);
529 }
530
531 static void
532 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline, enum ring_type ring)
534 {
535 struct radv_device *device = cmd_buffer->device;
536 uint32_t data[2];
537 uint64_t va;
538
539 va = radv_buffer_get_va(device->trace_bo);
540
541 switch (ring) {
542 case RING_GFX:
543 va += 8;
544 break;
545 case RING_COMPUTE:
546 va += 16;
547 break;
548 default:
549 assert(!"invalid ring type");
550 }
551
552 data[0] = (uintptr_t)pipeline;
553 data[1] = (uintptr_t)pipeline >> 32;
554
555 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
556 }
557
558 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
559 VkPipelineBindPoint bind_point,
560 struct radv_descriptor_set *set,
561 unsigned idx)
562 {
563 struct radv_descriptor_state *descriptors_state =
564 radv_get_descriptors_state(cmd_buffer, bind_point);
565
566 descriptors_state->sets[idx] = set;
567
568 descriptors_state->valid |= (1u << idx); /* active descriptors */
569 descriptors_state->dirty |= (1u << idx);
570 }
571
572 static void
573 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
574 VkPipelineBindPoint bind_point)
575 {
576 struct radv_descriptor_state *descriptors_state =
577 radv_get_descriptors_state(cmd_buffer, bind_point);
578 struct radv_device *device = cmd_buffer->device;
579 uint32_t data[MAX_SETS * 2] = {};
580 uint64_t va;
581 unsigned i;
582 va = radv_buffer_get_va(device->trace_bo) + 24;
583
584 for_each_bit(i, descriptors_state->valid) {
585 struct radv_descriptor_set *set = descriptors_state->sets[i];
586 data[i * 2] = (uintptr_t)set;
587 data[i * 2 + 1] = (uintptr_t)set >> 32;
588 }
589
590 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
591 }
592
593 struct radv_userdata_info *
594 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
595 gl_shader_stage stage,
596 int idx)
597 {
598 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
599 return &shader->info.user_sgprs_locs.shader_data[idx];
600 }
601
602 static void
603 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
604 struct radv_pipeline *pipeline,
605 gl_shader_stage stage,
606 int idx, uint64_t va)
607 {
608 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
609 uint32_t base_reg = pipeline->user_data_0[stage];
610 if (loc->sgpr_idx == -1)
611 return;
612
613 assert(loc->num_sgprs == 1);
614
615 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
616 base_reg + loc->sgpr_idx * 4, va, false);
617 }
618
619 static void
620 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
621 struct radv_pipeline *pipeline,
622 struct radv_descriptor_state *descriptors_state,
623 gl_shader_stage stage)
624 {
625 struct radv_device *device = cmd_buffer->device;
626 struct radeon_cmdbuf *cs = cmd_buffer->cs;
627 uint32_t sh_base = pipeline->user_data_0[stage];
628 struct radv_userdata_locations *locs =
629 &pipeline->shaders[stage]->info.user_sgprs_locs;
630 unsigned mask = locs->descriptor_sets_enabled;
631
632 mask &= descriptors_state->dirty & descriptors_state->valid;
633
634 while (mask) {
635 int start, count;
636
637 u_bit_scan_consecutive_range(&mask, &start, &count);
638
639 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
640 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
641
642 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
643 for (int i = 0; i < count; i++) {
644 struct radv_descriptor_set *set =
645 descriptors_state->sets[start + i];
646
647 radv_emit_shader_pointer_body(device, cs, set->va, true);
648 }
649 }
650 }
651
652 /**
653 * Convert the user sample locations to hardware sample locations (the values
654 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
655 */
656 static void
657 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
658 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
659 {
660 uint32_t x_offset = x % state->grid_size.width;
661 uint32_t y_offset = y % state->grid_size.height;
662 uint32_t num_samples = (uint32_t)state->per_pixel;
663 VkSampleLocationEXT *user_locs;
664 uint32_t pixel_offset;
665
666 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
667
668 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
669 user_locs = &state->locations[pixel_offset];
670
671 for (uint32_t i = 0; i < num_samples; i++) {
672 float shifted_pos_x = user_locs[i].x - 0.5;
673 float shifted_pos_y = user_locs[i].y - 0.5;
674
675 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
676 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
677
678 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
679 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
680 }
681 }
682
683 /**
684 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
685 * locations.
686 */
687 static void
688 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
689 uint32_t *sample_locs_pixel)
690 {
691 for (uint32_t i = 0; i < num_samples; i++) {
692 uint32_t sample_reg_idx = i / 4;
693 uint32_t sample_loc_idx = i % 4;
694 int32_t pos_x = sample_locs[i].x;
695 int32_t pos_y = sample_locs[i].y;
696
697 uint32_t shift_x = 8 * sample_loc_idx;
698 uint32_t shift_y = shift_x + 4;
699
700 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
701 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
702 }
703 }
704
705 /**
706 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
707 * sample locations.
708 */
709 static uint64_t
710 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
711 VkOffset2D *sample_locs,
712 uint32_t num_samples)
713 {
714 uint32_t centroid_priorities[num_samples];
715 uint32_t sample_mask = num_samples - 1;
716 uint32_t distances[num_samples];
717 uint64_t centroid_priority = 0;
718
719 /* Compute the distances from center for each sample. */
720 for (int i = 0; i < num_samples; i++) {
721 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
722 (sample_locs[i].y * sample_locs[i].y);
723 }
724
725 /* Compute the centroid priorities by looking at the distances array. */
726 for (int i = 0; i < num_samples; i++) {
727 uint32_t min_idx = 0;
728
729 for (int j = 1; j < num_samples; j++) {
730 if (distances[j] < distances[min_idx])
731 min_idx = j;
732 }
733
734 centroid_priorities[i] = min_idx;
735 distances[min_idx] = 0xffffffff;
736 }
737
738 /* Compute the final centroid priority. */
739 for (int i = 0; i < 8; i++) {
740 centroid_priority |=
741 centroid_priorities[i & sample_mask] << (i * 4);
742 }
743
744 return centroid_priority << 32 | centroid_priority;
745 }
746
747 /**
748 * Emit the sample locations that are specified with VK_EXT_sample_locations.
749 */
750 static void
751 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
752 {
753 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
754 struct radv_multisample_state *ms = &pipeline->graphics.ms;
755 struct radv_sample_locations_state *sample_location =
756 &cmd_buffer->state.dynamic.sample_location;
757 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
758 struct radeon_cmdbuf *cs = cmd_buffer->cs;
759 uint32_t sample_locs_pixel[4][2] = {};
760 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
761 uint32_t max_sample_dist = 0;
762 uint64_t centroid_priority;
763
764 if (!cmd_buffer->state.dynamic.sample_location.count)
765 return;
766
767 /* Convert the user sample locations to hardware sample locations. */
768 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
769 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
770 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
771 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
772
773 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
774 for (uint32_t i = 0; i < 4; i++) {
775 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
776 sample_locs_pixel[i]);
777 }
778
779 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
780 centroid_priority =
781 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
782 num_samples);
783
784 /* Compute the maximum sample distance from the specified locations. */
785 for (uint32_t i = 0; i < num_samples; i++) {
786 VkOffset2D offset = sample_locs[0][i];
787 max_sample_dist = MAX2(max_sample_dist,
788 MAX2(abs(offset.x), abs(offset.y)));
789 }
790
791 /* Emit the specified user sample locations. */
792 switch (num_samples) {
793 case 2:
794 case 4:
795 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
796 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
797 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
798 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
799 break;
800 case 8:
801 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
802 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
803 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
804 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
805 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
806 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
807 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
808 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
809 break;
810 default:
811 unreachable("invalid number of samples");
812 }
813
814 /* Emit the maximum sample distance and the centroid priority. */
815 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
816
817 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
818 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
819
820 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
821 radeon_emit(cs, pa_sc_aa_config);
822
823 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
824 radeon_emit(cs, centroid_priority);
825 radeon_emit(cs, centroid_priority >> 32);
826
827 /* GFX9: Flush DFSM when the AA mode changes. */
828 if (cmd_buffer->device->dfsm_allowed) {
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
830 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
831 }
832
833 cmd_buffer->state.context_roll_without_scissor_emitted = true;
834 }
835
836 static void
837 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
838 struct radv_pipeline *pipeline,
839 gl_shader_stage stage,
840 int idx, int count, uint32_t *values)
841 {
842 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
843 uint32_t base_reg = pipeline->user_data_0[stage];
844 if (loc->sgpr_idx == -1)
845 return;
846
847 assert(loc->num_sgprs == count);
848
849 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
850 radeon_emit_array(cmd_buffer->cs, values, count);
851 }
852
853 static void
854 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
855 struct radv_pipeline *pipeline)
856 {
857 int num_samples = pipeline->graphics.ms.num_samples;
858 struct radv_multisample_state *ms = &pipeline->graphics.ms;
859 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
860
861 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
862 cmd_buffer->sample_positions_needed = true;
863
864 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
865 return;
866
867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
868 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
870
871 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
872
873 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
874
875 /* GFX9: Flush DFSM when the AA mode changes. */
876 if (cmd_buffer->device->dfsm_allowed) {
877 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
878 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
879 }
880
881 cmd_buffer->state.context_roll_without_scissor_emitted = true;
882 }
883
884 static void
885 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
886 struct radv_shader_variant *shader)
887 {
888 uint64_t va;
889
890 if (!shader)
891 return;
892
893 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
894
895 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
896 }
897
898 static void
899 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
900 struct radv_pipeline *pipeline,
901 bool vertex_stage_only)
902 {
903 struct radv_cmd_state *state = &cmd_buffer->state;
904 uint32_t mask = state->prefetch_L2_mask;
905
906 if (vertex_stage_only) {
907 /* Fast prefetch path for starting draws as soon as possible.
908 */
909 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
910 RADV_PREFETCH_VBO_DESCRIPTORS);
911 }
912
913 if (mask & RADV_PREFETCH_VS)
914 radv_emit_shader_prefetch(cmd_buffer,
915 pipeline->shaders[MESA_SHADER_VERTEX]);
916
917 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
918 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
919
920 if (mask & RADV_PREFETCH_TCS)
921 radv_emit_shader_prefetch(cmd_buffer,
922 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
923
924 if (mask & RADV_PREFETCH_TES)
925 radv_emit_shader_prefetch(cmd_buffer,
926 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
927
928 if (mask & RADV_PREFETCH_GS) {
929 radv_emit_shader_prefetch(cmd_buffer,
930 pipeline->shaders[MESA_SHADER_GEOMETRY]);
931 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
932 }
933
934 if (mask & RADV_PREFETCH_PS)
935 radv_emit_shader_prefetch(cmd_buffer,
936 pipeline->shaders[MESA_SHADER_FRAGMENT]);
937
938 state->prefetch_L2_mask &= ~mask;
939 }
940
941 static void
942 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
943 {
944 if (!cmd_buffer->device->physical_device->rbplus_allowed)
945 return;
946
947 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
948 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
949 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
950
951 unsigned sx_ps_downconvert = 0;
952 unsigned sx_blend_opt_epsilon = 0;
953 unsigned sx_blend_opt_control = 0;
954
955 for (unsigned i = 0; i < subpass->color_count; ++i) {
956 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
957 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
958 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
959 continue;
960 }
961
962 int idx = subpass->color_attachments[i].attachment;
963 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
964
965 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
966 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
967 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
968 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
969
970 bool has_alpha, has_rgb;
971
972 /* Set if RGB and A are present. */
973 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
974
975 if (format == V_028C70_COLOR_8 ||
976 format == V_028C70_COLOR_16 ||
977 format == V_028C70_COLOR_32)
978 has_rgb = !has_alpha;
979 else
980 has_rgb = true;
981
982 /* Check the colormask and export format. */
983 if (!(colormask & 0x7))
984 has_rgb = false;
985 if (!(colormask & 0x8))
986 has_alpha = false;
987
988 if (spi_format == V_028714_SPI_SHADER_ZERO) {
989 has_rgb = false;
990 has_alpha = false;
991 }
992
993 /* Disable value checking for disabled channels. */
994 if (!has_rgb)
995 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
996 if (!has_alpha)
997 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
998
999 /* Enable down-conversion for 32bpp and smaller formats. */
1000 switch (format) {
1001 case V_028C70_COLOR_8:
1002 case V_028C70_COLOR_8_8:
1003 case V_028C70_COLOR_8_8_8_8:
1004 /* For 1 and 2-channel formats, use the superset thereof. */
1005 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1006 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1008 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1009 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1010 }
1011 break;
1012
1013 case V_028C70_COLOR_5_6_5:
1014 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1015 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1016 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1017 }
1018 break;
1019
1020 case V_028C70_COLOR_1_5_5_5:
1021 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1022 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1023 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1024 }
1025 break;
1026
1027 case V_028C70_COLOR_4_4_4_4:
1028 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1029 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1030 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1031 }
1032 break;
1033
1034 case V_028C70_COLOR_32:
1035 if (swap == V_028C70_SWAP_STD &&
1036 spi_format == V_028714_SPI_SHADER_32_R)
1037 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1038 else if (swap == V_028C70_SWAP_ALT_REV &&
1039 spi_format == V_028714_SPI_SHADER_32_AR)
1040 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1041 break;
1042
1043 case V_028C70_COLOR_16:
1044 case V_028C70_COLOR_16_16:
1045 /* For 1-channel formats, use the superset thereof. */
1046 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1047 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1050 if (swap == V_028C70_SWAP_STD ||
1051 swap == V_028C70_SWAP_STD_REV)
1052 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1053 else
1054 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1055 }
1056 break;
1057
1058 case V_028C70_COLOR_10_11_11:
1059 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1060 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1061 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1062 }
1063 break;
1064
1065 case V_028C70_COLOR_2_10_10_10:
1066 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1067 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1068 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1069 }
1070 break;
1071 }
1072 }
1073
1074 for (unsigned i = subpass->color_count; i < 8; ++i) {
1075 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1076 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1077 }
1078 /* TODO: avoid redundantly setting context registers */
1079 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1080 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1081 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1083
1084 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1085 }
1086
1087 static void
1088 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1089 {
1090 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1091
1092 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1093 return;
1094
1095 radv_update_multisample_state(cmd_buffer, pipeline);
1096
1097 cmd_buffer->scratch_size_needed =
1098 MAX2(cmd_buffer->scratch_size_needed,
1099 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1100
1101 if (!cmd_buffer->state.emitted_pipeline ||
1102 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1103 pipeline->graphics.can_use_guardband)
1104 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1105
1106 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1107
1108 if (!cmd_buffer->state.emitted_pipeline ||
1109 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1111 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1112 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1113 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1114 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1115 }
1116
1117 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1118 if (!pipeline->shaders[i])
1119 continue;
1120
1121 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1122 pipeline->shaders[i]->bo);
1123 }
1124
1125 if (radv_pipeline_has_gs(pipeline))
1126 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1127 pipeline->gs_copy_shader->bo);
1128
1129 if (unlikely(cmd_buffer->device->trace_bo))
1130 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1131
1132 cmd_buffer->state.emitted_pipeline = pipeline;
1133
1134 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1135 }
1136
1137 static void
1138 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1139 {
1140 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1141 cmd_buffer->state.dynamic.viewport.viewports);
1142 }
1143
1144 static void
1145 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1146 {
1147 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1148
1149 si_write_scissors(cmd_buffer->cs, 0, count,
1150 cmd_buffer->state.dynamic.scissor.scissors,
1151 cmd_buffer->state.dynamic.viewport.viewports,
1152 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1153
1154 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1155 }
1156
1157 static void
1158 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1159 {
1160 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1161 return;
1162
1163 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1164 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1165 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1166 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1167 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1168 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1169 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1170 }
1171 }
1172
1173 static void
1174 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1175 {
1176 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1177
1178 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1179 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1180 }
1181
1182 static void
1183 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1184 {
1185 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1186
1187 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1188 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1189 }
1190
1191 static void
1192 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1193 {
1194 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1195
1196 radeon_set_context_reg_seq(cmd_buffer->cs,
1197 R_028430_DB_STENCILREFMASK, 2);
1198 radeon_emit(cmd_buffer->cs,
1199 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1200 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1201 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1202 S_028430_STENCILOPVAL(1));
1203 radeon_emit(cmd_buffer->cs,
1204 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1205 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1206 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1207 S_028434_STENCILOPVAL_BF(1));
1208 }
1209
1210 static void
1211 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1212 {
1213 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1214
1215 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1216 fui(d->depth_bounds.min));
1217 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1218 fui(d->depth_bounds.max));
1219 }
1220
1221 static void
1222 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1223 {
1224 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1225 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1226 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1227
1228
1229 radeon_set_context_reg_seq(cmd_buffer->cs,
1230 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1231 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1232 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1233 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1234 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1235 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1236 }
1237
1238 static void
1239 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1240 int index,
1241 struct radv_attachment_info *att,
1242 struct radv_image *image,
1243 VkImageLayout layout)
1244 {
1245 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1246 struct radv_color_buffer_info *cb = &att->cb;
1247 uint32_t cb_color_info = cb->cb_color_info;
1248
1249 if (!radv_layout_dcc_compressed(image, layout,
1250 radv_image_queue_family_mask(image,
1251 cmd_buffer->queue_family_index,
1252 cmd_buffer->queue_family_index))) {
1253 cb_color_info &= C_028C70_DCC_ENABLE;
1254 }
1255
1256 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1257 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1258 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1259 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1260 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1261 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1262 radeon_emit(cmd_buffer->cs, cb_color_info);
1263 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1264 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1265 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1266 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1267 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1268 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1269
1270 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1271 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1272 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1273
1274 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1275 cb->cb_mrt_epitch);
1276 } else {
1277 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1282 radeon_emit(cmd_buffer->cs, cb_color_info);
1283 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1284 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1285 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1286 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1288 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1289
1290 if (is_vi) { /* DCC BASE */
1291 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1292 }
1293 }
1294
1295 if (radv_image_has_dcc(image)) {
1296 /* Drawing with DCC enabled also compresses colorbuffers. */
1297 radv_update_dcc_metadata(cmd_buffer, image, true);
1298 }
1299 }
1300
1301 static void
1302 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1303 struct radv_ds_buffer_info *ds,
1304 struct radv_image *image, VkImageLayout layout,
1305 bool requires_cond_exec)
1306 {
1307 uint32_t db_z_info = ds->db_z_info;
1308 uint32_t db_z_info_reg;
1309
1310 if (!radv_image_is_tc_compat_htile(image))
1311 return;
1312
1313 if (!radv_layout_has_htile(image, layout,
1314 radv_image_queue_family_mask(image,
1315 cmd_buffer->queue_family_index,
1316 cmd_buffer->queue_family_index))) {
1317 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1318 }
1319
1320 db_z_info &= C_028040_ZRANGE_PRECISION;
1321
1322 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1323 db_z_info_reg = R_028038_DB_Z_INFO;
1324 } else {
1325 db_z_info_reg = R_028040_DB_Z_INFO;
1326 }
1327
1328 /* When we don't know the last fast clear value we need to emit a
1329 * conditional packet that will eventually skip the following
1330 * SET_CONTEXT_REG packet.
1331 */
1332 if (requires_cond_exec) {
1333 uint64_t va = radv_buffer_get_va(image->bo);
1334 va += image->offset + image->tc_compat_zrange_offset;
1335
1336 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1337 radeon_emit(cmd_buffer->cs, va);
1338 radeon_emit(cmd_buffer->cs, va >> 32);
1339 radeon_emit(cmd_buffer->cs, 0);
1340 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1341 }
1342
1343 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1344 }
1345
1346 static void
1347 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1348 struct radv_ds_buffer_info *ds,
1349 struct radv_image *image,
1350 VkImageLayout layout)
1351 {
1352 uint32_t db_z_info = ds->db_z_info;
1353 uint32_t db_stencil_info = ds->db_stencil_info;
1354
1355 if (!radv_layout_has_htile(image, layout,
1356 radv_image_queue_family_mask(image,
1357 cmd_buffer->queue_family_index,
1358 cmd_buffer->queue_family_index))) {
1359 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1360 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1361 }
1362
1363 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1364 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1365
1366
1367 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1368 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1369 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1370 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1371 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1372
1373 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1374 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1375 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1376 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1377 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1378 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1379 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1380 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1381 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1382 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1383 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1384
1385 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1386 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1387 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1388 } else {
1389 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1390
1391 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1392 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1393 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1394 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1395 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1396 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1397 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1398 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1399 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1400 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1401
1402 }
1403
1404 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1405 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1406
1407 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1408 ds->pa_su_poly_offset_db_fmt_cntl);
1409 }
1410
1411 /**
1412 * Update the fast clear depth/stencil values if the image is bound as a
1413 * depth/stencil buffer.
1414 */
1415 static void
1416 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1417 struct radv_image *image,
1418 VkClearDepthStencilValue ds_clear_value,
1419 VkImageAspectFlags aspects)
1420 {
1421 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1422 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1423 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1424 struct radv_attachment_info *att;
1425 uint32_t att_idx;
1426
1427 if (!framebuffer || !subpass)
1428 return;
1429
1430 if (!subpass->depth_stencil_attachment)
1431 return;
1432
1433 att_idx = subpass->depth_stencil_attachment->attachment;
1434 att = &framebuffer->attachments[att_idx];
1435 if (att->attachment->image != image)
1436 return;
1437
1438 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1439 radeon_emit(cs, ds_clear_value.stencil);
1440 radeon_emit(cs, fui(ds_clear_value.depth));
1441
1442 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1443 * only needed when clearing Z to 0.0.
1444 */
1445 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1446 ds_clear_value.depth == 0.0) {
1447 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1448
1449 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1450 layout, false);
1451 }
1452
1453 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1454 }
1455
1456 /**
1457 * Set the clear depth/stencil values to the image's metadata.
1458 */
1459 static void
1460 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1461 struct radv_image *image,
1462 VkClearDepthStencilValue ds_clear_value,
1463 VkImageAspectFlags aspects)
1464 {
1465 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1466 uint64_t va = radv_buffer_get_va(image->bo);
1467 unsigned reg_offset = 0, reg_count = 0;
1468
1469 va += image->offset + image->clear_value_offset;
1470
1471 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1472 ++reg_count;
1473 } else {
1474 ++reg_offset;
1475 va += 4;
1476 }
1477 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1478 ++reg_count;
1479
1480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1482 S_370_WR_CONFIRM(1) |
1483 S_370_ENGINE_SEL(V_370_PFP));
1484 radeon_emit(cs, va);
1485 radeon_emit(cs, va >> 32);
1486 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1487 radeon_emit(cs, ds_clear_value.stencil);
1488 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1489 radeon_emit(cs, fui(ds_clear_value.depth));
1490 }
1491
1492 /**
1493 * Update the TC-compat metadata value for this image.
1494 */
1495 static void
1496 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1497 struct radv_image *image,
1498 uint32_t value)
1499 {
1500 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1501 uint64_t va = radv_buffer_get_va(image->bo);
1502 va += image->offset + image->tc_compat_zrange_offset;
1503
1504 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1505 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1506 S_370_WR_CONFIRM(1) |
1507 S_370_ENGINE_SEL(V_370_PFP));
1508 radeon_emit(cs, va);
1509 radeon_emit(cs, va >> 32);
1510 radeon_emit(cs, value);
1511 }
1512
1513 static void
1514 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1515 struct radv_image *image,
1516 VkClearDepthStencilValue ds_clear_value)
1517 {
1518 uint64_t va = radv_buffer_get_va(image->bo);
1519 va += image->offset + image->tc_compat_zrange_offset;
1520 uint32_t cond_val;
1521
1522 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1523 * depth clear value is 0.0f.
1524 */
1525 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1526
1527 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1528 }
1529
1530 /**
1531 * Update the clear depth/stencil values for this image.
1532 */
1533 void
1534 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1535 struct radv_image *image,
1536 VkClearDepthStencilValue ds_clear_value,
1537 VkImageAspectFlags aspects)
1538 {
1539 assert(radv_image_has_htile(image));
1540
1541 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1542
1543 if (radv_image_is_tc_compat_htile(image) &&
1544 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1545 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1546 ds_clear_value);
1547 }
1548
1549 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1550 aspects);
1551 }
1552
1553 /**
1554 * Load the clear depth/stencil values from the image's metadata.
1555 */
1556 static void
1557 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1558 struct radv_image *image)
1559 {
1560 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1561 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1562 uint64_t va = radv_buffer_get_va(image->bo);
1563 unsigned reg_offset = 0, reg_count = 0;
1564
1565 va += image->offset + image->clear_value_offset;
1566
1567 if (!radv_image_has_htile(image))
1568 return;
1569
1570 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1571 ++reg_count;
1572 } else {
1573 ++reg_offset;
1574 va += 4;
1575 }
1576 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1577 ++reg_count;
1578
1579 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1580
1581 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1582 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1583 radeon_emit(cs, va);
1584 radeon_emit(cs, va >> 32);
1585 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1586 radeon_emit(cs, reg_count);
1587 } else {
1588 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1589 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1590 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1591 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1592 radeon_emit(cs, va);
1593 radeon_emit(cs, va >> 32);
1594 radeon_emit(cs, reg >> 2);
1595 radeon_emit(cs, 0);
1596
1597 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1598 radeon_emit(cs, 0);
1599 }
1600 }
1601
1602 /*
1603 * With DCC some colors don't require CMASK elimination before being
1604 * used as a texture. This sets a predicate value to determine if the
1605 * cmask eliminate is required.
1606 */
1607 void
1608 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_image *image, bool value)
1610 {
1611 uint64_t pred_val = value;
1612 uint64_t va = radv_buffer_get_va(image->bo);
1613 va += image->offset + image->fce_pred_offset;
1614
1615 assert(radv_image_has_dcc(image));
1616
1617 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1618 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1619 S_370_WR_CONFIRM(1) |
1620 S_370_ENGINE_SEL(V_370_PFP));
1621 radeon_emit(cmd_buffer->cs, va);
1622 radeon_emit(cmd_buffer->cs, va >> 32);
1623 radeon_emit(cmd_buffer->cs, pred_val);
1624 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1625 }
1626
1627 /**
1628 * Update the DCC predicate to reflect the compression state.
1629 */
1630 void
1631 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1632 struct radv_image *image, bool value)
1633 {
1634 uint64_t pred_val = value;
1635 uint64_t va = radv_buffer_get_va(image->bo);
1636 va += image->offset + image->dcc_pred_offset;
1637
1638 assert(radv_image_has_dcc(image));
1639
1640 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1641 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1642 S_370_WR_CONFIRM(1) |
1643 S_370_ENGINE_SEL(V_370_PFP));
1644 radeon_emit(cmd_buffer->cs, va);
1645 radeon_emit(cmd_buffer->cs, va >> 32);
1646 radeon_emit(cmd_buffer->cs, pred_val);
1647 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1648 }
1649
1650 /**
1651 * Update the fast clear color values if the image is bound as a color buffer.
1652 */
1653 static void
1654 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1655 struct radv_image *image,
1656 int cb_idx,
1657 uint32_t color_values[2])
1658 {
1659 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1660 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1661 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1662 struct radv_attachment_info *att;
1663 uint32_t att_idx;
1664
1665 if (!framebuffer || !subpass)
1666 return;
1667
1668 att_idx = subpass->color_attachments[cb_idx].attachment;
1669 if (att_idx == VK_ATTACHMENT_UNUSED)
1670 return;
1671
1672 att = &framebuffer->attachments[att_idx];
1673 if (att->attachment->image != image)
1674 return;
1675
1676 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1677 radeon_emit(cs, color_values[0]);
1678 radeon_emit(cs, color_values[1]);
1679
1680 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1681 }
1682
1683 /**
1684 * Set the clear color values to the image's metadata.
1685 */
1686 static void
1687 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1688 struct radv_image *image,
1689 uint32_t color_values[2])
1690 {
1691 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1692 uint64_t va = radv_buffer_get_va(image->bo);
1693
1694 va += image->offset + image->clear_value_offset;
1695
1696 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1697
1698 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
1699 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1700 S_370_WR_CONFIRM(1) |
1701 S_370_ENGINE_SEL(V_370_PFP));
1702 radeon_emit(cs, va);
1703 radeon_emit(cs, va >> 32);
1704 radeon_emit(cs, color_values[0]);
1705 radeon_emit(cs, color_values[1]);
1706 }
1707
1708 /**
1709 * Update the clear color values for this image.
1710 */
1711 void
1712 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1713 struct radv_image *image,
1714 int cb_idx,
1715 uint32_t color_values[2])
1716 {
1717 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1718
1719 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1720
1721 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1722 color_values);
1723 }
1724
1725 /**
1726 * Load the clear color values from the image's metadata.
1727 */
1728 static void
1729 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1730 struct radv_image *image,
1731 int cb_idx)
1732 {
1733 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1734 uint64_t va = radv_buffer_get_va(image->bo);
1735
1736 va += image->offset + image->clear_value_offset;
1737
1738 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1739 return;
1740
1741 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1742
1743 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1744 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1745 radeon_emit(cs, va);
1746 radeon_emit(cs, va >> 32);
1747 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1748 radeon_emit(cs, 2);
1749 } else {
1750 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1751 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1752 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1753 COPY_DATA_COUNT_SEL);
1754 radeon_emit(cs, va);
1755 radeon_emit(cs, va >> 32);
1756 radeon_emit(cs, reg >> 2);
1757 radeon_emit(cs, 0);
1758
1759 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1760 radeon_emit(cs, 0);
1761 }
1762 }
1763
1764 static void
1765 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1766 {
1767 int i;
1768 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1769 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1770 unsigned num_bpp64_colorbufs = 0;
1771
1772 /* this may happen for inherited secondary recording */
1773 if (!framebuffer)
1774 return;
1775
1776 for (i = 0; i < 8; ++i) {
1777 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1778 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1779 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1780 continue;
1781 }
1782
1783 int idx = subpass->color_attachments[i].attachment;
1784 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1785 struct radv_image *image = att->attachment->image;
1786 VkImageLayout layout = subpass->color_attachments[i].layout;
1787
1788 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1789
1790 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1791 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1792 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1793
1794 radv_load_color_clear_metadata(cmd_buffer, image, i);
1795
1796 if (image->planes[0].surface.bpe >= 8)
1797 num_bpp64_colorbufs++;
1798 }
1799
1800 if (subpass->depth_stencil_attachment) {
1801 int idx = subpass->depth_stencil_attachment->attachment;
1802 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1803 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1804 struct radv_image *image = att->attachment->image;
1805 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1806 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1807 cmd_buffer->queue_family_index,
1808 cmd_buffer->queue_family_index);
1809 /* We currently don't support writing decompressed HTILE */
1810 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1811 radv_layout_is_htile_compressed(image, layout, queue_mask));
1812
1813 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1814
1815 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1816 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1817 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1818 }
1819 radv_load_ds_clear_metadata(cmd_buffer, image);
1820 } else {
1821 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1822 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1823 else
1824 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1825
1826 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1827 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1828 }
1829 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1830 S_028208_BR_X(framebuffer->width) |
1831 S_028208_BR_Y(framebuffer->height));
1832
1833 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1834 uint8_t watermark = 4; /* Default value for GFX8. */
1835
1836 /* For optimal DCC performance. */
1837 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1838 if (num_bpp64_colorbufs >= 5) {
1839 watermark = 8;
1840 } else {
1841 watermark = 6;
1842 }
1843 }
1844
1845 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1846 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1847 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1848 }
1849
1850 if (cmd_buffer->device->dfsm_allowed) {
1851 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1852 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1853 }
1854
1855 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1856 }
1857
1858 static void
1859 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1860 {
1861 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1862 struct radv_cmd_state *state = &cmd_buffer->state;
1863
1864 if (state->index_type != state->last_index_type) {
1865 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1866 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1867 2, state->index_type);
1868 } else {
1869 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1870 radeon_emit(cs, state->index_type);
1871 }
1872
1873 state->last_index_type = state->index_type;
1874 }
1875
1876 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1877 radeon_emit(cs, state->index_va);
1878 radeon_emit(cs, state->index_va >> 32);
1879
1880 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1881 radeon_emit(cs, state->max_index_count);
1882
1883 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1884 }
1885
1886 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1887 {
1888 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1889 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1890 uint32_t pa_sc_mode_cntl_1 =
1891 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1892 uint32_t db_count_control;
1893
1894 if(!cmd_buffer->state.active_occlusion_queries) {
1895 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1896 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1897 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1898 has_perfect_queries) {
1899 /* Re-enable out-of-order rasterization if the
1900 * bound pipeline supports it and if it's has
1901 * been disabled before starting any perfect
1902 * occlusion queries.
1903 */
1904 radeon_set_context_reg(cmd_buffer->cs,
1905 R_028A4C_PA_SC_MODE_CNTL_1,
1906 pa_sc_mode_cntl_1);
1907 }
1908 }
1909 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1910 } else {
1911 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1912 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1913
1914 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1915 db_count_control =
1916 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1917 S_028004_SAMPLE_RATE(sample_rate) |
1918 S_028004_ZPASS_ENABLE(1) |
1919 S_028004_SLICE_EVEN_ENABLE(1) |
1920 S_028004_SLICE_ODD_ENABLE(1);
1921
1922 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1923 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1924 has_perfect_queries) {
1925 /* If the bound pipeline has enabled
1926 * out-of-order rasterization, we should
1927 * disable it before starting any perfect
1928 * occlusion queries.
1929 */
1930 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1931
1932 radeon_set_context_reg(cmd_buffer->cs,
1933 R_028A4C_PA_SC_MODE_CNTL_1,
1934 pa_sc_mode_cntl_1);
1935 }
1936 } else {
1937 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1938 S_028004_SAMPLE_RATE(sample_rate);
1939 }
1940 }
1941
1942 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1943
1944 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1945 }
1946
1947 static void
1948 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1949 {
1950 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1951
1952 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1953 radv_emit_viewport(cmd_buffer);
1954
1955 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1956 !cmd_buffer->device->physical_device->has_scissor_bug)
1957 radv_emit_scissor(cmd_buffer);
1958
1959 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1960 radv_emit_line_width(cmd_buffer);
1961
1962 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1963 radv_emit_blend_constants(cmd_buffer);
1964
1965 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1966 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1968 radv_emit_stencil(cmd_buffer);
1969
1970 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1971 radv_emit_depth_bounds(cmd_buffer);
1972
1973 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1974 radv_emit_depth_bias(cmd_buffer);
1975
1976 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1977 radv_emit_discard_rectangle(cmd_buffer);
1978
1979 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
1980 radv_emit_sample_locations(cmd_buffer);
1981
1982 cmd_buffer->state.dirty &= ~states;
1983 }
1984
1985 static void
1986 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1987 VkPipelineBindPoint bind_point)
1988 {
1989 struct radv_descriptor_state *descriptors_state =
1990 radv_get_descriptors_state(cmd_buffer, bind_point);
1991 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1992 unsigned bo_offset;
1993
1994 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1995 set->mapped_ptr,
1996 &bo_offset))
1997 return;
1998
1999 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2000 set->va += bo_offset;
2001 }
2002
2003 static void
2004 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2005 VkPipelineBindPoint bind_point)
2006 {
2007 struct radv_descriptor_state *descriptors_state =
2008 radv_get_descriptors_state(cmd_buffer, bind_point);
2009 uint32_t size = MAX_SETS * 4;
2010 uint32_t offset;
2011 void *ptr;
2012
2013 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2014 256, &offset, &ptr))
2015 return;
2016
2017 for (unsigned i = 0; i < MAX_SETS; i++) {
2018 uint32_t *uptr = ((uint32_t *)ptr) + i;
2019 uint64_t set_va = 0;
2020 struct radv_descriptor_set *set = descriptors_state->sets[i];
2021 if (descriptors_state->valid & (1u << i))
2022 set_va = set->va;
2023 uptr[0] = set_va & 0xffffffff;
2024 }
2025
2026 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2027 va += offset;
2028
2029 if (cmd_buffer->state.pipeline) {
2030 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2031 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2032 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2033
2034 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2035 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2036 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2037
2038 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2039 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2040 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2041
2042 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2043 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2044 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2045
2046 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2047 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2048 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2049 }
2050
2051 if (cmd_buffer->state.compute_pipeline)
2052 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2053 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2054 }
2055
2056 static void
2057 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2058 VkShaderStageFlags stages)
2059 {
2060 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2061 VK_PIPELINE_BIND_POINT_COMPUTE :
2062 VK_PIPELINE_BIND_POINT_GRAPHICS;
2063 struct radv_descriptor_state *descriptors_state =
2064 radv_get_descriptors_state(cmd_buffer, bind_point);
2065 struct radv_cmd_state *state = &cmd_buffer->state;
2066 bool flush_indirect_descriptors;
2067
2068 if (!descriptors_state->dirty)
2069 return;
2070
2071 if (descriptors_state->push_dirty)
2072 radv_flush_push_descriptors(cmd_buffer, bind_point);
2073
2074 flush_indirect_descriptors =
2075 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2076 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2077 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2078 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2079
2080 if (flush_indirect_descriptors)
2081 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2082
2083 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2084 cmd_buffer->cs,
2085 MAX_SETS * MESA_SHADER_STAGES * 4);
2086
2087 if (cmd_buffer->state.pipeline) {
2088 radv_foreach_stage(stage, stages) {
2089 if (!cmd_buffer->state.pipeline->shaders[stage])
2090 continue;
2091
2092 radv_emit_descriptor_pointers(cmd_buffer,
2093 cmd_buffer->state.pipeline,
2094 descriptors_state, stage);
2095 }
2096 }
2097
2098 if (cmd_buffer->state.compute_pipeline &&
2099 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2100 radv_emit_descriptor_pointers(cmd_buffer,
2101 cmd_buffer->state.compute_pipeline,
2102 descriptors_state,
2103 MESA_SHADER_COMPUTE);
2104 }
2105
2106 descriptors_state->dirty = 0;
2107 descriptors_state->push_dirty = false;
2108
2109 assert(cmd_buffer->cs->cdw <= cdw_max);
2110
2111 if (unlikely(cmd_buffer->device->trace_bo))
2112 radv_save_descriptors(cmd_buffer, bind_point);
2113 }
2114
2115 static void
2116 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2117 VkShaderStageFlags stages)
2118 {
2119 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2120 ? cmd_buffer->state.compute_pipeline
2121 : cmd_buffer->state.pipeline;
2122 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2123 VK_PIPELINE_BIND_POINT_COMPUTE :
2124 VK_PIPELINE_BIND_POINT_GRAPHICS;
2125 struct radv_descriptor_state *descriptors_state =
2126 radv_get_descriptors_state(cmd_buffer, bind_point);
2127 struct radv_pipeline_layout *layout = pipeline->layout;
2128 struct radv_shader_variant *shader, *prev_shader;
2129 bool need_push_constants = false;
2130 unsigned offset;
2131 void *ptr;
2132 uint64_t va;
2133
2134 stages &= cmd_buffer->push_constant_stages;
2135 if (!stages ||
2136 (!layout->push_constant_size && !layout->dynamic_offset_count))
2137 return;
2138
2139 radv_foreach_stage(stage, stages) {
2140 if (!pipeline->shaders[stage])
2141 continue;
2142
2143 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2144 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2145
2146 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2147 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2148
2149 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2150 AC_UD_INLINE_PUSH_CONSTANTS,
2151 count,
2152 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2153 }
2154
2155 if (need_push_constants) {
2156 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2157 16 * layout->dynamic_offset_count,
2158 256, &offset, &ptr))
2159 return;
2160
2161 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2162 memcpy((char*)ptr + layout->push_constant_size,
2163 descriptors_state->dynamic_buffers,
2164 16 * layout->dynamic_offset_count);
2165
2166 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2167 va += offset;
2168
2169 MAYBE_UNUSED unsigned cdw_max =
2170 radeon_check_space(cmd_buffer->device->ws,
2171 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2172
2173 prev_shader = NULL;
2174 radv_foreach_stage(stage, stages) {
2175 shader = radv_get_shader(pipeline, stage);
2176
2177 /* Avoid redundantly emitting the address for merged stages. */
2178 if (shader && shader != prev_shader) {
2179 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2180 AC_UD_PUSH_CONSTANTS, va);
2181
2182 prev_shader = shader;
2183 }
2184 }
2185 assert(cmd_buffer->cs->cdw <= cdw_max);
2186 }
2187
2188 cmd_buffer->push_constant_stages &= ~stages;
2189 }
2190
2191 static void
2192 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2193 bool pipeline_is_dirty)
2194 {
2195 if ((pipeline_is_dirty ||
2196 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2197 cmd_buffer->state.pipeline->num_vertex_bindings &&
2198 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2199 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2200 unsigned vb_offset;
2201 void *vb_ptr;
2202 uint32_t i = 0;
2203 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2204 uint64_t va;
2205
2206 /* allocate some descriptor state for vertex buffers */
2207 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2208 &vb_offset, &vb_ptr))
2209 return;
2210
2211 for (i = 0; i < count; i++) {
2212 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2213 uint32_t offset;
2214 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2215 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2216
2217 if (!buffer)
2218 continue;
2219
2220 va = radv_buffer_get_va(buffer->bo);
2221
2222 offset = cmd_buffer->vertex_bindings[i].offset;
2223 va += offset + buffer->offset;
2224 desc[0] = va;
2225 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2226 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2227 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2228 else
2229 desc[2] = buffer->size - offset;
2230 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2231 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2232 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2233 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2234 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2235 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2236 }
2237
2238 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2239 va += vb_offset;
2240
2241 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2242 AC_UD_VS_VERTEX_BUFFERS, va);
2243
2244 cmd_buffer->state.vb_va = va;
2245 cmd_buffer->state.vb_size = count * 16;
2246 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2247 }
2248 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2249 }
2250
2251 static void
2252 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2253 {
2254 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2255 struct radv_userdata_info *loc;
2256 uint32_t base_reg;
2257
2258 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2259 if (!radv_get_shader(pipeline, stage))
2260 continue;
2261
2262 loc = radv_lookup_user_sgpr(pipeline, stage,
2263 AC_UD_STREAMOUT_BUFFERS);
2264 if (loc->sgpr_idx == -1)
2265 continue;
2266
2267 base_reg = pipeline->user_data_0[stage];
2268
2269 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2270 base_reg + loc->sgpr_idx * 4, va, false);
2271 }
2272
2273 if (pipeline->gs_copy_shader) {
2274 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2275 if (loc->sgpr_idx != -1) {
2276 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2277
2278 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2279 base_reg + loc->sgpr_idx * 4, va, false);
2280 }
2281 }
2282 }
2283
2284 static void
2285 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2286 {
2287 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2288 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2289 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2290 unsigned so_offset;
2291 void *so_ptr;
2292 uint64_t va;
2293
2294 /* Allocate some descriptor state for streamout buffers. */
2295 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2296 MAX_SO_BUFFERS * 16, 256,
2297 &so_offset, &so_ptr))
2298 return;
2299
2300 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2301 struct radv_buffer *buffer = sb[i].buffer;
2302 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2303
2304 if (!(so->enabled_mask & (1 << i)))
2305 continue;
2306
2307 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2308
2309 va += sb[i].offset;
2310
2311 /* Set the descriptor.
2312 *
2313 * On GFX8, the format must be non-INVALID, otherwise
2314 * the buffer will be considered not bound and store
2315 * instructions will be no-ops.
2316 */
2317 desc[0] = va;
2318 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2319 desc[2] = 0xffffffff;
2320 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2321 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2322 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2323 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2325 }
2326
2327 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2328 va += so_offset;
2329
2330 radv_emit_streamout_buffers(cmd_buffer, va);
2331 }
2332
2333 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2334 }
2335
2336 static void
2337 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2338 {
2339 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2340 radv_flush_streamout_descriptors(cmd_buffer);
2341 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2342 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2343 }
2344
2345 struct radv_draw_info {
2346 /**
2347 * Number of vertices.
2348 */
2349 uint32_t count;
2350
2351 /**
2352 * Index of the first vertex.
2353 */
2354 int32_t vertex_offset;
2355
2356 /**
2357 * First instance id.
2358 */
2359 uint32_t first_instance;
2360
2361 /**
2362 * Number of instances.
2363 */
2364 uint32_t instance_count;
2365
2366 /**
2367 * First index (indexed draws only).
2368 */
2369 uint32_t first_index;
2370
2371 /**
2372 * Whether it's an indexed draw.
2373 */
2374 bool indexed;
2375
2376 /**
2377 * Indirect draw parameters resource.
2378 */
2379 struct radv_buffer *indirect;
2380 uint64_t indirect_offset;
2381 uint32_t stride;
2382
2383 /**
2384 * Draw count parameters resource.
2385 */
2386 struct radv_buffer *count_buffer;
2387 uint64_t count_buffer_offset;
2388
2389 /**
2390 * Stream output parameters resource.
2391 */
2392 struct radv_buffer *strmout_buffer;
2393 uint64_t strmout_buffer_offset;
2394 };
2395
2396 static void
2397 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2398 const struct radv_draw_info *draw_info)
2399 {
2400 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2401 struct radv_cmd_state *state = &cmd_buffer->state;
2402 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2403 uint32_t ia_multi_vgt_param;
2404 int32_t primitive_reset_en;
2405
2406 /* Draw state. */
2407 ia_multi_vgt_param =
2408 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2409 draw_info->indirect,
2410 !!draw_info->strmout_buffer,
2411 draw_info->indirect ? 0 : draw_info->count);
2412
2413 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2414 if (info->chip_class >= GFX9) {
2415 radeon_set_uconfig_reg_idx(cs,
2416 R_030960_IA_MULTI_VGT_PARAM,
2417 4, ia_multi_vgt_param);
2418 } else if (info->chip_class >= GFX7) {
2419 radeon_set_context_reg_idx(cs,
2420 R_028AA8_IA_MULTI_VGT_PARAM,
2421 1, ia_multi_vgt_param);
2422 } else {
2423 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2424 ia_multi_vgt_param);
2425 }
2426 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2427 }
2428
2429 /* Primitive restart. */
2430 primitive_reset_en =
2431 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2432
2433 if (primitive_reset_en != state->last_primitive_reset_en) {
2434 state->last_primitive_reset_en = primitive_reset_en;
2435 if (info->chip_class >= GFX9) {
2436 radeon_set_uconfig_reg(cs,
2437 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2438 primitive_reset_en);
2439 } else {
2440 radeon_set_context_reg(cs,
2441 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2442 primitive_reset_en);
2443 }
2444 }
2445
2446 if (primitive_reset_en) {
2447 uint32_t primitive_reset_index =
2448 state->index_type ? 0xffffffffu : 0xffffu;
2449
2450 if (primitive_reset_index != state->last_primitive_reset_index) {
2451 radeon_set_context_reg(cs,
2452 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2453 primitive_reset_index);
2454 state->last_primitive_reset_index = primitive_reset_index;
2455 }
2456 }
2457
2458 if (draw_info->strmout_buffer) {
2459 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2460
2461 va += draw_info->strmout_buffer->offset +
2462 draw_info->strmout_buffer_offset;
2463
2464 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2465 draw_info->stride);
2466
2467 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2468 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2469 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2470 COPY_DATA_WR_CONFIRM);
2471 radeon_emit(cs, va);
2472 radeon_emit(cs, va >> 32);
2473 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2474 radeon_emit(cs, 0); /* unused */
2475
2476 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2477 }
2478 }
2479
2480 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2481 VkPipelineStageFlags src_stage_mask)
2482 {
2483 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2484 VK_PIPELINE_STAGE_TRANSFER_BIT |
2485 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2486 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2487 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2488 }
2489
2490 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2491 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2492 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2493 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2494 VK_PIPELINE_STAGE_TRANSFER_BIT |
2495 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2496 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2497 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2498 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2499 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2500 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2501 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2502 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2503 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2504 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2505 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2506 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2507 }
2508 }
2509
2510 static enum radv_cmd_flush_bits
2511 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2512 VkAccessFlags src_flags,
2513 struct radv_image *image)
2514 {
2515 bool flush_CB_meta = true, flush_DB_meta = true;
2516 enum radv_cmd_flush_bits flush_bits = 0;
2517 uint32_t b;
2518
2519 if (image) {
2520 if (!radv_image_has_CB_metadata(image))
2521 flush_CB_meta = false;
2522 if (!radv_image_has_htile(image))
2523 flush_DB_meta = false;
2524 }
2525
2526 for_each_bit(b, src_flags) {
2527 switch ((VkAccessFlagBits)(1 << b)) {
2528 case VK_ACCESS_SHADER_WRITE_BIT:
2529 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2530 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2531 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2532 break;
2533 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2534 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2535 if (flush_CB_meta)
2536 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2537 break;
2538 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2539 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2540 if (flush_DB_meta)
2541 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2542 break;
2543 case VK_ACCESS_TRANSFER_WRITE_BIT:
2544 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2545 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2546 RADV_CMD_FLAG_INV_GLOBAL_L2;
2547
2548 if (flush_CB_meta)
2549 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2550 if (flush_DB_meta)
2551 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2552 break;
2553 default:
2554 break;
2555 }
2556 }
2557 return flush_bits;
2558 }
2559
2560 static enum radv_cmd_flush_bits
2561 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2562 VkAccessFlags dst_flags,
2563 struct radv_image *image)
2564 {
2565 bool flush_CB_meta = true, flush_DB_meta = true;
2566 enum radv_cmd_flush_bits flush_bits = 0;
2567 bool flush_CB = true, flush_DB = true;
2568 bool image_is_coherent = false;
2569 uint32_t b;
2570
2571 if (image) {
2572 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2573 flush_CB = false;
2574 flush_DB = false;
2575 }
2576
2577 if (!radv_image_has_CB_metadata(image))
2578 flush_CB_meta = false;
2579 if (!radv_image_has_htile(image))
2580 flush_DB_meta = false;
2581
2582 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2583 if (image->info.samples == 1 &&
2584 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2585 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2586 !vk_format_is_stencil(image->vk_format)) {
2587 /* Single-sample color and single-sample depth
2588 * (not stencil) are coherent with shaders on
2589 * GFX9.
2590 */
2591 image_is_coherent = true;
2592 }
2593 }
2594 }
2595
2596 for_each_bit(b, dst_flags) {
2597 switch ((VkAccessFlagBits)(1 << b)) {
2598 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2599 case VK_ACCESS_INDEX_READ_BIT:
2600 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2601 break;
2602 case VK_ACCESS_UNIFORM_READ_BIT:
2603 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2604 break;
2605 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2606 case VK_ACCESS_TRANSFER_READ_BIT:
2607 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2608 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2609 RADV_CMD_FLAG_INV_GLOBAL_L2;
2610 break;
2611 case VK_ACCESS_SHADER_READ_BIT:
2612 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2613
2614 if (!image_is_coherent)
2615 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2616 break;
2617 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2618 if (flush_CB)
2619 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2620 if (flush_CB_meta)
2621 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2622 break;
2623 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2624 if (flush_DB)
2625 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2626 if (flush_DB_meta)
2627 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2628 break;
2629 default:
2630 break;
2631 }
2632 }
2633 return flush_bits;
2634 }
2635
2636 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2637 const struct radv_subpass_barrier *barrier)
2638 {
2639 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2640 NULL);
2641 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2642 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2643 NULL);
2644 }
2645
2646 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2647 struct radv_subpass_attachment att)
2648 {
2649 unsigned idx = att.attachment;
2650 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2651 VkImageSubresourceRange range;
2652 range.aspectMask = 0;
2653 range.baseMipLevel = view->base_mip;
2654 range.levelCount = 1;
2655 range.baseArrayLayer = view->base_layer;
2656 range.layerCount = cmd_buffer->state.framebuffer->layers;
2657
2658 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2659 /* If the current subpass uses multiview, the driver might have
2660 * performed a fast color/depth clear to the whole image
2661 * (including all layers). To make sure the driver will
2662 * decompress the image correctly (if needed), we have to
2663 * account for the "real" number of layers. If the view mask is
2664 * sparse, this will decompress more layers than needed.
2665 */
2666 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2667 }
2668
2669 radv_handle_image_transition(cmd_buffer,
2670 view->image,
2671 cmd_buffer->state.attachments[idx].current_layout,
2672 att.layout, 0, 0, &range);
2673
2674 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2675
2676
2677 }
2678
2679 void
2680 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2681 const struct radv_subpass *subpass)
2682 {
2683 cmd_buffer->state.subpass = subpass;
2684
2685 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2686 }
2687
2688 static VkResult
2689 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2690 struct radv_render_pass *pass,
2691 const VkRenderPassBeginInfo *info)
2692 {
2693 struct radv_cmd_state *state = &cmd_buffer->state;
2694
2695 if (pass->attachment_count == 0) {
2696 state->attachments = NULL;
2697 return VK_SUCCESS;
2698 }
2699
2700 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2701 pass->attachment_count *
2702 sizeof(state->attachments[0]),
2703 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2704 if (state->attachments == NULL) {
2705 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2706 return cmd_buffer->record_result;
2707 }
2708
2709 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2710 struct radv_render_pass_attachment *att = &pass->attachments[i];
2711 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2712 VkImageAspectFlags clear_aspects = 0;
2713
2714 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2715 /* color attachment */
2716 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2717 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2718 }
2719 } else {
2720 /* depthstencil attachment */
2721 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2722 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2723 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2724 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2725 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2726 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2727 }
2728 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2729 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2730 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2731 }
2732 }
2733
2734 state->attachments[i].pending_clear_aspects = clear_aspects;
2735 state->attachments[i].cleared_views = 0;
2736 if (clear_aspects && info) {
2737 assert(info->clearValueCount > i);
2738 state->attachments[i].clear_value = info->pClearValues[i];
2739 }
2740
2741 state->attachments[i].current_layout = att->initial_layout;
2742 }
2743
2744 return VK_SUCCESS;
2745 }
2746
2747 VkResult radv_AllocateCommandBuffers(
2748 VkDevice _device,
2749 const VkCommandBufferAllocateInfo *pAllocateInfo,
2750 VkCommandBuffer *pCommandBuffers)
2751 {
2752 RADV_FROM_HANDLE(radv_device, device, _device);
2753 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2754
2755 VkResult result = VK_SUCCESS;
2756 uint32_t i;
2757
2758 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2759
2760 if (!list_empty(&pool->free_cmd_buffers)) {
2761 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2762
2763 list_del(&cmd_buffer->pool_link);
2764 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2765
2766 result = radv_reset_cmd_buffer(cmd_buffer);
2767 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2768 cmd_buffer->level = pAllocateInfo->level;
2769
2770 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2771 } else {
2772 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2773 &pCommandBuffers[i]);
2774 }
2775 if (result != VK_SUCCESS)
2776 break;
2777 }
2778
2779 if (result != VK_SUCCESS) {
2780 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2781 i, pCommandBuffers);
2782
2783 /* From the Vulkan 1.0.66 spec:
2784 *
2785 * "vkAllocateCommandBuffers can be used to create multiple
2786 * command buffers. If the creation of any of those command
2787 * buffers fails, the implementation must destroy all
2788 * successfully created command buffer objects from this
2789 * command, set all entries of the pCommandBuffers array to
2790 * NULL and return the error."
2791 */
2792 memset(pCommandBuffers, 0,
2793 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2794 }
2795
2796 return result;
2797 }
2798
2799 void radv_FreeCommandBuffers(
2800 VkDevice device,
2801 VkCommandPool commandPool,
2802 uint32_t commandBufferCount,
2803 const VkCommandBuffer *pCommandBuffers)
2804 {
2805 for (uint32_t i = 0; i < commandBufferCount; i++) {
2806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2807
2808 if (cmd_buffer) {
2809 if (cmd_buffer->pool) {
2810 list_del(&cmd_buffer->pool_link);
2811 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2812 } else
2813 radv_cmd_buffer_destroy(cmd_buffer);
2814
2815 }
2816 }
2817 }
2818
2819 VkResult radv_ResetCommandBuffer(
2820 VkCommandBuffer commandBuffer,
2821 VkCommandBufferResetFlags flags)
2822 {
2823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2824 return radv_reset_cmd_buffer(cmd_buffer);
2825 }
2826
2827 VkResult radv_BeginCommandBuffer(
2828 VkCommandBuffer commandBuffer,
2829 const VkCommandBufferBeginInfo *pBeginInfo)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2832 VkResult result = VK_SUCCESS;
2833
2834 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2835 /* If the command buffer has already been resetted with
2836 * vkResetCommandBuffer, no need to do it again.
2837 */
2838 result = radv_reset_cmd_buffer(cmd_buffer);
2839 if (result != VK_SUCCESS)
2840 return result;
2841 }
2842
2843 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2844 cmd_buffer->state.last_primitive_reset_en = -1;
2845 cmd_buffer->state.last_index_type = -1;
2846 cmd_buffer->state.last_num_instances = -1;
2847 cmd_buffer->state.last_vertex_offset = -1;
2848 cmd_buffer->state.last_first_instance = -1;
2849 cmd_buffer->state.predication_type = -1;
2850 cmd_buffer->usage_flags = pBeginInfo->flags;
2851
2852 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2853 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2854 assert(pBeginInfo->pInheritanceInfo);
2855 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2856 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2857
2858 struct radv_subpass *subpass =
2859 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2860
2861 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2862 if (result != VK_SUCCESS)
2863 return result;
2864
2865 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2866 }
2867
2868 if (unlikely(cmd_buffer->device->trace_bo)) {
2869 struct radv_device *device = cmd_buffer->device;
2870
2871 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2872 device->trace_bo);
2873
2874 radv_cmd_buffer_trace_emit(cmd_buffer);
2875 }
2876
2877 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2878
2879 return result;
2880 }
2881
2882 void radv_CmdBindVertexBuffers(
2883 VkCommandBuffer commandBuffer,
2884 uint32_t firstBinding,
2885 uint32_t bindingCount,
2886 const VkBuffer* pBuffers,
2887 const VkDeviceSize* pOffsets)
2888 {
2889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2890 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2891 bool changed = false;
2892
2893 /* We have to defer setting up vertex buffer since we need the buffer
2894 * stride from the pipeline. */
2895
2896 assert(firstBinding + bindingCount <= MAX_VBS);
2897 for (uint32_t i = 0; i < bindingCount; i++) {
2898 uint32_t idx = firstBinding + i;
2899
2900 if (!changed &&
2901 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2902 vb[idx].offset != pOffsets[i])) {
2903 changed = true;
2904 }
2905
2906 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2907 vb[idx].offset = pOffsets[i];
2908
2909 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2910 vb[idx].buffer->bo);
2911 }
2912
2913 if (!changed) {
2914 /* No state changes. */
2915 return;
2916 }
2917
2918 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2919 }
2920
2921 void radv_CmdBindIndexBuffer(
2922 VkCommandBuffer commandBuffer,
2923 VkBuffer buffer,
2924 VkDeviceSize offset,
2925 VkIndexType indexType)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2929
2930 if (cmd_buffer->state.index_buffer == index_buffer &&
2931 cmd_buffer->state.index_offset == offset &&
2932 cmd_buffer->state.index_type == indexType) {
2933 /* No state changes. */
2934 return;
2935 }
2936
2937 cmd_buffer->state.index_buffer = index_buffer;
2938 cmd_buffer->state.index_offset = offset;
2939 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2940 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2941 cmd_buffer->state.index_va += index_buffer->offset + offset;
2942
2943 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2944 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2945 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2946 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2947 }
2948
2949
2950 static void
2951 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2952 VkPipelineBindPoint bind_point,
2953 struct radv_descriptor_set *set, unsigned idx)
2954 {
2955 struct radeon_winsys *ws = cmd_buffer->device->ws;
2956
2957 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2958
2959 assert(set);
2960 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2961
2962 if (!cmd_buffer->device->use_global_bo_list) {
2963 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2964 if (set->descriptors[j])
2965 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2966 }
2967
2968 if(set->bo)
2969 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2970 }
2971
2972 void radv_CmdBindDescriptorSets(
2973 VkCommandBuffer commandBuffer,
2974 VkPipelineBindPoint pipelineBindPoint,
2975 VkPipelineLayout _layout,
2976 uint32_t firstSet,
2977 uint32_t descriptorSetCount,
2978 const VkDescriptorSet* pDescriptorSets,
2979 uint32_t dynamicOffsetCount,
2980 const uint32_t* pDynamicOffsets)
2981 {
2982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2983 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2984 unsigned dyn_idx = 0;
2985
2986 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2987 struct radv_descriptor_state *descriptors_state =
2988 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2989
2990 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2991 unsigned idx = i + firstSet;
2992 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2993 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2994
2995 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2996 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2997 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2998 assert(dyn_idx < dynamicOffsetCount);
2999
3000 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3001 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3002 dst[0] = va;
3003 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3004 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3005 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3009 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3010 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3011 cmd_buffer->push_constant_stages |=
3012 set->layout->dynamic_shader_stages;
3013 }
3014 }
3015 }
3016
3017 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3018 struct radv_descriptor_set *set,
3019 struct radv_descriptor_set_layout *layout,
3020 VkPipelineBindPoint bind_point)
3021 {
3022 struct radv_descriptor_state *descriptors_state =
3023 radv_get_descriptors_state(cmd_buffer, bind_point);
3024 set->size = layout->size;
3025 set->layout = layout;
3026
3027 if (descriptors_state->push_set.capacity < set->size) {
3028 size_t new_size = MAX2(set->size, 1024);
3029 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3030 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3031
3032 free(set->mapped_ptr);
3033 set->mapped_ptr = malloc(new_size);
3034
3035 if (!set->mapped_ptr) {
3036 descriptors_state->push_set.capacity = 0;
3037 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3038 return false;
3039 }
3040
3041 descriptors_state->push_set.capacity = new_size;
3042 }
3043
3044 return true;
3045 }
3046
3047 void radv_meta_push_descriptor_set(
3048 struct radv_cmd_buffer* cmd_buffer,
3049 VkPipelineBindPoint pipelineBindPoint,
3050 VkPipelineLayout _layout,
3051 uint32_t set,
3052 uint32_t descriptorWriteCount,
3053 const VkWriteDescriptorSet* pDescriptorWrites)
3054 {
3055 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3056 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3057 unsigned bo_offset;
3058
3059 assert(set == 0);
3060 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3061
3062 push_set->size = layout->set[set].layout->size;
3063 push_set->layout = layout->set[set].layout;
3064
3065 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3066 &bo_offset,
3067 (void**) &push_set->mapped_ptr))
3068 return;
3069
3070 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3071 push_set->va += bo_offset;
3072
3073 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3074 radv_descriptor_set_to_handle(push_set),
3075 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3076
3077 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3078 }
3079
3080 void radv_CmdPushDescriptorSetKHR(
3081 VkCommandBuffer commandBuffer,
3082 VkPipelineBindPoint pipelineBindPoint,
3083 VkPipelineLayout _layout,
3084 uint32_t set,
3085 uint32_t descriptorWriteCount,
3086 const VkWriteDescriptorSet* pDescriptorWrites)
3087 {
3088 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3089 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3090 struct radv_descriptor_state *descriptors_state =
3091 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3092 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3093
3094 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3095
3096 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3097 layout->set[set].layout,
3098 pipelineBindPoint))
3099 return;
3100
3101 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3102 radv_descriptor_set_to_handle(push_set),
3103 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3104
3105 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3106 descriptors_state->push_dirty = true;
3107 }
3108
3109 void radv_CmdPushDescriptorSetWithTemplateKHR(
3110 VkCommandBuffer commandBuffer,
3111 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3112 VkPipelineLayout _layout,
3113 uint32_t set,
3114 const void* pData)
3115 {
3116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3117 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3118 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3119 struct radv_descriptor_state *descriptors_state =
3120 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3121 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3122
3123 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3124
3125 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3126 layout->set[set].layout,
3127 templ->bind_point))
3128 return;
3129
3130 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3131 descriptorUpdateTemplate, pData);
3132
3133 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3134 descriptors_state->push_dirty = true;
3135 }
3136
3137 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3138 VkPipelineLayout layout,
3139 VkShaderStageFlags stageFlags,
3140 uint32_t offset,
3141 uint32_t size,
3142 const void* pValues)
3143 {
3144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3145 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3146 cmd_buffer->push_constant_stages |= stageFlags;
3147 }
3148
3149 VkResult radv_EndCommandBuffer(
3150 VkCommandBuffer commandBuffer)
3151 {
3152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3153
3154 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3155 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3156 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3157
3158 /* Make sure to sync all pending active queries at the end of
3159 * command buffer.
3160 */
3161 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3162
3163 si_emit_cache_flush(cmd_buffer);
3164 }
3165
3166 /* Make sure CP DMA is idle at the end of IBs because the kernel
3167 * doesn't wait for it.
3168 */
3169 si_cp_dma_wait_for_idle(cmd_buffer);
3170
3171 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3172
3173 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3174 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3175
3176 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3177
3178 return cmd_buffer->record_result;
3179 }
3180
3181 static void
3182 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3183 {
3184 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3185
3186 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3187 return;
3188
3189 assert(!pipeline->ctx_cs.cdw);
3190
3191 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3192
3193 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3194 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3195
3196 cmd_buffer->compute_scratch_size_needed =
3197 MAX2(cmd_buffer->compute_scratch_size_needed,
3198 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3199
3200 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3201 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3202
3203 if (unlikely(cmd_buffer->device->trace_bo))
3204 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3205 }
3206
3207 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3208 VkPipelineBindPoint bind_point)
3209 {
3210 struct radv_descriptor_state *descriptors_state =
3211 radv_get_descriptors_state(cmd_buffer, bind_point);
3212
3213 descriptors_state->dirty |= descriptors_state->valid;
3214 }
3215
3216 void radv_CmdBindPipeline(
3217 VkCommandBuffer commandBuffer,
3218 VkPipelineBindPoint pipelineBindPoint,
3219 VkPipeline _pipeline)
3220 {
3221 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3222 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3223
3224 switch (pipelineBindPoint) {
3225 case VK_PIPELINE_BIND_POINT_COMPUTE:
3226 if (cmd_buffer->state.compute_pipeline == pipeline)
3227 return;
3228 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3229
3230 cmd_buffer->state.compute_pipeline = pipeline;
3231 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3232 break;
3233 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3234 if (cmd_buffer->state.pipeline == pipeline)
3235 return;
3236 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3237
3238 cmd_buffer->state.pipeline = pipeline;
3239 if (!pipeline)
3240 break;
3241
3242 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3243 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3244
3245 /* the new vertex shader might not have the same user regs */
3246 cmd_buffer->state.last_first_instance = -1;
3247 cmd_buffer->state.last_vertex_offset = -1;
3248
3249 /* Prefetch all pipeline shaders at first draw time. */
3250 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3251
3252 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3253 radv_bind_streamout_state(cmd_buffer, pipeline);
3254
3255 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3256 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3257 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3258 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3259
3260 if (radv_pipeline_has_tess(pipeline))
3261 cmd_buffer->tess_rings_needed = true;
3262 break;
3263 default:
3264 assert(!"invalid bind point");
3265 break;
3266 }
3267 }
3268
3269 void radv_CmdSetViewport(
3270 VkCommandBuffer commandBuffer,
3271 uint32_t firstViewport,
3272 uint32_t viewportCount,
3273 const VkViewport* pViewports)
3274 {
3275 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3276 struct radv_cmd_state *state = &cmd_buffer->state;
3277 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3278
3279 assert(firstViewport < MAX_VIEWPORTS);
3280 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3281
3282 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3283 pViewports, viewportCount * sizeof(*pViewports))) {
3284 return;
3285 }
3286
3287 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3288 viewportCount * sizeof(*pViewports));
3289
3290 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3291 }
3292
3293 void radv_CmdSetScissor(
3294 VkCommandBuffer commandBuffer,
3295 uint32_t firstScissor,
3296 uint32_t scissorCount,
3297 const VkRect2D* pScissors)
3298 {
3299 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3300 struct radv_cmd_state *state = &cmd_buffer->state;
3301 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3302
3303 assert(firstScissor < MAX_SCISSORS);
3304 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3305
3306 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3307 scissorCount * sizeof(*pScissors))) {
3308 return;
3309 }
3310
3311 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3312 scissorCount * sizeof(*pScissors));
3313
3314 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3315 }
3316
3317 void radv_CmdSetLineWidth(
3318 VkCommandBuffer commandBuffer,
3319 float lineWidth)
3320 {
3321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3322
3323 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3324 return;
3325
3326 cmd_buffer->state.dynamic.line_width = lineWidth;
3327 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3328 }
3329
3330 void radv_CmdSetDepthBias(
3331 VkCommandBuffer commandBuffer,
3332 float depthBiasConstantFactor,
3333 float depthBiasClamp,
3334 float depthBiasSlopeFactor)
3335 {
3336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3337 struct radv_cmd_state *state = &cmd_buffer->state;
3338
3339 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3340 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3341 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3342 return;
3343 }
3344
3345 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3346 state->dynamic.depth_bias.clamp = depthBiasClamp;
3347 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3348
3349 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3350 }
3351
3352 void radv_CmdSetBlendConstants(
3353 VkCommandBuffer commandBuffer,
3354 const float blendConstants[4])
3355 {
3356 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3357 struct radv_cmd_state *state = &cmd_buffer->state;
3358
3359 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3360 return;
3361
3362 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3363
3364 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3365 }
3366
3367 void radv_CmdSetDepthBounds(
3368 VkCommandBuffer commandBuffer,
3369 float minDepthBounds,
3370 float maxDepthBounds)
3371 {
3372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3373 struct radv_cmd_state *state = &cmd_buffer->state;
3374
3375 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3376 state->dynamic.depth_bounds.max == maxDepthBounds) {
3377 return;
3378 }
3379
3380 state->dynamic.depth_bounds.min = minDepthBounds;
3381 state->dynamic.depth_bounds.max = maxDepthBounds;
3382
3383 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3384 }
3385
3386 void radv_CmdSetStencilCompareMask(
3387 VkCommandBuffer commandBuffer,
3388 VkStencilFaceFlags faceMask,
3389 uint32_t compareMask)
3390 {
3391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3392 struct radv_cmd_state *state = &cmd_buffer->state;
3393 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3394 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3395
3396 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3397 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3398 return;
3399 }
3400
3401 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3402 state->dynamic.stencil_compare_mask.front = compareMask;
3403 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3404 state->dynamic.stencil_compare_mask.back = compareMask;
3405
3406 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3407 }
3408
3409 void radv_CmdSetStencilWriteMask(
3410 VkCommandBuffer commandBuffer,
3411 VkStencilFaceFlags faceMask,
3412 uint32_t writeMask)
3413 {
3414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3415 struct radv_cmd_state *state = &cmd_buffer->state;
3416 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3417 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3418
3419 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3420 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3421 return;
3422 }
3423
3424 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3425 state->dynamic.stencil_write_mask.front = writeMask;
3426 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3427 state->dynamic.stencil_write_mask.back = writeMask;
3428
3429 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3430 }
3431
3432 void radv_CmdSetStencilReference(
3433 VkCommandBuffer commandBuffer,
3434 VkStencilFaceFlags faceMask,
3435 uint32_t reference)
3436 {
3437 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3438 struct radv_cmd_state *state = &cmd_buffer->state;
3439 bool front_same = state->dynamic.stencil_reference.front == reference;
3440 bool back_same = state->dynamic.stencil_reference.back == reference;
3441
3442 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3443 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3444 return;
3445 }
3446
3447 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3448 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3449 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3450 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3451
3452 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3453 }
3454
3455 void radv_CmdSetDiscardRectangleEXT(
3456 VkCommandBuffer commandBuffer,
3457 uint32_t firstDiscardRectangle,
3458 uint32_t discardRectangleCount,
3459 const VkRect2D* pDiscardRectangles)
3460 {
3461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3462 struct radv_cmd_state *state = &cmd_buffer->state;
3463 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3464
3465 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3466 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3467
3468 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3469 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3470 return;
3471 }
3472
3473 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3474 pDiscardRectangles, discardRectangleCount);
3475
3476 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3477 }
3478
3479 void radv_CmdSetSampleLocationsEXT(
3480 VkCommandBuffer commandBuffer,
3481 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3482 {
3483 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3484 struct radv_cmd_state *state = &cmd_buffer->state;
3485
3486 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3487
3488 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3489 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3490 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3491 typed_memcpy(&state->dynamic.sample_location.locations[0],
3492 pSampleLocationsInfo->pSampleLocations,
3493 pSampleLocationsInfo->sampleLocationsCount);
3494
3495 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3496 }
3497
3498 void radv_CmdExecuteCommands(
3499 VkCommandBuffer commandBuffer,
3500 uint32_t commandBufferCount,
3501 const VkCommandBuffer* pCmdBuffers)
3502 {
3503 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3504
3505 assert(commandBufferCount > 0);
3506
3507 /* Emit pending flushes on primary prior to executing secondary */
3508 si_emit_cache_flush(primary);
3509
3510 for (uint32_t i = 0; i < commandBufferCount; i++) {
3511 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3512
3513 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3514 secondary->scratch_size_needed);
3515 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3516 secondary->compute_scratch_size_needed);
3517
3518 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3519 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3520 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3521 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3522 if (secondary->tess_rings_needed)
3523 primary->tess_rings_needed = true;
3524 if (secondary->sample_positions_needed)
3525 primary->sample_positions_needed = true;
3526
3527 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3528
3529
3530 /* When the secondary command buffer is compute only we don't
3531 * need to re-emit the current graphics pipeline.
3532 */
3533 if (secondary->state.emitted_pipeline) {
3534 primary->state.emitted_pipeline =
3535 secondary->state.emitted_pipeline;
3536 }
3537
3538 /* When the secondary command buffer is graphics only we don't
3539 * need to re-emit the current compute pipeline.
3540 */
3541 if (secondary->state.emitted_compute_pipeline) {
3542 primary->state.emitted_compute_pipeline =
3543 secondary->state.emitted_compute_pipeline;
3544 }
3545
3546 /* Only re-emit the draw packets when needed. */
3547 if (secondary->state.last_primitive_reset_en != -1) {
3548 primary->state.last_primitive_reset_en =
3549 secondary->state.last_primitive_reset_en;
3550 }
3551
3552 if (secondary->state.last_primitive_reset_index) {
3553 primary->state.last_primitive_reset_index =
3554 secondary->state.last_primitive_reset_index;
3555 }
3556
3557 if (secondary->state.last_ia_multi_vgt_param) {
3558 primary->state.last_ia_multi_vgt_param =
3559 secondary->state.last_ia_multi_vgt_param;
3560 }
3561
3562 primary->state.last_first_instance = secondary->state.last_first_instance;
3563 primary->state.last_num_instances = secondary->state.last_num_instances;
3564 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3565
3566 if (secondary->state.last_index_type != -1) {
3567 primary->state.last_index_type =
3568 secondary->state.last_index_type;
3569 }
3570 }
3571
3572 /* After executing commands from secondary buffers we have to dirty
3573 * some states.
3574 */
3575 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3576 RADV_CMD_DIRTY_INDEX_BUFFER |
3577 RADV_CMD_DIRTY_DYNAMIC_ALL;
3578 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3579 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3580 }
3581
3582 VkResult radv_CreateCommandPool(
3583 VkDevice _device,
3584 const VkCommandPoolCreateInfo* pCreateInfo,
3585 const VkAllocationCallbacks* pAllocator,
3586 VkCommandPool* pCmdPool)
3587 {
3588 RADV_FROM_HANDLE(radv_device, device, _device);
3589 struct radv_cmd_pool *pool;
3590
3591 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3592 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3593 if (pool == NULL)
3594 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3595
3596 if (pAllocator)
3597 pool->alloc = *pAllocator;
3598 else
3599 pool->alloc = device->alloc;
3600
3601 list_inithead(&pool->cmd_buffers);
3602 list_inithead(&pool->free_cmd_buffers);
3603
3604 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3605
3606 *pCmdPool = radv_cmd_pool_to_handle(pool);
3607
3608 return VK_SUCCESS;
3609
3610 }
3611
3612 void radv_DestroyCommandPool(
3613 VkDevice _device,
3614 VkCommandPool commandPool,
3615 const VkAllocationCallbacks* pAllocator)
3616 {
3617 RADV_FROM_HANDLE(radv_device, device, _device);
3618 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3619
3620 if (!pool)
3621 return;
3622
3623 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3624 &pool->cmd_buffers, pool_link) {
3625 radv_cmd_buffer_destroy(cmd_buffer);
3626 }
3627
3628 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3629 &pool->free_cmd_buffers, pool_link) {
3630 radv_cmd_buffer_destroy(cmd_buffer);
3631 }
3632
3633 vk_free2(&device->alloc, pAllocator, pool);
3634 }
3635
3636 VkResult radv_ResetCommandPool(
3637 VkDevice device,
3638 VkCommandPool commandPool,
3639 VkCommandPoolResetFlags flags)
3640 {
3641 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3642 VkResult result;
3643
3644 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3645 &pool->cmd_buffers, pool_link) {
3646 result = radv_reset_cmd_buffer(cmd_buffer);
3647 if (result != VK_SUCCESS)
3648 return result;
3649 }
3650
3651 return VK_SUCCESS;
3652 }
3653
3654 void radv_TrimCommandPool(
3655 VkDevice device,
3656 VkCommandPool commandPool,
3657 VkCommandPoolTrimFlags flags)
3658 {
3659 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3660
3661 if (!pool)
3662 return;
3663
3664 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3665 &pool->free_cmd_buffers, pool_link) {
3666 radv_cmd_buffer_destroy(cmd_buffer);
3667 }
3668 }
3669
3670 static uint32_t
3671 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3672 {
3673 struct radv_cmd_state *state = &cmd_buffer->state;
3674 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3675
3676 /* The id of this subpass shouldn't exceed the number of subpasses in
3677 * this render pass minus 1.
3678 */
3679 assert(subpass_id < state->pass->subpass_count);
3680 return subpass_id;
3681 }
3682
3683 static void
3684 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3685 uint32_t subpass_id)
3686 {
3687 struct radv_cmd_state *state = &cmd_buffer->state;
3688 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3689
3690 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3691 cmd_buffer->cs, 4096);
3692
3693 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3694
3695 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3696 const uint32_t a = subpass->attachments[i].attachment;
3697 if (a == VK_ATTACHMENT_UNUSED)
3698 continue;
3699
3700 radv_handle_subpass_image_transition(cmd_buffer,
3701 subpass->attachments[i]);
3702 }
3703
3704 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3705 radv_cmd_buffer_clear_subpass(cmd_buffer);
3706
3707 assert(cmd_buffer->cs->cdw <= cdw_max);
3708 }
3709
3710 static void
3711 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3712 {
3713 struct radv_cmd_state *state = &cmd_buffer->state;
3714 const struct radv_subpass *subpass = state->subpass;
3715 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3716
3717 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3718
3719 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3720 const uint32_t a = subpass->attachments[i].attachment;
3721 if (a == VK_ATTACHMENT_UNUSED)
3722 continue;
3723
3724 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3725 continue;
3726
3727 VkImageLayout layout = state->pass->attachments[a].final_layout;
3728 radv_handle_subpass_image_transition(cmd_buffer,
3729 (struct radv_subpass_attachment){a, layout});
3730 }
3731 }
3732
3733 void radv_CmdBeginRenderPass(
3734 VkCommandBuffer commandBuffer,
3735 const VkRenderPassBeginInfo* pRenderPassBegin,
3736 VkSubpassContents contents)
3737 {
3738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3739 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3740 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3741 VkResult result;
3742
3743 cmd_buffer->state.framebuffer = framebuffer;
3744 cmd_buffer->state.pass = pass;
3745 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3746
3747 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3748 if (result != VK_SUCCESS)
3749 return;
3750
3751 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3752 }
3753
3754 void radv_CmdBeginRenderPass2KHR(
3755 VkCommandBuffer commandBuffer,
3756 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3757 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3758 {
3759 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3760 pSubpassBeginInfo->contents);
3761 }
3762
3763 void radv_CmdNextSubpass(
3764 VkCommandBuffer commandBuffer,
3765 VkSubpassContents contents)
3766 {
3767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3768
3769 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3770 radv_cmd_buffer_end_subpass(cmd_buffer);
3771 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3772 }
3773
3774 void radv_CmdNextSubpass2KHR(
3775 VkCommandBuffer commandBuffer,
3776 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3777 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3778 {
3779 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3780 }
3781
3782 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3783 {
3784 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3785 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3786 if (!radv_get_shader(pipeline, stage))
3787 continue;
3788
3789 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3790 if (loc->sgpr_idx == -1)
3791 continue;
3792 uint32_t base_reg = pipeline->user_data_0[stage];
3793 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3794
3795 }
3796 if (pipeline->gs_copy_shader) {
3797 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3798 if (loc->sgpr_idx != -1) {
3799 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3800 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3801 }
3802 }
3803 }
3804
3805 static void
3806 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3807 uint32_t vertex_count,
3808 bool use_opaque)
3809 {
3810 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3811 radeon_emit(cmd_buffer->cs, vertex_count);
3812 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3813 S_0287F0_USE_OPAQUE(use_opaque));
3814 }
3815
3816 static void
3817 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3818 uint64_t index_va,
3819 uint32_t index_count)
3820 {
3821 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3822 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3823 radeon_emit(cmd_buffer->cs, index_va);
3824 radeon_emit(cmd_buffer->cs, index_va >> 32);
3825 radeon_emit(cmd_buffer->cs, index_count);
3826 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3827 }
3828
3829 static void
3830 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3831 bool indexed,
3832 uint32_t draw_count,
3833 uint64_t count_va,
3834 uint32_t stride)
3835 {
3836 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3837 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3838 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3839 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3840 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3841 bool predicating = cmd_buffer->state.predicating;
3842 assert(base_reg);
3843
3844 /* just reset draw state for vertex data */
3845 cmd_buffer->state.last_first_instance = -1;
3846 cmd_buffer->state.last_num_instances = -1;
3847 cmd_buffer->state.last_vertex_offset = -1;
3848
3849 if (draw_count == 1 && !count_va && !draw_id_enable) {
3850 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3851 PKT3_DRAW_INDIRECT, 3, predicating));
3852 radeon_emit(cs, 0);
3853 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3854 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3855 radeon_emit(cs, di_src_sel);
3856 } else {
3857 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3858 PKT3_DRAW_INDIRECT_MULTI,
3859 8, predicating));
3860 radeon_emit(cs, 0);
3861 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3862 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3863 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3864 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3865 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3866 radeon_emit(cs, draw_count); /* count */
3867 radeon_emit(cs, count_va); /* count_addr */
3868 radeon_emit(cs, count_va >> 32);
3869 radeon_emit(cs, stride); /* stride */
3870 radeon_emit(cs, di_src_sel);
3871 }
3872 }
3873
3874 static void
3875 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3876 const struct radv_draw_info *info)
3877 {
3878 struct radv_cmd_state *state = &cmd_buffer->state;
3879 struct radeon_winsys *ws = cmd_buffer->device->ws;
3880 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3881
3882 if (info->indirect) {
3883 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3884 uint64_t count_va = 0;
3885
3886 va += info->indirect->offset + info->indirect_offset;
3887
3888 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3889
3890 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3891 radeon_emit(cs, 1);
3892 radeon_emit(cs, va);
3893 radeon_emit(cs, va >> 32);
3894
3895 if (info->count_buffer) {
3896 count_va = radv_buffer_get_va(info->count_buffer->bo);
3897 count_va += info->count_buffer->offset +
3898 info->count_buffer_offset;
3899
3900 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3901 }
3902
3903 if (!state->subpass->view_mask) {
3904 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3905 info->indexed,
3906 info->count,
3907 count_va,
3908 info->stride);
3909 } else {
3910 unsigned i;
3911 for_each_bit(i, state->subpass->view_mask) {
3912 radv_emit_view_index(cmd_buffer, i);
3913
3914 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3915 info->indexed,
3916 info->count,
3917 count_va,
3918 info->stride);
3919 }
3920 }
3921 } else {
3922 assert(state->pipeline->graphics.vtx_base_sgpr);
3923
3924 if (info->vertex_offset != state->last_vertex_offset ||
3925 info->first_instance != state->last_first_instance) {
3926 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3927 state->pipeline->graphics.vtx_emit_num);
3928
3929 radeon_emit(cs, info->vertex_offset);
3930 radeon_emit(cs, info->first_instance);
3931 if (state->pipeline->graphics.vtx_emit_num == 3)
3932 radeon_emit(cs, 0);
3933 state->last_first_instance = info->first_instance;
3934 state->last_vertex_offset = info->vertex_offset;
3935 }
3936
3937 if (state->last_num_instances != info->instance_count) {
3938 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3939 radeon_emit(cs, info->instance_count);
3940 state->last_num_instances = info->instance_count;
3941 }
3942
3943 if (info->indexed) {
3944 int index_size = state->index_type ? 4 : 2;
3945 uint64_t index_va;
3946
3947 index_va = state->index_va;
3948 index_va += info->first_index * index_size;
3949
3950 if (!state->subpass->view_mask) {
3951 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3952 index_va,
3953 info->count);
3954 } else {
3955 unsigned i;
3956 for_each_bit(i, state->subpass->view_mask) {
3957 radv_emit_view_index(cmd_buffer, i);
3958
3959 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3960 index_va,
3961 info->count);
3962 }
3963 }
3964 } else {
3965 if (!state->subpass->view_mask) {
3966 radv_cs_emit_draw_packet(cmd_buffer,
3967 info->count,
3968 !!info->strmout_buffer);
3969 } else {
3970 unsigned i;
3971 for_each_bit(i, state->subpass->view_mask) {
3972 radv_emit_view_index(cmd_buffer, i);
3973
3974 radv_cs_emit_draw_packet(cmd_buffer,
3975 info->count,
3976 !!info->strmout_buffer);
3977 }
3978 }
3979 }
3980 }
3981 }
3982
3983 /*
3984 * Vega and raven have a bug which triggers if there are multiple context
3985 * register contexts active at the same time with different scissor values.
3986 *
3987 * There are two possible workarounds:
3988 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3989 * there is only ever 1 active set of scissor values at the same time.
3990 *
3991 * 2) Whenever the hardware switches contexts we have to set the scissor
3992 * registers again even if it is a noop. That way the new context gets
3993 * the correct scissor values.
3994 *
3995 * This implements option 2. radv_need_late_scissor_emission needs to
3996 * return true on affected HW if radv_emit_all_graphics_states sets
3997 * any context registers.
3998 */
3999 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4000 const struct radv_draw_info *info)
4001 {
4002 struct radv_cmd_state *state = &cmd_buffer->state;
4003
4004 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4005 return false;
4006
4007 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4008 return true;
4009
4010 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4011
4012 /* Index, vertex and streamout buffers don't change context regs, and
4013 * pipeline is already handled.
4014 */
4015 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4016 RADV_CMD_DIRTY_VERTEX_BUFFER |
4017 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4018 RADV_CMD_DIRTY_PIPELINE);
4019
4020 if (cmd_buffer->state.dirty & used_states)
4021 return true;
4022
4023 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4024 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4025 return true;
4026
4027 return false;
4028 }
4029
4030 static void
4031 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4032 const struct radv_draw_info *info)
4033 {
4034 bool late_scissor_emission;
4035
4036 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4037 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4038 radv_emit_rbplus_state(cmd_buffer);
4039
4040 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4041 radv_emit_graphics_pipeline(cmd_buffer);
4042
4043 /* This should be before the cmd_buffer->state.dirty is cleared
4044 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4045 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4046 late_scissor_emission =
4047 radv_need_late_scissor_emission(cmd_buffer, info);
4048
4049 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4050 radv_emit_framebuffer_state(cmd_buffer);
4051
4052 if (info->indexed) {
4053 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4054 radv_emit_index_buffer(cmd_buffer);
4055 } else {
4056 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4057 * so the state must be re-emitted before the next indexed
4058 * draw.
4059 */
4060 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4061 cmd_buffer->state.last_index_type = -1;
4062 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4063 }
4064 }
4065
4066 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4067
4068 radv_emit_draw_registers(cmd_buffer, info);
4069
4070 if (late_scissor_emission)
4071 radv_emit_scissor(cmd_buffer);
4072 }
4073
4074 static void
4075 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4076 const struct radv_draw_info *info)
4077 {
4078 struct radeon_info *rad_info =
4079 &cmd_buffer->device->physical_device->rad_info;
4080 bool has_prefetch =
4081 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4082 bool pipeline_is_dirty =
4083 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4084 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4085
4086 MAYBE_UNUSED unsigned cdw_max =
4087 radeon_check_space(cmd_buffer->device->ws,
4088 cmd_buffer->cs, 4096);
4089
4090 if (likely(!info->indirect)) {
4091 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4092 * no workaround for indirect draws, but we can at least skip
4093 * direct draws.
4094 */
4095 if (unlikely(!info->instance_count))
4096 return;
4097
4098 /* Handle count == 0. */
4099 if (unlikely(!info->count && !info->strmout_buffer))
4100 return;
4101 }
4102
4103 /* Use optimal packet order based on whether we need to sync the
4104 * pipeline.
4105 */
4106 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4107 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4108 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4109 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4110 /* If we have to wait for idle, set all states first, so that
4111 * all SET packets are processed in parallel with previous draw
4112 * calls. Then upload descriptors, set shader pointers, and
4113 * draw, and prefetch at the end. This ensures that the time
4114 * the CUs are idle is very short. (there are only SET_SH
4115 * packets between the wait and the draw)
4116 */
4117 radv_emit_all_graphics_states(cmd_buffer, info);
4118 si_emit_cache_flush(cmd_buffer);
4119 /* <-- CUs are idle here --> */
4120
4121 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4122
4123 radv_emit_draw_packets(cmd_buffer, info);
4124 /* <-- CUs are busy here --> */
4125
4126 /* Start prefetches after the draw has been started. Both will
4127 * run in parallel, but starting the draw first is more
4128 * important.
4129 */
4130 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4131 radv_emit_prefetch_L2(cmd_buffer,
4132 cmd_buffer->state.pipeline, false);
4133 }
4134 } else {
4135 /* If we don't wait for idle, start prefetches first, then set
4136 * states, and draw at the end.
4137 */
4138 si_emit_cache_flush(cmd_buffer);
4139
4140 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4141 /* Only prefetch the vertex shader and VBO descriptors
4142 * in order to start the draw as soon as possible.
4143 */
4144 radv_emit_prefetch_L2(cmd_buffer,
4145 cmd_buffer->state.pipeline, true);
4146 }
4147
4148 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4149
4150 radv_emit_all_graphics_states(cmd_buffer, info);
4151 radv_emit_draw_packets(cmd_buffer, info);
4152
4153 /* Prefetch the remaining shaders after the draw has been
4154 * started.
4155 */
4156 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4157 radv_emit_prefetch_L2(cmd_buffer,
4158 cmd_buffer->state.pipeline, false);
4159 }
4160 }
4161
4162 /* Workaround for a VGT hang when streamout is enabled.
4163 * It must be done after drawing.
4164 */
4165 if (cmd_buffer->state.streamout.streamout_enabled &&
4166 (rad_info->family == CHIP_HAWAII ||
4167 rad_info->family == CHIP_TONGA ||
4168 rad_info->family == CHIP_FIJI)) {
4169 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4170 }
4171
4172 assert(cmd_buffer->cs->cdw <= cdw_max);
4173 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4174 }
4175
4176 void radv_CmdDraw(
4177 VkCommandBuffer commandBuffer,
4178 uint32_t vertexCount,
4179 uint32_t instanceCount,
4180 uint32_t firstVertex,
4181 uint32_t firstInstance)
4182 {
4183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4184 struct radv_draw_info info = {};
4185
4186 info.count = vertexCount;
4187 info.instance_count = instanceCount;
4188 info.first_instance = firstInstance;
4189 info.vertex_offset = firstVertex;
4190
4191 radv_draw(cmd_buffer, &info);
4192 }
4193
4194 void radv_CmdDrawIndexed(
4195 VkCommandBuffer commandBuffer,
4196 uint32_t indexCount,
4197 uint32_t instanceCount,
4198 uint32_t firstIndex,
4199 int32_t vertexOffset,
4200 uint32_t firstInstance)
4201 {
4202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4203 struct radv_draw_info info = {};
4204
4205 info.indexed = true;
4206 info.count = indexCount;
4207 info.instance_count = instanceCount;
4208 info.first_index = firstIndex;
4209 info.vertex_offset = vertexOffset;
4210 info.first_instance = firstInstance;
4211
4212 radv_draw(cmd_buffer, &info);
4213 }
4214
4215 void radv_CmdDrawIndirect(
4216 VkCommandBuffer commandBuffer,
4217 VkBuffer _buffer,
4218 VkDeviceSize offset,
4219 uint32_t drawCount,
4220 uint32_t stride)
4221 {
4222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4223 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4224 struct radv_draw_info info = {};
4225
4226 info.count = drawCount;
4227 info.indirect = buffer;
4228 info.indirect_offset = offset;
4229 info.stride = stride;
4230
4231 radv_draw(cmd_buffer, &info);
4232 }
4233
4234 void radv_CmdDrawIndexedIndirect(
4235 VkCommandBuffer commandBuffer,
4236 VkBuffer _buffer,
4237 VkDeviceSize offset,
4238 uint32_t drawCount,
4239 uint32_t stride)
4240 {
4241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4242 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4243 struct radv_draw_info info = {};
4244
4245 info.indexed = true;
4246 info.count = drawCount;
4247 info.indirect = buffer;
4248 info.indirect_offset = offset;
4249 info.stride = stride;
4250
4251 radv_draw(cmd_buffer, &info);
4252 }
4253
4254 void radv_CmdDrawIndirectCountKHR(
4255 VkCommandBuffer commandBuffer,
4256 VkBuffer _buffer,
4257 VkDeviceSize offset,
4258 VkBuffer _countBuffer,
4259 VkDeviceSize countBufferOffset,
4260 uint32_t maxDrawCount,
4261 uint32_t stride)
4262 {
4263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4264 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4265 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4266 struct radv_draw_info info = {};
4267
4268 info.count = maxDrawCount;
4269 info.indirect = buffer;
4270 info.indirect_offset = offset;
4271 info.count_buffer = count_buffer;
4272 info.count_buffer_offset = countBufferOffset;
4273 info.stride = stride;
4274
4275 radv_draw(cmd_buffer, &info);
4276 }
4277
4278 void radv_CmdDrawIndexedIndirectCountKHR(
4279 VkCommandBuffer commandBuffer,
4280 VkBuffer _buffer,
4281 VkDeviceSize offset,
4282 VkBuffer _countBuffer,
4283 VkDeviceSize countBufferOffset,
4284 uint32_t maxDrawCount,
4285 uint32_t stride)
4286 {
4287 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4288 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4289 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4290 struct radv_draw_info info = {};
4291
4292 info.indexed = true;
4293 info.count = maxDrawCount;
4294 info.indirect = buffer;
4295 info.indirect_offset = offset;
4296 info.count_buffer = count_buffer;
4297 info.count_buffer_offset = countBufferOffset;
4298 info.stride = stride;
4299
4300 radv_draw(cmd_buffer, &info);
4301 }
4302
4303 struct radv_dispatch_info {
4304 /**
4305 * Determine the layout of the grid (in block units) to be used.
4306 */
4307 uint32_t blocks[3];
4308
4309 /**
4310 * A starting offset for the grid. If unaligned is set, the offset
4311 * must still be aligned.
4312 */
4313 uint32_t offsets[3];
4314 /**
4315 * Whether it's an unaligned compute dispatch.
4316 */
4317 bool unaligned;
4318
4319 /**
4320 * Indirect compute parameters resource.
4321 */
4322 struct radv_buffer *indirect;
4323 uint64_t indirect_offset;
4324 };
4325
4326 static void
4327 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4328 const struct radv_dispatch_info *info)
4329 {
4330 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4331 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4332 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4333 struct radeon_winsys *ws = cmd_buffer->device->ws;
4334 bool predicating = cmd_buffer->state.predicating;
4335 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4336 struct radv_userdata_info *loc;
4337
4338 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4339 AC_UD_CS_GRID_SIZE);
4340
4341 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4342
4343 if (info->indirect) {
4344 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4345
4346 va += info->indirect->offset + info->indirect_offset;
4347
4348 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4349
4350 if (loc->sgpr_idx != -1) {
4351 for (unsigned i = 0; i < 3; ++i) {
4352 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4353 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4354 COPY_DATA_DST_SEL(COPY_DATA_REG));
4355 radeon_emit(cs, (va + 4 * i));
4356 radeon_emit(cs, (va + 4 * i) >> 32);
4357 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4358 + loc->sgpr_idx * 4) >> 2) + i);
4359 radeon_emit(cs, 0);
4360 }
4361 }
4362
4363 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4364 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4365 PKT3_SHADER_TYPE_S(1));
4366 radeon_emit(cs, va);
4367 radeon_emit(cs, va >> 32);
4368 radeon_emit(cs, dispatch_initiator);
4369 } else {
4370 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4371 PKT3_SHADER_TYPE_S(1));
4372 radeon_emit(cs, 1);
4373 radeon_emit(cs, va);
4374 radeon_emit(cs, va >> 32);
4375
4376 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4377 PKT3_SHADER_TYPE_S(1));
4378 radeon_emit(cs, 0);
4379 radeon_emit(cs, dispatch_initiator);
4380 }
4381 } else {
4382 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4383 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4384
4385 if (info->unaligned) {
4386 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4387 unsigned remainder[3];
4388
4389 /* If aligned, these should be an entire block size,
4390 * not 0.
4391 */
4392 remainder[0] = blocks[0] + cs_block_size[0] -
4393 align_u32_npot(blocks[0], cs_block_size[0]);
4394 remainder[1] = blocks[1] + cs_block_size[1] -
4395 align_u32_npot(blocks[1], cs_block_size[1]);
4396 remainder[2] = blocks[2] + cs_block_size[2] -
4397 align_u32_npot(blocks[2], cs_block_size[2]);
4398
4399 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4400 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4401 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4402
4403 for(unsigned i = 0; i < 3; ++i) {
4404 assert(offsets[i] % cs_block_size[i] == 0);
4405 offsets[i] /= cs_block_size[i];
4406 }
4407
4408 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4409 radeon_emit(cs,
4410 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4411 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4412 radeon_emit(cs,
4413 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4414 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4415 radeon_emit(cs,
4416 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4417 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4418
4419 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4420 }
4421
4422 if (loc->sgpr_idx != -1) {
4423 assert(loc->num_sgprs == 3);
4424
4425 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4426 loc->sgpr_idx * 4, 3);
4427 radeon_emit(cs, blocks[0]);
4428 radeon_emit(cs, blocks[1]);
4429 radeon_emit(cs, blocks[2]);
4430 }
4431
4432 if (offsets[0] || offsets[1] || offsets[2]) {
4433 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4434 radeon_emit(cs, offsets[0]);
4435 radeon_emit(cs, offsets[1]);
4436 radeon_emit(cs, offsets[2]);
4437
4438 /* The blocks in the packet are not counts but end values. */
4439 for (unsigned i = 0; i < 3; ++i)
4440 blocks[i] += offsets[i];
4441 } else {
4442 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4443 }
4444
4445 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4446 PKT3_SHADER_TYPE_S(1));
4447 radeon_emit(cs, blocks[0]);
4448 radeon_emit(cs, blocks[1]);
4449 radeon_emit(cs, blocks[2]);
4450 radeon_emit(cs, dispatch_initiator);
4451 }
4452
4453 assert(cmd_buffer->cs->cdw <= cdw_max);
4454 }
4455
4456 static void
4457 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4458 {
4459 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4460 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4461 }
4462
4463 static void
4464 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4465 const struct radv_dispatch_info *info)
4466 {
4467 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4468 bool has_prefetch =
4469 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4470 bool pipeline_is_dirty = pipeline &&
4471 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4472
4473 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4474 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4475 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4476 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4477 /* If we have to wait for idle, set all states first, so that
4478 * all SET packets are processed in parallel with previous draw
4479 * calls. Then upload descriptors, set shader pointers, and
4480 * dispatch, and prefetch at the end. This ensures that the
4481 * time the CUs are idle is very short. (there are only SET_SH
4482 * packets between the wait and the draw)
4483 */
4484 radv_emit_compute_pipeline(cmd_buffer);
4485 si_emit_cache_flush(cmd_buffer);
4486 /* <-- CUs are idle here --> */
4487
4488 radv_upload_compute_shader_descriptors(cmd_buffer);
4489
4490 radv_emit_dispatch_packets(cmd_buffer, info);
4491 /* <-- CUs are busy here --> */
4492
4493 /* Start prefetches after the dispatch has been started. Both
4494 * will run in parallel, but starting the dispatch first is
4495 * more important.
4496 */
4497 if (has_prefetch && pipeline_is_dirty) {
4498 radv_emit_shader_prefetch(cmd_buffer,
4499 pipeline->shaders[MESA_SHADER_COMPUTE]);
4500 }
4501 } else {
4502 /* If we don't wait for idle, start prefetches first, then set
4503 * states, and dispatch at the end.
4504 */
4505 si_emit_cache_flush(cmd_buffer);
4506
4507 if (has_prefetch && pipeline_is_dirty) {
4508 radv_emit_shader_prefetch(cmd_buffer,
4509 pipeline->shaders[MESA_SHADER_COMPUTE]);
4510 }
4511
4512 radv_upload_compute_shader_descriptors(cmd_buffer);
4513
4514 radv_emit_compute_pipeline(cmd_buffer);
4515 radv_emit_dispatch_packets(cmd_buffer, info);
4516 }
4517
4518 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4519 }
4520
4521 void radv_CmdDispatchBase(
4522 VkCommandBuffer commandBuffer,
4523 uint32_t base_x,
4524 uint32_t base_y,
4525 uint32_t base_z,
4526 uint32_t x,
4527 uint32_t y,
4528 uint32_t z)
4529 {
4530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4531 struct radv_dispatch_info info = {};
4532
4533 info.blocks[0] = x;
4534 info.blocks[1] = y;
4535 info.blocks[2] = z;
4536
4537 info.offsets[0] = base_x;
4538 info.offsets[1] = base_y;
4539 info.offsets[2] = base_z;
4540 radv_dispatch(cmd_buffer, &info);
4541 }
4542
4543 void radv_CmdDispatch(
4544 VkCommandBuffer commandBuffer,
4545 uint32_t x,
4546 uint32_t y,
4547 uint32_t z)
4548 {
4549 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4550 }
4551
4552 void radv_CmdDispatchIndirect(
4553 VkCommandBuffer commandBuffer,
4554 VkBuffer _buffer,
4555 VkDeviceSize offset)
4556 {
4557 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4558 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4559 struct radv_dispatch_info info = {};
4560
4561 info.indirect = buffer;
4562 info.indirect_offset = offset;
4563
4564 radv_dispatch(cmd_buffer, &info);
4565 }
4566
4567 void radv_unaligned_dispatch(
4568 struct radv_cmd_buffer *cmd_buffer,
4569 uint32_t x,
4570 uint32_t y,
4571 uint32_t z)
4572 {
4573 struct radv_dispatch_info info = {};
4574
4575 info.blocks[0] = x;
4576 info.blocks[1] = y;
4577 info.blocks[2] = z;
4578 info.unaligned = 1;
4579
4580 radv_dispatch(cmd_buffer, &info);
4581 }
4582
4583 void radv_CmdEndRenderPass(
4584 VkCommandBuffer commandBuffer)
4585 {
4586 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4587
4588 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4589
4590 radv_cmd_buffer_end_subpass(cmd_buffer);
4591
4592 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4593
4594 cmd_buffer->state.pass = NULL;
4595 cmd_buffer->state.subpass = NULL;
4596 cmd_buffer->state.attachments = NULL;
4597 cmd_buffer->state.framebuffer = NULL;
4598 }
4599
4600 void radv_CmdEndRenderPass2KHR(
4601 VkCommandBuffer commandBuffer,
4602 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4603 {
4604 radv_CmdEndRenderPass(commandBuffer);
4605 }
4606
4607 /*
4608 * For HTILE we have the following interesting clear words:
4609 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4610 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4611 * 0xfffffff0: Clear depth to 1.0
4612 * 0x00000000: Clear depth to 0.0
4613 */
4614 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4615 struct radv_image *image,
4616 const VkImageSubresourceRange *range,
4617 uint32_t clear_word)
4618 {
4619 assert(range->baseMipLevel == 0);
4620 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4621 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4622 struct radv_cmd_state *state = &cmd_buffer->state;
4623 VkClearDepthStencilValue value = {};
4624
4625 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4627
4628 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4629
4630 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4631
4632 if (vk_format_is_stencil(image->vk_format))
4633 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4634
4635 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4636
4637 if (radv_image_is_tc_compat_htile(image)) {
4638 /* Initialize the TC-compat metada value to 0 because by
4639 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4640 * need have to conditionally update its value when performing
4641 * a fast depth clear.
4642 */
4643 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4644 }
4645 }
4646
4647 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4648 struct radv_image *image,
4649 VkImageLayout src_layout,
4650 VkImageLayout dst_layout,
4651 unsigned src_queue_mask,
4652 unsigned dst_queue_mask,
4653 const VkImageSubresourceRange *range)
4654 {
4655 if (!radv_image_has_htile(image))
4656 return;
4657
4658 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4659 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4660
4661 if (radv_layout_is_htile_compressed(image, dst_layout,
4662 dst_queue_mask)) {
4663 clear_value = 0;
4664 }
4665
4666 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4667 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4668 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4669 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4670 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4671 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4672 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4673 VkImageSubresourceRange local_range = *range;
4674 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4675 local_range.baseMipLevel = 0;
4676 local_range.levelCount = 1;
4677
4678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4679 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4680
4681 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4682
4683 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4684 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4685 }
4686 }
4687
4688 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4689 struct radv_image *image, uint32_t value)
4690 {
4691 struct radv_cmd_state *state = &cmd_buffer->state;
4692
4693 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4694 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4695
4696 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4697
4698 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4699 }
4700
4701 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4702 struct radv_image *image)
4703 {
4704 struct radv_cmd_state *state = &cmd_buffer->state;
4705 static const uint32_t fmask_clear_values[4] = {
4706 0x00000000,
4707 0x02020202,
4708 0xE4E4E4E4,
4709 0x76543210
4710 };
4711 uint32_t log2_samples = util_logbase2(image->info.samples);
4712 uint32_t value = fmask_clear_values[log2_samples];
4713
4714 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4715 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4716
4717 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4718
4719 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4720 }
4721
4722 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4723 struct radv_image *image, uint32_t value)
4724 {
4725 struct radv_cmd_state *state = &cmd_buffer->state;
4726
4727 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4728 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4729
4730 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4731
4732 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4733 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4734 }
4735
4736 /**
4737 * Initialize DCC/FMASK/CMASK metadata for a color image.
4738 */
4739 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4740 struct radv_image *image,
4741 VkImageLayout src_layout,
4742 VkImageLayout dst_layout,
4743 unsigned src_queue_mask,
4744 unsigned dst_queue_mask)
4745 {
4746 if (radv_image_has_cmask(image)) {
4747 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4748
4749 /* TODO: clarify this. */
4750 if (radv_image_has_fmask(image)) {
4751 value = 0xccccccccu;
4752 }
4753
4754 radv_initialise_cmask(cmd_buffer, image, value);
4755 }
4756
4757 if (radv_image_has_fmask(image)) {
4758 radv_initialize_fmask(cmd_buffer, image);
4759 }
4760
4761 if (radv_image_has_dcc(image)) {
4762 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4763 bool need_decompress_pass = false;
4764
4765 if (radv_layout_dcc_compressed(image, dst_layout,
4766 dst_queue_mask)) {
4767 value = 0x20202020u;
4768 need_decompress_pass = true;
4769 }
4770
4771 radv_initialize_dcc(cmd_buffer, image, value);
4772
4773 radv_update_fce_metadata(cmd_buffer, image,
4774 need_decompress_pass);
4775 }
4776
4777 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4778 uint32_t color_values[2] = {};
4779 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4780 }
4781 }
4782
4783 /**
4784 * Handle color image transitions for DCC/FMASK/CMASK.
4785 */
4786 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4787 struct radv_image *image,
4788 VkImageLayout src_layout,
4789 VkImageLayout dst_layout,
4790 unsigned src_queue_mask,
4791 unsigned dst_queue_mask,
4792 const VkImageSubresourceRange *range)
4793 {
4794 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4795 radv_init_color_image_metadata(cmd_buffer, image,
4796 src_layout, dst_layout,
4797 src_queue_mask, dst_queue_mask);
4798 return;
4799 }
4800
4801 if (radv_image_has_dcc(image)) {
4802 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4803 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4804 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4805 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4806 radv_decompress_dcc(cmd_buffer, image, range);
4807 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4808 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4809 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4810 }
4811 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4812 bool fce_eliminate = false, fmask_expand = false;
4813
4814 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4815 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4816 fce_eliminate = true;
4817 }
4818
4819 if (radv_image_has_fmask(image)) {
4820 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4821 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4822 /* A FMASK decompress is required before doing
4823 * a MSAA decompress using FMASK.
4824 */
4825 fmask_expand = true;
4826 }
4827 }
4828
4829 if (fce_eliminate || fmask_expand)
4830 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4831
4832 if (fmask_expand)
4833 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4834 }
4835 }
4836
4837 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4838 struct radv_image *image,
4839 VkImageLayout src_layout,
4840 VkImageLayout dst_layout,
4841 uint32_t src_family,
4842 uint32_t dst_family,
4843 const VkImageSubresourceRange *range)
4844 {
4845 if (image->exclusive && src_family != dst_family) {
4846 /* This is an acquire or a release operation and there will be
4847 * a corresponding release/acquire. Do the transition in the
4848 * most flexible queue. */
4849
4850 assert(src_family == cmd_buffer->queue_family_index ||
4851 dst_family == cmd_buffer->queue_family_index);
4852
4853 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4854 return;
4855
4856 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4857 (src_family == RADV_QUEUE_GENERAL ||
4858 dst_family == RADV_QUEUE_GENERAL))
4859 return;
4860 }
4861
4862 if (src_layout == dst_layout)
4863 return;
4864
4865 unsigned src_queue_mask =
4866 radv_image_queue_family_mask(image, src_family,
4867 cmd_buffer->queue_family_index);
4868 unsigned dst_queue_mask =
4869 radv_image_queue_family_mask(image, dst_family,
4870 cmd_buffer->queue_family_index);
4871
4872 if (vk_format_is_depth(image->vk_format)) {
4873 radv_handle_depth_image_transition(cmd_buffer, image,
4874 src_layout, dst_layout,
4875 src_queue_mask, dst_queue_mask,
4876 range);
4877 } else {
4878 radv_handle_color_image_transition(cmd_buffer, image,
4879 src_layout, dst_layout,
4880 src_queue_mask, dst_queue_mask,
4881 range);
4882 }
4883 }
4884
4885 struct radv_barrier_info {
4886 uint32_t eventCount;
4887 const VkEvent *pEvents;
4888 VkPipelineStageFlags srcStageMask;
4889 VkPipelineStageFlags dstStageMask;
4890 };
4891
4892 static void
4893 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4894 uint32_t memoryBarrierCount,
4895 const VkMemoryBarrier *pMemoryBarriers,
4896 uint32_t bufferMemoryBarrierCount,
4897 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4898 uint32_t imageMemoryBarrierCount,
4899 const VkImageMemoryBarrier *pImageMemoryBarriers,
4900 const struct radv_barrier_info *info)
4901 {
4902 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4903 enum radv_cmd_flush_bits src_flush_bits = 0;
4904 enum radv_cmd_flush_bits dst_flush_bits = 0;
4905
4906 for (unsigned i = 0; i < info->eventCount; ++i) {
4907 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4908 uint64_t va = radv_buffer_get_va(event->bo);
4909
4910 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4911
4912 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4913
4914 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4915 assert(cmd_buffer->cs->cdw <= cdw_max);
4916 }
4917
4918 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4919 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4920 NULL);
4921 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4922 NULL);
4923 }
4924
4925 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4926 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4927 NULL);
4928 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4929 NULL);
4930 }
4931
4932 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4933 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4934
4935 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4936 image);
4937 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4938 image);
4939 }
4940
4941 /* The Vulkan spec 1.1.98 says:
4942 *
4943 * "An execution dependency with only
4944 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4945 * will only prevent that stage from executing in subsequently
4946 * submitted commands. As this stage does not perform any actual
4947 * execution, this is not observable - in effect, it does not delay
4948 * processing of subsequent commands. Similarly an execution dependency
4949 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4950 * will effectively not wait for any prior commands to complete."
4951 */
4952 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4953 radv_stage_flush(cmd_buffer, info->srcStageMask);
4954 cmd_buffer->state.flush_bits |= src_flush_bits;
4955
4956 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4957 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4958 radv_handle_image_transition(cmd_buffer, image,
4959 pImageMemoryBarriers[i].oldLayout,
4960 pImageMemoryBarriers[i].newLayout,
4961 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4962 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4963 &pImageMemoryBarriers[i].subresourceRange);
4964 }
4965
4966 /* Make sure CP DMA is idle because the driver might have performed a
4967 * DMA operation for copying or filling buffers/images.
4968 */
4969 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4970 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4971 si_cp_dma_wait_for_idle(cmd_buffer);
4972
4973 cmd_buffer->state.flush_bits |= dst_flush_bits;
4974 }
4975
4976 void radv_CmdPipelineBarrier(
4977 VkCommandBuffer commandBuffer,
4978 VkPipelineStageFlags srcStageMask,
4979 VkPipelineStageFlags destStageMask,
4980 VkBool32 byRegion,
4981 uint32_t memoryBarrierCount,
4982 const VkMemoryBarrier* pMemoryBarriers,
4983 uint32_t bufferMemoryBarrierCount,
4984 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4985 uint32_t imageMemoryBarrierCount,
4986 const VkImageMemoryBarrier* pImageMemoryBarriers)
4987 {
4988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4989 struct radv_barrier_info info;
4990
4991 info.eventCount = 0;
4992 info.pEvents = NULL;
4993 info.srcStageMask = srcStageMask;
4994 info.dstStageMask = destStageMask;
4995
4996 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4997 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4998 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4999 }
5000
5001
5002 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5003 struct radv_event *event,
5004 VkPipelineStageFlags stageMask,
5005 unsigned value)
5006 {
5007 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5008 uint64_t va = radv_buffer_get_va(event->bo);
5009
5010 si_emit_cache_flush(cmd_buffer);
5011
5012 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5013
5014 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5015
5016 /* Flags that only require a top-of-pipe event. */
5017 VkPipelineStageFlags top_of_pipe_flags =
5018 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5019
5020 /* Flags that only require a post-index-fetch event. */
5021 VkPipelineStageFlags post_index_fetch_flags =
5022 top_of_pipe_flags |
5023 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5024 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5025
5026 /* Make sure CP DMA is idle because the driver might have performed a
5027 * DMA operation for copying or filling buffers/images.
5028 */
5029 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5030 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5031 si_cp_dma_wait_for_idle(cmd_buffer);
5032
5033 /* TODO: Emit EOS events for syncing PS/CS stages. */
5034
5035 if (!(stageMask & ~top_of_pipe_flags)) {
5036 /* Just need to sync the PFP engine. */
5037 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5038 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5039 S_370_WR_CONFIRM(1) |
5040 S_370_ENGINE_SEL(V_370_PFP));
5041 radeon_emit(cs, va);
5042 radeon_emit(cs, va >> 32);
5043 radeon_emit(cs, value);
5044 } else if (!(stageMask & ~post_index_fetch_flags)) {
5045 /* Sync ME because PFP reads index and indirect buffers. */
5046 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5047 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5048 S_370_WR_CONFIRM(1) |
5049 S_370_ENGINE_SEL(V_370_ME));
5050 radeon_emit(cs, va);
5051 radeon_emit(cs, va >> 32);
5052 radeon_emit(cs, value);
5053 } else {
5054 /* Otherwise, sync all prior GPU work using an EOP event. */
5055 si_cs_emit_write_event_eop(cs,
5056 cmd_buffer->device->physical_device->rad_info.chip_class,
5057 radv_cmd_buffer_uses_mec(cmd_buffer),
5058 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5059 EOP_DATA_SEL_VALUE_32BIT, va, value,
5060 cmd_buffer->gfx9_eop_bug_va);
5061 }
5062
5063 assert(cmd_buffer->cs->cdw <= cdw_max);
5064 }
5065
5066 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5067 VkEvent _event,
5068 VkPipelineStageFlags stageMask)
5069 {
5070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5071 RADV_FROM_HANDLE(radv_event, event, _event);
5072
5073 write_event(cmd_buffer, event, stageMask, 1);
5074 }
5075
5076 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5077 VkEvent _event,
5078 VkPipelineStageFlags stageMask)
5079 {
5080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5081 RADV_FROM_HANDLE(radv_event, event, _event);
5082
5083 write_event(cmd_buffer, event, stageMask, 0);
5084 }
5085
5086 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5087 uint32_t eventCount,
5088 const VkEvent* pEvents,
5089 VkPipelineStageFlags srcStageMask,
5090 VkPipelineStageFlags dstStageMask,
5091 uint32_t memoryBarrierCount,
5092 const VkMemoryBarrier* pMemoryBarriers,
5093 uint32_t bufferMemoryBarrierCount,
5094 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5095 uint32_t imageMemoryBarrierCount,
5096 const VkImageMemoryBarrier* pImageMemoryBarriers)
5097 {
5098 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5099 struct radv_barrier_info info;
5100
5101 info.eventCount = eventCount;
5102 info.pEvents = pEvents;
5103 info.srcStageMask = 0;
5104
5105 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5106 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5107 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5108 }
5109
5110
5111 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5112 uint32_t deviceMask)
5113 {
5114 /* No-op */
5115 }
5116
5117 /* VK_EXT_conditional_rendering */
5118 void radv_CmdBeginConditionalRenderingEXT(
5119 VkCommandBuffer commandBuffer,
5120 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5121 {
5122 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5123 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5124 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5125 bool draw_visible = true;
5126 uint64_t pred_value = 0;
5127 uint64_t va, new_va;
5128 unsigned pred_offset;
5129
5130 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5131
5132 /* By default, if the 32-bit value at offset in buffer memory is zero,
5133 * then the rendering commands are discarded, otherwise they are
5134 * executed as normal. If the inverted flag is set, all commands are
5135 * discarded if the value is non zero.
5136 */
5137 if (pConditionalRenderingBegin->flags &
5138 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5139 draw_visible = false;
5140 }
5141
5142 si_emit_cache_flush(cmd_buffer);
5143
5144 /* From the Vulkan spec 1.1.107:
5145 *
5146 * "If the 32-bit value at offset in buffer memory is zero, then the
5147 * rendering commands are discarded, otherwise they are executed as
5148 * normal. If the value of the predicate in buffer memory changes while
5149 * conditional rendering is active, the rendering commands may be
5150 * discarded in an implementation-dependent way. Some implementations
5151 * may latch the value of the predicate upon beginning conditional
5152 * rendering while others may read it before every rendering command."
5153 *
5154 * But, the AMD hardware treats the predicate as a 64-bit value which
5155 * means we need a workaround in the driver. Luckily, it's not required
5156 * to support if the value changes when predication is active.
5157 *
5158 * The workaround is as follows:
5159 * 1) allocate a 64-value in the upload BO and initialize it to 0
5160 * 2) copy the 32-bit predicate value to the upload BO
5161 * 3) use the new allocated VA address for predication
5162 *
5163 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5164 * in ME (+ sync PFP) instead of PFP.
5165 */
5166 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5167
5168 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5169
5170 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5171 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5172 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5173 COPY_DATA_WR_CONFIRM);
5174 radeon_emit(cs, va);
5175 radeon_emit(cs, va >> 32);
5176 radeon_emit(cs, new_va);
5177 radeon_emit(cs, new_va >> 32);
5178
5179 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5180 radeon_emit(cs, 0);
5181
5182 /* Enable predication for this command buffer. */
5183 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5184 cmd_buffer->state.predicating = true;
5185
5186 /* Store conditional rendering user info. */
5187 cmd_buffer->state.predication_type = draw_visible;
5188 cmd_buffer->state.predication_va = new_va;
5189 }
5190
5191 void radv_CmdEndConditionalRenderingEXT(
5192 VkCommandBuffer commandBuffer)
5193 {
5194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5195
5196 /* Disable predication for this command buffer. */
5197 si_emit_set_predication_state(cmd_buffer, false, 0);
5198 cmd_buffer->state.predicating = false;
5199
5200 /* Reset conditional rendering user info. */
5201 cmd_buffer->state.predication_type = -1;
5202 cmd_buffer->state.predication_va = 0;
5203 }
5204
5205 /* VK_EXT_transform_feedback */
5206 void radv_CmdBindTransformFeedbackBuffersEXT(
5207 VkCommandBuffer commandBuffer,
5208 uint32_t firstBinding,
5209 uint32_t bindingCount,
5210 const VkBuffer* pBuffers,
5211 const VkDeviceSize* pOffsets,
5212 const VkDeviceSize* pSizes)
5213 {
5214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5215 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5216 uint8_t enabled_mask = 0;
5217
5218 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5219 for (uint32_t i = 0; i < bindingCount; i++) {
5220 uint32_t idx = firstBinding + i;
5221
5222 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5223 sb[idx].offset = pOffsets[i];
5224 sb[idx].size = pSizes[i];
5225
5226 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5227 sb[idx].buffer->bo);
5228
5229 enabled_mask |= 1 << idx;
5230 }
5231
5232 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5233
5234 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5235 }
5236
5237 static void
5238 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5239 {
5240 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5241 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5242
5243 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5244 radeon_emit(cs,
5245 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5246 S_028B94_RAST_STREAM(0) |
5247 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5248 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5249 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5250 radeon_emit(cs, so->hw_enabled_mask &
5251 so->enabled_stream_buffers_mask);
5252
5253 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5254 }
5255
5256 static void
5257 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5258 {
5259 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5260 bool old_streamout_enabled = so->streamout_enabled;
5261 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5262
5263 so->streamout_enabled = enable;
5264
5265 so->hw_enabled_mask = so->enabled_mask |
5266 (so->enabled_mask << 4) |
5267 (so->enabled_mask << 8) |
5268 (so->enabled_mask << 12);
5269
5270 if ((old_streamout_enabled != so->streamout_enabled) ||
5271 (old_hw_enabled_mask != so->hw_enabled_mask))
5272 radv_emit_streamout_enable(cmd_buffer);
5273 }
5274
5275 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5276 {
5277 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5278 unsigned reg_strmout_cntl;
5279
5280 /* The register is at different places on different ASICs. */
5281 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5282 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5283 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5284 } else {
5285 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5286 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5287 }
5288
5289 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5290 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5291
5292 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5293 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5294 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5295 radeon_emit(cs, 0);
5296 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5297 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5298 radeon_emit(cs, 4); /* poll interval */
5299 }
5300
5301 void radv_CmdBeginTransformFeedbackEXT(
5302 VkCommandBuffer commandBuffer,
5303 uint32_t firstCounterBuffer,
5304 uint32_t counterBufferCount,
5305 const VkBuffer* pCounterBuffers,
5306 const VkDeviceSize* pCounterBufferOffsets)
5307 {
5308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5309 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5310 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5311 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5312 uint32_t i;
5313
5314 radv_flush_vgt_streamout(cmd_buffer);
5315
5316 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5317 for_each_bit(i, so->enabled_mask) {
5318 int32_t counter_buffer_idx = i - firstCounterBuffer;
5319 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5320 counter_buffer_idx = -1;
5321
5322 /* AMD GCN binds streamout buffers as shader resources.
5323 * VGT only counts primitives and tells the shader through
5324 * SGPRs what to do.
5325 */
5326 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5327 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5328 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5329
5330 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5331
5332 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5333 /* The array of counter buffers is optional. */
5334 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5335 uint64_t va = radv_buffer_get_va(buffer->bo);
5336
5337 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5338
5339 /* Append */
5340 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5341 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5342 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5343 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5344 radeon_emit(cs, 0); /* unused */
5345 radeon_emit(cs, 0); /* unused */
5346 radeon_emit(cs, va); /* src address lo */
5347 radeon_emit(cs, va >> 32); /* src address hi */
5348
5349 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5350 } else {
5351 /* Start from the beginning. */
5352 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5353 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5354 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5355 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5356 radeon_emit(cs, 0); /* unused */
5357 radeon_emit(cs, 0); /* unused */
5358 radeon_emit(cs, 0); /* unused */
5359 radeon_emit(cs, 0); /* unused */
5360 }
5361 }
5362
5363 radv_set_streamout_enable(cmd_buffer, true);
5364 }
5365
5366 void radv_CmdEndTransformFeedbackEXT(
5367 VkCommandBuffer commandBuffer,
5368 uint32_t firstCounterBuffer,
5369 uint32_t counterBufferCount,
5370 const VkBuffer* pCounterBuffers,
5371 const VkDeviceSize* pCounterBufferOffsets)
5372 {
5373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5374 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5375 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5376 uint32_t i;
5377
5378 radv_flush_vgt_streamout(cmd_buffer);
5379
5380 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5381 for_each_bit(i, so->enabled_mask) {
5382 int32_t counter_buffer_idx = i - firstCounterBuffer;
5383 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5384 counter_buffer_idx = -1;
5385
5386 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5387 /* The array of counters buffer is optional. */
5388 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5389 uint64_t va = radv_buffer_get_va(buffer->bo);
5390
5391 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5392
5393 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5394 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5395 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5396 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5397 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5398 radeon_emit(cs, va); /* dst address lo */
5399 radeon_emit(cs, va >> 32); /* dst address hi */
5400 radeon_emit(cs, 0); /* unused */
5401 radeon_emit(cs, 0); /* unused */
5402
5403 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5404 }
5405
5406 /* Deactivate transform feedback by zeroing the buffer size.
5407 * The counters (primitives generated, primitives emitted) may
5408 * be enabled even if there is not buffer bound. This ensures
5409 * that the primitives-emitted query won't increment.
5410 */
5411 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5412
5413 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5414 }
5415
5416 radv_set_streamout_enable(cmd_buffer, false);
5417 }
5418
5419 void radv_CmdDrawIndirectByteCountEXT(
5420 VkCommandBuffer commandBuffer,
5421 uint32_t instanceCount,
5422 uint32_t firstInstance,
5423 VkBuffer _counterBuffer,
5424 VkDeviceSize counterBufferOffset,
5425 uint32_t counterOffset,
5426 uint32_t vertexStride)
5427 {
5428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5429 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5430 struct radv_draw_info info = {};
5431
5432 info.instance_count = instanceCount;
5433 info.first_instance = firstInstance;
5434 info.strmout_buffer = counterBuffer;
5435 info.strmout_buffer_offset = counterBufferOffset;
5436 info.stride = vertexStride;
5437
5438 radv_draw(cmd_buffer, &info);
5439 }