2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
34 #include "radv_debug.h"
35 #include "radv_meta.h"
40 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
41 RADV_PREFETCH_VS
= (1 << 1),
42 RADV_PREFETCH_TCS
= (1 << 2),
43 RADV_PREFETCH_TES
= (1 << 3),
44 RADV_PREFETCH_GS
= (1 << 4),
45 RADV_PREFETCH_PS
= (1 << 5),
46 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
53 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
54 struct radv_image
*image
,
55 VkImageLayout src_layout
,
56 VkImageLayout dst_layout
,
59 const VkImageSubresourceRange
*range
);
61 const struct radv_dynamic_state default_dynamic_state
= {
74 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
79 .stencil_compare_mask
= {
83 .stencil_write_mask
= {
87 .stencil_reference
= {
94 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
95 const struct radv_dynamic_state
*src
)
97 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
98 uint32_t copy_mask
= src
->mask
;
99 uint32_t dest_mask
= 0;
101 /* Make sure to copy the number of viewports/scissors because they can
102 * only be specified at pipeline creation time.
104 dest
->viewport
.count
= src
->viewport
.count
;
105 dest
->scissor
.count
= src
->scissor
.count
;
106 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
107 dest
->sample_location
.count
= src
->sample_location
.count
;
109 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
110 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
111 src
->viewport
.count
* sizeof(VkViewport
))) {
112 typed_memcpy(dest
->viewport
.viewports
,
113 src
->viewport
.viewports
,
114 src
->viewport
.count
);
115 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
119 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
120 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
121 src
->scissor
.count
* sizeof(VkRect2D
))) {
122 typed_memcpy(dest
->scissor
.scissors
,
123 src
->scissor
.scissors
, src
->scissor
.count
);
124 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
128 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
129 if (dest
->line_width
!= src
->line_width
) {
130 dest
->line_width
= src
->line_width
;
131 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
135 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
136 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
137 sizeof(src
->depth_bias
))) {
138 dest
->depth_bias
= src
->depth_bias
;
139 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
143 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
144 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
145 sizeof(src
->blend_constants
))) {
146 typed_memcpy(dest
->blend_constants
,
147 src
->blend_constants
, 4);
148 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
152 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
153 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
154 sizeof(src
->depth_bounds
))) {
155 dest
->depth_bounds
= src
->depth_bounds
;
156 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
160 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
161 if (memcmp(&dest
->stencil_compare_mask
,
162 &src
->stencil_compare_mask
,
163 sizeof(src
->stencil_compare_mask
))) {
164 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
165 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
169 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
170 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
171 sizeof(src
->stencil_write_mask
))) {
172 dest
->stencil_write_mask
= src
->stencil_write_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
178 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
179 sizeof(src
->stencil_reference
))) {
180 dest
->stencil_reference
= src
->stencil_reference
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
185 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
186 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
187 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
188 typed_memcpy(dest
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.count
);
191 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
195 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
196 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
197 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
198 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
199 memcmp(&dest
->sample_location
.locations
,
200 &src
->sample_location
.locations
,
201 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
202 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
203 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
204 typed_memcpy(dest
->sample_location
.locations
,
205 src
->sample_location
.locations
,
206 src
->sample_location
.count
);
207 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
211 cmd_buffer
->state
.dirty
|= dest_mask
;
215 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
216 struct radv_pipeline
*pipeline
)
218 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
219 struct radv_shader_info
*info
;
221 if (!pipeline
->streamout_shader
)
224 info
= &pipeline
->streamout_shader
->info
.info
;
225 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
226 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
228 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
231 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
233 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
234 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
237 enum ring_type
radv_queue_family_to_ring(int f
) {
239 case RADV_QUEUE_GENERAL
:
241 case RADV_QUEUE_COMPUTE
:
243 case RADV_QUEUE_TRANSFER
:
246 unreachable("Unknown queue family");
250 static VkResult
radv_create_cmd_buffer(
251 struct radv_device
* device
,
252 struct radv_cmd_pool
* pool
,
253 VkCommandBufferLevel level
,
254 VkCommandBuffer
* pCommandBuffer
)
256 struct radv_cmd_buffer
*cmd_buffer
;
258 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
259 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
260 if (cmd_buffer
== NULL
)
261 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
263 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
264 cmd_buffer
->device
= device
;
265 cmd_buffer
->pool
= pool
;
266 cmd_buffer
->level
= level
;
269 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
270 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
273 /* Init the pool_link so we can safely call list_del when we destroy
276 list_inithead(&cmd_buffer
->pool_link
);
277 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
280 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
282 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
283 if (!cmd_buffer
->cs
) {
284 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
285 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
288 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
290 list_inithead(&cmd_buffer
->upload
.list
);
296 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
298 list_del(&cmd_buffer
->pool_link
);
300 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
301 &cmd_buffer
->upload
.list
, list
) {
302 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
307 if (cmd_buffer
->upload
.upload_bo
)
308 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
309 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
311 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
312 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
314 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
318 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
320 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
322 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
323 &cmd_buffer
->upload
.list
, list
) {
324 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
329 cmd_buffer
->push_constant_stages
= 0;
330 cmd_buffer
->scratch_size_needed
= 0;
331 cmd_buffer
->compute_scratch_size_needed
= 0;
332 cmd_buffer
->esgs_ring_size_needed
= 0;
333 cmd_buffer
->gsvs_ring_size_needed
= 0;
334 cmd_buffer
->tess_rings_needed
= false;
335 cmd_buffer
->sample_positions_needed
= false;
337 if (cmd_buffer
->upload
.upload_bo
)
338 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
339 cmd_buffer
->upload
.upload_bo
);
340 cmd_buffer
->upload
.offset
= 0;
342 cmd_buffer
->record_result
= VK_SUCCESS
;
344 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
346 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
347 cmd_buffer
->descriptors
[i
].dirty
= 0;
348 cmd_buffer
->descriptors
[i
].valid
= 0;
349 cmd_buffer
->descriptors
[i
].push_dirty
= false;
352 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
353 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
354 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
355 unsigned fence_offset
, eop_bug_offset
;
358 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
361 cmd_buffer
->gfx9_fence_va
=
362 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
363 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
365 /* Allocate a buffer for the EOP bug on GFX9. */
366 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
367 &eop_bug_offset
, &fence_ptr
);
368 cmd_buffer
->gfx9_eop_bug_va
=
369 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
370 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
373 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
375 return cmd_buffer
->record_result
;
379 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
383 struct radeon_winsys_bo
*bo
;
384 struct radv_cmd_buffer_upload
*upload
;
385 struct radv_device
*device
= cmd_buffer
->device
;
387 new_size
= MAX2(min_needed
, 16 * 1024);
388 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
390 bo
= device
->ws
->buffer_create(device
->ws
,
393 RADEON_FLAG_CPU_ACCESS
|
394 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
396 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
399 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
403 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
404 if (cmd_buffer
->upload
.upload_bo
) {
405 upload
= malloc(sizeof(*upload
));
408 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
409 device
->ws
->buffer_destroy(bo
);
413 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
414 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
417 cmd_buffer
->upload
.upload_bo
= bo
;
418 cmd_buffer
->upload
.size
= new_size
;
419 cmd_buffer
->upload
.offset
= 0;
420 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
422 if (!cmd_buffer
->upload
.map
) {
423 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
431 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
434 unsigned *out_offset
,
437 assert(util_is_power_of_two_nonzero(alignment
));
439 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
440 if (offset
+ size
> cmd_buffer
->upload
.size
) {
441 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
446 *out_offset
= offset
;
447 *ptr
= cmd_buffer
->upload
.map
+ offset
;
449 cmd_buffer
->upload
.offset
= offset
+ size
;
454 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
455 unsigned size
, unsigned alignment
,
456 const void *data
, unsigned *out_offset
)
460 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
461 out_offset
, (void **)&ptr
))
465 memcpy(ptr
, data
, size
);
471 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
472 unsigned count
, const uint32_t *data
)
474 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
476 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
478 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
479 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
480 S_370_WR_CONFIRM(1) |
481 S_370_ENGINE_SEL(V_370_ME
));
483 radeon_emit(cs
, va
>> 32);
484 radeon_emit_array(cs
, data
, count
);
487 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
489 struct radv_device
*device
= cmd_buffer
->device
;
490 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
493 va
= radv_buffer_get_va(device
->trace_bo
);
494 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
497 ++cmd_buffer
->state
.trace_id
;
498 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
499 &cmd_buffer
->state
.trace_id
);
501 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
503 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
504 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
508 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
509 enum radv_cmd_flush_bits flags
)
511 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
512 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
513 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
515 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
517 /* Force wait for graphics or compute engines to be idle. */
518 si_cs_emit_cache_flush(cmd_buffer
->cs
,
519 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
520 &cmd_buffer
->gfx9_fence_idx
,
521 cmd_buffer
->gfx9_fence_va
,
522 radv_cmd_buffer_uses_mec(cmd_buffer
),
523 flags
, cmd_buffer
->gfx9_eop_bug_va
);
526 if (unlikely(cmd_buffer
->device
->trace_bo
))
527 radv_cmd_buffer_trace_emit(cmd_buffer
);
531 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
532 struct radv_pipeline
*pipeline
, enum ring_type ring
)
534 struct radv_device
*device
= cmd_buffer
->device
;
538 va
= radv_buffer_get_va(device
->trace_bo
);
548 assert(!"invalid ring type");
551 data
[0] = (uintptr_t)pipeline
;
552 data
[1] = (uintptr_t)pipeline
>> 32;
554 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
557 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
558 VkPipelineBindPoint bind_point
,
559 struct radv_descriptor_set
*set
,
562 struct radv_descriptor_state
*descriptors_state
=
563 radv_get_descriptors_state(cmd_buffer
, bind_point
);
565 descriptors_state
->sets
[idx
] = set
;
567 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
568 descriptors_state
->dirty
|= (1u << idx
);
572 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
573 VkPipelineBindPoint bind_point
)
575 struct radv_descriptor_state
*descriptors_state
=
576 radv_get_descriptors_state(cmd_buffer
, bind_point
);
577 struct radv_device
*device
= cmd_buffer
->device
;
578 uint32_t data
[MAX_SETS
* 2] = {};
581 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
583 for_each_bit(i
, descriptors_state
->valid
) {
584 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
585 data
[i
* 2] = (uintptr_t)set
;
586 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
589 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
592 struct radv_userdata_info
*
593 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
594 gl_shader_stage stage
,
597 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
598 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
602 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
603 struct radv_pipeline
*pipeline
,
604 gl_shader_stage stage
,
605 int idx
, uint64_t va
)
607 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
608 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
609 if (loc
->sgpr_idx
== -1)
612 assert(loc
->num_sgprs
== 1);
614 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
615 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
619 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
620 struct radv_pipeline
*pipeline
,
621 struct radv_descriptor_state
*descriptors_state
,
622 gl_shader_stage stage
)
624 struct radv_device
*device
= cmd_buffer
->device
;
625 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
626 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
627 struct radv_userdata_locations
*locs
=
628 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
629 unsigned mask
= locs
->descriptor_sets_enabled
;
631 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
636 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
638 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
639 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
641 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
642 for (int i
= 0; i
< count
; i
++) {
643 struct radv_descriptor_set
*set
=
644 descriptors_state
->sets
[start
+ i
];
646 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
652 * Convert the user sample locations to hardware sample locations (the values
653 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
657 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
659 uint32_t x_offset
= x
% state
->grid_size
.width
;
660 uint32_t y_offset
= y
% state
->grid_size
.height
;
661 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
662 VkSampleLocationEXT
*user_locs
;
663 uint32_t pixel_offset
;
665 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
667 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
668 user_locs
= &state
->locations
[pixel_offset
];
670 for (uint32_t i
= 0; i
< num_samples
; i
++) {
671 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
672 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
674 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
675 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
677 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
678 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
683 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
687 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
688 uint32_t *sample_locs_pixel
)
690 for (uint32_t i
= 0; i
< num_samples
; i
++) {
691 uint32_t sample_reg_idx
= i
/ 4;
692 uint32_t sample_loc_idx
= i
% 4;
693 int32_t pos_x
= sample_locs
[i
].x
;
694 int32_t pos_y
= sample_locs
[i
].y
;
696 uint32_t shift_x
= 8 * sample_loc_idx
;
697 uint32_t shift_y
= shift_x
+ 4;
699 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
700 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
705 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
709 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
710 VkOffset2D
*sample_locs
,
711 uint32_t num_samples
)
713 uint32_t centroid_priorities
[num_samples
];
714 uint32_t sample_mask
= num_samples
- 1;
715 uint32_t distances
[num_samples
];
716 uint64_t centroid_priority
= 0;
718 /* Compute the distances from center for each sample. */
719 for (int i
= 0; i
< num_samples
; i
++) {
720 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
721 (sample_locs
[i
].y
* sample_locs
[i
].y
);
724 /* Compute the centroid priorities by looking at the distances array. */
725 for (int i
= 0; i
< num_samples
; i
++) {
726 uint32_t min_idx
= 0;
728 for (int j
= 1; j
< num_samples
; j
++) {
729 if (distances
[j
] < distances
[min_idx
])
733 centroid_priorities
[i
] = min_idx
;
734 distances
[min_idx
] = 0xffffffff;
737 /* Compute the final centroid priority. */
738 for (int i
= 0; i
< 8; i
++) {
740 centroid_priorities
[i
& sample_mask
] << (i
* 4);
743 return centroid_priority
<< 32 | centroid_priority
;
747 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
752 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
753 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
754 struct radv_sample_locations_state
*sample_location
=
755 &cmd_buffer
->state
.dynamic
.sample_location
;
756 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
757 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
758 uint32_t sample_locs_pixel
[4][2] = {};
759 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
760 uint32_t max_sample_dist
= 0;
761 uint64_t centroid_priority
;
763 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
766 /* Convert the user sample locations to hardware sample locations. */
767 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
768 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
769 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
770 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
772 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
773 for (uint32_t i
= 0; i
< 4; i
++) {
774 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
775 sample_locs_pixel
[i
]);
778 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
780 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
783 /* Compute the maximum sample distance from the specified locations. */
784 for (uint32_t i
= 0; i
< num_samples
; i
++) {
785 VkOffset2D offset
= sample_locs
[0][i
];
786 max_sample_dist
= MAX2(max_sample_dist
,
787 MAX2(abs(offset
.x
), abs(offset
.y
)));
790 /* Emit the specified user sample locations. */
791 switch (num_samples
) {
794 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
795 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
796 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
797 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
800 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
801 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
802 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
803 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
804 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
805 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
806 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
807 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
810 unreachable("invalid number of samples");
813 /* Emit the maximum sample distance and the centroid priority. */
814 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
816 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
817 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
819 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
820 radeon_emit(cs
, pa_sc_aa_config
);
822 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
823 radeon_emit(cs
, centroid_priority
);
824 radeon_emit(cs
, centroid_priority
>> 32);
826 /* GFX9: Flush DFSM when the AA mode changes. */
827 if (cmd_buffer
->device
->dfsm_allowed
) {
828 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
829 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
832 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
836 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
837 struct radv_pipeline
*pipeline
,
838 gl_shader_stage stage
,
839 int idx
, int count
, uint32_t *values
)
841 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
842 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
843 if (loc
->sgpr_idx
== -1)
846 assert(loc
->num_sgprs
== count
);
848 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
849 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
853 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
854 struct radv_pipeline
*pipeline
)
856 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
857 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
858 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
860 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
861 cmd_buffer
->sample_positions_needed
= true;
863 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
866 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
867 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
868 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
870 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
872 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
874 /* GFX9: Flush DFSM when the AA mode changes. */
875 if (cmd_buffer
->device
->dfsm_allowed
) {
876 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
877 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
880 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
884 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
885 struct radv_shader_variant
*shader
)
892 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
894 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
898 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
899 struct radv_pipeline
*pipeline
,
900 bool vertex_stage_only
)
902 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
903 uint32_t mask
= state
->prefetch_L2_mask
;
905 if (vertex_stage_only
) {
906 /* Fast prefetch path for starting draws as soon as possible.
908 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
909 RADV_PREFETCH_VBO_DESCRIPTORS
);
912 if (mask
& RADV_PREFETCH_VS
)
913 radv_emit_shader_prefetch(cmd_buffer
,
914 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
916 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
917 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
919 if (mask
& RADV_PREFETCH_TCS
)
920 radv_emit_shader_prefetch(cmd_buffer
,
921 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
923 if (mask
& RADV_PREFETCH_TES
)
924 radv_emit_shader_prefetch(cmd_buffer
,
925 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
927 if (mask
& RADV_PREFETCH_GS
) {
928 radv_emit_shader_prefetch(cmd_buffer
,
929 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
930 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
933 if (mask
& RADV_PREFETCH_PS
)
934 radv_emit_shader_prefetch(cmd_buffer
,
935 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
937 state
->prefetch_L2_mask
&= ~mask
;
941 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
943 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
946 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
947 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
948 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
950 unsigned sx_ps_downconvert
= 0;
951 unsigned sx_blend_opt_epsilon
= 0;
952 unsigned sx_blend_opt_control
= 0;
954 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
955 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
956 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
957 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
961 int idx
= subpass
->color_attachments
[i
].attachment
;
962 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
964 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
965 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
966 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
967 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
969 bool has_alpha
, has_rgb
;
971 /* Set if RGB and A are present. */
972 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
974 if (format
== V_028C70_COLOR_8
||
975 format
== V_028C70_COLOR_16
||
976 format
== V_028C70_COLOR_32
)
977 has_rgb
= !has_alpha
;
981 /* Check the colormask and export format. */
982 if (!(colormask
& 0x7))
984 if (!(colormask
& 0x8))
987 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
992 /* Disable value checking for disabled channels. */
994 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
996 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
998 /* Enable down-conversion for 32bpp and smaller formats. */
1000 case V_028C70_COLOR_8
:
1001 case V_028C70_COLOR_8_8
:
1002 case V_028C70_COLOR_8_8_8_8
:
1003 /* For 1 and 2-channel formats, use the superset thereof. */
1004 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1005 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1006 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1007 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1008 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1012 case V_028C70_COLOR_5_6_5
:
1013 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1014 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1015 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1019 case V_028C70_COLOR_1_5_5_5
:
1020 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1021 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1022 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1026 case V_028C70_COLOR_4_4_4_4
:
1027 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1028 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1029 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1033 case V_028C70_COLOR_32
:
1034 if (swap
== V_028C70_SWAP_STD
&&
1035 spi_format
== V_028714_SPI_SHADER_32_R
)
1036 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1037 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1038 spi_format
== V_028714_SPI_SHADER_32_AR
)
1039 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1042 case V_028C70_COLOR_16
:
1043 case V_028C70_COLOR_16_16
:
1044 /* For 1-channel formats, use the superset thereof. */
1045 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1046 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1047 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1048 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1049 if (swap
== V_028C70_SWAP_STD
||
1050 swap
== V_028C70_SWAP_STD_REV
)
1051 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1053 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1057 case V_028C70_COLOR_10_11_11
:
1058 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1059 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1060 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1064 case V_028C70_COLOR_2_10_10_10
:
1065 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1066 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1067 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1073 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1074 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1075 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1077 /* TODO: avoid redundantly setting context registers */
1078 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1079 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1080 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1081 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1083 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1087 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1089 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1091 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1094 radv_update_multisample_state(cmd_buffer
, pipeline
);
1096 cmd_buffer
->scratch_size_needed
=
1097 MAX2(cmd_buffer
->scratch_size_needed
,
1098 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1100 if (!cmd_buffer
->state
.emitted_pipeline
||
1101 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1102 pipeline
->graphics
.can_use_guardband
)
1103 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1105 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1107 if (!cmd_buffer
->state
.emitted_pipeline
||
1108 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1109 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1110 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1111 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1112 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1113 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1116 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1117 if (!pipeline
->shaders
[i
])
1120 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1121 pipeline
->shaders
[i
]->bo
);
1124 if (radv_pipeline_has_gs(pipeline
))
1125 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1126 pipeline
->gs_copy_shader
->bo
);
1128 if (unlikely(cmd_buffer
->device
->trace_bo
))
1129 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1131 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1133 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1137 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1139 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1140 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1144 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1146 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1148 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1149 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1150 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1151 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1153 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1157 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1159 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1162 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1163 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1164 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1165 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1166 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1167 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1168 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1173 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1175 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1177 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1178 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1182 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1184 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1186 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1187 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1191 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1193 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1195 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1196 R_028430_DB_STENCILREFMASK
, 2);
1197 radeon_emit(cmd_buffer
->cs
,
1198 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1199 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1200 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1201 S_028430_STENCILOPVAL(1));
1202 radeon_emit(cmd_buffer
->cs
,
1203 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1204 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1205 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1206 S_028434_STENCILOPVAL_BF(1));
1210 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1212 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1214 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1215 fui(d
->depth_bounds
.min
));
1216 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1217 fui(d
->depth_bounds
.max
));
1221 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1223 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1224 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1225 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1228 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1229 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1230 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1231 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1232 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1233 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1234 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1238 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1240 struct radv_attachment_info
*att
,
1241 struct radv_image
*image
,
1242 VkImageLayout layout
)
1244 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1245 struct radv_color_buffer_info
*cb
= &att
->cb
;
1246 uint32_t cb_color_info
= cb
->cb_color_info
;
1248 if (!radv_layout_dcc_compressed(image
, layout
,
1249 radv_image_queue_family_mask(image
,
1250 cmd_buffer
->queue_family_index
,
1251 cmd_buffer
->queue_family_index
))) {
1252 cb_color_info
&= C_028C70_DCC_ENABLE
;
1255 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1256 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1257 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1258 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1259 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1260 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1261 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1262 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1263 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1264 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1265 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1266 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1267 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1269 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1270 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1271 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1273 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1276 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1277 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1278 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1279 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1280 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1281 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1282 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1283 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1284 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1285 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1286 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1287 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1289 if (is_vi
) { /* DCC BASE */
1290 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1294 if (radv_image_has_dcc(image
)) {
1295 /* Drawing with DCC enabled also compresses colorbuffers. */
1296 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1301 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1302 struct radv_ds_buffer_info
*ds
,
1303 struct radv_image
*image
, VkImageLayout layout
,
1304 bool requires_cond_exec
)
1306 uint32_t db_z_info
= ds
->db_z_info
;
1307 uint32_t db_z_info_reg
;
1309 if (!radv_image_is_tc_compat_htile(image
))
1312 if (!radv_layout_has_htile(image
, layout
,
1313 radv_image_queue_family_mask(image
,
1314 cmd_buffer
->queue_family_index
,
1315 cmd_buffer
->queue_family_index
))) {
1316 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1319 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1321 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1322 db_z_info_reg
= R_028038_DB_Z_INFO
;
1324 db_z_info_reg
= R_028040_DB_Z_INFO
;
1327 /* When we don't know the last fast clear value we need to emit a
1328 * conditional packet that will eventually skip the following
1329 * SET_CONTEXT_REG packet.
1331 if (requires_cond_exec
) {
1332 uint64_t va
= radv_buffer_get_va(image
->bo
);
1333 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1335 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1336 radeon_emit(cmd_buffer
->cs
, va
);
1337 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1338 radeon_emit(cmd_buffer
->cs
, 0);
1339 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1342 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1346 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1347 struct radv_ds_buffer_info
*ds
,
1348 struct radv_image
*image
,
1349 VkImageLayout layout
)
1351 uint32_t db_z_info
= ds
->db_z_info
;
1352 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1354 if (!radv_layout_has_htile(image
, layout
,
1355 radv_image_queue_family_mask(image
,
1356 cmd_buffer
->queue_family_index
,
1357 cmd_buffer
->queue_family_index
))) {
1358 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1359 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1362 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1363 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1366 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1367 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1368 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1369 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1370 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1372 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1373 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1374 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1375 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1376 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1377 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1378 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1379 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1380 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1381 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1382 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1384 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1385 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1386 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1388 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1390 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1391 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1392 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1393 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1394 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1395 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1396 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1397 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1398 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1399 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1403 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1404 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1406 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1407 ds
->pa_su_poly_offset_db_fmt_cntl
);
1411 * Update the fast clear depth/stencil values if the image is bound as a
1412 * depth/stencil buffer.
1415 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1416 struct radv_image
*image
,
1417 VkClearDepthStencilValue ds_clear_value
,
1418 VkImageAspectFlags aspects
)
1420 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1421 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1422 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1423 struct radv_attachment_info
*att
;
1426 if (!framebuffer
|| !subpass
)
1429 if (!subpass
->depth_stencil_attachment
)
1432 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1433 att
= &framebuffer
->attachments
[att_idx
];
1434 if (att
->attachment
->image
!= image
)
1437 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1438 radeon_emit(cs
, ds_clear_value
.stencil
);
1439 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1441 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1442 * only needed when clearing Z to 0.0.
1444 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1445 ds_clear_value
.depth
== 0.0) {
1446 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1448 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1452 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1456 * Set the clear depth/stencil values to the image's metadata.
1459 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1460 struct radv_image
*image
,
1461 VkClearDepthStencilValue ds_clear_value
,
1462 VkImageAspectFlags aspects
)
1464 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1465 uint64_t va
= radv_buffer_get_va(image
->bo
);
1466 unsigned reg_offset
= 0, reg_count
= 0;
1468 va
+= image
->offset
+ image
->clear_value_offset
;
1470 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1476 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1479 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1480 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1481 S_370_WR_CONFIRM(1) |
1482 S_370_ENGINE_SEL(V_370_PFP
));
1483 radeon_emit(cs
, va
);
1484 radeon_emit(cs
, va
>> 32);
1485 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1486 radeon_emit(cs
, ds_clear_value
.stencil
);
1487 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1488 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1492 * Update the TC-compat metadata value for this image.
1495 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1496 struct radv_image
*image
,
1499 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1500 uint64_t va
= radv_buffer_get_va(image
->bo
);
1501 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1503 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1504 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1505 S_370_WR_CONFIRM(1) |
1506 S_370_ENGINE_SEL(V_370_PFP
));
1507 radeon_emit(cs
, va
);
1508 radeon_emit(cs
, va
>> 32);
1509 radeon_emit(cs
, value
);
1513 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1514 struct radv_image
*image
,
1515 VkClearDepthStencilValue ds_clear_value
)
1517 uint64_t va
= radv_buffer_get_va(image
->bo
);
1518 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1521 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1522 * depth clear value is 0.0f.
1524 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1526 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1530 * Update the clear depth/stencil values for this image.
1533 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1534 struct radv_image
*image
,
1535 VkClearDepthStencilValue ds_clear_value
,
1536 VkImageAspectFlags aspects
)
1538 assert(radv_image_has_htile(image
));
1540 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1542 if (radv_image_is_tc_compat_htile(image
) &&
1543 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1544 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1548 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1553 * Load the clear depth/stencil values from the image's metadata.
1556 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1557 struct radv_image
*image
)
1559 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1560 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1561 uint64_t va
= radv_buffer_get_va(image
->bo
);
1562 unsigned reg_offset
= 0, reg_count
= 0;
1564 va
+= image
->offset
+ image
->clear_value_offset
;
1566 if (!radv_image_has_htile(image
))
1569 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1575 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1578 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1580 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1581 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1582 radeon_emit(cs
, va
);
1583 radeon_emit(cs
, va
>> 32);
1584 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1585 radeon_emit(cs
, reg_count
);
1587 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1588 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1589 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1590 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1591 radeon_emit(cs
, va
);
1592 radeon_emit(cs
, va
>> 32);
1593 radeon_emit(cs
, reg
>> 2);
1596 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1602 * With DCC some colors don't require CMASK elimination before being
1603 * used as a texture. This sets a predicate value to determine if the
1604 * cmask eliminate is required.
1607 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1608 struct radv_image
*image
, bool value
)
1610 uint64_t pred_val
= value
;
1611 uint64_t va
= radv_buffer_get_va(image
->bo
);
1612 va
+= image
->offset
+ image
->fce_pred_offset
;
1614 assert(radv_image_has_dcc(image
));
1616 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1617 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1618 S_370_WR_CONFIRM(1) |
1619 S_370_ENGINE_SEL(V_370_PFP
));
1620 radeon_emit(cmd_buffer
->cs
, va
);
1621 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1622 radeon_emit(cmd_buffer
->cs
, pred_val
);
1623 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1627 * Update the DCC predicate to reflect the compression state.
1630 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1631 struct radv_image
*image
, bool value
)
1633 uint64_t pred_val
= value
;
1634 uint64_t va
= radv_buffer_get_va(image
->bo
);
1635 va
+= image
->offset
+ image
->dcc_pred_offset
;
1637 assert(radv_image_has_dcc(image
));
1639 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1640 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1641 S_370_WR_CONFIRM(1) |
1642 S_370_ENGINE_SEL(V_370_PFP
));
1643 radeon_emit(cmd_buffer
->cs
, va
);
1644 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1645 radeon_emit(cmd_buffer
->cs
, pred_val
);
1646 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1650 * Update the fast clear color values if the image is bound as a color buffer.
1653 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1654 struct radv_image
*image
,
1656 uint32_t color_values
[2])
1658 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1659 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1660 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1661 struct radv_attachment_info
*att
;
1664 if (!framebuffer
|| !subpass
)
1667 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1668 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1671 att
= &framebuffer
->attachments
[att_idx
];
1672 if (att
->attachment
->image
!= image
)
1675 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1676 radeon_emit(cs
, color_values
[0]);
1677 radeon_emit(cs
, color_values
[1]);
1679 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1683 * Set the clear color values to the image's metadata.
1686 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1687 struct radv_image
*image
,
1688 uint32_t color_values
[2])
1690 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1691 uint64_t va
= radv_buffer_get_va(image
->bo
);
1693 va
+= image
->offset
+ image
->clear_value_offset
;
1695 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1697 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, cmd_buffer
->state
.predicating
));
1698 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1699 S_370_WR_CONFIRM(1) |
1700 S_370_ENGINE_SEL(V_370_PFP
));
1701 radeon_emit(cs
, va
);
1702 radeon_emit(cs
, va
>> 32);
1703 radeon_emit(cs
, color_values
[0]);
1704 radeon_emit(cs
, color_values
[1]);
1708 * Update the clear color values for this image.
1711 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1712 struct radv_image
*image
,
1714 uint32_t color_values
[2])
1716 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1718 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1720 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1725 * Load the clear color values from the image's metadata.
1728 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1729 struct radv_image
*image
,
1732 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1733 uint64_t va
= radv_buffer_get_va(image
->bo
);
1735 va
+= image
->offset
+ image
->clear_value_offset
;
1737 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1740 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1742 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1743 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1744 radeon_emit(cs
, va
);
1745 radeon_emit(cs
, va
>> 32);
1746 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1749 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1750 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1751 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1752 COPY_DATA_COUNT_SEL
);
1753 radeon_emit(cs
, va
);
1754 radeon_emit(cs
, va
>> 32);
1755 radeon_emit(cs
, reg
>> 2);
1758 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1764 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1767 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1768 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1769 unsigned num_bpp64_colorbufs
= 0;
1771 /* this may happen for inherited secondary recording */
1775 for (i
= 0; i
< 8; ++i
) {
1776 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1777 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1778 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1782 int idx
= subpass
->color_attachments
[i
].attachment
;
1783 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1784 struct radv_image
*image
= att
->attachment
->image
;
1785 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1787 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1789 assert(att
->attachment
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1790 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1791 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1793 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1795 if (image
->planes
[0].surface
.bpe
>= 8)
1796 num_bpp64_colorbufs
++;
1799 if (subpass
->depth_stencil_attachment
) {
1800 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1801 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1802 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1803 struct radv_image
*image
= att
->attachment
->image
;
1804 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1805 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1806 cmd_buffer
->queue_family_index
,
1807 cmd_buffer
->queue_family_index
);
1808 /* We currently don't support writing decompressed HTILE */
1809 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1810 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1812 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1814 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1815 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1816 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1818 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1820 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1821 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1823 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1825 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1826 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1828 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1829 S_028208_BR_X(framebuffer
->width
) |
1830 S_028208_BR_Y(framebuffer
->height
));
1832 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1833 uint8_t watermark
= 4; /* Default value for GFX8. */
1835 /* For optimal DCC performance. */
1836 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1837 if (num_bpp64_colorbufs
>= 5) {
1844 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1845 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1846 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1849 if (cmd_buffer
->device
->dfsm_allowed
) {
1850 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1851 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1854 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1858 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1860 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1861 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1863 if (state
->index_type
!= state
->last_index_type
) {
1864 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1865 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1866 2, state
->index_type
);
1868 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1869 radeon_emit(cs
, state
->index_type
);
1872 state
->last_index_type
= state
->index_type
;
1875 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1876 radeon_emit(cs
, state
->index_va
);
1877 radeon_emit(cs
, state
->index_va
>> 32);
1879 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1880 radeon_emit(cs
, state
->max_index_count
);
1882 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1885 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1887 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1888 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1889 uint32_t pa_sc_mode_cntl_1
=
1890 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1891 uint32_t db_count_control
;
1893 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1894 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1895 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1896 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1897 has_perfect_queries
) {
1898 /* Re-enable out-of-order rasterization if the
1899 * bound pipeline supports it and if it's has
1900 * been disabled before starting any perfect
1901 * occlusion queries.
1903 radeon_set_context_reg(cmd_buffer
->cs
,
1904 R_028A4C_PA_SC_MODE_CNTL_1
,
1908 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1910 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1911 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1913 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1915 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1916 S_028004_SAMPLE_RATE(sample_rate
) |
1917 S_028004_ZPASS_ENABLE(1) |
1918 S_028004_SLICE_EVEN_ENABLE(1) |
1919 S_028004_SLICE_ODD_ENABLE(1);
1921 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1922 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1923 has_perfect_queries
) {
1924 /* If the bound pipeline has enabled
1925 * out-of-order rasterization, we should
1926 * disable it before starting any perfect
1927 * occlusion queries.
1929 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1931 radeon_set_context_reg(cmd_buffer
->cs
,
1932 R_028A4C_PA_SC_MODE_CNTL_1
,
1936 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1937 S_028004_SAMPLE_RATE(sample_rate
);
1941 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1943 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1947 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1949 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1951 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1952 radv_emit_viewport(cmd_buffer
);
1954 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1955 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1956 radv_emit_scissor(cmd_buffer
);
1958 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1959 radv_emit_line_width(cmd_buffer
);
1961 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1962 radv_emit_blend_constants(cmd_buffer
);
1964 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1965 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1966 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1967 radv_emit_stencil(cmd_buffer
);
1969 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1970 radv_emit_depth_bounds(cmd_buffer
);
1972 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1973 radv_emit_depth_bias(cmd_buffer
);
1975 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1976 radv_emit_discard_rectangle(cmd_buffer
);
1978 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
1979 radv_emit_sample_locations(cmd_buffer
);
1981 cmd_buffer
->state
.dirty
&= ~states
;
1985 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1986 VkPipelineBindPoint bind_point
)
1988 struct radv_descriptor_state
*descriptors_state
=
1989 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1990 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1993 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1998 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1999 set
->va
+= bo_offset
;
2003 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2004 VkPipelineBindPoint bind_point
)
2006 struct radv_descriptor_state
*descriptors_state
=
2007 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2008 uint32_t size
= MAX_SETS
* 4;
2012 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2013 256, &offset
, &ptr
))
2016 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2017 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2018 uint64_t set_va
= 0;
2019 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2020 if (descriptors_state
->valid
& (1u << i
))
2022 uptr
[0] = set_va
& 0xffffffff;
2025 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2028 if (cmd_buffer
->state
.pipeline
) {
2029 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2030 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2031 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2033 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2034 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2035 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2037 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2038 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2039 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2041 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2042 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2043 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2045 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2046 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2047 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2050 if (cmd_buffer
->state
.compute_pipeline
)
2051 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2052 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2056 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2057 VkShaderStageFlags stages
)
2059 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2060 VK_PIPELINE_BIND_POINT_COMPUTE
:
2061 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2062 struct radv_descriptor_state
*descriptors_state
=
2063 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2064 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2065 bool flush_indirect_descriptors
;
2067 if (!descriptors_state
->dirty
)
2070 if (descriptors_state
->push_dirty
)
2071 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2073 flush_indirect_descriptors
=
2074 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2075 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2076 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2077 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2079 if (flush_indirect_descriptors
)
2080 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2082 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2084 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2086 if (cmd_buffer
->state
.pipeline
) {
2087 radv_foreach_stage(stage
, stages
) {
2088 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2091 radv_emit_descriptor_pointers(cmd_buffer
,
2092 cmd_buffer
->state
.pipeline
,
2093 descriptors_state
, stage
);
2097 if (cmd_buffer
->state
.compute_pipeline
&&
2098 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2099 radv_emit_descriptor_pointers(cmd_buffer
,
2100 cmd_buffer
->state
.compute_pipeline
,
2102 MESA_SHADER_COMPUTE
);
2105 descriptors_state
->dirty
= 0;
2106 descriptors_state
->push_dirty
= false;
2108 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2110 if (unlikely(cmd_buffer
->device
->trace_bo
))
2111 radv_save_descriptors(cmd_buffer
, bind_point
);
2115 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2116 VkShaderStageFlags stages
)
2118 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2119 ? cmd_buffer
->state
.compute_pipeline
2120 : cmd_buffer
->state
.pipeline
;
2121 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2122 VK_PIPELINE_BIND_POINT_COMPUTE
:
2123 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2124 struct radv_descriptor_state
*descriptors_state
=
2125 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2126 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2127 struct radv_shader_variant
*shader
, *prev_shader
;
2128 bool need_push_constants
= false;
2133 stages
&= cmd_buffer
->push_constant_stages
;
2135 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2138 radv_foreach_stage(stage
, stages
) {
2139 if (!pipeline
->shaders
[stage
])
2142 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
2143 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
2145 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
2146 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
2148 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2149 AC_UD_INLINE_PUSH_CONSTANTS
,
2151 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2154 if (need_push_constants
) {
2155 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2156 16 * layout
->dynamic_offset_count
,
2157 256, &offset
, &ptr
))
2160 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2161 memcpy((char*)ptr
+ layout
->push_constant_size
,
2162 descriptors_state
->dynamic_buffers
,
2163 16 * layout
->dynamic_offset_count
);
2165 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2168 MAYBE_UNUSED
unsigned cdw_max
=
2169 radeon_check_space(cmd_buffer
->device
->ws
,
2170 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2173 radv_foreach_stage(stage
, stages
) {
2174 shader
= radv_get_shader(pipeline
, stage
);
2176 /* Avoid redundantly emitting the address for merged stages. */
2177 if (shader
&& shader
!= prev_shader
) {
2178 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2179 AC_UD_PUSH_CONSTANTS
, va
);
2181 prev_shader
= shader
;
2184 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2187 cmd_buffer
->push_constant_stages
&= ~stages
;
2191 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2192 bool pipeline_is_dirty
)
2194 if ((pipeline_is_dirty
||
2195 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2196 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2197 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
2198 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2202 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2205 /* allocate some descriptor state for vertex buffers */
2206 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2207 &vb_offset
, &vb_ptr
))
2210 for (i
= 0; i
< count
; i
++) {
2211 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2213 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2214 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2219 va
= radv_buffer_get_va(buffer
->bo
);
2221 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2222 va
+= offset
+ buffer
->offset
;
2224 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2225 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2226 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2228 desc
[2] = buffer
->size
- offset
;
2229 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2233 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2237 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2240 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2241 AC_UD_VS_VERTEX_BUFFERS
, va
);
2243 cmd_buffer
->state
.vb_va
= va
;
2244 cmd_buffer
->state
.vb_size
= count
* 16;
2245 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2247 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2251 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2253 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2254 struct radv_userdata_info
*loc
;
2257 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2258 if (!radv_get_shader(pipeline
, stage
))
2261 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2262 AC_UD_STREAMOUT_BUFFERS
);
2263 if (loc
->sgpr_idx
== -1)
2266 base_reg
= pipeline
->user_data_0
[stage
];
2268 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2269 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2272 if (pipeline
->gs_copy_shader
) {
2273 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2274 if (loc
->sgpr_idx
!= -1) {
2275 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2277 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2278 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2284 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2286 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2287 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2288 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2293 /* Allocate some descriptor state for streamout buffers. */
2294 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2295 MAX_SO_BUFFERS
* 16, 256,
2296 &so_offset
, &so_ptr
))
2299 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2300 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2301 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2303 if (!(so
->enabled_mask
& (1 << i
)))
2306 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2310 /* Set the descriptor.
2312 * On GFX8, the format must be non-INVALID, otherwise
2313 * the buffer will be considered not bound and store
2314 * instructions will be no-ops.
2317 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2318 desc
[2] = 0xffffffff;
2319 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2320 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2321 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2322 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2326 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2329 radv_emit_streamout_buffers(cmd_buffer
, va
);
2332 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2336 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2338 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2339 radv_flush_streamout_descriptors(cmd_buffer
);
2340 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2341 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2344 struct radv_draw_info
{
2346 * Number of vertices.
2351 * Index of the first vertex.
2353 int32_t vertex_offset
;
2356 * First instance id.
2358 uint32_t first_instance
;
2361 * Number of instances.
2363 uint32_t instance_count
;
2366 * First index (indexed draws only).
2368 uint32_t first_index
;
2371 * Whether it's an indexed draw.
2376 * Indirect draw parameters resource.
2378 struct radv_buffer
*indirect
;
2379 uint64_t indirect_offset
;
2383 * Draw count parameters resource.
2385 struct radv_buffer
*count_buffer
;
2386 uint64_t count_buffer_offset
;
2389 * Stream output parameters resource.
2391 struct radv_buffer
*strmout_buffer
;
2392 uint64_t strmout_buffer_offset
;
2396 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2397 const struct radv_draw_info
*draw_info
)
2399 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2400 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2401 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2402 uint32_t ia_multi_vgt_param
;
2403 int32_t primitive_reset_en
;
2406 ia_multi_vgt_param
=
2407 si_get_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2408 draw_info
->indirect
,
2409 !!draw_info
->strmout_buffer
,
2410 draw_info
->indirect
? 0 : draw_info
->count
);
2412 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2413 if (info
->chip_class
>= GFX9
) {
2414 radeon_set_uconfig_reg_idx(cs
,
2415 R_030960_IA_MULTI_VGT_PARAM
,
2416 4, ia_multi_vgt_param
);
2417 } else if (info
->chip_class
>= GFX7
) {
2418 radeon_set_context_reg_idx(cs
,
2419 R_028AA8_IA_MULTI_VGT_PARAM
,
2420 1, ia_multi_vgt_param
);
2422 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2423 ia_multi_vgt_param
);
2425 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2428 /* Primitive restart. */
2429 primitive_reset_en
=
2430 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2432 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2433 state
->last_primitive_reset_en
= primitive_reset_en
;
2434 if (info
->chip_class
>= GFX9
) {
2435 radeon_set_uconfig_reg(cs
,
2436 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2437 primitive_reset_en
);
2439 radeon_set_context_reg(cs
,
2440 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2441 primitive_reset_en
);
2445 if (primitive_reset_en
) {
2446 uint32_t primitive_reset_index
=
2447 state
->index_type
? 0xffffffffu
: 0xffffu
;
2449 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2450 radeon_set_context_reg(cs
,
2451 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2452 primitive_reset_index
);
2453 state
->last_primitive_reset_index
= primitive_reset_index
;
2457 if (draw_info
->strmout_buffer
) {
2458 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2460 va
+= draw_info
->strmout_buffer
->offset
+
2461 draw_info
->strmout_buffer_offset
;
2463 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2466 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2467 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2468 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2469 COPY_DATA_WR_CONFIRM
);
2470 radeon_emit(cs
, va
);
2471 radeon_emit(cs
, va
>> 32);
2472 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2473 radeon_emit(cs
, 0); /* unused */
2475 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2479 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2480 VkPipelineStageFlags src_stage_mask
)
2482 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2483 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2484 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2485 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2486 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2489 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2490 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2491 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2492 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2493 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2494 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2495 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2496 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2497 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2498 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2499 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2500 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2501 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2502 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2503 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2504 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2505 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2509 static enum radv_cmd_flush_bits
2510 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2511 VkAccessFlags src_flags
,
2512 struct radv_image
*image
)
2514 bool flush_CB_meta
= true, flush_DB_meta
= true;
2515 enum radv_cmd_flush_bits flush_bits
= 0;
2519 if (!radv_image_has_CB_metadata(image
))
2520 flush_CB_meta
= false;
2521 if (!radv_image_has_htile(image
))
2522 flush_DB_meta
= false;
2525 for_each_bit(b
, src_flags
) {
2526 switch ((VkAccessFlagBits
)(1 << b
)) {
2527 case VK_ACCESS_SHADER_WRITE_BIT
:
2528 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2529 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2530 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2532 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2533 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2535 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2537 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2538 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2540 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2542 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2543 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2544 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2545 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2548 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2550 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2559 static enum radv_cmd_flush_bits
2560 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2561 VkAccessFlags dst_flags
,
2562 struct radv_image
*image
)
2564 bool flush_CB_meta
= true, flush_DB_meta
= true;
2565 enum radv_cmd_flush_bits flush_bits
= 0;
2566 bool flush_CB
= true, flush_DB
= true;
2567 bool image_is_coherent
= false;
2571 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2576 if (!radv_image_has_CB_metadata(image
))
2577 flush_CB_meta
= false;
2578 if (!radv_image_has_htile(image
))
2579 flush_DB_meta
= false;
2581 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2582 if (image
->info
.samples
== 1 &&
2583 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2584 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2585 !vk_format_is_stencil(image
->vk_format
)) {
2586 /* Single-sample color and single-sample depth
2587 * (not stencil) are coherent with shaders on
2590 image_is_coherent
= true;
2595 for_each_bit(b
, dst_flags
) {
2596 switch ((VkAccessFlagBits
)(1 << b
)) {
2597 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2598 case VK_ACCESS_INDEX_READ_BIT
:
2599 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2601 case VK_ACCESS_UNIFORM_READ_BIT
:
2602 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2604 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2605 case VK_ACCESS_TRANSFER_READ_BIT
:
2606 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2607 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2608 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2610 case VK_ACCESS_SHADER_READ_BIT
:
2611 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2613 if (!image_is_coherent
)
2614 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2616 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2618 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2620 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2622 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2624 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2626 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2635 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2636 const struct radv_subpass_barrier
*barrier
)
2638 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2640 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2641 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2645 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2646 struct radv_subpass_attachment att
)
2648 unsigned idx
= att
.attachment
;
2649 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2650 VkImageSubresourceRange range
;
2651 range
.aspectMask
= 0;
2652 range
.baseMipLevel
= view
->base_mip
;
2653 range
.levelCount
= 1;
2654 range
.baseArrayLayer
= view
->base_layer
;
2655 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2657 if (cmd_buffer
->state
.subpass
->view_mask
) {
2658 /* If the current subpass uses multiview, the driver might have
2659 * performed a fast color/depth clear to the whole image
2660 * (including all layers). To make sure the driver will
2661 * decompress the image correctly (if needed), we have to
2662 * account for the "real" number of layers. If the view mask is
2663 * sparse, this will decompress more layers than needed.
2665 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2668 radv_handle_image_transition(cmd_buffer
,
2670 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2671 att
.layout
, 0, 0, &range
);
2673 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2679 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2680 const struct radv_subpass
*subpass
)
2682 cmd_buffer
->state
.subpass
= subpass
;
2684 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2688 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2689 struct radv_render_pass
*pass
,
2690 const VkRenderPassBeginInfo
*info
)
2692 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2694 if (pass
->attachment_count
== 0) {
2695 state
->attachments
= NULL
;
2699 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2700 pass
->attachment_count
*
2701 sizeof(state
->attachments
[0]),
2702 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2703 if (state
->attachments
== NULL
) {
2704 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2705 return cmd_buffer
->record_result
;
2708 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2709 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2710 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2711 VkImageAspectFlags clear_aspects
= 0;
2713 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2714 /* color attachment */
2715 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2716 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2719 /* depthstencil attachment */
2720 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2721 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2722 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2723 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2724 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2725 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2727 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2728 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2729 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2733 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2734 state
->attachments
[i
].cleared_views
= 0;
2735 if (clear_aspects
&& info
) {
2736 assert(info
->clearValueCount
> i
);
2737 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2740 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2746 VkResult
radv_AllocateCommandBuffers(
2748 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2749 VkCommandBuffer
*pCommandBuffers
)
2751 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2752 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2754 VkResult result
= VK_SUCCESS
;
2757 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2759 if (!list_empty(&pool
->free_cmd_buffers
)) {
2760 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2762 list_del(&cmd_buffer
->pool_link
);
2763 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2765 result
= radv_reset_cmd_buffer(cmd_buffer
);
2766 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2767 cmd_buffer
->level
= pAllocateInfo
->level
;
2769 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2771 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2772 &pCommandBuffers
[i
]);
2774 if (result
!= VK_SUCCESS
)
2778 if (result
!= VK_SUCCESS
) {
2779 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2780 i
, pCommandBuffers
);
2782 /* From the Vulkan 1.0.66 spec:
2784 * "vkAllocateCommandBuffers can be used to create multiple
2785 * command buffers. If the creation of any of those command
2786 * buffers fails, the implementation must destroy all
2787 * successfully created command buffer objects from this
2788 * command, set all entries of the pCommandBuffers array to
2789 * NULL and return the error."
2791 memset(pCommandBuffers
, 0,
2792 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2798 void radv_FreeCommandBuffers(
2800 VkCommandPool commandPool
,
2801 uint32_t commandBufferCount
,
2802 const VkCommandBuffer
*pCommandBuffers
)
2804 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2805 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2808 if (cmd_buffer
->pool
) {
2809 list_del(&cmd_buffer
->pool_link
);
2810 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2812 radv_cmd_buffer_destroy(cmd_buffer
);
2818 VkResult
radv_ResetCommandBuffer(
2819 VkCommandBuffer commandBuffer
,
2820 VkCommandBufferResetFlags flags
)
2822 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2823 return radv_reset_cmd_buffer(cmd_buffer
);
2826 VkResult
radv_BeginCommandBuffer(
2827 VkCommandBuffer commandBuffer
,
2828 const VkCommandBufferBeginInfo
*pBeginInfo
)
2830 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2831 VkResult result
= VK_SUCCESS
;
2833 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2834 /* If the command buffer has already been resetted with
2835 * vkResetCommandBuffer, no need to do it again.
2837 result
= radv_reset_cmd_buffer(cmd_buffer
);
2838 if (result
!= VK_SUCCESS
)
2842 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2843 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2844 cmd_buffer
->state
.last_index_type
= -1;
2845 cmd_buffer
->state
.last_num_instances
= -1;
2846 cmd_buffer
->state
.last_vertex_offset
= -1;
2847 cmd_buffer
->state
.last_first_instance
= -1;
2848 cmd_buffer
->state
.predication_type
= -1;
2849 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2851 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2852 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2853 assert(pBeginInfo
->pInheritanceInfo
);
2854 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2855 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2857 struct radv_subpass
*subpass
=
2858 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2860 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2861 if (result
!= VK_SUCCESS
)
2864 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
2867 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2868 struct radv_device
*device
= cmd_buffer
->device
;
2870 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2873 radv_cmd_buffer_trace_emit(cmd_buffer
);
2876 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2881 void radv_CmdBindVertexBuffers(
2882 VkCommandBuffer commandBuffer
,
2883 uint32_t firstBinding
,
2884 uint32_t bindingCount
,
2885 const VkBuffer
* pBuffers
,
2886 const VkDeviceSize
* pOffsets
)
2888 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2889 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2890 bool changed
= false;
2892 /* We have to defer setting up vertex buffer since we need the buffer
2893 * stride from the pipeline. */
2895 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2896 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2897 uint32_t idx
= firstBinding
+ i
;
2900 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2901 vb
[idx
].offset
!= pOffsets
[i
])) {
2905 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2906 vb
[idx
].offset
= pOffsets
[i
];
2908 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2909 vb
[idx
].buffer
->bo
);
2913 /* No state changes. */
2917 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2920 void radv_CmdBindIndexBuffer(
2921 VkCommandBuffer commandBuffer
,
2923 VkDeviceSize offset
,
2924 VkIndexType indexType
)
2926 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2927 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2929 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2930 cmd_buffer
->state
.index_offset
== offset
&&
2931 cmd_buffer
->state
.index_type
== indexType
) {
2932 /* No state changes. */
2936 cmd_buffer
->state
.index_buffer
= index_buffer
;
2937 cmd_buffer
->state
.index_offset
= offset
;
2938 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2939 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2940 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2942 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2943 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2944 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2945 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2950 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2951 VkPipelineBindPoint bind_point
,
2952 struct radv_descriptor_set
*set
, unsigned idx
)
2954 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2956 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2959 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2961 if (!cmd_buffer
->device
->use_global_bo_list
) {
2962 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2963 if (set
->descriptors
[j
])
2964 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2968 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2971 void radv_CmdBindDescriptorSets(
2972 VkCommandBuffer commandBuffer
,
2973 VkPipelineBindPoint pipelineBindPoint
,
2974 VkPipelineLayout _layout
,
2976 uint32_t descriptorSetCount
,
2977 const VkDescriptorSet
* pDescriptorSets
,
2978 uint32_t dynamicOffsetCount
,
2979 const uint32_t* pDynamicOffsets
)
2981 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2982 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2983 unsigned dyn_idx
= 0;
2985 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2986 struct radv_descriptor_state
*descriptors_state
=
2987 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2989 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2990 unsigned idx
= i
+ firstSet
;
2991 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2992 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2994 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2995 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2996 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2997 assert(dyn_idx
< dynamicOffsetCount
);
2999 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3000 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3002 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3003 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3004 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3005 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3006 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3007 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3008 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3009 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3010 cmd_buffer
->push_constant_stages
|=
3011 set
->layout
->dynamic_shader_stages
;
3016 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3017 struct radv_descriptor_set
*set
,
3018 struct radv_descriptor_set_layout
*layout
,
3019 VkPipelineBindPoint bind_point
)
3021 struct radv_descriptor_state
*descriptors_state
=
3022 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3023 set
->size
= layout
->size
;
3024 set
->layout
= layout
;
3026 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3027 size_t new_size
= MAX2(set
->size
, 1024);
3028 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3029 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3031 free(set
->mapped_ptr
);
3032 set
->mapped_ptr
= malloc(new_size
);
3034 if (!set
->mapped_ptr
) {
3035 descriptors_state
->push_set
.capacity
= 0;
3036 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3040 descriptors_state
->push_set
.capacity
= new_size
;
3046 void radv_meta_push_descriptor_set(
3047 struct radv_cmd_buffer
* cmd_buffer
,
3048 VkPipelineBindPoint pipelineBindPoint
,
3049 VkPipelineLayout _layout
,
3051 uint32_t descriptorWriteCount
,
3052 const VkWriteDescriptorSet
* pDescriptorWrites
)
3054 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3055 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3059 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3061 push_set
->size
= layout
->set
[set
].layout
->size
;
3062 push_set
->layout
= layout
->set
[set
].layout
;
3064 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3066 (void**) &push_set
->mapped_ptr
))
3069 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3070 push_set
->va
+= bo_offset
;
3072 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3073 radv_descriptor_set_to_handle(push_set
),
3074 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3076 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3079 void radv_CmdPushDescriptorSetKHR(
3080 VkCommandBuffer commandBuffer
,
3081 VkPipelineBindPoint pipelineBindPoint
,
3082 VkPipelineLayout _layout
,
3084 uint32_t descriptorWriteCount
,
3085 const VkWriteDescriptorSet
* pDescriptorWrites
)
3087 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3088 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3089 struct radv_descriptor_state
*descriptors_state
=
3090 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3091 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3093 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3095 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3096 layout
->set
[set
].layout
,
3100 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3101 radv_descriptor_set_to_handle(push_set
),
3102 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3104 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3105 descriptors_state
->push_dirty
= true;
3108 void radv_CmdPushDescriptorSetWithTemplateKHR(
3109 VkCommandBuffer commandBuffer
,
3110 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3111 VkPipelineLayout _layout
,
3115 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3116 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3117 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3118 struct radv_descriptor_state
*descriptors_state
=
3119 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3120 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3122 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3124 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3125 layout
->set
[set
].layout
,
3129 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3130 descriptorUpdateTemplate
, pData
);
3132 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3133 descriptors_state
->push_dirty
= true;
3136 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3137 VkPipelineLayout layout
,
3138 VkShaderStageFlags stageFlags
,
3141 const void* pValues
)
3143 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3144 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3145 cmd_buffer
->push_constant_stages
|= stageFlags
;
3148 VkResult
radv_EndCommandBuffer(
3149 VkCommandBuffer commandBuffer
)
3151 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3153 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3154 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3155 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3157 /* Make sure to sync all pending active queries at the end of
3160 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3162 si_emit_cache_flush(cmd_buffer
);
3165 /* Make sure CP DMA is idle at the end of IBs because the kernel
3166 * doesn't wait for it.
3168 si_cp_dma_wait_for_idle(cmd_buffer
);
3170 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3172 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3173 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3175 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3177 return cmd_buffer
->record_result
;
3181 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3183 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3185 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3188 assert(!pipeline
->ctx_cs
.cdw
);
3190 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3192 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3193 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3195 cmd_buffer
->compute_scratch_size_needed
=
3196 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3197 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3199 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3200 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3202 if (unlikely(cmd_buffer
->device
->trace_bo
))
3203 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3206 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3207 VkPipelineBindPoint bind_point
)
3209 struct radv_descriptor_state
*descriptors_state
=
3210 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3212 descriptors_state
->dirty
|= descriptors_state
->valid
;
3215 void radv_CmdBindPipeline(
3216 VkCommandBuffer commandBuffer
,
3217 VkPipelineBindPoint pipelineBindPoint
,
3218 VkPipeline _pipeline
)
3220 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3221 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3223 switch (pipelineBindPoint
) {
3224 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3225 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3227 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3229 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3230 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3232 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3233 if (cmd_buffer
->state
.pipeline
== pipeline
)
3235 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3237 cmd_buffer
->state
.pipeline
= pipeline
;
3241 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3242 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3244 /* the new vertex shader might not have the same user regs */
3245 cmd_buffer
->state
.last_first_instance
= -1;
3246 cmd_buffer
->state
.last_vertex_offset
= -1;
3248 /* Prefetch all pipeline shaders at first draw time. */
3249 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3251 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3252 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3254 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3255 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3256 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3257 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3259 if (radv_pipeline_has_tess(pipeline
))
3260 cmd_buffer
->tess_rings_needed
= true;
3263 assert(!"invalid bind point");
3268 void radv_CmdSetViewport(
3269 VkCommandBuffer commandBuffer
,
3270 uint32_t firstViewport
,
3271 uint32_t viewportCount
,
3272 const VkViewport
* pViewports
)
3274 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3275 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3276 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3278 assert(firstViewport
< MAX_VIEWPORTS
);
3279 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3281 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3282 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3286 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3287 viewportCount
* sizeof(*pViewports
));
3289 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3292 void radv_CmdSetScissor(
3293 VkCommandBuffer commandBuffer
,
3294 uint32_t firstScissor
,
3295 uint32_t scissorCount
,
3296 const VkRect2D
* pScissors
)
3298 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3299 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3300 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3302 assert(firstScissor
< MAX_SCISSORS
);
3303 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3305 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3306 scissorCount
* sizeof(*pScissors
))) {
3310 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3311 scissorCount
* sizeof(*pScissors
));
3313 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3316 void radv_CmdSetLineWidth(
3317 VkCommandBuffer commandBuffer
,
3320 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3322 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3325 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3326 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3329 void radv_CmdSetDepthBias(
3330 VkCommandBuffer commandBuffer
,
3331 float depthBiasConstantFactor
,
3332 float depthBiasClamp
,
3333 float depthBiasSlopeFactor
)
3335 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3336 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3338 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3339 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3340 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3344 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3345 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3346 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3348 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3351 void radv_CmdSetBlendConstants(
3352 VkCommandBuffer commandBuffer
,
3353 const float blendConstants
[4])
3355 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3356 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3358 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3361 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3363 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3366 void radv_CmdSetDepthBounds(
3367 VkCommandBuffer commandBuffer
,
3368 float minDepthBounds
,
3369 float maxDepthBounds
)
3371 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3372 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3374 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3375 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3379 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3380 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3382 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3385 void radv_CmdSetStencilCompareMask(
3386 VkCommandBuffer commandBuffer
,
3387 VkStencilFaceFlags faceMask
,
3388 uint32_t compareMask
)
3390 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3391 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3392 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3393 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3395 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3396 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3400 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3401 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3402 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3403 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3405 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3408 void radv_CmdSetStencilWriteMask(
3409 VkCommandBuffer commandBuffer
,
3410 VkStencilFaceFlags faceMask
,
3413 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3414 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3415 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3416 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3418 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3419 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3423 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3424 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3425 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3426 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3428 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3431 void radv_CmdSetStencilReference(
3432 VkCommandBuffer commandBuffer
,
3433 VkStencilFaceFlags faceMask
,
3436 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3437 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3438 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3439 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3441 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3442 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3446 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3447 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3448 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3449 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3451 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3454 void radv_CmdSetDiscardRectangleEXT(
3455 VkCommandBuffer commandBuffer
,
3456 uint32_t firstDiscardRectangle
,
3457 uint32_t discardRectangleCount
,
3458 const VkRect2D
* pDiscardRectangles
)
3460 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3461 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3462 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3464 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3465 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3467 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3468 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3472 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3473 pDiscardRectangles
, discardRectangleCount
);
3475 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3478 void radv_CmdSetSampleLocationsEXT(
3479 VkCommandBuffer commandBuffer
,
3480 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3482 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3483 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3485 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3487 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3488 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3489 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3490 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3491 pSampleLocationsInfo
->pSampleLocations
,
3492 pSampleLocationsInfo
->sampleLocationsCount
);
3494 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3497 void radv_CmdExecuteCommands(
3498 VkCommandBuffer commandBuffer
,
3499 uint32_t commandBufferCount
,
3500 const VkCommandBuffer
* pCmdBuffers
)
3502 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3504 assert(commandBufferCount
> 0);
3506 /* Emit pending flushes on primary prior to executing secondary */
3507 si_emit_cache_flush(primary
);
3509 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3510 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3512 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3513 secondary
->scratch_size_needed
);
3514 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3515 secondary
->compute_scratch_size_needed
);
3517 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3518 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3519 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3520 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3521 if (secondary
->tess_rings_needed
)
3522 primary
->tess_rings_needed
= true;
3523 if (secondary
->sample_positions_needed
)
3524 primary
->sample_positions_needed
= true;
3526 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3529 /* When the secondary command buffer is compute only we don't
3530 * need to re-emit the current graphics pipeline.
3532 if (secondary
->state
.emitted_pipeline
) {
3533 primary
->state
.emitted_pipeline
=
3534 secondary
->state
.emitted_pipeline
;
3537 /* When the secondary command buffer is graphics only we don't
3538 * need to re-emit the current compute pipeline.
3540 if (secondary
->state
.emitted_compute_pipeline
) {
3541 primary
->state
.emitted_compute_pipeline
=
3542 secondary
->state
.emitted_compute_pipeline
;
3545 /* Only re-emit the draw packets when needed. */
3546 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3547 primary
->state
.last_primitive_reset_en
=
3548 secondary
->state
.last_primitive_reset_en
;
3551 if (secondary
->state
.last_primitive_reset_index
) {
3552 primary
->state
.last_primitive_reset_index
=
3553 secondary
->state
.last_primitive_reset_index
;
3556 if (secondary
->state
.last_ia_multi_vgt_param
) {
3557 primary
->state
.last_ia_multi_vgt_param
=
3558 secondary
->state
.last_ia_multi_vgt_param
;
3561 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3562 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3563 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3565 if (secondary
->state
.last_index_type
!= -1) {
3566 primary
->state
.last_index_type
=
3567 secondary
->state
.last_index_type
;
3571 /* After executing commands from secondary buffers we have to dirty
3574 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3575 RADV_CMD_DIRTY_INDEX_BUFFER
|
3576 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3577 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3578 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3581 VkResult
radv_CreateCommandPool(
3583 const VkCommandPoolCreateInfo
* pCreateInfo
,
3584 const VkAllocationCallbacks
* pAllocator
,
3585 VkCommandPool
* pCmdPool
)
3587 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3588 struct radv_cmd_pool
*pool
;
3590 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3591 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3593 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3596 pool
->alloc
= *pAllocator
;
3598 pool
->alloc
= device
->alloc
;
3600 list_inithead(&pool
->cmd_buffers
);
3601 list_inithead(&pool
->free_cmd_buffers
);
3603 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3605 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3611 void radv_DestroyCommandPool(
3613 VkCommandPool commandPool
,
3614 const VkAllocationCallbacks
* pAllocator
)
3616 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3617 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3622 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3623 &pool
->cmd_buffers
, pool_link
) {
3624 radv_cmd_buffer_destroy(cmd_buffer
);
3627 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3628 &pool
->free_cmd_buffers
, pool_link
) {
3629 radv_cmd_buffer_destroy(cmd_buffer
);
3632 vk_free2(&device
->alloc
, pAllocator
, pool
);
3635 VkResult
radv_ResetCommandPool(
3637 VkCommandPool commandPool
,
3638 VkCommandPoolResetFlags flags
)
3640 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3643 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3644 &pool
->cmd_buffers
, pool_link
) {
3645 result
= radv_reset_cmd_buffer(cmd_buffer
);
3646 if (result
!= VK_SUCCESS
)
3653 void radv_TrimCommandPool(
3655 VkCommandPool commandPool
,
3656 VkCommandPoolTrimFlags flags
)
3658 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3663 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3664 &pool
->free_cmd_buffers
, pool_link
) {
3665 radv_cmd_buffer_destroy(cmd_buffer
);
3670 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
3672 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3673 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
3675 /* The id of this subpass shouldn't exceed the number of subpasses in
3676 * this render pass minus 1.
3678 assert(subpass_id
< state
->pass
->subpass_count
);
3683 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3684 uint32_t subpass_id
)
3686 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3687 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
3689 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3690 cmd_buffer
->cs
, 4096);
3692 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
3694 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3696 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3697 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3698 if (a
== VK_ATTACHMENT_UNUSED
)
3701 radv_handle_subpass_image_transition(cmd_buffer
,
3702 subpass
->attachments
[i
]);
3705 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3707 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3711 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
3713 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3714 const struct radv_subpass
*subpass
= state
->subpass
;
3715 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3717 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3719 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3720 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3721 if (a
== VK_ATTACHMENT_UNUSED
)
3724 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3727 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
3728 radv_handle_subpass_image_transition(cmd_buffer
,
3729 (struct radv_subpass_attachment
){a
, layout
});
3733 void radv_CmdBeginRenderPass(
3734 VkCommandBuffer commandBuffer
,
3735 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3736 VkSubpassContents contents
)
3738 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3739 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3740 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3743 cmd_buffer
->state
.framebuffer
= framebuffer
;
3744 cmd_buffer
->state
.pass
= pass
;
3745 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3747 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3748 if (result
!= VK_SUCCESS
)
3751 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
3754 void radv_CmdBeginRenderPass2KHR(
3755 VkCommandBuffer commandBuffer
,
3756 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3757 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3759 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3760 pSubpassBeginInfo
->contents
);
3763 void radv_CmdNextSubpass(
3764 VkCommandBuffer commandBuffer
,
3765 VkSubpassContents contents
)
3767 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3769 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
3770 radv_cmd_buffer_end_subpass(cmd_buffer
);
3771 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3774 void radv_CmdNextSubpass2KHR(
3775 VkCommandBuffer commandBuffer
,
3776 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3777 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3779 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3782 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3784 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3785 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3786 if (!radv_get_shader(pipeline
, stage
))
3789 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3790 if (loc
->sgpr_idx
== -1)
3792 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3793 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3796 if (pipeline
->gs_copy_shader
) {
3797 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3798 if (loc
->sgpr_idx
!= -1) {
3799 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3800 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3806 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3807 uint32_t vertex_count
,
3810 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3811 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3812 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3813 S_0287F0_USE_OPAQUE(use_opaque
));
3817 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3819 uint32_t index_count
)
3821 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3822 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3823 radeon_emit(cmd_buffer
->cs
, index_va
);
3824 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3825 radeon_emit(cmd_buffer
->cs
, index_count
);
3826 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3830 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3832 uint32_t draw_count
,
3836 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3837 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3838 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3839 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3840 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3841 bool predicating
= cmd_buffer
->state
.predicating
;
3844 /* just reset draw state for vertex data */
3845 cmd_buffer
->state
.last_first_instance
= -1;
3846 cmd_buffer
->state
.last_num_instances
= -1;
3847 cmd_buffer
->state
.last_vertex_offset
= -1;
3849 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3850 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3851 PKT3_DRAW_INDIRECT
, 3, predicating
));
3853 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3854 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3855 radeon_emit(cs
, di_src_sel
);
3857 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3858 PKT3_DRAW_INDIRECT_MULTI
,
3861 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3862 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3863 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3864 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3865 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3866 radeon_emit(cs
, draw_count
); /* count */
3867 radeon_emit(cs
, count_va
); /* count_addr */
3868 radeon_emit(cs
, count_va
>> 32);
3869 radeon_emit(cs
, stride
); /* stride */
3870 radeon_emit(cs
, di_src_sel
);
3875 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3876 const struct radv_draw_info
*info
)
3878 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3879 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3880 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3882 if (info
->indirect
) {
3883 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3884 uint64_t count_va
= 0;
3886 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3888 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3890 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3892 radeon_emit(cs
, va
);
3893 radeon_emit(cs
, va
>> 32);
3895 if (info
->count_buffer
) {
3896 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3897 count_va
+= info
->count_buffer
->offset
+
3898 info
->count_buffer_offset
;
3900 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3903 if (!state
->subpass
->view_mask
) {
3904 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3911 for_each_bit(i
, state
->subpass
->view_mask
) {
3912 radv_emit_view_index(cmd_buffer
, i
);
3914 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3922 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3924 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3925 info
->first_instance
!= state
->last_first_instance
) {
3926 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3927 state
->pipeline
->graphics
.vtx_emit_num
);
3929 radeon_emit(cs
, info
->vertex_offset
);
3930 radeon_emit(cs
, info
->first_instance
);
3931 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3933 state
->last_first_instance
= info
->first_instance
;
3934 state
->last_vertex_offset
= info
->vertex_offset
;
3937 if (state
->last_num_instances
!= info
->instance_count
) {
3938 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3939 radeon_emit(cs
, info
->instance_count
);
3940 state
->last_num_instances
= info
->instance_count
;
3943 if (info
->indexed
) {
3944 int index_size
= state
->index_type
? 4 : 2;
3947 index_va
= state
->index_va
;
3948 index_va
+= info
->first_index
* index_size
;
3950 if (!state
->subpass
->view_mask
) {
3951 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3956 for_each_bit(i
, state
->subpass
->view_mask
) {
3957 radv_emit_view_index(cmd_buffer
, i
);
3959 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3965 if (!state
->subpass
->view_mask
) {
3966 radv_cs_emit_draw_packet(cmd_buffer
,
3968 !!info
->strmout_buffer
);
3971 for_each_bit(i
, state
->subpass
->view_mask
) {
3972 radv_emit_view_index(cmd_buffer
, i
);
3974 radv_cs_emit_draw_packet(cmd_buffer
,
3976 !!info
->strmout_buffer
);
3984 * Vega and raven have a bug which triggers if there are multiple context
3985 * register contexts active at the same time with different scissor values.
3987 * There are two possible workarounds:
3988 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3989 * there is only ever 1 active set of scissor values at the same time.
3991 * 2) Whenever the hardware switches contexts we have to set the scissor
3992 * registers again even if it is a noop. That way the new context gets
3993 * the correct scissor values.
3995 * This implements option 2. radv_need_late_scissor_emission needs to
3996 * return true on affected HW if radv_emit_all_graphics_states sets
3997 * any context registers.
3999 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4000 const struct radv_draw_info
*info
)
4002 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4004 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
4007 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4010 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4012 /* Index, vertex and streamout buffers don't change context regs, and
4013 * pipeline is already handled.
4015 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4016 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4017 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4018 RADV_CMD_DIRTY_PIPELINE
);
4020 if (cmd_buffer
->state
.dirty
& used_states
)
4023 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4024 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
4031 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4032 const struct radv_draw_info
*info
)
4034 bool late_scissor_emission
;
4036 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4037 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4038 radv_emit_rbplus_state(cmd_buffer
);
4040 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4041 radv_emit_graphics_pipeline(cmd_buffer
);
4043 /* This should be before the cmd_buffer->state.dirty is cleared
4044 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4045 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4046 late_scissor_emission
=
4047 radv_need_late_scissor_emission(cmd_buffer
, info
);
4049 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4050 radv_emit_framebuffer_state(cmd_buffer
);
4052 if (info
->indexed
) {
4053 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4054 radv_emit_index_buffer(cmd_buffer
);
4056 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4057 * so the state must be re-emitted before the next indexed
4060 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4061 cmd_buffer
->state
.last_index_type
= -1;
4062 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4066 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4068 radv_emit_draw_registers(cmd_buffer
, info
);
4070 if (late_scissor_emission
)
4071 radv_emit_scissor(cmd_buffer
);
4075 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4076 const struct radv_draw_info
*info
)
4078 struct radeon_info
*rad_info
=
4079 &cmd_buffer
->device
->physical_device
->rad_info
;
4081 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4082 bool pipeline_is_dirty
=
4083 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4084 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4086 MAYBE_UNUSED
unsigned cdw_max
=
4087 radeon_check_space(cmd_buffer
->device
->ws
,
4088 cmd_buffer
->cs
, 4096);
4090 if (likely(!info
->indirect
)) {
4091 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4092 * no workaround for indirect draws, but we can at least skip
4095 if (unlikely(!info
->instance_count
))
4098 /* Handle count == 0. */
4099 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4103 /* Use optimal packet order based on whether we need to sync the
4106 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4107 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4108 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4109 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4110 /* If we have to wait for idle, set all states first, so that
4111 * all SET packets are processed in parallel with previous draw
4112 * calls. Then upload descriptors, set shader pointers, and
4113 * draw, and prefetch at the end. This ensures that the time
4114 * the CUs are idle is very short. (there are only SET_SH
4115 * packets between the wait and the draw)
4117 radv_emit_all_graphics_states(cmd_buffer
, info
);
4118 si_emit_cache_flush(cmd_buffer
);
4119 /* <-- CUs are idle here --> */
4121 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4123 radv_emit_draw_packets(cmd_buffer
, info
);
4124 /* <-- CUs are busy here --> */
4126 /* Start prefetches after the draw has been started. Both will
4127 * run in parallel, but starting the draw first is more
4130 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4131 radv_emit_prefetch_L2(cmd_buffer
,
4132 cmd_buffer
->state
.pipeline
, false);
4135 /* If we don't wait for idle, start prefetches first, then set
4136 * states, and draw at the end.
4138 si_emit_cache_flush(cmd_buffer
);
4140 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4141 /* Only prefetch the vertex shader and VBO descriptors
4142 * in order to start the draw as soon as possible.
4144 radv_emit_prefetch_L2(cmd_buffer
,
4145 cmd_buffer
->state
.pipeline
, true);
4148 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4150 radv_emit_all_graphics_states(cmd_buffer
, info
);
4151 radv_emit_draw_packets(cmd_buffer
, info
);
4153 /* Prefetch the remaining shaders after the draw has been
4156 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4157 radv_emit_prefetch_L2(cmd_buffer
,
4158 cmd_buffer
->state
.pipeline
, false);
4162 /* Workaround for a VGT hang when streamout is enabled.
4163 * It must be done after drawing.
4165 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4166 (rad_info
->family
== CHIP_HAWAII
||
4167 rad_info
->family
== CHIP_TONGA
||
4168 rad_info
->family
== CHIP_FIJI
)) {
4169 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4172 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4173 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4177 VkCommandBuffer commandBuffer
,
4178 uint32_t vertexCount
,
4179 uint32_t instanceCount
,
4180 uint32_t firstVertex
,
4181 uint32_t firstInstance
)
4183 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4184 struct radv_draw_info info
= {};
4186 info
.count
= vertexCount
;
4187 info
.instance_count
= instanceCount
;
4188 info
.first_instance
= firstInstance
;
4189 info
.vertex_offset
= firstVertex
;
4191 radv_draw(cmd_buffer
, &info
);
4194 void radv_CmdDrawIndexed(
4195 VkCommandBuffer commandBuffer
,
4196 uint32_t indexCount
,
4197 uint32_t instanceCount
,
4198 uint32_t firstIndex
,
4199 int32_t vertexOffset
,
4200 uint32_t firstInstance
)
4202 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4203 struct radv_draw_info info
= {};
4205 info
.indexed
= true;
4206 info
.count
= indexCount
;
4207 info
.instance_count
= instanceCount
;
4208 info
.first_index
= firstIndex
;
4209 info
.vertex_offset
= vertexOffset
;
4210 info
.first_instance
= firstInstance
;
4212 radv_draw(cmd_buffer
, &info
);
4215 void radv_CmdDrawIndirect(
4216 VkCommandBuffer commandBuffer
,
4218 VkDeviceSize offset
,
4222 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4223 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4224 struct radv_draw_info info
= {};
4226 info
.count
= drawCount
;
4227 info
.indirect
= buffer
;
4228 info
.indirect_offset
= offset
;
4229 info
.stride
= stride
;
4231 radv_draw(cmd_buffer
, &info
);
4234 void radv_CmdDrawIndexedIndirect(
4235 VkCommandBuffer commandBuffer
,
4237 VkDeviceSize offset
,
4241 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4242 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4243 struct radv_draw_info info
= {};
4245 info
.indexed
= true;
4246 info
.count
= drawCount
;
4247 info
.indirect
= buffer
;
4248 info
.indirect_offset
= offset
;
4249 info
.stride
= stride
;
4251 radv_draw(cmd_buffer
, &info
);
4254 void radv_CmdDrawIndirectCountKHR(
4255 VkCommandBuffer commandBuffer
,
4257 VkDeviceSize offset
,
4258 VkBuffer _countBuffer
,
4259 VkDeviceSize countBufferOffset
,
4260 uint32_t maxDrawCount
,
4263 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4264 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4265 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4266 struct radv_draw_info info
= {};
4268 info
.count
= maxDrawCount
;
4269 info
.indirect
= buffer
;
4270 info
.indirect_offset
= offset
;
4271 info
.count_buffer
= count_buffer
;
4272 info
.count_buffer_offset
= countBufferOffset
;
4273 info
.stride
= stride
;
4275 radv_draw(cmd_buffer
, &info
);
4278 void radv_CmdDrawIndexedIndirectCountKHR(
4279 VkCommandBuffer commandBuffer
,
4281 VkDeviceSize offset
,
4282 VkBuffer _countBuffer
,
4283 VkDeviceSize countBufferOffset
,
4284 uint32_t maxDrawCount
,
4287 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4288 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4289 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4290 struct radv_draw_info info
= {};
4292 info
.indexed
= true;
4293 info
.count
= maxDrawCount
;
4294 info
.indirect
= buffer
;
4295 info
.indirect_offset
= offset
;
4296 info
.count_buffer
= count_buffer
;
4297 info
.count_buffer_offset
= countBufferOffset
;
4298 info
.stride
= stride
;
4300 radv_draw(cmd_buffer
, &info
);
4303 struct radv_dispatch_info
{
4305 * Determine the layout of the grid (in block units) to be used.
4310 * A starting offset for the grid. If unaligned is set, the offset
4311 * must still be aligned.
4313 uint32_t offsets
[3];
4315 * Whether it's an unaligned compute dispatch.
4320 * Indirect compute parameters resource.
4322 struct radv_buffer
*indirect
;
4323 uint64_t indirect_offset
;
4327 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4328 const struct radv_dispatch_info
*info
)
4330 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4331 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4332 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4333 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4334 bool predicating
= cmd_buffer
->state
.predicating
;
4335 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4336 struct radv_userdata_info
*loc
;
4338 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4339 AC_UD_CS_GRID_SIZE
);
4341 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4343 if (info
->indirect
) {
4344 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4346 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4348 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4350 if (loc
->sgpr_idx
!= -1) {
4351 for (unsigned i
= 0; i
< 3; ++i
) {
4352 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4353 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4354 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4355 radeon_emit(cs
, (va
+ 4 * i
));
4356 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4357 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4358 + loc
->sgpr_idx
* 4) >> 2) + i
);
4363 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4364 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4365 PKT3_SHADER_TYPE_S(1));
4366 radeon_emit(cs
, va
);
4367 radeon_emit(cs
, va
>> 32);
4368 radeon_emit(cs
, dispatch_initiator
);
4370 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4371 PKT3_SHADER_TYPE_S(1));
4373 radeon_emit(cs
, va
);
4374 radeon_emit(cs
, va
>> 32);
4376 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4377 PKT3_SHADER_TYPE_S(1));
4379 radeon_emit(cs
, dispatch_initiator
);
4382 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4383 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4385 if (info
->unaligned
) {
4386 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4387 unsigned remainder
[3];
4389 /* If aligned, these should be an entire block size,
4392 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4393 align_u32_npot(blocks
[0], cs_block_size
[0]);
4394 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4395 align_u32_npot(blocks
[1], cs_block_size
[1]);
4396 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4397 align_u32_npot(blocks
[2], cs_block_size
[2]);
4399 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4400 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4401 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4403 for(unsigned i
= 0; i
< 3; ++i
) {
4404 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4405 offsets
[i
] /= cs_block_size
[i
];
4408 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4410 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4411 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4413 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4414 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4416 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4417 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4419 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4422 if (loc
->sgpr_idx
!= -1) {
4423 assert(loc
->num_sgprs
== 3);
4425 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4426 loc
->sgpr_idx
* 4, 3);
4427 radeon_emit(cs
, blocks
[0]);
4428 radeon_emit(cs
, blocks
[1]);
4429 radeon_emit(cs
, blocks
[2]);
4432 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4433 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4434 radeon_emit(cs
, offsets
[0]);
4435 radeon_emit(cs
, offsets
[1]);
4436 radeon_emit(cs
, offsets
[2]);
4438 /* The blocks in the packet are not counts but end values. */
4439 for (unsigned i
= 0; i
< 3; ++i
)
4440 blocks
[i
] += offsets
[i
];
4442 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4445 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4446 PKT3_SHADER_TYPE_S(1));
4447 radeon_emit(cs
, blocks
[0]);
4448 radeon_emit(cs
, blocks
[1]);
4449 radeon_emit(cs
, blocks
[2]);
4450 radeon_emit(cs
, dispatch_initiator
);
4453 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4457 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4459 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4460 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4464 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4465 const struct radv_dispatch_info
*info
)
4467 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4469 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4470 bool pipeline_is_dirty
= pipeline
&&
4471 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4473 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4474 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4475 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4476 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4477 /* If we have to wait for idle, set all states first, so that
4478 * all SET packets are processed in parallel with previous draw
4479 * calls. Then upload descriptors, set shader pointers, and
4480 * dispatch, and prefetch at the end. This ensures that the
4481 * time the CUs are idle is very short. (there are only SET_SH
4482 * packets between the wait and the draw)
4484 radv_emit_compute_pipeline(cmd_buffer
);
4485 si_emit_cache_flush(cmd_buffer
);
4486 /* <-- CUs are idle here --> */
4488 radv_upload_compute_shader_descriptors(cmd_buffer
);
4490 radv_emit_dispatch_packets(cmd_buffer
, info
);
4491 /* <-- CUs are busy here --> */
4493 /* Start prefetches after the dispatch has been started. Both
4494 * will run in parallel, but starting the dispatch first is
4497 if (has_prefetch
&& pipeline_is_dirty
) {
4498 radv_emit_shader_prefetch(cmd_buffer
,
4499 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4502 /* If we don't wait for idle, start prefetches first, then set
4503 * states, and dispatch at the end.
4505 si_emit_cache_flush(cmd_buffer
);
4507 if (has_prefetch
&& pipeline_is_dirty
) {
4508 radv_emit_shader_prefetch(cmd_buffer
,
4509 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4512 radv_upload_compute_shader_descriptors(cmd_buffer
);
4514 radv_emit_compute_pipeline(cmd_buffer
);
4515 radv_emit_dispatch_packets(cmd_buffer
, info
);
4518 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4521 void radv_CmdDispatchBase(
4522 VkCommandBuffer commandBuffer
,
4530 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4531 struct radv_dispatch_info info
= {};
4537 info
.offsets
[0] = base_x
;
4538 info
.offsets
[1] = base_y
;
4539 info
.offsets
[2] = base_z
;
4540 radv_dispatch(cmd_buffer
, &info
);
4543 void radv_CmdDispatch(
4544 VkCommandBuffer commandBuffer
,
4549 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4552 void radv_CmdDispatchIndirect(
4553 VkCommandBuffer commandBuffer
,
4555 VkDeviceSize offset
)
4557 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4558 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4559 struct radv_dispatch_info info
= {};
4561 info
.indirect
= buffer
;
4562 info
.indirect_offset
= offset
;
4564 radv_dispatch(cmd_buffer
, &info
);
4567 void radv_unaligned_dispatch(
4568 struct radv_cmd_buffer
*cmd_buffer
,
4573 struct radv_dispatch_info info
= {};
4580 radv_dispatch(cmd_buffer
, &info
);
4583 void radv_CmdEndRenderPass(
4584 VkCommandBuffer commandBuffer
)
4586 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4588 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4590 radv_cmd_buffer_end_subpass(cmd_buffer
);
4592 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4594 cmd_buffer
->state
.pass
= NULL
;
4595 cmd_buffer
->state
.subpass
= NULL
;
4596 cmd_buffer
->state
.attachments
= NULL
;
4597 cmd_buffer
->state
.framebuffer
= NULL
;
4600 void radv_CmdEndRenderPass2KHR(
4601 VkCommandBuffer commandBuffer
,
4602 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4604 radv_CmdEndRenderPass(commandBuffer
);
4608 * For HTILE we have the following interesting clear words:
4609 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4610 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4611 * 0xfffffff0: Clear depth to 1.0
4612 * 0x00000000: Clear depth to 0.0
4614 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4615 struct radv_image
*image
,
4616 const VkImageSubresourceRange
*range
,
4617 uint32_t clear_word
)
4619 assert(range
->baseMipLevel
== 0);
4620 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4621 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4622 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4623 VkClearDepthStencilValue value
= {};
4625 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4628 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
4630 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4632 if (vk_format_is_stencil(image
->vk_format
))
4633 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4635 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4637 if (radv_image_is_tc_compat_htile(image
)) {
4638 /* Initialize the TC-compat metada value to 0 because by
4639 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4640 * need have to conditionally update its value when performing
4641 * a fast depth clear.
4643 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4647 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4648 struct radv_image
*image
,
4649 VkImageLayout src_layout
,
4650 VkImageLayout dst_layout
,
4651 unsigned src_queue_mask
,
4652 unsigned dst_queue_mask
,
4653 const VkImageSubresourceRange
*range
)
4655 if (!radv_image_has_htile(image
))
4658 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4659 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4661 if (radv_layout_is_htile_compressed(image
, dst_layout
,
4666 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4667 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4668 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4669 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4670 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4671 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4672 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4673 VkImageSubresourceRange local_range
= *range
;
4674 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4675 local_range
.baseMipLevel
= 0;
4676 local_range
.levelCount
= 1;
4678 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4679 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4681 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4683 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4684 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4688 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4689 struct radv_image
*image
, uint32_t value
)
4691 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4693 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4694 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4696 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4698 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4701 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4702 struct radv_image
*image
)
4704 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4705 static const uint32_t fmask_clear_values
[4] = {
4711 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
4712 uint32_t value
= fmask_clear_values
[log2_samples
];
4714 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4715 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4717 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, value
);
4719 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4722 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4723 struct radv_image
*image
, uint32_t value
)
4725 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4727 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4728 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4730 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4732 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4733 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4737 * Initialize DCC/FMASK/CMASK metadata for a color image.
4739 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4740 struct radv_image
*image
,
4741 VkImageLayout src_layout
,
4742 VkImageLayout dst_layout
,
4743 unsigned src_queue_mask
,
4744 unsigned dst_queue_mask
)
4746 if (radv_image_has_cmask(image
)) {
4747 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4749 /* TODO: clarify this. */
4750 if (radv_image_has_fmask(image
)) {
4751 value
= 0xccccccccu
;
4754 radv_initialise_cmask(cmd_buffer
, image
, value
);
4757 if (radv_image_has_fmask(image
)) {
4758 radv_initialize_fmask(cmd_buffer
, image
);
4761 if (radv_image_has_dcc(image
)) {
4762 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4763 bool need_decompress_pass
= false;
4765 if (radv_layout_dcc_compressed(image
, dst_layout
,
4767 value
= 0x20202020u
;
4768 need_decompress_pass
= true;
4771 radv_initialize_dcc(cmd_buffer
, image
, value
);
4773 radv_update_fce_metadata(cmd_buffer
, image
,
4774 need_decompress_pass
);
4777 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4778 uint32_t color_values
[2] = {};
4779 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4784 * Handle color image transitions for DCC/FMASK/CMASK.
4786 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4787 struct radv_image
*image
,
4788 VkImageLayout src_layout
,
4789 VkImageLayout dst_layout
,
4790 unsigned src_queue_mask
,
4791 unsigned dst_queue_mask
,
4792 const VkImageSubresourceRange
*range
)
4794 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4795 radv_init_color_image_metadata(cmd_buffer
, image
,
4796 src_layout
, dst_layout
,
4797 src_queue_mask
, dst_queue_mask
);
4801 if (radv_image_has_dcc(image
)) {
4802 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4803 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4804 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4805 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4806 radv_decompress_dcc(cmd_buffer
, image
, range
);
4807 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4808 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4809 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4811 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4812 bool fce_eliminate
= false, fmask_expand
= false;
4814 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4815 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4816 fce_eliminate
= true;
4819 if (radv_image_has_fmask(image
)) {
4820 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
4821 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4822 /* A FMASK decompress is required before doing
4823 * a MSAA decompress using FMASK.
4825 fmask_expand
= true;
4829 if (fce_eliminate
|| fmask_expand
)
4830 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4833 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
4837 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4838 struct radv_image
*image
,
4839 VkImageLayout src_layout
,
4840 VkImageLayout dst_layout
,
4841 uint32_t src_family
,
4842 uint32_t dst_family
,
4843 const VkImageSubresourceRange
*range
)
4845 if (image
->exclusive
&& src_family
!= dst_family
) {
4846 /* This is an acquire or a release operation and there will be
4847 * a corresponding release/acquire. Do the transition in the
4848 * most flexible queue. */
4850 assert(src_family
== cmd_buffer
->queue_family_index
||
4851 dst_family
== cmd_buffer
->queue_family_index
);
4853 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4856 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4857 (src_family
== RADV_QUEUE_GENERAL
||
4858 dst_family
== RADV_QUEUE_GENERAL
))
4862 if (src_layout
== dst_layout
)
4865 unsigned src_queue_mask
=
4866 radv_image_queue_family_mask(image
, src_family
,
4867 cmd_buffer
->queue_family_index
);
4868 unsigned dst_queue_mask
=
4869 radv_image_queue_family_mask(image
, dst_family
,
4870 cmd_buffer
->queue_family_index
);
4872 if (vk_format_is_depth(image
->vk_format
)) {
4873 radv_handle_depth_image_transition(cmd_buffer
, image
,
4874 src_layout
, dst_layout
,
4875 src_queue_mask
, dst_queue_mask
,
4878 radv_handle_color_image_transition(cmd_buffer
, image
,
4879 src_layout
, dst_layout
,
4880 src_queue_mask
, dst_queue_mask
,
4885 struct radv_barrier_info
{
4886 uint32_t eventCount
;
4887 const VkEvent
*pEvents
;
4888 VkPipelineStageFlags srcStageMask
;
4889 VkPipelineStageFlags dstStageMask
;
4893 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4894 uint32_t memoryBarrierCount
,
4895 const VkMemoryBarrier
*pMemoryBarriers
,
4896 uint32_t bufferMemoryBarrierCount
,
4897 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4898 uint32_t imageMemoryBarrierCount
,
4899 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4900 const struct radv_barrier_info
*info
)
4902 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4903 enum radv_cmd_flush_bits src_flush_bits
= 0;
4904 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4906 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4907 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4908 uint64_t va
= radv_buffer_get_va(event
->bo
);
4910 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4912 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4914 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4915 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4918 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4919 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4921 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4925 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4926 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4928 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4932 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4933 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4935 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4937 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4941 /* The Vulkan spec 1.1.98 says:
4943 * "An execution dependency with only
4944 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4945 * will only prevent that stage from executing in subsequently
4946 * submitted commands. As this stage does not perform any actual
4947 * execution, this is not observable - in effect, it does not delay
4948 * processing of subsequent commands. Similarly an execution dependency
4949 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4950 * will effectively not wait for any prior commands to complete."
4952 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
4953 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4954 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4956 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4957 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4958 radv_handle_image_transition(cmd_buffer
, image
,
4959 pImageMemoryBarriers
[i
].oldLayout
,
4960 pImageMemoryBarriers
[i
].newLayout
,
4961 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4962 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4963 &pImageMemoryBarriers
[i
].subresourceRange
);
4966 /* Make sure CP DMA is idle because the driver might have performed a
4967 * DMA operation for copying or filling buffers/images.
4969 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4970 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4971 si_cp_dma_wait_for_idle(cmd_buffer
);
4973 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4976 void radv_CmdPipelineBarrier(
4977 VkCommandBuffer commandBuffer
,
4978 VkPipelineStageFlags srcStageMask
,
4979 VkPipelineStageFlags destStageMask
,
4981 uint32_t memoryBarrierCount
,
4982 const VkMemoryBarrier
* pMemoryBarriers
,
4983 uint32_t bufferMemoryBarrierCount
,
4984 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4985 uint32_t imageMemoryBarrierCount
,
4986 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4988 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4989 struct radv_barrier_info info
;
4991 info
.eventCount
= 0;
4992 info
.pEvents
= NULL
;
4993 info
.srcStageMask
= srcStageMask
;
4994 info
.dstStageMask
= destStageMask
;
4996 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4997 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4998 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5002 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5003 struct radv_event
*event
,
5004 VkPipelineStageFlags stageMask
,
5007 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5008 uint64_t va
= radv_buffer_get_va(event
->bo
);
5010 si_emit_cache_flush(cmd_buffer
);
5012 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5014 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5016 /* Flags that only require a top-of-pipe event. */
5017 VkPipelineStageFlags top_of_pipe_flags
=
5018 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5020 /* Flags that only require a post-index-fetch event. */
5021 VkPipelineStageFlags post_index_fetch_flags
=
5023 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5024 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5026 /* Make sure CP DMA is idle because the driver might have performed a
5027 * DMA operation for copying or filling buffers/images.
5029 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5030 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5031 si_cp_dma_wait_for_idle(cmd_buffer
);
5033 /* TODO: Emit EOS events for syncing PS/CS stages. */
5035 if (!(stageMask
& ~top_of_pipe_flags
)) {
5036 /* Just need to sync the PFP engine. */
5037 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5038 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5039 S_370_WR_CONFIRM(1) |
5040 S_370_ENGINE_SEL(V_370_PFP
));
5041 radeon_emit(cs
, va
);
5042 radeon_emit(cs
, va
>> 32);
5043 radeon_emit(cs
, value
);
5044 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5045 /* Sync ME because PFP reads index and indirect buffers. */
5046 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5047 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5048 S_370_WR_CONFIRM(1) |
5049 S_370_ENGINE_SEL(V_370_ME
));
5050 radeon_emit(cs
, va
);
5051 radeon_emit(cs
, va
>> 32);
5052 radeon_emit(cs
, value
);
5054 /* Otherwise, sync all prior GPU work using an EOP event. */
5055 si_cs_emit_write_event_eop(cs
,
5056 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5057 radv_cmd_buffer_uses_mec(cmd_buffer
),
5058 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5059 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5060 cmd_buffer
->gfx9_eop_bug_va
);
5063 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5066 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5068 VkPipelineStageFlags stageMask
)
5070 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5071 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5073 write_event(cmd_buffer
, event
, stageMask
, 1);
5076 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5078 VkPipelineStageFlags stageMask
)
5080 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5081 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5083 write_event(cmd_buffer
, event
, stageMask
, 0);
5086 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5087 uint32_t eventCount
,
5088 const VkEvent
* pEvents
,
5089 VkPipelineStageFlags srcStageMask
,
5090 VkPipelineStageFlags dstStageMask
,
5091 uint32_t memoryBarrierCount
,
5092 const VkMemoryBarrier
* pMemoryBarriers
,
5093 uint32_t bufferMemoryBarrierCount
,
5094 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5095 uint32_t imageMemoryBarrierCount
,
5096 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5098 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5099 struct radv_barrier_info info
;
5101 info
.eventCount
= eventCount
;
5102 info
.pEvents
= pEvents
;
5103 info
.srcStageMask
= 0;
5105 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5106 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5107 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5111 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5112 uint32_t deviceMask
)
5117 /* VK_EXT_conditional_rendering */
5118 void radv_CmdBeginConditionalRenderingEXT(
5119 VkCommandBuffer commandBuffer
,
5120 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5122 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5123 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5124 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5125 bool draw_visible
= true;
5126 uint64_t pred_value
= 0;
5127 uint64_t va
, new_va
;
5128 unsigned pred_offset
;
5130 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5132 /* By default, if the 32-bit value at offset in buffer memory is zero,
5133 * then the rendering commands are discarded, otherwise they are
5134 * executed as normal. If the inverted flag is set, all commands are
5135 * discarded if the value is non zero.
5137 if (pConditionalRenderingBegin
->flags
&
5138 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5139 draw_visible
= false;
5142 si_emit_cache_flush(cmd_buffer
);
5144 /* From the Vulkan spec 1.1.107:
5146 * "If the 32-bit value at offset in buffer memory is zero, then the
5147 * rendering commands are discarded, otherwise they are executed as
5148 * normal. If the value of the predicate in buffer memory changes while
5149 * conditional rendering is active, the rendering commands may be
5150 * discarded in an implementation-dependent way. Some implementations
5151 * may latch the value of the predicate upon beginning conditional
5152 * rendering while others may read it before every rendering command."
5154 * But, the AMD hardware treats the predicate as a 64-bit value which
5155 * means we need a workaround in the driver. Luckily, it's not required
5156 * to support if the value changes when predication is active.
5158 * The workaround is as follows:
5159 * 1) allocate a 64-value in the upload BO and initialize it to 0
5160 * 2) copy the 32-bit predicate value to the upload BO
5161 * 3) use the new allocated VA address for predication
5163 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5164 * in ME (+ sync PFP) instead of PFP.
5166 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5168 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5170 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5171 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5172 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5173 COPY_DATA_WR_CONFIRM
);
5174 radeon_emit(cs
, va
);
5175 radeon_emit(cs
, va
>> 32);
5176 radeon_emit(cs
, new_va
);
5177 radeon_emit(cs
, new_va
>> 32);
5179 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5182 /* Enable predication for this command buffer. */
5183 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5184 cmd_buffer
->state
.predicating
= true;
5186 /* Store conditional rendering user info. */
5187 cmd_buffer
->state
.predication_type
= draw_visible
;
5188 cmd_buffer
->state
.predication_va
= new_va
;
5191 void radv_CmdEndConditionalRenderingEXT(
5192 VkCommandBuffer commandBuffer
)
5194 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5196 /* Disable predication for this command buffer. */
5197 si_emit_set_predication_state(cmd_buffer
, false, 0);
5198 cmd_buffer
->state
.predicating
= false;
5200 /* Reset conditional rendering user info. */
5201 cmd_buffer
->state
.predication_type
= -1;
5202 cmd_buffer
->state
.predication_va
= 0;
5205 /* VK_EXT_transform_feedback */
5206 void radv_CmdBindTransformFeedbackBuffersEXT(
5207 VkCommandBuffer commandBuffer
,
5208 uint32_t firstBinding
,
5209 uint32_t bindingCount
,
5210 const VkBuffer
* pBuffers
,
5211 const VkDeviceSize
* pOffsets
,
5212 const VkDeviceSize
* pSizes
)
5214 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5215 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5216 uint8_t enabled_mask
= 0;
5218 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5219 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5220 uint32_t idx
= firstBinding
+ i
;
5222 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5223 sb
[idx
].offset
= pOffsets
[i
];
5224 sb
[idx
].size
= pSizes
[i
];
5226 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5227 sb
[idx
].buffer
->bo
);
5229 enabled_mask
|= 1 << idx
;
5232 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5234 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5238 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5240 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5241 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5243 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5245 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5246 S_028B94_RAST_STREAM(0) |
5247 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5248 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5249 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5250 radeon_emit(cs
, so
->hw_enabled_mask
&
5251 so
->enabled_stream_buffers_mask
);
5253 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5257 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5259 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5260 bool old_streamout_enabled
= so
->streamout_enabled
;
5261 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5263 so
->streamout_enabled
= enable
;
5265 so
->hw_enabled_mask
= so
->enabled_mask
|
5266 (so
->enabled_mask
<< 4) |
5267 (so
->enabled_mask
<< 8) |
5268 (so
->enabled_mask
<< 12);
5270 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5271 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5272 radv_emit_streamout_enable(cmd_buffer
);
5275 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5277 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5278 unsigned reg_strmout_cntl
;
5280 /* The register is at different places on different ASICs. */
5281 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5282 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5283 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5285 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5286 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5289 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5290 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5292 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5293 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5294 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5296 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5297 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5298 radeon_emit(cs
, 4); /* poll interval */
5301 void radv_CmdBeginTransformFeedbackEXT(
5302 VkCommandBuffer commandBuffer
,
5303 uint32_t firstCounterBuffer
,
5304 uint32_t counterBufferCount
,
5305 const VkBuffer
* pCounterBuffers
,
5306 const VkDeviceSize
* pCounterBufferOffsets
)
5308 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5309 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5310 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5311 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5314 radv_flush_vgt_streamout(cmd_buffer
);
5316 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5317 for_each_bit(i
, so
->enabled_mask
) {
5318 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5319 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5320 counter_buffer_idx
= -1;
5322 /* AMD GCN binds streamout buffers as shader resources.
5323 * VGT only counts primitives and tells the shader through
5326 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5327 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5328 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5330 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5332 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5333 /* The array of counter buffers is optional. */
5334 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5335 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5337 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5340 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5341 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5342 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5343 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5344 radeon_emit(cs
, 0); /* unused */
5345 radeon_emit(cs
, 0); /* unused */
5346 radeon_emit(cs
, va
); /* src address lo */
5347 radeon_emit(cs
, va
>> 32); /* src address hi */
5349 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5351 /* Start from the beginning. */
5352 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5353 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5354 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5355 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5356 radeon_emit(cs
, 0); /* unused */
5357 radeon_emit(cs
, 0); /* unused */
5358 radeon_emit(cs
, 0); /* unused */
5359 radeon_emit(cs
, 0); /* unused */
5363 radv_set_streamout_enable(cmd_buffer
, true);
5366 void radv_CmdEndTransformFeedbackEXT(
5367 VkCommandBuffer commandBuffer
,
5368 uint32_t firstCounterBuffer
,
5369 uint32_t counterBufferCount
,
5370 const VkBuffer
* pCounterBuffers
,
5371 const VkDeviceSize
* pCounterBufferOffsets
)
5373 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5374 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5375 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5378 radv_flush_vgt_streamout(cmd_buffer
);
5380 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5381 for_each_bit(i
, so
->enabled_mask
) {
5382 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5383 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5384 counter_buffer_idx
= -1;
5386 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5387 /* The array of counters buffer is optional. */
5388 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5389 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5391 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5393 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5394 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5395 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5396 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5397 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5398 radeon_emit(cs
, va
); /* dst address lo */
5399 radeon_emit(cs
, va
>> 32); /* dst address hi */
5400 radeon_emit(cs
, 0); /* unused */
5401 radeon_emit(cs
, 0); /* unused */
5403 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5406 /* Deactivate transform feedback by zeroing the buffer size.
5407 * The counters (primitives generated, primitives emitted) may
5408 * be enabled even if there is not buffer bound. This ensures
5409 * that the primitives-emitted query won't increment.
5411 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5413 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5416 radv_set_streamout_enable(cmd_buffer
, false);
5419 void radv_CmdDrawIndirectByteCountEXT(
5420 VkCommandBuffer commandBuffer
,
5421 uint32_t instanceCount
,
5422 uint32_t firstInstance
,
5423 VkBuffer _counterBuffer
,
5424 VkDeviceSize counterBufferOffset
,
5425 uint32_t counterOffset
,
5426 uint32_t vertexStride
)
5428 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5429 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5430 struct radv_draw_info info
= {};
5432 info
.instance_count
= instanceCount
;
5433 info
.first_instance
= firstInstance
;
5434 info
.strmout_buffer
= counterBuffer
;
5435 info
.strmout_buffer_offset
= counterBufferOffset
;
5436 info
.stride
= vertexStride
;
5438 radv_draw(cmd_buffer
, &info
);