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radv: add radv_vertex_elements_info data structure
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_result = VK_SUCCESS;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
345 va += 4;
346
347 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
348
349 ++cmd_buffer->state.trace_id;
350 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
351 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
352 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
353 S_370_WR_CONFIRM(1) |
354 S_370_ENGINE_SEL(V_370_ME));
355 radeon_emit(cs, va);
356 radeon_emit(cs, va >> 32);
357 radeon_emit(cs, cmd_buffer->state.trace_id);
358 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
359 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
360 }
361
362 static void
363 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
367 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
368 8);
369 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
370 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
371
372 if (cmd_buffer->device->physical_device->has_rbplus) {
373
374 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
375 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
376
377 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
378 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
379 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
380 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
381 }
382 }
383
384 static void
385 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
386 struct radv_pipeline *pipeline)
387 {
388 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
389 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
390 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
391
392 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
393 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
394 }
395
396 /* 12.4 fixed-point */
397 static unsigned radv_pack_float_12p4(float x)
398 {
399 return x <= 0 ? 0 :
400 x >= 4096 ? 0xffff : x * 16;
401 }
402
403 uint32_t
404 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
405 {
406 switch (stage) {
407 case MESA_SHADER_FRAGMENT:
408 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
409 case MESA_SHADER_VERTEX:
410 if (has_tess)
411 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
412 else
413 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
414 case MESA_SHADER_GEOMETRY:
415 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
416 case MESA_SHADER_COMPUTE:
417 return R_00B900_COMPUTE_USER_DATA_0;
418 case MESA_SHADER_TESS_CTRL:
419 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
420 case MESA_SHADER_TESS_EVAL:
421 if (has_gs)
422 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
423 else
424 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
425 default:
426 unreachable("unknown shader");
427 }
428 }
429
430 struct ac_userdata_info *
431 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
432 gl_shader_stage stage,
433 int idx)
434 {
435 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
436 }
437
438 static void
439 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
440 struct radv_pipeline *pipeline,
441 gl_shader_stage stage,
442 int idx, uint64_t va)
443 {
444 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
445 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
446 if (loc->sgpr_idx == -1)
447 return;
448 assert(loc->num_sgprs == 2);
449 assert(!loc->indirect);
450 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
451 radeon_emit(cmd_buffer->cs, va);
452 radeon_emit(cmd_buffer->cs, va >> 32);
453 }
454
455 static void
456 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
457 struct radv_pipeline *pipeline)
458 {
459 int num_samples = pipeline->graphics.ms.num_samples;
460 struct radv_multisample_state *ms = &pipeline->graphics.ms;
461 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
462
463 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
464 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
465 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
466
467 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
468 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
469
470 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
471 return;
472
473 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
474 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
475 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
476
477 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
478
479 /* GFX9: Flush DFSM when the AA mode changes. */
480 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
481 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
482 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
483 }
484 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
485 uint32_t offset;
486 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
487 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
488 if (loc->sgpr_idx == -1)
489 return;
490 assert(loc->num_sgprs == 1);
491 assert(!loc->indirect);
492 switch (num_samples) {
493 default:
494 offset = 0;
495 break;
496 case 2:
497 offset = 1;
498 break;
499 case 4:
500 offset = 3;
501 break;
502 case 8:
503 offset = 7;
504 break;
505 case 16:
506 offset = 15;
507 break;
508 }
509
510 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
511 cmd_buffer->sample_positions_needed = true;
512 }
513 }
514
515 static void
516 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline)
518 {
519 struct radv_raster_state *raster = &pipeline->graphics.raster;
520
521 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
522 raster->pa_cl_clip_cntl);
523
524 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
525 raster->spi_interp_control);
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
528 unsigned tmp = (unsigned)(1.0 * 8.0);
529 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
530 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
531 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
532
533 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
534 raster->pa_su_vtx_cntl);
535
536 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
537 raster->pa_su_sc_mode_cntl);
538 }
539
540 static inline void
541 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
542 unsigned size)
543 {
544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
545 si_cp_dma_prefetch(cmd_buffer, va, size);
546 }
547
548 static void
549 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
550 struct radv_pipeline *pipeline,
551 struct radv_shader_variant *shader,
552 struct ac_vs_output_info *outinfo)
553 {
554 struct radeon_winsys *ws = cmd_buffer->device->ws;
555 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
556 unsigned export_count;
557
558 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
559 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
560
561 export_count = MAX2(1, outinfo->param_exports);
562 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
563 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
564
565 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
566 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
567 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE) |
570 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
571 V_02870C_SPI_SHADER_4COMP :
572 V_02870C_SPI_SHADER_NONE) |
573 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
574 V_02870C_SPI_SHADER_4COMP :
575 V_02870C_SPI_SHADER_NONE));
576
577
578 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
579 radeon_emit(cmd_buffer->cs, va >> 8);
580 radeon_emit(cmd_buffer->cs, va >> 40);
581 radeon_emit(cmd_buffer->cs, shader->rsrc1);
582 radeon_emit(cmd_buffer->cs, shader->rsrc2);
583
584 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
585 S_028818_VTX_W0_FMT(1) |
586 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
587 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
588 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
589
590
591 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
592 pipeline->graphics.pa_cl_vs_out_cntl);
593
594 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
595 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
596 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
597 }
598
599 static void
600 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
601 struct radv_shader_variant *shader,
602 struct ac_es_output_info *outinfo)
603 {
604 struct radeon_winsys *ws = cmd_buffer->device->ws;
605 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
606
607 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
608 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
609
610 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
611 outinfo->esgs_itemsize / 4);
612 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
613 radeon_emit(cmd_buffer->cs, va >> 8);
614 radeon_emit(cmd_buffer->cs, va >> 40);
615 radeon_emit(cmd_buffer->cs, shader->rsrc1);
616 radeon_emit(cmd_buffer->cs, shader->rsrc2);
617 }
618
619 static void
620 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
621 struct radv_shader_variant *shader)
622 {
623 struct radeon_winsys *ws = cmd_buffer->device->ws;
624 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
625 uint32_t rsrc2 = shader->rsrc2;
626
627 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
628 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
629
630 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
631 radeon_emit(cmd_buffer->cs, va >> 8);
632 radeon_emit(cmd_buffer->cs, va >> 40);
633
634 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
635 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
636 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
637 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
638
639 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
640 radeon_emit(cmd_buffer->cs, shader->rsrc1);
641 radeon_emit(cmd_buffer->cs, rsrc2);
642 }
643
644 static void
645 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
646 struct radv_shader_variant *shader)
647 {
648 struct radeon_winsys *ws = cmd_buffer->device->ws;
649 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
650
651 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
652 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
653
654 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
655 radeon_emit(cmd_buffer->cs, va >> 8);
656 radeon_emit(cmd_buffer->cs, va >> 40);
657 radeon_emit(cmd_buffer->cs, shader->rsrc1);
658 radeon_emit(cmd_buffer->cs, shader->rsrc2);
659 }
660
661 static void
662 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
663 struct radv_pipeline *pipeline)
664 {
665 struct radv_shader_variant *vs;
666
667 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
668
669 vs = pipeline->shaders[MESA_SHADER_VERTEX];
670
671 if (vs->info.vs.as_ls)
672 radv_emit_hw_ls(cmd_buffer, vs);
673 else if (vs->info.vs.as_es)
674 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
675 else
676 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
677
678 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
679 }
680
681
682 static void
683 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_pipeline *pipeline)
685 {
686 if (!radv_pipeline_has_tess(pipeline))
687 return;
688
689 struct radv_shader_variant *tes, *tcs;
690
691 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
692 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
693
694 if (tes->info.tes.as_es)
695 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
696 else
697 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
698
699 radv_emit_hw_hs(cmd_buffer, tcs);
700
701 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
702 pipeline->graphics.tess.tf_param);
703
704 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
705 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
706 pipeline->graphics.tess.ls_hs_config);
707 else
708 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
709 pipeline->graphics.tess.ls_hs_config);
710
711 struct ac_userdata_info *loc;
712
713 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
714 if (loc->sgpr_idx != -1) {
715 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
716 assert(loc->num_sgprs == 4);
717 assert(!loc->indirect);
718 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
719 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
720 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
721 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
722 pipeline->graphics.tess.num_tcs_input_cp << 26);
723 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
724 }
725
726 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
727 if (loc->sgpr_idx != -1) {
728 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
729 assert(loc->num_sgprs == 1);
730 assert(!loc->indirect);
731
732 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
733 pipeline->graphics.tess.offchip_layout);
734 }
735
736 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
737 if (loc->sgpr_idx != -1) {
738 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
739 assert(loc->num_sgprs == 1);
740 assert(!loc->indirect);
741
742 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
743 pipeline->graphics.tess.tcs_in_layout);
744 }
745 }
746
747 static void
748 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
749 struct radv_pipeline *pipeline)
750 {
751 struct radeon_winsys *ws = cmd_buffer->device->ws;
752 struct radv_shader_variant *gs;
753 uint64_t va;
754
755 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
756
757 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
758 if (!gs)
759 return;
760
761 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
762
763 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
764 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
765 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
766 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
767
768 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
769
770 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
771
772 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
773 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
774 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
775 radeon_emit(cmd_buffer->cs, 0);
776 radeon_emit(cmd_buffer->cs, 0);
777 radeon_emit(cmd_buffer->cs, 0);
778
779 uint32_t gs_num_invocations = gs->info.gs.invocations;
780 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
781 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
782 S_028B90_ENABLE(gs_num_invocations > 0));
783
784 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
785 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
786 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
787
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791 radeon_emit(cmd_buffer->cs, gs->rsrc1);
792 radeon_emit(cmd_buffer->cs, gs->rsrc2);
793
794 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
795
796 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
797 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
798 if (loc->sgpr_idx != -1) {
799 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
800 uint32_t num_entries = 64;
801 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
802
803 if (is_vi)
804 num_entries *= stride;
805
806 stride = S_008F04_STRIDE(stride);
807 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
808 radeon_emit(cmd_buffer->cs, stride);
809 radeon_emit(cmd_buffer->cs, num_entries);
810 }
811 }
812
813 static void
814 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
815 struct radv_pipeline *pipeline)
816 {
817 struct radeon_winsys *ws = cmd_buffer->device->ws;
818 struct radv_shader_variant *ps;
819 uint64_t va;
820 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
821 struct radv_blend_state *blend = &pipeline->graphics.blend;
822 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
823
824 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
825 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
826 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
827 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
828
829 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
830 radeon_emit(cmd_buffer->cs, va >> 8);
831 radeon_emit(cmd_buffer->cs, va >> 40);
832 radeon_emit(cmd_buffer->cs, ps->rsrc1);
833 radeon_emit(cmd_buffer->cs, ps->rsrc2);
834
835 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
836 pipeline->graphics.db_shader_control);
837
838 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
839 ps->config.spi_ps_input_ena);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
842 ps->config.spi_ps_input_addr);
843
844 if (ps->info.info.ps.force_persample)
845 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
848 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
849
850 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
851
852 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
853 pipeline->graphics.shader_z_format);
854
855 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
856
857 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
858 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
859
860 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
861 /* optimise this? */
862 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
863 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
864 }
865
866 if (pipeline->graphics.ps_input_cntl_num) {
867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
868 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
869 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
870 }
871 }
872 }
873
874 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
875 struct radv_pipeline *pipeline)
876 {
877 uint32_t vtx_reuse_depth = 30;
878 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
879 return;
880
881 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
882 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
883 vtx_reuse_depth = 14;
884 }
885 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
886 vtx_reuse_depth);
887 }
888
889 static void
890 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
891 struct radv_pipeline *pipeline)
892 {
893 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
894 return;
895
896 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
897 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
898 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
899 radv_update_multisample_state(cmd_buffer, pipeline);
900 radv_emit_vertex_shader(cmd_buffer, pipeline);
901 radv_emit_tess_shaders(cmd_buffer, pipeline);
902 radv_emit_geometry_shader(cmd_buffer, pipeline);
903 radv_emit_fragment_shader(cmd_buffer, pipeline);
904 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
905
906 cmd_buffer->scratch_size_needed =
907 MAX2(cmd_buffer->scratch_size_needed,
908 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
909
910 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
911 S_0286E8_WAVES(pipeline->max_waves) |
912 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
913
914 if (!cmd_buffer->state.emitted_pipeline ||
915 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
916 pipeline->graphics.can_use_guardband)
917 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
922 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
923 } else {
924 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
925 }
926 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
927
928 cmd_buffer->state.emitted_pipeline = pipeline;
929 }
930
931 static void
932 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
933 {
934 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
935 cmd_buffer->state.dynamic.viewport.viewports);
936 }
937
938 static void
939 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
940 {
941 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
942 si_write_scissors(cmd_buffer->cs, 0, count,
943 cmd_buffer->state.dynamic.scissor.scissors,
944 cmd_buffer->state.dynamic.viewport.viewports,
945 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
946 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
947 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
948 }
949
950 static void
951 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
952 int index,
953 struct radv_color_buffer_info *cb)
954 {
955 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
956
957 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
958 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
965 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
966 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
967 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
968 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
969 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
970
971 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
972 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
973 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
974
975 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
976 cb->gfx9_epitch);
977 } else {
978 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
980 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
985 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
986 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
987 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
988 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
989 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
990
991 if (is_vi) { /* DCC BASE */
992 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
993 }
994 }
995 }
996
997 static void
998 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
999 struct radv_ds_buffer_info *ds,
1000 struct radv_image *image,
1001 VkImageLayout layout)
1002 {
1003 uint32_t db_z_info = ds->db_z_info;
1004 uint32_t db_stencil_info = ds->db_stencil_info;
1005
1006 if (!radv_layout_has_htile(image, layout,
1007 radv_image_queue_family_mask(image,
1008 cmd_buffer->queue_family_index,
1009 cmd_buffer->queue_family_index))) {
1010 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1011 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1012 }
1013
1014 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1015 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1016
1017
1018 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1019 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1020 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1021 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1022 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1025 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1026 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1027 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1028 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1029 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1030 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1031 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1032 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1033 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1034 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1035
1036 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1037 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1038 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1039 } else {
1040 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1041
1042 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1043 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1044 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1045 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1046 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1047 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1048 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1049 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1050 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1051 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1052
1053 }
1054
1055 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1056 ds->pa_su_poly_offset_db_fmt_cntl);
1057 }
1058
1059 void
1060 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1061 struct radv_image *image,
1062 VkClearDepthStencilValue ds_clear_value,
1063 VkImageAspectFlags aspects)
1064 {
1065 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1066 va += image->offset + image->clear_value_offset;
1067 unsigned reg_offset = 0, reg_count = 0;
1068
1069 if (!image->surface.htile_size || !aspects)
1070 return;
1071
1072 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1073 ++reg_count;
1074 } else {
1075 ++reg_offset;
1076 va += 4;
1077 }
1078 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1079 ++reg_count;
1080
1081 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1082
1083 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1084 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1085 S_370_WR_CONFIRM(1) |
1086 S_370_ENGINE_SEL(V_370_PFP));
1087 radeon_emit(cmd_buffer->cs, va);
1088 radeon_emit(cmd_buffer->cs, va >> 32);
1089 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1090 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1091 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1092 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1093
1094 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1095 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1096 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1097 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1098 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1099 }
1100
1101 static void
1102 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1103 struct radv_image *image)
1104 {
1105 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1106 va += image->offset + image->clear_value_offset;
1107
1108 if (!image->surface.htile_size)
1109 return;
1110
1111 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1112
1113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1114 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1115 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1116 COPY_DATA_COUNT_SEL);
1117 radeon_emit(cmd_buffer->cs, va);
1118 radeon_emit(cmd_buffer->cs, va >> 32);
1119 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1120 radeon_emit(cmd_buffer->cs, 0);
1121
1122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1123 radeon_emit(cmd_buffer->cs, 0);
1124 }
1125
1126 /*
1127 *with DCC some colors don't require CMASK elimiation before being
1128 * used as a texture. This sets a predicate value to determine if the
1129 * cmask eliminate is required.
1130 */
1131 void
1132 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_image *image,
1134 bool value)
1135 {
1136 uint64_t pred_val = value;
1137 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1138 va += image->offset + image->dcc_pred_offset;
1139
1140 if (!image->surface.dcc_size)
1141 return;
1142
1143 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1144
1145 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1146 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1147 S_370_WR_CONFIRM(1) |
1148 S_370_ENGINE_SEL(V_370_PFP));
1149 radeon_emit(cmd_buffer->cs, va);
1150 radeon_emit(cmd_buffer->cs, va >> 32);
1151 radeon_emit(cmd_buffer->cs, pred_val);
1152 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1153 }
1154
1155 void
1156 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_image *image,
1158 int idx,
1159 uint32_t color_values[2])
1160 {
1161 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1162 va += image->offset + image->clear_value_offset;
1163
1164 if (!image->cmask.size && !image->surface.dcc_size)
1165 return;
1166
1167 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1170 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1171 S_370_WR_CONFIRM(1) |
1172 S_370_ENGINE_SEL(V_370_PFP));
1173 radeon_emit(cmd_buffer->cs, va);
1174 radeon_emit(cmd_buffer->cs, va >> 32);
1175 radeon_emit(cmd_buffer->cs, color_values[0]);
1176 radeon_emit(cmd_buffer->cs, color_values[1]);
1177
1178 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1179 radeon_emit(cmd_buffer->cs, color_values[0]);
1180 radeon_emit(cmd_buffer->cs, color_values[1]);
1181 }
1182
1183 static void
1184 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1185 struct radv_image *image,
1186 int idx)
1187 {
1188 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1189 va += image->offset + image->clear_value_offset;
1190
1191 if (!image->cmask.size && !image->surface.dcc_size)
1192 return;
1193
1194 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1195 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1196
1197 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1198 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1199 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1200 COPY_DATA_COUNT_SEL);
1201 radeon_emit(cmd_buffer->cs, va);
1202 radeon_emit(cmd_buffer->cs, va >> 32);
1203 radeon_emit(cmd_buffer->cs, reg >> 2);
1204 radeon_emit(cmd_buffer->cs, 0);
1205
1206 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1207 radeon_emit(cmd_buffer->cs, 0);
1208 }
1209
1210 void
1211 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1212 {
1213 int i;
1214 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1215 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1216
1217 /* this may happen for inherited secondary recording */
1218 if (!framebuffer)
1219 return;
1220
1221 for (i = 0; i < 8; ++i) {
1222 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1223 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1224 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1225 continue;
1226 }
1227
1228 int idx = subpass->color_attachments[i].attachment;
1229 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1230
1231 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1232
1233 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1234 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1235
1236 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1237 }
1238
1239 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1240 int idx = subpass->depth_stencil_attachment.attachment;
1241 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1242 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1243 struct radv_image *image = att->attachment->image;
1244 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1245 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1246 cmd_buffer->queue_family_index,
1247 cmd_buffer->queue_family_index);
1248 /* We currently don't support writing decompressed HTILE */
1249 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1250 radv_layout_is_htile_compressed(image, layout, queue_mask));
1251
1252 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1253
1254 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1255 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1256 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1257 }
1258 radv_load_depth_clear_regs(cmd_buffer, image);
1259 } else {
1260 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1262 else
1263 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1264
1265 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1266 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1267 }
1268 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1269 S_028208_BR_X(framebuffer->width) |
1270 S_028208_BR_Y(framebuffer->height));
1271
1272 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1273 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1274 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1275 }
1276 }
1277
1278 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 uint32_t db_count_control;
1281
1282 if(!cmd_buffer->state.active_occlusion_queries) {
1283 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1284 db_count_control = 0;
1285 } else {
1286 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1287 }
1288 } else {
1289 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1290 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1291 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1292 S_028004_ZPASS_ENABLE(1) |
1293 S_028004_SLICE_EVEN_ENABLE(1) |
1294 S_028004_SLICE_ODD_ENABLE(1);
1295 } else {
1296 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1297 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1298 }
1299 }
1300
1301 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1302 }
1303
1304 static void
1305 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1306 {
1307 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1308
1309 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1310 return;
1311
1312 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1313 radv_emit_viewport(cmd_buffer);
1314
1315 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1316 radv_emit_scissor(cmd_buffer);
1317
1318 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1319 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1320 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1321 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1322 }
1323
1324 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1326 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1327 }
1328
1329 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1330 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1331 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1332 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1333 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1334 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1335 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1336 S_028430_STENCILOPVAL(1));
1337 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1338 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1339 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1340 S_028434_STENCILOPVAL_BF(1));
1341 }
1342
1343 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1344 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1345 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1346 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1347 }
1348
1349 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1350 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1351 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1352 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1353 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1354
1355 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1356 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1357 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1358 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1359 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1360 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1361 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1362 }
1363 }
1364
1365 cmd_buffer->state.dirty = 0;
1366 }
1367
1368 static void
1369 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1370 struct radv_pipeline *pipeline,
1371 int idx,
1372 uint64_t va,
1373 gl_shader_stage stage)
1374 {
1375 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1376 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1377
1378 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1379 return;
1380
1381 assert(!desc_set_loc->indirect);
1382 assert(desc_set_loc->num_sgprs == 2);
1383 radeon_set_sh_reg_seq(cmd_buffer->cs,
1384 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1385 radeon_emit(cmd_buffer->cs, va);
1386 radeon_emit(cmd_buffer->cs, va >> 32);
1387 }
1388
1389 static void
1390 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1391 VkShaderStageFlags stages,
1392 struct radv_descriptor_set *set,
1393 unsigned idx)
1394 {
1395 if (cmd_buffer->state.pipeline) {
1396 radv_foreach_stage(stage, stages) {
1397 if (cmd_buffer->state.pipeline->shaders[stage])
1398 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1399 idx, set->va,
1400 stage);
1401 }
1402 }
1403
1404 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1405 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1406 idx, set->va,
1407 MESA_SHADER_COMPUTE);
1408 }
1409
1410 static void
1411 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1412 {
1413 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1414 uint32_t *ptr = NULL;
1415 unsigned bo_offset;
1416
1417 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1418 &bo_offset,
1419 (void**) &ptr))
1420 return;
1421
1422 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1423 set->va += bo_offset;
1424
1425 memcpy(ptr, set->mapped_ptr, set->size);
1426 }
1427
1428 static void
1429 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1430 {
1431 uint32_t size = MAX_SETS * 2 * 4;
1432 uint32_t offset;
1433 void *ptr;
1434
1435 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1436 256, &offset, &ptr))
1437 return;
1438
1439 for (unsigned i = 0; i < MAX_SETS; i++) {
1440 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1441 uint64_t set_va = 0;
1442 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1443 if (set)
1444 set_va = set->va;
1445 uptr[0] = set_va & 0xffffffff;
1446 uptr[1] = set_va >> 32;
1447 }
1448
1449 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1450 va += offset;
1451
1452 if (cmd_buffer->state.pipeline) {
1453 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1454 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1455 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1456
1457 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1458 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1459 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1460
1461 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1462 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1463 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1464
1465 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1466 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1467 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1468
1469 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1470 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1471 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1472 }
1473
1474 if (cmd_buffer->state.compute_pipeline)
1475 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1476 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1477 }
1478
1479 static void
1480 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1481 VkShaderStageFlags stages)
1482 {
1483 unsigned i;
1484
1485 if (!cmd_buffer->state.descriptors_dirty)
1486 return;
1487
1488 if (cmd_buffer->state.push_descriptors_dirty)
1489 radv_flush_push_descriptors(cmd_buffer);
1490
1491 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1492 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1493 radv_flush_indirect_descriptor_sets(cmd_buffer);
1494 }
1495
1496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1497 cmd_buffer->cs,
1498 MAX_SETS * MESA_SHADER_STAGES * 4);
1499
1500 for (i = 0; i < MAX_SETS; i++) {
1501 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1502 continue;
1503 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1504 if (!set)
1505 continue;
1506
1507 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1508 }
1509 cmd_buffer->state.descriptors_dirty = 0;
1510 cmd_buffer->state.push_descriptors_dirty = false;
1511 assert(cmd_buffer->cs->cdw <= cdw_max);
1512 }
1513
1514 static void
1515 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_pipeline *pipeline,
1517 VkShaderStageFlags stages)
1518 {
1519 struct radv_pipeline_layout *layout = pipeline->layout;
1520 unsigned offset;
1521 void *ptr;
1522 uint64_t va;
1523
1524 stages &= cmd_buffer->push_constant_stages;
1525 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1526 return;
1527
1528 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1529 16 * layout->dynamic_offset_count,
1530 256, &offset, &ptr))
1531 return;
1532
1533 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1534 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1535 16 * layout->dynamic_offset_count);
1536
1537 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1538 va += offset;
1539
1540 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1541 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1542
1543 radv_foreach_stage(stage, stages) {
1544 if (pipeline->shaders[stage]) {
1545 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1546 AC_UD_PUSH_CONSTANTS, va);
1547 }
1548 }
1549
1550 cmd_buffer->push_constant_stages &= ~stages;
1551 assert(cmd_buffer->cs->cdw <= cdw_max);
1552 }
1553
1554 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1555 bool indexed_draw)
1556 {
1557 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1558
1559 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1560 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1561 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1562 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1563 primitive_reset_en);
1564 } else {
1565 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1566 primitive_reset_en);
1567 }
1568 }
1569
1570 if (primitive_reset_en) {
1571 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1572
1573 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1574 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1575 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1576 primitive_reset_index);
1577 }
1578 }
1579 }
1580
1581 static void
1582 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1583 {
1584 struct radv_device *device = cmd_buffer->device;
1585
1586 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1587 cmd_buffer->state.pipeline->vertex_elements.count &&
1588 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1589 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1590 unsigned vb_offset;
1591 void *vb_ptr;
1592 uint32_t i = 0;
1593 uint32_t count = velems->count;
1594 uint64_t va;
1595
1596 /* allocate some descriptor state for vertex buffers */
1597 radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1598 &vb_offset, &vb_ptr);
1599
1600 for (i = 0; i < count; i++) {
1601 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1602 uint32_t offset;
1603 int vb = velems->binding[i];
1604 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1605 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1606
1607 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1608 va = device->ws->buffer_get_va(buffer->bo);
1609
1610 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1611 va += offset + buffer->offset;
1612 desc[0] = va;
1613 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1614 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1615 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1616 else
1617 desc[2] = buffer->size - offset;
1618 desc[3] = velems->rsrc_word3[i];
1619 }
1620
1621 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1622 va += vb_offset;
1623
1624 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1625 AC_UD_VS_VERTEX_BUFFERS, va);
1626 }
1627 cmd_buffer->state.vb_dirty = false;
1628 }
1629
1630 static void
1631 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1632 bool indexed_draw, bool instanced_draw,
1633 bool indirect_draw,
1634 uint32_t draw_vertex_count)
1635 {
1636 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1637 uint32_t ia_multi_vgt_param;
1638
1639 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1640 cmd_buffer->cs, 4096);
1641
1642 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1643
1644 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1645 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1646
1647 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1648 radv_emit_framebuffer_state(cmd_buffer);
1649
1650 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1651 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1652 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1653 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1654 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1655 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1656 else
1657 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1658 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1659 }
1660
1661 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1662
1663 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1664
1665 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1666 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1667 VK_SHADER_STAGE_ALL_GRAPHICS);
1668
1669 assert(cmd_buffer->cs->cdw <= cdw_max);
1670
1671 si_emit_cache_flush(cmd_buffer);
1672 }
1673
1674 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1675 VkPipelineStageFlags src_stage_mask)
1676 {
1677 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1678 VK_PIPELINE_STAGE_TRANSFER_BIT |
1679 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1680 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1681 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1682 }
1683
1684 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1685 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1686 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1687 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1688 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1689 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1690 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1691 VK_PIPELINE_STAGE_TRANSFER_BIT |
1692 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1693 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1694 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1695 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1696 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1697 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1698 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1699 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1700 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1701 }
1702 }
1703
1704 static enum radv_cmd_flush_bits
1705 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1706 VkAccessFlags src_flags)
1707 {
1708 enum radv_cmd_flush_bits flush_bits = 0;
1709 uint32_t b;
1710 for_each_bit(b, src_flags) {
1711 switch ((VkAccessFlagBits)(1 << b)) {
1712 case VK_ACCESS_SHADER_WRITE_BIT:
1713 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1714 break;
1715 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1716 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1717 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1718 break;
1719 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1720 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1721 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1722 break;
1723 case VK_ACCESS_TRANSFER_WRITE_BIT:
1724 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1725 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1726 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1727 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1728 RADV_CMD_FLAG_INV_GLOBAL_L2;
1729 break;
1730 default:
1731 break;
1732 }
1733 }
1734 return flush_bits;
1735 }
1736
1737 static enum radv_cmd_flush_bits
1738 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1739 VkAccessFlags dst_flags,
1740 struct radv_image *image)
1741 {
1742 enum radv_cmd_flush_bits flush_bits = 0;
1743 uint32_t b;
1744 for_each_bit(b, dst_flags) {
1745 switch ((VkAccessFlagBits)(1 << b)) {
1746 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1747 case VK_ACCESS_INDEX_READ_BIT:
1748 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1749 break;
1750 case VK_ACCESS_UNIFORM_READ_BIT:
1751 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1752 break;
1753 case VK_ACCESS_SHADER_READ_BIT:
1754 case VK_ACCESS_TRANSFER_READ_BIT:
1755 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1756 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1757 RADV_CMD_FLAG_INV_GLOBAL_L2;
1758 break;
1759 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1760 /* TODO: change to image && when the image gets passed
1761 * through from the subpass. */
1762 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1763 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1764 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1765 break;
1766 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1767 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1768 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1769 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1770 break;
1771 default:
1772 break;
1773 }
1774 }
1775 return flush_bits;
1776 }
1777
1778 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1779 {
1780 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1781 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1782 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1783 NULL);
1784 }
1785
1786 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1787 VkAttachmentReference att)
1788 {
1789 unsigned idx = att.attachment;
1790 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1791 VkImageSubresourceRange range;
1792 range.aspectMask = 0;
1793 range.baseMipLevel = view->base_mip;
1794 range.levelCount = 1;
1795 range.baseArrayLayer = view->base_layer;
1796 range.layerCount = cmd_buffer->state.framebuffer->layers;
1797
1798 radv_handle_image_transition(cmd_buffer,
1799 view->image,
1800 cmd_buffer->state.attachments[idx].current_layout,
1801 att.layout, 0, 0, &range,
1802 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1803
1804 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1805
1806
1807 }
1808
1809 void
1810 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1811 const struct radv_subpass *subpass, bool transitions)
1812 {
1813 if (transitions) {
1814 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1815
1816 for (unsigned i = 0; i < subpass->color_count; ++i) {
1817 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1818 radv_handle_subpass_image_transition(cmd_buffer,
1819 subpass->color_attachments[i]);
1820 }
1821
1822 for (unsigned i = 0; i < subpass->input_count; ++i) {
1823 radv_handle_subpass_image_transition(cmd_buffer,
1824 subpass->input_attachments[i]);
1825 }
1826
1827 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1828 radv_handle_subpass_image_transition(cmd_buffer,
1829 subpass->depth_stencil_attachment);
1830 }
1831 }
1832
1833 cmd_buffer->state.subpass = subpass;
1834
1835 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1836 }
1837
1838 static VkResult
1839 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1840 struct radv_render_pass *pass,
1841 const VkRenderPassBeginInfo *info)
1842 {
1843 struct radv_cmd_state *state = &cmd_buffer->state;
1844
1845 if (pass->attachment_count == 0) {
1846 state->attachments = NULL;
1847 return VK_SUCCESS;
1848 }
1849
1850 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1851 pass->attachment_count *
1852 sizeof(state->attachments[0]),
1853 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1854 if (state->attachments == NULL) {
1855 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1856 return cmd_buffer->record_result;
1857 }
1858
1859 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1860 struct radv_render_pass_attachment *att = &pass->attachments[i];
1861 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1862 VkImageAspectFlags clear_aspects = 0;
1863
1864 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1865 /* color attachment */
1866 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1867 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1868 }
1869 } else {
1870 /* depthstencil attachment */
1871 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1872 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1873 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1874 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1875 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1876 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1877 }
1878 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1879 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1880 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1881 }
1882 }
1883
1884 state->attachments[i].pending_clear_aspects = clear_aspects;
1885 state->attachments[i].cleared_views = 0;
1886 if (clear_aspects && info) {
1887 assert(info->clearValueCount > i);
1888 state->attachments[i].clear_value = info->pClearValues[i];
1889 }
1890
1891 state->attachments[i].current_layout = att->initial_layout;
1892 }
1893
1894 return VK_SUCCESS;
1895 }
1896
1897 VkResult radv_AllocateCommandBuffers(
1898 VkDevice _device,
1899 const VkCommandBufferAllocateInfo *pAllocateInfo,
1900 VkCommandBuffer *pCommandBuffers)
1901 {
1902 RADV_FROM_HANDLE(radv_device, device, _device);
1903 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1904
1905 VkResult result = VK_SUCCESS;
1906 uint32_t i;
1907
1908 memset(pCommandBuffers, 0,
1909 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1910
1911 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1912
1913 if (!list_empty(&pool->free_cmd_buffers)) {
1914 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1915
1916 list_del(&cmd_buffer->pool_link);
1917 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1918
1919 radv_reset_cmd_buffer(cmd_buffer);
1920 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1921 cmd_buffer->level = pAllocateInfo->level;
1922
1923 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1924 result = VK_SUCCESS;
1925 } else {
1926 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1927 &pCommandBuffers[i]);
1928 }
1929 if (result != VK_SUCCESS)
1930 break;
1931 }
1932
1933 if (result != VK_SUCCESS)
1934 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1935 i, pCommandBuffers);
1936
1937 return result;
1938 }
1939
1940 void radv_FreeCommandBuffers(
1941 VkDevice device,
1942 VkCommandPool commandPool,
1943 uint32_t commandBufferCount,
1944 const VkCommandBuffer *pCommandBuffers)
1945 {
1946 for (uint32_t i = 0; i < commandBufferCount; i++) {
1947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1948
1949 if (cmd_buffer) {
1950 if (cmd_buffer->pool) {
1951 list_del(&cmd_buffer->pool_link);
1952 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1953 } else
1954 radv_cmd_buffer_destroy(cmd_buffer);
1955
1956 }
1957 }
1958 }
1959
1960 VkResult radv_ResetCommandBuffer(
1961 VkCommandBuffer commandBuffer,
1962 VkCommandBufferResetFlags flags)
1963 {
1964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1965 radv_reset_cmd_buffer(cmd_buffer);
1966 return VK_SUCCESS;
1967 }
1968
1969 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1970 {
1971 struct radv_device *device = cmd_buffer->device;
1972 if (device->gfx_init) {
1973 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1974 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1975 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1976 radeon_emit(cmd_buffer->cs, va);
1977 radeon_emit(cmd_buffer->cs, va >> 32);
1978 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1979 } else
1980 si_init_config(cmd_buffer);
1981 }
1982
1983 VkResult radv_BeginCommandBuffer(
1984 VkCommandBuffer commandBuffer,
1985 const VkCommandBufferBeginInfo *pBeginInfo)
1986 {
1987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1988 VkResult result = VK_SUCCESS;
1989
1990 radv_reset_cmd_buffer(cmd_buffer);
1991
1992 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1993 cmd_buffer->state.last_primitive_reset_en = -1;
1994 cmd_buffer->usage_flags = pBeginInfo->flags;
1995
1996 /* setup initial configuration into command buffer */
1997 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1998 switch (cmd_buffer->queue_family_index) {
1999 case RADV_QUEUE_GENERAL:
2000 emit_gfx_buffer_state(cmd_buffer);
2001 radv_set_db_count_control(cmd_buffer);
2002 break;
2003 case RADV_QUEUE_COMPUTE:
2004 si_init_compute(cmd_buffer);
2005 break;
2006 case RADV_QUEUE_TRANSFER:
2007 default:
2008 break;
2009 }
2010 }
2011
2012 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2013 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2014 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2015
2016 struct radv_subpass *subpass =
2017 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2018
2019 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2020 if (result != VK_SUCCESS)
2021 return result;
2022
2023 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2024 }
2025
2026 radv_cmd_buffer_trace_emit(cmd_buffer);
2027 return result;
2028 }
2029
2030 void radv_CmdBindVertexBuffers(
2031 VkCommandBuffer commandBuffer,
2032 uint32_t firstBinding,
2033 uint32_t bindingCount,
2034 const VkBuffer* pBuffers,
2035 const VkDeviceSize* pOffsets)
2036 {
2037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2038 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2039
2040 /* We have to defer setting up vertex buffer since we need the buffer
2041 * stride from the pipeline. */
2042
2043 assert(firstBinding + bindingCount <= MAX_VBS);
2044 for (uint32_t i = 0; i < bindingCount; i++) {
2045 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2046 vb[firstBinding + i].offset = pOffsets[i];
2047 }
2048
2049 cmd_buffer->state.vb_dirty = true;
2050 }
2051
2052 void radv_CmdBindIndexBuffer(
2053 VkCommandBuffer commandBuffer,
2054 VkBuffer buffer,
2055 VkDeviceSize offset,
2056 VkIndexType indexType)
2057 {
2058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2059 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2060
2061 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2062 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2063 cmd_buffer->state.index_va += index_buffer->offset + offset;
2064
2065 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2066 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2067 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2068 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2069 }
2070
2071
2072 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2073 struct radv_descriptor_set *set,
2074 unsigned idx)
2075 {
2076 struct radeon_winsys *ws = cmd_buffer->device->ws;
2077
2078 cmd_buffer->state.descriptors[idx] = set;
2079 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2080 if (!set)
2081 return;
2082
2083 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2084
2085 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2086 if (set->descriptors[j])
2087 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2088
2089 if(set->bo)
2090 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2091 }
2092
2093 void radv_CmdBindDescriptorSets(
2094 VkCommandBuffer commandBuffer,
2095 VkPipelineBindPoint pipelineBindPoint,
2096 VkPipelineLayout _layout,
2097 uint32_t firstSet,
2098 uint32_t descriptorSetCount,
2099 const VkDescriptorSet* pDescriptorSets,
2100 uint32_t dynamicOffsetCount,
2101 const uint32_t* pDynamicOffsets)
2102 {
2103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2104 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2105 unsigned dyn_idx = 0;
2106
2107 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2108 unsigned idx = i + firstSet;
2109 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2110 radv_bind_descriptor_set(cmd_buffer, set, idx);
2111
2112 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2113 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2114 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2115 assert(dyn_idx < dynamicOffsetCount);
2116
2117 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2118 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2119 dst[0] = va;
2120 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2121 dst[2] = range->size;
2122 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2123 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2124 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2125 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2126 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2127 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2128 cmd_buffer->push_constant_stages |=
2129 set->layout->dynamic_shader_stages;
2130 }
2131 }
2132 }
2133
2134 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2135 struct radv_descriptor_set *set,
2136 struct radv_descriptor_set_layout *layout)
2137 {
2138 set->size = layout->size;
2139 set->layout = layout;
2140
2141 if (cmd_buffer->push_descriptors.capacity < set->size) {
2142 size_t new_size = MAX2(set->size, 1024);
2143 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2144 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2145
2146 free(set->mapped_ptr);
2147 set->mapped_ptr = malloc(new_size);
2148
2149 if (!set->mapped_ptr) {
2150 cmd_buffer->push_descriptors.capacity = 0;
2151 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2152 return false;
2153 }
2154
2155 cmd_buffer->push_descriptors.capacity = new_size;
2156 }
2157
2158 return true;
2159 }
2160
2161 void radv_meta_push_descriptor_set(
2162 struct radv_cmd_buffer* cmd_buffer,
2163 VkPipelineBindPoint pipelineBindPoint,
2164 VkPipelineLayout _layout,
2165 uint32_t set,
2166 uint32_t descriptorWriteCount,
2167 const VkWriteDescriptorSet* pDescriptorWrites)
2168 {
2169 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2170 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2171 unsigned bo_offset;
2172
2173 assert(set == 0);
2174 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2175
2176 push_set->size = layout->set[set].layout->size;
2177 push_set->layout = layout->set[set].layout;
2178
2179 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2180 &bo_offset,
2181 (void**) &push_set->mapped_ptr))
2182 return;
2183
2184 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2185 push_set->va += bo_offset;
2186
2187 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2188 radv_descriptor_set_to_handle(push_set),
2189 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2190
2191 cmd_buffer->state.descriptors[set] = push_set;
2192 cmd_buffer->state.descriptors_dirty |= (1u << set);
2193 }
2194
2195 void radv_CmdPushDescriptorSetKHR(
2196 VkCommandBuffer commandBuffer,
2197 VkPipelineBindPoint pipelineBindPoint,
2198 VkPipelineLayout _layout,
2199 uint32_t set,
2200 uint32_t descriptorWriteCount,
2201 const VkWriteDescriptorSet* pDescriptorWrites)
2202 {
2203 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2204 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2205 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2206
2207 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2208
2209 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2210 return;
2211
2212 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2213 radv_descriptor_set_to_handle(push_set),
2214 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2215
2216 cmd_buffer->state.descriptors[set] = push_set;
2217 cmd_buffer->state.descriptors_dirty |= (1u << set);
2218 cmd_buffer->state.push_descriptors_dirty = true;
2219 }
2220
2221 void radv_CmdPushDescriptorSetWithTemplateKHR(
2222 VkCommandBuffer commandBuffer,
2223 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2224 VkPipelineLayout _layout,
2225 uint32_t set,
2226 const void* pData)
2227 {
2228 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2229 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2230 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2231
2232 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2233
2234 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2235 return;
2236
2237 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2238 descriptorUpdateTemplate, pData);
2239
2240 cmd_buffer->state.descriptors[set] = push_set;
2241 cmd_buffer->state.descriptors_dirty |= (1u << set);
2242 cmd_buffer->state.push_descriptors_dirty = true;
2243 }
2244
2245 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2246 VkPipelineLayout layout,
2247 VkShaderStageFlags stageFlags,
2248 uint32_t offset,
2249 uint32_t size,
2250 const void* pValues)
2251 {
2252 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2253 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2254 cmd_buffer->push_constant_stages |= stageFlags;
2255 }
2256
2257 VkResult radv_EndCommandBuffer(
2258 VkCommandBuffer commandBuffer)
2259 {
2260 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2261
2262 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2263 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2264 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2265 si_emit_cache_flush(cmd_buffer);
2266 }
2267
2268 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2269 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2270
2271 return cmd_buffer->record_result;
2272 }
2273
2274 static void
2275 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2276 {
2277 struct radeon_winsys *ws = cmd_buffer->device->ws;
2278 struct radv_shader_variant *compute_shader;
2279 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2280 uint64_t va;
2281
2282 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2283 return;
2284
2285 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2286
2287 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2288 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2289
2290 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2291 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2292
2293 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2294 cmd_buffer->cs, 16);
2295
2296 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2297 radeon_emit(cmd_buffer->cs, va >> 8);
2298 radeon_emit(cmd_buffer->cs, va >> 40);
2299
2300 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2301 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2302 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2303
2304
2305 cmd_buffer->compute_scratch_size_needed =
2306 MAX2(cmd_buffer->compute_scratch_size_needed,
2307 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2308
2309 /* change these once we have scratch support */
2310 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2311 S_00B860_WAVES(pipeline->max_waves) |
2312 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2313
2314 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2315 radeon_emit(cmd_buffer->cs,
2316 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2317 radeon_emit(cmd_buffer->cs,
2318 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2319 radeon_emit(cmd_buffer->cs,
2320 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2321
2322 assert(cmd_buffer->cs->cdw <= cdw_max);
2323 }
2324
2325 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2326 {
2327 for (unsigned i = 0; i < MAX_SETS; i++) {
2328 if (cmd_buffer->state.descriptors[i])
2329 cmd_buffer->state.descriptors_dirty |= (1u << i);
2330 }
2331 }
2332
2333 void radv_CmdBindPipeline(
2334 VkCommandBuffer commandBuffer,
2335 VkPipelineBindPoint pipelineBindPoint,
2336 VkPipeline _pipeline)
2337 {
2338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2339 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2340
2341 radv_mark_descriptor_sets_dirty(cmd_buffer);
2342
2343 switch (pipelineBindPoint) {
2344 case VK_PIPELINE_BIND_POINT_COMPUTE:
2345 cmd_buffer->state.compute_pipeline = pipeline;
2346 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2347 break;
2348 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2349 cmd_buffer->state.pipeline = pipeline;
2350 if (!pipeline)
2351 break;
2352
2353 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2354 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2355
2356 /* Apply the dynamic state from the pipeline */
2357 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2358 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2359 &pipeline->dynamic_state,
2360 pipeline->dynamic_state_mask);
2361
2362 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2363 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2364 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2365 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2366
2367 if (radv_pipeline_has_tess(pipeline))
2368 cmd_buffer->tess_rings_needed = true;
2369
2370 if (radv_pipeline_has_gs(pipeline)) {
2371 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2372 AC_UD_SCRATCH_RING_OFFSETS);
2373 if (cmd_buffer->ring_offsets_idx == -1)
2374 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2375 else if (loc->sgpr_idx != -1)
2376 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2377 }
2378 break;
2379 default:
2380 assert(!"invalid bind point");
2381 break;
2382 }
2383 }
2384
2385 void radv_CmdSetViewport(
2386 VkCommandBuffer commandBuffer,
2387 uint32_t firstViewport,
2388 uint32_t viewportCount,
2389 const VkViewport* pViewports)
2390 {
2391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2392
2393 const uint32_t total_count = firstViewport + viewportCount;
2394 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2395 cmd_buffer->state.dynamic.viewport.count = total_count;
2396
2397 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2398 pViewports, viewportCount * sizeof(*pViewports));
2399
2400 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2401 }
2402
2403 void radv_CmdSetScissor(
2404 VkCommandBuffer commandBuffer,
2405 uint32_t firstScissor,
2406 uint32_t scissorCount,
2407 const VkRect2D* pScissors)
2408 {
2409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2410
2411 const uint32_t total_count = firstScissor + scissorCount;
2412 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2413 cmd_buffer->state.dynamic.scissor.count = total_count;
2414
2415 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2416 pScissors, scissorCount * sizeof(*pScissors));
2417 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2418 }
2419
2420 void radv_CmdSetLineWidth(
2421 VkCommandBuffer commandBuffer,
2422 float lineWidth)
2423 {
2424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2425 cmd_buffer->state.dynamic.line_width = lineWidth;
2426 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2427 }
2428
2429 void radv_CmdSetDepthBias(
2430 VkCommandBuffer commandBuffer,
2431 float depthBiasConstantFactor,
2432 float depthBiasClamp,
2433 float depthBiasSlopeFactor)
2434 {
2435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2436
2437 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2438 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2439 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2440
2441 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2442 }
2443
2444 void radv_CmdSetBlendConstants(
2445 VkCommandBuffer commandBuffer,
2446 const float blendConstants[4])
2447 {
2448 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2449
2450 memcpy(cmd_buffer->state.dynamic.blend_constants,
2451 blendConstants, sizeof(float) * 4);
2452
2453 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2454 }
2455
2456 void radv_CmdSetDepthBounds(
2457 VkCommandBuffer commandBuffer,
2458 float minDepthBounds,
2459 float maxDepthBounds)
2460 {
2461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2462
2463 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2464 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2465
2466 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2467 }
2468
2469 void radv_CmdSetStencilCompareMask(
2470 VkCommandBuffer commandBuffer,
2471 VkStencilFaceFlags faceMask,
2472 uint32_t compareMask)
2473 {
2474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2475
2476 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2477 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2478 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2479 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2480
2481 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2482 }
2483
2484 void radv_CmdSetStencilWriteMask(
2485 VkCommandBuffer commandBuffer,
2486 VkStencilFaceFlags faceMask,
2487 uint32_t writeMask)
2488 {
2489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2490
2491 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2492 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2493 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2494 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2495
2496 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2497 }
2498
2499 void radv_CmdSetStencilReference(
2500 VkCommandBuffer commandBuffer,
2501 VkStencilFaceFlags faceMask,
2502 uint32_t reference)
2503 {
2504 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2505
2506 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2507 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2508 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2509 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2510
2511 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2512 }
2513
2514 void radv_CmdExecuteCommands(
2515 VkCommandBuffer commandBuffer,
2516 uint32_t commandBufferCount,
2517 const VkCommandBuffer* pCmdBuffers)
2518 {
2519 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2520
2521 /* Emit pending flushes on primary prior to executing secondary */
2522 si_emit_cache_flush(primary);
2523
2524 for (uint32_t i = 0; i < commandBufferCount; i++) {
2525 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2526
2527 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2528 secondary->scratch_size_needed);
2529 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2530 secondary->compute_scratch_size_needed);
2531
2532 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2533 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2534 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2535 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2536 if (secondary->tess_rings_needed)
2537 primary->tess_rings_needed = true;
2538 if (secondary->sample_positions_needed)
2539 primary->sample_positions_needed = true;
2540
2541 if (secondary->ring_offsets_idx != -1) {
2542 if (primary->ring_offsets_idx == -1)
2543 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2544 else
2545 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2546 }
2547 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2548 }
2549
2550 /* if we execute secondary we need to re-emit out pipelines */
2551 if (commandBufferCount) {
2552 primary->state.emitted_pipeline = NULL;
2553 primary->state.emitted_compute_pipeline = NULL;
2554 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2555 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2556 primary->state.last_primitive_reset_en = -1;
2557 primary->state.last_primitive_reset_index = 0;
2558 radv_mark_descriptor_sets_dirty(primary);
2559 }
2560 }
2561
2562 VkResult radv_CreateCommandPool(
2563 VkDevice _device,
2564 const VkCommandPoolCreateInfo* pCreateInfo,
2565 const VkAllocationCallbacks* pAllocator,
2566 VkCommandPool* pCmdPool)
2567 {
2568 RADV_FROM_HANDLE(radv_device, device, _device);
2569 struct radv_cmd_pool *pool;
2570
2571 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2572 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2573 if (pool == NULL)
2574 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2575
2576 if (pAllocator)
2577 pool->alloc = *pAllocator;
2578 else
2579 pool->alloc = device->alloc;
2580
2581 list_inithead(&pool->cmd_buffers);
2582 list_inithead(&pool->free_cmd_buffers);
2583
2584 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2585
2586 *pCmdPool = radv_cmd_pool_to_handle(pool);
2587
2588 return VK_SUCCESS;
2589
2590 }
2591
2592 void radv_DestroyCommandPool(
2593 VkDevice _device,
2594 VkCommandPool commandPool,
2595 const VkAllocationCallbacks* pAllocator)
2596 {
2597 RADV_FROM_HANDLE(radv_device, device, _device);
2598 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2599
2600 if (!pool)
2601 return;
2602
2603 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2604 &pool->cmd_buffers, pool_link) {
2605 radv_cmd_buffer_destroy(cmd_buffer);
2606 }
2607
2608 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2609 &pool->free_cmd_buffers, pool_link) {
2610 radv_cmd_buffer_destroy(cmd_buffer);
2611 }
2612
2613 vk_free2(&device->alloc, pAllocator, pool);
2614 }
2615
2616 VkResult radv_ResetCommandPool(
2617 VkDevice device,
2618 VkCommandPool commandPool,
2619 VkCommandPoolResetFlags flags)
2620 {
2621 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2622
2623 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2624 &pool->cmd_buffers, pool_link) {
2625 radv_reset_cmd_buffer(cmd_buffer);
2626 }
2627
2628 return VK_SUCCESS;
2629 }
2630
2631 void radv_TrimCommandPoolKHR(
2632 VkDevice device,
2633 VkCommandPool commandPool,
2634 VkCommandPoolTrimFlagsKHR flags)
2635 {
2636 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2637
2638 if (!pool)
2639 return;
2640
2641 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2642 &pool->free_cmd_buffers, pool_link) {
2643 radv_cmd_buffer_destroy(cmd_buffer);
2644 }
2645 }
2646
2647 void radv_CmdBeginRenderPass(
2648 VkCommandBuffer commandBuffer,
2649 const VkRenderPassBeginInfo* pRenderPassBegin,
2650 VkSubpassContents contents)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2654 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2655
2656 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2657 cmd_buffer->cs, 2048);
2658 MAYBE_UNUSED VkResult result;
2659
2660 cmd_buffer->state.framebuffer = framebuffer;
2661 cmd_buffer->state.pass = pass;
2662 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2663 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2664 if (result != VK_SUCCESS)
2665 cmd_buffer->record_result = result;
2666
2667 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2668 assert(cmd_buffer->cs->cdw <= cdw_max);
2669
2670 radv_cmd_buffer_clear_subpass(cmd_buffer);
2671 }
2672
2673 void radv_CmdNextSubpass(
2674 VkCommandBuffer commandBuffer,
2675 VkSubpassContents contents)
2676 {
2677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2678
2679 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2680
2681 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2682 2048);
2683
2684 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2685 radv_cmd_buffer_clear_subpass(cmd_buffer);
2686 }
2687
2688 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2689 {
2690 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2691 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2692 if (!pipeline->shaders[stage])
2693 continue;
2694 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2695 if (loc->sgpr_idx == -1)
2696 continue;
2697 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2698 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2699
2700 }
2701 if (pipeline->gs_copy_shader) {
2702 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2703 if (loc->sgpr_idx != -1) {
2704 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2705 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2706 }
2707 }
2708 }
2709
2710 static void
2711 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2712 uint32_t vertex_count)
2713 {
2714 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2715 radeon_emit(cmd_buffer->cs, vertex_count);
2716 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2717 S_0287F0_USE_OPAQUE(0));
2718 }
2719
2720 void radv_CmdDraw(
2721 VkCommandBuffer commandBuffer,
2722 uint32_t vertexCount,
2723 uint32_t instanceCount,
2724 uint32_t firstVertex,
2725 uint32_t firstInstance)
2726 {
2727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2728
2729 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2730
2731 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2732
2733 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2734 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2735 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2736 radeon_emit(cmd_buffer->cs, firstVertex);
2737 radeon_emit(cmd_buffer->cs, firstInstance);
2738 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2739 radeon_emit(cmd_buffer->cs, 0);
2740
2741 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2742 radeon_emit(cmd_buffer->cs, instanceCount);
2743
2744 if (!cmd_buffer->state.subpass->view_mask) {
2745 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2746 } else {
2747 unsigned i;
2748 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2749 radv_emit_view_index(cmd_buffer, i);
2750
2751 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2752 }
2753 }
2754
2755 assert(cmd_buffer->cs->cdw <= cdw_max);
2756
2757 radv_cmd_buffer_trace_emit(cmd_buffer);
2758 }
2759
2760
2761 static void
2762 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2763 uint64_t index_va,
2764 uint32_t index_count)
2765 {
2766 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2767 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2768 radeon_emit(cmd_buffer->cs, index_va);
2769 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2770 radeon_emit(cmd_buffer->cs, index_count);
2771 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2772 }
2773
2774 void radv_CmdDrawIndexed(
2775 VkCommandBuffer commandBuffer,
2776 uint32_t indexCount,
2777 uint32_t instanceCount,
2778 uint32_t firstIndex,
2779 int32_t vertexOffset,
2780 uint32_t firstInstance)
2781 {
2782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2783 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2784 uint64_t index_va;
2785
2786 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2787
2788 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2789
2790 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2791 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2792 2, cmd_buffer->state.index_type);
2793 } else {
2794 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2795 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2796 }
2797
2798 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2799 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2800 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2801 radeon_emit(cmd_buffer->cs, vertexOffset);
2802 radeon_emit(cmd_buffer->cs, firstInstance);
2803 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2804 radeon_emit(cmd_buffer->cs, 0);
2805
2806 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2807 radeon_emit(cmd_buffer->cs, instanceCount);
2808
2809 index_va = cmd_buffer->state.index_va;
2810 index_va += firstIndex * index_size;
2811 if (!cmd_buffer->state.subpass->view_mask) {
2812 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2813 } else {
2814 unsigned i;
2815 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2816 radv_emit_view_index(cmd_buffer, i);
2817
2818 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2819 }
2820 }
2821
2822 assert(cmd_buffer->cs->cdw <= cdw_max);
2823 radv_cmd_buffer_trace_emit(cmd_buffer);
2824 }
2825
2826 static void
2827 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2828 bool indexed,
2829 uint32_t draw_count,
2830 uint64_t count_va,
2831 uint32_t stride)
2832 {
2833 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2834 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2835 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2836 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2837 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2838 assert(base_reg);
2839
2840 if (draw_count == 1 && !count_va && !draw_id_enable) {
2841 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2842 PKT3_DRAW_INDIRECT, 3, false));
2843 radeon_emit(cs, 0);
2844 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2845 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2846 radeon_emit(cs, di_src_sel);
2847 } else {
2848 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2849 PKT3_DRAW_INDIRECT_MULTI,
2850 8, false));
2851 radeon_emit(cs, 0);
2852 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2853 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2854 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2855 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2856 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2857 radeon_emit(cs, draw_count); /* count */
2858 radeon_emit(cs, count_va); /* count_addr */
2859 radeon_emit(cs, count_va >> 32);
2860 radeon_emit(cs, stride); /* stride */
2861 radeon_emit(cs, di_src_sel);
2862 }
2863 }
2864
2865 static void
2866 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2867 VkBuffer _buffer,
2868 VkDeviceSize offset,
2869 VkBuffer _count_buffer,
2870 VkDeviceSize count_offset,
2871 uint32_t draw_count,
2872 uint32_t stride,
2873 bool indexed)
2874 {
2875 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2876 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2877 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2878
2879 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2880 indirect_va += offset + buffer->offset;
2881 uint64_t count_va = 0;
2882
2883 if (count_buffer) {
2884 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2885 count_va += count_offset + count_buffer->offset;
2886 }
2887
2888 if (!draw_count)
2889 return;
2890
2891 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2892
2893 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2894 radeon_emit(cs, 1);
2895 radeon_emit(cs, indirect_va);
2896 radeon_emit(cs, indirect_va >> 32);
2897
2898 if (!cmd_buffer->state.subpass->view_mask) {
2899 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2900 } else {
2901 unsigned i;
2902 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2903 radv_emit_view_index(cmd_buffer, i);
2904
2905 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2906 }
2907 }
2908 radv_cmd_buffer_trace_emit(cmd_buffer);
2909 }
2910
2911 static void
2912 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2913 VkBuffer buffer,
2914 VkDeviceSize offset,
2915 VkBuffer countBuffer,
2916 VkDeviceSize countBufferOffset,
2917 uint32_t maxDrawCount,
2918 uint32_t stride)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2922
2923 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2924 cmd_buffer->cs, 24 * MAX_VIEWS);
2925
2926 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2927 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2928
2929 assert(cmd_buffer->cs->cdw <= cdw_max);
2930 }
2931
2932 static void
2933 radv_cmd_draw_indexed_indirect_count(
2934 VkCommandBuffer commandBuffer,
2935 VkBuffer buffer,
2936 VkDeviceSize offset,
2937 VkBuffer countBuffer,
2938 VkDeviceSize countBufferOffset,
2939 uint32_t maxDrawCount,
2940 uint32_t stride)
2941 {
2942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2943 uint64_t index_va;
2944 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2945
2946 index_va = cmd_buffer->state.index_va;
2947
2948 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
2949
2950 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2951 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2952
2953 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2954 radeon_emit(cmd_buffer->cs, index_va);
2955 radeon_emit(cmd_buffer->cs, index_va >> 32);
2956
2957 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2958 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2959
2960 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2961 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2962
2963 assert(cmd_buffer->cs->cdw <= cdw_max);
2964 }
2965
2966 void radv_CmdDrawIndirect(
2967 VkCommandBuffer commandBuffer,
2968 VkBuffer buffer,
2969 VkDeviceSize offset,
2970 uint32_t drawCount,
2971 uint32_t stride)
2972 {
2973 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2974 VK_NULL_HANDLE, 0, drawCount, stride);
2975 }
2976
2977 void radv_CmdDrawIndexedIndirect(
2978 VkCommandBuffer commandBuffer,
2979 VkBuffer buffer,
2980 VkDeviceSize offset,
2981 uint32_t drawCount,
2982 uint32_t stride)
2983 {
2984 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2985 VK_NULL_HANDLE, 0, drawCount, stride);
2986 }
2987
2988 void radv_CmdDrawIndirectCountAMD(
2989 VkCommandBuffer commandBuffer,
2990 VkBuffer buffer,
2991 VkDeviceSize offset,
2992 VkBuffer countBuffer,
2993 VkDeviceSize countBufferOffset,
2994 uint32_t maxDrawCount,
2995 uint32_t stride)
2996 {
2997 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2998 countBuffer, countBufferOffset,
2999 maxDrawCount, stride);
3000 }
3001
3002 void radv_CmdDrawIndexedIndirectCountAMD(
3003 VkCommandBuffer commandBuffer,
3004 VkBuffer buffer,
3005 VkDeviceSize offset,
3006 VkBuffer countBuffer,
3007 VkDeviceSize countBufferOffset,
3008 uint32_t maxDrawCount,
3009 uint32_t stride)
3010 {
3011 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3012 countBuffer, countBufferOffset,
3013 maxDrawCount, stride);
3014 }
3015
3016 static void
3017 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
3018 {
3019 radv_emit_compute_pipeline(cmd_buffer);
3020 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3021 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3022 VK_SHADER_STAGE_COMPUTE_BIT);
3023 si_emit_cache_flush(cmd_buffer);
3024 }
3025
3026 void radv_CmdDispatch(
3027 VkCommandBuffer commandBuffer,
3028 uint32_t x,
3029 uint32_t y,
3030 uint32_t z)
3031 {
3032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3033
3034 radv_flush_compute_state(cmd_buffer);
3035
3036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
3037
3038 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3039 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3040 if (loc->sgpr_idx != -1) {
3041 assert(!loc->indirect);
3042 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3043 assert(loc->num_sgprs == grid_used);
3044 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3045 radeon_emit(cmd_buffer->cs, x);
3046 if (grid_used > 1)
3047 radeon_emit(cmd_buffer->cs, y);
3048 if (grid_used > 2)
3049 radeon_emit(cmd_buffer->cs, z);
3050 }
3051
3052 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3053 PKT3_SHADER_TYPE_S(1));
3054 radeon_emit(cmd_buffer->cs, x);
3055 radeon_emit(cmd_buffer->cs, y);
3056 radeon_emit(cmd_buffer->cs, z);
3057 radeon_emit(cmd_buffer->cs, 1);
3058
3059 assert(cmd_buffer->cs->cdw <= cdw_max);
3060 radv_cmd_buffer_trace_emit(cmd_buffer);
3061 }
3062
3063 void radv_CmdDispatchIndirect(
3064 VkCommandBuffer commandBuffer,
3065 VkBuffer _buffer,
3066 VkDeviceSize offset)
3067 {
3068 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3069 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3070 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
3071 va += buffer->offset + offset;
3072
3073 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
3074
3075 radv_flush_compute_state(cmd_buffer);
3076
3077 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
3078 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3079 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3080 if (loc->sgpr_idx != -1) {
3081 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3082 for (unsigned i = 0; i < grid_used; ++i) {
3083 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
3084 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3085 COPY_DATA_DST_SEL(COPY_DATA_REG));
3086 radeon_emit(cmd_buffer->cs, (va + 4 * i));
3087 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
3088 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
3089 radeon_emit(cmd_buffer->cs, 0);
3090 }
3091 }
3092
3093 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3095 PKT3_SHADER_TYPE_S(1));
3096 radeon_emit(cmd_buffer->cs, va);
3097 radeon_emit(cmd_buffer->cs, va >> 32);
3098 radeon_emit(cmd_buffer->cs, 1);
3099 } else {
3100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
3101 PKT3_SHADER_TYPE_S(1));
3102 radeon_emit(cmd_buffer->cs, 1);
3103 radeon_emit(cmd_buffer->cs, va);
3104 radeon_emit(cmd_buffer->cs, va >> 32);
3105
3106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3107 PKT3_SHADER_TYPE_S(1));
3108 radeon_emit(cmd_buffer->cs, 0);
3109 radeon_emit(cmd_buffer->cs, 1);
3110 }
3111
3112 assert(cmd_buffer->cs->cdw <= cdw_max);
3113 radv_cmd_buffer_trace_emit(cmd_buffer);
3114 }
3115
3116 void radv_unaligned_dispatch(
3117 struct radv_cmd_buffer *cmd_buffer,
3118 uint32_t x,
3119 uint32_t y,
3120 uint32_t z)
3121 {
3122 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3123 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3124 uint32_t blocks[3], remainder[3];
3125
3126 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3127 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3128 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3129
3130 /* If aligned, these should be an entire block size, not 0 */
3131 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3132 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3133 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3134
3135 radv_flush_compute_state(cmd_buffer);
3136
3137 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3138
3139 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3140 radeon_emit(cmd_buffer->cs,
3141 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3142 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3143 radeon_emit(cmd_buffer->cs,
3144 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3145 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3146 radeon_emit(cmd_buffer->cs,
3147 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3148 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3149
3150 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3151 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3152 if (loc->sgpr_idx != -1) {
3153 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3154 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3155 radeon_emit(cmd_buffer->cs, blocks[0]);
3156 if (grid_used > 1)
3157 radeon_emit(cmd_buffer->cs, blocks[1]);
3158 if (grid_used > 2)
3159 radeon_emit(cmd_buffer->cs, blocks[2]);
3160 }
3161 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3162 PKT3_SHADER_TYPE_S(1));
3163 radeon_emit(cmd_buffer->cs, blocks[0]);
3164 radeon_emit(cmd_buffer->cs, blocks[1]);
3165 radeon_emit(cmd_buffer->cs, blocks[2]);
3166 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3167 S_00B800_PARTIAL_TG_EN(1));
3168
3169 assert(cmd_buffer->cs->cdw <= cdw_max);
3170 radv_cmd_buffer_trace_emit(cmd_buffer);
3171 }
3172
3173 void radv_CmdEndRenderPass(
3174 VkCommandBuffer commandBuffer)
3175 {
3176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3177
3178 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3179
3180 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3181
3182 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3183 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3184 radv_handle_subpass_image_transition(cmd_buffer,
3185 (VkAttachmentReference){i, layout});
3186 }
3187
3188 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3189
3190 cmd_buffer->state.pass = NULL;
3191 cmd_buffer->state.subpass = NULL;
3192 cmd_buffer->state.attachments = NULL;
3193 cmd_buffer->state.framebuffer = NULL;
3194 }
3195
3196 /*
3197 * For HTILE we have the following interesting clear words:
3198 * 0x0000030f: Uncompressed.
3199 * 0xfffffff0: Clear depth to 1.0
3200 * 0x00000000: Clear depth to 0.0
3201 */
3202 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3203 struct radv_image *image,
3204 const VkImageSubresourceRange *range,
3205 uint32_t clear_word)
3206 {
3207 assert(range->baseMipLevel == 0);
3208 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3209 unsigned layer_count = radv_get_layerCount(image, range);
3210 uint64_t size = image->surface.htile_slice_size * layer_count;
3211 uint64_t offset = image->offset + image->htile_offset +
3212 image->surface.htile_slice_size * range->baseArrayLayer;
3213
3214 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3215 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3216
3217 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3218
3219 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3220 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3221 RADV_CMD_FLAG_INV_VMEM_L1 |
3222 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3223 }
3224
3225 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3226 struct radv_image *image,
3227 VkImageLayout src_layout,
3228 VkImageLayout dst_layout,
3229 unsigned src_queue_mask,
3230 unsigned dst_queue_mask,
3231 const VkImageSubresourceRange *range,
3232 VkImageAspectFlags pending_clears)
3233 {
3234 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3235 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3236 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3237 cmd_buffer->state.render_area.extent.width == image->info.width &&
3238 cmd_buffer->state.render_area.extent.height == image->info.height) {
3239 /* The clear will initialize htile. */
3240 return;
3241 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3242 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3243 /* TODO: merge with the clear if applicable */
3244 radv_initialize_htile(cmd_buffer, image, range, 0);
3245 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3246 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3247 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3248 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3249 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3250 VkImageSubresourceRange local_range = *range;
3251 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3252 local_range.baseMipLevel = 0;
3253 local_range.levelCount = 1;
3254
3255 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3256 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3257
3258 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3259
3260 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3261 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3262 }
3263 }
3264
3265 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3266 struct radv_image *image, uint32_t value)
3267 {
3268 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3269 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3270
3271 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3272 image->cmask.size, value);
3273
3274 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3275 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3276 RADV_CMD_FLAG_INV_VMEM_L1 |
3277 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3278 }
3279
3280 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3281 struct radv_image *image,
3282 VkImageLayout src_layout,
3283 VkImageLayout dst_layout,
3284 unsigned src_queue_mask,
3285 unsigned dst_queue_mask,
3286 const VkImageSubresourceRange *range,
3287 VkImageAspectFlags pending_clears)
3288 {
3289 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3290 if (image->fmask.size)
3291 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3292 else
3293 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3294 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3295 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3296 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3297 }
3298 }
3299
3300 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3301 struct radv_image *image, uint32_t value)
3302 {
3303
3304 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3305 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3306
3307 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3308 image->surface.dcc_size, value);
3309
3310 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3311 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3312 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3313 RADV_CMD_FLAG_INV_VMEM_L1 |
3314 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3315 }
3316
3317 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3318 struct radv_image *image,
3319 VkImageLayout src_layout,
3320 VkImageLayout dst_layout,
3321 unsigned src_queue_mask,
3322 unsigned dst_queue_mask,
3323 const VkImageSubresourceRange *range,
3324 VkImageAspectFlags pending_clears)
3325 {
3326 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3327 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3328 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3329 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3330 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3331 }
3332 }
3333
3334 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3335 struct radv_image *image,
3336 VkImageLayout src_layout,
3337 VkImageLayout dst_layout,
3338 uint32_t src_family,
3339 uint32_t dst_family,
3340 const VkImageSubresourceRange *range,
3341 VkImageAspectFlags pending_clears)
3342 {
3343 if (image->exclusive && src_family != dst_family) {
3344 /* This is an acquire or a release operation and there will be
3345 * a corresponding release/acquire. Do the transition in the
3346 * most flexible queue. */
3347
3348 assert(src_family == cmd_buffer->queue_family_index ||
3349 dst_family == cmd_buffer->queue_family_index);
3350
3351 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3352 return;
3353
3354 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3355 (src_family == RADV_QUEUE_GENERAL ||
3356 dst_family == RADV_QUEUE_GENERAL))
3357 return;
3358 }
3359
3360 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3361 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3362
3363 if (image->surface.htile_size)
3364 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3365 dst_layout, src_queue_mask,
3366 dst_queue_mask, range,
3367 pending_clears);
3368
3369 if (image->cmask.size)
3370 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3371 dst_layout, src_queue_mask,
3372 dst_queue_mask, range,
3373 pending_clears);
3374
3375 if (image->surface.dcc_size)
3376 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3377 dst_layout, src_queue_mask,
3378 dst_queue_mask, range,
3379 pending_clears);
3380 }
3381
3382 void radv_CmdPipelineBarrier(
3383 VkCommandBuffer commandBuffer,
3384 VkPipelineStageFlags srcStageMask,
3385 VkPipelineStageFlags destStageMask,
3386 VkBool32 byRegion,
3387 uint32_t memoryBarrierCount,
3388 const VkMemoryBarrier* pMemoryBarriers,
3389 uint32_t bufferMemoryBarrierCount,
3390 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3391 uint32_t imageMemoryBarrierCount,
3392 const VkImageMemoryBarrier* pImageMemoryBarriers)
3393 {
3394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3395 enum radv_cmd_flush_bits src_flush_bits = 0;
3396 enum radv_cmd_flush_bits dst_flush_bits = 0;
3397
3398 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3399 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3400 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3401 NULL);
3402 }
3403
3404 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3405 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3406 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3407 NULL);
3408 }
3409
3410 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3411 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3412 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3413 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3414 image);
3415 }
3416
3417 radv_stage_flush(cmd_buffer, srcStageMask);
3418 cmd_buffer->state.flush_bits |= src_flush_bits;
3419
3420 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3421 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3422 radv_handle_image_transition(cmd_buffer, image,
3423 pImageMemoryBarriers[i].oldLayout,
3424 pImageMemoryBarriers[i].newLayout,
3425 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3426 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3427 &pImageMemoryBarriers[i].subresourceRange,
3428 0);
3429 }
3430
3431 cmd_buffer->state.flush_bits |= dst_flush_bits;
3432 }
3433
3434
3435 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3436 struct radv_event *event,
3437 VkPipelineStageFlags stageMask,
3438 unsigned value)
3439 {
3440 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3441 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3442
3443 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3444
3445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3446
3447 /* TODO: this is overkill. Probably should figure something out from
3448 * the stage mask. */
3449
3450 si_cs_emit_write_event_eop(cs,
3451 cmd_buffer->state.predicating,
3452 cmd_buffer->device->physical_device->rad_info.chip_class,
3453 false,
3454 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3455 1, va, 2, value);
3456
3457 assert(cmd_buffer->cs->cdw <= cdw_max);
3458 }
3459
3460 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3461 VkEvent _event,
3462 VkPipelineStageFlags stageMask)
3463 {
3464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3465 RADV_FROM_HANDLE(radv_event, event, _event);
3466
3467 write_event(cmd_buffer, event, stageMask, 1);
3468 }
3469
3470 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3471 VkEvent _event,
3472 VkPipelineStageFlags stageMask)
3473 {
3474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3475 RADV_FROM_HANDLE(radv_event, event, _event);
3476
3477 write_event(cmd_buffer, event, stageMask, 0);
3478 }
3479
3480 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3481 uint32_t eventCount,
3482 const VkEvent* pEvents,
3483 VkPipelineStageFlags srcStageMask,
3484 VkPipelineStageFlags dstStageMask,
3485 uint32_t memoryBarrierCount,
3486 const VkMemoryBarrier* pMemoryBarriers,
3487 uint32_t bufferMemoryBarrierCount,
3488 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3489 uint32_t imageMemoryBarrierCount,
3490 const VkImageMemoryBarrier* pImageMemoryBarriers)
3491 {
3492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3493 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3494
3495 for (unsigned i = 0; i < eventCount; ++i) {
3496 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3497 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3498
3499 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3500
3501 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3502
3503 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3504 assert(cmd_buffer->cs->cdw <= cdw_max);
3505 }
3506
3507
3508 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3509 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3510
3511 radv_handle_image_transition(cmd_buffer, image,
3512 pImageMemoryBarriers[i].oldLayout,
3513 pImageMemoryBarriers[i].newLayout,
3514 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3515 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3516 &pImageMemoryBarriers[i].subresourceRange,
3517 0);
3518 }
3519
3520 /* TODO: figure out how to do memory barriers without waiting */
3521 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3522 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3523 RADV_CMD_FLAG_INV_VMEM_L1 |
3524 RADV_CMD_FLAG_INV_SMEM_L1;
3525 }