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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94 dest->discard_rectangle.count = src->discard_rectangle.count;
95
96 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
97 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
98 src->viewport.count * sizeof(VkViewport))) {
99 typed_memcpy(dest->viewport.viewports,
100 src->viewport.viewports,
101 src->viewport.count);
102 dest_mask |= RADV_DYNAMIC_VIEWPORT;
103 }
104 }
105
106 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
107 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
108 src->scissor.count * sizeof(VkRect2D))) {
109 typed_memcpy(dest->scissor.scissors,
110 src->scissor.scissors, src->scissor.count);
111 dest_mask |= RADV_DYNAMIC_SCISSOR;
112 }
113 }
114
115 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
116 if (dest->line_width != src->line_width) {
117 dest->line_width = src->line_width;
118 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
123 if (memcmp(&dest->depth_bias, &src->depth_bias,
124 sizeof(src->depth_bias))) {
125 dest->depth_bias = src->depth_bias;
126 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
131 if (memcmp(&dest->blend_constants, &src->blend_constants,
132 sizeof(src->blend_constants))) {
133 typed_memcpy(dest->blend_constants,
134 src->blend_constants, 4);
135 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
140 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
141 sizeof(src->depth_bounds))) {
142 dest->depth_bounds = src->depth_bounds;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
148 if (memcmp(&dest->stencil_compare_mask,
149 &src->stencil_compare_mask,
150 sizeof(src->stencil_compare_mask))) {
151 dest->stencil_compare_mask = src->stencil_compare_mask;
152 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
157 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
158 sizeof(src->stencil_write_mask))) {
159 dest->stencil_write_mask = src->stencil_write_mask;
160 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
165 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
166 sizeof(src->stencil_reference))) {
167 dest->stencil_reference = src->stencil_reference;
168 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
173 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
174 src->discard_rectangle.count * sizeof(VkRect2D))) {
175 typed_memcpy(dest->discard_rectangle.rectangles,
176 src->discard_rectangle.rectangles,
177 src->discard_rectangle.count);
178 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
179 }
180 }
181
182 cmd_buffer->state.dirty |= dest_mask;
183 }
184
185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
186 {
187 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
188 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
189 }
190
191 enum ring_type radv_queue_family_to_ring(int f) {
192 switch (f) {
193 case RADV_QUEUE_GENERAL:
194 return RING_GFX;
195 case RADV_QUEUE_COMPUTE:
196 return RING_COMPUTE;
197 case RADV_QUEUE_TRANSFER:
198 return RING_DMA;
199 default:
200 unreachable("Unknown queue family");
201 }
202 }
203
204 static VkResult radv_create_cmd_buffer(
205 struct radv_device * device,
206 struct radv_cmd_pool * pool,
207 VkCommandBufferLevel level,
208 VkCommandBuffer* pCommandBuffer)
209 {
210 struct radv_cmd_buffer *cmd_buffer;
211 unsigned ring;
212 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
216
217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 cmd_buffer->device = device;
219 cmd_buffer->pool = pool;
220 cmd_buffer->level = level;
221
222 if (pool) {
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 cmd_buffer->queue_family_index = pool->queue_family_index;
225
226 } else {
227 /* Init the pool_link so we can safefly call list_del when we destroy
228 * the command buffer
229 */
230 list_inithead(&cmd_buffer->pool_link);
231 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
232 }
233
234 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
235
236 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
237 if (!cmd_buffer->cs) {
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
240 }
241
242 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
243
244 list_inithead(&cmd_buffer->upload.list);
245
246 return VK_SUCCESS;
247 }
248
249 static void
250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
251 {
252 list_del(&cmd_buffer->pool_link);
253
254 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
255 &cmd_buffer->upload.list, list) {
256 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
257 list_del(&up->list);
258 free(up);
259 }
260
261 if (cmd_buffer->upload.upload_bo)
262 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
263 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
264 free(cmd_buffer->push_descriptors.set.mapped_ptr);
265 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
266 }
267
268 static VkResult
269 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
270 {
271
272 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
273
274 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
275 &cmd_buffer->upload.list, list) {
276 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
277 list_del(&up->list);
278 free(up);
279 }
280
281 cmd_buffer->push_constant_stages = 0;
282 cmd_buffer->scratch_size_needed = 0;
283 cmd_buffer->compute_scratch_size_needed = 0;
284 cmd_buffer->esgs_ring_size_needed = 0;
285 cmd_buffer->gsvs_ring_size_needed = 0;
286 cmd_buffer->tess_rings_needed = false;
287 cmd_buffer->sample_positions_needed = false;
288
289 if (cmd_buffer->upload.upload_bo)
290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
291 cmd_buffer->upload.upload_bo, 8);
292 cmd_buffer->upload.offset = 0;
293
294 cmd_buffer->record_result = VK_SUCCESS;
295
296 cmd_buffer->ring_offsets_idx = -1;
297
298 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
299 void *fence_ptr;
300 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
301 &cmd_buffer->gfx9_fence_offset,
302 &fence_ptr);
303 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
304 }
305
306 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
307
308 return cmd_buffer->record_result;
309 }
310
311 static bool
312 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
313 uint64_t min_needed)
314 {
315 uint64_t new_size;
316 struct radeon_winsys_bo *bo;
317 struct radv_cmd_buffer_upload *upload;
318 struct radv_device *device = cmd_buffer->device;
319
320 new_size = MAX2(min_needed, 16 * 1024);
321 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
322
323 bo = device->ws->buffer_create(device->ws,
324 new_size, 4096,
325 RADEON_DOMAIN_GTT,
326 RADEON_FLAG_CPU_ACCESS|
327 RADEON_FLAG_NO_INTERPROCESS_SHARING);
328
329 if (!bo) {
330 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
331 return false;
332 }
333
334 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
335 if (cmd_buffer->upload.upload_bo) {
336 upload = malloc(sizeof(*upload));
337
338 if (!upload) {
339 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
340 device->ws->buffer_destroy(bo);
341 return false;
342 }
343
344 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
345 list_add(&upload->list, &cmd_buffer->upload.list);
346 }
347
348 cmd_buffer->upload.upload_bo = bo;
349 cmd_buffer->upload.size = new_size;
350 cmd_buffer->upload.offset = 0;
351 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
352
353 if (!cmd_buffer->upload.map) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 return true;
359 }
360
361 bool
362 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
363 unsigned size,
364 unsigned alignment,
365 unsigned *out_offset,
366 void **ptr)
367 {
368 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
369 if (offset + size > cmd_buffer->upload.size) {
370 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
371 return false;
372 offset = 0;
373 }
374
375 *out_offset = offset;
376 *ptr = cmd_buffer->upload.map + offset;
377
378 cmd_buffer->upload.offset = offset + size;
379 return true;
380 }
381
382 bool
383 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
384 unsigned size, unsigned alignment,
385 const void *data, unsigned *out_offset)
386 {
387 uint8_t *ptr;
388
389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
390 out_offset, (void **)&ptr))
391 return false;
392
393 if (ptr)
394 memcpy(ptr, data, size);
395
396 return true;
397 }
398
399 static void
400 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
401 unsigned count, const uint32_t *data)
402 {
403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
404 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
405 S_370_WR_CONFIRM(1) |
406 S_370_ENGINE_SEL(V_370_ME));
407 radeon_emit(cs, va);
408 radeon_emit(cs, va >> 32);
409 radeon_emit_array(cs, data, count);
410 }
411
412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
413 {
414 struct radv_device *device = cmd_buffer->device;
415 struct radeon_winsys_cs *cs = cmd_buffer->cs;
416 uint64_t va;
417
418 va = radv_buffer_get_va(device->trace_bo);
419 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
420 va += 4;
421
422 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
423
424 ++cmd_buffer->state.trace_id;
425 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
426 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
428 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
429 }
430
431 static void
432 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
433 enum radv_cmd_flush_bits flags)
434 {
435 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
436 uint32_t *ptr = NULL;
437 uint64_t va = 0;
438
439 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
440 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
441
442 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
443 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
444 cmd_buffer->gfx9_fence_offset;
445 ptr = &cmd_buffer->gfx9_fence_idx;
446 }
447
448 /* Force wait for graphics or compute engines to be idle. */
449 si_cs_emit_cache_flush(cmd_buffer->cs, false,
450 cmd_buffer->device->physical_device->rad_info.chip_class,
451 ptr, va,
452 radv_cmd_buffer_uses_mec(cmd_buffer),
453 flags);
454 }
455
456 if (unlikely(cmd_buffer->device->trace_bo))
457 radv_cmd_buffer_trace_emit(cmd_buffer);
458 }
459
460 static void
461 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
462 struct radv_pipeline *pipeline, enum ring_type ring)
463 {
464 struct radv_device *device = cmd_buffer->device;
465 struct radeon_winsys_cs *cs = cmd_buffer->cs;
466 uint32_t data[2];
467 uint64_t va;
468
469 va = radv_buffer_get_va(device->trace_bo);
470
471 switch (ring) {
472 case RING_GFX:
473 va += 8;
474 break;
475 case RING_COMPUTE:
476 va += 16;
477 break;
478 default:
479 assert(!"invalid ring type");
480 }
481
482 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
483 cmd_buffer->cs, 6);
484
485 data[0] = (uintptr_t)pipeline;
486 data[1] = (uintptr_t)pipeline >> 32;
487
488 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
489 radv_emit_write_data_packet(cs, va, 2, data);
490 }
491
492 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_descriptor_set *set,
494 unsigned idx)
495 {
496 cmd_buffer->descriptors[idx] = set;
497 if (set)
498 cmd_buffer->state.valid_descriptors |= (1u << idx);
499 else
500 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
501 cmd_buffer->state.descriptors_dirty |= (1u << idx);
502
503 }
504
505 static void
506 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
507 {
508 struct radv_device *device = cmd_buffer->device;
509 struct radeon_winsys_cs *cs = cmd_buffer->cs;
510 uint32_t data[MAX_SETS * 2] = {};
511 uint64_t va;
512 unsigned i;
513 va = radv_buffer_get_va(device->trace_bo) + 24;
514
515 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
516 cmd_buffer->cs, 4 + MAX_SETS * 2);
517
518 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
519 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
520 data[i * 2] = (uintptr_t)set;
521 data[i * 2 + 1] = (uintptr_t)set >> 32;
522 }
523
524 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
525 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
526 }
527
528 static void
529 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
530 struct radv_pipeline *pipeline)
531 {
532 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
533 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
534 8);
535 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
536 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
537
538 if (cmd_buffer->device->physical_device->has_rbplus) {
539
540 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
541 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
542
543 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
544 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
545 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
546 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
547 }
548 }
549
550 static void
551 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
552 struct radv_pipeline *pipeline)
553 {
554 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
555 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
556 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
559 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
560 }
561
562 struct ac_userdata_info *
563 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
564 gl_shader_stage stage,
565 int idx)
566 {
567 if (stage == MESA_SHADER_VERTEX) {
568 if (pipeline->shaders[MESA_SHADER_VERTEX])
569 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
570 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
571 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 } else if (stage == MESA_SHADER_TESS_EVAL) {
575 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
576 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
577 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
578 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
579 }
580 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
581 }
582
583 static void
584 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_pipeline *pipeline,
586 gl_shader_stage stage,
587 int idx, uint64_t va)
588 {
589 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
590 uint32_t base_reg = pipeline->user_data_0[stage];
591 if (loc->sgpr_idx == -1)
592 return;
593 assert(loc->num_sgprs == 2);
594 assert(!loc->indirect);
595 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
596 radeon_emit(cmd_buffer->cs, va);
597 radeon_emit(cmd_buffer->cs, va >> 32);
598 }
599
600 static void
601 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
602 struct radv_pipeline *pipeline)
603 {
604 int num_samples = pipeline->graphics.ms.num_samples;
605 struct radv_multisample_state *ms = &pipeline->graphics.ms;
606 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
607
608 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
609 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
611
612 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
613 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
614
615 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
616 uint32_t offset;
617 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
618 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
619 if (loc->sgpr_idx == -1)
620 return;
621 assert(loc->num_sgprs == 1);
622 assert(!loc->indirect);
623 switch (num_samples) {
624 default:
625 offset = 0;
626 break;
627 case 2:
628 offset = 1;
629 break;
630 case 4:
631 offset = 3;
632 break;
633 case 8:
634 offset = 7;
635 break;
636 case 16:
637 offset = 15;
638 break;
639 }
640
641 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
642 cmd_buffer->sample_positions_needed = true;
643 }
644
645 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
646 return;
647
648 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
649 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
650 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
651
652 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
653
654 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
655
656 /* GFX9: Flush DFSM when the AA mode changes. */
657 if (cmd_buffer->device->dfsm_allowed) {
658 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
659 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
660 }
661 }
662
663 static void
664 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
665 struct radv_pipeline *pipeline)
666 {
667 struct radv_raster_state *raster = &pipeline->graphics.raster;
668
669 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
670 raster->pa_cl_clip_cntl);
671 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
672 raster->spi_interp_control);
673 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
674 raster->pa_su_vtx_cntl);
675 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
676 raster->pa_su_sc_mode_cntl);
677 }
678
679 static inline void
680 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
681 unsigned size)
682 {
683 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
684 si_cp_dma_prefetch(cmd_buffer, va, size);
685 }
686
687 static void
688 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
689 {
690 if (cmd_buffer->state.vb_prefetch_dirty) {
691 radv_emit_prefetch_TC_L2_async(cmd_buffer,
692 cmd_buffer->state.vb_va,
693 cmd_buffer->state.vb_size);
694 cmd_buffer->state.vb_prefetch_dirty = false;
695 }
696 }
697
698 static void
699 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
700 struct radv_shader_variant *shader)
701 {
702 struct radeon_winsys *ws = cmd_buffer->device->ws;
703 struct radeon_winsys_cs *cs = cmd_buffer->cs;
704 uint64_t va;
705
706 if (!shader)
707 return;
708
709 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
710
711 radv_cs_add_buffer(ws, cs, shader->bo, 8);
712 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
713 }
714
715 static void
716 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
717 struct radv_pipeline *pipeline)
718 {
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_VERTEX]);
721 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
722 radv_emit_shader_prefetch(cmd_buffer,
723 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
724 radv_emit_shader_prefetch(cmd_buffer,
725 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
726 radv_emit_shader_prefetch(cmd_buffer,
727 pipeline->shaders[MESA_SHADER_GEOMETRY]);
728 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
729 radv_emit_shader_prefetch(cmd_buffer,
730 pipeline->shaders[MESA_SHADER_FRAGMENT]);
731 }
732
733 static void
734 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
735 struct radv_pipeline *pipeline,
736 struct radv_shader_variant *shader)
737 {
738 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
739
740 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
741 pipeline->graphics.vs.spi_vs_out_config);
742
743 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
744 pipeline->graphics.vs.spi_shader_pos_format);
745
746 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
747 radeon_emit(cmd_buffer->cs, va >> 8);
748 radeon_emit(cmd_buffer->cs, va >> 40);
749 radeon_emit(cmd_buffer->cs, shader->rsrc1);
750 radeon_emit(cmd_buffer->cs, shader->rsrc2);
751
752 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
753 S_028818_VTX_W0_FMT(1) |
754 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
755 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
756 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
757
758
759 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
760 pipeline->graphics.vs.pa_cl_vs_out_cntl);
761
762 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
763 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
764 pipeline->graphics.vs.vgt_reuse_off);
765 }
766
767 static void
768 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
769 struct radv_pipeline *pipeline,
770 struct radv_shader_variant *shader)
771 {
772 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
773
774 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
775 radeon_emit(cmd_buffer->cs, va >> 8);
776 radeon_emit(cmd_buffer->cs, va >> 40);
777 radeon_emit(cmd_buffer->cs, shader->rsrc1);
778 radeon_emit(cmd_buffer->cs, shader->rsrc2);
779 }
780
781 static void
782 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
783 struct radv_shader_variant *shader)
784 {
785 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
786 uint32_t rsrc2 = shader->rsrc2;
787
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791
792 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
793 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
794 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
795 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
796
797 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
798 radeon_emit(cmd_buffer->cs, shader->rsrc1);
799 radeon_emit(cmd_buffer->cs, rsrc2);
800 }
801
802 static void
803 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_shader_variant *shader)
805 {
806 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
807
808 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
809 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
810 radeon_emit(cmd_buffer->cs, va >> 8);
811 radeon_emit(cmd_buffer->cs, va >> 40);
812
813 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
814 radeon_emit(cmd_buffer->cs, shader->rsrc1);
815 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
816 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
817 } else {
818 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
819 radeon_emit(cmd_buffer->cs, va >> 8);
820 radeon_emit(cmd_buffer->cs, va >> 40);
821 radeon_emit(cmd_buffer->cs, shader->rsrc1);
822 radeon_emit(cmd_buffer->cs, shader->rsrc2);
823 }
824 }
825
826 static void
827 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
828 struct radv_pipeline *pipeline)
829 {
830 struct radv_shader_variant *vs;
831
832 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
833
834 /* Skip shaders merged into HS/GS */
835 vs = pipeline->shaders[MESA_SHADER_VERTEX];
836 if (!vs)
837 return;
838
839 if (vs->info.vs.as_ls)
840 radv_emit_hw_ls(cmd_buffer, vs);
841 else if (vs->info.vs.as_es)
842 radv_emit_hw_es(cmd_buffer, pipeline, vs);
843 else
844 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
845 }
846
847
848 static void
849 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
850 struct radv_pipeline *pipeline)
851 {
852 if (!radv_pipeline_has_tess(pipeline))
853 return;
854
855 struct radv_shader_variant *tes, *tcs;
856
857 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
858 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
859
860 if (tes) {
861 if (tes->info.tes.as_es)
862 radv_emit_hw_es(cmd_buffer, pipeline, tes);
863 else
864 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
865 }
866
867 radv_emit_hw_hs(cmd_buffer, tcs);
868
869 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
870 pipeline->graphics.tess.tf_param);
871
872 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
873 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
874 pipeline->graphics.tess.ls_hs_config);
875 else
876 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
877 pipeline->graphics.tess.ls_hs_config);
878
879 struct ac_userdata_info *loc;
880
881 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
882 if (loc->sgpr_idx != -1) {
883 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
884 assert(loc->num_sgprs == 4);
885 assert(!loc->indirect);
886 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
887 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
888 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
889 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
890 pipeline->graphics.tess.num_tcs_input_cp << 26);
891 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
892 }
893
894 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
895 if (loc->sgpr_idx != -1) {
896 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
897 assert(loc->num_sgprs == 1);
898 assert(!loc->indirect);
899
900 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
901 pipeline->graphics.tess.offchip_layout);
902 }
903
904 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
905 if (loc->sgpr_idx != -1) {
906 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
907 assert(loc->num_sgprs == 1);
908 assert(!loc->indirect);
909
910 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
911 pipeline->graphics.tess.tcs_in_layout);
912 }
913 }
914
915 static void
916 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
917 struct radv_pipeline *pipeline)
918 {
919 struct radv_shader_variant *gs;
920 uint64_t va;
921
922 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
923
924 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
925 if (!gs)
926 return;
927
928 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
929
930 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
931 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
932 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
933 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
934
935 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
936
937 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
938
939 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
940 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
941 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
942 radeon_emit(cmd_buffer->cs, 0);
943 radeon_emit(cmd_buffer->cs, 0);
944 radeon_emit(cmd_buffer->cs, 0);
945
946 uint32_t gs_num_invocations = gs->info.gs.invocations;
947 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
948 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
949 S_028B90_ENABLE(gs_num_invocations > 0));
950
951 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
952 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
953
954 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
955
956 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
957 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
958 radeon_emit(cmd_buffer->cs, va >> 8);
959 radeon_emit(cmd_buffer->cs, va >> 40);
960
961 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
962 radeon_emit(cmd_buffer->cs, gs->rsrc1);
963 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
964 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
967 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
968 } else {
969 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
970 radeon_emit(cmd_buffer->cs, va >> 8);
971 radeon_emit(cmd_buffer->cs, va >> 40);
972 radeon_emit(cmd_buffer->cs, gs->rsrc1);
973 radeon_emit(cmd_buffer->cs, gs->rsrc2);
974 }
975
976 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
977
978 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
979 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
980 if (loc->sgpr_idx != -1) {
981 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
982 uint32_t num_entries = 64;
983 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
984
985 if (is_vi)
986 num_entries *= stride;
987
988 stride = S_008F04_STRIDE(stride);
989 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
990 radeon_emit(cmd_buffer->cs, stride);
991 radeon_emit(cmd_buffer->cs, num_entries);
992 }
993 }
994
995 static void
996 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
997 struct radv_pipeline *pipeline)
998 {
999 struct radv_shader_variant *ps;
1000 uint64_t va;
1001 struct radv_blend_state *blend = &pipeline->graphics.blend;
1002 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
1003
1004 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1005 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
1006
1007 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
1008 radeon_emit(cmd_buffer->cs, va >> 8);
1009 radeon_emit(cmd_buffer->cs, va >> 40);
1010 radeon_emit(cmd_buffer->cs, ps->rsrc1);
1011 radeon_emit(cmd_buffer->cs, ps->rsrc2);
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
1014 pipeline->graphics.db_shader_control);
1015
1016 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
1017 ps->config.spi_ps_input_ena);
1018
1019 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1020 ps->config.spi_ps_input_addr);
1021
1022 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1023 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
1026
1027 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1028 pipeline->graphics.shader_z_format);
1029
1030 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1031
1032 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1033 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1034
1035 if (cmd_buffer->device->dfsm_allowed) {
1036 /* optimise this? */
1037 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1038 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1039 }
1040
1041 if (pipeline->graphics.ps_input_cntl_num) {
1042 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1043 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1044 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1045 }
1046 }
1047 }
1048
1049 static void
1050 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1051 struct radv_pipeline *pipeline)
1052 {
1053 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1054
1055 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1056 return;
1057
1058 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1059 pipeline->graphics.vtx_reuse_depth);
1060 }
1061
1062 static void
1063 radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
1064 struct radv_pipeline *pipeline)
1065 {
1066 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
1069 return;
1070
1071 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
1072 pipeline->graphics.bin.pa_sc_binner_cntl_0);
1073 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
1074 pipeline->graphics.bin.db_dfsm_control);
1075 }
1076
1077 static void
1078 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1079 {
1080 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1081
1082 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1083 return;
1084
1085 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1086 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1087 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1088 radv_update_multisample_state(cmd_buffer, pipeline);
1089 radv_emit_vertex_shader(cmd_buffer, pipeline);
1090 radv_emit_tess_shaders(cmd_buffer, pipeline);
1091 radv_emit_geometry_shader(cmd_buffer, pipeline);
1092 radv_emit_fragment_shader(cmd_buffer, pipeline);
1093 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1094 radv_emit_binning_state(cmd_buffer, pipeline);
1095
1096 cmd_buffer->scratch_size_needed =
1097 MAX2(cmd_buffer->scratch_size_needed,
1098 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1099
1100 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1101 S_0286E8_WAVES(pipeline->max_waves) |
1102 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1103
1104 if (!cmd_buffer->state.emitted_pipeline ||
1105 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1106 pipeline->graphics.can_use_guardband)
1107 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1108
1109 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1110
1111 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1112 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1113 } else {
1114 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1115 }
1116 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1117
1118 radeon_set_context_reg(cmd_buffer->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
1119
1120 if (unlikely(cmd_buffer->device->trace_bo))
1121 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1122
1123 cmd_buffer->state.emitted_pipeline = pipeline;
1124
1125 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1126 }
1127
1128 static void
1129 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1130 {
1131 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1132 cmd_buffer->state.dynamic.viewport.viewports);
1133 }
1134
1135 static void
1136 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1137 {
1138 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1139
1140 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1141 * scissor registers are changed. There is also a more efficient but
1142 * more involved alternative workaround.
1143 */
1144 if (cmd_buffer->device->physical_device->has_scissor_bug) {
1145 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1146 si_emit_cache_flush(cmd_buffer);
1147 }
1148 si_write_scissors(cmd_buffer->cs, 0, count,
1149 cmd_buffer->state.dynamic.scissor.scissors,
1150 cmd_buffer->state.dynamic.viewport.viewports,
1151 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1152 }
1153
1154 static void
1155 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1156 {
1157 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1158 return;
1159
1160 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1161 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1162 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1163 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1164 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1165 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1166 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1167 }
1168 }
1169
1170 static void
1171 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1172 {
1173 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1174
1175 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1176 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1177 }
1178
1179 static void
1180 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1181 {
1182 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1183
1184 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1185 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1186 }
1187
1188 static void
1189 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1190 {
1191 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1192
1193 radeon_set_context_reg_seq(cmd_buffer->cs,
1194 R_028430_DB_STENCILREFMASK, 2);
1195 radeon_emit(cmd_buffer->cs,
1196 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1197 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1198 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1199 S_028430_STENCILOPVAL(1));
1200 radeon_emit(cmd_buffer->cs,
1201 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1202 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1203 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1204 S_028434_STENCILOPVAL_BF(1));
1205 }
1206
1207 static void
1208 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1209 {
1210 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1211
1212 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1213 fui(d->depth_bounds.min));
1214 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1215 fui(d->depth_bounds.max));
1216 }
1217
1218 static void
1219 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1220 {
1221 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1222 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1223 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1224 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1225
1226 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1227 radeon_set_context_reg_seq(cmd_buffer->cs,
1228 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1229 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1230 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1231 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1232 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1233 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1234 }
1235 }
1236
1237 static void
1238 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1239 int index,
1240 struct radv_attachment_info *att,
1241 struct radv_image *image,
1242 VkImageLayout layout)
1243 {
1244 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1245 struct radv_color_buffer_info *cb = &att->cb;
1246 uint32_t cb_color_info = cb->cb_color_info;
1247
1248 if (!radv_layout_dcc_compressed(image, layout,
1249 radv_image_queue_family_mask(image,
1250 cmd_buffer->queue_family_index,
1251 cmd_buffer->queue_family_index))) {
1252 cb_color_info &= C_028C70_DCC_ENABLE;
1253 }
1254
1255 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1256 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1257 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1258 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1259 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1260 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1261 radeon_emit(cmd_buffer->cs, cb_color_info);
1262 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1263 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1264 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1265 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1266 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1267 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1268
1269 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1270 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1271 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1272
1273 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1274 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1275 } else {
1276 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1281 radeon_emit(cmd_buffer->cs, cb_color_info);
1282 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1283 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1284 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1285 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1286 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1288
1289 if (is_vi) { /* DCC BASE */
1290 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1291 }
1292 }
1293 }
1294
1295 static void
1296 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_ds_buffer_info *ds,
1298 struct radv_image *image,
1299 VkImageLayout layout)
1300 {
1301 uint32_t db_z_info = ds->db_z_info;
1302 uint32_t db_stencil_info = ds->db_stencil_info;
1303
1304 if (!radv_layout_has_htile(image, layout,
1305 radv_image_queue_family_mask(image,
1306 cmd_buffer->queue_family_index,
1307 cmd_buffer->queue_family_index))) {
1308 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1309 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1310 }
1311
1312 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1313 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1314
1315
1316 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1317 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1318 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1319 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1320 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1321
1322 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1323 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1324 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1325 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1326 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1327 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1328 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1329 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1330 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1331 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1332 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1333
1334 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1335 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1336 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1337 } else {
1338 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1339
1340 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1341 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1342 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1343 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1344 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1345 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1346 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1347 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1348 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1349 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1350
1351 }
1352
1353 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1354 ds->pa_su_poly_offset_db_fmt_cntl);
1355 }
1356
1357 void
1358 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1359 struct radv_image *image,
1360 VkClearDepthStencilValue ds_clear_value,
1361 VkImageAspectFlags aspects)
1362 {
1363 uint64_t va = radv_buffer_get_va(image->bo);
1364 va += image->offset + image->clear_value_offset;
1365 unsigned reg_offset = 0, reg_count = 0;
1366
1367 assert(image->surface.htile_size);
1368
1369 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1370 ++reg_count;
1371 } else {
1372 ++reg_offset;
1373 va += 4;
1374 }
1375 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1376 ++reg_count;
1377
1378 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1379 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1380 S_370_WR_CONFIRM(1) |
1381 S_370_ENGINE_SEL(V_370_PFP));
1382 radeon_emit(cmd_buffer->cs, va);
1383 radeon_emit(cmd_buffer->cs, va >> 32);
1384 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1385 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1386 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1387 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1388
1389 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1390 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1391 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1392 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1393 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1394 }
1395
1396 static void
1397 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1398 struct radv_image *image)
1399 {
1400 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1401 uint64_t va = radv_buffer_get_va(image->bo);
1402 va += image->offset + image->clear_value_offset;
1403 unsigned reg_offset = 0, reg_count = 0;
1404
1405 if (!image->surface.htile_size)
1406 return;
1407
1408 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1409 ++reg_count;
1410 } else {
1411 ++reg_offset;
1412 va += 4;
1413 }
1414 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1415 ++reg_count;
1416
1417 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1418 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1419 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1420 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1421 radeon_emit(cmd_buffer->cs, va);
1422 radeon_emit(cmd_buffer->cs, va >> 32);
1423 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1424 radeon_emit(cmd_buffer->cs, 0);
1425
1426 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1427 radeon_emit(cmd_buffer->cs, 0);
1428 }
1429
1430 /*
1431 *with DCC some colors don't require CMASK elimiation before being
1432 * used as a texture. This sets a predicate value to determine if the
1433 * cmask eliminate is required.
1434 */
1435 void
1436 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1437 struct radv_image *image,
1438 bool value)
1439 {
1440 uint64_t pred_val = value;
1441 uint64_t va = radv_buffer_get_va(image->bo);
1442 va += image->offset + image->dcc_pred_offset;
1443
1444 assert(image->surface.dcc_size);
1445
1446 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1447 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1448 S_370_WR_CONFIRM(1) |
1449 S_370_ENGINE_SEL(V_370_PFP));
1450 radeon_emit(cmd_buffer->cs, va);
1451 radeon_emit(cmd_buffer->cs, va >> 32);
1452 radeon_emit(cmd_buffer->cs, pred_val);
1453 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1454 }
1455
1456 void
1457 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1458 struct radv_image *image,
1459 int idx,
1460 uint32_t color_values[2])
1461 {
1462 uint64_t va = radv_buffer_get_va(image->bo);
1463 va += image->offset + image->clear_value_offset;
1464
1465 assert(image->cmask.size || image->surface.dcc_size);
1466
1467 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1468 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1469 S_370_WR_CONFIRM(1) |
1470 S_370_ENGINE_SEL(V_370_PFP));
1471 radeon_emit(cmd_buffer->cs, va);
1472 radeon_emit(cmd_buffer->cs, va >> 32);
1473 radeon_emit(cmd_buffer->cs, color_values[0]);
1474 radeon_emit(cmd_buffer->cs, color_values[1]);
1475
1476 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1477 radeon_emit(cmd_buffer->cs, color_values[0]);
1478 radeon_emit(cmd_buffer->cs, color_values[1]);
1479 }
1480
1481 static void
1482 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1483 struct radv_image *image,
1484 int idx)
1485 {
1486 uint64_t va = radv_buffer_get_va(image->bo);
1487 va += image->offset + image->clear_value_offset;
1488
1489 if (!image->cmask.size && !image->surface.dcc_size)
1490 return;
1491
1492 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1493
1494 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1495 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1496 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1497 COPY_DATA_COUNT_SEL);
1498 radeon_emit(cmd_buffer->cs, va);
1499 radeon_emit(cmd_buffer->cs, va >> 32);
1500 radeon_emit(cmd_buffer->cs, reg >> 2);
1501 radeon_emit(cmd_buffer->cs, 0);
1502
1503 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1504 radeon_emit(cmd_buffer->cs, 0);
1505 }
1506
1507 static void
1508 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1509 {
1510 int i;
1511 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1512 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1513
1514 /* this may happen for inherited secondary recording */
1515 if (!framebuffer)
1516 return;
1517
1518 for (i = 0; i < 8; ++i) {
1519 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1520 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1521 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1522 continue;
1523 }
1524
1525 int idx = subpass->color_attachments[i].attachment;
1526 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1527 struct radv_image *image = att->attachment->image;
1528 VkImageLayout layout = subpass->color_attachments[i].layout;
1529
1530 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1531
1532 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1533 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1534
1535 radv_load_color_clear_regs(cmd_buffer, image, i);
1536 }
1537
1538 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1539 int idx = subpass->depth_stencil_attachment.attachment;
1540 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1541 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1542 struct radv_image *image = att->attachment->image;
1543 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1544 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1545 cmd_buffer->queue_family_index,
1546 cmd_buffer->queue_family_index);
1547 /* We currently don't support writing decompressed HTILE */
1548 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1549 radv_layout_is_htile_compressed(image, layout, queue_mask));
1550
1551 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1552
1553 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1554 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1555 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1556 }
1557 radv_load_depth_clear_regs(cmd_buffer, image);
1558 } else {
1559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1560 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1561 else
1562 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1563
1564 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1565 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1566 }
1567 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1568 S_028208_BR_X(framebuffer->width) |
1569 S_028208_BR_Y(framebuffer->height));
1570
1571 if (cmd_buffer->device->dfsm_allowed) {
1572 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1573 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1574 }
1575
1576 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1577 }
1578
1579 static void
1580 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1581 {
1582 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1583 struct radv_cmd_state *state = &cmd_buffer->state;
1584
1585 if (state->index_type != state->last_index_type) {
1586 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1587 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1588 2, state->index_type);
1589 } else {
1590 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1591 radeon_emit(cs, state->index_type);
1592 }
1593
1594 state->last_index_type = state->index_type;
1595 }
1596
1597 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1598 radeon_emit(cs, state->index_va);
1599 radeon_emit(cs, state->index_va >> 32);
1600
1601 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1602 radeon_emit(cs, state->max_index_count);
1603
1604 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1605 }
1606
1607 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1608 {
1609 uint32_t db_count_control;
1610
1611 if(!cmd_buffer->state.active_occlusion_queries) {
1612 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1613 db_count_control = 0;
1614 } else {
1615 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1616 }
1617 } else {
1618 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1619 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1620 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1621 S_028004_ZPASS_ENABLE(1) |
1622 S_028004_SLICE_EVEN_ENABLE(1) |
1623 S_028004_SLICE_ODD_ENABLE(1);
1624 } else {
1625 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1626 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1627 }
1628 }
1629
1630 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1631 }
1632
1633 static void
1634 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1635 {
1636 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1637 return;
1638
1639 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1640 radv_emit_viewport(cmd_buffer);
1641
1642 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1643 radv_emit_scissor(cmd_buffer);
1644
1645 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1646 radv_emit_line_width(cmd_buffer);
1647
1648 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1649 radv_emit_blend_constants(cmd_buffer);
1650
1651 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1652 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1653 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1654 radv_emit_stencil(cmd_buffer);
1655
1656 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1657 radv_emit_depth_bounds(cmd_buffer);
1658
1659 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1660 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1661 radv_emit_depth_bias(cmd_buffer);
1662
1663 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1664 radv_emit_discard_rectangle(cmd_buffer);
1665
1666 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1667 }
1668
1669 static void
1670 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1671 struct radv_pipeline *pipeline,
1672 int idx,
1673 uint64_t va,
1674 gl_shader_stage stage)
1675 {
1676 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1677 uint32_t base_reg = pipeline->user_data_0[stage];
1678
1679 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1680 return;
1681
1682 assert(!desc_set_loc->indirect);
1683 assert(desc_set_loc->num_sgprs == 2);
1684 radeon_set_sh_reg_seq(cmd_buffer->cs,
1685 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1686 radeon_emit(cmd_buffer->cs, va);
1687 radeon_emit(cmd_buffer->cs, va >> 32);
1688 }
1689
1690 static void
1691 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1692 VkShaderStageFlags stages,
1693 struct radv_descriptor_set *set,
1694 unsigned idx)
1695 {
1696 if (cmd_buffer->state.pipeline) {
1697 radv_foreach_stage(stage, stages) {
1698 if (cmd_buffer->state.pipeline->shaders[stage])
1699 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1700 idx, set->va,
1701 stage);
1702 }
1703 }
1704
1705 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1706 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1707 idx, set->va,
1708 MESA_SHADER_COMPUTE);
1709 }
1710
1711 static void
1712 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1713 {
1714 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1715 unsigned bo_offset;
1716
1717 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1718 set->mapped_ptr,
1719 &bo_offset))
1720 return;
1721
1722 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1723 set->va += bo_offset;
1724 }
1725
1726 static void
1727 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1728 {
1729 uint32_t size = MAX_SETS * 2 * 4;
1730 uint32_t offset;
1731 void *ptr;
1732
1733 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1734 256, &offset, &ptr))
1735 return;
1736
1737 for (unsigned i = 0; i < MAX_SETS; i++) {
1738 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1739 uint64_t set_va = 0;
1740 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1741 if (cmd_buffer->state.valid_descriptors & (1u << i))
1742 set_va = set->va;
1743 uptr[0] = set_va & 0xffffffff;
1744 uptr[1] = set_va >> 32;
1745 }
1746
1747 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1748 va += offset;
1749
1750 if (cmd_buffer->state.pipeline) {
1751 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1752 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1753 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1754
1755 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1756 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1757 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1758
1759 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1760 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1761 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1762
1763 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1764 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1765 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1766
1767 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1768 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1769 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1770 }
1771
1772 if (cmd_buffer->state.compute_pipeline)
1773 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1774 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1775 }
1776
1777 static void
1778 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1779 VkShaderStageFlags stages)
1780 {
1781 unsigned i;
1782
1783 if (!cmd_buffer->state.descriptors_dirty)
1784 return;
1785
1786 if (cmd_buffer->state.push_descriptors_dirty)
1787 radv_flush_push_descriptors(cmd_buffer);
1788
1789 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1790 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1791 radv_flush_indirect_descriptor_sets(cmd_buffer);
1792 }
1793
1794 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1795 cmd_buffer->cs,
1796 MAX_SETS * MESA_SHADER_STAGES * 4);
1797
1798 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1799 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1800 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1801 continue;
1802
1803 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1804 }
1805 cmd_buffer->state.descriptors_dirty = 0;
1806 cmd_buffer->state.push_descriptors_dirty = false;
1807
1808 if (unlikely(cmd_buffer->device->trace_bo))
1809 radv_save_descriptors(cmd_buffer);
1810
1811 assert(cmd_buffer->cs->cdw <= cdw_max);
1812 }
1813
1814 static void
1815 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1816 struct radv_pipeline *pipeline,
1817 VkShaderStageFlags stages)
1818 {
1819 struct radv_pipeline_layout *layout = pipeline->layout;
1820 unsigned offset;
1821 void *ptr;
1822 uint64_t va;
1823
1824 stages &= cmd_buffer->push_constant_stages;
1825 if (!stages ||
1826 (!layout->push_constant_size && !layout->dynamic_offset_count))
1827 return;
1828
1829 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1830 16 * layout->dynamic_offset_count,
1831 256, &offset, &ptr))
1832 return;
1833
1834 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1835 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1836 16 * layout->dynamic_offset_count);
1837
1838 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1839 va += offset;
1840
1841 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1842 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1843
1844 radv_foreach_stage(stage, stages) {
1845 if (pipeline->shaders[stage]) {
1846 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1847 AC_UD_PUSH_CONSTANTS, va);
1848 }
1849 }
1850
1851 cmd_buffer->push_constant_stages &= ~stages;
1852 assert(cmd_buffer->cs->cdw <= cdw_max);
1853 }
1854
1855 static bool
1856 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1857 {
1858 if ((pipeline_is_dirty ||
1859 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1860 cmd_buffer->state.pipeline->vertex_elements.count &&
1861 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1862 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1863 unsigned vb_offset;
1864 void *vb_ptr;
1865 uint32_t i = 0;
1866 uint32_t count = velems->count;
1867 uint64_t va;
1868
1869 /* allocate some descriptor state for vertex buffers */
1870 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1871 &vb_offset, &vb_ptr))
1872 return false;
1873
1874 for (i = 0; i < count; i++) {
1875 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1876 uint32_t offset;
1877 int vb = velems->binding[i];
1878 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1879 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1880
1881 va = radv_buffer_get_va(buffer->bo);
1882
1883 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1884 va += offset + buffer->offset;
1885 desc[0] = va;
1886 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1887 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1888 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1889 else
1890 desc[2] = buffer->size - offset;
1891 desc[3] = velems->rsrc_word3[i];
1892 }
1893
1894 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1895 va += vb_offset;
1896
1897 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1898 AC_UD_VS_VERTEX_BUFFERS, va);
1899
1900 cmd_buffer->state.vb_va = va;
1901 cmd_buffer->state.vb_size = count * 16;
1902 cmd_buffer->state.vb_prefetch_dirty = true;
1903 }
1904 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1905
1906 return true;
1907 }
1908
1909 static bool
1910 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1911 {
1912 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1913 return false;
1914
1915 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1916 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1917 VK_SHADER_STAGE_ALL_GRAPHICS);
1918
1919 return true;
1920 }
1921
1922 static void
1923 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1924 bool instanced_draw, bool indirect_draw,
1925 uint32_t draw_vertex_count)
1926 {
1927 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1928 struct radv_cmd_state *state = &cmd_buffer->state;
1929 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1930 uint32_t ia_multi_vgt_param;
1931 int32_t primitive_reset_en;
1932
1933 /* Draw state. */
1934 ia_multi_vgt_param =
1935 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1936 indirect_draw, draw_vertex_count);
1937
1938 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1939 if (info->chip_class >= GFX9) {
1940 radeon_set_uconfig_reg_idx(cs,
1941 R_030960_IA_MULTI_VGT_PARAM,
1942 4, ia_multi_vgt_param);
1943 } else if (info->chip_class >= CIK) {
1944 radeon_set_context_reg_idx(cs,
1945 R_028AA8_IA_MULTI_VGT_PARAM,
1946 1, ia_multi_vgt_param);
1947 } else {
1948 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1949 ia_multi_vgt_param);
1950 }
1951 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1952 }
1953
1954 /* Primitive restart. */
1955 primitive_reset_en =
1956 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1957
1958 if (primitive_reset_en != state->last_primitive_reset_en) {
1959 state->last_primitive_reset_en = primitive_reset_en;
1960 if (info->chip_class >= GFX9) {
1961 radeon_set_uconfig_reg(cs,
1962 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1963 primitive_reset_en);
1964 } else {
1965 radeon_set_context_reg(cs,
1966 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1967 primitive_reset_en);
1968 }
1969 }
1970
1971 if (primitive_reset_en) {
1972 uint32_t primitive_reset_index =
1973 state->index_type ? 0xffffffffu : 0xffffu;
1974
1975 if (primitive_reset_index != state->last_primitive_reset_index) {
1976 radeon_set_context_reg(cs,
1977 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1978 primitive_reset_index);
1979 state->last_primitive_reset_index = primitive_reset_index;
1980 }
1981 }
1982 }
1983
1984 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1985 VkPipelineStageFlags src_stage_mask)
1986 {
1987 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1988 VK_PIPELINE_STAGE_TRANSFER_BIT |
1989 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1990 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1991 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1992 }
1993
1994 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1995 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1996 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1997 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1998 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1999 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2000 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2001 VK_PIPELINE_STAGE_TRANSFER_BIT |
2002 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2003 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2004 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2005 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2006 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2007 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2008 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
2009 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2010 }
2011 }
2012
2013 static enum radv_cmd_flush_bits
2014 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2015 VkAccessFlags src_flags)
2016 {
2017 enum radv_cmd_flush_bits flush_bits = 0;
2018 uint32_t b;
2019 for_each_bit(b, src_flags) {
2020 switch ((VkAccessFlagBits)(1 << b)) {
2021 case VK_ACCESS_SHADER_WRITE_BIT:
2022 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2023 break;
2024 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2025 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2026 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2027 break;
2028 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2029 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2030 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2031 break;
2032 case VK_ACCESS_TRANSFER_WRITE_BIT:
2033 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2034 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2035 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2036 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2037 RADV_CMD_FLAG_INV_GLOBAL_L2;
2038 break;
2039 default:
2040 break;
2041 }
2042 }
2043 return flush_bits;
2044 }
2045
2046 static enum radv_cmd_flush_bits
2047 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2048 VkAccessFlags dst_flags,
2049 struct radv_image *image)
2050 {
2051 enum radv_cmd_flush_bits flush_bits = 0;
2052 uint32_t b;
2053 for_each_bit(b, dst_flags) {
2054 switch ((VkAccessFlagBits)(1 << b)) {
2055 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2056 case VK_ACCESS_INDEX_READ_BIT:
2057 break;
2058 case VK_ACCESS_UNIFORM_READ_BIT:
2059 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2060 break;
2061 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2062 case VK_ACCESS_SHADER_READ_BIT:
2063 case VK_ACCESS_TRANSFER_READ_BIT:
2064 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2065 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2066 RADV_CMD_FLAG_INV_GLOBAL_L2;
2067 break;
2068 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2069 /* TODO: change to image && when the image gets passed
2070 * through from the subpass. */
2071 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2072 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2073 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2074 break;
2075 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2076 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2077 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2078 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2079 break;
2080 default:
2081 break;
2082 }
2083 }
2084 return flush_bits;
2085 }
2086
2087 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2088 {
2089 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2090 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2091 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2092 NULL);
2093 }
2094
2095 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2096 VkAttachmentReference att)
2097 {
2098 unsigned idx = att.attachment;
2099 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2100 VkImageSubresourceRange range;
2101 range.aspectMask = 0;
2102 range.baseMipLevel = view->base_mip;
2103 range.levelCount = 1;
2104 range.baseArrayLayer = view->base_layer;
2105 range.layerCount = cmd_buffer->state.framebuffer->layers;
2106
2107 radv_handle_image_transition(cmd_buffer,
2108 view->image,
2109 cmd_buffer->state.attachments[idx].current_layout,
2110 att.layout, 0, 0, &range,
2111 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2112
2113 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2114
2115
2116 }
2117
2118 void
2119 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2120 const struct radv_subpass *subpass, bool transitions)
2121 {
2122 if (transitions) {
2123 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2124
2125 for (unsigned i = 0; i < subpass->color_count; ++i) {
2126 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2127 radv_handle_subpass_image_transition(cmd_buffer,
2128 subpass->color_attachments[i]);
2129 }
2130
2131 for (unsigned i = 0; i < subpass->input_count; ++i) {
2132 radv_handle_subpass_image_transition(cmd_buffer,
2133 subpass->input_attachments[i]);
2134 }
2135
2136 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2137 radv_handle_subpass_image_transition(cmd_buffer,
2138 subpass->depth_stencil_attachment);
2139 }
2140 }
2141
2142 cmd_buffer->state.subpass = subpass;
2143
2144 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2145 }
2146
2147 static VkResult
2148 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2149 struct radv_render_pass *pass,
2150 const VkRenderPassBeginInfo *info)
2151 {
2152 struct radv_cmd_state *state = &cmd_buffer->state;
2153
2154 if (pass->attachment_count == 0) {
2155 state->attachments = NULL;
2156 return VK_SUCCESS;
2157 }
2158
2159 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2160 pass->attachment_count *
2161 sizeof(state->attachments[0]),
2162 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2163 if (state->attachments == NULL) {
2164 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2165 return cmd_buffer->record_result;
2166 }
2167
2168 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2169 struct radv_render_pass_attachment *att = &pass->attachments[i];
2170 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2171 VkImageAspectFlags clear_aspects = 0;
2172
2173 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2174 /* color attachment */
2175 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2176 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2177 }
2178 } else {
2179 /* depthstencil attachment */
2180 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2181 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2182 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2183 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2184 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2185 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2186 }
2187 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2188 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2189 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2190 }
2191 }
2192
2193 state->attachments[i].pending_clear_aspects = clear_aspects;
2194 state->attachments[i].cleared_views = 0;
2195 if (clear_aspects && info) {
2196 assert(info->clearValueCount > i);
2197 state->attachments[i].clear_value = info->pClearValues[i];
2198 }
2199
2200 state->attachments[i].current_layout = att->initial_layout;
2201 }
2202
2203 return VK_SUCCESS;
2204 }
2205
2206 VkResult radv_AllocateCommandBuffers(
2207 VkDevice _device,
2208 const VkCommandBufferAllocateInfo *pAllocateInfo,
2209 VkCommandBuffer *pCommandBuffers)
2210 {
2211 RADV_FROM_HANDLE(radv_device, device, _device);
2212 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2213
2214 VkResult result = VK_SUCCESS;
2215 uint32_t i;
2216
2217 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2218
2219 if (!list_empty(&pool->free_cmd_buffers)) {
2220 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2221
2222 list_del(&cmd_buffer->pool_link);
2223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2224
2225 result = radv_reset_cmd_buffer(cmd_buffer);
2226 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2227 cmd_buffer->level = pAllocateInfo->level;
2228
2229 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2230 } else {
2231 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2232 &pCommandBuffers[i]);
2233 }
2234 if (result != VK_SUCCESS)
2235 break;
2236 }
2237
2238 if (result != VK_SUCCESS) {
2239 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2240 i, pCommandBuffers);
2241
2242 /* From the Vulkan 1.0.66 spec:
2243 *
2244 * "vkAllocateCommandBuffers can be used to create multiple
2245 * command buffers. If the creation of any of those command
2246 * buffers fails, the implementation must destroy all
2247 * successfully created command buffer objects from this
2248 * command, set all entries of the pCommandBuffers array to
2249 * NULL and return the error."
2250 */
2251 memset(pCommandBuffers, 0,
2252 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2253 }
2254
2255 return result;
2256 }
2257
2258 void radv_FreeCommandBuffers(
2259 VkDevice device,
2260 VkCommandPool commandPool,
2261 uint32_t commandBufferCount,
2262 const VkCommandBuffer *pCommandBuffers)
2263 {
2264 for (uint32_t i = 0; i < commandBufferCount; i++) {
2265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2266
2267 if (cmd_buffer) {
2268 if (cmd_buffer->pool) {
2269 list_del(&cmd_buffer->pool_link);
2270 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2271 } else
2272 radv_cmd_buffer_destroy(cmd_buffer);
2273
2274 }
2275 }
2276 }
2277
2278 VkResult radv_ResetCommandBuffer(
2279 VkCommandBuffer commandBuffer,
2280 VkCommandBufferResetFlags flags)
2281 {
2282 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2283 return radv_reset_cmd_buffer(cmd_buffer);
2284 }
2285
2286 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2287 {
2288 struct radv_device *device = cmd_buffer->device;
2289 if (device->gfx_init) {
2290 uint64_t va = radv_buffer_get_va(device->gfx_init);
2291 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2292 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2293 radeon_emit(cmd_buffer->cs, va);
2294 radeon_emit(cmd_buffer->cs, va >> 32);
2295 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2296 } else
2297 si_init_config(cmd_buffer);
2298 }
2299
2300 VkResult radv_BeginCommandBuffer(
2301 VkCommandBuffer commandBuffer,
2302 const VkCommandBufferBeginInfo *pBeginInfo)
2303 {
2304 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2305 VkResult result = VK_SUCCESS;
2306
2307 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2308 /* If the command buffer has already been resetted with
2309 * vkResetCommandBuffer, no need to do it again.
2310 */
2311 result = radv_reset_cmd_buffer(cmd_buffer);
2312 if (result != VK_SUCCESS)
2313 return result;
2314 }
2315
2316 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2317 cmd_buffer->state.last_primitive_reset_en = -1;
2318 cmd_buffer->state.last_index_type = -1;
2319 cmd_buffer->state.last_num_instances = -1;
2320 cmd_buffer->state.last_vertex_offset = -1;
2321 cmd_buffer->state.last_first_instance = -1;
2322 cmd_buffer->usage_flags = pBeginInfo->flags;
2323
2324 /* setup initial configuration into command buffer */
2325 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2326 switch (cmd_buffer->queue_family_index) {
2327 case RADV_QUEUE_GENERAL:
2328 emit_gfx_buffer_state(cmd_buffer);
2329 break;
2330 case RADV_QUEUE_COMPUTE:
2331 si_init_compute(cmd_buffer);
2332 break;
2333 case RADV_QUEUE_TRANSFER:
2334 default:
2335 break;
2336 }
2337 }
2338
2339 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2340 assert(pBeginInfo->pInheritanceInfo);
2341 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2342 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2343
2344 struct radv_subpass *subpass =
2345 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2346
2347 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2348 if (result != VK_SUCCESS)
2349 return result;
2350
2351 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2352 }
2353
2354 if (unlikely(cmd_buffer->device->trace_bo))
2355 radv_cmd_buffer_trace_emit(cmd_buffer);
2356
2357 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2358
2359 return result;
2360 }
2361
2362 void radv_CmdBindVertexBuffers(
2363 VkCommandBuffer commandBuffer,
2364 uint32_t firstBinding,
2365 uint32_t bindingCount,
2366 const VkBuffer* pBuffers,
2367 const VkDeviceSize* pOffsets)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2370 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2371 bool changed = false;
2372
2373 /* We have to defer setting up vertex buffer since we need the buffer
2374 * stride from the pipeline. */
2375
2376 assert(firstBinding + bindingCount <= MAX_VBS);
2377 for (uint32_t i = 0; i < bindingCount; i++) {
2378 uint32_t idx = firstBinding + i;
2379
2380 if (!changed &&
2381 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2382 vb[idx].offset != pOffsets[i])) {
2383 changed = true;
2384 }
2385
2386 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2387 vb[idx].offset = pOffsets[i];
2388
2389 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2390 vb[idx].buffer->bo, 8);
2391 }
2392
2393 if (!changed) {
2394 /* No state changes. */
2395 return;
2396 }
2397
2398 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2399 }
2400
2401 void radv_CmdBindIndexBuffer(
2402 VkCommandBuffer commandBuffer,
2403 VkBuffer buffer,
2404 VkDeviceSize offset,
2405 VkIndexType indexType)
2406 {
2407 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2408 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2409
2410 if (cmd_buffer->state.index_buffer == index_buffer &&
2411 cmd_buffer->state.index_offset == offset &&
2412 cmd_buffer->state.index_type == indexType) {
2413 /* No state changes. */
2414 return;
2415 }
2416
2417 cmd_buffer->state.index_buffer = index_buffer;
2418 cmd_buffer->state.index_offset = offset;
2419 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2420 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2421 cmd_buffer->state.index_va += index_buffer->offset + offset;
2422
2423 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2424 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2425 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2426 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2427 }
2428
2429
2430 static void
2431 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2432 struct radv_descriptor_set *set, unsigned idx)
2433 {
2434 struct radeon_winsys *ws = cmd_buffer->device->ws;
2435
2436 radv_set_descriptor_set(cmd_buffer, set, idx);
2437 if (!set)
2438 return;
2439
2440 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2441
2442 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2443 if (set->descriptors[j])
2444 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2445
2446 if(set->bo)
2447 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2448 }
2449
2450 void radv_CmdBindDescriptorSets(
2451 VkCommandBuffer commandBuffer,
2452 VkPipelineBindPoint pipelineBindPoint,
2453 VkPipelineLayout _layout,
2454 uint32_t firstSet,
2455 uint32_t descriptorSetCount,
2456 const VkDescriptorSet* pDescriptorSets,
2457 uint32_t dynamicOffsetCount,
2458 const uint32_t* pDynamicOffsets)
2459 {
2460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2461 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2462 unsigned dyn_idx = 0;
2463
2464 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2465 unsigned idx = i + firstSet;
2466 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2467 radv_bind_descriptor_set(cmd_buffer, set, idx);
2468
2469 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2470 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2471 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2472 assert(dyn_idx < dynamicOffsetCount);
2473
2474 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2475 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2476 dst[0] = va;
2477 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2478 dst[2] = range->size;
2479 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2480 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2481 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2482 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2483 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2484 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2485 cmd_buffer->push_constant_stages |=
2486 set->layout->dynamic_shader_stages;
2487 }
2488 }
2489 }
2490
2491 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2492 struct radv_descriptor_set *set,
2493 struct radv_descriptor_set_layout *layout)
2494 {
2495 set->size = layout->size;
2496 set->layout = layout;
2497
2498 if (cmd_buffer->push_descriptors.capacity < set->size) {
2499 size_t new_size = MAX2(set->size, 1024);
2500 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2501 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2502
2503 free(set->mapped_ptr);
2504 set->mapped_ptr = malloc(new_size);
2505
2506 if (!set->mapped_ptr) {
2507 cmd_buffer->push_descriptors.capacity = 0;
2508 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2509 return false;
2510 }
2511
2512 cmd_buffer->push_descriptors.capacity = new_size;
2513 }
2514
2515 return true;
2516 }
2517
2518 void radv_meta_push_descriptor_set(
2519 struct radv_cmd_buffer* cmd_buffer,
2520 VkPipelineBindPoint pipelineBindPoint,
2521 VkPipelineLayout _layout,
2522 uint32_t set,
2523 uint32_t descriptorWriteCount,
2524 const VkWriteDescriptorSet* pDescriptorWrites)
2525 {
2526 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2527 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2528 unsigned bo_offset;
2529
2530 assert(set == 0);
2531 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2532
2533 push_set->size = layout->set[set].layout->size;
2534 push_set->layout = layout->set[set].layout;
2535
2536 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2537 &bo_offset,
2538 (void**) &push_set->mapped_ptr))
2539 return;
2540
2541 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2542 push_set->va += bo_offset;
2543
2544 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2545 radv_descriptor_set_to_handle(push_set),
2546 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2547
2548 radv_set_descriptor_set(cmd_buffer, push_set, set);
2549 }
2550
2551 void radv_CmdPushDescriptorSetKHR(
2552 VkCommandBuffer commandBuffer,
2553 VkPipelineBindPoint pipelineBindPoint,
2554 VkPipelineLayout _layout,
2555 uint32_t set,
2556 uint32_t descriptorWriteCount,
2557 const VkWriteDescriptorSet* pDescriptorWrites)
2558 {
2559 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2560 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2561 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2562
2563 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2564
2565 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2566 return;
2567
2568 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2569 radv_descriptor_set_to_handle(push_set),
2570 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2571
2572 radv_set_descriptor_set(cmd_buffer, push_set, set);
2573 cmd_buffer->state.push_descriptors_dirty = true;
2574 }
2575
2576 void radv_CmdPushDescriptorSetWithTemplateKHR(
2577 VkCommandBuffer commandBuffer,
2578 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2579 VkPipelineLayout _layout,
2580 uint32_t set,
2581 const void* pData)
2582 {
2583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2585 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2586
2587 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2588
2589 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2590 return;
2591
2592 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2593 descriptorUpdateTemplate, pData);
2594
2595 radv_set_descriptor_set(cmd_buffer, push_set, set);
2596 cmd_buffer->state.push_descriptors_dirty = true;
2597 }
2598
2599 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2600 VkPipelineLayout layout,
2601 VkShaderStageFlags stageFlags,
2602 uint32_t offset,
2603 uint32_t size,
2604 const void* pValues)
2605 {
2606 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2607 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2608 cmd_buffer->push_constant_stages |= stageFlags;
2609 }
2610
2611 VkResult radv_EndCommandBuffer(
2612 VkCommandBuffer commandBuffer)
2613 {
2614 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2615
2616 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2617 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2618 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2619 si_emit_cache_flush(cmd_buffer);
2620 }
2621
2622 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2623
2624 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2625 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2626
2627 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2628
2629 return cmd_buffer->record_result;
2630 }
2631
2632 static void
2633 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2634 {
2635 struct radv_shader_variant *compute_shader;
2636 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2637 struct radv_device *device = cmd_buffer->device;
2638 unsigned compute_resource_limits;
2639 unsigned waves_per_threadgroup;
2640 uint64_t va;
2641
2642 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2643 return;
2644
2645 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2646
2647 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2648 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2649
2650 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2651 cmd_buffer->cs, 19);
2652
2653 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2654 radeon_emit(cmd_buffer->cs, va >> 8);
2655 radeon_emit(cmd_buffer->cs, va >> 40);
2656
2657 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2658 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2659 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2660
2661
2662 cmd_buffer->compute_scratch_size_needed =
2663 MAX2(cmd_buffer->compute_scratch_size_needed,
2664 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2665
2666 /* change these once we have scratch support */
2667 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2668 S_00B860_WAVES(pipeline->max_waves) |
2669 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2670
2671 /* Calculate best compute resource limits. */
2672 waves_per_threadgroup =
2673 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2674 compute_shader->info.cs.block_size[1] *
2675 compute_shader->info.cs.block_size[2], 64);
2676 compute_resource_limits =
2677 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2678
2679 if (device->physical_device->rad_info.chip_class >= CIK) {
2680 unsigned num_cu_per_se =
2681 device->physical_device->rad_info.num_good_compute_units /
2682 device->physical_device->rad_info.max_se;
2683
2684 /* Force even distribution on all SIMDs in CU if the workgroup
2685 * size is 64. This has shown some good improvements if # of
2686 * CUs per SE is not a multiple of 4.
2687 */
2688 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2689 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2690 }
2691
2692 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2693 compute_resource_limits);
2694
2695 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2696 radeon_emit(cmd_buffer->cs,
2697 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2698 radeon_emit(cmd_buffer->cs,
2699 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2700 radeon_emit(cmd_buffer->cs,
2701 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2702
2703 assert(cmd_buffer->cs->cdw <= cdw_max);
2704
2705 if (unlikely(cmd_buffer->device->trace_bo))
2706 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2707 }
2708
2709 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2710 {
2711 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2712 }
2713
2714 void radv_CmdBindPipeline(
2715 VkCommandBuffer commandBuffer,
2716 VkPipelineBindPoint pipelineBindPoint,
2717 VkPipeline _pipeline)
2718 {
2719 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2720 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2721
2722 switch (pipelineBindPoint) {
2723 case VK_PIPELINE_BIND_POINT_COMPUTE:
2724 if (cmd_buffer->state.compute_pipeline == pipeline)
2725 return;
2726 radv_mark_descriptor_sets_dirty(cmd_buffer);
2727
2728 cmd_buffer->state.compute_pipeline = pipeline;
2729 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2730 break;
2731 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2732 if (cmd_buffer->state.pipeline == pipeline)
2733 return;
2734 radv_mark_descriptor_sets_dirty(cmd_buffer);
2735
2736 cmd_buffer->state.pipeline = pipeline;
2737 if (!pipeline)
2738 break;
2739
2740 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2741 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2742
2743 /* the new vertex shader might not have the same user regs */
2744 cmd_buffer->state.last_first_instance = -1;
2745 cmd_buffer->state.last_vertex_offset = -1;
2746
2747 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2748
2749 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2750 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2751 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2752 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2753
2754 if (radv_pipeline_has_tess(pipeline))
2755 cmd_buffer->tess_rings_needed = true;
2756
2757 if (radv_pipeline_has_gs(pipeline)) {
2758 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2759 AC_UD_SCRATCH_RING_OFFSETS);
2760 if (cmd_buffer->ring_offsets_idx == -1)
2761 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2762 else if (loc->sgpr_idx != -1)
2763 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2764 }
2765 break;
2766 default:
2767 assert(!"invalid bind point");
2768 break;
2769 }
2770 }
2771
2772 void radv_CmdSetViewport(
2773 VkCommandBuffer commandBuffer,
2774 uint32_t firstViewport,
2775 uint32_t viewportCount,
2776 const VkViewport* pViewports)
2777 {
2778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2779 struct radv_cmd_state *state = &cmd_buffer->state;
2780 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2781
2782 assert(firstViewport < MAX_VIEWPORTS);
2783 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2784
2785 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2786 /* Try to skip unnecessary PS partial flushes when the viewports
2787 * don't change.
2788 */
2789 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2790 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2791 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2792 pViewports, viewportCount * sizeof(*pViewports))) {
2793 return;
2794 }
2795 }
2796
2797 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2798 viewportCount * sizeof(*pViewports));
2799
2800 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2801 }
2802
2803 void radv_CmdSetScissor(
2804 VkCommandBuffer commandBuffer,
2805 uint32_t firstScissor,
2806 uint32_t scissorCount,
2807 const VkRect2D* pScissors)
2808 {
2809 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2810 struct radv_cmd_state *state = &cmd_buffer->state;
2811 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2812
2813 assert(firstScissor < MAX_SCISSORS);
2814 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2815
2816 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2817 /* Try to skip unnecessary PS partial flushes when the scissors
2818 * don't change.
2819 */
2820 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2821 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2822 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2823 pScissors, scissorCount * sizeof(*pScissors))) {
2824 return;
2825 }
2826 }
2827
2828 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2829 scissorCount * sizeof(*pScissors));
2830
2831 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2832 }
2833
2834 void radv_CmdSetLineWidth(
2835 VkCommandBuffer commandBuffer,
2836 float lineWidth)
2837 {
2838 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2839 cmd_buffer->state.dynamic.line_width = lineWidth;
2840 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2841 }
2842
2843 void radv_CmdSetDepthBias(
2844 VkCommandBuffer commandBuffer,
2845 float depthBiasConstantFactor,
2846 float depthBiasClamp,
2847 float depthBiasSlopeFactor)
2848 {
2849 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2850
2851 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2852 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2853 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2854
2855 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2856 }
2857
2858 void radv_CmdSetBlendConstants(
2859 VkCommandBuffer commandBuffer,
2860 const float blendConstants[4])
2861 {
2862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2863
2864 memcpy(cmd_buffer->state.dynamic.blend_constants,
2865 blendConstants, sizeof(float) * 4);
2866
2867 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2868 }
2869
2870 void radv_CmdSetDepthBounds(
2871 VkCommandBuffer commandBuffer,
2872 float minDepthBounds,
2873 float maxDepthBounds)
2874 {
2875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2876
2877 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2878 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2879
2880 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2881 }
2882
2883 void radv_CmdSetStencilCompareMask(
2884 VkCommandBuffer commandBuffer,
2885 VkStencilFaceFlags faceMask,
2886 uint32_t compareMask)
2887 {
2888 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2889
2890 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2891 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2892 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2893 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2894
2895 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2896 }
2897
2898 void radv_CmdSetStencilWriteMask(
2899 VkCommandBuffer commandBuffer,
2900 VkStencilFaceFlags faceMask,
2901 uint32_t writeMask)
2902 {
2903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2904
2905 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2906 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2907 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2908 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2909
2910 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2911 }
2912
2913 void radv_CmdSetStencilReference(
2914 VkCommandBuffer commandBuffer,
2915 VkStencilFaceFlags faceMask,
2916 uint32_t reference)
2917 {
2918 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2919
2920 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2921 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2922 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2923 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2924
2925 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2926 }
2927
2928 void radv_CmdSetDiscardRectangleEXT(
2929 VkCommandBuffer commandBuffer,
2930 uint32_t firstDiscardRectangle,
2931 uint32_t discardRectangleCount,
2932 const VkRect2D* pDiscardRectangles)
2933 {
2934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2935 struct radv_cmd_state *state = &cmd_buffer->state;
2936 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2937
2938 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2939 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2940
2941 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2942 pDiscardRectangles, discardRectangleCount);
2943
2944 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2945 }
2946
2947 void radv_CmdExecuteCommands(
2948 VkCommandBuffer commandBuffer,
2949 uint32_t commandBufferCount,
2950 const VkCommandBuffer* pCmdBuffers)
2951 {
2952 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2953
2954 assert(commandBufferCount > 0);
2955
2956 /* Emit pending flushes on primary prior to executing secondary */
2957 si_emit_cache_flush(primary);
2958
2959 for (uint32_t i = 0; i < commandBufferCount; i++) {
2960 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2961
2962 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2963 secondary->scratch_size_needed);
2964 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2965 secondary->compute_scratch_size_needed);
2966
2967 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2968 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2969 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2970 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2971 if (secondary->tess_rings_needed)
2972 primary->tess_rings_needed = true;
2973 if (secondary->sample_positions_needed)
2974 primary->sample_positions_needed = true;
2975
2976 if (secondary->ring_offsets_idx != -1) {
2977 if (primary->ring_offsets_idx == -1)
2978 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2979 else
2980 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2981 }
2982 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2983
2984
2985 /* When the secondary command buffer is compute only we don't
2986 * need to re-emit the current graphics pipeline.
2987 */
2988 if (secondary->state.emitted_pipeline) {
2989 primary->state.emitted_pipeline =
2990 secondary->state.emitted_pipeline;
2991 }
2992
2993 /* When the secondary command buffer is graphics only we don't
2994 * need to re-emit the current compute pipeline.
2995 */
2996 if (secondary->state.emitted_compute_pipeline) {
2997 primary->state.emitted_compute_pipeline =
2998 secondary->state.emitted_compute_pipeline;
2999 }
3000
3001 /* Only re-emit the draw packets when needed. */
3002 if (secondary->state.last_primitive_reset_en != -1) {
3003 primary->state.last_primitive_reset_en =
3004 secondary->state.last_primitive_reset_en;
3005 }
3006
3007 if (secondary->state.last_primitive_reset_index) {
3008 primary->state.last_primitive_reset_index =
3009 secondary->state.last_primitive_reset_index;
3010 }
3011
3012 if (secondary->state.last_ia_multi_vgt_param) {
3013 primary->state.last_ia_multi_vgt_param =
3014 secondary->state.last_ia_multi_vgt_param;
3015 }
3016
3017 if (secondary->state.last_first_instance != -1) {
3018 primary->state.last_first_instance =
3019 secondary->state.last_first_instance;
3020 }
3021
3022 if (secondary->state.last_num_instances != -1) {
3023 primary->state.last_num_instances =
3024 secondary->state.last_num_instances;
3025 }
3026
3027 if (secondary->state.last_vertex_offset != -1) {
3028 primary->state.last_vertex_offset =
3029 secondary->state.last_vertex_offset;
3030 }
3031
3032 if (secondary->state.last_index_type != -1) {
3033 primary->state.last_index_type =
3034 secondary->state.last_index_type;
3035 }
3036 }
3037
3038 /* After executing commands from secondary buffers we have to dirty
3039 * some states.
3040 */
3041 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3042 RADV_CMD_DIRTY_INDEX_BUFFER |
3043 RADV_CMD_DIRTY_DYNAMIC_ALL;
3044 radv_mark_descriptor_sets_dirty(primary);
3045 }
3046
3047 VkResult radv_CreateCommandPool(
3048 VkDevice _device,
3049 const VkCommandPoolCreateInfo* pCreateInfo,
3050 const VkAllocationCallbacks* pAllocator,
3051 VkCommandPool* pCmdPool)
3052 {
3053 RADV_FROM_HANDLE(radv_device, device, _device);
3054 struct radv_cmd_pool *pool;
3055
3056 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3057 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3058 if (pool == NULL)
3059 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3060
3061 if (pAllocator)
3062 pool->alloc = *pAllocator;
3063 else
3064 pool->alloc = device->alloc;
3065
3066 list_inithead(&pool->cmd_buffers);
3067 list_inithead(&pool->free_cmd_buffers);
3068
3069 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3070
3071 *pCmdPool = radv_cmd_pool_to_handle(pool);
3072
3073 return VK_SUCCESS;
3074
3075 }
3076
3077 void radv_DestroyCommandPool(
3078 VkDevice _device,
3079 VkCommandPool commandPool,
3080 const VkAllocationCallbacks* pAllocator)
3081 {
3082 RADV_FROM_HANDLE(radv_device, device, _device);
3083 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3084
3085 if (!pool)
3086 return;
3087
3088 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3089 &pool->cmd_buffers, pool_link) {
3090 radv_cmd_buffer_destroy(cmd_buffer);
3091 }
3092
3093 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3094 &pool->free_cmd_buffers, pool_link) {
3095 radv_cmd_buffer_destroy(cmd_buffer);
3096 }
3097
3098 vk_free2(&device->alloc, pAllocator, pool);
3099 }
3100
3101 VkResult radv_ResetCommandPool(
3102 VkDevice device,
3103 VkCommandPool commandPool,
3104 VkCommandPoolResetFlags flags)
3105 {
3106 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3107 VkResult result;
3108
3109 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3110 &pool->cmd_buffers, pool_link) {
3111 result = radv_reset_cmd_buffer(cmd_buffer);
3112 if (result != VK_SUCCESS)
3113 return result;
3114 }
3115
3116 return VK_SUCCESS;
3117 }
3118
3119 void radv_TrimCommandPoolKHR(
3120 VkDevice device,
3121 VkCommandPool commandPool,
3122 VkCommandPoolTrimFlagsKHR flags)
3123 {
3124 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3125
3126 if (!pool)
3127 return;
3128
3129 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3130 &pool->free_cmd_buffers, pool_link) {
3131 radv_cmd_buffer_destroy(cmd_buffer);
3132 }
3133 }
3134
3135 void radv_CmdBeginRenderPass(
3136 VkCommandBuffer commandBuffer,
3137 const VkRenderPassBeginInfo* pRenderPassBegin,
3138 VkSubpassContents contents)
3139 {
3140 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3141 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3142 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3143
3144 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3145 cmd_buffer->cs, 2048);
3146 MAYBE_UNUSED VkResult result;
3147
3148 cmd_buffer->state.framebuffer = framebuffer;
3149 cmd_buffer->state.pass = pass;
3150 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3151
3152 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3153 if (result != VK_SUCCESS)
3154 return;
3155
3156 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3157 assert(cmd_buffer->cs->cdw <= cdw_max);
3158
3159 radv_cmd_buffer_clear_subpass(cmd_buffer);
3160 }
3161
3162 void radv_CmdNextSubpass(
3163 VkCommandBuffer commandBuffer,
3164 VkSubpassContents contents)
3165 {
3166 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3167
3168 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3169
3170 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3171 2048);
3172
3173 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3174 radv_cmd_buffer_clear_subpass(cmd_buffer);
3175 }
3176
3177 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3178 {
3179 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3180 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3181 if (!pipeline->shaders[stage])
3182 continue;
3183 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3184 if (loc->sgpr_idx == -1)
3185 continue;
3186 uint32_t base_reg = pipeline->user_data_0[stage];
3187 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3188
3189 }
3190 if (pipeline->gs_copy_shader) {
3191 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3192 if (loc->sgpr_idx != -1) {
3193 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3194 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3195 }
3196 }
3197 }
3198
3199 static void
3200 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3201 uint32_t vertex_count)
3202 {
3203 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3204 radeon_emit(cmd_buffer->cs, vertex_count);
3205 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3206 S_0287F0_USE_OPAQUE(0));
3207 }
3208
3209 static void
3210 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3211 uint64_t index_va,
3212 uint32_t index_count)
3213 {
3214 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3215 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3216 radeon_emit(cmd_buffer->cs, index_va);
3217 radeon_emit(cmd_buffer->cs, index_va >> 32);
3218 radeon_emit(cmd_buffer->cs, index_count);
3219 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3220 }
3221
3222 static void
3223 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3224 bool indexed,
3225 uint32_t draw_count,
3226 uint64_t count_va,
3227 uint32_t stride)
3228 {
3229 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3230 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3231 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3232 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3233 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3234 assert(base_reg);
3235
3236 /* just reset draw state for vertex data */
3237 cmd_buffer->state.last_first_instance = -1;
3238 cmd_buffer->state.last_num_instances = -1;
3239 cmd_buffer->state.last_vertex_offset = -1;
3240
3241 if (draw_count == 1 && !count_va && !draw_id_enable) {
3242 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3243 PKT3_DRAW_INDIRECT, 3, false));
3244 radeon_emit(cs, 0);
3245 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3246 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3247 radeon_emit(cs, di_src_sel);
3248 } else {
3249 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3250 PKT3_DRAW_INDIRECT_MULTI,
3251 8, false));
3252 radeon_emit(cs, 0);
3253 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3254 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3255 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3256 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3257 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3258 radeon_emit(cs, draw_count); /* count */
3259 radeon_emit(cs, count_va); /* count_addr */
3260 radeon_emit(cs, count_va >> 32);
3261 radeon_emit(cs, stride); /* stride */
3262 radeon_emit(cs, di_src_sel);
3263 }
3264 }
3265
3266 struct radv_draw_info {
3267 /**
3268 * Number of vertices.
3269 */
3270 uint32_t count;
3271
3272 /**
3273 * Index of the first vertex.
3274 */
3275 int32_t vertex_offset;
3276
3277 /**
3278 * First instance id.
3279 */
3280 uint32_t first_instance;
3281
3282 /**
3283 * Number of instances.
3284 */
3285 uint32_t instance_count;
3286
3287 /**
3288 * First index (indexed draws only).
3289 */
3290 uint32_t first_index;
3291
3292 /**
3293 * Whether it's an indexed draw.
3294 */
3295 bool indexed;
3296
3297 /**
3298 * Indirect draw parameters resource.
3299 */
3300 struct radv_buffer *indirect;
3301 uint64_t indirect_offset;
3302 uint32_t stride;
3303
3304 /**
3305 * Draw count parameters resource.
3306 */
3307 struct radv_buffer *count_buffer;
3308 uint64_t count_buffer_offset;
3309 };
3310
3311 static void
3312 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3313 const struct radv_draw_info *info)
3314 {
3315 struct radv_cmd_state *state = &cmd_buffer->state;
3316 struct radeon_winsys *ws = cmd_buffer->device->ws;
3317 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3318
3319 if (info->indirect) {
3320 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3321 uint64_t count_va = 0;
3322
3323 va += info->indirect->offset + info->indirect_offset;
3324
3325 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3326
3327 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3328 radeon_emit(cs, 1);
3329 radeon_emit(cs, va);
3330 radeon_emit(cs, va >> 32);
3331
3332 if (info->count_buffer) {
3333 count_va = radv_buffer_get_va(info->count_buffer->bo);
3334 count_va += info->count_buffer->offset +
3335 info->count_buffer_offset;
3336
3337 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3338 }
3339
3340 if (!state->subpass->view_mask) {
3341 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3342 info->indexed,
3343 info->count,
3344 count_va,
3345 info->stride);
3346 } else {
3347 unsigned i;
3348 for_each_bit(i, state->subpass->view_mask) {
3349 radv_emit_view_index(cmd_buffer, i);
3350
3351 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3352 info->indexed,
3353 info->count,
3354 count_va,
3355 info->stride);
3356 }
3357 }
3358 } else {
3359 assert(state->pipeline->graphics.vtx_base_sgpr);
3360
3361 if (info->vertex_offset != state->last_vertex_offset ||
3362 info->first_instance != state->last_first_instance) {
3363 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3364 state->pipeline->graphics.vtx_emit_num);
3365
3366 radeon_emit(cs, info->vertex_offset);
3367 radeon_emit(cs, info->first_instance);
3368 if (state->pipeline->graphics.vtx_emit_num == 3)
3369 radeon_emit(cs, 0);
3370 state->last_first_instance = info->first_instance;
3371 state->last_vertex_offset = info->vertex_offset;
3372 }
3373
3374 if (state->last_num_instances != info->instance_count) {
3375 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3376 radeon_emit(cs, info->instance_count);
3377 state->last_num_instances = info->instance_count;
3378 }
3379
3380 if (info->indexed) {
3381 int index_size = state->index_type ? 4 : 2;
3382 uint64_t index_va;
3383
3384 index_va = state->index_va;
3385 index_va += info->first_index * index_size;
3386
3387 if (!state->subpass->view_mask) {
3388 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3389 index_va,
3390 info->count);
3391 } else {
3392 unsigned i;
3393 for_each_bit(i, state->subpass->view_mask) {
3394 radv_emit_view_index(cmd_buffer, i);
3395
3396 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3397 index_va,
3398 info->count);
3399 }
3400 }
3401 } else {
3402 if (!state->subpass->view_mask) {
3403 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3404 } else {
3405 unsigned i;
3406 for_each_bit(i, state->subpass->view_mask) {
3407 radv_emit_view_index(cmd_buffer, i);
3408
3409 radv_cs_emit_draw_packet(cmd_buffer,
3410 info->count);
3411 }
3412 }
3413 }
3414 }
3415 }
3416
3417 static void
3418 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3419 const struct radv_draw_info *info)
3420 {
3421 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3422 radv_emit_graphics_pipeline(cmd_buffer);
3423
3424 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3425 radv_emit_framebuffer_state(cmd_buffer);
3426
3427 if (info->indexed) {
3428 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3429 radv_emit_index_buffer(cmd_buffer);
3430 } else {
3431 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3432 * so the state must be re-emitted before the next indexed
3433 * draw.
3434 */
3435 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3436 cmd_buffer->state.last_index_type = -1;
3437 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3438 }
3439 }
3440
3441 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3442
3443 radv_emit_draw_registers(cmd_buffer, info->indexed,
3444 info->instance_count > 1, info->indirect,
3445 info->indirect ? 0 : info->count);
3446 }
3447
3448 static void
3449 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3450 const struct radv_draw_info *info)
3451 {
3452 bool pipeline_is_dirty =
3453 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3454 cmd_buffer->state.pipeline &&
3455 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3456
3457 MAYBE_UNUSED unsigned cdw_max =
3458 radeon_check_space(cmd_buffer->device->ws,
3459 cmd_buffer->cs, 4096);
3460
3461 /* Use optimal packet order based on whether we need to sync the
3462 * pipeline.
3463 */
3464 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3465 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3466 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3467 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3468 /* If we have to wait for idle, set all states first, so that
3469 * all SET packets are processed in parallel with previous draw
3470 * calls. Then upload descriptors, set shader pointers, and
3471 * draw, and prefetch at the end. This ensures that the time
3472 * the CUs are idle is very short. (there are only SET_SH
3473 * packets between the wait and the draw)
3474 */
3475 radv_emit_all_graphics_states(cmd_buffer, info);
3476 si_emit_cache_flush(cmd_buffer);
3477 /* <-- CUs are idle here --> */
3478
3479 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3480 return;
3481
3482 radv_emit_draw_packets(cmd_buffer, info);
3483 /* <-- CUs are busy here --> */
3484
3485 /* Start prefetches after the draw has been started. Both will
3486 * run in parallel, but starting the draw first is more
3487 * important.
3488 */
3489 if (pipeline_is_dirty) {
3490 radv_emit_prefetch(cmd_buffer,
3491 cmd_buffer->state.pipeline);
3492 }
3493 } else {
3494 /* If we don't wait for idle, start prefetches first, then set
3495 * states, and draw at the end.
3496 */
3497 si_emit_cache_flush(cmd_buffer);
3498
3499 if (pipeline_is_dirty) {
3500 radv_emit_prefetch(cmd_buffer,
3501 cmd_buffer->state.pipeline);
3502 }
3503
3504 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3505 return;
3506
3507 radv_emit_all_graphics_states(cmd_buffer, info);
3508 radv_emit_draw_packets(cmd_buffer, info);
3509 }
3510
3511 assert(cmd_buffer->cs->cdw <= cdw_max);
3512 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3513 }
3514
3515 void radv_CmdDraw(
3516 VkCommandBuffer commandBuffer,
3517 uint32_t vertexCount,
3518 uint32_t instanceCount,
3519 uint32_t firstVertex,
3520 uint32_t firstInstance)
3521 {
3522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3523 struct radv_draw_info info = {};
3524
3525 info.count = vertexCount;
3526 info.instance_count = instanceCount;
3527 info.first_instance = firstInstance;
3528 info.vertex_offset = firstVertex;
3529
3530 radv_draw(cmd_buffer, &info);
3531 }
3532
3533 void radv_CmdDrawIndexed(
3534 VkCommandBuffer commandBuffer,
3535 uint32_t indexCount,
3536 uint32_t instanceCount,
3537 uint32_t firstIndex,
3538 int32_t vertexOffset,
3539 uint32_t firstInstance)
3540 {
3541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3542 struct radv_draw_info info = {};
3543
3544 info.indexed = true;
3545 info.count = indexCount;
3546 info.instance_count = instanceCount;
3547 info.first_index = firstIndex;
3548 info.vertex_offset = vertexOffset;
3549 info.first_instance = firstInstance;
3550
3551 radv_draw(cmd_buffer, &info);
3552 }
3553
3554 void radv_CmdDrawIndirect(
3555 VkCommandBuffer commandBuffer,
3556 VkBuffer _buffer,
3557 VkDeviceSize offset,
3558 uint32_t drawCount,
3559 uint32_t stride)
3560 {
3561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3562 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3563 struct radv_draw_info info = {};
3564
3565 info.count = drawCount;
3566 info.indirect = buffer;
3567 info.indirect_offset = offset;
3568 info.stride = stride;
3569
3570 radv_draw(cmd_buffer, &info);
3571 }
3572
3573 void radv_CmdDrawIndexedIndirect(
3574 VkCommandBuffer commandBuffer,
3575 VkBuffer _buffer,
3576 VkDeviceSize offset,
3577 uint32_t drawCount,
3578 uint32_t stride)
3579 {
3580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3581 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3582 struct radv_draw_info info = {};
3583
3584 info.indexed = true;
3585 info.count = drawCount;
3586 info.indirect = buffer;
3587 info.indirect_offset = offset;
3588 info.stride = stride;
3589
3590 radv_draw(cmd_buffer, &info);
3591 }
3592
3593 void radv_CmdDrawIndirectCountAMD(
3594 VkCommandBuffer commandBuffer,
3595 VkBuffer _buffer,
3596 VkDeviceSize offset,
3597 VkBuffer _countBuffer,
3598 VkDeviceSize countBufferOffset,
3599 uint32_t maxDrawCount,
3600 uint32_t stride)
3601 {
3602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3603 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3604 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3605 struct radv_draw_info info = {};
3606
3607 info.count = maxDrawCount;
3608 info.indirect = buffer;
3609 info.indirect_offset = offset;
3610 info.count_buffer = count_buffer;
3611 info.count_buffer_offset = countBufferOffset;
3612 info.stride = stride;
3613
3614 radv_draw(cmd_buffer, &info);
3615 }
3616
3617 void radv_CmdDrawIndexedIndirectCountAMD(
3618 VkCommandBuffer commandBuffer,
3619 VkBuffer _buffer,
3620 VkDeviceSize offset,
3621 VkBuffer _countBuffer,
3622 VkDeviceSize countBufferOffset,
3623 uint32_t maxDrawCount,
3624 uint32_t stride)
3625 {
3626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3627 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3628 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3629 struct radv_draw_info info = {};
3630
3631 info.indexed = true;
3632 info.count = maxDrawCount;
3633 info.indirect = buffer;
3634 info.indirect_offset = offset;
3635 info.count_buffer = count_buffer;
3636 info.count_buffer_offset = countBufferOffset;
3637 info.stride = stride;
3638
3639 radv_draw(cmd_buffer, &info);
3640 }
3641
3642 struct radv_dispatch_info {
3643 /**
3644 * Determine the layout of the grid (in block units) to be used.
3645 */
3646 uint32_t blocks[3];
3647
3648 /**
3649 * Whether it's an unaligned compute dispatch.
3650 */
3651 bool unaligned;
3652
3653 /**
3654 * Indirect compute parameters resource.
3655 */
3656 struct radv_buffer *indirect;
3657 uint64_t indirect_offset;
3658 };
3659
3660 static void
3661 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3662 const struct radv_dispatch_info *info)
3663 {
3664 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3665 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3666 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3667 struct radeon_winsys *ws = cmd_buffer->device->ws;
3668 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3669 struct ac_userdata_info *loc;
3670
3671 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3672 AC_UD_CS_GRID_SIZE);
3673
3674 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3675
3676 if (info->indirect) {
3677 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3678
3679 va += info->indirect->offset + info->indirect_offset;
3680
3681 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3682
3683 if (loc->sgpr_idx != -1) {
3684 for (unsigned i = 0; i < 3; ++i) {
3685 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3686 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3687 COPY_DATA_DST_SEL(COPY_DATA_REG));
3688 radeon_emit(cs, (va + 4 * i));
3689 radeon_emit(cs, (va + 4 * i) >> 32);
3690 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3691 + loc->sgpr_idx * 4) >> 2) + i);
3692 radeon_emit(cs, 0);
3693 }
3694 }
3695
3696 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3697 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3698 PKT3_SHADER_TYPE_S(1));
3699 radeon_emit(cs, va);
3700 radeon_emit(cs, va >> 32);
3701 radeon_emit(cs, dispatch_initiator);
3702 } else {
3703 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3704 PKT3_SHADER_TYPE_S(1));
3705 radeon_emit(cs, 1);
3706 radeon_emit(cs, va);
3707 radeon_emit(cs, va >> 32);
3708
3709 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3710 PKT3_SHADER_TYPE_S(1));
3711 radeon_emit(cs, 0);
3712 radeon_emit(cs, dispatch_initiator);
3713 }
3714 } else {
3715 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3716
3717 if (info->unaligned) {
3718 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3719 unsigned remainder[3];
3720
3721 /* If aligned, these should be an entire block size,
3722 * not 0.
3723 */
3724 remainder[0] = blocks[0] + cs_block_size[0] -
3725 align_u32_npot(blocks[0], cs_block_size[0]);
3726 remainder[1] = blocks[1] + cs_block_size[1] -
3727 align_u32_npot(blocks[1], cs_block_size[1]);
3728 remainder[2] = blocks[2] + cs_block_size[2] -
3729 align_u32_npot(blocks[2], cs_block_size[2]);
3730
3731 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3732 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3733 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3734
3735 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3736 radeon_emit(cs,
3737 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3738 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3739 radeon_emit(cs,
3740 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3741 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3742 radeon_emit(cs,
3743 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3744 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3745
3746 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3747 }
3748
3749 if (loc->sgpr_idx != -1) {
3750 assert(!loc->indirect);
3751 assert(loc->num_sgprs == 3);
3752
3753 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3754 loc->sgpr_idx * 4, 3);
3755 radeon_emit(cs, blocks[0]);
3756 radeon_emit(cs, blocks[1]);
3757 radeon_emit(cs, blocks[2]);
3758 }
3759
3760 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3761 PKT3_SHADER_TYPE_S(1));
3762 radeon_emit(cs, blocks[0]);
3763 radeon_emit(cs, blocks[1]);
3764 radeon_emit(cs, blocks[2]);
3765 radeon_emit(cs, dispatch_initiator);
3766 }
3767
3768 assert(cmd_buffer->cs->cdw <= cdw_max);
3769 }
3770
3771 static void
3772 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3773 {
3774 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3775 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3776 VK_SHADER_STAGE_COMPUTE_BIT);
3777 }
3778
3779 static void
3780 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3781 const struct radv_dispatch_info *info)
3782 {
3783 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3784 bool pipeline_is_dirty = pipeline &&
3785 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3786
3787 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3788 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3789 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3790 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3791 /* If we have to wait for idle, set all states first, so that
3792 * all SET packets are processed in parallel with previous draw
3793 * calls. Then upload descriptors, set shader pointers, and
3794 * dispatch, and prefetch at the end. This ensures that the
3795 * time the CUs are idle is very short. (there are only SET_SH
3796 * packets between the wait and the draw)
3797 */
3798 radv_emit_compute_pipeline(cmd_buffer);
3799 si_emit_cache_flush(cmd_buffer);
3800 /* <-- CUs are idle here --> */
3801
3802 radv_upload_compute_shader_descriptors(cmd_buffer);
3803
3804 radv_emit_dispatch_packets(cmd_buffer, info);
3805 /* <-- CUs are busy here --> */
3806
3807 /* Start prefetches after the dispatch has been started. Both
3808 * will run in parallel, but starting the dispatch first is
3809 * more important.
3810 */
3811 if (pipeline_is_dirty) {
3812 radv_emit_shader_prefetch(cmd_buffer,
3813 pipeline->shaders[MESA_SHADER_COMPUTE]);
3814 }
3815 } else {
3816 /* If we don't wait for idle, start prefetches first, then set
3817 * states, and dispatch at the end.
3818 */
3819 si_emit_cache_flush(cmd_buffer);
3820
3821 if (pipeline_is_dirty) {
3822 radv_emit_shader_prefetch(cmd_buffer,
3823 pipeline->shaders[MESA_SHADER_COMPUTE]);
3824 }
3825
3826 radv_upload_compute_shader_descriptors(cmd_buffer);
3827
3828 radv_emit_compute_pipeline(cmd_buffer);
3829 radv_emit_dispatch_packets(cmd_buffer, info);
3830 }
3831
3832 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3833 }
3834
3835 void radv_CmdDispatch(
3836 VkCommandBuffer commandBuffer,
3837 uint32_t x,
3838 uint32_t y,
3839 uint32_t z)
3840 {
3841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3842 struct radv_dispatch_info info = {};
3843
3844 info.blocks[0] = x;
3845 info.blocks[1] = y;
3846 info.blocks[2] = z;
3847
3848 radv_dispatch(cmd_buffer, &info);
3849 }
3850
3851 void radv_CmdDispatchIndirect(
3852 VkCommandBuffer commandBuffer,
3853 VkBuffer _buffer,
3854 VkDeviceSize offset)
3855 {
3856 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3857 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3858 struct radv_dispatch_info info = {};
3859
3860 info.indirect = buffer;
3861 info.indirect_offset = offset;
3862
3863 radv_dispatch(cmd_buffer, &info);
3864 }
3865
3866 void radv_unaligned_dispatch(
3867 struct radv_cmd_buffer *cmd_buffer,
3868 uint32_t x,
3869 uint32_t y,
3870 uint32_t z)
3871 {
3872 struct radv_dispatch_info info = {};
3873
3874 info.blocks[0] = x;
3875 info.blocks[1] = y;
3876 info.blocks[2] = z;
3877 info.unaligned = 1;
3878
3879 radv_dispatch(cmd_buffer, &info);
3880 }
3881
3882 void radv_CmdEndRenderPass(
3883 VkCommandBuffer commandBuffer)
3884 {
3885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3886
3887 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3888
3889 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3890
3891 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3892 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3893 radv_handle_subpass_image_transition(cmd_buffer,
3894 (VkAttachmentReference){i, layout});
3895 }
3896
3897 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3898
3899 cmd_buffer->state.pass = NULL;
3900 cmd_buffer->state.subpass = NULL;
3901 cmd_buffer->state.attachments = NULL;
3902 cmd_buffer->state.framebuffer = NULL;
3903 }
3904
3905 /*
3906 * For HTILE we have the following interesting clear words:
3907 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3908 * 0x0000000f: Uncompressed for depth only HTILE.
3909 * 0xfffffff0: Clear depth to 1.0
3910 * 0x00000000: Clear depth to 0.0
3911 */
3912 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3913 struct radv_image *image,
3914 const VkImageSubresourceRange *range,
3915 uint32_t clear_word)
3916 {
3917 assert(range->baseMipLevel == 0);
3918 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3919 unsigned layer_count = radv_get_layerCount(image, range);
3920 uint64_t size = image->surface.htile_slice_size * layer_count;
3921 uint64_t offset = image->offset + image->htile_offset +
3922 image->surface.htile_slice_size * range->baseArrayLayer;
3923 struct radv_cmd_state *state = &cmd_buffer->state;
3924
3925 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3926 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3927
3928 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3929 size, clear_word);
3930
3931 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3932 }
3933
3934 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3935 struct radv_image *image,
3936 VkImageLayout src_layout,
3937 VkImageLayout dst_layout,
3938 unsigned src_queue_mask,
3939 unsigned dst_queue_mask,
3940 const VkImageSubresourceRange *range,
3941 VkImageAspectFlags pending_clears)
3942 {
3943 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3944 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3945 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3946 cmd_buffer->state.render_area.extent.width == image->info.width &&
3947 cmd_buffer->state.render_area.extent.height == image->info.height) {
3948 /* The clear will initialize htile. */
3949 return;
3950 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3951 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3952 /* TODO: merge with the clear if applicable */
3953 radv_initialize_htile(cmd_buffer, image, range, 0);
3954 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3955 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3956 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3957 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3958 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3959 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3960 VkImageSubresourceRange local_range = *range;
3961 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3962 local_range.baseMipLevel = 0;
3963 local_range.levelCount = 1;
3964
3965 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3967
3968 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3969
3970 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3971 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3972 }
3973 }
3974
3975 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3976 struct radv_image *image, uint32_t value)
3977 {
3978 struct radv_cmd_state *state = &cmd_buffer->state;
3979
3980 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3981 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3982
3983 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3984 image->offset + image->cmask.offset,
3985 image->cmask.size, value);
3986
3987 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3988 }
3989
3990 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3991 struct radv_image *image,
3992 VkImageLayout src_layout,
3993 VkImageLayout dst_layout,
3994 unsigned src_queue_mask,
3995 unsigned dst_queue_mask,
3996 const VkImageSubresourceRange *range)
3997 {
3998 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3999 if (image->fmask.size)
4000 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
4001 else
4002 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
4003 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4004 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4005 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4006 }
4007 }
4008
4009 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4010 struct radv_image *image, uint32_t value)
4011 {
4012 struct radv_cmd_state *state = &cmd_buffer->state;
4013
4014 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4015 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4016
4017 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
4018 image->offset + image->dcc_offset,
4019 image->surface.dcc_size, value);
4020
4021 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4023 }
4024
4025 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
4026 struct radv_image *image,
4027 VkImageLayout src_layout,
4028 VkImageLayout dst_layout,
4029 unsigned src_queue_mask,
4030 unsigned dst_queue_mask,
4031 const VkImageSubresourceRange *range)
4032 {
4033 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4034 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4035 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4036 radv_initialize_dcc(cmd_buffer, image,
4037 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
4038 0x20202020u : 0xffffffffu);
4039 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4040 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4041 radv_decompress_dcc(cmd_buffer, image, range);
4042 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4043 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4044 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4045 }
4046 }
4047
4048 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4049 struct radv_image *image,
4050 VkImageLayout src_layout,
4051 VkImageLayout dst_layout,
4052 uint32_t src_family,
4053 uint32_t dst_family,
4054 const VkImageSubresourceRange *range,
4055 VkImageAspectFlags pending_clears)
4056 {
4057 if (image->exclusive && src_family != dst_family) {
4058 /* This is an acquire or a release operation and there will be
4059 * a corresponding release/acquire. Do the transition in the
4060 * most flexible queue. */
4061
4062 assert(src_family == cmd_buffer->queue_family_index ||
4063 dst_family == cmd_buffer->queue_family_index);
4064
4065 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4066 return;
4067
4068 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4069 (src_family == RADV_QUEUE_GENERAL ||
4070 dst_family == RADV_QUEUE_GENERAL))
4071 return;
4072 }
4073
4074 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
4075 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
4076
4077 if (image->surface.htile_size)
4078 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
4079 dst_layout, src_queue_mask,
4080 dst_queue_mask, range,
4081 pending_clears);
4082
4083 if (image->cmask.size || image->fmask.size)
4084 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
4085 dst_layout, src_queue_mask,
4086 dst_queue_mask, range);
4087
4088 if (image->surface.dcc_size)
4089 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
4090 dst_layout, src_queue_mask,
4091 dst_queue_mask, range);
4092 }
4093
4094 void radv_CmdPipelineBarrier(
4095 VkCommandBuffer commandBuffer,
4096 VkPipelineStageFlags srcStageMask,
4097 VkPipelineStageFlags destStageMask,
4098 VkBool32 byRegion,
4099 uint32_t memoryBarrierCount,
4100 const VkMemoryBarrier* pMemoryBarriers,
4101 uint32_t bufferMemoryBarrierCount,
4102 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4103 uint32_t imageMemoryBarrierCount,
4104 const VkImageMemoryBarrier* pImageMemoryBarriers)
4105 {
4106 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4107 enum radv_cmd_flush_bits src_flush_bits = 0;
4108 enum radv_cmd_flush_bits dst_flush_bits = 0;
4109
4110 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4111 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4112 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4113 NULL);
4114 }
4115
4116 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4117 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4118 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4119 NULL);
4120 }
4121
4122 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4123 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4124 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4125 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4126 image);
4127 }
4128
4129 radv_stage_flush(cmd_buffer, srcStageMask);
4130 cmd_buffer->state.flush_bits |= src_flush_bits;
4131
4132 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4133 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4134 radv_handle_image_transition(cmd_buffer, image,
4135 pImageMemoryBarriers[i].oldLayout,
4136 pImageMemoryBarriers[i].newLayout,
4137 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4138 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4139 &pImageMemoryBarriers[i].subresourceRange,
4140 0);
4141 }
4142
4143 cmd_buffer->state.flush_bits |= dst_flush_bits;
4144 }
4145
4146
4147 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4148 struct radv_event *event,
4149 VkPipelineStageFlags stageMask,
4150 unsigned value)
4151 {
4152 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4153 uint64_t va = radv_buffer_get_va(event->bo);
4154
4155 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4156
4157 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4158
4159 /* TODO: this is overkill. Probably should figure something out from
4160 * the stage mask. */
4161
4162 si_cs_emit_write_event_eop(cs,
4163 cmd_buffer->state.predicating,
4164 cmd_buffer->device->physical_device->rad_info.chip_class,
4165 radv_cmd_buffer_uses_mec(cmd_buffer),
4166 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4167 1, va, 2, value);
4168
4169 assert(cmd_buffer->cs->cdw <= cdw_max);
4170 }
4171
4172 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4173 VkEvent _event,
4174 VkPipelineStageFlags stageMask)
4175 {
4176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4177 RADV_FROM_HANDLE(radv_event, event, _event);
4178
4179 write_event(cmd_buffer, event, stageMask, 1);
4180 }
4181
4182 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4183 VkEvent _event,
4184 VkPipelineStageFlags stageMask)
4185 {
4186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4187 RADV_FROM_HANDLE(radv_event, event, _event);
4188
4189 write_event(cmd_buffer, event, stageMask, 0);
4190 }
4191
4192 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4193 uint32_t eventCount,
4194 const VkEvent* pEvents,
4195 VkPipelineStageFlags srcStageMask,
4196 VkPipelineStageFlags dstStageMask,
4197 uint32_t memoryBarrierCount,
4198 const VkMemoryBarrier* pMemoryBarriers,
4199 uint32_t bufferMemoryBarrierCount,
4200 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4201 uint32_t imageMemoryBarrierCount,
4202 const VkImageMemoryBarrier* pImageMemoryBarriers)
4203 {
4204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4205 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4206
4207 for (unsigned i = 0; i < eventCount; ++i) {
4208 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4209 uint64_t va = radv_buffer_get_va(event->bo);
4210
4211 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4212
4213 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4214
4215 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4216 assert(cmd_buffer->cs->cdw <= cdw_max);
4217 }
4218
4219
4220 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4221 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4222
4223 radv_handle_image_transition(cmd_buffer, image,
4224 pImageMemoryBarriers[i].oldLayout,
4225 pImageMemoryBarriers[i].newLayout,
4226 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4227 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4228 &pImageMemoryBarriers[i].subresourceRange,
4229 0);
4230 }
4231
4232 /* TODO: figure out how to do memory barriers without waiting */
4233 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4234 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4235 RADV_CMD_FLAG_INV_VMEM_L1 |
4236 RADV_CMD_FLAG_INV_SMEM_L1;
4237 }