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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94 dest->discard_rectangle.count = src->discard_rectangle.count;
95
96 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
97 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
98 src->viewport.count * sizeof(VkViewport))) {
99 typed_memcpy(dest->viewport.viewports,
100 src->viewport.viewports,
101 src->viewport.count);
102 dest_mask |= RADV_DYNAMIC_VIEWPORT;
103 }
104 }
105
106 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
107 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
108 src->scissor.count * sizeof(VkRect2D))) {
109 typed_memcpy(dest->scissor.scissors,
110 src->scissor.scissors, src->scissor.count);
111 dest_mask |= RADV_DYNAMIC_SCISSOR;
112 }
113 }
114
115 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
116 if (dest->line_width != src->line_width) {
117 dest->line_width = src->line_width;
118 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
119 }
120 }
121
122 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
123 if (memcmp(&dest->depth_bias, &src->depth_bias,
124 sizeof(src->depth_bias))) {
125 dest->depth_bias = src->depth_bias;
126 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
131 if (memcmp(&dest->blend_constants, &src->blend_constants,
132 sizeof(src->blend_constants))) {
133 typed_memcpy(dest->blend_constants,
134 src->blend_constants, 4);
135 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
140 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
141 sizeof(src->depth_bounds))) {
142 dest->depth_bounds = src->depth_bounds;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
148 if (memcmp(&dest->stencil_compare_mask,
149 &src->stencil_compare_mask,
150 sizeof(src->stencil_compare_mask))) {
151 dest->stencil_compare_mask = src->stencil_compare_mask;
152 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
157 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
158 sizeof(src->stencil_write_mask))) {
159 dest->stencil_write_mask = src->stencil_write_mask;
160 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
165 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
166 sizeof(src->stencil_reference))) {
167 dest->stencil_reference = src->stencil_reference;
168 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
169 }
170 }
171
172 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
173 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
174 src->discard_rectangle.count * sizeof(VkRect2D))) {
175 typed_memcpy(dest->discard_rectangle.rectangles,
176 src->discard_rectangle.rectangles,
177 src->discard_rectangle.count);
178 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
179 }
180 }
181
182 cmd_buffer->state.dirty |= dest_mask;
183 }
184
185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
186 {
187 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
188 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
189 }
190
191 enum ring_type radv_queue_family_to_ring(int f) {
192 switch (f) {
193 case RADV_QUEUE_GENERAL:
194 return RING_GFX;
195 case RADV_QUEUE_COMPUTE:
196 return RING_COMPUTE;
197 case RADV_QUEUE_TRANSFER:
198 return RING_DMA;
199 default:
200 unreachable("Unknown queue family");
201 }
202 }
203
204 static VkResult radv_create_cmd_buffer(
205 struct radv_device * device,
206 struct radv_cmd_pool * pool,
207 VkCommandBufferLevel level,
208 VkCommandBuffer* pCommandBuffer)
209 {
210 struct radv_cmd_buffer *cmd_buffer;
211 unsigned ring;
212 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
216
217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 cmd_buffer->device = device;
219 cmd_buffer->pool = pool;
220 cmd_buffer->level = level;
221
222 if (pool) {
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 cmd_buffer->queue_family_index = pool->queue_family_index;
225
226 } else {
227 /* Init the pool_link so we can safefly call list_del when we destroy
228 * the command buffer
229 */
230 list_inithead(&cmd_buffer->pool_link);
231 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
232 }
233
234 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
235
236 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
237 if (!cmd_buffer->cs) {
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
240 }
241
242 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
243
244 list_inithead(&cmd_buffer->upload.list);
245
246 return VK_SUCCESS;
247 }
248
249 static void
250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
251 {
252 list_del(&cmd_buffer->pool_link);
253
254 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
255 &cmd_buffer->upload.list, list) {
256 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
257 list_del(&up->list);
258 free(up);
259 }
260
261 if (cmd_buffer->upload.upload_bo)
262 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
263 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
264 free(cmd_buffer->push_descriptors.set.mapped_ptr);
265 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
266 }
267
268 static VkResult
269 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
270 {
271
272 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
273
274 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
275 &cmd_buffer->upload.list, list) {
276 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
277 list_del(&up->list);
278 free(up);
279 }
280
281 cmd_buffer->push_constant_stages = 0;
282 cmd_buffer->scratch_size_needed = 0;
283 cmd_buffer->compute_scratch_size_needed = 0;
284 cmd_buffer->esgs_ring_size_needed = 0;
285 cmd_buffer->gsvs_ring_size_needed = 0;
286 cmd_buffer->tess_rings_needed = false;
287 cmd_buffer->sample_positions_needed = false;
288
289 if (cmd_buffer->upload.upload_bo)
290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
291 cmd_buffer->upload.upload_bo, 8);
292 cmd_buffer->upload.offset = 0;
293
294 cmd_buffer->record_result = VK_SUCCESS;
295
296 cmd_buffer->ring_offsets_idx = -1;
297
298 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
299 void *fence_ptr;
300 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
301 &cmd_buffer->gfx9_fence_offset,
302 &fence_ptr);
303 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
304 }
305
306 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
307
308 return cmd_buffer->record_result;
309 }
310
311 static bool
312 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
313 uint64_t min_needed)
314 {
315 uint64_t new_size;
316 struct radeon_winsys_bo *bo;
317 struct radv_cmd_buffer_upload *upload;
318 struct radv_device *device = cmd_buffer->device;
319
320 new_size = MAX2(min_needed, 16 * 1024);
321 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
322
323 bo = device->ws->buffer_create(device->ws,
324 new_size, 4096,
325 RADEON_DOMAIN_GTT,
326 RADEON_FLAG_CPU_ACCESS|
327 RADEON_FLAG_NO_INTERPROCESS_SHARING);
328
329 if (!bo) {
330 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
331 return false;
332 }
333
334 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
335 if (cmd_buffer->upload.upload_bo) {
336 upload = malloc(sizeof(*upload));
337
338 if (!upload) {
339 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
340 device->ws->buffer_destroy(bo);
341 return false;
342 }
343
344 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
345 list_add(&upload->list, &cmd_buffer->upload.list);
346 }
347
348 cmd_buffer->upload.upload_bo = bo;
349 cmd_buffer->upload.size = new_size;
350 cmd_buffer->upload.offset = 0;
351 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
352
353 if (!cmd_buffer->upload.map) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 return true;
359 }
360
361 bool
362 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
363 unsigned size,
364 unsigned alignment,
365 unsigned *out_offset,
366 void **ptr)
367 {
368 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
369 if (offset + size > cmd_buffer->upload.size) {
370 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
371 return false;
372 offset = 0;
373 }
374
375 *out_offset = offset;
376 *ptr = cmd_buffer->upload.map + offset;
377
378 cmd_buffer->upload.offset = offset + size;
379 return true;
380 }
381
382 bool
383 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
384 unsigned size, unsigned alignment,
385 const void *data, unsigned *out_offset)
386 {
387 uint8_t *ptr;
388
389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
390 out_offset, (void **)&ptr))
391 return false;
392
393 if (ptr)
394 memcpy(ptr, data, size);
395
396 return true;
397 }
398
399 static void
400 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
401 unsigned count, const uint32_t *data)
402 {
403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
404 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
405 S_370_WR_CONFIRM(1) |
406 S_370_ENGINE_SEL(V_370_ME));
407 radeon_emit(cs, va);
408 radeon_emit(cs, va >> 32);
409 radeon_emit_array(cs, data, count);
410 }
411
412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
413 {
414 struct radv_device *device = cmd_buffer->device;
415 struct radeon_winsys_cs *cs = cmd_buffer->cs;
416 uint64_t va;
417
418 va = radv_buffer_get_va(device->trace_bo);
419 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
420 va += 4;
421
422 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
423
424 ++cmd_buffer->state.trace_id;
425 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
426 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
428 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
429 }
430
431 static void
432 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
433 enum radv_cmd_flush_bits flags)
434 {
435 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
436 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
437 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
438
439 /* Force wait for graphics or compute engines to be idle. */
440 si_cs_emit_cache_flush(cmd_buffer->cs, false,
441 cmd_buffer->device->physical_device->rad_info.chip_class,
442 NULL, 0,
443 radv_cmd_buffer_uses_mec(cmd_buffer),
444 flags);
445 }
446
447 if (unlikely(cmd_buffer->device->trace_bo))
448 radv_cmd_buffer_trace_emit(cmd_buffer);
449 }
450
451 static void
452 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
453 struct radv_pipeline *pipeline, enum ring_type ring)
454 {
455 struct radv_device *device = cmd_buffer->device;
456 struct radeon_winsys_cs *cs = cmd_buffer->cs;
457 uint32_t data[2];
458 uint64_t va;
459
460 va = radv_buffer_get_va(device->trace_bo);
461
462 switch (ring) {
463 case RING_GFX:
464 va += 8;
465 break;
466 case RING_COMPUTE:
467 va += 16;
468 break;
469 default:
470 assert(!"invalid ring type");
471 }
472
473 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
474 cmd_buffer->cs, 6);
475
476 data[0] = (uintptr_t)pipeline;
477 data[1] = (uintptr_t)pipeline >> 32;
478
479 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
480 radv_emit_write_data_packet(cs, va, 2, data);
481 }
482
483 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
484 struct radv_descriptor_set *set,
485 unsigned idx)
486 {
487 cmd_buffer->descriptors[idx] = set;
488 if (set)
489 cmd_buffer->state.valid_descriptors |= (1u << idx);
490 else
491 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
492 cmd_buffer->state.descriptors_dirty |= (1u << idx);
493
494 }
495
496 static void
497 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
498 {
499 struct radv_device *device = cmd_buffer->device;
500 struct radeon_winsys_cs *cs = cmd_buffer->cs;
501 uint32_t data[MAX_SETS * 2] = {};
502 uint64_t va;
503 unsigned i;
504 va = radv_buffer_get_va(device->trace_bo) + 24;
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 4 + MAX_SETS * 2);
508
509 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
510 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
511 data[i * 2] = (uintptr_t)set;
512 data[i * 2 + 1] = (uintptr_t)set >> 32;
513 }
514
515 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
516 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
517 }
518
519 static void
520 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_pipeline *pipeline)
522 {
523 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
524 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
525 8);
526 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
527 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
528
529 if (cmd_buffer->device->physical_device->has_rbplus) {
530
531 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
532 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
533
534 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
535 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
536 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
537 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
538 }
539 }
540
541 static void
542 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
543 struct radv_pipeline *pipeline)
544 {
545 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
546 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
547 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
548
549 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
550 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
551 }
552
553 struct ac_userdata_info *
554 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
555 gl_shader_stage stage,
556 int idx)
557 {
558 if (stage == MESA_SHADER_VERTEX) {
559 if (pipeline->shaders[MESA_SHADER_VERTEX])
560 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
561 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
562 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
563 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
564 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
565 } else if (stage == MESA_SHADER_TESS_EVAL) {
566 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
567 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
568 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
569 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
570 }
571 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
572 }
573
574 static void
575 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
576 struct radv_pipeline *pipeline,
577 gl_shader_stage stage,
578 int idx, uint64_t va)
579 {
580 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
581 uint32_t base_reg = pipeline->user_data_0[stage];
582 if (loc->sgpr_idx == -1)
583 return;
584 assert(loc->num_sgprs == 2);
585 assert(!loc->indirect);
586 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
587 radeon_emit(cmd_buffer->cs, va);
588 radeon_emit(cmd_buffer->cs, va >> 32);
589 }
590
591 static void
592 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
593 struct radv_pipeline *pipeline)
594 {
595 int num_samples = pipeline->graphics.ms.num_samples;
596 struct radv_multisample_state *ms = &pipeline->graphics.ms;
597 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
598
599 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
600 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
602
603 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
604 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
605
606 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
607 uint32_t offset;
608 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
609 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
610 if (loc->sgpr_idx == -1)
611 return;
612 assert(loc->num_sgprs == 1);
613 assert(!loc->indirect);
614 switch (num_samples) {
615 default:
616 offset = 0;
617 break;
618 case 2:
619 offset = 1;
620 break;
621 case 4:
622 offset = 3;
623 break;
624 case 8:
625 offset = 7;
626 break;
627 case 16:
628 offset = 15;
629 break;
630 }
631
632 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
633 cmd_buffer->sample_positions_needed = true;
634 }
635
636 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
637 return;
638
639 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
640 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
641 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
642
643 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
644
645 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
646
647 /* GFX9: Flush DFSM when the AA mode changes. */
648 if (cmd_buffer->device->dfsm_allowed) {
649 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
650 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
651 }
652 }
653
654 static void
655 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
656 struct radv_pipeline *pipeline)
657 {
658 struct radv_raster_state *raster = &pipeline->graphics.raster;
659
660 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
661 raster->pa_cl_clip_cntl);
662 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
663 raster->spi_interp_control);
664 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
665 raster->pa_su_vtx_cntl);
666 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
667 raster->pa_su_sc_mode_cntl);
668 }
669
670 static inline void
671 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
672 unsigned size)
673 {
674 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
675 si_cp_dma_prefetch(cmd_buffer, va, size);
676 }
677
678 static void
679 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
680 {
681 if (cmd_buffer->state.vb_prefetch_dirty) {
682 radv_emit_prefetch_TC_L2_async(cmd_buffer,
683 cmd_buffer->state.vb_va,
684 cmd_buffer->state.vb_size);
685 cmd_buffer->state.vb_prefetch_dirty = false;
686 }
687 }
688
689 static void
690 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
691 struct radv_shader_variant *shader)
692 {
693 struct radeon_winsys *ws = cmd_buffer->device->ws;
694 struct radeon_winsys_cs *cs = cmd_buffer->cs;
695 uint64_t va;
696
697 if (!shader)
698 return;
699
700 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
701
702 radv_cs_add_buffer(ws, cs, shader->bo, 8);
703 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
704 }
705
706 static void
707 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
708 struct radv_pipeline *pipeline)
709 {
710 radv_emit_shader_prefetch(cmd_buffer,
711 pipeline->shaders[MESA_SHADER_VERTEX]);
712 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
715 radv_emit_shader_prefetch(cmd_buffer,
716 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
717 radv_emit_shader_prefetch(cmd_buffer,
718 pipeline->shaders[MESA_SHADER_GEOMETRY]);
719 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
720 radv_emit_shader_prefetch(cmd_buffer,
721 pipeline->shaders[MESA_SHADER_FRAGMENT]);
722 }
723
724 static void
725 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
726 struct radv_pipeline *pipeline,
727 struct radv_shader_variant *shader)
728 {
729 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
730
731 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
732 pipeline->graphics.vs.spi_vs_out_config);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
735 pipeline->graphics.vs.spi_shader_pos_format);
736
737 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
738 radeon_emit(cmd_buffer->cs, va >> 8);
739 radeon_emit(cmd_buffer->cs, va >> 40);
740 radeon_emit(cmd_buffer->cs, shader->rsrc1);
741 radeon_emit(cmd_buffer->cs, shader->rsrc2);
742
743 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
744 S_028818_VTX_W0_FMT(1) |
745 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
746 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
747 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
748
749
750 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
751 pipeline->graphics.vs.pa_cl_vs_out_cntl);
752
753 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
754 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
755 pipeline->graphics.vs.vgt_reuse_off);
756 }
757
758 static void
759 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
760 struct radv_pipeline *pipeline,
761 struct radv_shader_variant *shader)
762 {
763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
764
765 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
766 radeon_emit(cmd_buffer->cs, va >> 8);
767 radeon_emit(cmd_buffer->cs, va >> 40);
768 radeon_emit(cmd_buffer->cs, shader->rsrc1);
769 radeon_emit(cmd_buffer->cs, shader->rsrc2);
770 }
771
772 static void
773 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
774 struct radv_shader_variant *shader)
775 {
776 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
777 uint32_t rsrc2 = shader->rsrc2;
778
779 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
780 radeon_emit(cmd_buffer->cs, va >> 8);
781 radeon_emit(cmd_buffer->cs, va >> 40);
782
783 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
784 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
785 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
786 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
787
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
789 radeon_emit(cmd_buffer->cs, shader->rsrc1);
790 radeon_emit(cmd_buffer->cs, rsrc2);
791 }
792
793 static void
794 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
795 struct radv_shader_variant *shader)
796 {
797 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
798
799 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
800 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
801 radeon_emit(cmd_buffer->cs, va >> 8);
802 radeon_emit(cmd_buffer->cs, va >> 40);
803
804 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
805 radeon_emit(cmd_buffer->cs, shader->rsrc1);
806 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
807 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
808 } else {
809 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
810 radeon_emit(cmd_buffer->cs, va >> 8);
811 radeon_emit(cmd_buffer->cs, va >> 40);
812 radeon_emit(cmd_buffer->cs, shader->rsrc1);
813 radeon_emit(cmd_buffer->cs, shader->rsrc2);
814 }
815 }
816
817 static void
818 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
819 struct radv_pipeline *pipeline)
820 {
821 struct radv_shader_variant *vs;
822
823 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
824
825 /* Skip shaders merged into HS/GS */
826 vs = pipeline->shaders[MESA_SHADER_VERTEX];
827 if (!vs)
828 return;
829
830 if (vs->info.vs.as_ls)
831 radv_emit_hw_ls(cmd_buffer, vs);
832 else if (vs->info.vs.as_es)
833 radv_emit_hw_es(cmd_buffer, pipeline, vs);
834 else
835 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
836 }
837
838
839 static void
840 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_pipeline *pipeline)
842 {
843 if (!radv_pipeline_has_tess(pipeline))
844 return;
845
846 struct radv_shader_variant *tes, *tcs;
847
848 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
849 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
850
851 if (tes) {
852 if (tes->info.tes.as_es)
853 radv_emit_hw_es(cmd_buffer, pipeline, tes);
854 else
855 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
856 }
857
858 radv_emit_hw_hs(cmd_buffer, tcs);
859
860 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
861 pipeline->graphics.tess.tf_param);
862
863 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
864 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
865 pipeline->graphics.tess.ls_hs_config);
866 else
867 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
868 pipeline->graphics.tess.ls_hs_config);
869
870 struct ac_userdata_info *loc;
871
872 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
873 if (loc->sgpr_idx != -1) {
874 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
875 assert(loc->num_sgprs == 4);
876 assert(!loc->indirect);
877 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
878 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
879 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
880 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
881 pipeline->graphics.tess.num_tcs_input_cp << 26);
882 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
883 }
884
885 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
886 if (loc->sgpr_idx != -1) {
887 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
888 assert(loc->num_sgprs == 1);
889 assert(!loc->indirect);
890
891 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
892 pipeline->graphics.tess.offchip_layout);
893 }
894
895 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
896 if (loc->sgpr_idx != -1) {
897 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
898 assert(loc->num_sgprs == 1);
899 assert(!loc->indirect);
900
901 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
902 pipeline->graphics.tess.tcs_in_layout);
903 }
904 }
905
906 static void
907 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
908 struct radv_pipeline *pipeline)
909 {
910 struct radv_shader_variant *gs;
911 uint64_t va;
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
914
915 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
916 if (!gs)
917 return;
918
919 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
920
921 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
922 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
923 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
924 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
925
926 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
927
928 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
929
930 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
931 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
932 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
933 radeon_emit(cmd_buffer->cs, 0);
934 radeon_emit(cmd_buffer->cs, 0);
935 radeon_emit(cmd_buffer->cs, 0);
936
937 uint32_t gs_num_invocations = gs->info.gs.invocations;
938 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
939 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
940 S_028B90_ENABLE(gs_num_invocations > 0));
941
942 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
943 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
944
945 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
946
947 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
948 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
949 radeon_emit(cmd_buffer->cs, va >> 8);
950 radeon_emit(cmd_buffer->cs, va >> 40);
951
952 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
953 radeon_emit(cmd_buffer->cs, gs->rsrc1);
954 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
955 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
956
957 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
958 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
959 } else {
960 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
961 radeon_emit(cmd_buffer->cs, va >> 8);
962 radeon_emit(cmd_buffer->cs, va >> 40);
963 radeon_emit(cmd_buffer->cs, gs->rsrc1);
964 radeon_emit(cmd_buffer->cs, gs->rsrc2);
965 }
966
967 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
968
969 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
970 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
971 if (loc->sgpr_idx != -1) {
972 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
973 uint32_t num_entries = 64;
974 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
975
976 if (is_vi)
977 num_entries *= stride;
978
979 stride = S_008F04_STRIDE(stride);
980 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
981 radeon_emit(cmd_buffer->cs, stride);
982 radeon_emit(cmd_buffer->cs, num_entries);
983 }
984 }
985
986 static void
987 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
988 struct radv_pipeline *pipeline)
989 {
990 struct radv_shader_variant *ps;
991 uint64_t va;
992 struct radv_blend_state *blend = &pipeline->graphics.blend;
993 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
994
995 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
996 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
997
998 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
999 radeon_emit(cmd_buffer->cs, va >> 8);
1000 radeon_emit(cmd_buffer->cs, va >> 40);
1001 radeon_emit(cmd_buffer->cs, ps->rsrc1);
1002 radeon_emit(cmd_buffer->cs, ps->rsrc2);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
1005 pipeline->graphics.db_shader_control);
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
1008 ps->config.spi_ps_input_ena);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1011 ps->config.spi_ps_input_addr);
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1014 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1015
1016 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
1017
1018 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1019 pipeline->graphics.shader_z_format);
1020
1021 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1022
1023 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1024 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1025
1026 if (cmd_buffer->device->dfsm_allowed) {
1027 /* optimise this? */
1028 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1029 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1030 }
1031
1032 if (pipeline->graphics.ps_input_cntl_num) {
1033 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1034 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1035 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1036 }
1037 }
1038 }
1039
1040 static void
1041 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1042 struct radv_pipeline *pipeline)
1043 {
1044 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1045
1046 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1047 return;
1048
1049 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1050 pipeline->graphics.vtx_reuse_depth);
1051 }
1052
1053 static void
1054 radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_pipeline *pipeline)
1056 {
1057 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1058
1059 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
1060 return;
1061
1062 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
1063 pipeline->graphics.bin.pa_sc_binner_cntl_0);
1064 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
1065 pipeline->graphics.bin.db_dfsm_control);
1066 }
1067
1068 static void
1069 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1070 {
1071 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1072
1073 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1074 return;
1075
1076 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1077 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1078 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1079 radv_update_multisample_state(cmd_buffer, pipeline);
1080 radv_emit_vertex_shader(cmd_buffer, pipeline);
1081 radv_emit_tess_shaders(cmd_buffer, pipeline);
1082 radv_emit_geometry_shader(cmd_buffer, pipeline);
1083 radv_emit_fragment_shader(cmd_buffer, pipeline);
1084 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1085 radv_emit_binning_state(cmd_buffer, pipeline);
1086
1087 cmd_buffer->scratch_size_needed =
1088 MAX2(cmd_buffer->scratch_size_needed,
1089 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1090
1091 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1092 S_0286E8_WAVES(pipeline->max_waves) |
1093 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1094
1095 if (!cmd_buffer->state.emitted_pipeline ||
1096 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1097 pipeline->graphics.can_use_guardband)
1098 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1099
1100 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1101
1102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1103 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1104 } else {
1105 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1106 }
1107 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1108
1109 radeon_set_context_reg(cmd_buffer->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
1110
1111 if (unlikely(cmd_buffer->device->trace_bo))
1112 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1113
1114 cmd_buffer->state.emitted_pipeline = pipeline;
1115
1116 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1117 }
1118
1119 static void
1120 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1121 {
1122 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1123 cmd_buffer->state.dynamic.viewport.viewports);
1124 }
1125
1126 static void
1127 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1128 {
1129 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1130
1131 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1132 * scissor registers are changed. There is also a more efficient but
1133 * more involved alternative workaround.
1134 */
1135 if (cmd_buffer->device->physical_device->has_scissor_bug) {
1136 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1137 si_emit_cache_flush(cmd_buffer);
1138 }
1139 si_write_scissors(cmd_buffer->cs, 0, count,
1140 cmd_buffer->state.dynamic.scissor.scissors,
1141 cmd_buffer->state.dynamic.viewport.viewports,
1142 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1143 }
1144
1145 static void
1146 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1149 return;
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1152 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1153 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1154 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1155 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1156 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1157 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1158 }
1159 }
1160
1161 static void
1162 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1163 {
1164 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1165
1166 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1167 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1168 }
1169
1170 static void
1171 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1172 {
1173 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1174
1175 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1176 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1177 }
1178
1179 static void
1180 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1181 {
1182 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1183
1184 radeon_set_context_reg_seq(cmd_buffer->cs,
1185 R_028430_DB_STENCILREFMASK, 2);
1186 radeon_emit(cmd_buffer->cs,
1187 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1188 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1189 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1190 S_028430_STENCILOPVAL(1));
1191 radeon_emit(cmd_buffer->cs,
1192 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1193 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1194 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1195 S_028434_STENCILOPVAL_BF(1));
1196 }
1197
1198 static void
1199 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1200 {
1201 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1202
1203 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1204 fui(d->depth_bounds.min));
1205 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1206 fui(d->depth_bounds.max));
1207 }
1208
1209 static void
1210 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1211 {
1212 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1213 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1214 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1215 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1216
1217 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1218 radeon_set_context_reg_seq(cmd_buffer->cs,
1219 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1220 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1221 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1222 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1223 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1224 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1225 }
1226 }
1227
1228 static void
1229 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1230 int index,
1231 struct radv_attachment_info *att,
1232 struct radv_image *image,
1233 VkImageLayout layout)
1234 {
1235 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1236 struct radv_color_buffer_info *cb = &att->cb;
1237 uint32_t cb_color_info = cb->cb_color_info;
1238
1239 if (!radv_layout_dcc_compressed(image, layout,
1240 radv_image_queue_family_mask(image,
1241 cmd_buffer->queue_family_index,
1242 cmd_buffer->queue_family_index))) {
1243 cb_color_info &= C_028C70_DCC_ENABLE;
1244 }
1245
1246 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1247 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1248 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1249 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1250 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1251 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1252 radeon_emit(cmd_buffer->cs, cb_color_info);
1253 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1254 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1255 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1256 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1257 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1258 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1259
1260 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1261 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1262 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1263
1264 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1265 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1266 } else {
1267 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1268 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1270 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1271 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1272 radeon_emit(cmd_buffer->cs, cb_color_info);
1273 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1274 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1275 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1276 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1279
1280 if (is_vi) { /* DCC BASE */
1281 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1282 }
1283 }
1284 }
1285
1286 static void
1287 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1288 struct radv_ds_buffer_info *ds,
1289 struct radv_image *image,
1290 VkImageLayout layout)
1291 {
1292 uint32_t db_z_info = ds->db_z_info;
1293 uint32_t db_stencil_info = ds->db_stencil_info;
1294
1295 if (!radv_layout_has_htile(image, layout,
1296 radv_image_queue_family_mask(image,
1297 cmd_buffer->queue_family_index,
1298 cmd_buffer->queue_family_index))) {
1299 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1300 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1301 }
1302
1303 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1304 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1305
1306
1307 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1308 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1309 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1310 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1311 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1312
1313 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1314 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1315 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1316 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1317 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1318 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1319 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1320 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1321 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1322 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1323 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1324
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1326 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1327 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1328 } else {
1329 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1330
1331 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1332 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1333 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1334 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1335 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1336 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1337 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1338 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1339 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1340 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1341
1342 }
1343
1344 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1345 ds->pa_su_poly_offset_db_fmt_cntl);
1346 }
1347
1348 void
1349 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1350 struct radv_image *image,
1351 VkClearDepthStencilValue ds_clear_value,
1352 VkImageAspectFlags aspects)
1353 {
1354 uint64_t va = radv_buffer_get_va(image->bo);
1355 va += image->offset + image->clear_value_offset;
1356 unsigned reg_offset = 0, reg_count = 0;
1357
1358 assert(image->surface.htile_size);
1359
1360 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1361 ++reg_count;
1362 } else {
1363 ++reg_offset;
1364 va += 4;
1365 }
1366 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1367 ++reg_count;
1368
1369 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1370 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1371 S_370_WR_CONFIRM(1) |
1372 S_370_ENGINE_SEL(V_370_PFP));
1373 radeon_emit(cmd_buffer->cs, va);
1374 radeon_emit(cmd_buffer->cs, va >> 32);
1375 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1376 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1377 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1378 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1379
1380 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1381 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1382 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1383 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1384 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1385 }
1386
1387 static void
1388 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1389 struct radv_image *image)
1390 {
1391 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1392 uint64_t va = radv_buffer_get_va(image->bo);
1393 va += image->offset + image->clear_value_offset;
1394 unsigned reg_offset = 0, reg_count = 0;
1395
1396 if (!image->surface.htile_size)
1397 return;
1398
1399 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1400 ++reg_count;
1401 } else {
1402 ++reg_offset;
1403 va += 4;
1404 }
1405 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1406 ++reg_count;
1407
1408 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1409 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1410 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1411 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1412 radeon_emit(cmd_buffer->cs, va);
1413 radeon_emit(cmd_buffer->cs, va >> 32);
1414 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1415 radeon_emit(cmd_buffer->cs, 0);
1416
1417 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1418 radeon_emit(cmd_buffer->cs, 0);
1419 }
1420
1421 /*
1422 *with DCC some colors don't require CMASK elimiation before being
1423 * used as a texture. This sets a predicate value to determine if the
1424 * cmask eliminate is required.
1425 */
1426 void
1427 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1428 struct radv_image *image,
1429 bool value)
1430 {
1431 uint64_t pred_val = value;
1432 uint64_t va = radv_buffer_get_va(image->bo);
1433 va += image->offset + image->dcc_pred_offset;
1434
1435 assert(image->surface.dcc_size);
1436
1437 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1438 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1439 S_370_WR_CONFIRM(1) |
1440 S_370_ENGINE_SEL(V_370_PFP));
1441 radeon_emit(cmd_buffer->cs, va);
1442 radeon_emit(cmd_buffer->cs, va >> 32);
1443 radeon_emit(cmd_buffer->cs, pred_val);
1444 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1445 }
1446
1447 void
1448 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1449 struct radv_image *image,
1450 int idx,
1451 uint32_t color_values[2])
1452 {
1453 uint64_t va = radv_buffer_get_va(image->bo);
1454 va += image->offset + image->clear_value_offset;
1455
1456 assert(image->cmask.size || image->surface.dcc_size);
1457
1458 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1459 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1460 S_370_WR_CONFIRM(1) |
1461 S_370_ENGINE_SEL(V_370_PFP));
1462 radeon_emit(cmd_buffer->cs, va);
1463 radeon_emit(cmd_buffer->cs, va >> 32);
1464 radeon_emit(cmd_buffer->cs, color_values[0]);
1465 radeon_emit(cmd_buffer->cs, color_values[1]);
1466
1467 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1468 radeon_emit(cmd_buffer->cs, color_values[0]);
1469 radeon_emit(cmd_buffer->cs, color_values[1]);
1470 }
1471
1472 static void
1473 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1474 struct radv_image *image,
1475 int idx)
1476 {
1477 uint64_t va = radv_buffer_get_va(image->bo);
1478 va += image->offset + image->clear_value_offset;
1479
1480 if (!image->cmask.size && !image->surface.dcc_size)
1481 return;
1482
1483 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1484
1485 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1486 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1487 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1488 COPY_DATA_COUNT_SEL);
1489 radeon_emit(cmd_buffer->cs, va);
1490 radeon_emit(cmd_buffer->cs, va >> 32);
1491 radeon_emit(cmd_buffer->cs, reg >> 2);
1492 radeon_emit(cmd_buffer->cs, 0);
1493
1494 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1495 radeon_emit(cmd_buffer->cs, 0);
1496 }
1497
1498 static void
1499 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1500 {
1501 int i;
1502 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1503 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1504
1505 /* this may happen for inherited secondary recording */
1506 if (!framebuffer)
1507 return;
1508
1509 for (i = 0; i < 8; ++i) {
1510 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1511 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1512 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1513 continue;
1514 }
1515
1516 int idx = subpass->color_attachments[i].attachment;
1517 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1518 struct radv_image *image = att->attachment->image;
1519 VkImageLayout layout = subpass->color_attachments[i].layout;
1520
1521 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1522
1523 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1524 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1525
1526 radv_load_color_clear_regs(cmd_buffer, image, i);
1527 }
1528
1529 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1530 int idx = subpass->depth_stencil_attachment.attachment;
1531 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1532 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1533 struct radv_image *image = att->attachment->image;
1534 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1535 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1536 cmd_buffer->queue_family_index,
1537 cmd_buffer->queue_family_index);
1538 /* We currently don't support writing decompressed HTILE */
1539 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1540 radv_layout_is_htile_compressed(image, layout, queue_mask));
1541
1542 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1543
1544 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1545 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1546 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1547 }
1548 radv_load_depth_clear_regs(cmd_buffer, image);
1549 } else {
1550 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1551 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1552 else
1553 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1554
1555 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1556 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1557 }
1558 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1559 S_028208_BR_X(framebuffer->width) |
1560 S_028208_BR_Y(framebuffer->height));
1561
1562 if (cmd_buffer->device->dfsm_allowed) {
1563 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1564 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1565 }
1566
1567 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1568 }
1569
1570 static void
1571 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1572 {
1573 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1574 struct radv_cmd_state *state = &cmd_buffer->state;
1575
1576 if (state->index_type != state->last_index_type) {
1577 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1578 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1579 2, state->index_type);
1580 } else {
1581 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1582 radeon_emit(cs, state->index_type);
1583 }
1584
1585 state->last_index_type = state->index_type;
1586 }
1587
1588 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1589 radeon_emit(cs, state->index_va);
1590 radeon_emit(cs, state->index_va >> 32);
1591
1592 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1593 radeon_emit(cs, state->max_index_count);
1594
1595 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1596 }
1597
1598 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1599 {
1600 uint32_t db_count_control;
1601
1602 if(!cmd_buffer->state.active_occlusion_queries) {
1603 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1604 db_count_control = 0;
1605 } else {
1606 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1607 }
1608 } else {
1609 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1610 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1611 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1612 S_028004_ZPASS_ENABLE(1) |
1613 S_028004_SLICE_EVEN_ENABLE(1) |
1614 S_028004_SLICE_ODD_ENABLE(1);
1615 } else {
1616 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1617 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1618 }
1619 }
1620
1621 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1622 }
1623
1624 static void
1625 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1626 {
1627 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1628 return;
1629
1630 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1631 radv_emit_viewport(cmd_buffer);
1632
1633 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1634 radv_emit_scissor(cmd_buffer);
1635
1636 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1637 radv_emit_line_width(cmd_buffer);
1638
1639 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1640 radv_emit_blend_constants(cmd_buffer);
1641
1642 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1643 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1644 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1645 radv_emit_stencil(cmd_buffer);
1646
1647 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1648 radv_emit_depth_bounds(cmd_buffer);
1649
1650 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1651 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1652 radv_emit_depth_bias(cmd_buffer);
1653
1654 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1655 radv_emit_discard_rectangle(cmd_buffer);
1656
1657 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1658 }
1659
1660 static void
1661 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1662 struct radv_pipeline *pipeline,
1663 int idx,
1664 uint64_t va,
1665 gl_shader_stage stage)
1666 {
1667 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1668 uint32_t base_reg = pipeline->user_data_0[stage];
1669
1670 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1671 return;
1672
1673 assert(!desc_set_loc->indirect);
1674 assert(desc_set_loc->num_sgprs == 2);
1675 radeon_set_sh_reg_seq(cmd_buffer->cs,
1676 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1677 radeon_emit(cmd_buffer->cs, va);
1678 radeon_emit(cmd_buffer->cs, va >> 32);
1679 }
1680
1681 static void
1682 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1683 VkShaderStageFlags stages,
1684 struct radv_descriptor_set *set,
1685 unsigned idx)
1686 {
1687 if (cmd_buffer->state.pipeline) {
1688 radv_foreach_stage(stage, stages) {
1689 if (cmd_buffer->state.pipeline->shaders[stage])
1690 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1691 idx, set->va,
1692 stage);
1693 }
1694 }
1695
1696 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1697 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1698 idx, set->va,
1699 MESA_SHADER_COMPUTE);
1700 }
1701
1702 static void
1703 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1704 {
1705 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1706 unsigned bo_offset;
1707
1708 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1709 set->mapped_ptr,
1710 &bo_offset))
1711 return;
1712
1713 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1714 set->va += bo_offset;
1715 }
1716
1717 static void
1718 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1719 {
1720 uint32_t size = MAX_SETS * 2 * 4;
1721 uint32_t offset;
1722 void *ptr;
1723
1724 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1725 256, &offset, &ptr))
1726 return;
1727
1728 for (unsigned i = 0; i < MAX_SETS; i++) {
1729 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1730 uint64_t set_va = 0;
1731 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1732 if (cmd_buffer->state.valid_descriptors & (1u << i))
1733 set_va = set->va;
1734 uptr[0] = set_va & 0xffffffff;
1735 uptr[1] = set_va >> 32;
1736 }
1737
1738 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1739 va += offset;
1740
1741 if (cmd_buffer->state.pipeline) {
1742 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1743 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1744 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1745
1746 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1747 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1748 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1749
1750 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1751 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1752 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1753
1754 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1755 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1756 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1757
1758 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1759 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1760 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1761 }
1762
1763 if (cmd_buffer->state.compute_pipeline)
1764 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1765 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1766 }
1767
1768 static void
1769 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1770 VkShaderStageFlags stages)
1771 {
1772 unsigned i;
1773
1774 if (!cmd_buffer->state.descriptors_dirty)
1775 return;
1776
1777 if (cmd_buffer->state.push_descriptors_dirty)
1778 radv_flush_push_descriptors(cmd_buffer);
1779
1780 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1781 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1782 radv_flush_indirect_descriptor_sets(cmd_buffer);
1783 }
1784
1785 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1786 cmd_buffer->cs,
1787 MAX_SETS * MESA_SHADER_STAGES * 4);
1788
1789 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1790 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1791 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1792 continue;
1793
1794 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1795 }
1796 cmd_buffer->state.descriptors_dirty = 0;
1797 cmd_buffer->state.push_descriptors_dirty = false;
1798
1799 if (unlikely(cmd_buffer->device->trace_bo))
1800 radv_save_descriptors(cmd_buffer);
1801
1802 assert(cmd_buffer->cs->cdw <= cdw_max);
1803 }
1804
1805 static void
1806 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1807 struct radv_pipeline *pipeline,
1808 VkShaderStageFlags stages)
1809 {
1810 struct radv_pipeline_layout *layout = pipeline->layout;
1811 unsigned offset;
1812 void *ptr;
1813 uint64_t va;
1814
1815 stages &= cmd_buffer->push_constant_stages;
1816 if (!stages ||
1817 (!layout->push_constant_size && !layout->dynamic_offset_count))
1818 return;
1819
1820 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1821 16 * layout->dynamic_offset_count,
1822 256, &offset, &ptr))
1823 return;
1824
1825 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1826 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1827 16 * layout->dynamic_offset_count);
1828
1829 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1830 va += offset;
1831
1832 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1833 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1834
1835 radv_foreach_stage(stage, stages) {
1836 if (pipeline->shaders[stage]) {
1837 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1838 AC_UD_PUSH_CONSTANTS, va);
1839 }
1840 }
1841
1842 cmd_buffer->push_constant_stages &= ~stages;
1843 assert(cmd_buffer->cs->cdw <= cdw_max);
1844 }
1845
1846 static bool
1847 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1848 {
1849 if ((pipeline_is_dirty ||
1850 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1851 cmd_buffer->state.pipeline->vertex_elements.count &&
1852 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1853 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1854 unsigned vb_offset;
1855 void *vb_ptr;
1856 uint32_t i = 0;
1857 uint32_t count = velems->count;
1858 uint64_t va;
1859
1860 /* allocate some descriptor state for vertex buffers */
1861 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1862 &vb_offset, &vb_ptr))
1863 return false;
1864
1865 for (i = 0; i < count; i++) {
1866 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1867 uint32_t offset;
1868 int vb = velems->binding[i];
1869 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1870 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1871
1872 va = radv_buffer_get_va(buffer->bo);
1873
1874 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1875 va += offset + buffer->offset;
1876 desc[0] = va;
1877 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1878 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1879 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1880 else
1881 desc[2] = buffer->size - offset;
1882 desc[3] = velems->rsrc_word3[i];
1883 }
1884
1885 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1886 va += vb_offset;
1887
1888 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1889 AC_UD_VS_VERTEX_BUFFERS, va);
1890
1891 cmd_buffer->state.vb_va = va;
1892 cmd_buffer->state.vb_size = count * 16;
1893 cmd_buffer->state.vb_prefetch_dirty = true;
1894 }
1895 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1896
1897 return true;
1898 }
1899
1900 static bool
1901 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1902 {
1903 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1904 return false;
1905
1906 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1907 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1908 VK_SHADER_STAGE_ALL_GRAPHICS);
1909
1910 return true;
1911 }
1912
1913 static void
1914 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1915 bool instanced_draw, bool indirect_draw,
1916 uint32_t draw_vertex_count)
1917 {
1918 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1919 struct radv_cmd_state *state = &cmd_buffer->state;
1920 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1921 uint32_t ia_multi_vgt_param;
1922 int32_t primitive_reset_en;
1923
1924 /* Draw state. */
1925 ia_multi_vgt_param =
1926 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1927 indirect_draw, draw_vertex_count);
1928
1929 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1930 if (info->chip_class >= GFX9) {
1931 radeon_set_uconfig_reg_idx(cs,
1932 R_030960_IA_MULTI_VGT_PARAM,
1933 4, ia_multi_vgt_param);
1934 } else if (info->chip_class >= CIK) {
1935 radeon_set_context_reg_idx(cs,
1936 R_028AA8_IA_MULTI_VGT_PARAM,
1937 1, ia_multi_vgt_param);
1938 } else {
1939 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1940 ia_multi_vgt_param);
1941 }
1942 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1943 }
1944
1945 /* Primitive restart. */
1946 primitive_reset_en =
1947 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1948
1949 if (primitive_reset_en != state->last_primitive_reset_en) {
1950 state->last_primitive_reset_en = primitive_reset_en;
1951 if (info->chip_class >= GFX9) {
1952 radeon_set_uconfig_reg(cs,
1953 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1954 primitive_reset_en);
1955 } else {
1956 radeon_set_context_reg(cs,
1957 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1958 primitive_reset_en);
1959 }
1960 }
1961
1962 if (primitive_reset_en) {
1963 uint32_t primitive_reset_index =
1964 state->index_type ? 0xffffffffu : 0xffffu;
1965
1966 if (primitive_reset_index != state->last_primitive_reset_index) {
1967 radeon_set_context_reg(cs,
1968 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1969 primitive_reset_index);
1970 state->last_primitive_reset_index = primitive_reset_index;
1971 }
1972 }
1973 }
1974
1975 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1976 VkPipelineStageFlags src_stage_mask)
1977 {
1978 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1979 VK_PIPELINE_STAGE_TRANSFER_BIT |
1980 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1981 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1982 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1983 }
1984
1985 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1986 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1987 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1988 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1989 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1990 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1991 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1992 VK_PIPELINE_STAGE_TRANSFER_BIT |
1993 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1994 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1995 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1996 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1997 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1998 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1999 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
2000 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2001 }
2002 }
2003
2004 static enum radv_cmd_flush_bits
2005 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2006 VkAccessFlags src_flags)
2007 {
2008 enum radv_cmd_flush_bits flush_bits = 0;
2009 uint32_t b;
2010 for_each_bit(b, src_flags) {
2011 switch ((VkAccessFlagBits)(1 << b)) {
2012 case VK_ACCESS_SHADER_WRITE_BIT:
2013 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2014 break;
2015 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2016 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2017 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2018 break;
2019 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2020 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2021 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2022 break;
2023 case VK_ACCESS_TRANSFER_WRITE_BIT:
2024 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2025 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2026 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2027 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2028 RADV_CMD_FLAG_INV_GLOBAL_L2;
2029 break;
2030 default:
2031 break;
2032 }
2033 }
2034 return flush_bits;
2035 }
2036
2037 static enum radv_cmd_flush_bits
2038 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2039 VkAccessFlags dst_flags,
2040 struct radv_image *image)
2041 {
2042 enum radv_cmd_flush_bits flush_bits = 0;
2043 uint32_t b;
2044 for_each_bit(b, dst_flags) {
2045 switch ((VkAccessFlagBits)(1 << b)) {
2046 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2047 case VK_ACCESS_INDEX_READ_BIT:
2048 break;
2049 case VK_ACCESS_UNIFORM_READ_BIT:
2050 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2051 break;
2052 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2053 case VK_ACCESS_SHADER_READ_BIT:
2054 case VK_ACCESS_TRANSFER_READ_BIT:
2055 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2056 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2057 RADV_CMD_FLAG_INV_GLOBAL_L2;
2058 break;
2059 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2060 /* TODO: change to image && when the image gets passed
2061 * through from the subpass. */
2062 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2063 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2064 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2065 break;
2066 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2067 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2068 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2069 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2070 break;
2071 default:
2072 break;
2073 }
2074 }
2075 return flush_bits;
2076 }
2077
2078 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2079 {
2080 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2081 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2082 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2083 NULL);
2084 }
2085
2086 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2087 VkAttachmentReference att)
2088 {
2089 unsigned idx = att.attachment;
2090 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2091 VkImageSubresourceRange range;
2092 range.aspectMask = 0;
2093 range.baseMipLevel = view->base_mip;
2094 range.levelCount = 1;
2095 range.baseArrayLayer = view->base_layer;
2096 range.layerCount = cmd_buffer->state.framebuffer->layers;
2097
2098 radv_handle_image_transition(cmd_buffer,
2099 view->image,
2100 cmd_buffer->state.attachments[idx].current_layout,
2101 att.layout, 0, 0, &range,
2102 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2103
2104 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2105
2106
2107 }
2108
2109 void
2110 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2111 const struct radv_subpass *subpass, bool transitions)
2112 {
2113 if (transitions) {
2114 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2115
2116 for (unsigned i = 0; i < subpass->color_count; ++i) {
2117 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2118 radv_handle_subpass_image_transition(cmd_buffer,
2119 subpass->color_attachments[i]);
2120 }
2121
2122 for (unsigned i = 0; i < subpass->input_count; ++i) {
2123 radv_handle_subpass_image_transition(cmd_buffer,
2124 subpass->input_attachments[i]);
2125 }
2126
2127 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2128 radv_handle_subpass_image_transition(cmd_buffer,
2129 subpass->depth_stencil_attachment);
2130 }
2131 }
2132
2133 cmd_buffer->state.subpass = subpass;
2134
2135 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2136 }
2137
2138 static VkResult
2139 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2140 struct radv_render_pass *pass,
2141 const VkRenderPassBeginInfo *info)
2142 {
2143 struct radv_cmd_state *state = &cmd_buffer->state;
2144
2145 if (pass->attachment_count == 0) {
2146 state->attachments = NULL;
2147 return VK_SUCCESS;
2148 }
2149
2150 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2151 pass->attachment_count *
2152 sizeof(state->attachments[0]),
2153 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2154 if (state->attachments == NULL) {
2155 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2156 return cmd_buffer->record_result;
2157 }
2158
2159 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2160 struct radv_render_pass_attachment *att = &pass->attachments[i];
2161 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2162 VkImageAspectFlags clear_aspects = 0;
2163
2164 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2165 /* color attachment */
2166 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2167 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2168 }
2169 } else {
2170 /* depthstencil attachment */
2171 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2172 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2173 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2174 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2175 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2176 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2177 }
2178 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2179 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2180 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2181 }
2182 }
2183
2184 state->attachments[i].pending_clear_aspects = clear_aspects;
2185 state->attachments[i].cleared_views = 0;
2186 if (clear_aspects && info) {
2187 assert(info->clearValueCount > i);
2188 state->attachments[i].clear_value = info->pClearValues[i];
2189 }
2190
2191 state->attachments[i].current_layout = att->initial_layout;
2192 }
2193
2194 return VK_SUCCESS;
2195 }
2196
2197 VkResult radv_AllocateCommandBuffers(
2198 VkDevice _device,
2199 const VkCommandBufferAllocateInfo *pAllocateInfo,
2200 VkCommandBuffer *pCommandBuffers)
2201 {
2202 RADV_FROM_HANDLE(radv_device, device, _device);
2203 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2204
2205 VkResult result = VK_SUCCESS;
2206 uint32_t i;
2207
2208 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2209
2210 if (!list_empty(&pool->free_cmd_buffers)) {
2211 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2212
2213 list_del(&cmd_buffer->pool_link);
2214 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2215
2216 result = radv_reset_cmd_buffer(cmd_buffer);
2217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2218 cmd_buffer->level = pAllocateInfo->level;
2219
2220 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2221 } else {
2222 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2223 &pCommandBuffers[i]);
2224 }
2225 if (result != VK_SUCCESS)
2226 break;
2227 }
2228
2229 if (result != VK_SUCCESS) {
2230 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2231 i, pCommandBuffers);
2232
2233 /* From the Vulkan 1.0.66 spec:
2234 *
2235 * "vkAllocateCommandBuffers can be used to create multiple
2236 * command buffers. If the creation of any of those command
2237 * buffers fails, the implementation must destroy all
2238 * successfully created command buffer objects from this
2239 * command, set all entries of the pCommandBuffers array to
2240 * NULL and return the error."
2241 */
2242 memset(pCommandBuffers, 0,
2243 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2244 }
2245
2246 return result;
2247 }
2248
2249 void radv_FreeCommandBuffers(
2250 VkDevice device,
2251 VkCommandPool commandPool,
2252 uint32_t commandBufferCount,
2253 const VkCommandBuffer *pCommandBuffers)
2254 {
2255 for (uint32_t i = 0; i < commandBufferCount; i++) {
2256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2257
2258 if (cmd_buffer) {
2259 if (cmd_buffer->pool) {
2260 list_del(&cmd_buffer->pool_link);
2261 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2262 } else
2263 radv_cmd_buffer_destroy(cmd_buffer);
2264
2265 }
2266 }
2267 }
2268
2269 VkResult radv_ResetCommandBuffer(
2270 VkCommandBuffer commandBuffer,
2271 VkCommandBufferResetFlags flags)
2272 {
2273 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2274 return radv_reset_cmd_buffer(cmd_buffer);
2275 }
2276
2277 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2278 {
2279 struct radv_device *device = cmd_buffer->device;
2280 if (device->gfx_init) {
2281 uint64_t va = radv_buffer_get_va(device->gfx_init);
2282 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2283 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2284 radeon_emit(cmd_buffer->cs, va);
2285 radeon_emit(cmd_buffer->cs, va >> 32);
2286 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2287 } else
2288 si_init_config(cmd_buffer);
2289 }
2290
2291 VkResult radv_BeginCommandBuffer(
2292 VkCommandBuffer commandBuffer,
2293 const VkCommandBufferBeginInfo *pBeginInfo)
2294 {
2295 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2296 VkResult result = VK_SUCCESS;
2297
2298 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2299 /* If the command buffer has already been resetted with
2300 * vkResetCommandBuffer, no need to do it again.
2301 */
2302 result = radv_reset_cmd_buffer(cmd_buffer);
2303 if (result != VK_SUCCESS)
2304 return result;
2305 }
2306
2307 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2308 cmd_buffer->state.last_primitive_reset_en = -1;
2309 cmd_buffer->state.last_index_type = -1;
2310 cmd_buffer->state.last_num_instances = -1;
2311 cmd_buffer->state.last_vertex_offset = -1;
2312 cmd_buffer->state.last_first_instance = -1;
2313 cmd_buffer->usage_flags = pBeginInfo->flags;
2314
2315 /* setup initial configuration into command buffer */
2316 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2317 switch (cmd_buffer->queue_family_index) {
2318 case RADV_QUEUE_GENERAL:
2319 emit_gfx_buffer_state(cmd_buffer);
2320 break;
2321 case RADV_QUEUE_COMPUTE:
2322 si_init_compute(cmd_buffer);
2323 break;
2324 case RADV_QUEUE_TRANSFER:
2325 default:
2326 break;
2327 }
2328 }
2329
2330 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2331 assert(pBeginInfo->pInheritanceInfo);
2332 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2333 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2334
2335 struct radv_subpass *subpass =
2336 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2337
2338 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2339 if (result != VK_SUCCESS)
2340 return result;
2341
2342 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2343 }
2344
2345 if (unlikely(cmd_buffer->device->trace_bo))
2346 radv_cmd_buffer_trace_emit(cmd_buffer);
2347
2348 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2349
2350 return result;
2351 }
2352
2353 void radv_CmdBindVertexBuffers(
2354 VkCommandBuffer commandBuffer,
2355 uint32_t firstBinding,
2356 uint32_t bindingCount,
2357 const VkBuffer* pBuffers,
2358 const VkDeviceSize* pOffsets)
2359 {
2360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2361 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2362 bool changed = false;
2363
2364 /* We have to defer setting up vertex buffer since we need the buffer
2365 * stride from the pipeline. */
2366
2367 assert(firstBinding + bindingCount <= MAX_VBS);
2368 for (uint32_t i = 0; i < bindingCount; i++) {
2369 uint32_t idx = firstBinding + i;
2370
2371 if (!changed &&
2372 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2373 vb[idx].offset != pOffsets[i])) {
2374 changed = true;
2375 }
2376
2377 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2378 vb[idx].offset = pOffsets[i];
2379
2380 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2381 vb[idx].buffer->bo, 8);
2382 }
2383
2384 if (!changed) {
2385 /* No state changes. */
2386 return;
2387 }
2388
2389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2390 }
2391
2392 void radv_CmdBindIndexBuffer(
2393 VkCommandBuffer commandBuffer,
2394 VkBuffer buffer,
2395 VkDeviceSize offset,
2396 VkIndexType indexType)
2397 {
2398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2400
2401 if (cmd_buffer->state.index_buffer == index_buffer &&
2402 cmd_buffer->state.index_offset == offset &&
2403 cmd_buffer->state.index_type == indexType) {
2404 /* No state changes. */
2405 return;
2406 }
2407
2408 cmd_buffer->state.index_buffer = index_buffer;
2409 cmd_buffer->state.index_offset = offset;
2410 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2411 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2412 cmd_buffer->state.index_va += index_buffer->offset + offset;
2413
2414 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2415 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2416 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2417 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2418 }
2419
2420
2421 static void
2422 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2423 struct radv_descriptor_set *set, unsigned idx)
2424 {
2425 struct radeon_winsys *ws = cmd_buffer->device->ws;
2426
2427 radv_set_descriptor_set(cmd_buffer, set, idx);
2428 if (!set)
2429 return;
2430
2431 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2432
2433 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2434 if (set->descriptors[j])
2435 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2436
2437 if(set->bo)
2438 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2439 }
2440
2441 void radv_CmdBindDescriptorSets(
2442 VkCommandBuffer commandBuffer,
2443 VkPipelineBindPoint pipelineBindPoint,
2444 VkPipelineLayout _layout,
2445 uint32_t firstSet,
2446 uint32_t descriptorSetCount,
2447 const VkDescriptorSet* pDescriptorSets,
2448 uint32_t dynamicOffsetCount,
2449 const uint32_t* pDynamicOffsets)
2450 {
2451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2452 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2453 unsigned dyn_idx = 0;
2454
2455 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2456 unsigned idx = i + firstSet;
2457 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2458 radv_bind_descriptor_set(cmd_buffer, set, idx);
2459
2460 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2461 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2462 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2463 assert(dyn_idx < dynamicOffsetCount);
2464
2465 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2466 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2467 dst[0] = va;
2468 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2469 dst[2] = range->size;
2470 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2471 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2472 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2473 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2474 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2476 cmd_buffer->push_constant_stages |=
2477 set->layout->dynamic_shader_stages;
2478 }
2479 }
2480 }
2481
2482 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2483 struct radv_descriptor_set *set,
2484 struct radv_descriptor_set_layout *layout)
2485 {
2486 set->size = layout->size;
2487 set->layout = layout;
2488
2489 if (cmd_buffer->push_descriptors.capacity < set->size) {
2490 size_t new_size = MAX2(set->size, 1024);
2491 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2492 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2493
2494 free(set->mapped_ptr);
2495 set->mapped_ptr = malloc(new_size);
2496
2497 if (!set->mapped_ptr) {
2498 cmd_buffer->push_descriptors.capacity = 0;
2499 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2500 return false;
2501 }
2502
2503 cmd_buffer->push_descriptors.capacity = new_size;
2504 }
2505
2506 return true;
2507 }
2508
2509 void radv_meta_push_descriptor_set(
2510 struct radv_cmd_buffer* cmd_buffer,
2511 VkPipelineBindPoint pipelineBindPoint,
2512 VkPipelineLayout _layout,
2513 uint32_t set,
2514 uint32_t descriptorWriteCount,
2515 const VkWriteDescriptorSet* pDescriptorWrites)
2516 {
2517 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2518 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2519 unsigned bo_offset;
2520
2521 assert(set == 0);
2522 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2523
2524 push_set->size = layout->set[set].layout->size;
2525 push_set->layout = layout->set[set].layout;
2526
2527 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2528 &bo_offset,
2529 (void**) &push_set->mapped_ptr))
2530 return;
2531
2532 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2533 push_set->va += bo_offset;
2534
2535 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2536 radv_descriptor_set_to_handle(push_set),
2537 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2538
2539 radv_set_descriptor_set(cmd_buffer, push_set, set);
2540 }
2541
2542 void radv_CmdPushDescriptorSetKHR(
2543 VkCommandBuffer commandBuffer,
2544 VkPipelineBindPoint pipelineBindPoint,
2545 VkPipelineLayout _layout,
2546 uint32_t set,
2547 uint32_t descriptorWriteCount,
2548 const VkWriteDescriptorSet* pDescriptorWrites)
2549 {
2550 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2551 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2552 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2553
2554 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2555
2556 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2557 return;
2558
2559 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2560 radv_descriptor_set_to_handle(push_set),
2561 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2562
2563 radv_set_descriptor_set(cmd_buffer, push_set, set);
2564 cmd_buffer->state.push_descriptors_dirty = true;
2565 }
2566
2567 void radv_CmdPushDescriptorSetWithTemplateKHR(
2568 VkCommandBuffer commandBuffer,
2569 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2570 VkPipelineLayout _layout,
2571 uint32_t set,
2572 const void* pData)
2573 {
2574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2575 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2576 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2577
2578 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2579
2580 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2581 return;
2582
2583 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2584 descriptorUpdateTemplate, pData);
2585
2586 radv_set_descriptor_set(cmd_buffer, push_set, set);
2587 cmd_buffer->state.push_descriptors_dirty = true;
2588 }
2589
2590 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2591 VkPipelineLayout layout,
2592 VkShaderStageFlags stageFlags,
2593 uint32_t offset,
2594 uint32_t size,
2595 const void* pValues)
2596 {
2597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2598 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2599 cmd_buffer->push_constant_stages |= stageFlags;
2600 }
2601
2602 VkResult radv_EndCommandBuffer(
2603 VkCommandBuffer commandBuffer)
2604 {
2605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2606
2607 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2608 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2609 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2610 si_emit_cache_flush(cmd_buffer);
2611 }
2612
2613 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2614
2615 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2616 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2617
2618 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2619
2620 return cmd_buffer->record_result;
2621 }
2622
2623 static void
2624 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2625 {
2626 struct radv_shader_variant *compute_shader;
2627 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2628 struct radv_device *device = cmd_buffer->device;
2629 unsigned compute_resource_limits;
2630 unsigned waves_per_threadgroup;
2631 uint64_t va;
2632
2633 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2634 return;
2635
2636 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2637
2638 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2639 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2640
2641 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2642 cmd_buffer->cs, 19);
2643
2644 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2645 radeon_emit(cmd_buffer->cs, va >> 8);
2646 radeon_emit(cmd_buffer->cs, va >> 40);
2647
2648 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2649 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2650 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2651
2652
2653 cmd_buffer->compute_scratch_size_needed =
2654 MAX2(cmd_buffer->compute_scratch_size_needed,
2655 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2656
2657 /* change these once we have scratch support */
2658 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2659 S_00B860_WAVES(pipeline->max_waves) |
2660 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2661
2662 /* Calculate best compute resource limits. */
2663 waves_per_threadgroup =
2664 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2665 compute_shader->info.cs.block_size[1] *
2666 compute_shader->info.cs.block_size[2], 64);
2667 compute_resource_limits =
2668 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2669
2670 if (device->physical_device->rad_info.chip_class >= CIK) {
2671 unsigned num_cu_per_se =
2672 device->physical_device->rad_info.num_good_compute_units /
2673 device->physical_device->rad_info.max_se;
2674
2675 /* Force even distribution on all SIMDs in CU if the workgroup
2676 * size is 64. This has shown some good improvements if # of
2677 * CUs per SE is not a multiple of 4.
2678 */
2679 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2680 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2681 }
2682
2683 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2684 compute_resource_limits);
2685
2686 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2687 radeon_emit(cmd_buffer->cs,
2688 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2689 radeon_emit(cmd_buffer->cs,
2690 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2691 radeon_emit(cmd_buffer->cs,
2692 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2693
2694 assert(cmd_buffer->cs->cdw <= cdw_max);
2695
2696 if (unlikely(cmd_buffer->device->trace_bo))
2697 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2698 }
2699
2700 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2701 {
2702 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2703 }
2704
2705 void radv_CmdBindPipeline(
2706 VkCommandBuffer commandBuffer,
2707 VkPipelineBindPoint pipelineBindPoint,
2708 VkPipeline _pipeline)
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2712
2713 switch (pipelineBindPoint) {
2714 case VK_PIPELINE_BIND_POINT_COMPUTE:
2715 if (cmd_buffer->state.compute_pipeline == pipeline)
2716 return;
2717 radv_mark_descriptor_sets_dirty(cmd_buffer);
2718
2719 cmd_buffer->state.compute_pipeline = pipeline;
2720 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2721 break;
2722 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2723 if (cmd_buffer->state.pipeline == pipeline)
2724 return;
2725 radv_mark_descriptor_sets_dirty(cmd_buffer);
2726
2727 cmd_buffer->state.pipeline = pipeline;
2728 if (!pipeline)
2729 break;
2730
2731 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2732 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2733
2734 /* the new vertex shader might not have the same user regs */
2735 cmd_buffer->state.last_first_instance = -1;
2736 cmd_buffer->state.last_vertex_offset = -1;
2737
2738 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2739
2740 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2741 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2742 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2743 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2744
2745 if (radv_pipeline_has_tess(pipeline))
2746 cmd_buffer->tess_rings_needed = true;
2747
2748 if (radv_pipeline_has_gs(pipeline)) {
2749 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2750 AC_UD_SCRATCH_RING_OFFSETS);
2751 if (cmd_buffer->ring_offsets_idx == -1)
2752 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2753 else if (loc->sgpr_idx != -1)
2754 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2755 }
2756 break;
2757 default:
2758 assert(!"invalid bind point");
2759 break;
2760 }
2761 }
2762
2763 void radv_CmdSetViewport(
2764 VkCommandBuffer commandBuffer,
2765 uint32_t firstViewport,
2766 uint32_t viewportCount,
2767 const VkViewport* pViewports)
2768 {
2769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2770 struct radv_cmd_state *state = &cmd_buffer->state;
2771 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2772
2773 assert(firstViewport < MAX_VIEWPORTS);
2774 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2775
2776 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2777 /* Try to skip unnecessary PS partial flushes when the viewports
2778 * don't change.
2779 */
2780 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2781 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2782 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2783 pViewports, viewportCount * sizeof(*pViewports))) {
2784 return;
2785 }
2786 }
2787
2788 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2789 viewportCount * sizeof(*pViewports));
2790
2791 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2792 }
2793
2794 void radv_CmdSetScissor(
2795 VkCommandBuffer commandBuffer,
2796 uint32_t firstScissor,
2797 uint32_t scissorCount,
2798 const VkRect2D* pScissors)
2799 {
2800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2801 struct radv_cmd_state *state = &cmd_buffer->state;
2802 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2803
2804 assert(firstScissor < MAX_SCISSORS);
2805 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2806
2807 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2808 /* Try to skip unnecessary PS partial flushes when the scissors
2809 * don't change.
2810 */
2811 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2812 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2813 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2814 pScissors, scissorCount * sizeof(*pScissors))) {
2815 return;
2816 }
2817 }
2818
2819 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2820 scissorCount * sizeof(*pScissors));
2821
2822 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2823 }
2824
2825 void radv_CmdSetLineWidth(
2826 VkCommandBuffer commandBuffer,
2827 float lineWidth)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2830 cmd_buffer->state.dynamic.line_width = lineWidth;
2831 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2832 }
2833
2834 void radv_CmdSetDepthBias(
2835 VkCommandBuffer commandBuffer,
2836 float depthBiasConstantFactor,
2837 float depthBiasClamp,
2838 float depthBiasSlopeFactor)
2839 {
2840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2841
2842 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2843 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2844 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2845
2846 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2847 }
2848
2849 void radv_CmdSetBlendConstants(
2850 VkCommandBuffer commandBuffer,
2851 const float blendConstants[4])
2852 {
2853 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2854
2855 memcpy(cmd_buffer->state.dynamic.blend_constants,
2856 blendConstants, sizeof(float) * 4);
2857
2858 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2859 }
2860
2861 void radv_CmdSetDepthBounds(
2862 VkCommandBuffer commandBuffer,
2863 float minDepthBounds,
2864 float maxDepthBounds)
2865 {
2866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2867
2868 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2869 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2870
2871 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2872 }
2873
2874 void radv_CmdSetStencilCompareMask(
2875 VkCommandBuffer commandBuffer,
2876 VkStencilFaceFlags faceMask,
2877 uint32_t compareMask)
2878 {
2879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2880
2881 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2882 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2883 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2884 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2885
2886 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2887 }
2888
2889 void radv_CmdSetStencilWriteMask(
2890 VkCommandBuffer commandBuffer,
2891 VkStencilFaceFlags faceMask,
2892 uint32_t writeMask)
2893 {
2894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2895
2896 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2897 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2898 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2899 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2900
2901 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2902 }
2903
2904 void radv_CmdSetStencilReference(
2905 VkCommandBuffer commandBuffer,
2906 VkStencilFaceFlags faceMask,
2907 uint32_t reference)
2908 {
2909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2910
2911 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2912 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2913 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2914 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2915
2916 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2917 }
2918
2919 void radv_CmdSetDiscardRectangleEXT(
2920 VkCommandBuffer commandBuffer,
2921 uint32_t firstDiscardRectangle,
2922 uint32_t discardRectangleCount,
2923 const VkRect2D* pDiscardRectangles)
2924 {
2925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2926 struct radv_cmd_state *state = &cmd_buffer->state;
2927 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2928
2929 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2930 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2931
2932 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2933 pDiscardRectangles, discardRectangleCount);
2934
2935 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2936 }
2937
2938 void radv_CmdExecuteCommands(
2939 VkCommandBuffer commandBuffer,
2940 uint32_t commandBufferCount,
2941 const VkCommandBuffer* pCmdBuffers)
2942 {
2943 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2944
2945 assert(commandBufferCount > 0);
2946
2947 /* Emit pending flushes on primary prior to executing secondary */
2948 si_emit_cache_flush(primary);
2949
2950 for (uint32_t i = 0; i < commandBufferCount; i++) {
2951 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2952
2953 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2954 secondary->scratch_size_needed);
2955 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2956 secondary->compute_scratch_size_needed);
2957
2958 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2959 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2960 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2961 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2962 if (secondary->tess_rings_needed)
2963 primary->tess_rings_needed = true;
2964 if (secondary->sample_positions_needed)
2965 primary->sample_positions_needed = true;
2966
2967 if (secondary->ring_offsets_idx != -1) {
2968 if (primary->ring_offsets_idx == -1)
2969 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2970 else
2971 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2972 }
2973 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2974
2975
2976 /* When the secondary command buffer is compute only we don't
2977 * need to re-emit the current graphics pipeline.
2978 */
2979 if (secondary->state.emitted_pipeline) {
2980 primary->state.emitted_pipeline =
2981 secondary->state.emitted_pipeline;
2982 }
2983
2984 /* When the secondary command buffer is graphics only we don't
2985 * need to re-emit the current compute pipeline.
2986 */
2987 if (secondary->state.emitted_compute_pipeline) {
2988 primary->state.emitted_compute_pipeline =
2989 secondary->state.emitted_compute_pipeline;
2990 }
2991
2992 /* Only re-emit the draw packets when needed. */
2993 if (secondary->state.last_primitive_reset_en != -1) {
2994 primary->state.last_primitive_reset_en =
2995 secondary->state.last_primitive_reset_en;
2996 }
2997
2998 if (secondary->state.last_primitive_reset_index) {
2999 primary->state.last_primitive_reset_index =
3000 secondary->state.last_primitive_reset_index;
3001 }
3002
3003 if (secondary->state.last_ia_multi_vgt_param) {
3004 primary->state.last_ia_multi_vgt_param =
3005 secondary->state.last_ia_multi_vgt_param;
3006 }
3007
3008 if (secondary->state.last_first_instance != -1) {
3009 primary->state.last_first_instance =
3010 secondary->state.last_first_instance;
3011 }
3012
3013 if (secondary->state.last_num_instances != -1) {
3014 primary->state.last_num_instances =
3015 secondary->state.last_num_instances;
3016 }
3017
3018 if (secondary->state.last_vertex_offset != -1) {
3019 primary->state.last_vertex_offset =
3020 secondary->state.last_vertex_offset;
3021 }
3022
3023 if (secondary->state.last_index_type != -1) {
3024 primary->state.last_index_type =
3025 secondary->state.last_index_type;
3026 }
3027 }
3028
3029 /* After executing commands from secondary buffers we have to dirty
3030 * some states.
3031 */
3032 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3033 RADV_CMD_DIRTY_INDEX_BUFFER |
3034 RADV_CMD_DIRTY_DYNAMIC_ALL;
3035 radv_mark_descriptor_sets_dirty(primary);
3036 }
3037
3038 VkResult radv_CreateCommandPool(
3039 VkDevice _device,
3040 const VkCommandPoolCreateInfo* pCreateInfo,
3041 const VkAllocationCallbacks* pAllocator,
3042 VkCommandPool* pCmdPool)
3043 {
3044 RADV_FROM_HANDLE(radv_device, device, _device);
3045 struct radv_cmd_pool *pool;
3046
3047 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3048 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3049 if (pool == NULL)
3050 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3051
3052 if (pAllocator)
3053 pool->alloc = *pAllocator;
3054 else
3055 pool->alloc = device->alloc;
3056
3057 list_inithead(&pool->cmd_buffers);
3058 list_inithead(&pool->free_cmd_buffers);
3059
3060 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3061
3062 *pCmdPool = radv_cmd_pool_to_handle(pool);
3063
3064 return VK_SUCCESS;
3065
3066 }
3067
3068 void radv_DestroyCommandPool(
3069 VkDevice _device,
3070 VkCommandPool commandPool,
3071 const VkAllocationCallbacks* pAllocator)
3072 {
3073 RADV_FROM_HANDLE(radv_device, device, _device);
3074 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3075
3076 if (!pool)
3077 return;
3078
3079 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3080 &pool->cmd_buffers, pool_link) {
3081 radv_cmd_buffer_destroy(cmd_buffer);
3082 }
3083
3084 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3085 &pool->free_cmd_buffers, pool_link) {
3086 radv_cmd_buffer_destroy(cmd_buffer);
3087 }
3088
3089 vk_free2(&device->alloc, pAllocator, pool);
3090 }
3091
3092 VkResult radv_ResetCommandPool(
3093 VkDevice device,
3094 VkCommandPool commandPool,
3095 VkCommandPoolResetFlags flags)
3096 {
3097 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3098 VkResult result;
3099
3100 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3101 &pool->cmd_buffers, pool_link) {
3102 result = radv_reset_cmd_buffer(cmd_buffer);
3103 if (result != VK_SUCCESS)
3104 return result;
3105 }
3106
3107 return VK_SUCCESS;
3108 }
3109
3110 void radv_TrimCommandPoolKHR(
3111 VkDevice device,
3112 VkCommandPool commandPool,
3113 VkCommandPoolTrimFlagsKHR flags)
3114 {
3115 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3116
3117 if (!pool)
3118 return;
3119
3120 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3121 &pool->free_cmd_buffers, pool_link) {
3122 radv_cmd_buffer_destroy(cmd_buffer);
3123 }
3124 }
3125
3126 void radv_CmdBeginRenderPass(
3127 VkCommandBuffer commandBuffer,
3128 const VkRenderPassBeginInfo* pRenderPassBegin,
3129 VkSubpassContents contents)
3130 {
3131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3132 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3133 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3134
3135 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3136 cmd_buffer->cs, 2048);
3137 MAYBE_UNUSED VkResult result;
3138
3139 cmd_buffer->state.framebuffer = framebuffer;
3140 cmd_buffer->state.pass = pass;
3141 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3142
3143 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3144 if (result != VK_SUCCESS)
3145 return;
3146
3147 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3148 assert(cmd_buffer->cs->cdw <= cdw_max);
3149
3150 radv_cmd_buffer_clear_subpass(cmd_buffer);
3151 }
3152
3153 void radv_CmdNextSubpass(
3154 VkCommandBuffer commandBuffer,
3155 VkSubpassContents contents)
3156 {
3157 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3158
3159 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3160
3161 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3162 2048);
3163
3164 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3165 radv_cmd_buffer_clear_subpass(cmd_buffer);
3166 }
3167
3168 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3169 {
3170 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3171 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3172 if (!pipeline->shaders[stage])
3173 continue;
3174 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3175 if (loc->sgpr_idx == -1)
3176 continue;
3177 uint32_t base_reg = pipeline->user_data_0[stage];
3178 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3179
3180 }
3181 if (pipeline->gs_copy_shader) {
3182 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3183 if (loc->sgpr_idx != -1) {
3184 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3185 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3186 }
3187 }
3188 }
3189
3190 static void
3191 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3192 uint32_t vertex_count)
3193 {
3194 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3195 radeon_emit(cmd_buffer->cs, vertex_count);
3196 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3197 S_0287F0_USE_OPAQUE(0));
3198 }
3199
3200 static void
3201 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3202 uint64_t index_va,
3203 uint32_t index_count)
3204 {
3205 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3206 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3207 radeon_emit(cmd_buffer->cs, index_va);
3208 radeon_emit(cmd_buffer->cs, index_va >> 32);
3209 radeon_emit(cmd_buffer->cs, index_count);
3210 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3211 }
3212
3213 static void
3214 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3215 bool indexed,
3216 uint32_t draw_count,
3217 uint64_t count_va,
3218 uint32_t stride)
3219 {
3220 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3221 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3222 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3223 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3224 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3225 assert(base_reg);
3226
3227 /* just reset draw state for vertex data */
3228 cmd_buffer->state.last_first_instance = -1;
3229 cmd_buffer->state.last_num_instances = -1;
3230 cmd_buffer->state.last_vertex_offset = -1;
3231
3232 if (draw_count == 1 && !count_va && !draw_id_enable) {
3233 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3234 PKT3_DRAW_INDIRECT, 3, false));
3235 radeon_emit(cs, 0);
3236 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3237 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3238 radeon_emit(cs, di_src_sel);
3239 } else {
3240 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3241 PKT3_DRAW_INDIRECT_MULTI,
3242 8, false));
3243 radeon_emit(cs, 0);
3244 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3245 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3246 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3247 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3248 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3249 radeon_emit(cs, draw_count); /* count */
3250 radeon_emit(cs, count_va); /* count_addr */
3251 radeon_emit(cs, count_va >> 32);
3252 radeon_emit(cs, stride); /* stride */
3253 radeon_emit(cs, di_src_sel);
3254 }
3255 }
3256
3257 struct radv_draw_info {
3258 /**
3259 * Number of vertices.
3260 */
3261 uint32_t count;
3262
3263 /**
3264 * Index of the first vertex.
3265 */
3266 int32_t vertex_offset;
3267
3268 /**
3269 * First instance id.
3270 */
3271 uint32_t first_instance;
3272
3273 /**
3274 * Number of instances.
3275 */
3276 uint32_t instance_count;
3277
3278 /**
3279 * First index (indexed draws only).
3280 */
3281 uint32_t first_index;
3282
3283 /**
3284 * Whether it's an indexed draw.
3285 */
3286 bool indexed;
3287
3288 /**
3289 * Indirect draw parameters resource.
3290 */
3291 struct radv_buffer *indirect;
3292 uint64_t indirect_offset;
3293 uint32_t stride;
3294
3295 /**
3296 * Draw count parameters resource.
3297 */
3298 struct radv_buffer *count_buffer;
3299 uint64_t count_buffer_offset;
3300 };
3301
3302 static void
3303 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3304 const struct radv_draw_info *info)
3305 {
3306 struct radv_cmd_state *state = &cmd_buffer->state;
3307 struct radeon_winsys *ws = cmd_buffer->device->ws;
3308 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3309
3310 if (info->indirect) {
3311 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3312 uint64_t count_va = 0;
3313
3314 va += info->indirect->offset + info->indirect_offset;
3315
3316 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3317
3318 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3319 radeon_emit(cs, 1);
3320 radeon_emit(cs, va);
3321 radeon_emit(cs, va >> 32);
3322
3323 if (info->count_buffer) {
3324 count_va = radv_buffer_get_va(info->count_buffer->bo);
3325 count_va += info->count_buffer->offset +
3326 info->count_buffer_offset;
3327
3328 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3329 }
3330
3331 if (!state->subpass->view_mask) {
3332 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3333 info->indexed,
3334 info->count,
3335 count_va,
3336 info->stride);
3337 } else {
3338 unsigned i;
3339 for_each_bit(i, state->subpass->view_mask) {
3340 radv_emit_view_index(cmd_buffer, i);
3341
3342 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3343 info->indexed,
3344 info->count,
3345 count_va,
3346 info->stride);
3347 }
3348 }
3349 } else {
3350 assert(state->pipeline->graphics.vtx_base_sgpr);
3351
3352 if (info->vertex_offset != state->last_vertex_offset ||
3353 info->first_instance != state->last_first_instance) {
3354 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3355 state->pipeline->graphics.vtx_emit_num);
3356
3357 radeon_emit(cs, info->vertex_offset);
3358 radeon_emit(cs, info->first_instance);
3359 if (state->pipeline->graphics.vtx_emit_num == 3)
3360 radeon_emit(cs, 0);
3361 state->last_first_instance = info->first_instance;
3362 state->last_vertex_offset = info->vertex_offset;
3363 }
3364
3365 if (state->last_num_instances != info->instance_count) {
3366 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3367 radeon_emit(cs, info->instance_count);
3368 state->last_num_instances = info->instance_count;
3369 }
3370
3371 if (info->indexed) {
3372 int index_size = state->index_type ? 4 : 2;
3373 uint64_t index_va;
3374
3375 index_va = state->index_va;
3376 index_va += info->first_index * index_size;
3377
3378 if (!state->subpass->view_mask) {
3379 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3380 index_va,
3381 info->count);
3382 } else {
3383 unsigned i;
3384 for_each_bit(i, state->subpass->view_mask) {
3385 radv_emit_view_index(cmd_buffer, i);
3386
3387 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3388 index_va,
3389 info->count);
3390 }
3391 }
3392 } else {
3393 if (!state->subpass->view_mask) {
3394 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3395 } else {
3396 unsigned i;
3397 for_each_bit(i, state->subpass->view_mask) {
3398 radv_emit_view_index(cmd_buffer, i);
3399
3400 radv_cs_emit_draw_packet(cmd_buffer,
3401 info->count);
3402 }
3403 }
3404 }
3405 }
3406 }
3407
3408 static void
3409 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3410 const struct radv_draw_info *info)
3411 {
3412 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3413 radv_emit_graphics_pipeline(cmd_buffer);
3414
3415 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3416 radv_emit_framebuffer_state(cmd_buffer);
3417
3418 if (info->indexed) {
3419 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3420 radv_emit_index_buffer(cmd_buffer);
3421 } else {
3422 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3423 * so the state must be re-emitted before the next indexed
3424 * draw.
3425 */
3426 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3427 cmd_buffer->state.last_index_type = -1;
3428 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3429 }
3430 }
3431
3432 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3433
3434 radv_emit_draw_registers(cmd_buffer, info->indexed,
3435 info->instance_count > 1, info->indirect,
3436 info->indirect ? 0 : info->count);
3437 }
3438
3439 static void
3440 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3441 const struct radv_draw_info *info)
3442 {
3443 bool pipeline_is_dirty =
3444 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3445 cmd_buffer->state.pipeline &&
3446 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3447
3448 MAYBE_UNUSED unsigned cdw_max =
3449 radeon_check_space(cmd_buffer->device->ws,
3450 cmd_buffer->cs, 4096);
3451
3452 /* Use optimal packet order based on whether we need to sync the
3453 * pipeline.
3454 */
3455 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3456 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3457 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3458 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3459 /* If we have to wait for idle, set all states first, so that
3460 * all SET packets are processed in parallel with previous draw
3461 * calls. Then upload descriptors, set shader pointers, and
3462 * draw, and prefetch at the end. This ensures that the time
3463 * the CUs are idle is very short. (there are only SET_SH
3464 * packets between the wait and the draw)
3465 */
3466 radv_emit_all_graphics_states(cmd_buffer, info);
3467 si_emit_cache_flush(cmd_buffer);
3468 /* <-- CUs are idle here --> */
3469
3470 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3471 return;
3472
3473 radv_emit_draw_packets(cmd_buffer, info);
3474 /* <-- CUs are busy here --> */
3475
3476 /* Start prefetches after the draw has been started. Both will
3477 * run in parallel, but starting the draw first is more
3478 * important.
3479 */
3480 if (pipeline_is_dirty) {
3481 radv_emit_prefetch(cmd_buffer,
3482 cmd_buffer->state.pipeline);
3483 }
3484 } else {
3485 /* If we don't wait for idle, start prefetches first, then set
3486 * states, and draw at the end.
3487 */
3488 si_emit_cache_flush(cmd_buffer);
3489
3490 if (pipeline_is_dirty) {
3491 radv_emit_prefetch(cmd_buffer,
3492 cmd_buffer->state.pipeline);
3493 }
3494
3495 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3496 return;
3497
3498 radv_emit_all_graphics_states(cmd_buffer, info);
3499 radv_emit_draw_packets(cmd_buffer, info);
3500 }
3501
3502 assert(cmd_buffer->cs->cdw <= cdw_max);
3503 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3504 }
3505
3506 void radv_CmdDraw(
3507 VkCommandBuffer commandBuffer,
3508 uint32_t vertexCount,
3509 uint32_t instanceCount,
3510 uint32_t firstVertex,
3511 uint32_t firstInstance)
3512 {
3513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3514 struct radv_draw_info info = {};
3515
3516 info.count = vertexCount;
3517 info.instance_count = instanceCount;
3518 info.first_instance = firstInstance;
3519 info.vertex_offset = firstVertex;
3520
3521 radv_draw(cmd_buffer, &info);
3522 }
3523
3524 void radv_CmdDrawIndexed(
3525 VkCommandBuffer commandBuffer,
3526 uint32_t indexCount,
3527 uint32_t instanceCount,
3528 uint32_t firstIndex,
3529 int32_t vertexOffset,
3530 uint32_t firstInstance)
3531 {
3532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3533 struct radv_draw_info info = {};
3534
3535 info.indexed = true;
3536 info.count = indexCount;
3537 info.instance_count = instanceCount;
3538 info.first_index = firstIndex;
3539 info.vertex_offset = vertexOffset;
3540 info.first_instance = firstInstance;
3541
3542 radv_draw(cmd_buffer, &info);
3543 }
3544
3545 void radv_CmdDrawIndirect(
3546 VkCommandBuffer commandBuffer,
3547 VkBuffer _buffer,
3548 VkDeviceSize offset,
3549 uint32_t drawCount,
3550 uint32_t stride)
3551 {
3552 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3553 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3554 struct radv_draw_info info = {};
3555
3556 info.count = drawCount;
3557 info.indirect = buffer;
3558 info.indirect_offset = offset;
3559 info.stride = stride;
3560
3561 radv_draw(cmd_buffer, &info);
3562 }
3563
3564 void radv_CmdDrawIndexedIndirect(
3565 VkCommandBuffer commandBuffer,
3566 VkBuffer _buffer,
3567 VkDeviceSize offset,
3568 uint32_t drawCount,
3569 uint32_t stride)
3570 {
3571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3572 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3573 struct radv_draw_info info = {};
3574
3575 info.indexed = true;
3576 info.count = drawCount;
3577 info.indirect = buffer;
3578 info.indirect_offset = offset;
3579 info.stride = stride;
3580
3581 radv_draw(cmd_buffer, &info);
3582 }
3583
3584 void radv_CmdDrawIndirectCountAMD(
3585 VkCommandBuffer commandBuffer,
3586 VkBuffer _buffer,
3587 VkDeviceSize offset,
3588 VkBuffer _countBuffer,
3589 VkDeviceSize countBufferOffset,
3590 uint32_t maxDrawCount,
3591 uint32_t stride)
3592 {
3593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3594 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3595 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3596 struct radv_draw_info info = {};
3597
3598 info.count = maxDrawCount;
3599 info.indirect = buffer;
3600 info.indirect_offset = offset;
3601 info.count_buffer = count_buffer;
3602 info.count_buffer_offset = countBufferOffset;
3603 info.stride = stride;
3604
3605 radv_draw(cmd_buffer, &info);
3606 }
3607
3608 void radv_CmdDrawIndexedIndirectCountAMD(
3609 VkCommandBuffer commandBuffer,
3610 VkBuffer _buffer,
3611 VkDeviceSize offset,
3612 VkBuffer _countBuffer,
3613 VkDeviceSize countBufferOffset,
3614 uint32_t maxDrawCount,
3615 uint32_t stride)
3616 {
3617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3618 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3619 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3620 struct radv_draw_info info = {};
3621
3622 info.indexed = true;
3623 info.count = maxDrawCount;
3624 info.indirect = buffer;
3625 info.indirect_offset = offset;
3626 info.count_buffer = count_buffer;
3627 info.count_buffer_offset = countBufferOffset;
3628 info.stride = stride;
3629
3630 radv_draw(cmd_buffer, &info);
3631 }
3632
3633 struct radv_dispatch_info {
3634 /**
3635 * Determine the layout of the grid (in block units) to be used.
3636 */
3637 uint32_t blocks[3];
3638
3639 /**
3640 * Whether it's an unaligned compute dispatch.
3641 */
3642 bool unaligned;
3643
3644 /**
3645 * Indirect compute parameters resource.
3646 */
3647 struct radv_buffer *indirect;
3648 uint64_t indirect_offset;
3649 };
3650
3651 static void
3652 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3653 const struct radv_dispatch_info *info)
3654 {
3655 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3656 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3657 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3658 struct radeon_winsys *ws = cmd_buffer->device->ws;
3659 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3660 struct ac_userdata_info *loc;
3661
3662 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3663 AC_UD_CS_GRID_SIZE);
3664
3665 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3666
3667 if (info->indirect) {
3668 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3669
3670 va += info->indirect->offset + info->indirect_offset;
3671
3672 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3673
3674 if (loc->sgpr_idx != -1) {
3675 for (unsigned i = 0; i < 3; ++i) {
3676 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3677 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3678 COPY_DATA_DST_SEL(COPY_DATA_REG));
3679 radeon_emit(cs, (va + 4 * i));
3680 radeon_emit(cs, (va + 4 * i) >> 32);
3681 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3682 + loc->sgpr_idx * 4) >> 2) + i);
3683 radeon_emit(cs, 0);
3684 }
3685 }
3686
3687 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3688 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3689 PKT3_SHADER_TYPE_S(1));
3690 radeon_emit(cs, va);
3691 radeon_emit(cs, va >> 32);
3692 radeon_emit(cs, dispatch_initiator);
3693 } else {
3694 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3695 PKT3_SHADER_TYPE_S(1));
3696 radeon_emit(cs, 1);
3697 radeon_emit(cs, va);
3698 radeon_emit(cs, va >> 32);
3699
3700 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3701 PKT3_SHADER_TYPE_S(1));
3702 radeon_emit(cs, 0);
3703 radeon_emit(cs, dispatch_initiator);
3704 }
3705 } else {
3706 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3707
3708 if (info->unaligned) {
3709 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3710 unsigned remainder[3];
3711
3712 /* If aligned, these should be an entire block size,
3713 * not 0.
3714 */
3715 remainder[0] = blocks[0] + cs_block_size[0] -
3716 align_u32_npot(blocks[0], cs_block_size[0]);
3717 remainder[1] = blocks[1] + cs_block_size[1] -
3718 align_u32_npot(blocks[1], cs_block_size[1]);
3719 remainder[2] = blocks[2] + cs_block_size[2] -
3720 align_u32_npot(blocks[2], cs_block_size[2]);
3721
3722 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3723 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3724 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3725
3726 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3727 radeon_emit(cs,
3728 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3729 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3730 radeon_emit(cs,
3731 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3732 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3733 radeon_emit(cs,
3734 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3735 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3736
3737 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3738 }
3739
3740 if (loc->sgpr_idx != -1) {
3741 assert(!loc->indirect);
3742 assert(loc->num_sgprs == 3);
3743
3744 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3745 loc->sgpr_idx * 4, 3);
3746 radeon_emit(cs, blocks[0]);
3747 radeon_emit(cs, blocks[1]);
3748 radeon_emit(cs, blocks[2]);
3749 }
3750
3751 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3752 PKT3_SHADER_TYPE_S(1));
3753 radeon_emit(cs, blocks[0]);
3754 radeon_emit(cs, blocks[1]);
3755 radeon_emit(cs, blocks[2]);
3756 radeon_emit(cs, dispatch_initiator);
3757 }
3758
3759 assert(cmd_buffer->cs->cdw <= cdw_max);
3760 }
3761
3762 static void
3763 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3764 {
3765 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3766 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3767 VK_SHADER_STAGE_COMPUTE_BIT);
3768 }
3769
3770 static void
3771 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3772 const struct radv_dispatch_info *info)
3773 {
3774 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3775 bool pipeline_is_dirty = pipeline &&
3776 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3777
3778 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3779 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3780 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3781 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3782 /* If we have to wait for idle, set all states first, so that
3783 * all SET packets are processed in parallel with previous draw
3784 * calls. Then upload descriptors, set shader pointers, and
3785 * dispatch, and prefetch at the end. This ensures that the
3786 * time the CUs are idle is very short. (there are only SET_SH
3787 * packets between the wait and the draw)
3788 */
3789 radv_emit_compute_pipeline(cmd_buffer);
3790 si_emit_cache_flush(cmd_buffer);
3791 /* <-- CUs are idle here --> */
3792
3793 radv_upload_compute_shader_descriptors(cmd_buffer);
3794
3795 radv_emit_dispatch_packets(cmd_buffer, info);
3796 /* <-- CUs are busy here --> */
3797
3798 /* Start prefetches after the dispatch has been started. Both
3799 * will run in parallel, but starting the dispatch first is
3800 * more important.
3801 */
3802 if (pipeline_is_dirty) {
3803 radv_emit_shader_prefetch(cmd_buffer,
3804 pipeline->shaders[MESA_SHADER_COMPUTE]);
3805 }
3806 } else {
3807 /* If we don't wait for idle, start prefetches first, then set
3808 * states, and dispatch at the end.
3809 */
3810 si_emit_cache_flush(cmd_buffer);
3811
3812 if (pipeline_is_dirty) {
3813 radv_emit_shader_prefetch(cmd_buffer,
3814 pipeline->shaders[MESA_SHADER_COMPUTE]);
3815 }
3816
3817 radv_upload_compute_shader_descriptors(cmd_buffer);
3818
3819 radv_emit_compute_pipeline(cmd_buffer);
3820 radv_emit_dispatch_packets(cmd_buffer, info);
3821 }
3822
3823 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3824 }
3825
3826 void radv_CmdDispatch(
3827 VkCommandBuffer commandBuffer,
3828 uint32_t x,
3829 uint32_t y,
3830 uint32_t z)
3831 {
3832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3833 struct radv_dispatch_info info = {};
3834
3835 info.blocks[0] = x;
3836 info.blocks[1] = y;
3837 info.blocks[2] = z;
3838
3839 radv_dispatch(cmd_buffer, &info);
3840 }
3841
3842 void radv_CmdDispatchIndirect(
3843 VkCommandBuffer commandBuffer,
3844 VkBuffer _buffer,
3845 VkDeviceSize offset)
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3848 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3849 struct radv_dispatch_info info = {};
3850
3851 info.indirect = buffer;
3852 info.indirect_offset = offset;
3853
3854 radv_dispatch(cmd_buffer, &info);
3855 }
3856
3857 void radv_unaligned_dispatch(
3858 struct radv_cmd_buffer *cmd_buffer,
3859 uint32_t x,
3860 uint32_t y,
3861 uint32_t z)
3862 {
3863 struct radv_dispatch_info info = {};
3864
3865 info.blocks[0] = x;
3866 info.blocks[1] = y;
3867 info.blocks[2] = z;
3868 info.unaligned = 1;
3869
3870 radv_dispatch(cmd_buffer, &info);
3871 }
3872
3873 void radv_CmdEndRenderPass(
3874 VkCommandBuffer commandBuffer)
3875 {
3876 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3877
3878 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3879
3880 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3881
3882 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3883 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3884 radv_handle_subpass_image_transition(cmd_buffer,
3885 (VkAttachmentReference){i, layout});
3886 }
3887
3888 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3889
3890 cmd_buffer->state.pass = NULL;
3891 cmd_buffer->state.subpass = NULL;
3892 cmd_buffer->state.attachments = NULL;
3893 cmd_buffer->state.framebuffer = NULL;
3894 }
3895
3896 /*
3897 * For HTILE we have the following interesting clear words:
3898 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3899 * 0x0000000f: Uncompressed for depth only HTILE.
3900 * 0xfffffff0: Clear depth to 1.0
3901 * 0x00000000: Clear depth to 0.0
3902 */
3903 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3904 struct radv_image *image,
3905 const VkImageSubresourceRange *range,
3906 uint32_t clear_word)
3907 {
3908 assert(range->baseMipLevel == 0);
3909 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3910 unsigned layer_count = radv_get_layerCount(image, range);
3911 uint64_t size = image->surface.htile_slice_size * layer_count;
3912 uint64_t offset = image->offset + image->htile_offset +
3913 image->surface.htile_slice_size * range->baseArrayLayer;
3914 struct radv_cmd_state *state = &cmd_buffer->state;
3915
3916 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3917 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3918
3919 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3920 size, clear_word);
3921
3922 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3923 }
3924
3925 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3926 struct radv_image *image,
3927 VkImageLayout src_layout,
3928 VkImageLayout dst_layout,
3929 unsigned src_queue_mask,
3930 unsigned dst_queue_mask,
3931 const VkImageSubresourceRange *range,
3932 VkImageAspectFlags pending_clears)
3933 {
3934 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3935 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3936 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3937 cmd_buffer->state.render_area.extent.width == image->info.width &&
3938 cmd_buffer->state.render_area.extent.height == image->info.height) {
3939 /* The clear will initialize htile. */
3940 return;
3941 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3942 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3943 /* TODO: merge with the clear if applicable */
3944 radv_initialize_htile(cmd_buffer, image, range, 0);
3945 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3946 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3947 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3948 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3949 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3950 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3951 VkImageSubresourceRange local_range = *range;
3952 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3953 local_range.baseMipLevel = 0;
3954 local_range.levelCount = 1;
3955
3956 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3957 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3958
3959 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3960
3961 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3962 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3963 }
3964 }
3965
3966 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3967 struct radv_image *image, uint32_t value)
3968 {
3969 struct radv_cmd_state *state = &cmd_buffer->state;
3970
3971 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3972 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3973
3974 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3975 image->offset + image->cmask.offset,
3976 image->cmask.size, value);
3977
3978 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3979 }
3980
3981 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3982 struct radv_image *image,
3983 VkImageLayout src_layout,
3984 VkImageLayout dst_layout,
3985 unsigned src_queue_mask,
3986 unsigned dst_queue_mask,
3987 const VkImageSubresourceRange *range)
3988 {
3989 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3990 if (image->fmask.size)
3991 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3992 else
3993 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3994 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3995 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3996 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3997 }
3998 }
3999
4000 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4001 struct radv_image *image, uint32_t value)
4002 {
4003 struct radv_cmd_state *state = &cmd_buffer->state;
4004
4005 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4006 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4007
4008 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
4009 image->offset + image->dcc_offset,
4010 image->surface.dcc_size, value);
4011
4012 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4013 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4014 }
4015
4016 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
4017 struct radv_image *image,
4018 VkImageLayout src_layout,
4019 VkImageLayout dst_layout,
4020 unsigned src_queue_mask,
4021 unsigned dst_queue_mask,
4022 const VkImageSubresourceRange *range)
4023 {
4024 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4025 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4026 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4027 radv_initialize_dcc(cmd_buffer, image,
4028 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
4029 0x20202020u : 0xffffffffu);
4030 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4031 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4032 radv_decompress_dcc(cmd_buffer, image, range);
4033 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4034 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4035 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4036 }
4037 }
4038
4039 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4040 struct radv_image *image,
4041 VkImageLayout src_layout,
4042 VkImageLayout dst_layout,
4043 uint32_t src_family,
4044 uint32_t dst_family,
4045 const VkImageSubresourceRange *range,
4046 VkImageAspectFlags pending_clears)
4047 {
4048 if (image->exclusive && src_family != dst_family) {
4049 /* This is an acquire or a release operation and there will be
4050 * a corresponding release/acquire. Do the transition in the
4051 * most flexible queue. */
4052
4053 assert(src_family == cmd_buffer->queue_family_index ||
4054 dst_family == cmd_buffer->queue_family_index);
4055
4056 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4057 return;
4058
4059 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4060 (src_family == RADV_QUEUE_GENERAL ||
4061 dst_family == RADV_QUEUE_GENERAL))
4062 return;
4063 }
4064
4065 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
4066 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
4067
4068 if (image->surface.htile_size)
4069 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
4070 dst_layout, src_queue_mask,
4071 dst_queue_mask, range,
4072 pending_clears);
4073
4074 if (image->cmask.size || image->fmask.size)
4075 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
4076 dst_layout, src_queue_mask,
4077 dst_queue_mask, range);
4078
4079 if (image->surface.dcc_size)
4080 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
4081 dst_layout, src_queue_mask,
4082 dst_queue_mask, range);
4083 }
4084
4085 void radv_CmdPipelineBarrier(
4086 VkCommandBuffer commandBuffer,
4087 VkPipelineStageFlags srcStageMask,
4088 VkPipelineStageFlags destStageMask,
4089 VkBool32 byRegion,
4090 uint32_t memoryBarrierCount,
4091 const VkMemoryBarrier* pMemoryBarriers,
4092 uint32_t bufferMemoryBarrierCount,
4093 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4094 uint32_t imageMemoryBarrierCount,
4095 const VkImageMemoryBarrier* pImageMemoryBarriers)
4096 {
4097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4098 enum radv_cmd_flush_bits src_flush_bits = 0;
4099 enum radv_cmd_flush_bits dst_flush_bits = 0;
4100
4101 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4102 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4103 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4104 NULL);
4105 }
4106
4107 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4108 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4109 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4110 NULL);
4111 }
4112
4113 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4114 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4115 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4116 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4117 image);
4118 }
4119
4120 radv_stage_flush(cmd_buffer, srcStageMask);
4121 cmd_buffer->state.flush_bits |= src_flush_bits;
4122
4123 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4124 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4125 radv_handle_image_transition(cmd_buffer, image,
4126 pImageMemoryBarriers[i].oldLayout,
4127 pImageMemoryBarriers[i].newLayout,
4128 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4129 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4130 &pImageMemoryBarriers[i].subresourceRange,
4131 0);
4132 }
4133
4134 cmd_buffer->state.flush_bits |= dst_flush_bits;
4135 }
4136
4137
4138 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4139 struct radv_event *event,
4140 VkPipelineStageFlags stageMask,
4141 unsigned value)
4142 {
4143 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4144 uint64_t va = radv_buffer_get_va(event->bo);
4145
4146 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4147
4148 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4149
4150 /* TODO: this is overkill. Probably should figure something out from
4151 * the stage mask. */
4152
4153 si_cs_emit_write_event_eop(cs,
4154 cmd_buffer->state.predicating,
4155 cmd_buffer->device->physical_device->rad_info.chip_class,
4156 radv_cmd_buffer_uses_mec(cmd_buffer),
4157 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4158 1, va, 2, value);
4159
4160 assert(cmd_buffer->cs->cdw <= cdw_max);
4161 }
4162
4163 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4164 VkEvent _event,
4165 VkPipelineStageFlags stageMask)
4166 {
4167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4168 RADV_FROM_HANDLE(radv_event, event, _event);
4169
4170 write_event(cmd_buffer, event, stageMask, 1);
4171 }
4172
4173 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4174 VkEvent _event,
4175 VkPipelineStageFlags stageMask)
4176 {
4177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4178 RADV_FROM_HANDLE(radv_event, event, _event);
4179
4180 write_event(cmd_buffer, event, stageMask, 0);
4181 }
4182
4183 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4184 uint32_t eventCount,
4185 const VkEvent* pEvents,
4186 VkPipelineStageFlags srcStageMask,
4187 VkPipelineStageFlags dstStageMask,
4188 uint32_t memoryBarrierCount,
4189 const VkMemoryBarrier* pMemoryBarriers,
4190 uint32_t bufferMemoryBarrierCount,
4191 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4192 uint32_t imageMemoryBarrierCount,
4193 const VkImageMemoryBarrier* pImageMemoryBarriers)
4194 {
4195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4196 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4197
4198 for (unsigned i = 0; i < eventCount; ++i) {
4199 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4200 uint64_t va = radv_buffer_get_va(event->bo);
4201
4202 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4203
4204 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4205
4206 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4207 assert(cmd_buffer->cs->cdw <= cdw_max);
4208 }
4209
4210
4211 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4212 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4213
4214 radv_handle_image_transition(cmd_buffer, image,
4215 pImageMemoryBarriers[i].oldLayout,
4216 pImageMemoryBarriers[i].newLayout,
4217 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4218 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4219 &pImageMemoryBarriers[i].subresourceRange,
4220 0);
4221 }
4222
4223 /* TODO: figure out how to do memory barriers without waiting */
4224 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4225 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4226 RADV_CMD_FLAG_INV_VMEM_L1 |
4227 RADV_CMD_FLAG_INV_SMEM_L1;
4228 }