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c43e12f6d621d280caaf653c08ed693c43c9a951
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 static void
200 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
201 struct radv_pipeline *pipeline)
202 {
203 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
204 struct radv_shader_info *info;
205
206 if (!pipeline->streamout_shader)
207 return;
208
209 info = &pipeline->streamout_shader->info.info;
210 for (int i = 0; i < MAX_SO_BUFFERS; i++)
211 so->stride_in_dw[i] = info->so.strides[i];
212
213 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
214 }
215
216 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
217 {
218 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
219 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
220 }
221
222 enum ring_type radv_queue_family_to_ring(int f) {
223 switch (f) {
224 case RADV_QUEUE_GENERAL:
225 return RING_GFX;
226 case RADV_QUEUE_COMPUTE:
227 return RING_COMPUTE;
228 case RADV_QUEUE_TRANSFER:
229 return RING_DMA;
230 default:
231 unreachable("Unknown queue family");
232 }
233 }
234
235 static VkResult radv_create_cmd_buffer(
236 struct radv_device * device,
237 struct radv_cmd_pool * pool,
238 VkCommandBufferLevel level,
239 VkCommandBuffer* pCommandBuffer)
240 {
241 struct radv_cmd_buffer *cmd_buffer;
242 unsigned ring;
243 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
244 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
245 if (cmd_buffer == NULL)
246 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
247
248 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
249 cmd_buffer->device = device;
250 cmd_buffer->pool = pool;
251 cmd_buffer->level = level;
252
253 if (pool) {
254 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
255 cmd_buffer->queue_family_index = pool->queue_family_index;
256
257 } else {
258 /* Init the pool_link so we can safely call list_del when we destroy
259 * the command buffer
260 */
261 list_inithead(&cmd_buffer->pool_link);
262 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
263 }
264
265 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
266
267 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
268 if (!cmd_buffer->cs) {
269 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
270 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
271 }
272
273 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
274
275 list_inithead(&cmd_buffer->upload.list);
276
277 return VK_SUCCESS;
278 }
279
280 static void
281 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
282 {
283 list_del(&cmd_buffer->pool_link);
284
285 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
286 &cmd_buffer->upload.list, list) {
287 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
288 list_del(&up->list);
289 free(up);
290 }
291
292 if (cmd_buffer->upload.upload_bo)
293 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
294 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
295
296 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
297 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
298
299 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
300 }
301
302 static VkResult
303 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
304 {
305
306 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
307
308 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
309 &cmd_buffer->upload.list, list) {
310 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
311 list_del(&up->list);
312 free(up);
313 }
314
315 cmd_buffer->push_constant_stages = 0;
316 cmd_buffer->scratch_size_needed = 0;
317 cmd_buffer->compute_scratch_size_needed = 0;
318 cmd_buffer->esgs_ring_size_needed = 0;
319 cmd_buffer->gsvs_ring_size_needed = 0;
320 cmd_buffer->tess_rings_needed = false;
321 cmd_buffer->sample_positions_needed = false;
322
323 if (cmd_buffer->upload.upload_bo)
324 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
325 cmd_buffer->upload.upload_bo);
326 cmd_buffer->upload.offset = 0;
327
328 cmd_buffer->record_result = VK_SUCCESS;
329
330 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
331 cmd_buffer->descriptors[i].dirty = 0;
332 cmd_buffer->descriptors[i].valid = 0;
333 cmd_buffer->descriptors[i].push_dirty = false;
334 }
335
336 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
337 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
338 unsigned eop_bug_offset;
339 void *fence_ptr;
340
341 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
342 &cmd_buffer->gfx9_fence_offset,
343 &fence_ptr);
344 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
345
346 /* Allocate a buffer for the EOP bug on GFX9. */
347 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
348 &eop_bug_offset, &fence_ptr);
349 cmd_buffer->gfx9_eop_bug_va =
350 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
351 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
352 }
353
354 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
355
356 return cmd_buffer->record_result;
357 }
358
359 static bool
360 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
361 uint64_t min_needed)
362 {
363 uint64_t new_size;
364 struct radeon_winsys_bo *bo;
365 struct radv_cmd_buffer_upload *upload;
366 struct radv_device *device = cmd_buffer->device;
367
368 new_size = MAX2(min_needed, 16 * 1024);
369 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
370
371 bo = device->ws->buffer_create(device->ws,
372 new_size, 4096,
373 RADEON_DOMAIN_GTT,
374 RADEON_FLAG_CPU_ACCESS|
375 RADEON_FLAG_NO_INTERPROCESS_SHARING |
376 RADEON_FLAG_32BIT);
377
378 if (!bo) {
379 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
380 return false;
381 }
382
383 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
384 if (cmd_buffer->upload.upload_bo) {
385 upload = malloc(sizeof(*upload));
386
387 if (!upload) {
388 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
389 device->ws->buffer_destroy(bo);
390 return false;
391 }
392
393 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
394 list_add(&upload->list, &cmd_buffer->upload.list);
395 }
396
397 cmd_buffer->upload.upload_bo = bo;
398 cmd_buffer->upload.size = new_size;
399 cmd_buffer->upload.offset = 0;
400 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
401
402 if (!cmd_buffer->upload.map) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 return true;
408 }
409
410 bool
411 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
412 unsigned size,
413 unsigned alignment,
414 unsigned *out_offset,
415 void **ptr)
416 {
417 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
418 if (offset + size > cmd_buffer->upload.size) {
419 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
420 return false;
421 offset = 0;
422 }
423
424 *out_offset = offset;
425 *ptr = cmd_buffer->upload.map + offset;
426
427 cmd_buffer->upload.offset = offset + size;
428 return true;
429 }
430
431 bool
432 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
433 unsigned size, unsigned alignment,
434 const void *data, unsigned *out_offset)
435 {
436 uint8_t *ptr;
437
438 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
439 out_offset, (void **)&ptr))
440 return false;
441
442 if (ptr)
443 memcpy(ptr, data, size);
444
445 return true;
446 }
447
448 static void
449 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
450 unsigned count, const uint32_t *data)
451 {
452 struct radeon_cmdbuf *cs = cmd_buffer->cs;
453
454 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
455
456 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
457 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
458 S_370_WR_CONFIRM(1) |
459 S_370_ENGINE_SEL(V_370_ME));
460 radeon_emit(cs, va);
461 radeon_emit(cs, va >> 32);
462 radeon_emit_array(cs, data, count);
463 }
464
465 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
466 {
467 struct radv_device *device = cmd_buffer->device;
468 struct radeon_cmdbuf *cs = cmd_buffer->cs;
469 uint64_t va;
470
471 va = radv_buffer_get_va(device->trace_bo);
472 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
473 va += 4;
474
475 ++cmd_buffer->state.trace_id;
476 radv_emit_write_data_packet(cmd_buffer, va, 1,
477 &cmd_buffer->state.trace_id);
478
479 radeon_check_space(cmd_buffer->device->ws, cs, 2);
480
481 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
482 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
483 }
484
485 static void
486 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
487 enum radv_cmd_flush_bits flags)
488 {
489 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
490 uint32_t *ptr = NULL;
491 uint64_t va = 0;
492
493 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
494 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
495
496 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
497 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
498 cmd_buffer->gfx9_fence_offset;
499 ptr = &cmd_buffer->gfx9_fence_idx;
500 }
501
502 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
503
504 /* Force wait for graphics or compute engines to be idle. */
505 si_cs_emit_cache_flush(cmd_buffer->cs,
506 cmd_buffer->device->physical_device->rad_info.chip_class,
507 ptr, va,
508 radv_cmd_buffer_uses_mec(cmd_buffer),
509 flags, cmd_buffer->gfx9_eop_bug_va);
510 }
511
512 if (unlikely(cmd_buffer->device->trace_bo))
513 radv_cmd_buffer_trace_emit(cmd_buffer);
514 }
515
516 static void
517 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
518 struct radv_pipeline *pipeline, enum ring_type ring)
519 {
520 struct radv_device *device = cmd_buffer->device;
521 uint32_t data[2];
522 uint64_t va;
523
524 va = radv_buffer_get_va(device->trace_bo);
525
526 switch (ring) {
527 case RING_GFX:
528 va += 8;
529 break;
530 case RING_COMPUTE:
531 va += 16;
532 break;
533 default:
534 assert(!"invalid ring type");
535 }
536
537 data[0] = (uintptr_t)pipeline;
538 data[1] = (uintptr_t)pipeline >> 32;
539
540 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
541 }
542
543 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
544 VkPipelineBindPoint bind_point,
545 struct radv_descriptor_set *set,
546 unsigned idx)
547 {
548 struct radv_descriptor_state *descriptors_state =
549 radv_get_descriptors_state(cmd_buffer, bind_point);
550
551 descriptors_state->sets[idx] = set;
552
553 descriptors_state->valid |= (1u << idx); /* active descriptors */
554 descriptors_state->dirty |= (1u << idx);
555 }
556
557 static void
558 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
559 VkPipelineBindPoint bind_point)
560 {
561 struct radv_descriptor_state *descriptors_state =
562 radv_get_descriptors_state(cmd_buffer, bind_point);
563 struct radv_device *device = cmd_buffer->device;
564 uint32_t data[MAX_SETS * 2] = {};
565 uint64_t va;
566 unsigned i;
567 va = radv_buffer_get_va(device->trace_bo) + 24;
568
569 for_each_bit(i, descriptors_state->valid) {
570 struct radv_descriptor_set *set = descriptors_state->sets[i];
571 data[i * 2] = (uintptr_t)set;
572 data[i * 2 + 1] = (uintptr_t)set >> 32;
573 }
574
575 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
576 }
577
578 struct radv_userdata_info *
579 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
580 gl_shader_stage stage,
581 int idx)
582 {
583 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
584 return &shader->info.user_sgprs_locs.shader_data[idx];
585 }
586
587 static void
588 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
589 struct radv_pipeline *pipeline,
590 gl_shader_stage stage,
591 int idx, uint64_t va)
592 {
593 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
594 uint32_t base_reg = pipeline->user_data_0[stage];
595 if (loc->sgpr_idx == -1)
596 return;
597
598 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
599 assert(!loc->indirect);
600
601 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
602 base_reg + loc->sgpr_idx * 4, va, false);
603 }
604
605 static void
606 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 struct radv_descriptor_state *descriptors_state,
609 gl_shader_stage stage)
610 {
611 struct radv_device *device = cmd_buffer->device;
612 struct radeon_cmdbuf *cs = cmd_buffer->cs;
613 uint32_t sh_base = pipeline->user_data_0[stage];
614 struct radv_userdata_locations *locs =
615 &pipeline->shaders[stage]->info.user_sgprs_locs;
616 unsigned mask = locs->descriptor_sets_enabled;
617
618 mask &= descriptors_state->dirty & descriptors_state->valid;
619
620 while (mask) {
621 int start, count;
622
623 u_bit_scan_consecutive_range(&mask, &start, &count);
624
625 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
626 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
627
628 radv_emit_shader_pointer_head(cs, sh_offset, count,
629 HAVE_32BIT_POINTERS);
630 for (int i = 0; i < count; i++) {
631 struct radv_descriptor_set *set =
632 descriptors_state->sets[start + i];
633
634 radv_emit_shader_pointer_body(device, cs, set->va,
635 HAVE_32BIT_POINTERS);
636 }
637 }
638 }
639
640 static void
641 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
642 struct radv_pipeline *pipeline)
643 {
644 int num_samples = pipeline->graphics.ms.num_samples;
645 struct radv_multisample_state *ms = &pipeline->graphics.ms;
646 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
647
648 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
649 cmd_buffer->sample_positions_needed = true;
650
651 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
652 return;
653
654 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
655 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
656 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
657
658 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
659
660 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
661
662 /* GFX9: Flush DFSM when the AA mode changes. */
663 if (cmd_buffer->device->dfsm_allowed) {
664 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
665 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
666 }
667 }
668
669 static void
670 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
671 struct radv_shader_variant *shader)
672 {
673 uint64_t va;
674
675 if (!shader)
676 return;
677
678 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
679
680 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
681 }
682
683 static void
684 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
685 struct radv_pipeline *pipeline,
686 bool vertex_stage_only)
687 {
688 struct radv_cmd_state *state = &cmd_buffer->state;
689 uint32_t mask = state->prefetch_L2_mask;
690
691 if (vertex_stage_only) {
692 /* Fast prefetch path for starting draws as soon as possible.
693 */
694 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
695 RADV_PREFETCH_VBO_DESCRIPTORS);
696 }
697
698 if (mask & RADV_PREFETCH_VS)
699 radv_emit_shader_prefetch(cmd_buffer,
700 pipeline->shaders[MESA_SHADER_VERTEX]);
701
702 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
703 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
704
705 if (mask & RADV_PREFETCH_TCS)
706 radv_emit_shader_prefetch(cmd_buffer,
707 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
708
709 if (mask & RADV_PREFETCH_TES)
710 radv_emit_shader_prefetch(cmd_buffer,
711 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
712
713 if (mask & RADV_PREFETCH_GS) {
714 radv_emit_shader_prefetch(cmd_buffer,
715 pipeline->shaders[MESA_SHADER_GEOMETRY]);
716 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
717 }
718
719 if (mask & RADV_PREFETCH_PS)
720 radv_emit_shader_prefetch(cmd_buffer,
721 pipeline->shaders[MESA_SHADER_FRAGMENT]);
722
723 state->prefetch_L2_mask &= ~mask;
724 }
725
726 static void
727 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
728 {
729 if (!cmd_buffer->device->physical_device->rbplus_allowed)
730 return;
731
732 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
733 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
734 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
735
736 unsigned sx_ps_downconvert = 0;
737 unsigned sx_blend_opt_epsilon = 0;
738 unsigned sx_blend_opt_control = 0;
739
740 for (unsigned i = 0; i < subpass->color_count; ++i) {
741 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
742 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
743 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
744 continue;
745 }
746
747 int idx = subpass->color_attachments[i].attachment;
748 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
749
750 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
751 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
752 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
753 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
754
755 bool has_alpha, has_rgb;
756
757 /* Set if RGB and A are present. */
758 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
759
760 if (format == V_028C70_COLOR_8 ||
761 format == V_028C70_COLOR_16 ||
762 format == V_028C70_COLOR_32)
763 has_rgb = !has_alpha;
764 else
765 has_rgb = true;
766
767 /* Check the colormask and export format. */
768 if (!(colormask & 0x7))
769 has_rgb = false;
770 if (!(colormask & 0x8))
771 has_alpha = false;
772
773 if (spi_format == V_028714_SPI_SHADER_ZERO) {
774 has_rgb = false;
775 has_alpha = false;
776 }
777
778 /* Disable value checking for disabled channels. */
779 if (!has_rgb)
780 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
781 if (!has_alpha)
782 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
783
784 /* Enable down-conversion for 32bpp and smaller formats. */
785 switch (format) {
786 case V_028C70_COLOR_8:
787 case V_028C70_COLOR_8_8:
788 case V_028C70_COLOR_8_8_8_8:
789 /* For 1 and 2-channel formats, use the superset thereof. */
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
791 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
792 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
793 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
794 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
795 }
796 break;
797
798 case V_028C70_COLOR_5_6_5:
799 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
800 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
801 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
802 }
803 break;
804
805 case V_028C70_COLOR_1_5_5_5:
806 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
807 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
808 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
809 }
810 break;
811
812 case V_028C70_COLOR_4_4_4_4:
813 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
814 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
815 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
816 }
817 break;
818
819 case V_028C70_COLOR_32:
820 if (swap == V_028C70_SWAP_STD &&
821 spi_format == V_028714_SPI_SHADER_32_R)
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
823 else if (swap == V_028C70_SWAP_ALT_REV &&
824 spi_format == V_028714_SPI_SHADER_32_AR)
825 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
826 break;
827
828 case V_028C70_COLOR_16:
829 case V_028C70_COLOR_16_16:
830 /* For 1-channel formats, use the superset thereof. */
831 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
832 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
833 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
834 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
835 if (swap == V_028C70_SWAP_STD ||
836 swap == V_028C70_SWAP_STD_REV)
837 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
838 else
839 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
840 }
841 break;
842
843 case V_028C70_COLOR_10_11_11:
844 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
845 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
846 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
847 }
848 break;
849
850 case V_028C70_COLOR_2_10_10_10:
851 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
852 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
853 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
854 }
855 break;
856 }
857 }
858
859 for (unsigned i = subpass->color_count; i < 8; ++i) {
860 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
861 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
862 }
863 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
864 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
865 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
866 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
867 }
868
869 static void
870 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
871 {
872 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
873
874 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
875 return;
876
877 radv_update_multisample_state(cmd_buffer, pipeline);
878
879 cmd_buffer->scratch_size_needed =
880 MAX2(cmd_buffer->scratch_size_needed,
881 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
882
883 if (!cmd_buffer->state.emitted_pipeline ||
884 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
885 pipeline->graphics.can_use_guardband)
886 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
887
888 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
889
890 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
891 if (!pipeline->shaders[i])
892 continue;
893
894 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
895 pipeline->shaders[i]->bo);
896 }
897
898 if (radv_pipeline_has_gs(pipeline))
899 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
900 pipeline->gs_copy_shader->bo);
901
902 if (unlikely(cmd_buffer->device->trace_bo))
903 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
904
905 cmd_buffer->state.emitted_pipeline = pipeline;
906
907 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
908 }
909
910 static void
911 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
912 {
913 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
914 cmd_buffer->state.dynamic.viewport.viewports);
915 }
916
917 static void
918 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
919 {
920 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
921
922 si_write_scissors(cmd_buffer->cs, 0, count,
923 cmd_buffer->state.dynamic.scissor.scissors,
924 cmd_buffer->state.dynamic.viewport.viewports,
925 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
926 }
927
928 static void
929 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
930 {
931 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
932 return;
933
934 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
935 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
936 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
937 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
938 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
939 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
940 S_028214_BR_Y(rect.offset.y + rect.extent.height));
941 }
942 }
943
944 static void
945 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
946 {
947 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
948
949 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
950 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
951 }
952
953 static void
954 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
955 {
956 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
957
958 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
959 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
960 }
961
962 static void
963 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
964 {
965 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
966
967 radeon_set_context_reg_seq(cmd_buffer->cs,
968 R_028430_DB_STENCILREFMASK, 2);
969 radeon_emit(cmd_buffer->cs,
970 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
971 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
972 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
973 S_028430_STENCILOPVAL(1));
974 radeon_emit(cmd_buffer->cs,
975 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
976 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
977 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
978 S_028434_STENCILOPVAL_BF(1));
979 }
980
981 static void
982 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
983 {
984 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
985
986 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
987 fui(d->depth_bounds.min));
988 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
989 fui(d->depth_bounds.max));
990 }
991
992 static void
993 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
994 {
995 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
996 unsigned slope = fui(d->depth_bias.slope * 16.0f);
997 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
998
999
1000 radeon_set_context_reg_seq(cmd_buffer->cs,
1001 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1002 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1003 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1004 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1005 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1006 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1007 }
1008
1009 static void
1010 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1011 int index,
1012 struct radv_attachment_info *att,
1013 struct radv_image *image,
1014 VkImageLayout layout)
1015 {
1016 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1017 struct radv_color_buffer_info *cb = &att->cb;
1018 uint32_t cb_color_info = cb->cb_color_info;
1019
1020 if (!radv_layout_dcc_compressed(image, layout,
1021 radv_image_queue_family_mask(image,
1022 cmd_buffer->queue_family_index,
1023 cmd_buffer->queue_family_index))) {
1024 cb_color_info &= C_028C70_DCC_ENABLE;
1025 }
1026
1027 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1040
1041 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1042 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1043 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1044
1045 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1046 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1047 } else {
1048 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1050 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1052 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1053 radeon_emit(cmd_buffer->cs, cb_color_info);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1055 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1059 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1060
1061 if (is_vi) { /* DCC BASE */
1062 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1063 }
1064 }
1065 }
1066
1067 static void
1068 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1069 struct radv_ds_buffer_info *ds,
1070 struct radv_image *image, VkImageLayout layout,
1071 bool requires_cond_write)
1072 {
1073 uint32_t db_z_info = ds->db_z_info;
1074 uint32_t db_z_info_reg;
1075
1076 if (!radv_image_is_tc_compat_htile(image))
1077 return;
1078
1079 if (!radv_layout_has_htile(image, layout,
1080 radv_image_queue_family_mask(image,
1081 cmd_buffer->queue_family_index,
1082 cmd_buffer->queue_family_index))) {
1083 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1084 }
1085
1086 db_z_info &= C_028040_ZRANGE_PRECISION;
1087
1088 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1089 db_z_info_reg = R_028038_DB_Z_INFO;
1090 } else {
1091 db_z_info_reg = R_028040_DB_Z_INFO;
1092 }
1093
1094 /* When we don't know the last fast clear value we need to emit a
1095 * conditional packet, otherwise we can update DB_Z_INFO directly.
1096 */
1097 if (requires_cond_write) {
1098 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1099
1100 const uint32_t write_space = 0 << 8; /* register */
1101 const uint32_t poll_space = 1 << 4; /* memory */
1102 const uint32_t function = 3 << 0; /* equal to the reference */
1103 const uint32_t options = write_space | poll_space | function;
1104 radeon_emit(cmd_buffer->cs, options);
1105
1106 /* poll address - location of the depth clear value */
1107 uint64_t va = radv_buffer_get_va(image->bo);
1108 va += image->offset + image->clear_value_offset;
1109
1110 /* In presence of stencil format, we have to adjust the base
1111 * address because the first value is the stencil clear value.
1112 */
1113 if (vk_format_is_stencil(image->vk_format))
1114 va += 4;
1115
1116 radeon_emit(cmd_buffer->cs, va);
1117 radeon_emit(cmd_buffer->cs, va >> 32);
1118
1119 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1120 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1121 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1122 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1123 radeon_emit(cmd_buffer->cs, db_z_info);
1124 } else {
1125 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1126 }
1127 }
1128
1129 static void
1130 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1131 struct radv_ds_buffer_info *ds,
1132 struct radv_image *image,
1133 VkImageLayout layout)
1134 {
1135 uint32_t db_z_info = ds->db_z_info;
1136 uint32_t db_stencil_info = ds->db_stencil_info;
1137
1138 if (!radv_layout_has_htile(image, layout,
1139 radv_image_queue_family_mask(image,
1140 cmd_buffer->queue_family_index,
1141 cmd_buffer->queue_family_index))) {
1142 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1143 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1144 }
1145
1146 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1147 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1148
1149
1150 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1152 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1153 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1154 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1155
1156 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1157 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1158 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1159 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1167
1168 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1169 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1170 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1171 } else {
1172 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1173
1174 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1175 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1176 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1177 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1178 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1179 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1183 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1184
1185 }
1186
1187 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1188 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1189
1190 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1191 ds->pa_su_poly_offset_db_fmt_cntl);
1192 }
1193
1194 /**
1195 * Update the fast clear depth/stencil values if the image is bound as a
1196 * depth/stencil buffer.
1197 */
1198 static void
1199 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1200 struct radv_image *image,
1201 VkClearDepthStencilValue ds_clear_value,
1202 VkImageAspectFlags aspects)
1203 {
1204 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1205 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1206 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1207 struct radv_attachment_info *att;
1208 uint32_t att_idx;
1209
1210 if (!framebuffer || !subpass)
1211 return;
1212
1213 att_idx = subpass->depth_stencil_attachment.attachment;
1214 if (att_idx == VK_ATTACHMENT_UNUSED)
1215 return;
1216
1217 att = &framebuffer->attachments[att_idx];
1218 if (att->attachment->image != image)
1219 return;
1220
1221 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1222 radeon_emit(cs, ds_clear_value.stencil);
1223 radeon_emit(cs, fui(ds_clear_value.depth));
1224
1225 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1226 * only needed when clearing Z to 0.0.
1227 */
1228 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1229 ds_clear_value.depth == 0.0) {
1230 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1231
1232 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1233 layout, false);
1234 }
1235 }
1236
1237 /**
1238 * Set the clear depth/stencil values to the image's metadata.
1239 */
1240 static void
1241 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1242 struct radv_image *image,
1243 VkClearDepthStencilValue ds_clear_value,
1244 VkImageAspectFlags aspects)
1245 {
1246 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1247 uint64_t va = radv_buffer_get_va(image->bo);
1248 unsigned reg_offset = 0, reg_count = 0;
1249
1250 va += image->offset + image->clear_value_offset;
1251
1252 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1253 ++reg_count;
1254 } else {
1255 ++reg_offset;
1256 va += 4;
1257 }
1258 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1259 ++reg_count;
1260
1261 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1262 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1263 S_370_WR_CONFIRM(1) |
1264 S_370_ENGINE_SEL(V_370_PFP));
1265 radeon_emit(cs, va);
1266 radeon_emit(cs, va >> 32);
1267 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1268 radeon_emit(cs, ds_clear_value.stencil);
1269 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1270 radeon_emit(cs, fui(ds_clear_value.depth));
1271 }
1272
1273 /**
1274 * Update the clear depth/stencil values for this image.
1275 */
1276 void
1277 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image,
1279 VkClearDepthStencilValue ds_clear_value,
1280 VkImageAspectFlags aspects)
1281 {
1282 assert(radv_image_has_htile(image));
1283
1284 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1285
1286 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1287 aspects);
1288 }
1289
1290 /**
1291 * Load the clear depth/stencil values from the image's metadata.
1292 */
1293 static void
1294 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1295 struct radv_image *image)
1296 {
1297 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1298 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1299 uint64_t va = radv_buffer_get_va(image->bo);
1300 unsigned reg_offset = 0, reg_count = 0;
1301
1302 va += image->offset + image->clear_value_offset;
1303
1304 if (!radv_image_has_htile(image))
1305 return;
1306
1307 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1308 ++reg_count;
1309 } else {
1310 ++reg_offset;
1311 va += 4;
1312 }
1313 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1314 ++reg_count;
1315
1316 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1317 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1318 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1319 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1320 radeon_emit(cs, va);
1321 radeon_emit(cs, va >> 32);
1322 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1323 radeon_emit(cs, 0);
1324
1325 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1326 radeon_emit(cs, 0);
1327 }
1328
1329 /*
1330 * With DCC some colors don't require CMASK elimination before being
1331 * used as a texture. This sets a predicate value to determine if the
1332 * cmask eliminate is required.
1333 */
1334 void
1335 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1336 struct radv_image *image,
1337 bool value)
1338 {
1339 uint64_t pred_val = value;
1340 uint64_t va = radv_buffer_get_va(image->bo);
1341 va += image->offset + image->dcc_pred_offset;
1342
1343 assert(radv_image_has_dcc(image));
1344
1345 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1346 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1347 S_370_WR_CONFIRM(1) |
1348 S_370_ENGINE_SEL(V_370_PFP));
1349 radeon_emit(cmd_buffer->cs, va);
1350 radeon_emit(cmd_buffer->cs, va >> 32);
1351 radeon_emit(cmd_buffer->cs, pred_val);
1352 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1353 }
1354
1355 /**
1356 * Update the fast clear color values if the image is bound as a color buffer.
1357 */
1358 static void
1359 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1360 struct radv_image *image,
1361 int cb_idx,
1362 uint32_t color_values[2])
1363 {
1364 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1365 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1366 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1367 struct radv_attachment_info *att;
1368 uint32_t att_idx;
1369
1370 if (!framebuffer || !subpass)
1371 return;
1372
1373 att_idx = subpass->color_attachments[cb_idx].attachment;
1374 if (att_idx == VK_ATTACHMENT_UNUSED)
1375 return;
1376
1377 att = &framebuffer->attachments[att_idx];
1378 if (att->attachment->image != image)
1379 return;
1380
1381 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1382 radeon_emit(cs, color_values[0]);
1383 radeon_emit(cs, color_values[1]);
1384 }
1385
1386 /**
1387 * Set the clear color values to the image's metadata.
1388 */
1389 static void
1390 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1391 struct radv_image *image,
1392 uint32_t color_values[2])
1393 {
1394 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1395 uint64_t va = radv_buffer_get_va(image->bo);
1396
1397 va += image->offset + image->clear_value_offset;
1398
1399 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1400
1401 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1402 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1403 S_370_WR_CONFIRM(1) |
1404 S_370_ENGINE_SEL(V_370_PFP));
1405 radeon_emit(cs, va);
1406 radeon_emit(cs, va >> 32);
1407 radeon_emit(cs, color_values[0]);
1408 radeon_emit(cs, color_values[1]);
1409 }
1410
1411 /**
1412 * Update the clear color values for this image.
1413 */
1414 void
1415 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image,
1417 int cb_idx,
1418 uint32_t color_values[2])
1419 {
1420 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1421
1422 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1423
1424 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1425 color_values);
1426 }
1427
1428 /**
1429 * Load the clear color values from the image's metadata.
1430 */
1431 static void
1432 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1433 struct radv_image *image,
1434 int cb_idx)
1435 {
1436 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1437 uint64_t va = radv_buffer_get_va(image->bo);
1438
1439 va += image->offset + image->clear_value_offset;
1440
1441 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1442 return;
1443
1444 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1445
1446 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1447 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1448 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1449 COPY_DATA_COUNT_SEL);
1450 radeon_emit(cs, va);
1451 radeon_emit(cs, va >> 32);
1452 radeon_emit(cs, reg >> 2);
1453 radeon_emit(cs, 0);
1454
1455 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1456 radeon_emit(cs, 0);
1457 }
1458
1459 static void
1460 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1461 {
1462 int i;
1463 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1464 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1465
1466 /* this may happen for inherited secondary recording */
1467 if (!framebuffer)
1468 return;
1469
1470 for (i = 0; i < 8; ++i) {
1471 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1472 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1473 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1474 continue;
1475 }
1476
1477 int idx = subpass->color_attachments[i].attachment;
1478 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1479 struct radv_image *image = att->attachment->image;
1480 VkImageLayout layout = subpass->color_attachments[i].layout;
1481
1482 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1483
1484 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1485 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1486
1487 radv_load_color_clear_metadata(cmd_buffer, image, i);
1488 }
1489
1490 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1491 int idx = subpass->depth_stencil_attachment.attachment;
1492 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1493 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1494 struct radv_image *image = att->attachment->image;
1495 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1496 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1497 cmd_buffer->queue_family_index,
1498 cmd_buffer->queue_family_index);
1499 /* We currently don't support writing decompressed HTILE */
1500 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1501 radv_layout_is_htile_compressed(image, layout, queue_mask));
1502
1503 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1504
1505 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1507 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1508 }
1509 radv_load_ds_clear_metadata(cmd_buffer, image);
1510 } else {
1511 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1512 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1513 else
1514 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1515
1516 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1517 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1518 }
1519 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1520 S_028208_BR_X(framebuffer->width) |
1521 S_028208_BR_Y(framebuffer->height));
1522
1523 if (cmd_buffer->device->dfsm_allowed) {
1524 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1525 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1526 }
1527
1528 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1529 }
1530
1531 static void
1532 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1533 {
1534 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1535 struct radv_cmd_state *state = &cmd_buffer->state;
1536
1537 if (state->index_type != state->last_index_type) {
1538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1539 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1540 2, state->index_type);
1541 } else {
1542 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1543 radeon_emit(cs, state->index_type);
1544 }
1545
1546 state->last_index_type = state->index_type;
1547 }
1548
1549 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1550 radeon_emit(cs, state->index_va);
1551 radeon_emit(cs, state->index_va >> 32);
1552
1553 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1554 radeon_emit(cs, state->max_index_count);
1555
1556 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1557 }
1558
1559 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1560 {
1561 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1562 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1563 uint32_t pa_sc_mode_cntl_1 =
1564 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1565 uint32_t db_count_control;
1566
1567 if(!cmd_buffer->state.active_occlusion_queries) {
1568 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1569 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1570 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1571 has_perfect_queries) {
1572 /* Re-enable out-of-order rasterization if the
1573 * bound pipeline supports it and if it's has
1574 * been disabled before starting any perfect
1575 * occlusion queries.
1576 */
1577 radeon_set_context_reg(cmd_buffer->cs,
1578 R_028A4C_PA_SC_MODE_CNTL_1,
1579 pa_sc_mode_cntl_1);
1580 }
1581 }
1582 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1583 } else {
1584 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1585 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1586
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1588 db_count_control =
1589 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1590 S_028004_SAMPLE_RATE(sample_rate) |
1591 S_028004_ZPASS_ENABLE(1) |
1592 S_028004_SLICE_EVEN_ENABLE(1) |
1593 S_028004_SLICE_ODD_ENABLE(1);
1594
1595 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1596 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1597 has_perfect_queries) {
1598 /* If the bound pipeline has enabled
1599 * out-of-order rasterization, we should
1600 * disable it before starting any perfect
1601 * occlusion queries.
1602 */
1603 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1604
1605 radeon_set_context_reg(cmd_buffer->cs,
1606 R_028A4C_PA_SC_MODE_CNTL_1,
1607 pa_sc_mode_cntl_1);
1608 }
1609 } else {
1610 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1611 S_028004_SAMPLE_RATE(sample_rate);
1612 }
1613 }
1614
1615 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1616 }
1617
1618 static void
1619 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1620 {
1621 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1622
1623 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1624 radv_emit_viewport(cmd_buffer);
1625
1626 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1627 !cmd_buffer->device->physical_device->has_scissor_bug)
1628 radv_emit_scissor(cmd_buffer);
1629
1630 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1631 radv_emit_line_width(cmd_buffer);
1632
1633 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1634 radv_emit_blend_constants(cmd_buffer);
1635
1636 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1637 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1638 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1639 radv_emit_stencil(cmd_buffer);
1640
1641 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1642 radv_emit_depth_bounds(cmd_buffer);
1643
1644 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1645 radv_emit_depth_bias(cmd_buffer);
1646
1647 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1648 radv_emit_discard_rectangle(cmd_buffer);
1649
1650 cmd_buffer->state.dirty &= ~states;
1651 }
1652
1653 static void
1654 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1655 VkPipelineBindPoint bind_point)
1656 {
1657 struct radv_descriptor_state *descriptors_state =
1658 radv_get_descriptors_state(cmd_buffer, bind_point);
1659 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1660 unsigned bo_offset;
1661
1662 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1663 set->mapped_ptr,
1664 &bo_offset))
1665 return;
1666
1667 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1668 set->va += bo_offset;
1669 }
1670
1671 static void
1672 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1673 VkPipelineBindPoint bind_point)
1674 {
1675 struct radv_descriptor_state *descriptors_state =
1676 radv_get_descriptors_state(cmd_buffer, bind_point);
1677 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1678 uint32_t size = MAX_SETS * 4 * ptr_size;
1679 uint32_t offset;
1680 void *ptr;
1681
1682 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1683 256, &offset, &ptr))
1684 return;
1685
1686 for (unsigned i = 0; i < MAX_SETS; i++) {
1687 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1688 uint64_t set_va = 0;
1689 struct radv_descriptor_set *set = descriptors_state->sets[i];
1690 if (descriptors_state->valid & (1u << i))
1691 set_va = set->va;
1692 uptr[0] = set_va & 0xffffffff;
1693 if (ptr_size == 2)
1694 uptr[1] = set_va >> 32;
1695 }
1696
1697 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1698 va += offset;
1699
1700 if (cmd_buffer->state.pipeline) {
1701 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1702 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1703 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1704
1705 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1706 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1707 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1708
1709 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1710 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1711 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1712
1713 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1714 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1715 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1716
1717 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1718 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1719 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1720 }
1721
1722 if (cmd_buffer->state.compute_pipeline)
1723 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1724 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1725 }
1726
1727 static void
1728 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1729 VkShaderStageFlags stages)
1730 {
1731 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1732 VK_PIPELINE_BIND_POINT_COMPUTE :
1733 VK_PIPELINE_BIND_POINT_GRAPHICS;
1734 struct radv_descriptor_state *descriptors_state =
1735 radv_get_descriptors_state(cmd_buffer, bind_point);
1736 struct radv_cmd_state *state = &cmd_buffer->state;
1737 bool flush_indirect_descriptors;
1738
1739 if (!descriptors_state->dirty)
1740 return;
1741
1742 if (descriptors_state->push_dirty)
1743 radv_flush_push_descriptors(cmd_buffer, bind_point);
1744
1745 flush_indirect_descriptors =
1746 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1747 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1748 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1749 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1750
1751 if (flush_indirect_descriptors)
1752 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1753
1754 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1755 cmd_buffer->cs,
1756 MAX_SETS * MESA_SHADER_STAGES * 4);
1757
1758 if (cmd_buffer->state.pipeline) {
1759 radv_foreach_stage(stage, stages) {
1760 if (!cmd_buffer->state.pipeline->shaders[stage])
1761 continue;
1762
1763 radv_emit_descriptor_pointers(cmd_buffer,
1764 cmd_buffer->state.pipeline,
1765 descriptors_state, stage);
1766 }
1767 }
1768
1769 if (cmd_buffer->state.compute_pipeline &&
1770 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1771 radv_emit_descriptor_pointers(cmd_buffer,
1772 cmd_buffer->state.compute_pipeline,
1773 descriptors_state,
1774 MESA_SHADER_COMPUTE);
1775 }
1776
1777 descriptors_state->dirty = 0;
1778 descriptors_state->push_dirty = false;
1779
1780 assert(cmd_buffer->cs->cdw <= cdw_max);
1781
1782 if (unlikely(cmd_buffer->device->trace_bo))
1783 radv_save_descriptors(cmd_buffer, bind_point);
1784 }
1785
1786 static void
1787 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1788 VkShaderStageFlags stages)
1789 {
1790 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1791 ? cmd_buffer->state.compute_pipeline
1792 : cmd_buffer->state.pipeline;
1793 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1794 VK_PIPELINE_BIND_POINT_COMPUTE :
1795 VK_PIPELINE_BIND_POINT_GRAPHICS;
1796 struct radv_descriptor_state *descriptors_state =
1797 radv_get_descriptors_state(cmd_buffer, bind_point);
1798 struct radv_pipeline_layout *layout = pipeline->layout;
1799 struct radv_shader_variant *shader, *prev_shader;
1800 unsigned offset;
1801 void *ptr;
1802 uint64_t va;
1803
1804 stages &= cmd_buffer->push_constant_stages;
1805 if (!stages ||
1806 (!layout->push_constant_size && !layout->dynamic_offset_count))
1807 return;
1808
1809 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1810 16 * layout->dynamic_offset_count,
1811 256, &offset, &ptr))
1812 return;
1813
1814 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1815 memcpy((char*)ptr + layout->push_constant_size,
1816 descriptors_state->dynamic_buffers,
1817 16 * layout->dynamic_offset_count);
1818
1819 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1820 va += offset;
1821
1822 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1823 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1824
1825 prev_shader = NULL;
1826 radv_foreach_stage(stage, stages) {
1827 shader = radv_get_shader(pipeline, stage);
1828
1829 /* Avoid redundantly emitting the address for merged stages. */
1830 if (shader && shader != prev_shader) {
1831 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1832 AC_UD_PUSH_CONSTANTS, va);
1833
1834 prev_shader = shader;
1835 }
1836 }
1837
1838 cmd_buffer->push_constant_stages &= ~stages;
1839 assert(cmd_buffer->cs->cdw <= cdw_max);
1840 }
1841
1842 static void
1843 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1844 bool pipeline_is_dirty)
1845 {
1846 if ((pipeline_is_dirty ||
1847 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1848 cmd_buffer->state.pipeline->vertex_elements.count &&
1849 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1850 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1851 unsigned vb_offset;
1852 void *vb_ptr;
1853 uint32_t i = 0;
1854 uint32_t count = velems->count;
1855 uint64_t va;
1856
1857 /* allocate some descriptor state for vertex buffers */
1858 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1859 &vb_offset, &vb_ptr))
1860 return;
1861
1862 for (i = 0; i < count; i++) {
1863 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1864 uint32_t offset;
1865 int vb = velems->binding[i];
1866 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1867 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1868
1869 va = radv_buffer_get_va(buffer->bo);
1870
1871 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1872 va += offset + buffer->offset;
1873 desc[0] = va;
1874 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1875 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1876 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1877 else
1878 desc[2] = buffer->size - offset;
1879 desc[3] = velems->rsrc_word3[i];
1880 }
1881
1882 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1883 va += vb_offset;
1884
1885 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1886 AC_UD_VS_VERTEX_BUFFERS, va);
1887
1888 cmd_buffer->state.vb_va = va;
1889 cmd_buffer->state.vb_size = count * 16;
1890 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1891 }
1892 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1893 }
1894
1895 static void
1896 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1897 {
1898 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1899 struct radv_userdata_info *loc;
1900 uint32_t base_reg;
1901
1902 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1903 if (!radv_get_shader(pipeline, stage))
1904 continue;
1905
1906 loc = radv_lookup_user_sgpr(pipeline, stage,
1907 AC_UD_STREAMOUT_BUFFERS);
1908 if (loc->sgpr_idx == -1)
1909 continue;
1910
1911 base_reg = pipeline->user_data_0[stage];
1912
1913 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1914 base_reg + loc->sgpr_idx * 4, va, false);
1915 }
1916
1917 if (pipeline->gs_copy_shader) {
1918 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1919 if (loc->sgpr_idx != -1) {
1920 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1921
1922 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1923 base_reg + loc->sgpr_idx * 4, va, false);
1924 }
1925 }
1926 }
1927
1928 static void
1929 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1930 {
1931 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1932 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1933 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1934 unsigned so_offset;
1935 void *so_ptr;
1936 uint64_t va;
1937
1938 /* Allocate some descriptor state for streamout buffers. */
1939 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1940 MAX_SO_BUFFERS * 16, 256,
1941 &so_offset, &so_ptr))
1942 return;
1943
1944 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1945 struct radv_buffer *buffer = sb[i].buffer;
1946 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1947
1948 if (!(so->enabled_mask & (1 << i)))
1949 continue;
1950
1951 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1952
1953 /* Set the descriptor.
1954 *
1955 * On VI, the format must be non-INVALID, otherwise
1956 * the buffer will be considered not bound and store
1957 * instructions will be no-ops.
1958 */
1959 desc[0] = va;
1960 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1961 desc[2] = 0xffffffff;
1962 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1963 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1964 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1965 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1966 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1967 }
1968
1969 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1970 va += so_offset;
1971
1972 radv_emit_streamout_buffers(cmd_buffer, va);
1973 }
1974
1975 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
1976 }
1977
1978 static void
1979 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1980 {
1981 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1982 radv_flush_streamout_descriptors(cmd_buffer);
1983 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1984 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1985 }
1986
1987 static void
1988 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1989 bool instanced_draw, bool indirect_draw,
1990 uint32_t draw_vertex_count)
1991 {
1992 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1993 struct radv_cmd_state *state = &cmd_buffer->state;
1994 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1995 uint32_t ia_multi_vgt_param;
1996 int32_t primitive_reset_en;
1997
1998 /* Draw state. */
1999 ia_multi_vgt_param =
2000 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2001 indirect_draw, draw_vertex_count);
2002
2003 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2004 if (info->chip_class >= GFX9) {
2005 radeon_set_uconfig_reg_idx(cs,
2006 R_030960_IA_MULTI_VGT_PARAM,
2007 4, ia_multi_vgt_param);
2008 } else if (info->chip_class >= CIK) {
2009 radeon_set_context_reg_idx(cs,
2010 R_028AA8_IA_MULTI_VGT_PARAM,
2011 1, ia_multi_vgt_param);
2012 } else {
2013 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2014 ia_multi_vgt_param);
2015 }
2016 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2017 }
2018
2019 /* Primitive restart. */
2020 primitive_reset_en =
2021 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2022
2023 if (primitive_reset_en != state->last_primitive_reset_en) {
2024 state->last_primitive_reset_en = primitive_reset_en;
2025 if (info->chip_class >= GFX9) {
2026 radeon_set_uconfig_reg(cs,
2027 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2028 primitive_reset_en);
2029 } else {
2030 radeon_set_context_reg(cs,
2031 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2032 primitive_reset_en);
2033 }
2034 }
2035
2036 if (primitive_reset_en) {
2037 uint32_t primitive_reset_index =
2038 state->index_type ? 0xffffffffu : 0xffffu;
2039
2040 if (primitive_reset_index != state->last_primitive_reset_index) {
2041 radeon_set_context_reg(cs,
2042 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2043 primitive_reset_index);
2044 state->last_primitive_reset_index = primitive_reset_index;
2045 }
2046 }
2047 }
2048
2049 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2050 VkPipelineStageFlags src_stage_mask)
2051 {
2052 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2053 VK_PIPELINE_STAGE_TRANSFER_BIT |
2054 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2055 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2056 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2057 }
2058
2059 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2060 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2061 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2062 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2063 VK_PIPELINE_STAGE_TRANSFER_BIT |
2064 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2065 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2066 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2067 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2068 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2069 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2070 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2071 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2072 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2073 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2074 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2075 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2076 }
2077 }
2078
2079 static enum radv_cmd_flush_bits
2080 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2081 VkAccessFlags src_flags,
2082 struct radv_image *image)
2083 {
2084 bool flush_CB_meta = true, flush_DB_meta = true;
2085 enum radv_cmd_flush_bits flush_bits = 0;
2086 uint32_t b;
2087
2088 if (image) {
2089 if (!radv_image_has_CB_metadata(image))
2090 flush_CB_meta = false;
2091 if (!radv_image_has_htile(image))
2092 flush_DB_meta = false;
2093 }
2094
2095 for_each_bit(b, src_flags) {
2096 switch ((VkAccessFlagBits)(1 << b)) {
2097 case VK_ACCESS_SHADER_WRITE_BIT:
2098 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2099 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2100 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2101 break;
2102 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2103 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2104 if (flush_CB_meta)
2105 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2106 break;
2107 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2108 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2109 if (flush_DB_meta)
2110 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2111 break;
2112 case VK_ACCESS_TRANSFER_WRITE_BIT:
2113 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2114 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2115 RADV_CMD_FLAG_INV_GLOBAL_L2;
2116
2117 if (flush_CB_meta)
2118 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2119 if (flush_DB_meta)
2120 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2121 break;
2122 default:
2123 break;
2124 }
2125 }
2126 return flush_bits;
2127 }
2128
2129 static enum radv_cmd_flush_bits
2130 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2131 VkAccessFlags dst_flags,
2132 struct radv_image *image)
2133 {
2134 bool flush_CB_meta = true, flush_DB_meta = true;
2135 enum radv_cmd_flush_bits flush_bits = 0;
2136 bool flush_CB = true, flush_DB = true;
2137 bool image_is_coherent = false;
2138 uint32_t b;
2139
2140 if (image) {
2141 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2142 flush_CB = false;
2143 flush_DB = false;
2144 }
2145
2146 if (!radv_image_has_CB_metadata(image))
2147 flush_CB_meta = false;
2148 if (!radv_image_has_htile(image))
2149 flush_DB_meta = false;
2150
2151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2152 if (image->info.samples == 1 &&
2153 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2154 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2155 !vk_format_is_stencil(image->vk_format)) {
2156 /* Single-sample color and single-sample depth
2157 * (not stencil) are coherent with shaders on
2158 * GFX9.
2159 */
2160 image_is_coherent = true;
2161 }
2162 }
2163 }
2164
2165 for_each_bit(b, dst_flags) {
2166 switch ((VkAccessFlagBits)(1 << b)) {
2167 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2168 case VK_ACCESS_INDEX_READ_BIT:
2169 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2170 break;
2171 case VK_ACCESS_UNIFORM_READ_BIT:
2172 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2173 break;
2174 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2175 case VK_ACCESS_TRANSFER_READ_BIT:
2176 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2177 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2178 RADV_CMD_FLAG_INV_GLOBAL_L2;
2179 break;
2180 case VK_ACCESS_SHADER_READ_BIT:
2181 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2182
2183 if (!image_is_coherent)
2184 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2185 break;
2186 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2187 if (flush_CB)
2188 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2189 if (flush_CB_meta)
2190 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2191 break;
2192 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2193 if (flush_DB)
2194 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2195 if (flush_DB_meta)
2196 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2197 break;
2198 default:
2199 break;
2200 }
2201 }
2202 return flush_bits;
2203 }
2204
2205 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2206 const struct radv_subpass_barrier *barrier)
2207 {
2208 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2209 NULL);
2210 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2211 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2212 NULL);
2213 }
2214
2215 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2216 struct radv_subpass_attachment att)
2217 {
2218 unsigned idx = att.attachment;
2219 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2220 VkImageSubresourceRange range;
2221 range.aspectMask = 0;
2222 range.baseMipLevel = view->base_mip;
2223 range.levelCount = 1;
2224 range.baseArrayLayer = view->base_layer;
2225 range.layerCount = cmd_buffer->state.framebuffer->layers;
2226
2227 radv_handle_image_transition(cmd_buffer,
2228 view->image,
2229 cmd_buffer->state.attachments[idx].current_layout,
2230 att.layout, 0, 0, &range,
2231 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2232
2233 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2234
2235
2236 }
2237
2238 void
2239 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2240 const struct radv_subpass *subpass, bool transitions)
2241 {
2242 if (transitions) {
2243 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2244
2245 for (unsigned i = 0; i < subpass->color_count; ++i) {
2246 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2247 radv_handle_subpass_image_transition(cmd_buffer,
2248 subpass->color_attachments[i]);
2249 }
2250
2251 for (unsigned i = 0; i < subpass->input_count; ++i) {
2252 radv_handle_subpass_image_transition(cmd_buffer,
2253 subpass->input_attachments[i]);
2254 }
2255
2256 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2257 radv_handle_subpass_image_transition(cmd_buffer,
2258 subpass->depth_stencil_attachment);
2259 }
2260 }
2261
2262 cmd_buffer->state.subpass = subpass;
2263
2264 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2265 }
2266
2267 static VkResult
2268 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2269 struct radv_render_pass *pass,
2270 const VkRenderPassBeginInfo *info)
2271 {
2272 struct radv_cmd_state *state = &cmd_buffer->state;
2273
2274 if (pass->attachment_count == 0) {
2275 state->attachments = NULL;
2276 return VK_SUCCESS;
2277 }
2278
2279 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2280 pass->attachment_count *
2281 sizeof(state->attachments[0]),
2282 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2283 if (state->attachments == NULL) {
2284 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2285 return cmd_buffer->record_result;
2286 }
2287
2288 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2289 struct radv_render_pass_attachment *att = &pass->attachments[i];
2290 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2291 VkImageAspectFlags clear_aspects = 0;
2292
2293 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2294 /* color attachment */
2295 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2296 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2297 }
2298 } else {
2299 /* depthstencil attachment */
2300 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2301 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2302 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2303 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2304 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2305 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2306 }
2307 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2308 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2309 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2310 }
2311 }
2312
2313 state->attachments[i].pending_clear_aspects = clear_aspects;
2314 state->attachments[i].cleared_views = 0;
2315 if (clear_aspects && info) {
2316 assert(info->clearValueCount > i);
2317 state->attachments[i].clear_value = info->pClearValues[i];
2318 }
2319
2320 state->attachments[i].current_layout = att->initial_layout;
2321 }
2322
2323 return VK_SUCCESS;
2324 }
2325
2326 VkResult radv_AllocateCommandBuffers(
2327 VkDevice _device,
2328 const VkCommandBufferAllocateInfo *pAllocateInfo,
2329 VkCommandBuffer *pCommandBuffers)
2330 {
2331 RADV_FROM_HANDLE(radv_device, device, _device);
2332 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2333
2334 VkResult result = VK_SUCCESS;
2335 uint32_t i;
2336
2337 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2338
2339 if (!list_empty(&pool->free_cmd_buffers)) {
2340 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2341
2342 list_del(&cmd_buffer->pool_link);
2343 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2344
2345 result = radv_reset_cmd_buffer(cmd_buffer);
2346 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2347 cmd_buffer->level = pAllocateInfo->level;
2348
2349 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2350 } else {
2351 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2352 &pCommandBuffers[i]);
2353 }
2354 if (result != VK_SUCCESS)
2355 break;
2356 }
2357
2358 if (result != VK_SUCCESS) {
2359 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2360 i, pCommandBuffers);
2361
2362 /* From the Vulkan 1.0.66 spec:
2363 *
2364 * "vkAllocateCommandBuffers can be used to create multiple
2365 * command buffers. If the creation of any of those command
2366 * buffers fails, the implementation must destroy all
2367 * successfully created command buffer objects from this
2368 * command, set all entries of the pCommandBuffers array to
2369 * NULL and return the error."
2370 */
2371 memset(pCommandBuffers, 0,
2372 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2373 }
2374
2375 return result;
2376 }
2377
2378 void radv_FreeCommandBuffers(
2379 VkDevice device,
2380 VkCommandPool commandPool,
2381 uint32_t commandBufferCount,
2382 const VkCommandBuffer *pCommandBuffers)
2383 {
2384 for (uint32_t i = 0; i < commandBufferCount; i++) {
2385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2386
2387 if (cmd_buffer) {
2388 if (cmd_buffer->pool) {
2389 list_del(&cmd_buffer->pool_link);
2390 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2391 } else
2392 radv_cmd_buffer_destroy(cmd_buffer);
2393
2394 }
2395 }
2396 }
2397
2398 VkResult radv_ResetCommandBuffer(
2399 VkCommandBuffer commandBuffer,
2400 VkCommandBufferResetFlags flags)
2401 {
2402 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2403 return radv_reset_cmd_buffer(cmd_buffer);
2404 }
2405
2406 VkResult radv_BeginCommandBuffer(
2407 VkCommandBuffer commandBuffer,
2408 const VkCommandBufferBeginInfo *pBeginInfo)
2409 {
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2411 VkResult result = VK_SUCCESS;
2412
2413 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2414 /* If the command buffer has already been resetted with
2415 * vkResetCommandBuffer, no need to do it again.
2416 */
2417 result = radv_reset_cmd_buffer(cmd_buffer);
2418 if (result != VK_SUCCESS)
2419 return result;
2420 }
2421
2422 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2423 cmd_buffer->state.last_primitive_reset_en = -1;
2424 cmd_buffer->state.last_index_type = -1;
2425 cmd_buffer->state.last_num_instances = -1;
2426 cmd_buffer->state.last_vertex_offset = -1;
2427 cmd_buffer->state.last_first_instance = -1;
2428 cmd_buffer->state.predication_type = -1;
2429 cmd_buffer->usage_flags = pBeginInfo->flags;
2430
2431 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2432 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2433 assert(pBeginInfo->pInheritanceInfo);
2434 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2435 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2436
2437 struct radv_subpass *subpass =
2438 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2439
2440 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2441 if (result != VK_SUCCESS)
2442 return result;
2443
2444 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2445 }
2446
2447 if (unlikely(cmd_buffer->device->trace_bo)) {
2448 struct radv_device *device = cmd_buffer->device;
2449
2450 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2451 device->trace_bo);
2452
2453 radv_cmd_buffer_trace_emit(cmd_buffer);
2454 }
2455
2456 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2457
2458 return result;
2459 }
2460
2461 void radv_CmdBindVertexBuffers(
2462 VkCommandBuffer commandBuffer,
2463 uint32_t firstBinding,
2464 uint32_t bindingCount,
2465 const VkBuffer* pBuffers,
2466 const VkDeviceSize* pOffsets)
2467 {
2468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2469 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2470 bool changed = false;
2471
2472 /* We have to defer setting up vertex buffer since we need the buffer
2473 * stride from the pipeline. */
2474
2475 assert(firstBinding + bindingCount <= MAX_VBS);
2476 for (uint32_t i = 0; i < bindingCount; i++) {
2477 uint32_t idx = firstBinding + i;
2478
2479 if (!changed &&
2480 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2481 vb[idx].offset != pOffsets[i])) {
2482 changed = true;
2483 }
2484
2485 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2486 vb[idx].offset = pOffsets[i];
2487
2488 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2489 vb[idx].buffer->bo);
2490 }
2491
2492 if (!changed) {
2493 /* No state changes. */
2494 return;
2495 }
2496
2497 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2498 }
2499
2500 void radv_CmdBindIndexBuffer(
2501 VkCommandBuffer commandBuffer,
2502 VkBuffer buffer,
2503 VkDeviceSize offset,
2504 VkIndexType indexType)
2505 {
2506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2507 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2508
2509 if (cmd_buffer->state.index_buffer == index_buffer &&
2510 cmd_buffer->state.index_offset == offset &&
2511 cmd_buffer->state.index_type == indexType) {
2512 /* No state changes. */
2513 return;
2514 }
2515
2516 cmd_buffer->state.index_buffer = index_buffer;
2517 cmd_buffer->state.index_offset = offset;
2518 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2519 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2520 cmd_buffer->state.index_va += index_buffer->offset + offset;
2521
2522 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2523 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2524 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2525 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2526 }
2527
2528
2529 static void
2530 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2531 VkPipelineBindPoint bind_point,
2532 struct radv_descriptor_set *set, unsigned idx)
2533 {
2534 struct radeon_winsys *ws = cmd_buffer->device->ws;
2535
2536 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2537
2538 assert(set);
2539 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2540
2541 if (!cmd_buffer->device->use_global_bo_list) {
2542 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2543 if (set->descriptors[j])
2544 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2545 }
2546
2547 if(set->bo)
2548 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2549 }
2550
2551 void radv_CmdBindDescriptorSets(
2552 VkCommandBuffer commandBuffer,
2553 VkPipelineBindPoint pipelineBindPoint,
2554 VkPipelineLayout _layout,
2555 uint32_t firstSet,
2556 uint32_t descriptorSetCount,
2557 const VkDescriptorSet* pDescriptorSets,
2558 uint32_t dynamicOffsetCount,
2559 const uint32_t* pDynamicOffsets)
2560 {
2561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2562 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2563 unsigned dyn_idx = 0;
2564
2565 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2566 struct radv_descriptor_state *descriptors_state =
2567 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2568
2569 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2570 unsigned idx = i + firstSet;
2571 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2572 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2573
2574 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2575 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2576 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2577 assert(dyn_idx < dynamicOffsetCount);
2578
2579 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2580 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2581 dst[0] = va;
2582 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2583 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2584 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2585 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2586 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2587 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2588 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2589 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2590 cmd_buffer->push_constant_stages |=
2591 set->layout->dynamic_shader_stages;
2592 }
2593 }
2594 }
2595
2596 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2597 struct radv_descriptor_set *set,
2598 struct radv_descriptor_set_layout *layout,
2599 VkPipelineBindPoint bind_point)
2600 {
2601 struct radv_descriptor_state *descriptors_state =
2602 radv_get_descriptors_state(cmd_buffer, bind_point);
2603 set->size = layout->size;
2604 set->layout = layout;
2605
2606 if (descriptors_state->push_set.capacity < set->size) {
2607 size_t new_size = MAX2(set->size, 1024);
2608 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2609 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2610
2611 free(set->mapped_ptr);
2612 set->mapped_ptr = malloc(new_size);
2613
2614 if (!set->mapped_ptr) {
2615 descriptors_state->push_set.capacity = 0;
2616 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2617 return false;
2618 }
2619
2620 descriptors_state->push_set.capacity = new_size;
2621 }
2622
2623 return true;
2624 }
2625
2626 void radv_meta_push_descriptor_set(
2627 struct radv_cmd_buffer* cmd_buffer,
2628 VkPipelineBindPoint pipelineBindPoint,
2629 VkPipelineLayout _layout,
2630 uint32_t set,
2631 uint32_t descriptorWriteCount,
2632 const VkWriteDescriptorSet* pDescriptorWrites)
2633 {
2634 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2635 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2636 unsigned bo_offset;
2637
2638 assert(set == 0);
2639 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2640
2641 push_set->size = layout->set[set].layout->size;
2642 push_set->layout = layout->set[set].layout;
2643
2644 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2645 &bo_offset,
2646 (void**) &push_set->mapped_ptr))
2647 return;
2648
2649 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2650 push_set->va += bo_offset;
2651
2652 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2653 radv_descriptor_set_to_handle(push_set),
2654 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2655
2656 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2657 }
2658
2659 void radv_CmdPushDescriptorSetKHR(
2660 VkCommandBuffer commandBuffer,
2661 VkPipelineBindPoint pipelineBindPoint,
2662 VkPipelineLayout _layout,
2663 uint32_t set,
2664 uint32_t descriptorWriteCount,
2665 const VkWriteDescriptorSet* pDescriptorWrites)
2666 {
2667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2668 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2669 struct radv_descriptor_state *descriptors_state =
2670 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2671 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2672
2673 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2674
2675 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2676 layout->set[set].layout,
2677 pipelineBindPoint))
2678 return;
2679
2680 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2681 radv_descriptor_set_to_handle(push_set),
2682 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2683
2684 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2685 descriptors_state->push_dirty = true;
2686 }
2687
2688 void radv_CmdPushDescriptorSetWithTemplateKHR(
2689 VkCommandBuffer commandBuffer,
2690 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2691 VkPipelineLayout _layout,
2692 uint32_t set,
2693 const void* pData)
2694 {
2695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2696 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2697 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2698 struct radv_descriptor_state *descriptors_state =
2699 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2700 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2701
2702 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2703
2704 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2705 layout->set[set].layout,
2706 templ->bind_point))
2707 return;
2708
2709 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2710 descriptorUpdateTemplate, pData);
2711
2712 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2713 descriptors_state->push_dirty = true;
2714 }
2715
2716 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2717 VkPipelineLayout layout,
2718 VkShaderStageFlags stageFlags,
2719 uint32_t offset,
2720 uint32_t size,
2721 const void* pValues)
2722 {
2723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2724 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2725 cmd_buffer->push_constant_stages |= stageFlags;
2726 }
2727
2728 VkResult radv_EndCommandBuffer(
2729 VkCommandBuffer commandBuffer)
2730 {
2731 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2732
2733 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2734 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2735 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2736 si_emit_cache_flush(cmd_buffer);
2737 }
2738
2739 /* Make sure CP DMA is idle at the end of IBs because the kernel
2740 * doesn't wait for it.
2741 */
2742 si_cp_dma_wait_for_idle(cmd_buffer);
2743
2744 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2745
2746 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2747 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2748
2749 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2750
2751 return cmd_buffer->record_result;
2752 }
2753
2754 static void
2755 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2756 {
2757 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2758
2759 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2760 return;
2761
2762 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2763
2764 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2765 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2766
2767 cmd_buffer->compute_scratch_size_needed =
2768 MAX2(cmd_buffer->compute_scratch_size_needed,
2769 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2770
2771 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2772 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2773
2774 if (unlikely(cmd_buffer->device->trace_bo))
2775 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2776 }
2777
2778 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2779 VkPipelineBindPoint bind_point)
2780 {
2781 struct radv_descriptor_state *descriptors_state =
2782 radv_get_descriptors_state(cmd_buffer, bind_point);
2783
2784 descriptors_state->dirty |= descriptors_state->valid;
2785 }
2786
2787 void radv_CmdBindPipeline(
2788 VkCommandBuffer commandBuffer,
2789 VkPipelineBindPoint pipelineBindPoint,
2790 VkPipeline _pipeline)
2791 {
2792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2793 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2794
2795 switch (pipelineBindPoint) {
2796 case VK_PIPELINE_BIND_POINT_COMPUTE:
2797 if (cmd_buffer->state.compute_pipeline == pipeline)
2798 return;
2799 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2800
2801 cmd_buffer->state.compute_pipeline = pipeline;
2802 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2803 break;
2804 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2805 if (cmd_buffer->state.pipeline == pipeline)
2806 return;
2807 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2808
2809 cmd_buffer->state.pipeline = pipeline;
2810 if (!pipeline)
2811 break;
2812
2813 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2814 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2815
2816 /* the new vertex shader might not have the same user regs */
2817 cmd_buffer->state.last_first_instance = -1;
2818 cmd_buffer->state.last_vertex_offset = -1;
2819
2820 /* Prefetch all pipeline shaders at first draw time. */
2821 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2822
2823 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2824 radv_bind_streamout_state(cmd_buffer, pipeline);
2825
2826 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2827 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2828 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2829 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2830
2831 if (radv_pipeline_has_tess(pipeline))
2832 cmd_buffer->tess_rings_needed = true;
2833 break;
2834 default:
2835 assert(!"invalid bind point");
2836 break;
2837 }
2838 }
2839
2840 void radv_CmdSetViewport(
2841 VkCommandBuffer commandBuffer,
2842 uint32_t firstViewport,
2843 uint32_t viewportCount,
2844 const VkViewport* pViewports)
2845 {
2846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2847 struct radv_cmd_state *state = &cmd_buffer->state;
2848 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2849
2850 assert(firstViewport < MAX_VIEWPORTS);
2851 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2852
2853 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2854 viewportCount * sizeof(*pViewports));
2855
2856 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2857 }
2858
2859 void radv_CmdSetScissor(
2860 VkCommandBuffer commandBuffer,
2861 uint32_t firstScissor,
2862 uint32_t scissorCount,
2863 const VkRect2D* pScissors)
2864 {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2866 struct radv_cmd_state *state = &cmd_buffer->state;
2867 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2868
2869 assert(firstScissor < MAX_SCISSORS);
2870 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2871
2872 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2873 scissorCount * sizeof(*pScissors));
2874
2875 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2876 }
2877
2878 void radv_CmdSetLineWidth(
2879 VkCommandBuffer commandBuffer,
2880 float lineWidth)
2881 {
2882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2883 cmd_buffer->state.dynamic.line_width = lineWidth;
2884 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2885 }
2886
2887 void radv_CmdSetDepthBias(
2888 VkCommandBuffer commandBuffer,
2889 float depthBiasConstantFactor,
2890 float depthBiasClamp,
2891 float depthBiasSlopeFactor)
2892 {
2893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2894
2895 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2896 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2897 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2898
2899 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2900 }
2901
2902 void radv_CmdSetBlendConstants(
2903 VkCommandBuffer commandBuffer,
2904 const float blendConstants[4])
2905 {
2906 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2907
2908 memcpy(cmd_buffer->state.dynamic.blend_constants,
2909 blendConstants, sizeof(float) * 4);
2910
2911 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2912 }
2913
2914 void radv_CmdSetDepthBounds(
2915 VkCommandBuffer commandBuffer,
2916 float minDepthBounds,
2917 float maxDepthBounds)
2918 {
2919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2920
2921 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2922 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2923
2924 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2925 }
2926
2927 void radv_CmdSetStencilCompareMask(
2928 VkCommandBuffer commandBuffer,
2929 VkStencilFaceFlags faceMask,
2930 uint32_t compareMask)
2931 {
2932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2933
2934 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2935 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2936 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2937 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2938
2939 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2940 }
2941
2942 void radv_CmdSetStencilWriteMask(
2943 VkCommandBuffer commandBuffer,
2944 VkStencilFaceFlags faceMask,
2945 uint32_t writeMask)
2946 {
2947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2948
2949 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2950 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2951 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2952 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2953
2954 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2955 }
2956
2957 void radv_CmdSetStencilReference(
2958 VkCommandBuffer commandBuffer,
2959 VkStencilFaceFlags faceMask,
2960 uint32_t reference)
2961 {
2962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2963
2964 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2965 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2966 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2967 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2968
2969 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2970 }
2971
2972 void radv_CmdSetDiscardRectangleEXT(
2973 VkCommandBuffer commandBuffer,
2974 uint32_t firstDiscardRectangle,
2975 uint32_t discardRectangleCount,
2976 const VkRect2D* pDiscardRectangles)
2977 {
2978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2979 struct radv_cmd_state *state = &cmd_buffer->state;
2980 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2981
2982 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2983 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2984
2985 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2986 pDiscardRectangles, discardRectangleCount);
2987
2988 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2989 }
2990
2991 void radv_CmdExecuteCommands(
2992 VkCommandBuffer commandBuffer,
2993 uint32_t commandBufferCount,
2994 const VkCommandBuffer* pCmdBuffers)
2995 {
2996 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2997
2998 assert(commandBufferCount > 0);
2999
3000 /* Emit pending flushes on primary prior to executing secondary */
3001 si_emit_cache_flush(primary);
3002
3003 for (uint32_t i = 0; i < commandBufferCount; i++) {
3004 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3005
3006 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3007 secondary->scratch_size_needed);
3008 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3009 secondary->compute_scratch_size_needed);
3010
3011 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3012 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3013 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3014 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3015 if (secondary->tess_rings_needed)
3016 primary->tess_rings_needed = true;
3017 if (secondary->sample_positions_needed)
3018 primary->sample_positions_needed = true;
3019
3020 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3021
3022
3023 /* When the secondary command buffer is compute only we don't
3024 * need to re-emit the current graphics pipeline.
3025 */
3026 if (secondary->state.emitted_pipeline) {
3027 primary->state.emitted_pipeline =
3028 secondary->state.emitted_pipeline;
3029 }
3030
3031 /* When the secondary command buffer is graphics only we don't
3032 * need to re-emit the current compute pipeline.
3033 */
3034 if (secondary->state.emitted_compute_pipeline) {
3035 primary->state.emitted_compute_pipeline =
3036 secondary->state.emitted_compute_pipeline;
3037 }
3038
3039 /* Only re-emit the draw packets when needed. */
3040 if (secondary->state.last_primitive_reset_en != -1) {
3041 primary->state.last_primitive_reset_en =
3042 secondary->state.last_primitive_reset_en;
3043 }
3044
3045 if (secondary->state.last_primitive_reset_index) {
3046 primary->state.last_primitive_reset_index =
3047 secondary->state.last_primitive_reset_index;
3048 }
3049
3050 if (secondary->state.last_ia_multi_vgt_param) {
3051 primary->state.last_ia_multi_vgt_param =
3052 secondary->state.last_ia_multi_vgt_param;
3053 }
3054
3055 primary->state.last_first_instance = secondary->state.last_first_instance;
3056 primary->state.last_num_instances = secondary->state.last_num_instances;
3057 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3058
3059 if (secondary->state.last_index_type != -1) {
3060 primary->state.last_index_type =
3061 secondary->state.last_index_type;
3062 }
3063 }
3064
3065 /* After executing commands from secondary buffers we have to dirty
3066 * some states.
3067 */
3068 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3069 RADV_CMD_DIRTY_INDEX_BUFFER |
3070 RADV_CMD_DIRTY_DYNAMIC_ALL;
3071 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3072 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3073 }
3074
3075 VkResult radv_CreateCommandPool(
3076 VkDevice _device,
3077 const VkCommandPoolCreateInfo* pCreateInfo,
3078 const VkAllocationCallbacks* pAllocator,
3079 VkCommandPool* pCmdPool)
3080 {
3081 RADV_FROM_HANDLE(radv_device, device, _device);
3082 struct radv_cmd_pool *pool;
3083
3084 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3085 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3086 if (pool == NULL)
3087 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3088
3089 if (pAllocator)
3090 pool->alloc = *pAllocator;
3091 else
3092 pool->alloc = device->alloc;
3093
3094 list_inithead(&pool->cmd_buffers);
3095 list_inithead(&pool->free_cmd_buffers);
3096
3097 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3098
3099 *pCmdPool = radv_cmd_pool_to_handle(pool);
3100
3101 return VK_SUCCESS;
3102
3103 }
3104
3105 void radv_DestroyCommandPool(
3106 VkDevice _device,
3107 VkCommandPool commandPool,
3108 const VkAllocationCallbacks* pAllocator)
3109 {
3110 RADV_FROM_HANDLE(radv_device, device, _device);
3111 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3112
3113 if (!pool)
3114 return;
3115
3116 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3117 &pool->cmd_buffers, pool_link) {
3118 radv_cmd_buffer_destroy(cmd_buffer);
3119 }
3120
3121 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3122 &pool->free_cmd_buffers, pool_link) {
3123 radv_cmd_buffer_destroy(cmd_buffer);
3124 }
3125
3126 vk_free2(&device->alloc, pAllocator, pool);
3127 }
3128
3129 VkResult radv_ResetCommandPool(
3130 VkDevice device,
3131 VkCommandPool commandPool,
3132 VkCommandPoolResetFlags flags)
3133 {
3134 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3135 VkResult result;
3136
3137 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3138 &pool->cmd_buffers, pool_link) {
3139 result = radv_reset_cmd_buffer(cmd_buffer);
3140 if (result != VK_SUCCESS)
3141 return result;
3142 }
3143
3144 return VK_SUCCESS;
3145 }
3146
3147 void radv_TrimCommandPool(
3148 VkDevice device,
3149 VkCommandPool commandPool,
3150 VkCommandPoolTrimFlagsKHR flags)
3151 {
3152 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3153
3154 if (!pool)
3155 return;
3156
3157 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3158 &pool->free_cmd_buffers, pool_link) {
3159 radv_cmd_buffer_destroy(cmd_buffer);
3160 }
3161 }
3162
3163 void radv_CmdBeginRenderPass(
3164 VkCommandBuffer commandBuffer,
3165 const VkRenderPassBeginInfo* pRenderPassBegin,
3166 VkSubpassContents contents)
3167 {
3168 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3169 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3170 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3171
3172 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3173 cmd_buffer->cs, 2048);
3174 MAYBE_UNUSED VkResult result;
3175
3176 cmd_buffer->state.framebuffer = framebuffer;
3177 cmd_buffer->state.pass = pass;
3178 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3179
3180 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3181 if (result != VK_SUCCESS)
3182 return;
3183
3184 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3185 assert(cmd_buffer->cs->cdw <= cdw_max);
3186
3187 radv_cmd_buffer_clear_subpass(cmd_buffer);
3188 }
3189
3190 void radv_CmdBeginRenderPass2KHR(
3191 VkCommandBuffer commandBuffer,
3192 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3193 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3194 {
3195 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3196 pSubpassBeginInfo->contents);
3197 }
3198
3199 void radv_CmdNextSubpass(
3200 VkCommandBuffer commandBuffer,
3201 VkSubpassContents contents)
3202 {
3203 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3204
3205 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3206
3207 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3208 2048);
3209
3210 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3211 radv_cmd_buffer_clear_subpass(cmd_buffer);
3212 }
3213
3214 void radv_CmdNextSubpass2KHR(
3215 VkCommandBuffer commandBuffer,
3216 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3217 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3218 {
3219 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3220 }
3221
3222 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3223 {
3224 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3225 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3226 if (!radv_get_shader(pipeline, stage))
3227 continue;
3228
3229 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3230 if (loc->sgpr_idx == -1)
3231 continue;
3232 uint32_t base_reg = pipeline->user_data_0[stage];
3233 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3234
3235 }
3236 if (pipeline->gs_copy_shader) {
3237 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3238 if (loc->sgpr_idx != -1) {
3239 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3240 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3241 }
3242 }
3243 }
3244
3245 static void
3246 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3247 uint32_t vertex_count,
3248 bool use_opaque)
3249 {
3250 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3251 radeon_emit(cmd_buffer->cs, vertex_count);
3252 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3253 S_0287F0_USE_OPAQUE(use_opaque));
3254 }
3255
3256 static void
3257 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3258 uint64_t index_va,
3259 uint32_t index_count)
3260 {
3261 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3262 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3263 radeon_emit(cmd_buffer->cs, index_va);
3264 radeon_emit(cmd_buffer->cs, index_va >> 32);
3265 radeon_emit(cmd_buffer->cs, index_count);
3266 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3267 }
3268
3269 static void
3270 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3271 bool indexed,
3272 uint32_t draw_count,
3273 uint64_t count_va,
3274 uint32_t stride)
3275 {
3276 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3277 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3278 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3279 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3280 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3281 bool predicating = cmd_buffer->state.predicating;
3282 assert(base_reg);
3283
3284 /* just reset draw state for vertex data */
3285 cmd_buffer->state.last_first_instance = -1;
3286 cmd_buffer->state.last_num_instances = -1;
3287 cmd_buffer->state.last_vertex_offset = -1;
3288
3289 if (draw_count == 1 && !count_va && !draw_id_enable) {
3290 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3291 PKT3_DRAW_INDIRECT, 3, predicating));
3292 radeon_emit(cs, 0);
3293 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3294 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3295 radeon_emit(cs, di_src_sel);
3296 } else {
3297 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3298 PKT3_DRAW_INDIRECT_MULTI,
3299 8, predicating));
3300 radeon_emit(cs, 0);
3301 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3302 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3303 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3304 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3305 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3306 radeon_emit(cs, draw_count); /* count */
3307 radeon_emit(cs, count_va); /* count_addr */
3308 radeon_emit(cs, count_va >> 32);
3309 radeon_emit(cs, stride); /* stride */
3310 radeon_emit(cs, di_src_sel);
3311 }
3312 }
3313
3314 struct radv_draw_info {
3315 /**
3316 * Number of vertices.
3317 */
3318 uint32_t count;
3319
3320 /**
3321 * Index of the first vertex.
3322 */
3323 int32_t vertex_offset;
3324
3325 /**
3326 * First instance id.
3327 */
3328 uint32_t first_instance;
3329
3330 /**
3331 * Number of instances.
3332 */
3333 uint32_t instance_count;
3334
3335 /**
3336 * First index (indexed draws only).
3337 */
3338 uint32_t first_index;
3339
3340 /**
3341 * Whether it's an indexed draw.
3342 */
3343 bool indexed;
3344
3345 /**
3346 * Indirect draw parameters resource.
3347 */
3348 struct radv_buffer *indirect;
3349 uint64_t indirect_offset;
3350 uint32_t stride;
3351
3352 /**
3353 * Draw count parameters resource.
3354 */
3355 struct radv_buffer *count_buffer;
3356 uint64_t count_buffer_offset;
3357
3358 /**
3359 * Stream output parameters resource.
3360 */
3361 struct radv_buffer *strmout_buffer;
3362 uint64_t strmout_buffer_offset;
3363 };
3364
3365 static void
3366 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3367 const struct radv_draw_info *info)
3368 {
3369 struct radv_cmd_state *state = &cmd_buffer->state;
3370 struct radeon_winsys *ws = cmd_buffer->device->ws;
3371 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3372
3373 if (info->strmout_buffer) {
3374 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3375
3376 va += info->strmout_buffer->offset +
3377 info->strmout_buffer_offset;
3378
3379 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3380 info->stride);
3381
3382 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3383 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3384 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3385 COPY_DATA_WR_CONFIRM);
3386 radeon_emit(cs, va);
3387 radeon_emit(cs, va >> 32);
3388 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3389 radeon_emit(cs, 0); /* unused */
3390
3391 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3392 }
3393
3394 if (info->indirect) {
3395 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3396 uint64_t count_va = 0;
3397
3398 va += info->indirect->offset + info->indirect_offset;
3399
3400 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3401
3402 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3403 radeon_emit(cs, 1);
3404 radeon_emit(cs, va);
3405 radeon_emit(cs, va >> 32);
3406
3407 if (info->count_buffer) {
3408 count_va = radv_buffer_get_va(info->count_buffer->bo);
3409 count_va += info->count_buffer->offset +
3410 info->count_buffer_offset;
3411
3412 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3413 }
3414
3415 if (!state->subpass->view_mask) {
3416 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3417 info->indexed,
3418 info->count,
3419 count_va,
3420 info->stride);
3421 } else {
3422 unsigned i;
3423 for_each_bit(i, state->subpass->view_mask) {
3424 radv_emit_view_index(cmd_buffer, i);
3425
3426 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3427 info->indexed,
3428 info->count,
3429 count_va,
3430 info->stride);
3431 }
3432 }
3433 } else {
3434 assert(state->pipeline->graphics.vtx_base_sgpr);
3435
3436 if (info->vertex_offset != state->last_vertex_offset ||
3437 info->first_instance != state->last_first_instance) {
3438 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3439 state->pipeline->graphics.vtx_emit_num);
3440
3441 radeon_emit(cs, info->vertex_offset);
3442 radeon_emit(cs, info->first_instance);
3443 if (state->pipeline->graphics.vtx_emit_num == 3)
3444 radeon_emit(cs, 0);
3445 state->last_first_instance = info->first_instance;
3446 state->last_vertex_offset = info->vertex_offset;
3447 }
3448
3449 if (state->last_num_instances != info->instance_count) {
3450 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3451 radeon_emit(cs, info->instance_count);
3452 state->last_num_instances = info->instance_count;
3453 }
3454
3455 if (info->indexed) {
3456 int index_size = state->index_type ? 4 : 2;
3457 uint64_t index_va;
3458
3459 index_va = state->index_va;
3460 index_va += info->first_index * index_size;
3461
3462 if (!state->subpass->view_mask) {
3463 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3464 index_va,
3465 info->count);
3466 } else {
3467 unsigned i;
3468 for_each_bit(i, state->subpass->view_mask) {
3469 radv_emit_view_index(cmd_buffer, i);
3470
3471 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3472 index_va,
3473 info->count);
3474 }
3475 }
3476 } else {
3477 if (!state->subpass->view_mask) {
3478 radv_cs_emit_draw_packet(cmd_buffer,
3479 info->count,
3480 !!info->strmout_buffer);
3481 } else {
3482 unsigned i;
3483 for_each_bit(i, state->subpass->view_mask) {
3484 radv_emit_view_index(cmd_buffer, i);
3485
3486 radv_cs_emit_draw_packet(cmd_buffer,
3487 info->count,
3488 !!info->strmout_buffer);
3489 }
3490 }
3491 }
3492 }
3493 }
3494
3495 /*
3496 * Vega and raven have a bug which triggers if there are multiple context
3497 * register contexts active at the same time with different scissor values.
3498 *
3499 * There are two possible workarounds:
3500 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3501 * there is only ever 1 active set of scissor values at the same time.
3502 *
3503 * 2) Whenever the hardware switches contexts we have to set the scissor
3504 * registers again even if it is a noop. That way the new context gets
3505 * the correct scissor values.
3506 *
3507 * This implements option 2. radv_need_late_scissor_emission needs to
3508 * return true on affected HW if radv_emit_all_graphics_states sets
3509 * any context registers.
3510 */
3511 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3512 bool indexed_draw)
3513 {
3514 struct radv_cmd_state *state = &cmd_buffer->state;
3515
3516 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3517 return false;
3518
3519 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3520
3521 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3522 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3523
3524 /* Assume all state changes except these two can imply context rolls. */
3525 if (cmd_buffer->state.dirty & used_states)
3526 return true;
3527
3528 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3529 return true;
3530
3531 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3532 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3533 return true;
3534
3535 return false;
3536 }
3537
3538 static void
3539 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3540 const struct radv_draw_info *info)
3541 {
3542 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3543
3544 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3545 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3546 radv_emit_rbplus_state(cmd_buffer);
3547
3548 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3549 radv_emit_graphics_pipeline(cmd_buffer);
3550
3551 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3552 radv_emit_framebuffer_state(cmd_buffer);
3553
3554 if (info->indexed) {
3555 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3556 radv_emit_index_buffer(cmd_buffer);
3557 } else {
3558 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3559 * so the state must be re-emitted before the next indexed
3560 * draw.
3561 */
3562 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3563 cmd_buffer->state.last_index_type = -1;
3564 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3565 }
3566 }
3567
3568 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3569
3570 radv_emit_draw_registers(cmd_buffer, info->indexed,
3571 info->instance_count > 1, info->indirect,
3572 info->indirect ? 0 : info->count);
3573
3574 if (late_scissor_emission)
3575 radv_emit_scissor(cmd_buffer);
3576 }
3577
3578 static void
3579 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3580 const struct radv_draw_info *info)
3581 {
3582 struct radeon_info *rad_info =
3583 &cmd_buffer->device->physical_device->rad_info;
3584 bool has_prefetch =
3585 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3586 bool pipeline_is_dirty =
3587 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3588 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3589
3590 MAYBE_UNUSED unsigned cdw_max =
3591 radeon_check_space(cmd_buffer->device->ws,
3592 cmd_buffer->cs, 4096);
3593
3594 /* Use optimal packet order based on whether we need to sync the
3595 * pipeline.
3596 */
3597 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3598 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3599 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3600 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3601 /* If we have to wait for idle, set all states first, so that
3602 * all SET packets are processed in parallel with previous draw
3603 * calls. Then upload descriptors, set shader pointers, and
3604 * draw, and prefetch at the end. This ensures that the time
3605 * the CUs are idle is very short. (there are only SET_SH
3606 * packets between the wait and the draw)
3607 */
3608 radv_emit_all_graphics_states(cmd_buffer, info);
3609 si_emit_cache_flush(cmd_buffer);
3610 /* <-- CUs are idle here --> */
3611
3612 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3613
3614 radv_emit_draw_packets(cmd_buffer, info);
3615 /* <-- CUs are busy here --> */
3616
3617 /* Start prefetches after the draw has been started. Both will
3618 * run in parallel, but starting the draw first is more
3619 * important.
3620 */
3621 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3622 radv_emit_prefetch_L2(cmd_buffer,
3623 cmd_buffer->state.pipeline, false);
3624 }
3625 } else {
3626 /* If we don't wait for idle, start prefetches first, then set
3627 * states, and draw at the end.
3628 */
3629 si_emit_cache_flush(cmd_buffer);
3630
3631 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3632 /* Only prefetch the vertex shader and VBO descriptors
3633 * in order to start the draw as soon as possible.
3634 */
3635 radv_emit_prefetch_L2(cmd_buffer,
3636 cmd_buffer->state.pipeline, true);
3637 }
3638
3639 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3640
3641 radv_emit_all_graphics_states(cmd_buffer, info);
3642 radv_emit_draw_packets(cmd_buffer, info);
3643
3644 /* Prefetch the remaining shaders after the draw has been
3645 * started.
3646 */
3647 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3648 radv_emit_prefetch_L2(cmd_buffer,
3649 cmd_buffer->state.pipeline, false);
3650 }
3651 }
3652
3653 /* Workaround for a VGT hang when streamout is enabled.
3654 * It must be done after drawing.
3655 */
3656 if (cmd_buffer->state.streamout.streamout_enabled &&
3657 (rad_info->family == CHIP_HAWAII ||
3658 rad_info->family == CHIP_TONGA ||
3659 rad_info->family == CHIP_FIJI)) {
3660 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3661 }
3662
3663 assert(cmd_buffer->cs->cdw <= cdw_max);
3664 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3665 }
3666
3667 void radv_CmdDraw(
3668 VkCommandBuffer commandBuffer,
3669 uint32_t vertexCount,
3670 uint32_t instanceCount,
3671 uint32_t firstVertex,
3672 uint32_t firstInstance)
3673 {
3674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3675 struct radv_draw_info info = {};
3676
3677 info.count = vertexCount;
3678 info.instance_count = instanceCount;
3679 info.first_instance = firstInstance;
3680 info.vertex_offset = firstVertex;
3681
3682 radv_draw(cmd_buffer, &info);
3683 }
3684
3685 void radv_CmdDrawIndexed(
3686 VkCommandBuffer commandBuffer,
3687 uint32_t indexCount,
3688 uint32_t instanceCount,
3689 uint32_t firstIndex,
3690 int32_t vertexOffset,
3691 uint32_t firstInstance)
3692 {
3693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3694 struct radv_draw_info info = {};
3695
3696 info.indexed = true;
3697 info.count = indexCount;
3698 info.instance_count = instanceCount;
3699 info.first_index = firstIndex;
3700 info.vertex_offset = vertexOffset;
3701 info.first_instance = firstInstance;
3702
3703 radv_draw(cmd_buffer, &info);
3704 }
3705
3706 void radv_CmdDrawIndirect(
3707 VkCommandBuffer commandBuffer,
3708 VkBuffer _buffer,
3709 VkDeviceSize offset,
3710 uint32_t drawCount,
3711 uint32_t stride)
3712 {
3713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3714 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3715 struct radv_draw_info info = {};
3716
3717 info.count = drawCount;
3718 info.indirect = buffer;
3719 info.indirect_offset = offset;
3720 info.stride = stride;
3721
3722 radv_draw(cmd_buffer, &info);
3723 }
3724
3725 void radv_CmdDrawIndexedIndirect(
3726 VkCommandBuffer commandBuffer,
3727 VkBuffer _buffer,
3728 VkDeviceSize offset,
3729 uint32_t drawCount,
3730 uint32_t stride)
3731 {
3732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3733 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3734 struct radv_draw_info info = {};
3735
3736 info.indexed = true;
3737 info.count = drawCount;
3738 info.indirect = buffer;
3739 info.indirect_offset = offset;
3740 info.stride = stride;
3741
3742 radv_draw(cmd_buffer, &info);
3743 }
3744
3745 void radv_CmdDrawIndirectCountAMD(
3746 VkCommandBuffer commandBuffer,
3747 VkBuffer _buffer,
3748 VkDeviceSize offset,
3749 VkBuffer _countBuffer,
3750 VkDeviceSize countBufferOffset,
3751 uint32_t maxDrawCount,
3752 uint32_t stride)
3753 {
3754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3755 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3756 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3757 struct radv_draw_info info = {};
3758
3759 info.count = maxDrawCount;
3760 info.indirect = buffer;
3761 info.indirect_offset = offset;
3762 info.count_buffer = count_buffer;
3763 info.count_buffer_offset = countBufferOffset;
3764 info.stride = stride;
3765
3766 radv_draw(cmd_buffer, &info);
3767 }
3768
3769 void radv_CmdDrawIndexedIndirectCountAMD(
3770 VkCommandBuffer commandBuffer,
3771 VkBuffer _buffer,
3772 VkDeviceSize offset,
3773 VkBuffer _countBuffer,
3774 VkDeviceSize countBufferOffset,
3775 uint32_t maxDrawCount,
3776 uint32_t stride)
3777 {
3778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3779 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3780 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3781 struct radv_draw_info info = {};
3782
3783 info.indexed = true;
3784 info.count = maxDrawCount;
3785 info.indirect = buffer;
3786 info.indirect_offset = offset;
3787 info.count_buffer = count_buffer;
3788 info.count_buffer_offset = countBufferOffset;
3789 info.stride = stride;
3790
3791 radv_draw(cmd_buffer, &info);
3792 }
3793
3794 void radv_CmdDrawIndirectCountKHR(
3795 VkCommandBuffer commandBuffer,
3796 VkBuffer _buffer,
3797 VkDeviceSize offset,
3798 VkBuffer _countBuffer,
3799 VkDeviceSize countBufferOffset,
3800 uint32_t maxDrawCount,
3801 uint32_t stride)
3802 {
3803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3804 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3805 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3806 struct radv_draw_info info = {};
3807
3808 info.count = maxDrawCount;
3809 info.indirect = buffer;
3810 info.indirect_offset = offset;
3811 info.count_buffer = count_buffer;
3812 info.count_buffer_offset = countBufferOffset;
3813 info.stride = stride;
3814
3815 radv_draw(cmd_buffer, &info);
3816 }
3817
3818 void radv_CmdDrawIndexedIndirectCountKHR(
3819 VkCommandBuffer commandBuffer,
3820 VkBuffer _buffer,
3821 VkDeviceSize offset,
3822 VkBuffer _countBuffer,
3823 VkDeviceSize countBufferOffset,
3824 uint32_t maxDrawCount,
3825 uint32_t stride)
3826 {
3827 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3828 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3829 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3830 struct radv_draw_info info = {};
3831
3832 info.indexed = true;
3833 info.count = maxDrawCount;
3834 info.indirect = buffer;
3835 info.indirect_offset = offset;
3836 info.count_buffer = count_buffer;
3837 info.count_buffer_offset = countBufferOffset;
3838 info.stride = stride;
3839
3840 radv_draw(cmd_buffer, &info);
3841 }
3842
3843 struct radv_dispatch_info {
3844 /**
3845 * Determine the layout of the grid (in block units) to be used.
3846 */
3847 uint32_t blocks[3];
3848
3849 /**
3850 * A starting offset for the grid. If unaligned is set, the offset
3851 * must still be aligned.
3852 */
3853 uint32_t offsets[3];
3854 /**
3855 * Whether it's an unaligned compute dispatch.
3856 */
3857 bool unaligned;
3858
3859 /**
3860 * Indirect compute parameters resource.
3861 */
3862 struct radv_buffer *indirect;
3863 uint64_t indirect_offset;
3864 };
3865
3866 static void
3867 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3868 const struct radv_dispatch_info *info)
3869 {
3870 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3871 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3872 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3873 struct radeon_winsys *ws = cmd_buffer->device->ws;
3874 bool predicating = cmd_buffer->state.predicating;
3875 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3876 struct radv_userdata_info *loc;
3877
3878 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3879 AC_UD_CS_GRID_SIZE);
3880
3881 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3882
3883 if (info->indirect) {
3884 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3885
3886 va += info->indirect->offset + info->indirect_offset;
3887
3888 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3889
3890 if (loc->sgpr_idx != -1) {
3891 for (unsigned i = 0; i < 3; ++i) {
3892 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3893 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3894 COPY_DATA_DST_SEL(COPY_DATA_REG));
3895 radeon_emit(cs, (va + 4 * i));
3896 radeon_emit(cs, (va + 4 * i) >> 32);
3897 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3898 + loc->sgpr_idx * 4) >> 2) + i);
3899 radeon_emit(cs, 0);
3900 }
3901 }
3902
3903 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3904 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3905 PKT3_SHADER_TYPE_S(1));
3906 radeon_emit(cs, va);
3907 radeon_emit(cs, va >> 32);
3908 radeon_emit(cs, dispatch_initiator);
3909 } else {
3910 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3911 PKT3_SHADER_TYPE_S(1));
3912 radeon_emit(cs, 1);
3913 radeon_emit(cs, va);
3914 radeon_emit(cs, va >> 32);
3915
3916 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3917 PKT3_SHADER_TYPE_S(1));
3918 radeon_emit(cs, 0);
3919 radeon_emit(cs, dispatch_initiator);
3920 }
3921 } else {
3922 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3923 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3924
3925 if (info->unaligned) {
3926 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3927 unsigned remainder[3];
3928
3929 /* If aligned, these should be an entire block size,
3930 * not 0.
3931 */
3932 remainder[0] = blocks[0] + cs_block_size[0] -
3933 align_u32_npot(blocks[0], cs_block_size[0]);
3934 remainder[1] = blocks[1] + cs_block_size[1] -
3935 align_u32_npot(blocks[1], cs_block_size[1]);
3936 remainder[2] = blocks[2] + cs_block_size[2] -
3937 align_u32_npot(blocks[2], cs_block_size[2]);
3938
3939 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3940 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3941 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3942
3943 for(unsigned i = 0; i < 3; ++i) {
3944 assert(offsets[i] % cs_block_size[i] == 0);
3945 offsets[i] /= cs_block_size[i];
3946 }
3947
3948 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3949 radeon_emit(cs,
3950 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3951 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3952 radeon_emit(cs,
3953 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3954 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3955 radeon_emit(cs,
3956 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3957 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3958
3959 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3960 }
3961
3962 if (loc->sgpr_idx != -1) {
3963 assert(!loc->indirect);
3964 assert(loc->num_sgprs == 3);
3965
3966 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3967 loc->sgpr_idx * 4, 3);
3968 radeon_emit(cs, blocks[0]);
3969 radeon_emit(cs, blocks[1]);
3970 radeon_emit(cs, blocks[2]);
3971 }
3972
3973 if (offsets[0] || offsets[1] || offsets[2]) {
3974 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3975 radeon_emit(cs, offsets[0]);
3976 radeon_emit(cs, offsets[1]);
3977 radeon_emit(cs, offsets[2]);
3978
3979 /* The blocks in the packet are not counts but end values. */
3980 for (unsigned i = 0; i < 3; ++i)
3981 blocks[i] += offsets[i];
3982 } else {
3983 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3984 }
3985
3986 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3987 PKT3_SHADER_TYPE_S(1));
3988 radeon_emit(cs, blocks[0]);
3989 radeon_emit(cs, blocks[1]);
3990 radeon_emit(cs, blocks[2]);
3991 radeon_emit(cs, dispatch_initiator);
3992 }
3993
3994 assert(cmd_buffer->cs->cdw <= cdw_max);
3995 }
3996
3997 static void
3998 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3999 {
4000 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4001 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4002 }
4003
4004 static void
4005 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4006 const struct radv_dispatch_info *info)
4007 {
4008 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4009 bool has_prefetch =
4010 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4011 bool pipeline_is_dirty = pipeline &&
4012 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4013
4014 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4015 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4016 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4017 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4018 /* If we have to wait for idle, set all states first, so that
4019 * all SET packets are processed in parallel with previous draw
4020 * calls. Then upload descriptors, set shader pointers, and
4021 * dispatch, and prefetch at the end. This ensures that the
4022 * time the CUs are idle is very short. (there are only SET_SH
4023 * packets between the wait and the draw)
4024 */
4025 radv_emit_compute_pipeline(cmd_buffer);
4026 si_emit_cache_flush(cmd_buffer);
4027 /* <-- CUs are idle here --> */
4028
4029 radv_upload_compute_shader_descriptors(cmd_buffer);
4030
4031 radv_emit_dispatch_packets(cmd_buffer, info);
4032 /* <-- CUs are busy here --> */
4033
4034 /* Start prefetches after the dispatch has been started. Both
4035 * will run in parallel, but starting the dispatch first is
4036 * more important.
4037 */
4038 if (has_prefetch && pipeline_is_dirty) {
4039 radv_emit_shader_prefetch(cmd_buffer,
4040 pipeline->shaders[MESA_SHADER_COMPUTE]);
4041 }
4042 } else {
4043 /* If we don't wait for idle, start prefetches first, then set
4044 * states, and dispatch at the end.
4045 */
4046 si_emit_cache_flush(cmd_buffer);
4047
4048 if (has_prefetch && pipeline_is_dirty) {
4049 radv_emit_shader_prefetch(cmd_buffer,
4050 pipeline->shaders[MESA_SHADER_COMPUTE]);
4051 }
4052
4053 radv_upload_compute_shader_descriptors(cmd_buffer);
4054
4055 radv_emit_compute_pipeline(cmd_buffer);
4056 radv_emit_dispatch_packets(cmd_buffer, info);
4057 }
4058
4059 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4060 }
4061
4062 void radv_CmdDispatchBase(
4063 VkCommandBuffer commandBuffer,
4064 uint32_t base_x,
4065 uint32_t base_y,
4066 uint32_t base_z,
4067 uint32_t x,
4068 uint32_t y,
4069 uint32_t z)
4070 {
4071 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4072 struct radv_dispatch_info info = {};
4073
4074 info.blocks[0] = x;
4075 info.blocks[1] = y;
4076 info.blocks[2] = z;
4077
4078 info.offsets[0] = base_x;
4079 info.offsets[1] = base_y;
4080 info.offsets[2] = base_z;
4081 radv_dispatch(cmd_buffer, &info);
4082 }
4083
4084 void radv_CmdDispatch(
4085 VkCommandBuffer commandBuffer,
4086 uint32_t x,
4087 uint32_t y,
4088 uint32_t z)
4089 {
4090 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4091 }
4092
4093 void radv_CmdDispatchIndirect(
4094 VkCommandBuffer commandBuffer,
4095 VkBuffer _buffer,
4096 VkDeviceSize offset)
4097 {
4098 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4099 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4100 struct radv_dispatch_info info = {};
4101
4102 info.indirect = buffer;
4103 info.indirect_offset = offset;
4104
4105 radv_dispatch(cmd_buffer, &info);
4106 }
4107
4108 void radv_unaligned_dispatch(
4109 struct radv_cmd_buffer *cmd_buffer,
4110 uint32_t x,
4111 uint32_t y,
4112 uint32_t z)
4113 {
4114 struct radv_dispatch_info info = {};
4115
4116 info.blocks[0] = x;
4117 info.blocks[1] = y;
4118 info.blocks[2] = z;
4119 info.unaligned = 1;
4120
4121 radv_dispatch(cmd_buffer, &info);
4122 }
4123
4124 void radv_CmdEndRenderPass(
4125 VkCommandBuffer commandBuffer)
4126 {
4127 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4128
4129 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4130
4131 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4132
4133 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4134 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4135 radv_handle_subpass_image_transition(cmd_buffer,
4136 (struct radv_subpass_attachment){i, layout});
4137 }
4138
4139 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4140
4141 cmd_buffer->state.pass = NULL;
4142 cmd_buffer->state.subpass = NULL;
4143 cmd_buffer->state.attachments = NULL;
4144 cmd_buffer->state.framebuffer = NULL;
4145 }
4146
4147 void radv_CmdEndRenderPass2KHR(
4148 VkCommandBuffer commandBuffer,
4149 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4150 {
4151 radv_CmdEndRenderPass(commandBuffer);
4152 }
4153
4154 /*
4155 * For HTILE we have the following interesting clear words:
4156 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4157 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4158 * 0xfffffff0: Clear depth to 1.0
4159 * 0x00000000: Clear depth to 0.0
4160 */
4161 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4162 struct radv_image *image,
4163 const VkImageSubresourceRange *range,
4164 uint32_t clear_word)
4165 {
4166 assert(range->baseMipLevel == 0);
4167 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4168 unsigned layer_count = radv_get_layerCount(image, range);
4169 uint64_t size = image->surface.htile_slice_size * layer_count;
4170 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4171 uint64_t offset = image->offset + image->htile_offset +
4172 image->surface.htile_slice_size * range->baseArrayLayer;
4173 struct radv_cmd_state *state = &cmd_buffer->state;
4174 VkClearDepthStencilValue value = {};
4175
4176 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4177 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4178
4179 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4180 size, clear_word);
4181
4182 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4183
4184 if (vk_format_is_stencil(image->vk_format))
4185 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4186
4187 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4188 }
4189
4190 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4191 struct radv_image *image,
4192 VkImageLayout src_layout,
4193 VkImageLayout dst_layout,
4194 unsigned src_queue_mask,
4195 unsigned dst_queue_mask,
4196 const VkImageSubresourceRange *range,
4197 VkImageAspectFlags pending_clears)
4198 {
4199 if (!radv_image_has_htile(image))
4200 return;
4201
4202 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4203 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4204 /* TODO: merge with the clear if applicable */
4205 radv_initialize_htile(cmd_buffer, image, range, 0);
4206 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4207 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4208 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4209 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4210 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4211 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4212 VkImageSubresourceRange local_range = *range;
4213 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4214 local_range.baseMipLevel = 0;
4215 local_range.levelCount = 1;
4216
4217 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4218 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4219
4220 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4221
4222 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4223 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4224 }
4225 }
4226
4227 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4228 struct radv_image *image, uint32_t value)
4229 {
4230 struct radv_cmd_state *state = &cmd_buffer->state;
4231
4232 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4233 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4234
4235 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4236
4237 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4238 }
4239
4240 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4241 struct radv_image *image, uint32_t value)
4242 {
4243 struct radv_cmd_state *state = &cmd_buffer->state;
4244
4245 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4246 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4247
4248 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4249
4250 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4251 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4252 }
4253
4254 /**
4255 * Initialize DCC/FMASK/CMASK metadata for a color image.
4256 */
4257 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4258 struct radv_image *image,
4259 VkImageLayout src_layout,
4260 VkImageLayout dst_layout,
4261 unsigned src_queue_mask,
4262 unsigned dst_queue_mask)
4263 {
4264 if (radv_image_has_cmask(image)) {
4265 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4266
4267 /* TODO: clarify this. */
4268 if (radv_image_has_fmask(image)) {
4269 value = 0xccccccccu;
4270 }
4271
4272 radv_initialise_cmask(cmd_buffer, image, value);
4273 }
4274
4275 if (radv_image_has_dcc(image)) {
4276 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4277 bool need_decompress_pass = false;
4278
4279 if (radv_layout_dcc_compressed(image, dst_layout,
4280 dst_queue_mask)) {
4281 value = 0x20202020u;
4282 need_decompress_pass = true;
4283 }
4284
4285 radv_initialize_dcc(cmd_buffer, image, value);
4286
4287 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4288 need_decompress_pass);
4289 }
4290
4291 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4292 uint32_t color_values[2] = {};
4293 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4294 }
4295 }
4296
4297 /**
4298 * Handle color image transitions for DCC/FMASK/CMASK.
4299 */
4300 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4301 struct radv_image *image,
4302 VkImageLayout src_layout,
4303 VkImageLayout dst_layout,
4304 unsigned src_queue_mask,
4305 unsigned dst_queue_mask,
4306 const VkImageSubresourceRange *range)
4307 {
4308 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4309 radv_init_color_image_metadata(cmd_buffer, image,
4310 src_layout, dst_layout,
4311 src_queue_mask, dst_queue_mask);
4312 return;
4313 }
4314
4315 if (radv_image_has_dcc(image)) {
4316 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4317 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4318 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4319 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4320 radv_decompress_dcc(cmd_buffer, image, range);
4321 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4322 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4323 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4324 }
4325 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4326 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4327 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4328 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4329 }
4330 }
4331 }
4332
4333 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4334 struct radv_image *image,
4335 VkImageLayout src_layout,
4336 VkImageLayout dst_layout,
4337 uint32_t src_family,
4338 uint32_t dst_family,
4339 const VkImageSubresourceRange *range,
4340 VkImageAspectFlags pending_clears)
4341 {
4342 if (image->exclusive && src_family != dst_family) {
4343 /* This is an acquire or a release operation and there will be
4344 * a corresponding release/acquire. Do the transition in the
4345 * most flexible queue. */
4346
4347 assert(src_family == cmd_buffer->queue_family_index ||
4348 dst_family == cmd_buffer->queue_family_index);
4349
4350 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4351 return;
4352
4353 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4354 (src_family == RADV_QUEUE_GENERAL ||
4355 dst_family == RADV_QUEUE_GENERAL))
4356 return;
4357 }
4358
4359 unsigned src_queue_mask =
4360 radv_image_queue_family_mask(image, src_family,
4361 cmd_buffer->queue_family_index);
4362 unsigned dst_queue_mask =
4363 radv_image_queue_family_mask(image, dst_family,
4364 cmd_buffer->queue_family_index);
4365
4366 if (vk_format_is_depth(image->vk_format)) {
4367 radv_handle_depth_image_transition(cmd_buffer, image,
4368 src_layout, dst_layout,
4369 src_queue_mask, dst_queue_mask,
4370 range, pending_clears);
4371 } else {
4372 radv_handle_color_image_transition(cmd_buffer, image,
4373 src_layout, dst_layout,
4374 src_queue_mask, dst_queue_mask,
4375 range);
4376 }
4377 }
4378
4379 struct radv_barrier_info {
4380 uint32_t eventCount;
4381 const VkEvent *pEvents;
4382 VkPipelineStageFlags srcStageMask;
4383 };
4384
4385 static void
4386 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4387 uint32_t memoryBarrierCount,
4388 const VkMemoryBarrier *pMemoryBarriers,
4389 uint32_t bufferMemoryBarrierCount,
4390 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4391 uint32_t imageMemoryBarrierCount,
4392 const VkImageMemoryBarrier *pImageMemoryBarriers,
4393 const struct radv_barrier_info *info)
4394 {
4395 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4396 enum radv_cmd_flush_bits src_flush_bits = 0;
4397 enum radv_cmd_flush_bits dst_flush_bits = 0;
4398
4399 for (unsigned i = 0; i < info->eventCount; ++i) {
4400 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4401 uint64_t va = radv_buffer_get_va(event->bo);
4402
4403 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4404
4405 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4406
4407 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4408 assert(cmd_buffer->cs->cdw <= cdw_max);
4409 }
4410
4411 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4412 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4413 NULL);
4414 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4415 NULL);
4416 }
4417
4418 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4419 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4420 NULL);
4421 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4422 NULL);
4423 }
4424
4425 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4426 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4427
4428 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4429 image);
4430 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4431 image);
4432 }
4433
4434 radv_stage_flush(cmd_buffer, info->srcStageMask);
4435 cmd_buffer->state.flush_bits |= src_flush_bits;
4436
4437 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4438 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4439 radv_handle_image_transition(cmd_buffer, image,
4440 pImageMemoryBarriers[i].oldLayout,
4441 pImageMemoryBarriers[i].newLayout,
4442 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4443 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4444 &pImageMemoryBarriers[i].subresourceRange,
4445 0);
4446 }
4447
4448 /* Make sure CP DMA is idle because the driver might have performed a
4449 * DMA operation for copying or filling buffers/images.
4450 */
4451 si_cp_dma_wait_for_idle(cmd_buffer);
4452
4453 cmd_buffer->state.flush_bits |= dst_flush_bits;
4454 }
4455
4456 void radv_CmdPipelineBarrier(
4457 VkCommandBuffer commandBuffer,
4458 VkPipelineStageFlags srcStageMask,
4459 VkPipelineStageFlags destStageMask,
4460 VkBool32 byRegion,
4461 uint32_t memoryBarrierCount,
4462 const VkMemoryBarrier* pMemoryBarriers,
4463 uint32_t bufferMemoryBarrierCount,
4464 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4465 uint32_t imageMemoryBarrierCount,
4466 const VkImageMemoryBarrier* pImageMemoryBarriers)
4467 {
4468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4469 struct radv_barrier_info info;
4470
4471 info.eventCount = 0;
4472 info.pEvents = NULL;
4473 info.srcStageMask = srcStageMask;
4474
4475 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4476 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4477 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4478 }
4479
4480
4481 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4482 struct radv_event *event,
4483 VkPipelineStageFlags stageMask,
4484 unsigned value)
4485 {
4486 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4487 uint64_t va = radv_buffer_get_va(event->bo);
4488
4489 si_emit_cache_flush(cmd_buffer);
4490
4491 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4492
4493 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4494
4495 /* Flags that only require a top-of-pipe event. */
4496 VkPipelineStageFlags top_of_pipe_flags =
4497 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4498
4499 /* Flags that only require a post-index-fetch event. */
4500 VkPipelineStageFlags post_index_fetch_flags =
4501 top_of_pipe_flags |
4502 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4503 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4504
4505 /* Make sure CP DMA is idle because the driver might have performed a
4506 * DMA operation for copying or filling buffers/images.
4507 */
4508 si_cp_dma_wait_for_idle(cmd_buffer);
4509
4510 /* TODO: Emit EOS events for syncing PS/CS stages. */
4511
4512 if (!(stageMask & ~top_of_pipe_flags)) {
4513 /* Just need to sync the PFP engine. */
4514 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4515 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4516 S_370_WR_CONFIRM(1) |
4517 S_370_ENGINE_SEL(V_370_PFP));
4518 radeon_emit(cs, va);
4519 radeon_emit(cs, va >> 32);
4520 radeon_emit(cs, value);
4521 } else if (!(stageMask & ~post_index_fetch_flags)) {
4522 /* Sync ME because PFP reads index and indirect buffers. */
4523 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4524 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4525 S_370_WR_CONFIRM(1) |
4526 S_370_ENGINE_SEL(V_370_ME));
4527 radeon_emit(cs, va);
4528 radeon_emit(cs, va >> 32);
4529 radeon_emit(cs, value);
4530 } else {
4531 /* Otherwise, sync all prior GPU work using an EOP event. */
4532 si_cs_emit_write_event_eop(cs,
4533 cmd_buffer->device->physical_device->rad_info.chip_class,
4534 radv_cmd_buffer_uses_mec(cmd_buffer),
4535 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4536 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4537 cmd_buffer->gfx9_eop_bug_va);
4538 }
4539
4540 assert(cmd_buffer->cs->cdw <= cdw_max);
4541 }
4542
4543 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4544 VkEvent _event,
4545 VkPipelineStageFlags stageMask)
4546 {
4547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4548 RADV_FROM_HANDLE(radv_event, event, _event);
4549
4550 write_event(cmd_buffer, event, stageMask, 1);
4551 }
4552
4553 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4554 VkEvent _event,
4555 VkPipelineStageFlags stageMask)
4556 {
4557 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4558 RADV_FROM_HANDLE(radv_event, event, _event);
4559
4560 write_event(cmd_buffer, event, stageMask, 0);
4561 }
4562
4563 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4564 uint32_t eventCount,
4565 const VkEvent* pEvents,
4566 VkPipelineStageFlags srcStageMask,
4567 VkPipelineStageFlags dstStageMask,
4568 uint32_t memoryBarrierCount,
4569 const VkMemoryBarrier* pMemoryBarriers,
4570 uint32_t bufferMemoryBarrierCount,
4571 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4572 uint32_t imageMemoryBarrierCount,
4573 const VkImageMemoryBarrier* pImageMemoryBarriers)
4574 {
4575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4576 struct radv_barrier_info info;
4577
4578 info.eventCount = eventCount;
4579 info.pEvents = pEvents;
4580 info.srcStageMask = 0;
4581
4582 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4583 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4584 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4585 }
4586
4587
4588 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4589 uint32_t deviceMask)
4590 {
4591 /* No-op */
4592 }
4593
4594 /* VK_EXT_conditional_rendering */
4595 void radv_CmdBeginConditionalRenderingEXT(
4596 VkCommandBuffer commandBuffer,
4597 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4598 {
4599 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4600 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4601 bool draw_visible = true;
4602 uint64_t va;
4603
4604 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4605
4606 /* By default, if the 32-bit value at offset in buffer memory is zero,
4607 * then the rendering commands are discarded, otherwise they are
4608 * executed as normal. If the inverted flag is set, all commands are
4609 * discarded if the value is non zero.
4610 */
4611 if (pConditionalRenderingBegin->flags &
4612 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4613 draw_visible = false;
4614 }
4615
4616 /* Enable predication for this command buffer. */
4617 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4618 cmd_buffer->state.predicating = true;
4619
4620 /* Store conditional rendering user info. */
4621 cmd_buffer->state.predication_type = draw_visible;
4622 cmd_buffer->state.predication_va = va;
4623 }
4624
4625 void radv_CmdEndConditionalRenderingEXT(
4626 VkCommandBuffer commandBuffer)
4627 {
4628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4629
4630 /* Disable predication for this command buffer. */
4631 si_emit_set_predication_state(cmd_buffer, false, 0);
4632 cmd_buffer->state.predicating = false;
4633
4634 /* Reset conditional rendering user info. */
4635 cmd_buffer->state.predication_type = -1;
4636 cmd_buffer->state.predication_va = 0;
4637 }
4638
4639 /* VK_EXT_transform_feedback */
4640 void radv_CmdBindTransformFeedbackBuffersEXT(
4641 VkCommandBuffer commandBuffer,
4642 uint32_t firstBinding,
4643 uint32_t bindingCount,
4644 const VkBuffer* pBuffers,
4645 const VkDeviceSize* pOffsets,
4646 const VkDeviceSize* pSizes)
4647 {
4648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4649 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4650 uint8_t enabled_mask = 0;
4651
4652 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4653 for (uint32_t i = 0; i < bindingCount; i++) {
4654 uint32_t idx = firstBinding + i;
4655
4656 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4657 sb[idx].offset = pOffsets[i];
4658 sb[idx].size = pSizes[i];
4659
4660 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4661 sb[idx].buffer->bo);
4662
4663 enabled_mask |= 1 << idx;
4664 }
4665
4666 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4667
4668 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4669 }
4670
4671 static void
4672 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4673 {
4674 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4675 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4676
4677 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4678 radeon_emit(cs,
4679 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4680 S_028B94_RAST_STREAM(0) |
4681 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4682 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4683 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4684 radeon_emit(cs, so->hw_enabled_mask &
4685 so->enabled_stream_buffers_mask);
4686 }
4687
4688 static void
4689 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4690 {
4691 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4692 bool old_streamout_enabled = so->streamout_enabled;
4693 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4694
4695 so->streamout_enabled = enable;
4696
4697 so->hw_enabled_mask = so->enabled_mask |
4698 (so->enabled_mask << 4) |
4699 (so->enabled_mask << 8) |
4700 (so->enabled_mask << 12);
4701
4702 if ((old_streamout_enabled != so->streamout_enabled) ||
4703 (old_hw_enabled_mask != so->hw_enabled_mask))
4704 radv_emit_streamout_enable(cmd_buffer);
4705 }
4706
4707 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4708 {
4709 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4710 unsigned reg_strmout_cntl;
4711
4712 /* The register is at different places on different ASICs. */
4713 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4714 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4715 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4716 } else {
4717 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4718 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4719 }
4720
4721 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4722 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4723
4724 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4725 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4726 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4727 radeon_emit(cs, 0);
4728 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4729 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4730 radeon_emit(cs, 4); /* poll interval */
4731 }
4732
4733 void radv_CmdBeginTransformFeedbackEXT(
4734 VkCommandBuffer commandBuffer,
4735 uint32_t firstCounterBuffer,
4736 uint32_t counterBufferCount,
4737 const VkBuffer* pCounterBuffers,
4738 const VkDeviceSize* pCounterBufferOffsets)
4739 {
4740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4741 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4742 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4743 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4744
4745 radv_flush_vgt_streamout(cmd_buffer);
4746
4747 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4748 for (uint32_t i = firstCounterBuffer; i < counterBufferCount; i++) {
4749 if (!(so->enabled_mask & (1 << i)))
4750 continue;
4751
4752 /* SI binds streamout buffers as shader resources.
4753 * VGT only counts primitives and tells the shader through
4754 * SGPRs what to do.
4755 */
4756 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4757 radeon_emit(cs, (sb[i].offset + sb[i].size) >> 2); /* BUFFER_SIZE (in DW) */
4758 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4759
4760 if (pCounterBuffers && pCounterBuffers[i]) {
4761 /* The array of counter buffers is optional. */
4762 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[i]);
4763 uint64_t va = radv_buffer_get_va(buffer->bo);
4764
4765 va += buffer->offset + pCounterBufferOffsets[i];
4766
4767 /* Append */
4768 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4769 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4770 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4771 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4772 radeon_emit(cs, 0); /* unused */
4773 radeon_emit(cs, 0); /* unused */
4774 radeon_emit(cs, va); /* src address lo */
4775 radeon_emit(cs, va >> 32); /* src address hi */
4776
4777 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4778 } else {
4779 /* Start from the beginning. */
4780 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4781 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4782 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4783 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4784 radeon_emit(cs, 0); /* unused */
4785 radeon_emit(cs, 0); /* unused */
4786 radeon_emit(cs, sb[i].offset >> 2); /* buffer offset in DW */
4787 radeon_emit(cs, 0); /* unused */
4788 }
4789 }
4790
4791 radv_set_streamout_enable(cmd_buffer, true);
4792 }
4793
4794 void radv_CmdEndTransformFeedbackEXT(
4795 VkCommandBuffer commandBuffer,
4796 uint32_t firstCounterBuffer,
4797 uint32_t counterBufferCount,
4798 const VkBuffer* pCounterBuffers,
4799 const VkDeviceSize* pCounterBufferOffsets)
4800 {
4801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4802 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4803 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4804
4805 radv_flush_vgt_streamout(cmd_buffer);
4806
4807 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4808 for (uint32_t i = firstCounterBuffer; i < counterBufferCount; i++) {
4809 if (!(so->enabled_mask & (1 << i)))
4810 continue;
4811
4812 if (pCounterBuffers && pCounterBuffers[i]) {
4813 /* The array of counters buffer is optional. */
4814 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[i]);
4815 uint64_t va = radv_buffer_get_va(buffer->bo);
4816
4817 va += buffer->offset + pCounterBufferOffsets[i];
4818
4819 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4820 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4821 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4822 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4823 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4824 radeon_emit(cs, va); /* dst address lo */
4825 radeon_emit(cs, va >> 32); /* dst address hi */
4826 radeon_emit(cs, 0); /* unused */
4827 radeon_emit(cs, 0); /* unused */
4828
4829 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4830 }
4831
4832 /* Deactivate transform feedback by zeroing the buffer size.
4833 * The counters (primitives generated, primitives emitted) may
4834 * be enabled even if there is not buffer bound. This ensures
4835 * that the primitives-emitted query won't increment.
4836 */
4837 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4838 }
4839
4840 radv_set_streamout_enable(cmd_buffer, false);
4841 }
4842
4843 void radv_CmdDrawIndirectByteCountEXT(
4844 VkCommandBuffer commandBuffer,
4845 uint32_t instanceCount,
4846 uint32_t firstInstance,
4847 VkBuffer _counterBuffer,
4848 VkDeviceSize counterBufferOffset,
4849 uint32_t counterOffset,
4850 uint32_t vertexStride)
4851 {
4852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4853 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4854 struct radv_draw_info info = {};
4855
4856 info.instance_count = instanceCount;
4857 info.first_instance = firstInstance;
4858 info.strmout_buffer = counterBuffer;
4859 info.strmout_buffer_offset = counterBufferOffset;
4860 info.stride = vertexStride;
4861
4862 radv_draw(cmd_buffer, &info);
4863 }