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c4e8324a33863fe390d27043b867352a601ce7ed
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 int src_family,
42 int dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_COMPUTE:
342 return R_00B900_COMPUTE_USER_DATA_0;
343 default:
344 unreachable("unknown shader");
345 }
346 }
347
348 static struct ac_userdata_info *
349 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
350 gl_shader_stage stage,
351 int idx)
352 {
353 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
354 }
355
356 static void
357 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
358 struct radv_pipeline *pipeline,
359 gl_shader_stage stage,
360 int idx, uint64_t va)
361 {
362 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
363 uint32_t base_reg = shader_stage_to_user_data_0(stage);
364 if (loc->sgpr_idx == -1)
365 return;
366 assert(loc->num_sgprs == 2);
367 assert(!loc->indirect);
368 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
369 radeon_emit(cmd_buffer->cs, va);
370 radeon_emit(cmd_buffer->cs, va >> 32);
371 }
372
373 static void
374 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
375 struct radv_pipeline *pipeline)
376 {
377 int num_samples = pipeline->graphics.ms.num_samples;
378 struct radv_multisample_state *ms = &pipeline->graphics.ms;
379 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
380
381 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
382 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
383 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
384
385 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
386 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
387
388 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
389 return;
390
391 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
392 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
393 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
394
395 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
396
397 uint32_t samples_offset;
398 void *samples_ptr;
399 void *src;
400 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
401 &samples_ptr);
402 switch (num_samples) {
403 case 1:
404 src = cmd_buffer->device->sample_locations_1x;
405 break;
406 case 2:
407 src = cmd_buffer->device->sample_locations_2x;
408 break;
409 case 4:
410 src = cmd_buffer->device->sample_locations_4x;
411 break;
412 case 8:
413 src = cmd_buffer->device->sample_locations_8x;
414 break;
415 case 16:
416 src = cmd_buffer->device->sample_locations_16x;
417 break;
418 }
419 memcpy(samples_ptr, src, num_samples * 4 * 2);
420
421 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
422 va += samples_offset;
423
424 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
425 AC_UD_PS_SAMPLE_POS, va);
426 }
427
428 static void
429 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
430 struct radv_pipeline *pipeline)
431 {
432 struct radv_raster_state *raster = &pipeline->graphics.raster;
433
434 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
435 raster->pa_cl_clip_cntl);
436
437 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
438 raster->spi_interp_control);
439
440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
441 unsigned tmp = (unsigned)(1.0 * 8.0);
442 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
443 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
444 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
445
446 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
447 raster->pa_su_vtx_cntl);
448
449 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
450 raster->pa_su_sc_mode_cntl);
451 }
452
453 static void
454 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
455 struct radv_pipeline *pipeline)
456 {
457 struct radeon_winsys *ws = cmd_buffer->device->ws;
458 struct radv_shader_variant *vs;
459 uint64_t va;
460 unsigned export_count;
461 unsigned clip_dist_mask, cull_dist_mask, total_mask;
462
463 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
464
465 vs = pipeline->shaders[MESA_SHADER_VERTEX];
466 va = ws->buffer_get_va(vs->bo);
467 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
468
469 clip_dist_mask = vs->info.vs.clip_dist_mask;
470 cull_dist_mask = vs->info.vs.cull_dist_mask;
471 total_mask = clip_dist_mask | cull_dist_mask;
472 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
473 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
474
475 export_count = MAX2(1, vs->info.vs.param_exports);
476 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
477 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
478 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
479 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
480 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
481 V_02870C_SPI_SHADER_4COMP :
482 V_02870C_SPI_SHADER_NONE) |
483 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
484 V_02870C_SPI_SHADER_4COMP :
485 V_02870C_SPI_SHADER_NONE) |
486 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
487 V_02870C_SPI_SHADER_4COMP :
488 V_02870C_SPI_SHADER_NONE));
489
490 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
491 radeon_emit(cmd_buffer->cs, va >> 8);
492 radeon_emit(cmd_buffer->cs, va >> 40);
493 radeon_emit(cmd_buffer->cs, vs->rsrc1);
494 radeon_emit(cmd_buffer->cs, vs->rsrc2);
495
496 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
497 S_028818_VTX_W0_FMT(1) |
498 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
499 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
500 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
501
502 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
504 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->info.vs.writes_layer) |
505 S_02881C_USE_VTX_VIEWPORT_INDX(vs->info.vs.writes_viewport_index) |
506 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize ||
507 vs->info.vs.writes_layer ||
508 vs->info.vs.writes_viewport_index) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
511 pipeline->graphics.raster.pa_cl_vs_out_cntl |
512 cull_dist_mask << 8 |
513 clip_dist_mask);
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
516 S_028AB4_REUSE_OFF(vs->info.vs.writes_viewport_index));
517 }
518
519
520
521 static void
522 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
523 struct radv_pipeline *pipeline)
524 {
525 struct radeon_winsys *ws = cmd_buffer->device->ws;
526 struct radv_shader_variant *ps, *vs;
527 uint64_t va;
528 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
529 struct radv_blend_state *blend = &pipeline->graphics.blend;
530 unsigned ps_offset = 0;
531 unsigned z_order;
532 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
533
534 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
535 vs = pipeline->shaders[MESA_SHADER_VERTEX];
536 va = ws->buffer_get_va(ps->bo);
537 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
538
539 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
540 radeon_emit(cmd_buffer->cs, va >> 8);
541 radeon_emit(cmd_buffer->cs, va >> 40);
542 radeon_emit(cmd_buffer->cs, ps->rsrc1);
543 radeon_emit(cmd_buffer->cs, ps->rsrc2);
544
545 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
546 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
547 else
548 z_order = V_02880C_LATE_Z;
549
550
551 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
552 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
553 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
554 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
555 S_02880C_Z_ORDER(z_order) |
556 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
557 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
558 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
559
560 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
561 ps->config.spi_ps_input_ena);
562
563 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
564 ps->config.spi_ps_input_addr);
565
566 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
567 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
568 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
569
570 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
573 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
574 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
575 V_028710_SPI_SHADER_ZERO);
576
577 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
578
579 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
580 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
581
582 if (ps->info.fs.has_pcoord) {
583 unsigned val;
584 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
585 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
586 ps_offset = 1;
587 }
588
589 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
590 unsigned vs_offset, flat_shade;
591 unsigned val;
592
593 if (!(ps->info.fs.input_mask & (1u << i)))
594 continue;
595
596
597 if (!(vs->info.vs.export_mask & (1u << i))) {
598 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
599 S_028644_OFFSET(0x20));
600 ++ps_offset;
601 continue;
602 }
603
604 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
605 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
606
607 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
608 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
609 ++ps_offset;
610 }
611 }
612
613 static void
614 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline)
616 {
617 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
618 return;
619
620 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
621 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
622 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
623 radv_update_multisample_state(cmd_buffer, pipeline);
624 radv_emit_vertex_shader(cmd_buffer, pipeline);
625 radv_emit_fragment_shader(cmd_buffer, pipeline);
626
627 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
628 pipeline->graphics.prim_restart_enable);
629
630 cmd_buffer->scratch_size_needed =
631 MAX2(cmd_buffer->scratch_size_needed,
632 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
633
634 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
635 S_0286E8_WAVES(pipeline->max_waves) |
636 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
637 cmd_buffer->state.emitted_pipeline = pipeline;
638 }
639
640 static void
641 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
642 {
643 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
644 cmd_buffer->state.dynamic.viewport.viewports);
645 }
646
647 static void
648 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
649 {
650 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
651 si_write_scissors(cmd_buffer->cs, 0, count,
652 cmd_buffer->state.dynamic.scissor.scissors);
653 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
654 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
655 }
656
657 static void
658 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
659 int index,
660 struct radv_color_buffer_info *cb)
661 {
662 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
663 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
664 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
665 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
666 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
667 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
668 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
669 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
670 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
671 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
672 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
673 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
674 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
675
676 if (is_vi) { /* DCC BASE */
677 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
678 }
679 }
680
681 static void
682 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
683 struct radv_ds_buffer_info *ds,
684 struct radv_image *image,
685 VkImageLayout layout)
686 {
687 uint32_t db_z_info = ds->db_z_info;
688
689 if (!radv_layout_has_htile(image, layout))
690 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
691
692 if (!radv_layout_can_expclear(image, layout))
693 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
696 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
697
698 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
699 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
700 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
701 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
702 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
703 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
704 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
705 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
706 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
707 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
708
709 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
710 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
711 ds->pa_su_poly_offset_db_fmt_cntl);
712 }
713
714 /*
715 * To hw resolve multisample images both src and dst need to have the same
716 * micro tiling mode. However we don't always know in advance when creating
717 * the images. This function gets called if we have a resolve attachment,
718 * and tests if the attachment image has the same tiling mode, then it
719 * checks if the generated framebuffer data has the same tiling mode, and
720 * updates it if not.
721 */
722 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
723 struct radv_attachment_info *att,
724 uint32_t micro_tile_mode)
725 {
726 struct radv_image *image = att->attachment->image;
727 uint32_t tile_mode_index;
728 if (image->surface.nsamples <= 1)
729 return;
730
731 if (image->surface.micro_tile_mode != micro_tile_mode) {
732 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
733 }
734
735 if (att->cb.micro_tile_mode != micro_tile_mode) {
736 tile_mode_index = image->surface.tiling_index[0];
737
738 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
739 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
740 att->cb.micro_tile_mode = micro_tile_mode;
741 }
742 }
743
744 void
745 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
746 struct radv_image *image,
747 VkClearDepthStencilValue ds_clear_value,
748 VkImageAspectFlags aspects)
749 {
750 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
751 va += image->offset + image->clear_value_offset;
752 unsigned reg_offset = 0, reg_count = 0;
753
754 if (!image->htile.size || !aspects)
755 return;
756
757 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
758 ++reg_count;
759 } else {
760 ++reg_offset;
761 va += 4;
762 }
763 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
764 ++reg_count;
765
766 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
767
768 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
769 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
770 S_370_WR_CONFIRM(1) |
771 S_370_ENGINE_SEL(V_370_PFP));
772 radeon_emit(cmd_buffer->cs, va);
773 radeon_emit(cmd_buffer->cs, va >> 32);
774 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
775 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
776 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
777 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
778
779 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
780 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
781 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
782 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
783 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
784 }
785
786 static void
787 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
788 struct radv_image *image)
789 {
790 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
791 va += image->offset + image->clear_value_offset;
792
793 if (!image->htile.size)
794 return;
795
796 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
797
798 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
799 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
800 COPY_DATA_DST_SEL(COPY_DATA_REG) |
801 COPY_DATA_COUNT_SEL);
802 radeon_emit(cmd_buffer->cs, va);
803 radeon_emit(cmd_buffer->cs, va >> 32);
804 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
805 radeon_emit(cmd_buffer->cs, 0);
806
807 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
808 radeon_emit(cmd_buffer->cs, 0);
809 }
810
811 void
812 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_image *image,
814 int idx,
815 uint32_t color_values[2])
816 {
817 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
818 va += image->offset + image->clear_value_offset;
819
820 if (!image->cmask.size && !image->surface.dcc_size)
821 return;
822
823 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
824
825 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
826 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
827 S_370_WR_CONFIRM(1) |
828 S_370_ENGINE_SEL(V_370_PFP));
829 radeon_emit(cmd_buffer->cs, va);
830 radeon_emit(cmd_buffer->cs, va >> 32);
831 radeon_emit(cmd_buffer->cs, color_values[0]);
832 radeon_emit(cmd_buffer->cs, color_values[1]);
833
834 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
835 radeon_emit(cmd_buffer->cs, color_values[0]);
836 radeon_emit(cmd_buffer->cs, color_values[1]);
837 }
838
839 static void
840 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_image *image,
842 int idx)
843 {
844 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
845 va += image->offset + image->clear_value_offset;
846
847 if (!image->cmask.size && !image->surface.dcc_size)
848 return;
849
850 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
851 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
852
853 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
854 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
855 COPY_DATA_DST_SEL(COPY_DATA_REG) |
856 COPY_DATA_COUNT_SEL);
857 radeon_emit(cmd_buffer->cs, va);
858 radeon_emit(cmd_buffer->cs, va >> 32);
859 radeon_emit(cmd_buffer->cs, reg >> 2);
860 radeon_emit(cmd_buffer->cs, 0);
861
862 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
863 radeon_emit(cmd_buffer->cs, 0);
864 }
865
866 void
867 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
868 {
869 int i;
870 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
871 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
872 int dst_resolve_micro_tile_mode = -1;
873
874 if (subpass->has_resolve) {
875 uint32_t a = subpass->resolve_attachments[0].attachment;
876 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
877 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
878 }
879 for (i = 0; i < subpass->color_count; ++i) {
880 int idx = subpass->color_attachments[i].attachment;
881 struct radv_attachment_info *att = &framebuffer->attachments[idx];
882
883 if (dst_resolve_micro_tile_mode != -1) {
884 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
885 att, dst_resolve_micro_tile_mode);
886 }
887 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
888
889 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
890 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
891
892 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
893 }
894
895 for (i = subpass->color_count; i < 8; i++)
896 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
897 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
898
899 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
900 int idx = subpass->depth_stencil_attachment.attachment;
901 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
902 struct radv_attachment_info *att = &framebuffer->attachments[idx];
903 struct radv_image *image = att->attachment->image;
904 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
905
906 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
907
908 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
909 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
910 cmd_buffer->state.offset_scale = att->ds.offset_scale;
911 }
912 radv_load_depth_clear_regs(cmd_buffer, image);
913 } else {
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
915 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
916 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
917 }
918 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
919 S_028208_BR_X(framebuffer->width) |
920 S_028208_BR_Y(framebuffer->height));
921 }
922
923 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
924 {
925 uint32_t db_count_control;
926
927 if(!cmd_buffer->state.active_occlusion_queries) {
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
929 db_count_control = 0;
930 } else {
931 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
932 }
933 } else {
934 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
935 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
936 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
937 S_028004_ZPASS_ENABLE(1) |
938 S_028004_SLICE_EVEN_ENABLE(1) |
939 S_028004_SLICE_ODD_ENABLE(1);
940 } else {
941 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
942 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
943 }
944 }
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
947 }
948
949 static void
950 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
951 {
952 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
953
954 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
955 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
956 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
957 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
958 }
959
960 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
962 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
963 }
964
965 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
966 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
968 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
969 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
970 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
971 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
972 S_028430_STENCILOPVAL(1));
973 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
974 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
975 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
976 S_028434_STENCILOPVAL_BF(1));
977 }
978
979 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
980 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
981 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
982 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
983 }
984
985 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
987 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
988 unsigned slope = fui(d->depth_bias.slope * 16.0f);
989 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
990
991 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
992 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
993 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
994 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
995 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
996 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
997 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
998 }
999 }
1000
1001 cmd_buffer->state.dirty = 0;
1002 }
1003
1004 static void
1005 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_pipeline *pipeline,
1007 int idx,
1008 uint64_t va,
1009 gl_shader_stage stage)
1010 {
1011 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1012 uint32_t base_reg = shader_stage_to_user_data_0(stage);
1013
1014 if (desc_set_loc->sgpr_idx == -1)
1015 return;
1016
1017 assert(!desc_set_loc->indirect);
1018 assert(desc_set_loc->num_sgprs == 2);
1019 radeon_set_sh_reg_seq(cmd_buffer->cs,
1020 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1021 radeon_emit(cmd_buffer->cs, va);
1022 radeon_emit(cmd_buffer->cs, va >> 32);
1023 }
1024
1025 static void
1026 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_pipeline *pipeline,
1028 VkShaderStageFlags stages,
1029 struct radv_descriptor_set *set,
1030 unsigned idx)
1031 {
1032 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1033 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1034 idx, set->va,
1035 MESA_SHADER_FRAGMENT);
1036
1037 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1038 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1039 idx, set->va,
1040 MESA_SHADER_VERTEX);
1041
1042 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1043 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1044 idx, set->va,
1045 MESA_SHADER_COMPUTE);
1046 }
1047
1048 static void
1049 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1050 struct radv_pipeline *pipeline,
1051 VkShaderStageFlags stages)
1052 {
1053 unsigned i;
1054 if (!cmd_buffer->state.descriptors_dirty)
1055 return;
1056
1057 for (i = 0; i < MAX_SETS; i++) {
1058 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1059 continue;
1060 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1061 if (!set)
1062 continue;
1063
1064 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1065 }
1066 cmd_buffer->state.descriptors_dirty = 0;
1067 }
1068
1069 static void
1070 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_pipeline *pipeline,
1072 VkShaderStageFlags stages)
1073 {
1074 struct radv_pipeline_layout *layout = pipeline->layout;
1075 unsigned offset;
1076 void *ptr;
1077 uint64_t va;
1078
1079 stages &= cmd_buffer->push_constant_stages;
1080 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1081 return;
1082
1083 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1084 16 * layout->dynamic_offset_count,
1085 256, &offset, &ptr);
1086
1087 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1088 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1089 16 * layout->dynamic_offset_count);
1090
1091 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1092 va += offset;
1093
1094 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1095 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1096 AC_UD_PUSH_CONSTANTS, va);
1097
1098 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1099 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1100 AC_UD_PUSH_CONSTANTS, va);
1101
1102 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1103 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1104 AC_UD_PUSH_CONSTANTS, va);
1105
1106 cmd_buffer->push_constant_stages &= ~stages;
1107 }
1108
1109 static void
1110 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1111 {
1112 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1113 struct radv_device *device = cmd_buffer->device;
1114 uint32_t ia_multi_vgt_param;
1115 uint32_t ls_hs_config = 0;
1116
1117 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1118 cmd_buffer->cs, 4096);
1119
1120 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1121 cmd_buffer->state.pipeline->num_vertex_attribs) {
1122 unsigned vb_offset;
1123 void *vb_ptr;
1124 uint32_t i = 0;
1125 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1126 uint64_t va;
1127
1128 /* allocate some descriptor state for vertex buffers */
1129 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1130 &vb_offset, &vb_ptr);
1131
1132 for (i = 0; i < num_attribs; i++) {
1133 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1134 uint32_t offset;
1135 int vb = cmd_buffer->state.pipeline->va_binding[i];
1136 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1137 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1138
1139 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1140 va = device->ws->buffer_get_va(buffer->bo);
1141
1142 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1143 va += offset + buffer->offset;
1144 desc[0] = va;
1145 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1146 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1147 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1148 else
1149 desc[2] = buffer->size - offset;
1150 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1151 }
1152
1153 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1154 va += vb_offset;
1155
1156 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1157 AC_UD_VS_VERTEX_BUFFERS, va);
1158 }
1159
1160 cmd_buffer->state.vertex_descriptors_dirty = false;
1161 cmd_buffer->state.vb_dirty = 0;
1162 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1163 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1164
1165 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1166 radv_emit_framebuffer_state(cmd_buffer);
1167
1168 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1169 radv_emit_viewport(cmd_buffer);
1170
1171 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1172 radv_emit_scissor(cmd_buffer);
1173
1174 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1175 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1176 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1177
1178 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1179 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1180 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1181 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1182 } else {
1183 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1184 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1185 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1186 }
1187 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1188 }
1189
1190 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1191
1192 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1193 VK_SHADER_STAGE_ALL_GRAPHICS);
1194 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1195 VK_SHADER_STAGE_ALL_GRAPHICS);
1196
1197 assert(cmd_buffer->cs->cdw <= cdw_max);
1198
1199 si_emit_cache_flush(cmd_buffer);
1200 }
1201
1202 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1203 VkPipelineStageFlags src_stage_mask)
1204 {
1205 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1206 VK_PIPELINE_STAGE_TRANSFER_BIT |
1207 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1208 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1209 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1210 }
1211
1212 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1213 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1214 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1215 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1216 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1217 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1218 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1219 VK_PIPELINE_STAGE_TRANSFER_BIT |
1220 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1221 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1222 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1223 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1224 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1225 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1226 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1227 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1228 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1229 }
1230 }
1231
1232 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1233 {
1234 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1235
1236 /* TODO: actual cache flushes */
1237 }
1238
1239 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1240 VkAttachmentReference att)
1241 {
1242 unsigned idx = att.attachment;
1243 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1244 VkImageSubresourceRange range;
1245 range.aspectMask = 0;
1246 range.baseMipLevel = view->base_mip;
1247 range.levelCount = 1;
1248 range.baseArrayLayer = view->base_layer;
1249 range.layerCount = cmd_buffer->state.framebuffer->layers;
1250
1251 radv_handle_image_transition(cmd_buffer,
1252 view->image,
1253 cmd_buffer->state.attachments[idx].current_layout,
1254 att.layout, 0, 0, range,
1255 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1256
1257 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1258
1259
1260 }
1261
1262 void
1263 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1264 const struct radv_subpass *subpass, bool transitions)
1265 {
1266 if (transitions) {
1267 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1268
1269 for (unsigned i = 0; i < subpass->color_count; ++i) {
1270 radv_handle_subpass_image_transition(cmd_buffer,
1271 subpass->color_attachments[i]);
1272 }
1273
1274 for (unsigned i = 0; i < subpass->input_count; ++i) {
1275 radv_handle_subpass_image_transition(cmd_buffer,
1276 subpass->input_attachments[i]);
1277 }
1278
1279 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1280 radv_handle_subpass_image_transition(cmd_buffer,
1281 subpass->depth_stencil_attachment);
1282 }
1283 }
1284
1285 cmd_buffer->state.subpass = subpass;
1286
1287 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1288 }
1289
1290 static void
1291 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_render_pass *pass,
1293 const VkRenderPassBeginInfo *info)
1294 {
1295 struct radv_cmd_state *state = &cmd_buffer->state;
1296
1297 if (pass->attachment_count == 0) {
1298 state->attachments = NULL;
1299 return;
1300 }
1301
1302 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1303 pass->attachment_count *
1304 sizeof(state->attachments[0]),
1305 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1306 if (state->attachments == NULL) {
1307 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1308 abort();
1309 }
1310
1311 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1312 struct radv_render_pass_attachment *att = &pass->attachments[i];
1313 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1314 VkImageAspectFlags clear_aspects = 0;
1315
1316 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1317 /* color attachment */
1318 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1319 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1320 }
1321 } else {
1322 /* depthstencil attachment */
1323 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1324 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1325 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1326 }
1327 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1328 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1329 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1330 }
1331 }
1332
1333 state->attachments[i].pending_clear_aspects = clear_aspects;
1334 if (clear_aspects && info) {
1335 assert(info->clearValueCount > i);
1336 state->attachments[i].clear_value = info->pClearValues[i];
1337 }
1338
1339 state->attachments[i].current_layout = att->initial_layout;
1340 }
1341 }
1342
1343 VkResult radv_AllocateCommandBuffers(
1344 VkDevice _device,
1345 const VkCommandBufferAllocateInfo *pAllocateInfo,
1346 VkCommandBuffer *pCommandBuffers)
1347 {
1348 RADV_FROM_HANDLE(radv_device, device, _device);
1349 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1350
1351 VkResult result = VK_SUCCESS;
1352 uint32_t i;
1353
1354 memset(pCommandBuffers, 0,
1355 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1356
1357 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1358 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1359 &pCommandBuffers[i]);
1360 if (result != VK_SUCCESS)
1361 break;
1362 }
1363
1364 if (result != VK_SUCCESS)
1365 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1366 i, pCommandBuffers);
1367
1368 return result;
1369 }
1370
1371 static void
1372 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1373 {
1374 list_del(&cmd_buffer->pool_link);
1375
1376 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1377 &cmd_buffer->upload.list, list) {
1378 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1379 list_del(&up->list);
1380 free(up);
1381 }
1382
1383 if (cmd_buffer->upload.upload_bo)
1384 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1385 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1386 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1387 }
1388
1389 void radv_FreeCommandBuffers(
1390 VkDevice device,
1391 VkCommandPool commandPool,
1392 uint32_t commandBufferCount,
1393 const VkCommandBuffer *pCommandBuffers)
1394 {
1395 for (uint32_t i = 0; i < commandBufferCount; i++) {
1396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1397
1398 if (cmd_buffer)
1399 radv_cmd_buffer_destroy(cmd_buffer);
1400 }
1401 }
1402
1403 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1404 {
1405
1406 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1407
1408 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1409 &cmd_buffer->upload.list, list) {
1410 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1411 list_del(&up->list);
1412 free(up);
1413 }
1414
1415 cmd_buffer->scratch_size_needed = 0;
1416 cmd_buffer->compute_scratch_size_needed = 0;
1417 if (cmd_buffer->upload.upload_bo)
1418 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1419 cmd_buffer->upload.upload_bo, 8);
1420 cmd_buffer->upload.offset = 0;
1421
1422 cmd_buffer->record_fail = false;
1423 }
1424
1425 VkResult radv_ResetCommandBuffer(
1426 VkCommandBuffer commandBuffer,
1427 VkCommandBufferResetFlags flags)
1428 {
1429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1430 radv_reset_cmd_buffer(cmd_buffer);
1431 return VK_SUCCESS;
1432 }
1433
1434 VkResult radv_BeginCommandBuffer(
1435 VkCommandBuffer commandBuffer,
1436 const VkCommandBufferBeginInfo *pBeginInfo)
1437 {
1438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1439 radv_reset_cmd_buffer(cmd_buffer);
1440
1441 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1442
1443 /* setup initial configuration into command buffer */
1444 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1445 switch (cmd_buffer->queue_family_index) {
1446 case RADV_QUEUE_GENERAL:
1447 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1448 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1449 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1450 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1451 RADV_CMD_FLAG_INV_VMEM_L1 |
1452 RADV_CMD_FLAG_INV_SMEM_L1 |
1453 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1454 RADV_CMD_FLAG_INV_GLOBAL_L2;
1455 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1456 radv_set_db_count_control(cmd_buffer);
1457 si_emit_cache_flush(cmd_buffer);
1458 break;
1459 case RADV_QUEUE_COMPUTE:
1460 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1461 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1462 RADV_CMD_FLAG_INV_VMEM_L1 |
1463 RADV_CMD_FLAG_INV_SMEM_L1 |
1464 RADV_CMD_FLAG_INV_GLOBAL_L2;
1465 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1466 si_emit_cache_flush(cmd_buffer);
1467 break;
1468 case RADV_QUEUE_TRANSFER:
1469 default:
1470 break;
1471 }
1472 }
1473
1474 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1475 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1476 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1477
1478 struct radv_subpass *subpass =
1479 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1480
1481 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1482 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1483 }
1484
1485 return VK_SUCCESS;
1486 }
1487
1488 void radv_CmdBindVertexBuffers(
1489 VkCommandBuffer commandBuffer,
1490 uint32_t firstBinding,
1491 uint32_t bindingCount,
1492 const VkBuffer* pBuffers,
1493 const VkDeviceSize* pOffsets)
1494 {
1495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1496 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1497
1498 /* We have to defer setting up vertex buffer since we need the buffer
1499 * stride from the pipeline. */
1500
1501 assert(firstBinding + bindingCount < MAX_VBS);
1502 for (uint32_t i = 0; i < bindingCount; i++) {
1503 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1504 vb[firstBinding + i].offset = pOffsets[i];
1505 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1506 }
1507 }
1508
1509 void radv_CmdBindIndexBuffer(
1510 VkCommandBuffer commandBuffer,
1511 VkBuffer buffer,
1512 VkDeviceSize offset,
1513 VkIndexType indexType)
1514 {
1515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1516
1517 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1518 cmd_buffer->state.index_offset = offset;
1519 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1520 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1521 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1522 }
1523
1524
1525 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1526 struct radv_descriptor_set *set,
1527 unsigned idx)
1528 {
1529 struct radeon_winsys *ws = cmd_buffer->device->ws;
1530
1531 cmd_buffer->state.descriptors[idx] = set;
1532 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1533 if (!set)
1534 return;
1535
1536 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1537 if (set->descriptors[j])
1538 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1539
1540 if(set->bo)
1541 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1542 }
1543
1544 void radv_CmdBindDescriptorSets(
1545 VkCommandBuffer commandBuffer,
1546 VkPipelineBindPoint pipelineBindPoint,
1547 VkPipelineLayout _layout,
1548 uint32_t firstSet,
1549 uint32_t descriptorSetCount,
1550 const VkDescriptorSet* pDescriptorSets,
1551 uint32_t dynamicOffsetCount,
1552 const uint32_t* pDynamicOffsets)
1553 {
1554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1555 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1556 unsigned dyn_idx = 0;
1557
1558 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1559 cmd_buffer->cs, MAX_SETS * 4 * 6);
1560
1561 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1562 unsigned idx = i + firstSet;
1563 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1564 radv_bind_descriptor_set(cmd_buffer, set, idx);
1565
1566 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1567 unsigned idx = j + layout->set[i].dynamic_offset_start;
1568 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1569 assert(dyn_idx < dynamicOffsetCount);
1570
1571 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1572 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1573 dst[0] = va;
1574 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1575 dst[2] = range->size;
1576 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1577 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1578 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1579 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1580 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1581 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1582 cmd_buffer->push_constant_stages |=
1583 set->layout->dynamic_shader_stages;
1584 }
1585 }
1586
1587 assert(cmd_buffer->cs->cdw <= cdw_max);
1588 }
1589
1590 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1591 VkPipelineLayout layout,
1592 VkShaderStageFlags stageFlags,
1593 uint32_t offset,
1594 uint32_t size,
1595 const void* pValues)
1596 {
1597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1598 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1599 cmd_buffer->push_constant_stages |= stageFlags;
1600 }
1601
1602 VkResult radv_EndCommandBuffer(
1603 VkCommandBuffer commandBuffer)
1604 {
1605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1606
1607 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1608 si_emit_cache_flush(cmd_buffer);
1609 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1610 cmd_buffer->record_fail)
1611 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1612 return VK_SUCCESS;
1613 }
1614
1615 static void
1616 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1617 {
1618 struct radeon_winsys *ws = cmd_buffer->device->ws;
1619 struct radv_shader_variant *compute_shader;
1620 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1621 uint64_t va;
1622
1623 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1624 return;
1625
1626 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1627
1628 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1629 va = ws->buffer_get_va(compute_shader->bo);
1630
1631 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1632
1633 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1634 cmd_buffer->cs, 16);
1635
1636 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1637 radeon_emit(cmd_buffer->cs, va >> 8);
1638 radeon_emit(cmd_buffer->cs, va >> 40);
1639
1640 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1641 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1642 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1643
1644
1645 cmd_buffer->compute_scratch_size_needed =
1646 MAX2(cmd_buffer->compute_scratch_size_needed,
1647 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1648
1649 /* change these once we have scratch support */
1650 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1651 S_00B860_WAVES(pipeline->max_waves) |
1652 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1653
1654 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1655 radeon_emit(cmd_buffer->cs,
1656 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1657 radeon_emit(cmd_buffer->cs,
1658 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1659 radeon_emit(cmd_buffer->cs,
1660 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1661
1662 assert(cmd_buffer->cs->cdw <= cdw_max);
1663 }
1664
1665
1666 void radv_CmdBindPipeline(
1667 VkCommandBuffer commandBuffer,
1668 VkPipelineBindPoint pipelineBindPoint,
1669 VkPipeline _pipeline)
1670 {
1671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1672 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1673
1674 for (unsigned i = 0; i < MAX_SETS; i++) {
1675 if (cmd_buffer->state.descriptors[i])
1676 cmd_buffer->state.descriptors_dirty |= (1 << i);
1677 }
1678
1679 switch (pipelineBindPoint) {
1680 case VK_PIPELINE_BIND_POINT_COMPUTE:
1681 cmd_buffer->state.compute_pipeline = pipeline;
1682 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1683 break;
1684 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1685 cmd_buffer->state.pipeline = pipeline;
1686 cmd_buffer->state.vertex_descriptors_dirty = true;
1687 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1688 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1689
1690 /* Apply the dynamic state from the pipeline */
1691 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1692 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1693 &pipeline->dynamic_state,
1694 pipeline->dynamic_state_mask);
1695 break;
1696 default:
1697 assert(!"invalid bind point");
1698 break;
1699 }
1700 }
1701
1702 void radv_CmdSetViewport(
1703 VkCommandBuffer commandBuffer,
1704 uint32_t firstViewport,
1705 uint32_t viewportCount,
1706 const VkViewport* pViewports)
1707 {
1708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1709
1710 const uint32_t total_count = firstViewport + viewportCount;
1711 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1712 cmd_buffer->state.dynamic.viewport.count = total_count;
1713
1714 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1715 pViewports, viewportCount * sizeof(*pViewports));
1716
1717 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1718 }
1719
1720 void radv_CmdSetScissor(
1721 VkCommandBuffer commandBuffer,
1722 uint32_t firstScissor,
1723 uint32_t scissorCount,
1724 const VkRect2D* pScissors)
1725 {
1726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1727
1728 const uint32_t total_count = firstScissor + scissorCount;
1729 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1730 cmd_buffer->state.dynamic.scissor.count = total_count;
1731
1732 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1733 pScissors, scissorCount * sizeof(*pScissors));
1734 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1735 }
1736
1737 void radv_CmdSetLineWidth(
1738 VkCommandBuffer commandBuffer,
1739 float lineWidth)
1740 {
1741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1742 cmd_buffer->state.dynamic.line_width = lineWidth;
1743 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1744 }
1745
1746 void radv_CmdSetDepthBias(
1747 VkCommandBuffer commandBuffer,
1748 float depthBiasConstantFactor,
1749 float depthBiasClamp,
1750 float depthBiasSlopeFactor)
1751 {
1752 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1753
1754 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1755 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1756 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1757
1758 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1759 }
1760
1761 void radv_CmdSetBlendConstants(
1762 VkCommandBuffer commandBuffer,
1763 const float blendConstants[4])
1764 {
1765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1766
1767 memcpy(cmd_buffer->state.dynamic.blend_constants,
1768 blendConstants, sizeof(float) * 4);
1769
1770 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1771 }
1772
1773 void radv_CmdSetDepthBounds(
1774 VkCommandBuffer commandBuffer,
1775 float minDepthBounds,
1776 float maxDepthBounds)
1777 {
1778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1779
1780 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1781 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1782
1783 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1784 }
1785
1786 void radv_CmdSetStencilCompareMask(
1787 VkCommandBuffer commandBuffer,
1788 VkStencilFaceFlags faceMask,
1789 uint32_t compareMask)
1790 {
1791 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1792
1793 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1794 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1795 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1796 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1797
1798 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1799 }
1800
1801 void radv_CmdSetStencilWriteMask(
1802 VkCommandBuffer commandBuffer,
1803 VkStencilFaceFlags faceMask,
1804 uint32_t writeMask)
1805 {
1806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1807
1808 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1809 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1810 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1811 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1812
1813 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1814 }
1815
1816 void radv_CmdSetStencilReference(
1817 VkCommandBuffer commandBuffer,
1818 VkStencilFaceFlags faceMask,
1819 uint32_t reference)
1820 {
1821 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1822
1823 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1824 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1825 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1826 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1827
1828 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1829 }
1830
1831
1832 void radv_CmdExecuteCommands(
1833 VkCommandBuffer commandBuffer,
1834 uint32_t commandBufferCount,
1835 const VkCommandBuffer* pCmdBuffers)
1836 {
1837 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1838
1839 for (uint32_t i = 0; i < commandBufferCount; i++) {
1840 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1841
1842 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
1843 secondary->scratch_size_needed);
1844 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
1845 secondary->compute_scratch_size_needed);
1846
1847 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1848 }
1849
1850 /* if we execute secondary we need to re-emit out pipelines */
1851 if (commandBufferCount) {
1852 primary->state.emitted_pipeline = NULL;
1853 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1854 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1855 }
1856 }
1857
1858 VkResult radv_CreateCommandPool(
1859 VkDevice _device,
1860 const VkCommandPoolCreateInfo* pCreateInfo,
1861 const VkAllocationCallbacks* pAllocator,
1862 VkCommandPool* pCmdPool)
1863 {
1864 RADV_FROM_HANDLE(radv_device, device, _device);
1865 struct radv_cmd_pool *pool;
1866
1867 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1869 if (pool == NULL)
1870 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1871
1872 if (pAllocator)
1873 pool->alloc = *pAllocator;
1874 else
1875 pool->alloc = device->alloc;
1876
1877 list_inithead(&pool->cmd_buffers);
1878
1879 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1880
1881 *pCmdPool = radv_cmd_pool_to_handle(pool);
1882
1883 return VK_SUCCESS;
1884
1885 }
1886
1887 void radv_DestroyCommandPool(
1888 VkDevice _device,
1889 VkCommandPool commandPool,
1890 const VkAllocationCallbacks* pAllocator)
1891 {
1892 RADV_FROM_HANDLE(radv_device, device, _device);
1893 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1894
1895 if (!pool)
1896 return;
1897
1898 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1899 &pool->cmd_buffers, pool_link) {
1900 radv_cmd_buffer_destroy(cmd_buffer);
1901 }
1902
1903 vk_free2(&device->alloc, pAllocator, pool);
1904 }
1905
1906 VkResult radv_ResetCommandPool(
1907 VkDevice device,
1908 VkCommandPool commandPool,
1909 VkCommandPoolResetFlags flags)
1910 {
1911 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1912
1913 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1914 &pool->cmd_buffers, pool_link) {
1915 radv_reset_cmd_buffer(cmd_buffer);
1916 }
1917
1918 return VK_SUCCESS;
1919 }
1920
1921 void radv_TrimCommandPoolKHR(
1922 VkDevice device,
1923 VkCommandPool commandPool,
1924 VkCommandPoolTrimFlagsKHR flags)
1925 {
1926 }
1927
1928 void radv_CmdBeginRenderPass(
1929 VkCommandBuffer commandBuffer,
1930 const VkRenderPassBeginInfo* pRenderPassBegin,
1931 VkSubpassContents contents)
1932 {
1933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1934 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1935 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1936
1937 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1938 cmd_buffer->cs, 2048);
1939
1940 cmd_buffer->state.framebuffer = framebuffer;
1941 cmd_buffer->state.pass = pass;
1942 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1943 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1944
1945 si_emit_cache_flush(cmd_buffer);
1946
1947 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1948 assert(cmd_buffer->cs->cdw <= cdw_max);
1949
1950 radv_cmd_buffer_clear_subpass(cmd_buffer);
1951 }
1952
1953 void radv_CmdNextSubpass(
1954 VkCommandBuffer commandBuffer,
1955 VkSubpassContents contents)
1956 {
1957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1958
1959 si_emit_cache_flush(cmd_buffer);
1960 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1961
1962 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1963 2048);
1964
1965 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1966 radv_cmd_buffer_clear_subpass(cmd_buffer);
1967 }
1968
1969 void radv_CmdDraw(
1970 VkCommandBuffer commandBuffer,
1971 uint32_t vertexCount,
1972 uint32_t instanceCount,
1973 uint32_t firstVertex,
1974 uint32_t firstInstance)
1975 {
1976 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1977 radv_cmd_buffer_flush_state(cmd_buffer);
1978
1979 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1980
1981 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1982 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1983 if (loc->sgpr_idx != -1) {
1984 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1985 radeon_emit(cmd_buffer->cs, firstVertex);
1986 radeon_emit(cmd_buffer->cs, firstInstance);
1987 }
1988 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1989 radeon_emit(cmd_buffer->cs, instanceCount);
1990
1991 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1992 radeon_emit(cmd_buffer->cs, vertexCount);
1993 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1994 S_0287F0_USE_OPAQUE(0));
1995
1996 assert(cmd_buffer->cs->cdw <= cdw_max);
1997
1998 radv_cmd_buffer_trace_emit(cmd_buffer);
1999 }
2000
2001 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2002 {
2003 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2004
2005 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2006 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2007 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2008 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2009 primitive_reset_index);
2010 }
2011 }
2012
2013 void radv_CmdDrawIndexed(
2014 VkCommandBuffer commandBuffer,
2015 uint32_t indexCount,
2016 uint32_t instanceCount,
2017 uint32_t firstIndex,
2018 int32_t vertexOffset,
2019 uint32_t firstInstance)
2020 {
2021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2022 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2023 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2024 uint64_t index_va;
2025
2026 radv_cmd_buffer_flush_state(cmd_buffer);
2027 radv_emit_primitive_reset_index(cmd_buffer);
2028
2029 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
2030
2031 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2032 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2033
2034 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2035 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2036 if (loc->sgpr_idx != -1) {
2037 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
2038 radeon_emit(cmd_buffer->cs, vertexOffset);
2039 radeon_emit(cmd_buffer->cs, firstInstance);
2040 }
2041 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2042 radeon_emit(cmd_buffer->cs, instanceCount);
2043
2044 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2045 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2046 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2047 radeon_emit(cmd_buffer->cs, index_max_size);
2048 radeon_emit(cmd_buffer->cs, index_va);
2049 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2050 radeon_emit(cmd_buffer->cs, indexCount);
2051 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2052
2053 assert(cmd_buffer->cs->cdw <= cdw_max);
2054 radv_cmd_buffer_trace_emit(cmd_buffer);
2055 }
2056
2057 static void
2058 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2059 VkBuffer _buffer,
2060 VkDeviceSize offset,
2061 VkBuffer _count_buffer,
2062 VkDeviceSize count_offset,
2063 uint32_t draw_count,
2064 uint32_t stride,
2065 bool indexed)
2066 {
2067 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2068 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2069 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2070 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2071 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2072 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2073 indirect_va += offset + buffer->offset;
2074 uint64_t count_va = 0;
2075
2076 if (count_buffer) {
2077 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2078 count_va += count_offset + count_buffer->offset;
2079 }
2080
2081 if (!draw_count)
2082 return;
2083
2084 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2085
2086 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2087 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2088 assert(loc->sgpr_idx != -1);
2089 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2090 radeon_emit(cs, 1);
2091 radeon_emit(cs, indirect_va);
2092 radeon_emit(cs, indirect_va >> 32);
2093
2094 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2095 PKT3_DRAW_INDIRECT_MULTI,
2096 8, false));
2097 radeon_emit(cs, 0);
2098 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2099 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2100 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2101 radeon_emit(cs, draw_count); /* count */
2102 radeon_emit(cs, count_va); /* count_addr */
2103 radeon_emit(cs, count_va >> 32);
2104 radeon_emit(cs, stride); /* stride */
2105 radeon_emit(cs, di_src_sel);
2106 radv_cmd_buffer_trace_emit(cmd_buffer);
2107 }
2108
2109 static void
2110 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2111 VkBuffer buffer,
2112 VkDeviceSize offset,
2113 VkBuffer countBuffer,
2114 VkDeviceSize countBufferOffset,
2115 uint32_t maxDrawCount,
2116 uint32_t stride)
2117 {
2118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2119 radv_cmd_buffer_flush_state(cmd_buffer);
2120
2121 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2122 cmd_buffer->cs, 14);
2123
2124 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2125 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2126
2127 assert(cmd_buffer->cs->cdw <= cdw_max);
2128 }
2129
2130 static void
2131 radv_cmd_draw_indexed_indirect_count(
2132 VkCommandBuffer commandBuffer,
2133 VkBuffer buffer,
2134 VkDeviceSize offset,
2135 VkBuffer countBuffer,
2136 VkDeviceSize countBufferOffset,
2137 uint32_t maxDrawCount,
2138 uint32_t stride)
2139 {
2140 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2141 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2142 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2143 uint64_t index_va;
2144 radv_cmd_buffer_flush_state(cmd_buffer);
2145 radv_emit_primitive_reset_index(cmd_buffer);
2146
2147 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2148 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2149
2150 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2151
2152 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2153 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2154
2155 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2156 radeon_emit(cmd_buffer->cs, index_va);
2157 radeon_emit(cmd_buffer->cs, index_va >> 32);
2158
2159 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2160 radeon_emit(cmd_buffer->cs, index_max_size);
2161
2162 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2163 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2164
2165 assert(cmd_buffer->cs->cdw <= cdw_max);
2166 }
2167
2168 void radv_CmdDrawIndirect(
2169 VkCommandBuffer commandBuffer,
2170 VkBuffer buffer,
2171 VkDeviceSize offset,
2172 uint32_t drawCount,
2173 uint32_t stride)
2174 {
2175 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2176 VK_NULL_HANDLE, 0, drawCount, stride);
2177 }
2178
2179 void radv_CmdDrawIndexedIndirect(
2180 VkCommandBuffer commandBuffer,
2181 VkBuffer buffer,
2182 VkDeviceSize offset,
2183 uint32_t drawCount,
2184 uint32_t stride)
2185 {
2186 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2187 VK_NULL_HANDLE, 0, drawCount, stride);
2188 }
2189
2190 void radv_CmdDrawIndirectCountAMD(
2191 VkCommandBuffer commandBuffer,
2192 VkBuffer buffer,
2193 VkDeviceSize offset,
2194 VkBuffer countBuffer,
2195 VkDeviceSize countBufferOffset,
2196 uint32_t maxDrawCount,
2197 uint32_t stride)
2198 {
2199 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2200 countBuffer, countBufferOffset,
2201 maxDrawCount, stride);
2202 }
2203
2204 void radv_CmdDrawIndexedIndirectCountAMD(
2205 VkCommandBuffer commandBuffer,
2206 VkBuffer buffer,
2207 VkDeviceSize offset,
2208 VkBuffer countBuffer,
2209 VkDeviceSize countBufferOffset,
2210 uint32_t maxDrawCount,
2211 uint32_t stride)
2212 {
2213 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2214 countBuffer, countBufferOffset,
2215 maxDrawCount, stride);
2216 }
2217
2218 static void
2219 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2220 {
2221 radv_emit_compute_pipeline(cmd_buffer);
2222 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2223 VK_SHADER_STAGE_COMPUTE_BIT);
2224 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2225 VK_SHADER_STAGE_COMPUTE_BIT);
2226 si_emit_cache_flush(cmd_buffer);
2227 }
2228
2229 void radv_CmdDispatch(
2230 VkCommandBuffer commandBuffer,
2231 uint32_t x,
2232 uint32_t y,
2233 uint32_t z)
2234 {
2235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236
2237 radv_flush_compute_state(cmd_buffer);
2238
2239 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2240
2241 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2242 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2243 if (loc->sgpr_idx != -1) {
2244 assert(!loc->indirect);
2245 assert(loc->num_sgprs == 3);
2246 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2247 radeon_emit(cmd_buffer->cs, x);
2248 radeon_emit(cmd_buffer->cs, y);
2249 radeon_emit(cmd_buffer->cs, z);
2250 }
2251
2252 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2253 PKT3_SHADER_TYPE_S(1));
2254 radeon_emit(cmd_buffer->cs, x);
2255 radeon_emit(cmd_buffer->cs, y);
2256 radeon_emit(cmd_buffer->cs, z);
2257 radeon_emit(cmd_buffer->cs, 1);
2258
2259 assert(cmd_buffer->cs->cdw <= cdw_max);
2260 radv_cmd_buffer_trace_emit(cmd_buffer);
2261 }
2262
2263 void radv_CmdDispatchIndirect(
2264 VkCommandBuffer commandBuffer,
2265 VkBuffer _buffer,
2266 VkDeviceSize offset)
2267 {
2268 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2269 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2270 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2271 va += buffer->offset + offset;
2272
2273 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2274
2275 radv_flush_compute_state(cmd_buffer);
2276
2277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2278 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2279 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2280 if (loc->sgpr_idx != -1) {
2281 for (unsigned i = 0; i < 3; ++i) {
2282 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2283 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2284 COPY_DATA_DST_SEL(COPY_DATA_REG));
2285 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2286 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2287 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2288 radeon_emit(cmd_buffer->cs, 0);
2289 }
2290 }
2291
2292 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2293 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2294 PKT3_SHADER_TYPE_S(1));
2295 radeon_emit(cmd_buffer->cs, va);
2296 radeon_emit(cmd_buffer->cs, va >> 32);
2297 radeon_emit(cmd_buffer->cs, 1);
2298 } else {
2299 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2300 PKT3_SHADER_TYPE_S(1));
2301 radeon_emit(cmd_buffer->cs, 1);
2302 radeon_emit(cmd_buffer->cs, va);
2303 radeon_emit(cmd_buffer->cs, va >> 32);
2304
2305 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2306 PKT3_SHADER_TYPE_S(1));
2307 radeon_emit(cmd_buffer->cs, 0);
2308 radeon_emit(cmd_buffer->cs, 1);
2309 }
2310
2311 assert(cmd_buffer->cs->cdw <= cdw_max);
2312 radv_cmd_buffer_trace_emit(cmd_buffer);
2313 }
2314
2315 void radv_unaligned_dispatch(
2316 struct radv_cmd_buffer *cmd_buffer,
2317 uint32_t x,
2318 uint32_t y,
2319 uint32_t z)
2320 {
2321 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2322 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2323 uint32_t blocks[3], remainder[3];
2324
2325 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2326 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2327 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2328
2329 /* If aligned, these should be an entire block size, not 0 */
2330 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2331 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2332 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2333
2334 radv_flush_compute_state(cmd_buffer);
2335
2336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2337
2338 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2339 radeon_emit(cmd_buffer->cs,
2340 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2341 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2342 radeon_emit(cmd_buffer->cs,
2343 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2344 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2345 radeon_emit(cmd_buffer->cs,
2346 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2347 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2348
2349 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2350 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2351 if (loc->sgpr_idx != -1) {
2352 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2353 radeon_emit(cmd_buffer->cs, blocks[0]);
2354 radeon_emit(cmd_buffer->cs, blocks[1]);
2355 radeon_emit(cmd_buffer->cs, blocks[2]);
2356 }
2357 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2358 PKT3_SHADER_TYPE_S(1));
2359 radeon_emit(cmd_buffer->cs, blocks[0]);
2360 radeon_emit(cmd_buffer->cs, blocks[1]);
2361 radeon_emit(cmd_buffer->cs, blocks[2]);
2362 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2363 S_00B800_PARTIAL_TG_EN(1));
2364
2365 assert(cmd_buffer->cs->cdw <= cdw_max);
2366 radv_cmd_buffer_trace_emit(cmd_buffer);
2367 }
2368
2369 void radv_CmdEndRenderPass(
2370 VkCommandBuffer commandBuffer)
2371 {
2372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2373
2374 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2375
2376 si_emit_cache_flush(cmd_buffer);
2377 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2378
2379 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2380 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2381 radv_handle_subpass_image_transition(cmd_buffer,
2382 (VkAttachmentReference){i, layout});
2383 }
2384
2385 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2386
2387 cmd_buffer->state.pass = NULL;
2388 cmd_buffer->state.subpass = NULL;
2389 cmd_buffer->state.attachments = NULL;
2390 cmd_buffer->state.framebuffer = NULL;
2391 }
2392
2393
2394 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2395 struct radv_image *image)
2396 {
2397
2398 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2399 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2400
2401 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2402 image->htile.size, 0xffffffff);
2403
2404 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2405 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2406 RADV_CMD_FLAG_INV_VMEM_L1 |
2407 RADV_CMD_FLAG_INV_GLOBAL_L2;
2408 }
2409
2410 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2411 struct radv_image *image,
2412 VkImageLayout src_layout,
2413 VkImageLayout dst_layout,
2414 VkImageSubresourceRange range,
2415 VkImageAspectFlags pending_clears)
2416 {
2417 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2418 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2419 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2420 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2421 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2422 /* The clear will initialize htile. */
2423 return;
2424 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2425 radv_layout_has_htile(image, dst_layout)) {
2426 /* TODO: merge with the clear if applicable */
2427 radv_initialize_htile(cmd_buffer, image);
2428 } else if (!radv_layout_has_htile(image, src_layout) &&
2429 radv_layout_has_htile(image, dst_layout)) {
2430 radv_initialize_htile(cmd_buffer, image);
2431 } else if ((radv_layout_has_htile(image, src_layout) &&
2432 !radv_layout_has_htile(image, dst_layout)) ||
2433 (radv_layout_is_htile_compressed(image, src_layout) &&
2434 !radv_layout_is_htile_compressed(image, dst_layout))) {
2435
2436 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2437 range.baseMipLevel = 0;
2438 range.levelCount = 1;
2439
2440 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2441 }
2442 }
2443
2444 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2445 struct radv_image *image, uint32_t value)
2446 {
2447 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2448 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2449
2450 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2451 image->cmask.size, value);
2452
2453 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2454 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2455 RADV_CMD_FLAG_INV_VMEM_L1 |
2456 RADV_CMD_FLAG_INV_GLOBAL_L2;
2457 }
2458
2459 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2460 struct radv_image *image,
2461 VkImageLayout src_layout,
2462 VkImageLayout dst_layout,
2463 unsigned src_queue_mask,
2464 unsigned dst_queue_mask,
2465 VkImageSubresourceRange range,
2466 VkImageAspectFlags pending_clears)
2467 {
2468 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2469 if (image->fmask.size)
2470 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2471 else
2472 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2473 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2474 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2475 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2476 }
2477 }
2478
2479 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2480 struct radv_image *image, uint32_t value)
2481 {
2482
2483 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2484 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2485
2486 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2487 image->surface.dcc_size, value);
2488
2489 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2490 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2491 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2492 RADV_CMD_FLAG_INV_VMEM_L1 |
2493 RADV_CMD_FLAG_INV_GLOBAL_L2;
2494 }
2495
2496 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2497 struct radv_image *image,
2498 VkImageLayout src_layout,
2499 VkImageLayout dst_layout,
2500 unsigned src_queue_mask,
2501 unsigned dst_queue_mask,
2502 VkImageSubresourceRange range,
2503 VkImageAspectFlags pending_clears)
2504 {
2505 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2506 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2507 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2508 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2509 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2510 }
2511 }
2512
2513 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2514 struct radv_image *image,
2515 VkImageLayout src_layout,
2516 VkImageLayout dst_layout,
2517 int src_family,
2518 int dst_family,
2519 VkImageSubresourceRange range,
2520 VkImageAspectFlags pending_clears)
2521 {
2522 if (image->exclusive && src_family != dst_family) {
2523 /* This is an acquire or a release operation and there will be
2524 * a corresponding release/acquire. Do the transition in the
2525 * most flexible queue. */
2526
2527 assert(src_family == cmd_buffer->queue_family_index ||
2528 dst_family == cmd_buffer->queue_family_index);
2529
2530 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2531 return;
2532
2533 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2534 (src_family == RADV_QUEUE_GENERAL ||
2535 dst_family == RADV_QUEUE_GENERAL))
2536 return;
2537 }
2538
2539 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family);
2540 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family);
2541
2542 if (image->htile.size)
2543 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2544 dst_layout, range, pending_clears);
2545
2546 if (image->cmask.size)
2547 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2548 dst_layout, src_queue_mask,
2549 dst_queue_mask, range,
2550 pending_clears);
2551
2552 if (image->surface.dcc_size)
2553 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2554 dst_layout, src_queue_mask,
2555 dst_queue_mask, range,
2556 pending_clears);
2557 }
2558
2559 void radv_CmdPipelineBarrier(
2560 VkCommandBuffer commandBuffer,
2561 VkPipelineStageFlags srcStageMask,
2562 VkPipelineStageFlags destStageMask,
2563 VkBool32 byRegion,
2564 uint32_t memoryBarrierCount,
2565 const VkMemoryBarrier* pMemoryBarriers,
2566 uint32_t bufferMemoryBarrierCount,
2567 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2568 uint32_t imageMemoryBarrierCount,
2569 const VkImageMemoryBarrier* pImageMemoryBarriers)
2570 {
2571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2572 VkAccessFlags src_flags = 0;
2573 VkAccessFlags dst_flags = 0;
2574 uint32_t b;
2575 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2576 src_flags |= pMemoryBarriers[i].srcAccessMask;
2577 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2578 }
2579
2580 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2581 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2582 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2583 }
2584
2585 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2586 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2587 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2588 }
2589
2590 enum radv_cmd_flush_bits flush_bits = 0;
2591 for_each_bit(b, src_flags) {
2592 switch ((VkAccessFlagBits)(1 << b)) {
2593 case VK_ACCESS_SHADER_WRITE_BIT:
2594 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2595 break;
2596 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2597 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2598 break;
2599 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2600 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2601 break;
2602 case VK_ACCESS_TRANSFER_WRITE_BIT:
2603 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2604 break;
2605 default:
2606 break;
2607 }
2608 }
2609 cmd_buffer->state.flush_bits |= flush_bits;
2610
2611 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2612 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2613 radv_handle_image_transition(cmd_buffer, image,
2614 pImageMemoryBarriers[i].oldLayout,
2615 pImageMemoryBarriers[i].newLayout,
2616 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2617 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2618 pImageMemoryBarriers[i].subresourceRange,
2619 0);
2620 }
2621
2622 flush_bits = 0;
2623
2624 for_each_bit(b, dst_flags) {
2625 switch ((VkAccessFlagBits)(1 << b)) {
2626 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2627 case VK_ACCESS_INDEX_READ_BIT:
2628 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2629 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2630 break;
2631 case VK_ACCESS_UNIFORM_READ_BIT:
2632 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2633 break;
2634 case VK_ACCESS_SHADER_READ_BIT:
2635 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2636 break;
2637 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2638 case VK_ACCESS_TRANSFER_READ_BIT:
2639 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2640 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2641 default:
2642 break;
2643 }
2644 }
2645
2646 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2647 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2648
2649 cmd_buffer->state.flush_bits |= flush_bits;
2650 }
2651
2652
2653 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2654 struct radv_event *event,
2655 VkPipelineStageFlags stageMask,
2656 unsigned value)
2657 {
2658 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2659 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2660
2661 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2662
2663 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2664
2665 /* TODO: this is overkill. Probably should figure something out from
2666 * the stage mask. */
2667
2668 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2669 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2670 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2671 EVENT_INDEX(5));
2672 radeon_emit(cs, va);
2673 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2674 radeon_emit(cs, 2);
2675 radeon_emit(cs, 0);
2676 }
2677
2678 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2679 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2680 EVENT_INDEX(5));
2681 radeon_emit(cs, va);
2682 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2683 radeon_emit(cs, value);
2684 radeon_emit(cs, 0);
2685
2686 assert(cmd_buffer->cs->cdw <= cdw_max);
2687 }
2688
2689 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2690 VkEvent _event,
2691 VkPipelineStageFlags stageMask)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2694 RADV_FROM_HANDLE(radv_event, event, _event);
2695
2696 write_event(cmd_buffer, event, stageMask, 1);
2697 }
2698
2699 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2700 VkEvent _event,
2701 VkPipelineStageFlags stageMask)
2702 {
2703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704 RADV_FROM_HANDLE(radv_event, event, _event);
2705
2706 write_event(cmd_buffer, event, stageMask, 0);
2707 }
2708
2709 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2710 uint32_t eventCount,
2711 const VkEvent* pEvents,
2712 VkPipelineStageFlags srcStageMask,
2713 VkPipelineStageFlags dstStageMask,
2714 uint32_t memoryBarrierCount,
2715 const VkMemoryBarrier* pMemoryBarriers,
2716 uint32_t bufferMemoryBarrierCount,
2717 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2718 uint32_t imageMemoryBarrierCount,
2719 const VkImageMemoryBarrier* pImageMemoryBarriers)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2723
2724 for (unsigned i = 0; i < eventCount; ++i) {
2725 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2726 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2727
2728 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2729
2730 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2731
2732 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2733 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2734 radeon_emit(cs, va);
2735 radeon_emit(cs, va >> 32);
2736 radeon_emit(cs, 1); /* reference value */
2737 radeon_emit(cs, 0xffffffff); /* mask */
2738 radeon_emit(cs, 4); /* poll interval */
2739
2740 assert(cmd_buffer->cs->cdw <= cdw_max);
2741 }
2742
2743
2744 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2745 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2746
2747 radv_handle_image_transition(cmd_buffer, image,
2748 pImageMemoryBarriers[i].oldLayout,
2749 pImageMemoryBarriers[i].newLayout,
2750 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2751 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2752 pImageMemoryBarriers[i].subresourceRange,
2753 0);
2754 }
2755
2756 /* TODO: figure out how to do memory barriers without waiting */
2757 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2758 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2759 RADV_CMD_FLAG_INV_VMEM_L1 |
2760 RADV_CMD_FLAG_INV_SMEM_L1;
2761 }