2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 VkImageAspectFlags pending_clears
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
110 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
111 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
112 src
->viewport
.count
* sizeof(VkViewport
))) {
113 typed_memcpy(dest
->viewport
.viewports
,
114 src
->viewport
.viewports
,
115 src
->viewport
.count
);
116 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
120 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
121 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
122 src
->scissor
.count
* sizeof(VkRect2D
))) {
123 typed_memcpy(dest
->scissor
.scissors
,
124 src
->scissor
.scissors
, src
->scissor
.count
);
125 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
129 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
130 if (dest
->line_width
!= src
->line_width
) {
131 dest
->line_width
= src
->line_width
;
132 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
136 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
137 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
138 sizeof(src
->depth_bias
))) {
139 dest
->depth_bias
= src
->depth_bias
;
140 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
144 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
145 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
146 sizeof(src
->blend_constants
))) {
147 typed_memcpy(dest
->blend_constants
,
148 src
->blend_constants
, 4);
149 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
153 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
154 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
155 sizeof(src
->depth_bounds
))) {
156 dest
->depth_bounds
= src
->depth_bounds
;
157 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
161 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
162 if (memcmp(&dest
->stencil_compare_mask
,
163 &src
->stencil_compare_mask
,
164 sizeof(src
->stencil_compare_mask
))) {
165 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
166 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
170 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
171 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
172 sizeof(src
->stencil_write_mask
))) {
173 dest
->stencil_write_mask
= src
->stencil_write_mask
;
174 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
178 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
179 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
180 sizeof(src
->stencil_reference
))) {
181 dest
->stencil_reference
= src
->stencil_reference
;
182 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
186 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
187 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
188 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
189 typed_memcpy(dest
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
);
192 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
196 cmd_buffer
->state
.dirty
|= dest_mask
;
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
201 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
202 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
205 enum ring_type
radv_queue_family_to_ring(int f
) {
207 case RADV_QUEUE_GENERAL
:
209 case RADV_QUEUE_COMPUTE
:
211 case RADV_QUEUE_TRANSFER
:
214 unreachable("Unknown queue family");
218 static VkResult
radv_create_cmd_buffer(
219 struct radv_device
* device
,
220 struct radv_cmd_pool
* pool
,
221 VkCommandBufferLevel level
,
222 VkCommandBuffer
* pCommandBuffer
)
224 struct radv_cmd_buffer
*cmd_buffer
;
226 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
228 if (cmd_buffer
== NULL
)
229 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
231 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
232 cmd_buffer
->device
= device
;
233 cmd_buffer
->pool
= pool
;
234 cmd_buffer
->level
= level
;
237 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
238 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
241 /* Init the pool_link so we can safely call list_del when we destroy
244 list_inithead(&cmd_buffer
->pool_link
);
245 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
248 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
250 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
251 if (!cmd_buffer
->cs
) {
252 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
253 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
256 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
258 list_inithead(&cmd_buffer
->upload
.list
);
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
266 list_del(&cmd_buffer
->pool_link
);
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
269 &cmd_buffer
->upload
.list
, list
) {
270 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
275 if (cmd_buffer
->upload
.upload_bo
)
276 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
277 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
279 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
280 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
282 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
286 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
289 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
292 &cmd_buffer
->upload
.list
, list
) {
293 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
298 cmd_buffer
->push_constant_stages
= 0;
299 cmd_buffer
->scratch_size_needed
= 0;
300 cmd_buffer
->compute_scratch_size_needed
= 0;
301 cmd_buffer
->esgs_ring_size_needed
= 0;
302 cmd_buffer
->gsvs_ring_size_needed
= 0;
303 cmd_buffer
->tess_rings_needed
= false;
304 cmd_buffer
->sample_positions_needed
= false;
306 if (cmd_buffer
->upload
.upload_bo
)
307 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
308 cmd_buffer
->upload
.upload_bo
);
309 cmd_buffer
->upload
.offset
= 0;
311 cmd_buffer
->record_result
= VK_SUCCESS
;
313 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
314 cmd_buffer
->descriptors
[i
].dirty
= 0;
315 cmd_buffer
->descriptors
[i
].valid
= 0;
316 cmd_buffer
->descriptors
[i
].push_dirty
= false;
319 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
320 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
321 unsigned eop_bug_offset
;
324 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
325 &cmd_buffer
->gfx9_fence_offset
,
327 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
331 &eop_bug_offset
, &fence_ptr
);
332 cmd_buffer
->gfx9_eop_bug_va
=
333 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
334 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
337 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
339 return cmd_buffer
->record_result
;
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
347 struct radeon_winsys_bo
*bo
;
348 struct radv_cmd_buffer_upload
*upload
;
349 struct radv_device
*device
= cmd_buffer
->device
;
351 new_size
= MAX2(min_needed
, 16 * 1024);
352 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
354 bo
= device
->ws
->buffer_create(device
->ws
,
357 RADEON_FLAG_CPU_ACCESS
|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
362 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
366 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
367 if (cmd_buffer
->upload
.upload_bo
) {
368 upload
= malloc(sizeof(*upload
));
371 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
372 device
->ws
->buffer_destroy(bo
);
376 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
377 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
380 cmd_buffer
->upload
.upload_bo
= bo
;
381 cmd_buffer
->upload
.size
= new_size
;
382 cmd_buffer
->upload
.offset
= 0;
383 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
385 if (!cmd_buffer
->upload
.map
) {
386 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
397 unsigned *out_offset
,
400 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
401 if (offset
+ size
> cmd_buffer
->upload
.size
) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
407 *out_offset
= offset
;
408 *ptr
= cmd_buffer
->upload
.map
+ offset
;
410 cmd_buffer
->upload
.offset
= offset
+ size
;
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
416 unsigned size
, unsigned alignment
,
417 const void *data
, unsigned *out_offset
)
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
422 out_offset
, (void **)&ptr
))
426 memcpy(ptr
, data
, size
);
432 radv_emit_write_data_packet(struct radeon_cmdbuf
*cs
, uint64_t va
,
433 unsigned count
, const uint32_t *data
)
435 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
436 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
437 S_370_WR_CONFIRM(1) |
438 S_370_ENGINE_SEL(V_370_ME
));
440 radeon_emit(cs
, va
>> 32);
441 radeon_emit_array(cs
, data
, count
);
444 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
446 struct radv_device
*device
= cmd_buffer
->device
;
447 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
450 va
= radv_buffer_get_va(device
->trace_bo
);
451 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
454 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
456 ++cmd_buffer
->state
.trace_id
;
457 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
458 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
459 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
463 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
464 enum radv_cmd_flush_bits flags
)
466 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
467 uint32_t *ptr
= NULL
;
470 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
473 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
474 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
475 cmd_buffer
->gfx9_fence_offset
;
476 ptr
= &cmd_buffer
->gfx9_fence_idx
;
479 /* Force wait for graphics or compute engines to be idle. */
480 si_cs_emit_cache_flush(cmd_buffer
->cs
,
481 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
483 radv_cmd_buffer_uses_mec(cmd_buffer
),
484 flags
, cmd_buffer
->gfx9_eop_bug_va
);
487 if (unlikely(cmd_buffer
->device
->trace_bo
))
488 radv_cmd_buffer_trace_emit(cmd_buffer
);
492 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
493 struct radv_pipeline
*pipeline
, enum ring_type ring
)
495 struct radv_device
*device
= cmd_buffer
->device
;
496 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
500 va
= radv_buffer_get_va(device
->trace_bo
);
510 assert(!"invalid ring type");
513 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
516 data
[0] = (uintptr_t)pipeline
;
517 data
[1] = (uintptr_t)pipeline
>> 32;
519 radv_emit_write_data_packet(cs
, va
, 2, data
);
522 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
523 VkPipelineBindPoint bind_point
,
524 struct radv_descriptor_set
*set
,
527 struct radv_descriptor_state
*descriptors_state
=
528 radv_get_descriptors_state(cmd_buffer
, bind_point
);
530 descriptors_state
->sets
[idx
] = set
;
532 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
533 descriptors_state
->dirty
|= (1u << idx
);
537 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
538 VkPipelineBindPoint bind_point
)
540 struct radv_descriptor_state
*descriptors_state
=
541 radv_get_descriptors_state(cmd_buffer
, bind_point
);
542 struct radv_device
*device
= cmd_buffer
->device
;
543 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
544 uint32_t data
[MAX_SETS
* 2] = {};
547 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
549 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
550 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
552 for_each_bit(i
, descriptors_state
->valid
) {
553 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
554 data
[i
* 2] = (uintptr_t)set
;
555 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
558 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
561 struct radv_userdata_info
*
562 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
563 gl_shader_stage stage
,
566 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
567 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
571 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
572 struct radv_pipeline
*pipeline
,
573 gl_shader_stage stage
,
574 int idx
, uint64_t va
)
576 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
577 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
578 if (loc
->sgpr_idx
== -1)
581 assert(loc
->num_sgprs
== (HAVE_32BIT_POINTERS
? 1 : 2));
582 assert(!loc
->indirect
);
584 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
585 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
590 struct radv_pipeline
*pipeline
,
591 struct radv_descriptor_state
*descriptors_state
,
592 gl_shader_stage stage
)
594 struct radv_device
*device
= cmd_buffer
->device
;
595 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
596 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
597 struct radv_userdata_locations
*locs
=
598 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
599 unsigned mask
= locs
->descriptor_sets_enabled
;
601 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
606 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
608 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
609 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
611 radv_emit_shader_pointer_head(cs
, sh_offset
, count
,
612 HAVE_32BIT_POINTERS
);
613 for (int i
= 0; i
< count
; i
++) {
614 struct radv_descriptor_set
*set
=
615 descriptors_state
->sets
[start
+ i
];
617 radv_emit_shader_pointer_body(device
, cs
, set
->va
,
618 HAVE_32BIT_POINTERS
);
624 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
625 struct radv_pipeline
*pipeline
)
627 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
628 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
629 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
631 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
632 cmd_buffer
->sample_positions_needed
= true;
634 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
637 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
638 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
639 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
641 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer
->device
->dfsm_allowed
) {
647 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
648 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
653 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
654 struct radv_shader_variant
*shader
)
661 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
663 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
667 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
668 struct radv_pipeline
*pipeline
,
669 bool vertex_stage_only
)
671 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
672 uint32_t mask
= state
->prefetch_L2_mask
;
674 if (vertex_stage_only
) {
675 /* Fast prefetch path for starting draws as soon as possible.
677 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
678 RADV_PREFETCH_VBO_DESCRIPTORS
);
681 if (mask
& RADV_PREFETCH_VS
)
682 radv_emit_shader_prefetch(cmd_buffer
,
683 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
685 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
686 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
688 if (mask
& RADV_PREFETCH_TCS
)
689 radv_emit_shader_prefetch(cmd_buffer
,
690 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
692 if (mask
& RADV_PREFETCH_TES
)
693 radv_emit_shader_prefetch(cmd_buffer
,
694 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
696 if (mask
& RADV_PREFETCH_GS
) {
697 radv_emit_shader_prefetch(cmd_buffer
,
698 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
699 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
702 if (mask
& RADV_PREFETCH_PS
)
703 radv_emit_shader_prefetch(cmd_buffer
,
704 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
706 state
->prefetch_L2_mask
&= ~mask
;
710 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
712 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
715 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
716 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
717 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
719 unsigned sx_ps_downconvert
= 0;
720 unsigned sx_blend_opt_epsilon
= 0;
721 unsigned sx_blend_opt_control
= 0;
723 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
724 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
727 int idx
= subpass
->color_attachments
[i
].attachment
;
728 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
730 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
731 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
732 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
733 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
735 bool has_alpha
, has_rgb
;
737 /* Set if RGB and A are present. */
738 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
740 if (format
== V_028C70_COLOR_8
||
741 format
== V_028C70_COLOR_16
||
742 format
== V_028C70_COLOR_32
)
743 has_rgb
= !has_alpha
;
747 /* Check the colormask and export format. */
748 if (!(colormask
& 0x7))
750 if (!(colormask
& 0x8))
753 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
758 /* Disable value checking for disabled channels. */
760 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
762 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
764 /* Enable down-conversion for 32bpp and smaller formats. */
766 case V_028C70_COLOR_8
:
767 case V_028C70_COLOR_8_8
:
768 case V_028C70_COLOR_8_8_8_8
:
769 /* For 1 and 2-channel formats, use the superset thereof. */
770 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
771 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
772 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
773 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
774 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
778 case V_028C70_COLOR_5_6_5
:
779 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
780 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
781 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
785 case V_028C70_COLOR_1_5_5_5
:
786 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
787 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
788 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
792 case V_028C70_COLOR_4_4_4_4
:
793 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
794 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
795 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
799 case V_028C70_COLOR_32
:
800 if (swap
== V_028C70_SWAP_STD
&&
801 spi_format
== V_028714_SPI_SHADER_32_R
)
802 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
803 else if (swap
== V_028C70_SWAP_ALT_REV
&&
804 spi_format
== V_028714_SPI_SHADER_32_AR
)
805 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
808 case V_028C70_COLOR_16
:
809 case V_028C70_COLOR_16_16
:
810 /* For 1-channel formats, use the superset thereof. */
811 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
812 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
813 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
814 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
815 if (swap
== V_028C70_SWAP_STD
||
816 swap
== V_028C70_SWAP_STD_REV
)
817 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
819 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
823 case V_028C70_COLOR_10_11_11
:
824 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
825 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
826 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
830 case V_028C70_COLOR_2_10_10_10
:
831 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
832 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
833 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
839 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
840 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
841 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
842 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
846 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
848 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
850 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
853 radv_update_multisample_state(cmd_buffer
, pipeline
);
855 cmd_buffer
->scratch_size_needed
=
856 MAX2(cmd_buffer
->scratch_size_needed
,
857 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
859 if (!cmd_buffer
->state
.emitted_pipeline
||
860 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
861 pipeline
->graphics
.can_use_guardband
)
862 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
864 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
866 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
867 if (!pipeline
->shaders
[i
])
870 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
871 pipeline
->shaders
[i
]->bo
);
874 if (radv_pipeline_has_gs(pipeline
))
875 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
876 pipeline
->gs_copy_shader
->bo
);
878 if (unlikely(cmd_buffer
->device
->trace_bo
))
879 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
881 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
883 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
887 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
889 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
890 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
894 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
896 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
898 si_write_scissors(cmd_buffer
->cs
, 0, count
,
899 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
900 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
901 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
905 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
907 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
910 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
911 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
912 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
913 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
914 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
915 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
916 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
921 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
923 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
925 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
926 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
930 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
932 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
934 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
935 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
939 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
941 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
943 radeon_set_context_reg_seq(cmd_buffer
->cs
,
944 R_028430_DB_STENCILREFMASK
, 2);
945 radeon_emit(cmd_buffer
->cs
,
946 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
947 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
948 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
949 S_028430_STENCILOPVAL(1));
950 radeon_emit(cmd_buffer
->cs
,
951 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
952 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
953 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
954 S_028434_STENCILOPVAL_BF(1));
958 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
960 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
962 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
963 fui(d
->depth_bounds
.min
));
964 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
965 fui(d
->depth_bounds
.max
));
969 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
971 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
972 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
973 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
976 radeon_set_context_reg_seq(cmd_buffer
->cs
,
977 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
978 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
979 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
980 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
981 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
982 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
986 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
988 struct radv_attachment_info
*att
,
989 struct radv_image
*image
,
990 VkImageLayout layout
)
992 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
993 struct radv_color_buffer_info
*cb
= &att
->cb
;
994 uint32_t cb_color_info
= cb
->cb_color_info
;
996 if (!radv_layout_dcc_compressed(image
, layout
,
997 radv_image_queue_family_mask(image
,
998 cmd_buffer
->queue_family_index
,
999 cmd_buffer
->queue_family_index
))) {
1000 cb_color_info
&= C_028C70_DCC_ENABLE
;
1003 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1004 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1005 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1006 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1007 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1008 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1009 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1010 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1011 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1012 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1013 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1014 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1015 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1017 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1018 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1019 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1021 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1022 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1024 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1025 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1026 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1027 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1028 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1029 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1030 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1031 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1032 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1033 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1034 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1035 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1037 if (is_vi
) { /* DCC BASE */
1038 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1044 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1045 struct radv_ds_buffer_info
*ds
,
1046 struct radv_image
*image
, VkImageLayout layout
,
1047 bool requires_cond_write
)
1049 uint32_t db_z_info
= ds
->db_z_info
;
1050 uint32_t db_z_info_reg
;
1052 if (!radv_image_is_tc_compat_htile(image
))
1055 if (!radv_layout_has_htile(image
, layout
,
1056 radv_image_queue_family_mask(image
,
1057 cmd_buffer
->queue_family_index
,
1058 cmd_buffer
->queue_family_index
))) {
1059 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1062 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1064 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1065 db_z_info_reg
= R_028038_DB_Z_INFO
;
1067 db_z_info_reg
= R_028040_DB_Z_INFO
;
1070 /* When we don't know the last fast clear value we need to emit a
1071 * conditional packet, otherwise we can update DB_Z_INFO directly.
1073 if (requires_cond_write
) {
1074 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_WRITE
, 7, 0));
1076 const uint32_t write_space
= 0 << 8; /* register */
1077 const uint32_t poll_space
= 1 << 4; /* memory */
1078 const uint32_t function
= 3 << 0; /* equal to the reference */
1079 const uint32_t options
= write_space
| poll_space
| function
;
1080 radeon_emit(cmd_buffer
->cs
, options
);
1082 /* poll address - location of the depth clear value */
1083 uint64_t va
= radv_buffer_get_va(image
->bo
);
1084 va
+= image
->offset
+ image
->clear_value_offset
;
1086 /* In presence of stencil format, we have to adjust the base
1087 * address because the first value is the stencil clear value.
1089 if (vk_format_is_stencil(image
->vk_format
))
1092 radeon_emit(cmd_buffer
->cs
, va
);
1093 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1095 radeon_emit(cmd_buffer
->cs
, fui(0.0f
)); /* reference value */
1096 radeon_emit(cmd_buffer
->cs
, (uint32_t)-1); /* comparison mask */
1097 radeon_emit(cmd_buffer
->cs
, db_z_info_reg
>> 2); /* write address low */
1098 radeon_emit(cmd_buffer
->cs
, 0u); /* write address high */
1099 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1101 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1106 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1107 struct radv_ds_buffer_info
*ds
,
1108 struct radv_image
*image
,
1109 VkImageLayout layout
)
1111 uint32_t db_z_info
= ds
->db_z_info
;
1112 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1114 if (!radv_layout_has_htile(image
, layout
,
1115 radv_image_queue_family_mask(image
,
1116 cmd_buffer
->queue_family_index
,
1117 cmd_buffer
->queue_family_index
))) {
1118 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1119 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1122 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1123 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1126 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1127 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1128 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1129 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1130 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1132 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1133 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1134 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1135 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1136 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1137 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1138 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1139 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1140 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1141 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1142 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1144 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1145 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1146 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1148 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1150 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1151 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1152 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1153 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1156 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1157 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1158 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1159 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1163 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1164 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1166 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1167 ds
->pa_su_poly_offset_db_fmt_cntl
);
1171 * Update the fast clear depth/stencil values if the image is bound as a
1172 * depth/stencil buffer.
1175 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1176 struct radv_image
*image
,
1177 VkClearDepthStencilValue ds_clear_value
,
1178 VkImageAspectFlags aspects
)
1180 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1181 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1182 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1183 struct radv_attachment_info
*att
;
1186 if (!framebuffer
|| !subpass
)
1189 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1190 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1193 att
= &framebuffer
->attachments
[att_idx
];
1194 if (att
->attachment
->image
!= image
)
1197 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1198 radeon_emit(cs
, ds_clear_value
.stencil
);
1199 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1201 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1202 * only needed when clearing Z to 0.0.
1204 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1205 ds_clear_value
.depth
== 0.0) {
1206 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1208 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1214 * Set the clear depth/stencil values to the image's metadata.
1217 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1218 struct radv_image
*image
,
1219 VkClearDepthStencilValue ds_clear_value
,
1220 VkImageAspectFlags aspects
)
1222 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1223 uint64_t va
= radv_buffer_get_va(image
->bo
);
1224 unsigned reg_offset
= 0, reg_count
= 0;
1226 va
+= image
->offset
+ image
->clear_value_offset
;
1228 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1234 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1237 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1238 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1239 S_370_WR_CONFIRM(1) |
1240 S_370_ENGINE_SEL(V_370_PFP
));
1241 radeon_emit(cs
, va
);
1242 radeon_emit(cs
, va
>> 32);
1243 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1244 radeon_emit(cs
, ds_clear_value
.stencil
);
1245 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1246 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1250 * Update the clear depth/stencil values for this image.
1253 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1254 struct radv_image
*image
,
1255 VkClearDepthStencilValue ds_clear_value
,
1256 VkImageAspectFlags aspects
)
1258 assert(radv_image_has_htile(image
));
1260 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1262 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1267 * Load the clear depth/stencil values from the image's metadata.
1270 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1271 struct radv_image
*image
)
1273 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1274 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1275 uint64_t va
= radv_buffer_get_va(image
->bo
);
1276 unsigned reg_offset
= 0, reg_count
= 0;
1278 va
+= image
->offset
+ image
->clear_value_offset
;
1280 if (!radv_image_has_htile(image
))
1283 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1289 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1292 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1293 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1294 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1295 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1296 radeon_emit(cs
, va
);
1297 radeon_emit(cs
, va
>> 32);
1298 radeon_emit(cs
, (R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
) >> 2);
1301 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1306 * With DCC some colors don't require CMASK elimination before being
1307 * used as a texture. This sets a predicate value to determine if the
1308 * cmask eliminate is required.
1311 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1312 struct radv_image
*image
,
1315 uint64_t pred_val
= value
;
1316 uint64_t va
= radv_buffer_get_va(image
->bo
);
1317 va
+= image
->offset
+ image
->dcc_pred_offset
;
1319 assert(radv_image_has_dcc(image
));
1321 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1322 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1323 S_370_WR_CONFIRM(1) |
1324 S_370_ENGINE_SEL(V_370_PFP
));
1325 radeon_emit(cmd_buffer
->cs
, va
);
1326 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1327 radeon_emit(cmd_buffer
->cs
, pred_val
);
1328 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1332 * Update the fast clear color values if the image is bound as a color buffer.
1335 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1336 struct radv_image
*image
,
1338 uint32_t color_values
[2])
1340 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1341 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1342 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1343 struct radv_attachment_info
*att
;
1346 if (!framebuffer
|| !subpass
)
1349 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1350 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1353 att
= &framebuffer
->attachments
[att_idx
];
1354 if (att
->attachment
->image
!= image
)
1357 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1358 radeon_emit(cs
, color_values
[0]);
1359 radeon_emit(cs
, color_values
[1]);
1363 * Set the clear color values to the image's metadata.
1366 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1367 struct radv_image
*image
,
1368 uint32_t color_values
[2])
1370 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1371 uint64_t va
= radv_buffer_get_va(image
->bo
);
1373 va
+= image
->offset
+ image
->clear_value_offset
;
1375 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1377 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1378 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1379 S_370_WR_CONFIRM(1) |
1380 S_370_ENGINE_SEL(V_370_PFP
));
1381 radeon_emit(cs
, va
);
1382 radeon_emit(cs
, va
>> 32);
1383 radeon_emit(cs
, color_values
[0]);
1384 radeon_emit(cs
, color_values
[1]);
1388 * Update the clear color values for this image.
1391 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1392 struct radv_image
*image
,
1394 uint32_t color_values
[2])
1396 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1398 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1400 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1405 * Load the clear color values from the image's metadata.
1408 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1409 struct radv_image
*image
,
1412 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1413 uint64_t va
= radv_buffer_get_va(image
->bo
);
1415 va
+= image
->offset
+ image
->clear_value_offset
;
1417 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1420 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1422 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1423 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1424 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1425 COPY_DATA_COUNT_SEL
);
1426 radeon_emit(cs
, va
);
1427 radeon_emit(cs
, va
>> 32);
1428 radeon_emit(cs
, reg
>> 2);
1431 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1436 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1439 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1440 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1442 /* this may happen for inherited secondary recording */
1446 for (i
= 0; i
< 8; ++i
) {
1447 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1448 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1449 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1453 int idx
= subpass
->color_attachments
[i
].attachment
;
1454 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1455 struct radv_image
*image
= att
->attachment
->image
;
1456 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1458 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1460 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1461 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1463 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1466 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1467 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1468 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1469 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1470 struct radv_image
*image
= att
->attachment
->image
;
1471 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1472 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1473 cmd_buffer
->queue_family_index
,
1474 cmd_buffer
->queue_family_index
);
1475 /* We currently don't support writing decompressed HTILE */
1476 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1477 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1479 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1481 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1482 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1483 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1485 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1487 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1488 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1490 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1492 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1495 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1496 S_028208_BR_X(framebuffer
->width
) |
1497 S_028208_BR_Y(framebuffer
->height
));
1499 if (cmd_buffer
->device
->dfsm_allowed
) {
1500 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1501 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1504 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1508 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1510 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1511 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1513 if (state
->index_type
!= state
->last_index_type
) {
1514 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1515 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1516 2, state
->index_type
);
1518 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1519 radeon_emit(cs
, state
->index_type
);
1522 state
->last_index_type
= state
->index_type
;
1525 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1526 radeon_emit(cs
, state
->index_va
);
1527 radeon_emit(cs
, state
->index_va
>> 32);
1529 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1530 radeon_emit(cs
, state
->max_index_count
);
1532 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1535 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1537 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1538 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1539 uint32_t pa_sc_mode_cntl_1
=
1540 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1541 uint32_t db_count_control
;
1543 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1544 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1545 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1546 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1547 has_perfect_queries
) {
1548 /* Re-enable out-of-order rasterization if the
1549 * bound pipeline supports it and if it's has
1550 * been disabled before starting any perfect
1551 * occlusion queries.
1553 radeon_set_context_reg(cmd_buffer
->cs
,
1554 R_028A4C_PA_SC_MODE_CNTL_1
,
1557 db_count_control
= 0;
1559 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1562 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1563 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1565 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1567 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1568 S_028004_SAMPLE_RATE(sample_rate
) |
1569 S_028004_ZPASS_ENABLE(1) |
1570 S_028004_SLICE_EVEN_ENABLE(1) |
1571 S_028004_SLICE_ODD_ENABLE(1);
1573 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1574 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1575 has_perfect_queries
) {
1576 /* If the bound pipeline has enabled
1577 * out-of-order rasterization, we should
1578 * disable it before starting any perfect
1579 * occlusion queries.
1581 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1583 radeon_set_context_reg(cmd_buffer
->cs
,
1584 R_028A4C_PA_SC_MODE_CNTL_1
,
1588 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1589 S_028004_SAMPLE_RATE(sample_rate
);
1593 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1597 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1599 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1601 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1602 radv_emit_viewport(cmd_buffer
);
1604 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1605 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1606 radv_emit_scissor(cmd_buffer
);
1608 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1609 radv_emit_line_width(cmd_buffer
);
1611 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1612 radv_emit_blend_constants(cmd_buffer
);
1614 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1615 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1616 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1617 radv_emit_stencil(cmd_buffer
);
1619 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1620 radv_emit_depth_bounds(cmd_buffer
);
1622 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1623 radv_emit_depth_bias(cmd_buffer
);
1625 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1626 radv_emit_discard_rectangle(cmd_buffer
);
1628 cmd_buffer
->state
.dirty
&= ~states
;
1632 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1633 VkPipelineBindPoint bind_point
)
1635 struct radv_descriptor_state
*descriptors_state
=
1636 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1637 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1640 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1645 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1646 set
->va
+= bo_offset
;
1650 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1651 VkPipelineBindPoint bind_point
)
1653 struct radv_descriptor_state
*descriptors_state
=
1654 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1655 uint32_t size
= MAX_SETS
* 2 * 4;
1659 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1660 256, &offset
, &ptr
))
1663 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1664 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1665 uint64_t set_va
= 0;
1666 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1667 if (descriptors_state
->valid
& (1u << i
))
1669 uptr
[0] = set_va
& 0xffffffff;
1670 uptr
[1] = set_va
>> 32;
1673 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1676 if (cmd_buffer
->state
.pipeline
) {
1677 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1678 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1681 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1682 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1685 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1686 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1689 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1690 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1693 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1694 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1698 if (cmd_buffer
->state
.compute_pipeline
)
1699 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1704 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1705 VkShaderStageFlags stages
)
1707 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1708 VK_PIPELINE_BIND_POINT_COMPUTE
:
1709 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1710 struct radv_descriptor_state
*descriptors_state
=
1711 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1713 if (!descriptors_state
->dirty
)
1716 if (descriptors_state
->push_dirty
)
1717 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1719 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1720 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1721 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1724 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1726 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1728 if (cmd_buffer
->state
.pipeline
) {
1729 radv_foreach_stage(stage
, stages
) {
1730 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1733 radv_emit_descriptor_pointers(cmd_buffer
,
1734 cmd_buffer
->state
.pipeline
,
1735 descriptors_state
, stage
);
1739 if (cmd_buffer
->state
.compute_pipeline
&&
1740 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1741 radv_emit_descriptor_pointers(cmd_buffer
,
1742 cmd_buffer
->state
.compute_pipeline
,
1744 MESA_SHADER_COMPUTE
);
1747 descriptors_state
->dirty
= 0;
1748 descriptors_state
->push_dirty
= false;
1750 if (unlikely(cmd_buffer
->device
->trace_bo
))
1751 radv_save_descriptors(cmd_buffer
, bind_point
);
1753 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1757 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1758 VkShaderStageFlags stages
)
1760 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1761 ? cmd_buffer
->state
.compute_pipeline
1762 : cmd_buffer
->state
.pipeline
;
1763 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1764 VK_PIPELINE_BIND_POINT_COMPUTE
:
1765 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1766 struct radv_descriptor_state
*descriptors_state
=
1767 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1768 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1769 struct radv_shader_variant
*shader
, *prev_shader
;
1774 stages
&= cmd_buffer
->push_constant_stages
;
1776 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1779 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1780 16 * layout
->dynamic_offset_count
,
1781 256, &offset
, &ptr
))
1784 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1785 memcpy((char*)ptr
+ layout
->push_constant_size
,
1786 descriptors_state
->dynamic_buffers
,
1787 16 * layout
->dynamic_offset_count
);
1789 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1792 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1793 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1796 radv_foreach_stage(stage
, stages
) {
1797 shader
= radv_get_shader(pipeline
, stage
);
1799 /* Avoid redundantly emitting the address for merged stages. */
1800 if (shader
&& shader
!= prev_shader
) {
1801 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1802 AC_UD_PUSH_CONSTANTS
, va
);
1804 prev_shader
= shader
;
1808 cmd_buffer
->push_constant_stages
&= ~stages
;
1809 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1813 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1814 bool pipeline_is_dirty
)
1816 if ((pipeline_is_dirty
||
1817 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1818 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1819 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1820 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1824 uint32_t count
= velems
->count
;
1827 /* allocate some descriptor state for vertex buffers */
1828 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1829 &vb_offset
, &vb_ptr
))
1832 for (i
= 0; i
< count
; i
++) {
1833 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1835 int vb
= velems
->binding
[i
];
1836 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1837 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1839 va
= radv_buffer_get_va(buffer
->bo
);
1841 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1842 va
+= offset
+ buffer
->offset
;
1844 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1845 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1846 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1848 desc
[2] = buffer
->size
- offset
;
1849 desc
[3] = velems
->rsrc_word3
[i
];
1852 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1855 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1856 AC_UD_VS_VERTEX_BUFFERS
, va
);
1858 cmd_buffer
->state
.vb_va
= va
;
1859 cmd_buffer
->state
.vb_size
= count
* 16;
1860 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
1862 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1866 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1868 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
1869 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1870 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1874 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1875 bool instanced_draw
, bool indirect_draw
,
1876 uint32_t draw_vertex_count
)
1878 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1879 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1880 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1881 uint32_t ia_multi_vgt_param
;
1882 int32_t primitive_reset_en
;
1885 ia_multi_vgt_param
=
1886 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1887 indirect_draw
, draw_vertex_count
);
1889 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1890 if (info
->chip_class
>= GFX9
) {
1891 radeon_set_uconfig_reg_idx(cs
,
1892 R_030960_IA_MULTI_VGT_PARAM
,
1893 4, ia_multi_vgt_param
);
1894 } else if (info
->chip_class
>= CIK
) {
1895 radeon_set_context_reg_idx(cs
,
1896 R_028AA8_IA_MULTI_VGT_PARAM
,
1897 1, ia_multi_vgt_param
);
1899 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1900 ia_multi_vgt_param
);
1902 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1905 /* Primitive restart. */
1906 primitive_reset_en
=
1907 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1909 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1910 state
->last_primitive_reset_en
= primitive_reset_en
;
1911 if (info
->chip_class
>= GFX9
) {
1912 radeon_set_uconfig_reg(cs
,
1913 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1914 primitive_reset_en
);
1916 radeon_set_context_reg(cs
,
1917 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1918 primitive_reset_en
);
1922 if (primitive_reset_en
) {
1923 uint32_t primitive_reset_index
=
1924 state
->index_type
? 0xffffffffu
: 0xffffu
;
1926 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1927 radeon_set_context_reg(cs
,
1928 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1929 primitive_reset_index
);
1930 state
->last_primitive_reset_index
= primitive_reset_index
;
1935 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1936 VkPipelineStageFlags src_stage_mask
)
1938 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1939 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1940 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1941 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1942 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1945 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1946 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1947 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1948 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1949 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1950 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1951 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1952 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1953 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1954 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1955 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1956 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
1957 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1958 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1959 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
)) {
1960 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1964 static enum radv_cmd_flush_bits
1965 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1966 VkAccessFlags src_flags
,
1967 struct radv_image
*image
)
1969 bool flush_CB_meta
= true, flush_DB_meta
= true;
1970 enum radv_cmd_flush_bits flush_bits
= 0;
1973 if (image
&& !radv_image_has_CB_metadata(image
))
1974 flush_CB_meta
= false;
1975 if (image
&& !radv_image_has_htile(image
))
1976 flush_DB_meta
= false;
1978 for_each_bit(b
, src_flags
) {
1979 switch ((VkAccessFlagBits
)(1 << b
)) {
1980 case VK_ACCESS_SHADER_WRITE_BIT
:
1981 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1983 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1984 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
1986 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1988 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1989 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
1991 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1993 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1994 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1995 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1996 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1999 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2001 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2010 static enum radv_cmd_flush_bits
2011 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2012 VkAccessFlags dst_flags
,
2013 struct radv_image
*image
)
2015 enum radv_cmd_flush_bits flush_bits
= 0;
2017 for_each_bit(b
, dst_flags
) {
2018 switch ((VkAccessFlagBits
)(1 << b
)) {
2019 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2020 case VK_ACCESS_INDEX_READ_BIT
:
2022 case VK_ACCESS_UNIFORM_READ_BIT
:
2023 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2025 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2026 case VK_ACCESS_SHADER_READ_BIT
:
2027 case VK_ACCESS_TRANSFER_READ_BIT
:
2028 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2029 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2030 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2032 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2033 /* TODO: change to image && when the image gets passed
2034 * through from the subpass. */
2035 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2036 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2037 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2039 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2040 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2041 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2051 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2053 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2055 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2056 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2060 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2061 struct radv_subpass_attachment att
)
2063 unsigned idx
= att
.attachment
;
2064 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2065 VkImageSubresourceRange range
;
2066 range
.aspectMask
= 0;
2067 range
.baseMipLevel
= view
->base_mip
;
2068 range
.levelCount
= 1;
2069 range
.baseArrayLayer
= view
->base_layer
;
2070 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2072 radv_handle_image_transition(cmd_buffer
,
2074 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2075 att
.layout
, 0, 0, &range
,
2076 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2078 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2084 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2085 const struct radv_subpass
*subpass
, bool transitions
)
2088 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2090 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2091 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2092 radv_handle_subpass_image_transition(cmd_buffer
,
2093 subpass
->color_attachments
[i
]);
2096 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2097 radv_handle_subpass_image_transition(cmd_buffer
,
2098 subpass
->input_attachments
[i
]);
2101 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2102 radv_handle_subpass_image_transition(cmd_buffer
,
2103 subpass
->depth_stencil_attachment
);
2107 cmd_buffer
->state
.subpass
= subpass
;
2109 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2113 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2114 struct radv_render_pass
*pass
,
2115 const VkRenderPassBeginInfo
*info
)
2117 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2119 if (pass
->attachment_count
== 0) {
2120 state
->attachments
= NULL
;
2124 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2125 pass
->attachment_count
*
2126 sizeof(state
->attachments
[0]),
2127 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2128 if (state
->attachments
== NULL
) {
2129 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2130 return cmd_buffer
->record_result
;
2133 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2134 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2135 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2136 VkImageAspectFlags clear_aspects
= 0;
2138 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2139 /* color attachment */
2140 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2141 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2144 /* depthstencil attachment */
2145 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2146 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2147 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2148 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2149 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2150 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2152 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2153 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2154 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2158 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2159 state
->attachments
[i
].cleared_views
= 0;
2160 if (clear_aspects
&& info
) {
2161 assert(info
->clearValueCount
> i
);
2162 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2165 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2171 VkResult
radv_AllocateCommandBuffers(
2173 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2174 VkCommandBuffer
*pCommandBuffers
)
2176 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2177 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2179 VkResult result
= VK_SUCCESS
;
2182 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2184 if (!list_empty(&pool
->free_cmd_buffers
)) {
2185 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2187 list_del(&cmd_buffer
->pool_link
);
2188 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2190 result
= radv_reset_cmd_buffer(cmd_buffer
);
2191 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2192 cmd_buffer
->level
= pAllocateInfo
->level
;
2194 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2196 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2197 &pCommandBuffers
[i
]);
2199 if (result
!= VK_SUCCESS
)
2203 if (result
!= VK_SUCCESS
) {
2204 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2205 i
, pCommandBuffers
);
2207 /* From the Vulkan 1.0.66 spec:
2209 * "vkAllocateCommandBuffers can be used to create multiple
2210 * command buffers. If the creation of any of those command
2211 * buffers fails, the implementation must destroy all
2212 * successfully created command buffer objects from this
2213 * command, set all entries of the pCommandBuffers array to
2214 * NULL and return the error."
2216 memset(pCommandBuffers
, 0,
2217 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2223 void radv_FreeCommandBuffers(
2225 VkCommandPool commandPool
,
2226 uint32_t commandBufferCount
,
2227 const VkCommandBuffer
*pCommandBuffers
)
2229 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2230 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2233 if (cmd_buffer
->pool
) {
2234 list_del(&cmd_buffer
->pool_link
);
2235 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2237 radv_cmd_buffer_destroy(cmd_buffer
);
2243 VkResult
radv_ResetCommandBuffer(
2244 VkCommandBuffer commandBuffer
,
2245 VkCommandBufferResetFlags flags
)
2247 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2248 return radv_reset_cmd_buffer(cmd_buffer
);
2251 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2253 struct radv_device
*device
= cmd_buffer
->device
;
2254 if (device
->gfx_init
) {
2255 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2256 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, device
->gfx_init
);
2257 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2258 radeon_emit(cmd_buffer
->cs
, va
);
2259 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2260 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2262 si_init_config(cmd_buffer
);
2265 VkResult
radv_BeginCommandBuffer(
2266 VkCommandBuffer commandBuffer
,
2267 const VkCommandBufferBeginInfo
*pBeginInfo
)
2269 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2270 VkResult result
= VK_SUCCESS
;
2272 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2273 /* If the command buffer has already been resetted with
2274 * vkResetCommandBuffer, no need to do it again.
2276 result
= radv_reset_cmd_buffer(cmd_buffer
);
2277 if (result
!= VK_SUCCESS
)
2281 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2282 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2283 cmd_buffer
->state
.last_index_type
= -1;
2284 cmd_buffer
->state
.last_num_instances
= -1;
2285 cmd_buffer
->state
.last_vertex_offset
= -1;
2286 cmd_buffer
->state
.last_first_instance
= -1;
2287 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2289 /* setup initial configuration into command buffer */
2290 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2291 switch (cmd_buffer
->queue_family_index
) {
2292 case RADV_QUEUE_GENERAL
:
2293 emit_gfx_buffer_state(cmd_buffer
);
2295 case RADV_QUEUE_COMPUTE
:
2296 si_init_compute(cmd_buffer
);
2298 case RADV_QUEUE_TRANSFER
:
2304 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2305 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2306 assert(pBeginInfo
->pInheritanceInfo
);
2307 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2308 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2310 struct radv_subpass
*subpass
=
2311 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2313 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2314 if (result
!= VK_SUCCESS
)
2317 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2320 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2321 struct radv_device
*device
= cmd_buffer
->device
;
2323 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2326 radv_cmd_buffer_trace_emit(cmd_buffer
);
2329 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2334 void radv_CmdBindVertexBuffers(
2335 VkCommandBuffer commandBuffer
,
2336 uint32_t firstBinding
,
2337 uint32_t bindingCount
,
2338 const VkBuffer
* pBuffers
,
2339 const VkDeviceSize
* pOffsets
)
2341 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2342 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2343 bool changed
= false;
2345 /* We have to defer setting up vertex buffer since we need the buffer
2346 * stride from the pipeline. */
2348 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2349 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2350 uint32_t idx
= firstBinding
+ i
;
2353 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2354 vb
[idx
].offset
!= pOffsets
[i
])) {
2358 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2359 vb
[idx
].offset
= pOffsets
[i
];
2361 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2362 vb
[idx
].buffer
->bo
);
2366 /* No state changes. */
2370 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2373 void radv_CmdBindIndexBuffer(
2374 VkCommandBuffer commandBuffer
,
2376 VkDeviceSize offset
,
2377 VkIndexType indexType
)
2379 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2380 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2382 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2383 cmd_buffer
->state
.index_offset
== offset
&&
2384 cmd_buffer
->state
.index_type
== indexType
) {
2385 /* No state changes. */
2389 cmd_buffer
->state
.index_buffer
= index_buffer
;
2390 cmd_buffer
->state
.index_offset
= offset
;
2391 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2392 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2393 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2395 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2396 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2397 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2398 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2403 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2404 VkPipelineBindPoint bind_point
,
2405 struct radv_descriptor_set
*set
, unsigned idx
)
2407 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2409 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2412 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2414 if (!cmd_buffer
->device
->use_global_bo_list
) {
2415 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2416 if (set
->descriptors
[j
])
2417 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2421 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2424 void radv_CmdBindDescriptorSets(
2425 VkCommandBuffer commandBuffer
,
2426 VkPipelineBindPoint pipelineBindPoint
,
2427 VkPipelineLayout _layout
,
2429 uint32_t descriptorSetCount
,
2430 const VkDescriptorSet
* pDescriptorSets
,
2431 uint32_t dynamicOffsetCount
,
2432 const uint32_t* pDynamicOffsets
)
2434 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2435 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2436 unsigned dyn_idx
= 0;
2438 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2439 struct radv_descriptor_state
*descriptors_state
=
2440 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2442 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2443 unsigned idx
= i
+ firstSet
;
2444 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2445 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2447 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2448 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2449 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2450 assert(dyn_idx
< dynamicOffsetCount
);
2452 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2453 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2455 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2456 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2457 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2458 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2459 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2460 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2461 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2462 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2463 cmd_buffer
->push_constant_stages
|=
2464 set
->layout
->dynamic_shader_stages
;
2469 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2470 struct radv_descriptor_set
*set
,
2471 struct radv_descriptor_set_layout
*layout
,
2472 VkPipelineBindPoint bind_point
)
2474 struct radv_descriptor_state
*descriptors_state
=
2475 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2476 set
->size
= layout
->size
;
2477 set
->layout
= layout
;
2479 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2480 size_t new_size
= MAX2(set
->size
, 1024);
2481 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2482 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2484 free(set
->mapped_ptr
);
2485 set
->mapped_ptr
= malloc(new_size
);
2487 if (!set
->mapped_ptr
) {
2488 descriptors_state
->push_set
.capacity
= 0;
2489 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2493 descriptors_state
->push_set
.capacity
= new_size
;
2499 void radv_meta_push_descriptor_set(
2500 struct radv_cmd_buffer
* cmd_buffer
,
2501 VkPipelineBindPoint pipelineBindPoint
,
2502 VkPipelineLayout _layout
,
2504 uint32_t descriptorWriteCount
,
2505 const VkWriteDescriptorSet
* pDescriptorWrites
)
2507 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2508 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2512 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2514 push_set
->size
= layout
->set
[set
].layout
->size
;
2515 push_set
->layout
= layout
->set
[set
].layout
;
2517 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2519 (void**) &push_set
->mapped_ptr
))
2522 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2523 push_set
->va
+= bo_offset
;
2525 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2526 radv_descriptor_set_to_handle(push_set
),
2527 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2529 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2532 void radv_CmdPushDescriptorSetKHR(
2533 VkCommandBuffer commandBuffer
,
2534 VkPipelineBindPoint pipelineBindPoint
,
2535 VkPipelineLayout _layout
,
2537 uint32_t descriptorWriteCount
,
2538 const VkWriteDescriptorSet
* pDescriptorWrites
)
2540 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2541 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2542 struct radv_descriptor_state
*descriptors_state
=
2543 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2544 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2546 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2548 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2549 layout
->set
[set
].layout
,
2553 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2554 radv_descriptor_set_to_handle(push_set
),
2555 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2557 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2558 descriptors_state
->push_dirty
= true;
2561 void radv_CmdPushDescriptorSetWithTemplateKHR(
2562 VkCommandBuffer commandBuffer
,
2563 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2564 VkPipelineLayout _layout
,
2568 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2569 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2570 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2571 struct radv_descriptor_state
*descriptors_state
=
2572 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2573 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2575 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2577 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2578 layout
->set
[set
].layout
,
2582 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2583 descriptorUpdateTemplate
, pData
);
2585 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2586 descriptors_state
->push_dirty
= true;
2589 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2590 VkPipelineLayout layout
,
2591 VkShaderStageFlags stageFlags
,
2594 const void* pValues
)
2596 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2597 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2598 cmd_buffer
->push_constant_stages
|= stageFlags
;
2601 VkResult
radv_EndCommandBuffer(
2602 VkCommandBuffer commandBuffer
)
2604 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2606 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2607 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2608 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2609 si_emit_cache_flush(cmd_buffer
);
2612 /* Make sure CP DMA is idle at the end of IBs because the kernel
2613 * doesn't wait for it.
2615 si_cp_dma_wait_for_idle(cmd_buffer
);
2617 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2619 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2620 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2622 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2624 return cmd_buffer
->record_result
;
2628 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2630 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2632 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2635 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2637 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2638 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2640 cmd_buffer
->compute_scratch_size_needed
=
2641 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2642 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2644 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2645 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2647 if (unlikely(cmd_buffer
->device
->trace_bo
))
2648 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2651 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2652 VkPipelineBindPoint bind_point
)
2654 struct radv_descriptor_state
*descriptors_state
=
2655 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2657 descriptors_state
->dirty
|= descriptors_state
->valid
;
2660 void radv_CmdBindPipeline(
2661 VkCommandBuffer commandBuffer
,
2662 VkPipelineBindPoint pipelineBindPoint
,
2663 VkPipeline _pipeline
)
2665 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2666 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2668 switch (pipelineBindPoint
) {
2669 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2670 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2672 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2674 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2675 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2677 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2678 if (cmd_buffer
->state
.pipeline
== pipeline
)
2680 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2682 cmd_buffer
->state
.pipeline
= pipeline
;
2686 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2687 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2689 /* the new vertex shader might not have the same user regs */
2690 cmd_buffer
->state
.last_first_instance
= -1;
2691 cmd_buffer
->state
.last_vertex_offset
= -1;
2693 /* Prefetch all pipeline shaders at first draw time. */
2694 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
2696 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2698 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2699 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2700 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2701 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2703 if (radv_pipeline_has_tess(pipeline
))
2704 cmd_buffer
->tess_rings_needed
= true;
2707 assert(!"invalid bind point");
2712 void radv_CmdSetViewport(
2713 VkCommandBuffer commandBuffer
,
2714 uint32_t firstViewport
,
2715 uint32_t viewportCount
,
2716 const VkViewport
* pViewports
)
2718 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2719 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2720 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2722 assert(firstViewport
< MAX_VIEWPORTS
);
2723 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2725 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
2726 viewportCount
* sizeof(*pViewports
));
2728 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2731 void radv_CmdSetScissor(
2732 VkCommandBuffer commandBuffer
,
2733 uint32_t firstScissor
,
2734 uint32_t scissorCount
,
2735 const VkRect2D
* pScissors
)
2737 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2738 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2739 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2741 assert(firstScissor
< MAX_SCISSORS
);
2742 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2744 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
2745 scissorCount
* sizeof(*pScissors
));
2747 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2750 void radv_CmdSetLineWidth(
2751 VkCommandBuffer commandBuffer
,
2754 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2755 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2756 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2759 void radv_CmdSetDepthBias(
2760 VkCommandBuffer commandBuffer
,
2761 float depthBiasConstantFactor
,
2762 float depthBiasClamp
,
2763 float depthBiasSlopeFactor
)
2765 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2767 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2768 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2769 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2771 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2774 void radv_CmdSetBlendConstants(
2775 VkCommandBuffer commandBuffer
,
2776 const float blendConstants
[4])
2778 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2780 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2781 blendConstants
, sizeof(float) * 4);
2783 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2786 void radv_CmdSetDepthBounds(
2787 VkCommandBuffer commandBuffer
,
2788 float minDepthBounds
,
2789 float maxDepthBounds
)
2791 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2793 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2794 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2796 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2799 void radv_CmdSetStencilCompareMask(
2800 VkCommandBuffer commandBuffer
,
2801 VkStencilFaceFlags faceMask
,
2802 uint32_t compareMask
)
2804 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2806 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2807 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2808 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2809 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2811 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2814 void radv_CmdSetStencilWriteMask(
2815 VkCommandBuffer commandBuffer
,
2816 VkStencilFaceFlags faceMask
,
2819 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2821 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2822 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2823 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2824 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2826 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2829 void radv_CmdSetStencilReference(
2830 VkCommandBuffer commandBuffer
,
2831 VkStencilFaceFlags faceMask
,
2834 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2836 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2837 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2838 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2839 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2841 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2844 void radv_CmdSetDiscardRectangleEXT(
2845 VkCommandBuffer commandBuffer
,
2846 uint32_t firstDiscardRectangle
,
2847 uint32_t discardRectangleCount
,
2848 const VkRect2D
* pDiscardRectangles
)
2850 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2851 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2852 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
2854 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
2855 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
2857 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
2858 pDiscardRectangles
, discardRectangleCount
);
2860 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
2863 void radv_CmdExecuteCommands(
2864 VkCommandBuffer commandBuffer
,
2865 uint32_t commandBufferCount
,
2866 const VkCommandBuffer
* pCmdBuffers
)
2868 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2870 assert(commandBufferCount
> 0);
2872 /* Emit pending flushes on primary prior to executing secondary */
2873 si_emit_cache_flush(primary
);
2875 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2876 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2878 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2879 secondary
->scratch_size_needed
);
2880 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2881 secondary
->compute_scratch_size_needed
);
2883 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2884 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2885 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2886 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2887 if (secondary
->tess_rings_needed
)
2888 primary
->tess_rings_needed
= true;
2889 if (secondary
->sample_positions_needed
)
2890 primary
->sample_positions_needed
= true;
2892 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2895 /* When the secondary command buffer is compute only we don't
2896 * need to re-emit the current graphics pipeline.
2898 if (secondary
->state
.emitted_pipeline
) {
2899 primary
->state
.emitted_pipeline
=
2900 secondary
->state
.emitted_pipeline
;
2903 /* When the secondary command buffer is graphics only we don't
2904 * need to re-emit the current compute pipeline.
2906 if (secondary
->state
.emitted_compute_pipeline
) {
2907 primary
->state
.emitted_compute_pipeline
=
2908 secondary
->state
.emitted_compute_pipeline
;
2911 /* Only re-emit the draw packets when needed. */
2912 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2913 primary
->state
.last_primitive_reset_en
=
2914 secondary
->state
.last_primitive_reset_en
;
2917 if (secondary
->state
.last_primitive_reset_index
) {
2918 primary
->state
.last_primitive_reset_index
=
2919 secondary
->state
.last_primitive_reset_index
;
2922 if (secondary
->state
.last_ia_multi_vgt_param
) {
2923 primary
->state
.last_ia_multi_vgt_param
=
2924 secondary
->state
.last_ia_multi_vgt_param
;
2927 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
2928 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
2929 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
2931 if (secondary
->state
.last_index_type
!= -1) {
2932 primary
->state
.last_index_type
=
2933 secondary
->state
.last_index_type
;
2937 /* After executing commands from secondary buffers we have to dirty
2940 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2941 RADV_CMD_DIRTY_INDEX_BUFFER
|
2942 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2943 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
2944 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
2947 VkResult
radv_CreateCommandPool(
2949 const VkCommandPoolCreateInfo
* pCreateInfo
,
2950 const VkAllocationCallbacks
* pAllocator
,
2951 VkCommandPool
* pCmdPool
)
2953 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2954 struct radv_cmd_pool
*pool
;
2956 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2957 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2959 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2962 pool
->alloc
= *pAllocator
;
2964 pool
->alloc
= device
->alloc
;
2966 list_inithead(&pool
->cmd_buffers
);
2967 list_inithead(&pool
->free_cmd_buffers
);
2969 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2971 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2977 void radv_DestroyCommandPool(
2979 VkCommandPool commandPool
,
2980 const VkAllocationCallbacks
* pAllocator
)
2982 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2983 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2988 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2989 &pool
->cmd_buffers
, pool_link
) {
2990 radv_cmd_buffer_destroy(cmd_buffer
);
2993 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2994 &pool
->free_cmd_buffers
, pool_link
) {
2995 radv_cmd_buffer_destroy(cmd_buffer
);
2998 vk_free2(&device
->alloc
, pAllocator
, pool
);
3001 VkResult
radv_ResetCommandPool(
3003 VkCommandPool commandPool
,
3004 VkCommandPoolResetFlags flags
)
3006 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3009 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3010 &pool
->cmd_buffers
, pool_link
) {
3011 result
= radv_reset_cmd_buffer(cmd_buffer
);
3012 if (result
!= VK_SUCCESS
)
3019 void radv_TrimCommandPool(
3021 VkCommandPool commandPool
,
3022 VkCommandPoolTrimFlagsKHR flags
)
3024 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3029 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3030 &pool
->free_cmd_buffers
, pool_link
) {
3031 radv_cmd_buffer_destroy(cmd_buffer
);
3035 void radv_CmdBeginRenderPass(
3036 VkCommandBuffer commandBuffer
,
3037 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3038 VkSubpassContents contents
)
3040 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3041 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3042 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3044 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3045 cmd_buffer
->cs
, 2048);
3046 MAYBE_UNUSED VkResult result
;
3048 cmd_buffer
->state
.framebuffer
= framebuffer
;
3049 cmd_buffer
->state
.pass
= pass
;
3050 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3052 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3053 if (result
!= VK_SUCCESS
)
3056 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3057 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3059 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3062 void radv_CmdBeginRenderPass2KHR(
3063 VkCommandBuffer commandBuffer
,
3064 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3065 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3067 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3068 pSubpassBeginInfo
->contents
);
3071 void radv_CmdNextSubpass(
3072 VkCommandBuffer commandBuffer
,
3073 VkSubpassContents contents
)
3075 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3077 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3079 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3082 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3083 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3086 void radv_CmdNextSubpass2KHR(
3087 VkCommandBuffer commandBuffer
,
3088 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3089 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3091 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3094 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3096 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3097 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3098 if (!radv_get_shader(pipeline
, stage
))
3101 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3102 if (loc
->sgpr_idx
== -1)
3104 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3105 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3108 if (pipeline
->gs_copy_shader
) {
3109 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3110 if (loc
->sgpr_idx
!= -1) {
3111 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3112 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3118 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3119 uint32_t vertex_count
)
3121 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3122 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3123 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3124 S_0287F0_USE_OPAQUE(0));
3128 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3130 uint32_t index_count
)
3132 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
3133 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3134 radeon_emit(cmd_buffer
->cs
, index_va
);
3135 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3136 radeon_emit(cmd_buffer
->cs
, index_count
);
3137 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3141 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3143 uint32_t draw_count
,
3147 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3148 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3149 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3150 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3151 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3154 /* just reset draw state for vertex data */
3155 cmd_buffer
->state
.last_first_instance
= -1;
3156 cmd_buffer
->state
.last_num_instances
= -1;
3157 cmd_buffer
->state
.last_vertex_offset
= -1;
3159 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3160 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3161 PKT3_DRAW_INDIRECT
, 3, false));
3163 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3164 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3165 radeon_emit(cs
, di_src_sel
);
3167 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3168 PKT3_DRAW_INDIRECT_MULTI
,
3171 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3172 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3173 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3174 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3175 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3176 radeon_emit(cs
, draw_count
); /* count */
3177 radeon_emit(cs
, count_va
); /* count_addr */
3178 radeon_emit(cs
, count_va
>> 32);
3179 radeon_emit(cs
, stride
); /* stride */
3180 radeon_emit(cs
, di_src_sel
);
3184 struct radv_draw_info
{
3186 * Number of vertices.
3191 * Index of the first vertex.
3193 int32_t vertex_offset
;
3196 * First instance id.
3198 uint32_t first_instance
;
3201 * Number of instances.
3203 uint32_t instance_count
;
3206 * First index (indexed draws only).
3208 uint32_t first_index
;
3211 * Whether it's an indexed draw.
3216 * Indirect draw parameters resource.
3218 struct radv_buffer
*indirect
;
3219 uint64_t indirect_offset
;
3223 * Draw count parameters resource.
3225 struct radv_buffer
*count_buffer
;
3226 uint64_t count_buffer_offset
;
3230 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3231 const struct radv_draw_info
*info
)
3233 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3234 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3235 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3237 if (info
->indirect
) {
3238 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3239 uint64_t count_va
= 0;
3241 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3243 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3245 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3247 radeon_emit(cs
, va
);
3248 radeon_emit(cs
, va
>> 32);
3250 if (info
->count_buffer
) {
3251 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3252 count_va
+= info
->count_buffer
->offset
+
3253 info
->count_buffer_offset
;
3255 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3258 if (!state
->subpass
->view_mask
) {
3259 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3266 for_each_bit(i
, state
->subpass
->view_mask
) {
3267 radv_emit_view_index(cmd_buffer
, i
);
3269 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3277 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3279 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3280 info
->first_instance
!= state
->last_first_instance
) {
3281 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3282 state
->pipeline
->graphics
.vtx_emit_num
);
3284 radeon_emit(cs
, info
->vertex_offset
);
3285 radeon_emit(cs
, info
->first_instance
);
3286 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3288 state
->last_first_instance
= info
->first_instance
;
3289 state
->last_vertex_offset
= info
->vertex_offset
;
3292 if (state
->last_num_instances
!= info
->instance_count
) {
3293 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3294 radeon_emit(cs
, info
->instance_count
);
3295 state
->last_num_instances
= info
->instance_count
;
3298 if (info
->indexed
) {
3299 int index_size
= state
->index_type
? 4 : 2;
3302 index_va
= state
->index_va
;
3303 index_va
+= info
->first_index
* index_size
;
3305 if (!state
->subpass
->view_mask
) {
3306 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3311 for_each_bit(i
, state
->subpass
->view_mask
) {
3312 radv_emit_view_index(cmd_buffer
, i
);
3314 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3320 if (!state
->subpass
->view_mask
) {
3321 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3324 for_each_bit(i
, state
->subpass
->view_mask
) {
3325 radv_emit_view_index(cmd_buffer
, i
);
3327 radv_cs_emit_draw_packet(cmd_buffer
,
3336 * Vega and raven have a bug which triggers if there are multiple context
3337 * register contexts active at the same time with different scissor values.
3339 * There are two possible workarounds:
3340 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3341 * there is only ever 1 active set of scissor values at the same time.
3343 * 2) Whenever the hardware switches contexts we have to set the scissor
3344 * registers again even if it is a noop. That way the new context gets
3345 * the correct scissor values.
3347 * This implements option 2. radv_need_late_scissor_emission needs to
3348 * return true on affected HW if radv_emit_all_graphics_states sets
3349 * any context registers.
3351 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3354 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3356 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3359 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3361 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3362 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
| RADV_CMD_DIRTY_VERTEX_BUFFER
| RADV_CMD_DIRTY_PIPELINE
);
3364 /* Assume all state changes except these two can imply context rolls. */
3365 if (cmd_buffer
->state
.dirty
& used_states
)
3368 if (cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3371 if (indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3372 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3379 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3380 const struct radv_draw_info
*info
)
3382 bool late_scissor_emission
= radv_need_late_scissor_emission(cmd_buffer
, info
->indexed
);
3384 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3385 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3386 radv_emit_rbplus_state(cmd_buffer
);
3388 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3389 radv_emit_graphics_pipeline(cmd_buffer
);
3391 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3392 radv_emit_framebuffer_state(cmd_buffer
);
3394 if (info
->indexed
) {
3395 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3396 radv_emit_index_buffer(cmd_buffer
);
3398 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3399 * so the state must be re-emitted before the next indexed
3402 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3403 cmd_buffer
->state
.last_index_type
= -1;
3404 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3408 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3410 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3411 info
->instance_count
> 1, info
->indirect
,
3412 info
->indirect
? 0 : info
->count
);
3414 if (late_scissor_emission
)
3415 radv_emit_scissor(cmd_buffer
);
3419 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3420 const struct radv_draw_info
*info
)
3423 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3424 bool pipeline_is_dirty
=
3425 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3426 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3428 MAYBE_UNUSED
unsigned cdw_max
=
3429 radeon_check_space(cmd_buffer
->device
->ws
,
3430 cmd_buffer
->cs
, 4096);
3432 /* Use optimal packet order based on whether we need to sync the
3435 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3436 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3437 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3438 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3439 /* If we have to wait for idle, set all states first, so that
3440 * all SET packets are processed in parallel with previous draw
3441 * calls. Then upload descriptors, set shader pointers, and
3442 * draw, and prefetch at the end. This ensures that the time
3443 * the CUs are idle is very short. (there are only SET_SH
3444 * packets between the wait and the draw)
3446 radv_emit_all_graphics_states(cmd_buffer
, info
);
3447 si_emit_cache_flush(cmd_buffer
);
3448 /* <-- CUs are idle here --> */
3450 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3452 radv_emit_draw_packets(cmd_buffer
, info
);
3453 /* <-- CUs are busy here --> */
3455 /* Start prefetches after the draw has been started. Both will
3456 * run in parallel, but starting the draw first is more
3459 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3460 radv_emit_prefetch_L2(cmd_buffer
,
3461 cmd_buffer
->state
.pipeline
, false);
3464 /* If we don't wait for idle, start prefetches first, then set
3465 * states, and draw at the end.
3467 si_emit_cache_flush(cmd_buffer
);
3469 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3470 /* Only prefetch the vertex shader and VBO descriptors
3471 * in order to start the draw as soon as possible.
3473 radv_emit_prefetch_L2(cmd_buffer
,
3474 cmd_buffer
->state
.pipeline
, true);
3477 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3479 radv_emit_all_graphics_states(cmd_buffer
, info
);
3480 radv_emit_draw_packets(cmd_buffer
, info
);
3482 /* Prefetch the remaining shaders after the draw has been
3485 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3486 radv_emit_prefetch_L2(cmd_buffer
,
3487 cmd_buffer
->state
.pipeline
, false);
3491 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3492 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3496 VkCommandBuffer commandBuffer
,
3497 uint32_t vertexCount
,
3498 uint32_t instanceCount
,
3499 uint32_t firstVertex
,
3500 uint32_t firstInstance
)
3502 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3503 struct radv_draw_info info
= {};
3505 info
.count
= vertexCount
;
3506 info
.instance_count
= instanceCount
;
3507 info
.first_instance
= firstInstance
;
3508 info
.vertex_offset
= firstVertex
;
3510 radv_draw(cmd_buffer
, &info
);
3513 void radv_CmdDrawIndexed(
3514 VkCommandBuffer commandBuffer
,
3515 uint32_t indexCount
,
3516 uint32_t instanceCount
,
3517 uint32_t firstIndex
,
3518 int32_t vertexOffset
,
3519 uint32_t firstInstance
)
3521 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3522 struct radv_draw_info info
= {};
3524 info
.indexed
= true;
3525 info
.count
= indexCount
;
3526 info
.instance_count
= instanceCount
;
3527 info
.first_index
= firstIndex
;
3528 info
.vertex_offset
= vertexOffset
;
3529 info
.first_instance
= firstInstance
;
3531 radv_draw(cmd_buffer
, &info
);
3534 void radv_CmdDrawIndirect(
3535 VkCommandBuffer commandBuffer
,
3537 VkDeviceSize offset
,
3541 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3542 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3543 struct radv_draw_info info
= {};
3545 info
.count
= drawCount
;
3546 info
.indirect
= buffer
;
3547 info
.indirect_offset
= offset
;
3548 info
.stride
= stride
;
3550 radv_draw(cmd_buffer
, &info
);
3553 void radv_CmdDrawIndexedIndirect(
3554 VkCommandBuffer commandBuffer
,
3556 VkDeviceSize offset
,
3560 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3561 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3562 struct radv_draw_info info
= {};
3564 info
.indexed
= true;
3565 info
.count
= drawCount
;
3566 info
.indirect
= buffer
;
3567 info
.indirect_offset
= offset
;
3568 info
.stride
= stride
;
3570 radv_draw(cmd_buffer
, &info
);
3573 void radv_CmdDrawIndirectCountAMD(
3574 VkCommandBuffer commandBuffer
,
3576 VkDeviceSize offset
,
3577 VkBuffer _countBuffer
,
3578 VkDeviceSize countBufferOffset
,
3579 uint32_t maxDrawCount
,
3582 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3583 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3584 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3585 struct radv_draw_info info
= {};
3587 info
.count
= maxDrawCount
;
3588 info
.indirect
= buffer
;
3589 info
.indirect_offset
= offset
;
3590 info
.count_buffer
= count_buffer
;
3591 info
.count_buffer_offset
= countBufferOffset
;
3592 info
.stride
= stride
;
3594 radv_draw(cmd_buffer
, &info
);
3597 void radv_CmdDrawIndexedIndirectCountAMD(
3598 VkCommandBuffer commandBuffer
,
3600 VkDeviceSize offset
,
3601 VkBuffer _countBuffer
,
3602 VkDeviceSize countBufferOffset
,
3603 uint32_t maxDrawCount
,
3606 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3607 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3608 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3609 struct radv_draw_info info
= {};
3611 info
.indexed
= true;
3612 info
.count
= maxDrawCount
;
3613 info
.indirect
= buffer
;
3614 info
.indirect_offset
= offset
;
3615 info
.count_buffer
= count_buffer
;
3616 info
.count_buffer_offset
= countBufferOffset
;
3617 info
.stride
= stride
;
3619 radv_draw(cmd_buffer
, &info
);
3622 void radv_CmdDrawIndirectCountKHR(
3623 VkCommandBuffer commandBuffer
,
3625 VkDeviceSize offset
,
3626 VkBuffer _countBuffer
,
3627 VkDeviceSize countBufferOffset
,
3628 uint32_t maxDrawCount
,
3631 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3632 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3633 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3634 struct radv_draw_info info
= {};
3636 info
.count
= maxDrawCount
;
3637 info
.indirect
= buffer
;
3638 info
.indirect_offset
= offset
;
3639 info
.count_buffer
= count_buffer
;
3640 info
.count_buffer_offset
= countBufferOffset
;
3641 info
.stride
= stride
;
3643 radv_draw(cmd_buffer
, &info
);
3646 void radv_CmdDrawIndexedIndirectCountKHR(
3647 VkCommandBuffer commandBuffer
,
3649 VkDeviceSize offset
,
3650 VkBuffer _countBuffer
,
3651 VkDeviceSize countBufferOffset
,
3652 uint32_t maxDrawCount
,
3655 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3656 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3657 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3658 struct radv_draw_info info
= {};
3660 info
.indexed
= true;
3661 info
.count
= maxDrawCount
;
3662 info
.indirect
= buffer
;
3663 info
.indirect_offset
= offset
;
3664 info
.count_buffer
= count_buffer
;
3665 info
.count_buffer_offset
= countBufferOffset
;
3666 info
.stride
= stride
;
3668 radv_draw(cmd_buffer
, &info
);
3671 struct radv_dispatch_info
{
3673 * Determine the layout of the grid (in block units) to be used.
3678 * A starting offset for the grid. If unaligned is set, the offset
3679 * must still be aligned.
3681 uint32_t offsets
[3];
3683 * Whether it's an unaligned compute dispatch.
3688 * Indirect compute parameters resource.
3690 struct radv_buffer
*indirect
;
3691 uint64_t indirect_offset
;
3695 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3696 const struct radv_dispatch_info
*info
)
3698 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3699 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3700 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3701 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3702 bool predicating
= cmd_buffer
->state
.predicating
;
3703 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3704 struct radv_userdata_info
*loc
;
3706 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3707 AC_UD_CS_GRID_SIZE
);
3709 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3711 if (info
->indirect
) {
3712 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3714 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3716 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3718 if (loc
->sgpr_idx
!= -1) {
3719 for (unsigned i
= 0; i
< 3; ++i
) {
3720 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3721 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3722 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3723 radeon_emit(cs
, (va
+ 4 * i
));
3724 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3725 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3726 + loc
->sgpr_idx
* 4) >> 2) + i
);
3731 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3732 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
3733 PKT3_SHADER_TYPE_S(1));
3734 radeon_emit(cs
, va
);
3735 radeon_emit(cs
, va
>> 32);
3736 radeon_emit(cs
, dispatch_initiator
);
3738 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3739 PKT3_SHADER_TYPE_S(1));
3741 radeon_emit(cs
, va
);
3742 radeon_emit(cs
, va
>> 32);
3744 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
3745 PKT3_SHADER_TYPE_S(1));
3747 radeon_emit(cs
, dispatch_initiator
);
3750 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3751 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
3753 if (info
->unaligned
) {
3754 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3755 unsigned remainder
[3];
3757 /* If aligned, these should be an entire block size,
3760 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3761 align_u32_npot(blocks
[0], cs_block_size
[0]);
3762 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3763 align_u32_npot(blocks
[1], cs_block_size
[1]);
3764 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3765 align_u32_npot(blocks
[2], cs_block_size
[2]);
3767 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3768 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3769 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3771 for(unsigned i
= 0; i
< 3; ++i
) {
3772 assert(offsets
[i
] % cs_block_size
[i
] == 0);
3773 offsets
[i
] /= cs_block_size
[i
];
3776 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3778 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3779 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3781 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3782 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3784 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3785 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3787 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3790 if (loc
->sgpr_idx
!= -1) {
3791 assert(!loc
->indirect
);
3792 assert(loc
->num_sgprs
== 3);
3794 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3795 loc
->sgpr_idx
* 4, 3);
3796 radeon_emit(cs
, blocks
[0]);
3797 radeon_emit(cs
, blocks
[1]);
3798 radeon_emit(cs
, blocks
[2]);
3801 if (offsets
[0] || offsets
[1] || offsets
[2]) {
3802 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
3803 radeon_emit(cs
, offsets
[0]);
3804 radeon_emit(cs
, offsets
[1]);
3805 radeon_emit(cs
, offsets
[2]);
3807 /* The blocks in the packet are not counts but end values. */
3808 for (unsigned i
= 0; i
< 3; ++i
)
3809 blocks
[i
] += offsets
[i
];
3811 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
3814 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
3815 PKT3_SHADER_TYPE_S(1));
3816 radeon_emit(cs
, blocks
[0]);
3817 radeon_emit(cs
, blocks
[1]);
3818 radeon_emit(cs
, blocks
[2]);
3819 radeon_emit(cs
, dispatch_initiator
);
3822 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3826 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
3828 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3829 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3833 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3834 const struct radv_dispatch_info
*info
)
3836 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3838 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3839 bool pipeline_is_dirty
= pipeline
&&
3840 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
3842 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3843 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3844 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3845 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3846 /* If we have to wait for idle, set all states first, so that
3847 * all SET packets are processed in parallel with previous draw
3848 * calls. Then upload descriptors, set shader pointers, and
3849 * dispatch, and prefetch at the end. This ensures that the
3850 * time the CUs are idle is very short. (there are only SET_SH
3851 * packets between the wait and the draw)
3853 radv_emit_compute_pipeline(cmd_buffer
);
3854 si_emit_cache_flush(cmd_buffer
);
3855 /* <-- CUs are idle here --> */
3857 radv_upload_compute_shader_descriptors(cmd_buffer
);
3859 radv_emit_dispatch_packets(cmd_buffer
, info
);
3860 /* <-- CUs are busy here --> */
3862 /* Start prefetches after the dispatch has been started. Both
3863 * will run in parallel, but starting the dispatch first is
3866 if (has_prefetch
&& pipeline_is_dirty
) {
3867 radv_emit_shader_prefetch(cmd_buffer
,
3868 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3871 /* If we don't wait for idle, start prefetches first, then set
3872 * states, and dispatch at the end.
3874 si_emit_cache_flush(cmd_buffer
);
3876 if (has_prefetch
&& pipeline_is_dirty
) {
3877 radv_emit_shader_prefetch(cmd_buffer
,
3878 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3881 radv_upload_compute_shader_descriptors(cmd_buffer
);
3883 radv_emit_compute_pipeline(cmd_buffer
);
3884 radv_emit_dispatch_packets(cmd_buffer
, info
);
3887 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
3890 void radv_CmdDispatchBase(
3891 VkCommandBuffer commandBuffer
,
3899 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3900 struct radv_dispatch_info info
= {};
3906 info
.offsets
[0] = base_x
;
3907 info
.offsets
[1] = base_y
;
3908 info
.offsets
[2] = base_z
;
3909 radv_dispatch(cmd_buffer
, &info
);
3912 void radv_CmdDispatch(
3913 VkCommandBuffer commandBuffer
,
3918 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3921 void radv_CmdDispatchIndirect(
3922 VkCommandBuffer commandBuffer
,
3924 VkDeviceSize offset
)
3926 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3927 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3928 struct radv_dispatch_info info
= {};
3930 info
.indirect
= buffer
;
3931 info
.indirect_offset
= offset
;
3933 radv_dispatch(cmd_buffer
, &info
);
3936 void radv_unaligned_dispatch(
3937 struct radv_cmd_buffer
*cmd_buffer
,
3942 struct radv_dispatch_info info
= {};
3949 radv_dispatch(cmd_buffer
, &info
);
3952 void radv_CmdEndRenderPass(
3953 VkCommandBuffer commandBuffer
)
3955 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3957 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3959 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3961 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3962 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3963 radv_handle_subpass_image_transition(cmd_buffer
,
3964 (struct radv_subpass_attachment
){i
, layout
});
3967 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3969 cmd_buffer
->state
.pass
= NULL
;
3970 cmd_buffer
->state
.subpass
= NULL
;
3971 cmd_buffer
->state
.attachments
= NULL
;
3972 cmd_buffer
->state
.framebuffer
= NULL
;
3975 void radv_CmdEndRenderPass2KHR(
3976 VkCommandBuffer commandBuffer
,
3977 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3979 radv_CmdEndRenderPass(commandBuffer
);
3983 * For HTILE we have the following interesting clear words:
3984 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3985 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3986 * 0xfffffff0: Clear depth to 1.0
3987 * 0x00000000: Clear depth to 0.0
3989 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3990 struct radv_image
*image
,
3991 const VkImageSubresourceRange
*range
,
3992 uint32_t clear_word
)
3994 assert(range
->baseMipLevel
== 0);
3995 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3996 unsigned layer_count
= radv_get_layerCount(image
, range
);
3997 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3998 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3999 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4000 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4001 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4002 VkClearDepthStencilValue value
= {};
4004 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4005 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4007 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4010 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4012 if (vk_format_is_stencil(image
->vk_format
))
4013 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4015 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4018 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4019 struct radv_image
*image
,
4020 VkImageLayout src_layout
,
4021 VkImageLayout dst_layout
,
4022 unsigned src_queue_mask
,
4023 unsigned dst_queue_mask
,
4024 const VkImageSubresourceRange
*range
,
4025 VkImageAspectFlags pending_clears
)
4027 if (!radv_image_has_htile(image
))
4030 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4031 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4032 /* TODO: merge with the clear if applicable */
4033 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4034 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4035 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4036 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4037 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4038 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4039 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4040 VkImageSubresourceRange local_range
= *range
;
4041 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4042 local_range
.baseMipLevel
= 0;
4043 local_range
.levelCount
= 1;
4045 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4046 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4048 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4050 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4051 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4055 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4056 struct radv_image
*image
, uint32_t value
)
4058 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4060 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4061 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4063 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4065 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4068 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4069 struct radv_image
*image
, uint32_t value
)
4071 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4073 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4074 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4076 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4078 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4079 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4083 * Initialize DCC/FMASK/CMASK metadata for a color image.
4085 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4086 struct radv_image
*image
,
4087 VkImageLayout src_layout
,
4088 VkImageLayout dst_layout
,
4089 unsigned src_queue_mask
,
4090 unsigned dst_queue_mask
)
4092 if (radv_image_has_cmask(image
)) {
4093 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4095 /* TODO: clarify this. */
4096 if (radv_image_has_fmask(image
)) {
4097 value
= 0xccccccccu
;
4100 radv_initialise_cmask(cmd_buffer
, image
, value
);
4103 if (radv_image_has_dcc(image
)) {
4104 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4106 if (radv_layout_dcc_compressed(image
, dst_layout
,
4108 value
= 0x20202020u
;
4111 radv_initialize_dcc(cmd_buffer
, image
, value
);
4113 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, image
, false);
4116 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4117 uint32_t color_values
[2] = {};
4118 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4123 * Handle color image transitions for DCC/FMASK/CMASK.
4125 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4126 struct radv_image
*image
,
4127 VkImageLayout src_layout
,
4128 VkImageLayout dst_layout
,
4129 unsigned src_queue_mask
,
4130 unsigned dst_queue_mask
,
4131 const VkImageSubresourceRange
*range
)
4133 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4134 radv_init_color_image_metadata(cmd_buffer
, image
,
4135 src_layout
, dst_layout
,
4136 src_queue_mask
, dst_queue_mask
);
4140 if (radv_image_has_dcc(image
)) {
4141 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4142 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4143 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4144 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4145 radv_decompress_dcc(cmd_buffer
, image
, range
);
4146 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4147 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4148 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4150 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4151 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4152 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4153 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4158 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4159 struct radv_image
*image
,
4160 VkImageLayout src_layout
,
4161 VkImageLayout dst_layout
,
4162 uint32_t src_family
,
4163 uint32_t dst_family
,
4164 const VkImageSubresourceRange
*range
,
4165 VkImageAspectFlags pending_clears
)
4167 if (image
->exclusive
&& src_family
!= dst_family
) {
4168 /* This is an acquire or a release operation and there will be
4169 * a corresponding release/acquire. Do the transition in the
4170 * most flexible queue. */
4172 assert(src_family
== cmd_buffer
->queue_family_index
||
4173 dst_family
== cmd_buffer
->queue_family_index
);
4175 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4178 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4179 (src_family
== RADV_QUEUE_GENERAL
||
4180 dst_family
== RADV_QUEUE_GENERAL
))
4184 unsigned src_queue_mask
=
4185 radv_image_queue_family_mask(image
, src_family
,
4186 cmd_buffer
->queue_family_index
);
4187 unsigned dst_queue_mask
=
4188 radv_image_queue_family_mask(image
, dst_family
,
4189 cmd_buffer
->queue_family_index
);
4191 if (vk_format_is_depth(image
->vk_format
)) {
4192 radv_handle_depth_image_transition(cmd_buffer
, image
,
4193 src_layout
, dst_layout
,
4194 src_queue_mask
, dst_queue_mask
,
4195 range
, pending_clears
);
4197 radv_handle_color_image_transition(cmd_buffer
, image
,
4198 src_layout
, dst_layout
,
4199 src_queue_mask
, dst_queue_mask
,
4204 struct radv_barrier_info
{
4205 uint32_t eventCount
;
4206 const VkEvent
*pEvents
;
4207 VkPipelineStageFlags srcStageMask
;
4211 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4212 uint32_t memoryBarrierCount
,
4213 const VkMemoryBarrier
*pMemoryBarriers
,
4214 uint32_t bufferMemoryBarrierCount
,
4215 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4216 uint32_t imageMemoryBarrierCount
,
4217 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4218 const struct radv_barrier_info
*info
)
4220 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4221 enum radv_cmd_flush_bits src_flush_bits
= 0;
4222 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4224 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4225 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4226 uint64_t va
= radv_buffer_get_va(event
->bo
);
4228 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4230 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4232 si_emit_wait_fence(cs
, va
, 1, 0xffffffff);
4233 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4236 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4237 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4239 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4243 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4244 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4246 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4250 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4251 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4253 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4255 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4259 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4260 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4262 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4263 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4264 radv_handle_image_transition(cmd_buffer
, image
,
4265 pImageMemoryBarriers
[i
].oldLayout
,
4266 pImageMemoryBarriers
[i
].newLayout
,
4267 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4268 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4269 &pImageMemoryBarriers
[i
].subresourceRange
,
4273 /* Make sure CP DMA is idle because the driver might have performed a
4274 * DMA operation for copying or filling buffers/images.
4276 si_cp_dma_wait_for_idle(cmd_buffer
);
4278 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4281 void radv_CmdPipelineBarrier(
4282 VkCommandBuffer commandBuffer
,
4283 VkPipelineStageFlags srcStageMask
,
4284 VkPipelineStageFlags destStageMask
,
4286 uint32_t memoryBarrierCount
,
4287 const VkMemoryBarrier
* pMemoryBarriers
,
4288 uint32_t bufferMemoryBarrierCount
,
4289 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4290 uint32_t imageMemoryBarrierCount
,
4291 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4293 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4294 struct radv_barrier_info info
;
4296 info
.eventCount
= 0;
4297 info
.pEvents
= NULL
;
4298 info
.srcStageMask
= srcStageMask
;
4300 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4301 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4302 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4306 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4307 struct radv_event
*event
,
4308 VkPipelineStageFlags stageMask
,
4311 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4312 uint64_t va
= radv_buffer_get_va(event
->bo
);
4314 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4316 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4318 /* Flags that only require a top-of-pipe event. */
4319 VkPipelineStageFlags top_of_pipe_flags
=
4320 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4322 /* Flags that only require a post-index-fetch event. */
4323 VkPipelineStageFlags post_index_fetch_flags
=
4325 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4326 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4328 /* Make sure CP DMA is idle because the driver might have performed a
4329 * DMA operation for copying or filling buffers/images.
4331 si_cp_dma_wait_for_idle(cmd_buffer
);
4333 /* TODO: Emit EOS events for syncing PS/CS stages. */
4335 if (!(stageMask
& ~top_of_pipe_flags
)) {
4336 /* Just need to sync the PFP engine. */
4337 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4338 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4339 S_370_WR_CONFIRM(1) |
4340 S_370_ENGINE_SEL(V_370_PFP
));
4341 radeon_emit(cs
, va
);
4342 radeon_emit(cs
, va
>> 32);
4343 radeon_emit(cs
, value
);
4344 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4345 /* Sync ME because PFP reads index and indirect buffers. */
4346 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4347 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4348 S_370_WR_CONFIRM(1) |
4349 S_370_ENGINE_SEL(V_370_ME
));
4350 radeon_emit(cs
, va
);
4351 radeon_emit(cs
, va
>> 32);
4352 radeon_emit(cs
, value
);
4354 /* Otherwise, sync all prior GPU work using an EOP event. */
4355 si_cs_emit_write_event_eop(cs
,
4356 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4357 radv_cmd_buffer_uses_mec(cmd_buffer
),
4358 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4359 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4360 cmd_buffer
->gfx9_eop_bug_va
);
4363 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4366 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4368 VkPipelineStageFlags stageMask
)
4370 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4371 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4373 write_event(cmd_buffer
, event
, stageMask
, 1);
4376 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4378 VkPipelineStageFlags stageMask
)
4380 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4381 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4383 write_event(cmd_buffer
, event
, stageMask
, 0);
4386 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4387 uint32_t eventCount
,
4388 const VkEvent
* pEvents
,
4389 VkPipelineStageFlags srcStageMask
,
4390 VkPipelineStageFlags dstStageMask
,
4391 uint32_t memoryBarrierCount
,
4392 const VkMemoryBarrier
* pMemoryBarriers
,
4393 uint32_t bufferMemoryBarrierCount
,
4394 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4395 uint32_t imageMemoryBarrierCount
,
4396 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4398 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4399 struct radv_barrier_info info
;
4401 info
.eventCount
= eventCount
;
4402 info
.pEvents
= pEvents
;
4403 info
.srcStageMask
= 0;
4405 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4406 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4407 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4411 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4412 uint32_t deviceMask
)