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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 struct ac_userdata_info *
492 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
493 gl_shader_stage stage,
494 int idx)
495 {
496 if (stage == MESA_SHADER_VERTEX) {
497 if (pipeline->shaders[MESA_SHADER_VERTEX])
498 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
499 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
500 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
501 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
502 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
503 }
504 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
505 }
506
507 static void
508 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
509 struct radv_pipeline *pipeline,
510 gl_shader_stage stage,
511 int idx, uint64_t va)
512 {
513 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
514 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
515 if (loc->sgpr_idx == -1)
516 return;
517 assert(loc->num_sgprs == 2);
518 assert(!loc->indirect);
519 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
520 radeon_emit(cmd_buffer->cs, va);
521 radeon_emit(cmd_buffer->cs, va >> 32);
522 }
523
524 static void
525 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
526 struct radv_pipeline *pipeline)
527 {
528 int num_samples = pipeline->graphics.ms.num_samples;
529 struct radv_multisample_state *ms = &pipeline->graphics.ms;
530 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
531
532 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
533 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
534 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
535
536 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
537 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
538
539 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
540 return;
541
542 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
543 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
544 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
545
546 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
547
548 /* GFX9: Flush DFSM when the AA mode changes. */
549 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
550 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
551 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
552 }
553 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
554 uint32_t offset;
555 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
556 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
557 if (loc->sgpr_idx == -1)
558 return;
559 assert(loc->num_sgprs == 1);
560 assert(!loc->indirect);
561 switch (num_samples) {
562 default:
563 offset = 0;
564 break;
565 case 2:
566 offset = 1;
567 break;
568 case 4:
569 offset = 3;
570 break;
571 case 8:
572 offset = 7;
573 break;
574 case 16:
575 offset = 15;
576 break;
577 }
578
579 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
580 cmd_buffer->sample_positions_needed = true;
581 }
582 }
583
584 static void
585 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_pipeline *pipeline)
587 {
588 struct radv_raster_state *raster = &pipeline->graphics.raster;
589
590 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
591 raster->pa_cl_clip_cntl);
592 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
593 raster->spi_interp_control);
594 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
595 raster->pa_su_vtx_cntl);
596 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
597 raster->pa_su_sc_mode_cntl);
598 }
599
600 static inline void
601 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
602 unsigned size)
603 {
604 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
605 si_cp_dma_prefetch(cmd_buffer, va, size);
606 }
607
608 static void
609 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_pipeline *pipeline,
611 struct radv_shader_variant *shader,
612 struct ac_vs_output_info *outinfo)
613 {
614 struct radeon_winsys *ws = cmd_buffer->device->ws;
615 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
616 unsigned export_count;
617
618 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
619 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
620
621 export_count = MAX2(1, outinfo->param_exports);
622 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
623 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
624
625 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
626 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
627 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
628 V_02870C_SPI_SHADER_4COMP :
629 V_02870C_SPI_SHADER_NONE) |
630 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
631 V_02870C_SPI_SHADER_4COMP :
632 V_02870C_SPI_SHADER_NONE) |
633 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
634 V_02870C_SPI_SHADER_4COMP :
635 V_02870C_SPI_SHADER_NONE));
636
637
638 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
639 radeon_emit(cmd_buffer->cs, va >> 8);
640 radeon_emit(cmd_buffer->cs, va >> 40);
641 radeon_emit(cmd_buffer->cs, shader->rsrc1);
642 radeon_emit(cmd_buffer->cs, shader->rsrc2);
643
644 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
645 S_028818_VTX_W0_FMT(1) |
646 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
647 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
648 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
649
650
651 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
652 pipeline->graphics.pa_cl_vs_out_cntl);
653
654 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
655 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
656 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
657 }
658
659 static void
660 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
661 struct radv_shader_variant *shader,
662 struct ac_es_output_info *outinfo)
663 {
664 struct radeon_winsys *ws = cmd_buffer->device->ws;
665 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
668 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
669
670 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
671 outinfo->esgs_itemsize / 4);
672 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
673 radeon_emit(cmd_buffer->cs, va >> 8);
674 radeon_emit(cmd_buffer->cs, va >> 40);
675 radeon_emit(cmd_buffer->cs, shader->rsrc1);
676 radeon_emit(cmd_buffer->cs, shader->rsrc2);
677 }
678
679 static void
680 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
681 struct radv_shader_variant *shader)
682 {
683 struct radeon_winsys *ws = cmd_buffer->device->ws;
684 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
685 uint32_t rsrc2 = shader->rsrc2;
686
687 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
688 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
689
690 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
691 radeon_emit(cmd_buffer->cs, va >> 8);
692 radeon_emit(cmd_buffer->cs, va >> 40);
693
694 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
695 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
696 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
697 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
698
699 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
700 radeon_emit(cmd_buffer->cs, shader->rsrc1);
701 radeon_emit(cmd_buffer->cs, rsrc2);
702 }
703
704 static void
705 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
706 struct radv_shader_variant *shader)
707 {
708 struct radeon_winsys *ws = cmd_buffer->device->ws;
709 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
710
711 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
712 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
713
714 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
715 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
716 radeon_emit(cmd_buffer->cs, va >> 8);
717 radeon_emit(cmd_buffer->cs, va >> 40);
718
719 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
720 radeon_emit(cmd_buffer->cs, shader->rsrc1);
721 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
722 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
723 } else {
724 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
725 radeon_emit(cmd_buffer->cs, va >> 8);
726 radeon_emit(cmd_buffer->cs, va >> 40);
727 radeon_emit(cmd_buffer->cs, shader->rsrc1);
728 radeon_emit(cmd_buffer->cs, shader->rsrc2);
729 }
730 }
731
732 static void
733 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
734 struct radv_pipeline *pipeline)
735 {
736 struct radv_shader_variant *vs;
737
738 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
739
740 /* Skip shaders merged into HS/GS */
741 vs = pipeline->shaders[MESA_SHADER_VERTEX];
742 if (!vs)
743 return;
744
745 if (vs->info.vs.as_ls)
746 radv_emit_hw_ls(cmd_buffer, vs);
747 else if (vs->info.vs.as_es)
748 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
749 else
750 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
751 }
752
753
754 static void
755 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
756 struct radv_pipeline *pipeline)
757 {
758 if (!radv_pipeline_has_tess(pipeline))
759 return;
760
761 struct radv_shader_variant *tes, *tcs;
762
763 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
764 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
765
766 if (tes->info.tes.as_es)
767 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
768 else
769 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
770
771 radv_emit_hw_hs(cmd_buffer, tcs);
772
773 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
774 pipeline->graphics.tess.tf_param);
775
776 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
777 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
778 pipeline->graphics.tess.ls_hs_config);
779 else
780 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
781 pipeline->graphics.tess.ls_hs_config);
782
783 struct ac_userdata_info *loc;
784
785 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
786 if (loc->sgpr_idx != -1) {
787 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
788 assert(loc->num_sgprs == 4);
789 assert(!loc->indirect);
790 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
791 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
792 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
793 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
794 pipeline->graphics.tess.num_tcs_input_cp << 26);
795 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
796 }
797
798 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
799 if (loc->sgpr_idx != -1) {
800 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
801 assert(loc->num_sgprs == 1);
802 assert(!loc->indirect);
803
804 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
805 pipeline->graphics.tess.offchip_layout);
806 }
807
808 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
809 if (loc->sgpr_idx != -1) {
810 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
811 assert(loc->num_sgprs == 1);
812 assert(!loc->indirect);
813
814 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
815 pipeline->graphics.tess.tcs_in_layout);
816 }
817 }
818
819 static void
820 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
821 struct radv_pipeline *pipeline)
822 {
823 struct radeon_winsys *ws = cmd_buffer->device->ws;
824 struct radv_shader_variant *gs;
825 uint64_t va;
826
827 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
828
829 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
830 if (!gs)
831 return;
832
833 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
834
835 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
836 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
837 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
838 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
839
840 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
841
842 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
843
844 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
845 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
846 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
847 radeon_emit(cmd_buffer->cs, 0);
848 radeon_emit(cmd_buffer->cs, 0);
849 radeon_emit(cmd_buffer->cs, 0);
850
851 uint32_t gs_num_invocations = gs->info.gs.invocations;
852 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
853 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
854 S_028B90_ENABLE(gs_num_invocations > 0));
855
856 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
857 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
858 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
859
860 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
861 radeon_emit(cmd_buffer->cs, va >> 8);
862 radeon_emit(cmd_buffer->cs, va >> 40);
863 radeon_emit(cmd_buffer->cs, gs->rsrc1);
864 radeon_emit(cmd_buffer->cs, gs->rsrc2);
865
866 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
867
868 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
869 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
870 if (loc->sgpr_idx != -1) {
871 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
872 uint32_t num_entries = 64;
873 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
874
875 if (is_vi)
876 num_entries *= stride;
877
878 stride = S_008F04_STRIDE(stride);
879 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
880 radeon_emit(cmd_buffer->cs, stride);
881 radeon_emit(cmd_buffer->cs, num_entries);
882 }
883 }
884
885 static void
886 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_pipeline *pipeline)
888 {
889 struct radeon_winsys *ws = cmd_buffer->device->ws;
890 struct radv_shader_variant *ps;
891 uint64_t va;
892 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
893 struct radv_blend_state *blend = &pipeline->graphics.blend;
894 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
895
896 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
897 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
898 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
899 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
900
901 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
902 radeon_emit(cmd_buffer->cs, va >> 8);
903 radeon_emit(cmd_buffer->cs, va >> 40);
904 radeon_emit(cmd_buffer->cs, ps->rsrc1);
905 radeon_emit(cmd_buffer->cs, ps->rsrc2);
906
907 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
908 pipeline->graphics.db_shader_control);
909
910 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
911 ps->config.spi_ps_input_ena);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
914 ps->config.spi_ps_input_addr);
915
916 if (ps->info.info.ps.force_persample)
917 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
918
919 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
920 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
921
922 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
923
924 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
925 pipeline->graphics.shader_z_format);
926
927 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
930 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
931
932 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
933 /* optimise this? */
934 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
935 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
936 }
937
938 if (pipeline->graphics.ps_input_cntl_num) {
939 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
940 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
941 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
942 }
943 }
944 }
945
946 static void
947 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_pipeline *pipeline)
949 {
950 struct radeon_winsys_cs *cs = cmd_buffer->cs;
951
952 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
953 return;
954
955 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
956 pipeline->graphics.vtx_reuse_depth);
957 }
958
959 static void
960 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
961 {
962 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
963
964 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
965 return;
966
967 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
968 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
969 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
970 radv_update_multisample_state(cmd_buffer, pipeline);
971 radv_emit_vertex_shader(cmd_buffer, pipeline);
972 radv_emit_tess_shaders(cmd_buffer, pipeline);
973 radv_emit_geometry_shader(cmd_buffer, pipeline);
974 radv_emit_fragment_shader(cmd_buffer, pipeline);
975 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
976
977 cmd_buffer->scratch_size_needed =
978 MAX2(cmd_buffer->scratch_size_needed,
979 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
980
981 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
982 S_0286E8_WAVES(pipeline->max_waves) |
983 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
984
985 if (!cmd_buffer->state.emitted_pipeline ||
986 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
987 pipeline->graphics.can_use_guardband)
988 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
989
990 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
991
992 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
993 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
994 } else {
995 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
996 }
997 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
998
999 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1000
1001 cmd_buffer->state.emitted_pipeline = pipeline;
1002 }
1003
1004 static void
1005 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1006 {
1007 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1008 cmd_buffer->state.dynamic.viewport.viewports);
1009 }
1010
1011 static void
1012 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1013 {
1014 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1015
1016 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1017 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1018 si_emit_cache_flush(cmd_buffer);
1019 }
1020 si_write_scissors(cmd_buffer->cs, 0, count,
1021 cmd_buffer->state.dynamic.scissor.scissors,
1022 cmd_buffer->state.dynamic.viewport.viewports,
1023 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1024 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1025 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1026 }
1027
1028 static void
1029 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1030 {
1031 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1032
1033 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1034 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1035 }
1036
1037 static void
1038 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1039 {
1040 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1041
1042 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1043 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1044 }
1045
1046 static void
1047 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1048 {
1049 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1050
1051 radeon_set_context_reg_seq(cmd_buffer->cs,
1052 R_028430_DB_STENCILREFMASK, 2);
1053 radeon_emit(cmd_buffer->cs,
1054 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1055 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1056 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1057 S_028430_STENCILOPVAL(1));
1058 radeon_emit(cmd_buffer->cs,
1059 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1060 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1061 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1062 S_028434_STENCILOPVAL_BF(1));
1063 }
1064
1065 static void
1066 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1067 {
1068 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1069
1070 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1071 fui(d->depth_bounds.min));
1072 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1073 fui(d->depth_bounds.max));
1074 }
1075
1076 static void
1077 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1078 {
1079 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1080 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1081 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1082 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1083
1084 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1085 radeon_set_context_reg_seq(cmd_buffer->cs,
1086 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1087 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1088 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1089 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1090 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1091 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1092 }
1093 }
1094
1095 static void
1096 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1097 int index,
1098 struct radv_color_buffer_info *cb)
1099 {
1100 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1101
1102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1103 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1104 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1105 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1106 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1107 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1108 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1109 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1110 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1111 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1112 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1115
1116 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1117 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1118 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1119
1120 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1121 cb->gfx9_epitch);
1122 } else {
1123 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1124 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1125 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1126 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1127 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1128 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1129 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1130 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1131 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1132 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1133 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1134 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1135
1136 if (is_vi) { /* DCC BASE */
1137 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1138 }
1139 }
1140 }
1141
1142 static void
1143 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1144 struct radv_ds_buffer_info *ds,
1145 struct radv_image *image,
1146 VkImageLayout layout)
1147 {
1148 uint32_t db_z_info = ds->db_z_info;
1149 uint32_t db_stencil_info = ds->db_stencil_info;
1150
1151 if (!radv_layout_has_htile(image, layout,
1152 radv_image_queue_family_mask(image,
1153 cmd_buffer->queue_family_index,
1154 cmd_buffer->queue_family_index))) {
1155 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1156 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1157 }
1158
1159 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1160 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1161
1162
1163 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1165 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1166 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1167 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1168
1169 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1170 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1171 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1172 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1173 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1174 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1177 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1178 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1179 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1180
1181 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1182 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1184 } else {
1185 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1186
1187 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1188 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1189 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1190 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1191 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1192 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1193 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1194 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1195 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1196 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1197
1198 }
1199
1200 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1201 ds->pa_su_poly_offset_db_fmt_cntl);
1202 }
1203
1204 void
1205 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1206 struct radv_image *image,
1207 VkClearDepthStencilValue ds_clear_value,
1208 VkImageAspectFlags aspects)
1209 {
1210 uint64_t va = radv_buffer_get_va(image->bo);
1211 va += image->offset + image->clear_value_offset;
1212 unsigned reg_offset = 0, reg_count = 0;
1213
1214 if (!image->surface.htile_size || !aspects)
1215 return;
1216
1217 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1218 ++reg_count;
1219 } else {
1220 ++reg_offset;
1221 va += 4;
1222 }
1223 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1224 ++reg_count;
1225
1226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1227
1228 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1229 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1230 S_370_WR_CONFIRM(1) |
1231 S_370_ENGINE_SEL(V_370_PFP));
1232 radeon_emit(cmd_buffer->cs, va);
1233 radeon_emit(cmd_buffer->cs, va >> 32);
1234 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1235 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1236 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1237 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1238
1239 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1240 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1241 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1242 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1243 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1244 }
1245
1246 static void
1247 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1248 struct radv_image *image)
1249 {
1250 uint64_t va = radv_buffer_get_va(image->bo);
1251 va += image->offset + image->clear_value_offset;
1252
1253 if (!image->surface.htile_size)
1254 return;
1255
1256 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1257
1258 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1259 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1260 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1261 COPY_DATA_COUNT_SEL);
1262 radeon_emit(cmd_buffer->cs, va);
1263 radeon_emit(cmd_buffer->cs, va >> 32);
1264 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1265 radeon_emit(cmd_buffer->cs, 0);
1266
1267 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1268 radeon_emit(cmd_buffer->cs, 0);
1269 }
1270
1271 /*
1272 *with DCC some colors don't require CMASK elimiation before being
1273 * used as a texture. This sets a predicate value to determine if the
1274 * cmask eliminate is required.
1275 */
1276 void
1277 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image,
1279 bool value)
1280 {
1281 uint64_t pred_val = value;
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 va += image->offset + image->dcc_pred_offset;
1284
1285 if (!image->surface.dcc_size)
1286 return;
1287
1288 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1289
1290 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1291 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1292 S_370_WR_CONFIRM(1) |
1293 S_370_ENGINE_SEL(V_370_PFP));
1294 radeon_emit(cmd_buffer->cs, va);
1295 radeon_emit(cmd_buffer->cs, va >> 32);
1296 radeon_emit(cmd_buffer->cs, pred_val);
1297 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1298 }
1299
1300 void
1301 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_image *image,
1303 int idx,
1304 uint32_t color_values[2])
1305 {
1306 uint64_t va = radv_buffer_get_va(image->bo);
1307 va += image->offset + image->clear_value_offset;
1308
1309 if (!image->cmask.size && !image->surface.dcc_size)
1310 return;
1311
1312 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1313
1314 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1315 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1316 S_370_WR_CONFIRM(1) |
1317 S_370_ENGINE_SEL(V_370_PFP));
1318 radeon_emit(cmd_buffer->cs, va);
1319 radeon_emit(cmd_buffer->cs, va >> 32);
1320 radeon_emit(cmd_buffer->cs, color_values[0]);
1321 radeon_emit(cmd_buffer->cs, color_values[1]);
1322
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1324 radeon_emit(cmd_buffer->cs, color_values[0]);
1325 radeon_emit(cmd_buffer->cs, color_values[1]);
1326 }
1327
1328 static void
1329 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1330 struct radv_image *image,
1331 int idx)
1332 {
1333 uint64_t va = radv_buffer_get_va(image->bo);
1334 va += image->offset + image->clear_value_offset;
1335
1336 if (!image->cmask.size && !image->surface.dcc_size)
1337 return;
1338
1339 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1340 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1341
1342 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1343 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1344 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1345 COPY_DATA_COUNT_SEL);
1346 radeon_emit(cmd_buffer->cs, va);
1347 radeon_emit(cmd_buffer->cs, va >> 32);
1348 radeon_emit(cmd_buffer->cs, reg >> 2);
1349 radeon_emit(cmd_buffer->cs, 0);
1350
1351 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1352 radeon_emit(cmd_buffer->cs, 0);
1353 }
1354
1355 void
1356 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1357 {
1358 int i;
1359 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1360 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1361
1362 /* this may happen for inherited secondary recording */
1363 if (!framebuffer)
1364 return;
1365
1366 for (i = 0; i < 8; ++i) {
1367 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1368 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1369 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1370 continue;
1371 }
1372
1373 int idx = subpass->color_attachments[i].attachment;
1374 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1375
1376 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1377
1378 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1379 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1380
1381 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1382 }
1383
1384 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1385 int idx = subpass->depth_stencil_attachment.attachment;
1386 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1387 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1388 struct radv_image *image = att->attachment->image;
1389 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1390 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1391 cmd_buffer->queue_family_index,
1392 cmd_buffer->queue_family_index);
1393 /* We currently don't support writing decompressed HTILE */
1394 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1395 radv_layout_is_htile_compressed(image, layout, queue_mask));
1396
1397 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1398
1399 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1400 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1401 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1402 }
1403 radv_load_depth_clear_regs(cmd_buffer, image);
1404 } else {
1405 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1406 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1407 else
1408 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1409
1410 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1411 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1412 }
1413 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1414 S_028208_BR_X(framebuffer->width) |
1415 S_028208_BR_Y(framebuffer->height));
1416
1417 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1418 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1419 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1420 }
1421 }
1422
1423 static void
1424 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1425 {
1426 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1427
1428 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1429 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1430 2, cmd_buffer->state.index_type);
1431 } else {
1432 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1433 radeon_emit(cs, cmd_buffer->state.index_type);
1434 }
1435
1436 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1437 radeon_emit(cs, cmd_buffer->state.index_va);
1438 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1439
1440 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1441 radeon_emit(cs, cmd_buffer->state.max_index_count);
1442 }
1443
1444 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1445 {
1446 uint32_t db_count_control;
1447
1448 if(!cmd_buffer->state.active_occlusion_queries) {
1449 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1450 db_count_control = 0;
1451 } else {
1452 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1453 }
1454 } else {
1455 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1456 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1457 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1458 S_028004_ZPASS_ENABLE(1) |
1459 S_028004_SLICE_EVEN_ENABLE(1) |
1460 S_028004_SLICE_ODD_ENABLE(1);
1461 } else {
1462 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1463 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1464 }
1465 }
1466
1467 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1468 }
1469
1470 static void
1471 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1472 {
1473 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1474 return;
1475
1476 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1477 radv_emit_viewport(cmd_buffer);
1478
1479 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1480 radv_emit_scissor(cmd_buffer);
1481
1482 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1483 radv_emit_line_width(cmd_buffer);
1484
1485 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1486 radv_emit_blend_constants(cmd_buffer);
1487
1488 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1489 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1490 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1491 radv_emit_stencil(cmd_buffer);
1492
1493 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1494 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1495 radv_emit_depth_bounds(cmd_buffer);
1496
1497 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1498 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1499 radv_emit_depth_biais(cmd_buffer);
1500 }
1501
1502 static void
1503 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1504 struct radv_pipeline *pipeline,
1505 int idx,
1506 uint64_t va,
1507 gl_shader_stage stage)
1508 {
1509 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1510 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1511
1512 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1513 return;
1514
1515 assert(!desc_set_loc->indirect);
1516 assert(desc_set_loc->num_sgprs == 2);
1517 radeon_set_sh_reg_seq(cmd_buffer->cs,
1518 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1519 radeon_emit(cmd_buffer->cs, va);
1520 radeon_emit(cmd_buffer->cs, va >> 32);
1521 }
1522
1523 static void
1524 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1525 VkShaderStageFlags stages,
1526 struct radv_descriptor_set *set,
1527 unsigned idx)
1528 {
1529 if (cmd_buffer->state.pipeline) {
1530 radv_foreach_stage(stage, stages) {
1531 if (cmd_buffer->state.pipeline->shaders[stage])
1532 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1533 idx, set->va,
1534 stage);
1535 }
1536 }
1537
1538 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1539 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1540 idx, set->va,
1541 MESA_SHADER_COMPUTE);
1542 }
1543
1544 static void
1545 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1546 {
1547 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1548 unsigned bo_offset;
1549
1550 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1551 set->mapped_ptr,
1552 &bo_offset))
1553 return;
1554
1555 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1556 set->va += bo_offset;
1557 }
1558
1559 static void
1560 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1561 {
1562 uint32_t size = MAX_SETS * 2 * 4;
1563 uint32_t offset;
1564 void *ptr;
1565
1566 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1567 256, &offset, &ptr))
1568 return;
1569
1570 for (unsigned i = 0; i < MAX_SETS; i++) {
1571 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1572 uint64_t set_va = 0;
1573 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1574 if (set)
1575 set_va = set->va;
1576 uptr[0] = set_va & 0xffffffff;
1577 uptr[1] = set_va >> 32;
1578 }
1579
1580 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1581 va += offset;
1582
1583 if (cmd_buffer->state.pipeline) {
1584 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1585 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1586 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1587
1588 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1589 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1590 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1591
1592 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1593 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1594 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1595
1596 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1597 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1598 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1599
1600 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1601 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1602 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1603 }
1604
1605 if (cmd_buffer->state.compute_pipeline)
1606 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1607 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1608 }
1609
1610 static void
1611 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1612 VkShaderStageFlags stages)
1613 {
1614 unsigned i;
1615
1616 if (!cmd_buffer->state.descriptors_dirty)
1617 return;
1618
1619 if (cmd_buffer->state.push_descriptors_dirty)
1620 radv_flush_push_descriptors(cmd_buffer);
1621
1622 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1623 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1624 radv_flush_indirect_descriptor_sets(cmd_buffer);
1625 }
1626
1627 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1628 cmd_buffer->cs,
1629 MAX_SETS * MESA_SHADER_STAGES * 4);
1630
1631 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1632 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1633 if (!set)
1634 continue;
1635
1636 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1637 }
1638 cmd_buffer->state.descriptors_dirty = 0;
1639 cmd_buffer->state.push_descriptors_dirty = false;
1640
1641 radv_save_descriptors(cmd_buffer);
1642
1643 assert(cmd_buffer->cs->cdw <= cdw_max);
1644 }
1645
1646 static void
1647 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1648 struct radv_pipeline *pipeline,
1649 VkShaderStageFlags stages)
1650 {
1651 struct radv_pipeline_layout *layout = pipeline->layout;
1652 unsigned offset;
1653 void *ptr;
1654 uint64_t va;
1655
1656 stages &= cmd_buffer->push_constant_stages;
1657 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1658 return;
1659
1660 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1661 16 * layout->dynamic_offset_count,
1662 256, &offset, &ptr))
1663 return;
1664
1665 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1666 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1667 16 * layout->dynamic_offset_count);
1668
1669 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1670 va += offset;
1671
1672 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1673 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1674
1675 radv_foreach_stage(stage, stages) {
1676 if (pipeline->shaders[stage]) {
1677 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1678 AC_UD_PUSH_CONSTANTS, va);
1679 }
1680 }
1681
1682 cmd_buffer->push_constant_stages &= ~stages;
1683 assert(cmd_buffer->cs->cdw <= cdw_max);
1684 }
1685
1686 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1687 bool indexed_draw)
1688 {
1689 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1690
1691 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1692 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1693 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1694 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1695 primitive_reset_en);
1696 } else {
1697 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1698 primitive_reset_en);
1699 }
1700 }
1701
1702 if (primitive_reset_en) {
1703 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1704
1705 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1706 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1707 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1708 primitive_reset_index);
1709 }
1710 }
1711 }
1712
1713 static bool
1714 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1715 {
1716 struct radv_device *device = cmd_buffer->device;
1717
1718 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1719 cmd_buffer->state.pipeline->vertex_elements.count &&
1720 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1721 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1722 unsigned vb_offset;
1723 void *vb_ptr;
1724 uint32_t i = 0;
1725 uint32_t count = velems->count;
1726 uint64_t va;
1727
1728 /* allocate some descriptor state for vertex buffers */
1729 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1730 &vb_offset, &vb_ptr))
1731 return false;
1732
1733 for (i = 0; i < count; i++) {
1734 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1735 uint32_t offset;
1736 int vb = velems->binding[i];
1737 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1738 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1739
1740 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1741 va = radv_buffer_get_va(buffer->bo);
1742
1743 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1744 va += offset + buffer->offset;
1745 desc[0] = va;
1746 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1747 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1748 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1749 else
1750 desc[2] = buffer->size - offset;
1751 desc[3] = velems->rsrc_word3[i];
1752 }
1753
1754 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1755 va += vb_offset;
1756
1757 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1758 AC_UD_VS_VERTEX_BUFFERS, va);
1759 }
1760 cmd_buffer->state.vb_dirty = false;
1761
1762 return true;
1763 }
1764
1765 static void
1766 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1767 bool indexed_draw, bool instanced_draw,
1768 bool indirect_draw,
1769 uint32_t draw_vertex_count)
1770 {
1771 uint32_t ia_multi_vgt_param;
1772
1773 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1774 cmd_buffer->cs, 4096);
1775
1776 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1777 return;
1778
1779 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1780 radv_emit_graphics_pipeline(cmd_buffer);
1781
1782 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1783 radv_emit_framebuffer_state(cmd_buffer);
1784
1785 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
1786 radv_emit_index_buffer(cmd_buffer);
1787
1788 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1789 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1790 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1791 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1792 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1793 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1794 else
1795 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1796 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1797 }
1798
1799 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1800
1801 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1802
1803 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1804 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1805 VK_SHADER_STAGE_ALL_GRAPHICS);
1806
1807 assert(cmd_buffer->cs->cdw <= cdw_max);
1808
1809 si_emit_cache_flush(cmd_buffer);
1810
1811 cmd_buffer->state.dirty = 0;
1812 }
1813
1814 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1815 VkPipelineStageFlags src_stage_mask)
1816 {
1817 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1818 VK_PIPELINE_STAGE_TRANSFER_BIT |
1819 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1820 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1821 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1822 }
1823
1824 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1825 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1826 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1827 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1828 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1829 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1830 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1831 VK_PIPELINE_STAGE_TRANSFER_BIT |
1832 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1833 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1834 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1835 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1836 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1837 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1838 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1839 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1840 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1841 }
1842 }
1843
1844 static enum radv_cmd_flush_bits
1845 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1846 VkAccessFlags src_flags)
1847 {
1848 enum radv_cmd_flush_bits flush_bits = 0;
1849 uint32_t b;
1850 for_each_bit(b, src_flags) {
1851 switch ((VkAccessFlagBits)(1 << b)) {
1852 case VK_ACCESS_SHADER_WRITE_BIT:
1853 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1854 break;
1855 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1856 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1857 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1858 break;
1859 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1860 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1861 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1862 break;
1863 case VK_ACCESS_TRANSFER_WRITE_BIT:
1864 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1865 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1866 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1867 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1868 RADV_CMD_FLAG_INV_GLOBAL_L2;
1869 break;
1870 default:
1871 break;
1872 }
1873 }
1874 return flush_bits;
1875 }
1876
1877 static enum radv_cmd_flush_bits
1878 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1879 VkAccessFlags dst_flags,
1880 struct radv_image *image)
1881 {
1882 enum radv_cmd_flush_bits flush_bits = 0;
1883 uint32_t b;
1884 for_each_bit(b, dst_flags) {
1885 switch ((VkAccessFlagBits)(1 << b)) {
1886 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1887 case VK_ACCESS_INDEX_READ_BIT:
1888 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1889 break;
1890 case VK_ACCESS_UNIFORM_READ_BIT:
1891 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1892 break;
1893 case VK_ACCESS_SHADER_READ_BIT:
1894 case VK_ACCESS_TRANSFER_READ_BIT:
1895 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1896 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1897 RADV_CMD_FLAG_INV_GLOBAL_L2;
1898 break;
1899 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1900 /* TODO: change to image && when the image gets passed
1901 * through from the subpass. */
1902 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1903 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1904 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1905 break;
1906 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1907 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1908 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1909 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1910 break;
1911 default:
1912 break;
1913 }
1914 }
1915 return flush_bits;
1916 }
1917
1918 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1919 {
1920 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1921 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1922 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1923 NULL);
1924 }
1925
1926 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1927 VkAttachmentReference att)
1928 {
1929 unsigned idx = att.attachment;
1930 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1931 VkImageSubresourceRange range;
1932 range.aspectMask = 0;
1933 range.baseMipLevel = view->base_mip;
1934 range.levelCount = 1;
1935 range.baseArrayLayer = view->base_layer;
1936 range.layerCount = cmd_buffer->state.framebuffer->layers;
1937
1938 radv_handle_image_transition(cmd_buffer,
1939 view->image,
1940 cmd_buffer->state.attachments[idx].current_layout,
1941 att.layout, 0, 0, &range,
1942 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1943
1944 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1945
1946
1947 }
1948
1949 void
1950 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1951 const struct radv_subpass *subpass, bool transitions)
1952 {
1953 if (transitions) {
1954 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1955
1956 for (unsigned i = 0; i < subpass->color_count; ++i) {
1957 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1958 radv_handle_subpass_image_transition(cmd_buffer,
1959 subpass->color_attachments[i]);
1960 }
1961
1962 for (unsigned i = 0; i < subpass->input_count; ++i) {
1963 radv_handle_subpass_image_transition(cmd_buffer,
1964 subpass->input_attachments[i]);
1965 }
1966
1967 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1968 radv_handle_subpass_image_transition(cmd_buffer,
1969 subpass->depth_stencil_attachment);
1970 }
1971 }
1972
1973 cmd_buffer->state.subpass = subpass;
1974
1975 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1976 }
1977
1978 static VkResult
1979 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1980 struct radv_render_pass *pass,
1981 const VkRenderPassBeginInfo *info)
1982 {
1983 struct radv_cmd_state *state = &cmd_buffer->state;
1984
1985 if (pass->attachment_count == 0) {
1986 state->attachments = NULL;
1987 return VK_SUCCESS;
1988 }
1989
1990 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1991 pass->attachment_count *
1992 sizeof(state->attachments[0]),
1993 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1994 if (state->attachments == NULL) {
1995 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1996 return cmd_buffer->record_result;
1997 }
1998
1999 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2000 struct radv_render_pass_attachment *att = &pass->attachments[i];
2001 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2002 VkImageAspectFlags clear_aspects = 0;
2003
2004 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2005 /* color attachment */
2006 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2007 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2008 }
2009 } else {
2010 /* depthstencil attachment */
2011 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2012 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2013 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2014 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2015 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2016 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2017 }
2018 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2019 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2020 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2021 }
2022 }
2023
2024 state->attachments[i].pending_clear_aspects = clear_aspects;
2025 state->attachments[i].cleared_views = 0;
2026 if (clear_aspects && info) {
2027 assert(info->clearValueCount > i);
2028 state->attachments[i].clear_value = info->pClearValues[i];
2029 }
2030
2031 state->attachments[i].current_layout = att->initial_layout;
2032 }
2033
2034 return VK_SUCCESS;
2035 }
2036
2037 VkResult radv_AllocateCommandBuffers(
2038 VkDevice _device,
2039 const VkCommandBufferAllocateInfo *pAllocateInfo,
2040 VkCommandBuffer *pCommandBuffers)
2041 {
2042 RADV_FROM_HANDLE(radv_device, device, _device);
2043 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2044
2045 VkResult result = VK_SUCCESS;
2046 uint32_t i;
2047
2048 memset(pCommandBuffers, 0,
2049 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2050
2051 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2052
2053 if (!list_empty(&pool->free_cmd_buffers)) {
2054 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2055
2056 list_del(&cmd_buffer->pool_link);
2057 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2058
2059 result = radv_reset_cmd_buffer(cmd_buffer);
2060 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2061 cmd_buffer->level = pAllocateInfo->level;
2062
2063 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2064 } else {
2065 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2066 &pCommandBuffers[i]);
2067 }
2068 if (result != VK_SUCCESS)
2069 break;
2070 }
2071
2072 if (result != VK_SUCCESS)
2073 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2074 i, pCommandBuffers);
2075
2076 return result;
2077 }
2078
2079 void radv_FreeCommandBuffers(
2080 VkDevice device,
2081 VkCommandPool commandPool,
2082 uint32_t commandBufferCount,
2083 const VkCommandBuffer *pCommandBuffers)
2084 {
2085 for (uint32_t i = 0; i < commandBufferCount; i++) {
2086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2087
2088 if (cmd_buffer) {
2089 if (cmd_buffer->pool) {
2090 list_del(&cmd_buffer->pool_link);
2091 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2092 } else
2093 radv_cmd_buffer_destroy(cmd_buffer);
2094
2095 }
2096 }
2097 }
2098
2099 VkResult radv_ResetCommandBuffer(
2100 VkCommandBuffer commandBuffer,
2101 VkCommandBufferResetFlags flags)
2102 {
2103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2104 return radv_reset_cmd_buffer(cmd_buffer);
2105 }
2106
2107 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2108 {
2109 struct radv_device *device = cmd_buffer->device;
2110 if (device->gfx_init) {
2111 uint64_t va = radv_buffer_get_va(device->gfx_init);
2112 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2114 radeon_emit(cmd_buffer->cs, va);
2115 radeon_emit(cmd_buffer->cs, va >> 32);
2116 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2117 } else
2118 si_init_config(cmd_buffer);
2119 }
2120
2121 VkResult radv_BeginCommandBuffer(
2122 VkCommandBuffer commandBuffer,
2123 const VkCommandBufferBeginInfo *pBeginInfo)
2124 {
2125 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2126 VkResult result;
2127
2128 result = radv_reset_cmd_buffer(cmd_buffer);
2129 if (result != VK_SUCCESS)
2130 return result;
2131
2132 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2133 cmd_buffer->state.last_primitive_reset_en = -1;
2134 cmd_buffer->usage_flags = pBeginInfo->flags;
2135
2136 /* setup initial configuration into command buffer */
2137 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2138 switch (cmd_buffer->queue_family_index) {
2139 case RADV_QUEUE_GENERAL:
2140 emit_gfx_buffer_state(cmd_buffer);
2141 radv_set_db_count_control(cmd_buffer);
2142 break;
2143 case RADV_QUEUE_COMPUTE:
2144 si_init_compute(cmd_buffer);
2145 break;
2146 case RADV_QUEUE_TRANSFER:
2147 default:
2148 break;
2149 }
2150 }
2151
2152 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2153 assert(pBeginInfo->pInheritanceInfo);
2154 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2155 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2156
2157 struct radv_subpass *subpass =
2158 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2159
2160 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2161 if (result != VK_SUCCESS)
2162 return result;
2163
2164 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2165 }
2166
2167 radv_cmd_buffer_trace_emit(cmd_buffer);
2168 return result;
2169 }
2170
2171 void radv_CmdBindVertexBuffers(
2172 VkCommandBuffer commandBuffer,
2173 uint32_t firstBinding,
2174 uint32_t bindingCount,
2175 const VkBuffer* pBuffers,
2176 const VkDeviceSize* pOffsets)
2177 {
2178 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2179 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2180
2181 /* We have to defer setting up vertex buffer since we need the buffer
2182 * stride from the pipeline. */
2183
2184 assert(firstBinding + bindingCount <= MAX_VBS);
2185 for (uint32_t i = 0; i < bindingCount; i++) {
2186 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2187 vb[firstBinding + i].offset = pOffsets[i];
2188 }
2189
2190 cmd_buffer->state.vb_dirty = true;
2191 }
2192
2193 void radv_CmdBindIndexBuffer(
2194 VkCommandBuffer commandBuffer,
2195 VkBuffer buffer,
2196 VkDeviceSize offset,
2197 VkIndexType indexType)
2198 {
2199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2200 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2201
2202 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2203 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2204 cmd_buffer->state.index_va += index_buffer->offset + offset;
2205
2206 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2207 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2208 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2209 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2210 }
2211
2212
2213 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2214 struct radv_descriptor_set *set,
2215 unsigned idx)
2216 {
2217 struct radeon_winsys *ws = cmd_buffer->device->ws;
2218
2219 cmd_buffer->state.descriptors[idx] = set;
2220 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2221 if (!set)
2222 return;
2223
2224 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2225
2226 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2227 if (set->descriptors[j])
2228 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2229
2230 if(set->bo)
2231 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2232 }
2233
2234 void radv_CmdBindDescriptorSets(
2235 VkCommandBuffer commandBuffer,
2236 VkPipelineBindPoint pipelineBindPoint,
2237 VkPipelineLayout _layout,
2238 uint32_t firstSet,
2239 uint32_t descriptorSetCount,
2240 const VkDescriptorSet* pDescriptorSets,
2241 uint32_t dynamicOffsetCount,
2242 const uint32_t* pDynamicOffsets)
2243 {
2244 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2245 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2246 unsigned dyn_idx = 0;
2247
2248 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2249 unsigned idx = i + firstSet;
2250 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2251 radv_bind_descriptor_set(cmd_buffer, set, idx);
2252
2253 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2254 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2255 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2256 assert(dyn_idx < dynamicOffsetCount);
2257
2258 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2259 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2260 dst[0] = va;
2261 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2262 dst[2] = range->size;
2263 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2264 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2265 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2266 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2267 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2268 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2269 cmd_buffer->push_constant_stages |=
2270 set->layout->dynamic_shader_stages;
2271 }
2272 }
2273 }
2274
2275 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2276 struct radv_descriptor_set *set,
2277 struct radv_descriptor_set_layout *layout)
2278 {
2279 set->size = layout->size;
2280 set->layout = layout;
2281
2282 if (cmd_buffer->push_descriptors.capacity < set->size) {
2283 size_t new_size = MAX2(set->size, 1024);
2284 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2285 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2286
2287 free(set->mapped_ptr);
2288 set->mapped_ptr = malloc(new_size);
2289
2290 if (!set->mapped_ptr) {
2291 cmd_buffer->push_descriptors.capacity = 0;
2292 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2293 return false;
2294 }
2295
2296 cmd_buffer->push_descriptors.capacity = new_size;
2297 }
2298
2299 return true;
2300 }
2301
2302 void radv_meta_push_descriptor_set(
2303 struct radv_cmd_buffer* cmd_buffer,
2304 VkPipelineBindPoint pipelineBindPoint,
2305 VkPipelineLayout _layout,
2306 uint32_t set,
2307 uint32_t descriptorWriteCount,
2308 const VkWriteDescriptorSet* pDescriptorWrites)
2309 {
2310 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2311 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2312 unsigned bo_offset;
2313
2314 assert(set == 0);
2315 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2316
2317 push_set->size = layout->set[set].layout->size;
2318 push_set->layout = layout->set[set].layout;
2319
2320 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2321 &bo_offset,
2322 (void**) &push_set->mapped_ptr))
2323 return;
2324
2325 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2326 push_set->va += bo_offset;
2327
2328 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2329 radv_descriptor_set_to_handle(push_set),
2330 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2331
2332 cmd_buffer->state.descriptors[set] = push_set;
2333 cmd_buffer->state.descriptors_dirty |= (1u << set);
2334 }
2335
2336 void radv_CmdPushDescriptorSetKHR(
2337 VkCommandBuffer commandBuffer,
2338 VkPipelineBindPoint pipelineBindPoint,
2339 VkPipelineLayout _layout,
2340 uint32_t set,
2341 uint32_t descriptorWriteCount,
2342 const VkWriteDescriptorSet* pDescriptorWrites)
2343 {
2344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2345 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2346 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2347
2348 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2349
2350 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2351 return;
2352
2353 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2354 radv_descriptor_set_to_handle(push_set),
2355 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2356
2357 cmd_buffer->state.descriptors[set] = push_set;
2358 cmd_buffer->state.descriptors_dirty |= (1u << set);
2359 cmd_buffer->state.push_descriptors_dirty = true;
2360 }
2361
2362 void radv_CmdPushDescriptorSetWithTemplateKHR(
2363 VkCommandBuffer commandBuffer,
2364 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2365 VkPipelineLayout _layout,
2366 uint32_t set,
2367 const void* pData)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2370 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2371 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2372
2373 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2374
2375 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2376 return;
2377
2378 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2379 descriptorUpdateTemplate, pData);
2380
2381 cmd_buffer->state.descriptors[set] = push_set;
2382 cmd_buffer->state.descriptors_dirty |= (1u << set);
2383 cmd_buffer->state.push_descriptors_dirty = true;
2384 }
2385
2386 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2387 VkPipelineLayout layout,
2388 VkShaderStageFlags stageFlags,
2389 uint32_t offset,
2390 uint32_t size,
2391 const void* pValues)
2392 {
2393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2394 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2395 cmd_buffer->push_constant_stages |= stageFlags;
2396 }
2397
2398 VkResult radv_EndCommandBuffer(
2399 VkCommandBuffer commandBuffer)
2400 {
2401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2402
2403 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2404 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2405 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2406 si_emit_cache_flush(cmd_buffer);
2407 }
2408
2409 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2410 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2411
2412 return cmd_buffer->record_result;
2413 }
2414
2415 static void
2416 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2417 {
2418 struct radeon_winsys *ws = cmd_buffer->device->ws;
2419 struct radv_shader_variant *compute_shader;
2420 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2421 uint64_t va;
2422
2423 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2424 return;
2425
2426 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2427
2428 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2429 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2430
2431 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2432 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2433
2434 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2435 cmd_buffer->cs, 16);
2436
2437 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2438 radeon_emit(cmd_buffer->cs, va >> 8);
2439 radeon_emit(cmd_buffer->cs, va >> 40);
2440
2441 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2442 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2443 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2444
2445
2446 cmd_buffer->compute_scratch_size_needed =
2447 MAX2(cmd_buffer->compute_scratch_size_needed,
2448 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2449
2450 /* change these once we have scratch support */
2451 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2452 S_00B860_WAVES(pipeline->max_waves) |
2453 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2454
2455 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2456 radeon_emit(cmd_buffer->cs,
2457 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2458 radeon_emit(cmd_buffer->cs,
2459 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2460 radeon_emit(cmd_buffer->cs,
2461 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2462
2463 assert(cmd_buffer->cs->cdw <= cdw_max);
2464 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2465 }
2466
2467 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2468 {
2469 for (unsigned i = 0; i < MAX_SETS; i++) {
2470 if (cmd_buffer->state.descriptors[i])
2471 cmd_buffer->state.descriptors_dirty |= (1u << i);
2472 }
2473 }
2474
2475 void radv_CmdBindPipeline(
2476 VkCommandBuffer commandBuffer,
2477 VkPipelineBindPoint pipelineBindPoint,
2478 VkPipeline _pipeline)
2479 {
2480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2481 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2482
2483 switch (pipelineBindPoint) {
2484 case VK_PIPELINE_BIND_POINT_COMPUTE:
2485 if (cmd_buffer->state.compute_pipeline == pipeline)
2486 return;
2487 radv_mark_descriptor_sets_dirty(cmd_buffer);
2488
2489 cmd_buffer->state.compute_pipeline = pipeline;
2490 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2491 break;
2492 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2493 if (cmd_buffer->state.pipeline == pipeline)
2494 return;
2495 radv_mark_descriptor_sets_dirty(cmd_buffer);
2496
2497 cmd_buffer->state.pipeline = pipeline;
2498 if (!pipeline)
2499 break;
2500
2501 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2502 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2503
2504 /* Apply the dynamic state from the pipeline */
2505 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2506 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2507 &pipeline->dynamic_state,
2508 pipeline->dynamic_state_mask);
2509
2510 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2511 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2512 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2513 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2514
2515 if (radv_pipeline_has_tess(pipeline))
2516 cmd_buffer->tess_rings_needed = true;
2517
2518 if (radv_pipeline_has_gs(pipeline)) {
2519 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2520 AC_UD_SCRATCH_RING_OFFSETS);
2521 if (cmd_buffer->ring_offsets_idx == -1)
2522 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2523 else if (loc->sgpr_idx != -1)
2524 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2525 }
2526 break;
2527 default:
2528 assert(!"invalid bind point");
2529 break;
2530 }
2531 }
2532
2533 void radv_CmdSetViewport(
2534 VkCommandBuffer commandBuffer,
2535 uint32_t firstViewport,
2536 uint32_t viewportCount,
2537 const VkViewport* pViewports)
2538 {
2539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2540 const uint32_t total_count = firstViewport + viewportCount;
2541
2542 assert(firstViewport < MAX_VIEWPORTS);
2543 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2544
2545 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2546 pViewports, viewportCount * sizeof(*pViewports));
2547
2548 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2549 }
2550
2551 void radv_CmdSetScissor(
2552 VkCommandBuffer commandBuffer,
2553 uint32_t firstScissor,
2554 uint32_t scissorCount,
2555 const VkRect2D* pScissors)
2556 {
2557 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2558 const uint32_t total_count = firstScissor + scissorCount;
2559
2560 assert(firstScissor < MAX_SCISSORS);
2561 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2562
2563 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2564 pScissors, scissorCount * sizeof(*pScissors));
2565 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2566 }
2567
2568 void radv_CmdSetLineWidth(
2569 VkCommandBuffer commandBuffer,
2570 float lineWidth)
2571 {
2572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2573 cmd_buffer->state.dynamic.line_width = lineWidth;
2574 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2575 }
2576
2577 void radv_CmdSetDepthBias(
2578 VkCommandBuffer commandBuffer,
2579 float depthBiasConstantFactor,
2580 float depthBiasClamp,
2581 float depthBiasSlopeFactor)
2582 {
2583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584
2585 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2586 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2587 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2588
2589 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2590 }
2591
2592 void radv_CmdSetBlendConstants(
2593 VkCommandBuffer commandBuffer,
2594 const float blendConstants[4])
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597
2598 memcpy(cmd_buffer->state.dynamic.blend_constants,
2599 blendConstants, sizeof(float) * 4);
2600
2601 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2602 }
2603
2604 void radv_CmdSetDepthBounds(
2605 VkCommandBuffer commandBuffer,
2606 float minDepthBounds,
2607 float maxDepthBounds)
2608 {
2609 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2610
2611 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2612 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2613
2614 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2615 }
2616
2617 void radv_CmdSetStencilCompareMask(
2618 VkCommandBuffer commandBuffer,
2619 VkStencilFaceFlags faceMask,
2620 uint32_t compareMask)
2621 {
2622 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2623
2624 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2625 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2626 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2627 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2628
2629 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2630 }
2631
2632 void radv_CmdSetStencilWriteMask(
2633 VkCommandBuffer commandBuffer,
2634 VkStencilFaceFlags faceMask,
2635 uint32_t writeMask)
2636 {
2637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2638
2639 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2640 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2641 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2642 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2643
2644 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2645 }
2646
2647 void radv_CmdSetStencilReference(
2648 VkCommandBuffer commandBuffer,
2649 VkStencilFaceFlags faceMask,
2650 uint32_t reference)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653
2654 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2655 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2656 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2657 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2658
2659 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2660 }
2661
2662 void radv_CmdExecuteCommands(
2663 VkCommandBuffer commandBuffer,
2664 uint32_t commandBufferCount,
2665 const VkCommandBuffer* pCmdBuffers)
2666 {
2667 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2668
2669 assert(commandBufferCount > 0);
2670
2671 /* Emit pending flushes on primary prior to executing secondary */
2672 si_emit_cache_flush(primary);
2673
2674 for (uint32_t i = 0; i < commandBufferCount; i++) {
2675 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2676
2677 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2678 secondary->scratch_size_needed);
2679 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2680 secondary->compute_scratch_size_needed);
2681
2682 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2683 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2684 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2685 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2686 if (secondary->tess_rings_needed)
2687 primary->tess_rings_needed = true;
2688 if (secondary->sample_positions_needed)
2689 primary->sample_positions_needed = true;
2690
2691 if (secondary->ring_offsets_idx != -1) {
2692 if (primary->ring_offsets_idx == -1)
2693 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2694 else
2695 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2696 }
2697 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2698
2699
2700 /* When the secondary command buffer is compute only we don't
2701 * need to re-emit the current graphics pipeline.
2702 */
2703 if (secondary->state.emitted_pipeline) {
2704 primary->state.emitted_pipeline =
2705 secondary->state.emitted_pipeline;
2706 }
2707
2708 /* When the secondary command buffer is graphics only we don't
2709 * need to re-emit the current compute pipeline.
2710 */
2711 if (secondary->state.emitted_compute_pipeline) {
2712 primary->state.emitted_compute_pipeline =
2713 secondary->state.emitted_compute_pipeline;
2714 }
2715
2716 /* Only re-emit the draw packets when needed. */
2717 if (secondary->state.last_primitive_reset_en != -1) {
2718 primary->state.last_primitive_reset_en =
2719 secondary->state.last_primitive_reset_en;
2720 }
2721
2722 if (secondary->state.last_primitive_reset_index) {
2723 primary->state.last_primitive_reset_index =
2724 secondary->state.last_primitive_reset_index;
2725 }
2726
2727 if (secondary->state.last_ia_multi_vgt_param) {
2728 primary->state.last_ia_multi_vgt_param =
2729 secondary->state.last_ia_multi_vgt_param;
2730 }
2731 }
2732
2733 /* After executing commands from secondary buffers we have to dirty
2734 * some states.
2735 */
2736 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2737 RADV_CMD_DIRTY_INDEX_BUFFER |
2738 RADV_CMD_DIRTY_DYNAMIC_ALL;
2739 radv_mark_descriptor_sets_dirty(primary);
2740 }
2741
2742 VkResult radv_CreateCommandPool(
2743 VkDevice _device,
2744 const VkCommandPoolCreateInfo* pCreateInfo,
2745 const VkAllocationCallbacks* pAllocator,
2746 VkCommandPool* pCmdPool)
2747 {
2748 RADV_FROM_HANDLE(radv_device, device, _device);
2749 struct radv_cmd_pool *pool;
2750
2751 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2752 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2753 if (pool == NULL)
2754 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2755
2756 if (pAllocator)
2757 pool->alloc = *pAllocator;
2758 else
2759 pool->alloc = device->alloc;
2760
2761 list_inithead(&pool->cmd_buffers);
2762 list_inithead(&pool->free_cmd_buffers);
2763
2764 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2765
2766 *pCmdPool = radv_cmd_pool_to_handle(pool);
2767
2768 return VK_SUCCESS;
2769
2770 }
2771
2772 void radv_DestroyCommandPool(
2773 VkDevice _device,
2774 VkCommandPool commandPool,
2775 const VkAllocationCallbacks* pAllocator)
2776 {
2777 RADV_FROM_HANDLE(radv_device, device, _device);
2778 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2779
2780 if (!pool)
2781 return;
2782
2783 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2784 &pool->cmd_buffers, pool_link) {
2785 radv_cmd_buffer_destroy(cmd_buffer);
2786 }
2787
2788 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2789 &pool->free_cmd_buffers, pool_link) {
2790 radv_cmd_buffer_destroy(cmd_buffer);
2791 }
2792
2793 vk_free2(&device->alloc, pAllocator, pool);
2794 }
2795
2796 VkResult radv_ResetCommandPool(
2797 VkDevice device,
2798 VkCommandPool commandPool,
2799 VkCommandPoolResetFlags flags)
2800 {
2801 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2802 VkResult result;
2803
2804 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2805 &pool->cmd_buffers, pool_link) {
2806 result = radv_reset_cmd_buffer(cmd_buffer);
2807 if (result != VK_SUCCESS)
2808 return result;
2809 }
2810
2811 return VK_SUCCESS;
2812 }
2813
2814 void radv_TrimCommandPoolKHR(
2815 VkDevice device,
2816 VkCommandPool commandPool,
2817 VkCommandPoolTrimFlagsKHR flags)
2818 {
2819 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2820
2821 if (!pool)
2822 return;
2823
2824 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2825 &pool->free_cmd_buffers, pool_link) {
2826 radv_cmd_buffer_destroy(cmd_buffer);
2827 }
2828 }
2829
2830 void radv_CmdBeginRenderPass(
2831 VkCommandBuffer commandBuffer,
2832 const VkRenderPassBeginInfo* pRenderPassBegin,
2833 VkSubpassContents contents)
2834 {
2835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2836 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2837 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2838
2839 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2840 cmd_buffer->cs, 2048);
2841 MAYBE_UNUSED VkResult result;
2842
2843 cmd_buffer->state.framebuffer = framebuffer;
2844 cmd_buffer->state.pass = pass;
2845 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2846
2847 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2848 if (result != VK_SUCCESS)
2849 return;
2850
2851 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2852 assert(cmd_buffer->cs->cdw <= cdw_max);
2853
2854 radv_cmd_buffer_clear_subpass(cmd_buffer);
2855 }
2856
2857 void radv_CmdNextSubpass(
2858 VkCommandBuffer commandBuffer,
2859 VkSubpassContents contents)
2860 {
2861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2862
2863 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2864
2865 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2866 2048);
2867
2868 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2869 radv_cmd_buffer_clear_subpass(cmd_buffer);
2870 }
2871
2872 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2873 {
2874 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2875 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2876 if (!pipeline->shaders[stage])
2877 continue;
2878 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2879 if (loc->sgpr_idx == -1)
2880 continue;
2881 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2882 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2883
2884 }
2885 if (pipeline->gs_copy_shader) {
2886 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2887 if (loc->sgpr_idx != -1) {
2888 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2889 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2890 }
2891 }
2892 }
2893
2894 static void
2895 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2896 uint32_t vertex_count)
2897 {
2898 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2899 radeon_emit(cmd_buffer->cs, vertex_count);
2900 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2901 S_0287F0_USE_OPAQUE(0));
2902 }
2903
2904 void radv_CmdDraw(
2905 VkCommandBuffer commandBuffer,
2906 uint32_t vertexCount,
2907 uint32_t instanceCount,
2908 uint32_t firstVertex,
2909 uint32_t firstInstance)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2912
2913 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2914
2915 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2916
2917 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2918 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2919 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2920 radeon_emit(cmd_buffer->cs, firstVertex);
2921 radeon_emit(cmd_buffer->cs, firstInstance);
2922 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2923 radeon_emit(cmd_buffer->cs, 0);
2924
2925 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2926 radeon_emit(cmd_buffer->cs, instanceCount);
2927
2928 if (!cmd_buffer->state.subpass->view_mask) {
2929 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2930 } else {
2931 unsigned i;
2932 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2933 radv_emit_view_index(cmd_buffer, i);
2934
2935 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2936 }
2937 }
2938
2939 assert(cmd_buffer->cs->cdw <= cdw_max);
2940
2941 radv_cmd_buffer_after_draw(cmd_buffer);
2942 }
2943
2944
2945 static void
2946 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2947 uint64_t index_va,
2948 uint32_t index_count)
2949 {
2950 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2951 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2952 radeon_emit(cmd_buffer->cs, index_va);
2953 radeon_emit(cmd_buffer->cs, index_va >> 32);
2954 radeon_emit(cmd_buffer->cs, index_count);
2955 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2956 }
2957
2958 void radv_CmdDrawIndexed(
2959 VkCommandBuffer commandBuffer,
2960 uint32_t indexCount,
2961 uint32_t instanceCount,
2962 uint32_t firstIndex,
2963 int32_t vertexOffset,
2964 uint32_t firstInstance)
2965 {
2966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2967 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2968 uint64_t index_va;
2969
2970 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2971
2972 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2973
2974 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2975 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2976 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2977 radeon_emit(cmd_buffer->cs, vertexOffset);
2978 radeon_emit(cmd_buffer->cs, firstInstance);
2979 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2980 radeon_emit(cmd_buffer->cs, 0);
2981
2982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2983 radeon_emit(cmd_buffer->cs, instanceCount);
2984
2985 index_va = cmd_buffer->state.index_va;
2986 index_va += firstIndex * index_size;
2987 if (!cmd_buffer->state.subpass->view_mask) {
2988 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2989 } else {
2990 unsigned i;
2991 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2992 radv_emit_view_index(cmd_buffer, i);
2993
2994 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2995 }
2996 }
2997
2998 assert(cmd_buffer->cs->cdw <= cdw_max);
2999 radv_cmd_buffer_after_draw(cmd_buffer);
3000 }
3001
3002 static void
3003 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3004 bool indexed,
3005 uint32_t draw_count,
3006 uint64_t count_va,
3007 uint32_t stride)
3008 {
3009 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3010 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3011 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3012 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3013 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3014 assert(base_reg);
3015
3016 if (draw_count == 1 && !count_va && !draw_id_enable) {
3017 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3018 PKT3_DRAW_INDIRECT, 3, false));
3019 radeon_emit(cs, 0);
3020 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3021 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3022 radeon_emit(cs, di_src_sel);
3023 } else {
3024 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3025 PKT3_DRAW_INDIRECT_MULTI,
3026 8, false));
3027 radeon_emit(cs, 0);
3028 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3029 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3030 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3031 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3032 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3033 radeon_emit(cs, draw_count); /* count */
3034 radeon_emit(cs, count_va); /* count_addr */
3035 radeon_emit(cs, count_va >> 32);
3036 radeon_emit(cs, stride); /* stride */
3037 radeon_emit(cs, di_src_sel);
3038 }
3039 }
3040
3041 static void
3042 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
3043 VkBuffer _buffer,
3044 VkDeviceSize offset,
3045 VkBuffer _count_buffer,
3046 VkDeviceSize count_offset,
3047 uint32_t draw_count,
3048 uint32_t stride,
3049 bool indexed)
3050 {
3051 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3052 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
3053 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3054
3055 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
3056 indirect_va += offset + buffer->offset;
3057 uint64_t count_va = 0;
3058
3059 if (count_buffer) {
3060 count_va = radv_buffer_get_va(count_buffer->bo);
3061 count_va += count_offset + count_buffer->offset;
3062
3063 cmd_buffer->device->ws->cs_add_buffer(cs, count_buffer->bo, 8);
3064 }
3065
3066 if (!draw_count)
3067 return;
3068
3069 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3070
3071 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3072 radeon_emit(cs, 1);
3073 radeon_emit(cs, indirect_va);
3074 radeon_emit(cs, indirect_va >> 32);
3075
3076 if (!cmd_buffer->state.subpass->view_mask) {
3077 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3078 } else {
3079 unsigned i;
3080 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3081 radv_emit_view_index(cmd_buffer, i);
3082
3083 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3084 }
3085 }
3086 radv_cmd_buffer_after_draw(cmd_buffer);
3087 }
3088
3089 static void
3090 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3091 VkBuffer buffer,
3092 VkDeviceSize offset,
3093 VkBuffer countBuffer,
3094 VkDeviceSize countBufferOffset,
3095 uint32_t maxDrawCount,
3096 uint32_t stride)
3097 {
3098 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3099 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3100
3101 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3102 cmd_buffer->cs, 24 * MAX_VIEWS);
3103
3104 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3105 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3106
3107 assert(cmd_buffer->cs->cdw <= cdw_max);
3108 }
3109
3110 static void
3111 radv_cmd_draw_indexed_indirect_count(
3112 VkCommandBuffer commandBuffer,
3113 VkBuffer buffer,
3114 VkDeviceSize offset,
3115 VkBuffer countBuffer,
3116 VkDeviceSize countBufferOffset,
3117 uint32_t maxDrawCount,
3118 uint32_t stride)
3119 {
3120 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3121
3122 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3123
3124 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3125
3126 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3127 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3128
3129 assert(cmd_buffer->cs->cdw <= cdw_max);
3130 }
3131
3132 void radv_CmdDrawIndirect(
3133 VkCommandBuffer commandBuffer,
3134 VkBuffer buffer,
3135 VkDeviceSize offset,
3136 uint32_t drawCount,
3137 uint32_t stride)
3138 {
3139 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3140 VK_NULL_HANDLE, 0, drawCount, stride);
3141 }
3142
3143 void radv_CmdDrawIndexedIndirect(
3144 VkCommandBuffer commandBuffer,
3145 VkBuffer buffer,
3146 VkDeviceSize offset,
3147 uint32_t drawCount,
3148 uint32_t stride)
3149 {
3150 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3151 VK_NULL_HANDLE, 0, drawCount, stride);
3152 }
3153
3154 void radv_CmdDrawIndirectCountAMD(
3155 VkCommandBuffer commandBuffer,
3156 VkBuffer buffer,
3157 VkDeviceSize offset,
3158 VkBuffer countBuffer,
3159 VkDeviceSize countBufferOffset,
3160 uint32_t maxDrawCount,
3161 uint32_t stride)
3162 {
3163 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3164 countBuffer, countBufferOffset,
3165 maxDrawCount, stride);
3166 }
3167
3168 void radv_CmdDrawIndexedIndirectCountAMD(
3169 VkCommandBuffer commandBuffer,
3170 VkBuffer buffer,
3171 VkDeviceSize offset,
3172 VkBuffer countBuffer,
3173 VkDeviceSize countBufferOffset,
3174 uint32_t maxDrawCount,
3175 uint32_t stride)
3176 {
3177 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3178 countBuffer, countBufferOffset,
3179 maxDrawCount, stride);
3180 }
3181
3182 struct radv_dispatch_info {
3183 /**
3184 * Determine the layout of the grid (in block units) to be used.
3185 */
3186 uint32_t blocks[3];
3187
3188 /**
3189 * Whether it's an unaligned compute dispatch.
3190 */
3191 bool unaligned;
3192
3193 /**
3194 * Indirect compute parameters resource.
3195 */
3196 struct radv_buffer *indirect;
3197 uint64_t indirect_offset;
3198 };
3199
3200 static void
3201 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3202 const struct radv_dispatch_info *info)
3203 {
3204 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3205 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3206 struct radeon_winsys *ws = cmd_buffer->device->ws;
3207 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3208 struct ac_userdata_info *loc;
3209 unsigned dispatch_initiator;
3210 uint8_t grid_used;
3211
3212 grid_used = compute_shader->info.info.cs.grid_components_used;
3213
3214 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3215 AC_UD_CS_GRID_SIZE);
3216
3217 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3218
3219 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3220 S_00B800_FORCE_START_AT_000(1);
3221
3222 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3223 /* If the KMD allows it (there is a KMD hw register for it),
3224 * allow launching waves out-of-order.
3225 */
3226 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3227 }
3228
3229 if (info->indirect) {
3230 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3231
3232 va += info->indirect->offset + info->indirect_offset;
3233
3234 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3235
3236 if (loc->sgpr_idx != -1) {
3237 for (unsigned i = 0; i < grid_used; ++i) {
3238 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3239 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3240 COPY_DATA_DST_SEL(COPY_DATA_REG));
3241 radeon_emit(cs, (va + 4 * i));
3242 radeon_emit(cs, (va + 4 * i) >> 32);
3243 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3244 + loc->sgpr_idx * 4) >> 2) + i);
3245 radeon_emit(cs, 0);
3246 }
3247 }
3248
3249 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3250 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3251 PKT3_SHADER_TYPE_S(1));
3252 radeon_emit(cs, va);
3253 radeon_emit(cs, va >> 32);
3254 radeon_emit(cs, dispatch_initiator);
3255 } else {
3256 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3257 PKT3_SHADER_TYPE_S(1));
3258 radeon_emit(cs, 1);
3259 radeon_emit(cs, va);
3260 radeon_emit(cs, va >> 32);
3261
3262 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3263 PKT3_SHADER_TYPE_S(1));
3264 radeon_emit(cs, 0);
3265 radeon_emit(cs, dispatch_initiator);
3266 }
3267 } else {
3268 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3269
3270 if (info->unaligned) {
3271 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3272 unsigned remainder[3];
3273
3274 /* If aligned, these should be an entire block size,
3275 * not 0.
3276 */
3277 remainder[0] = blocks[0] + cs_block_size[0] -
3278 align_u32_npot(blocks[0], cs_block_size[0]);
3279 remainder[1] = blocks[1] + cs_block_size[1] -
3280 align_u32_npot(blocks[1], cs_block_size[1]);
3281 remainder[2] = blocks[2] + cs_block_size[2] -
3282 align_u32_npot(blocks[2], cs_block_size[2]);
3283
3284 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3285 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3286 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3287
3288 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3289 radeon_emit(cs,
3290 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3291 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3292 radeon_emit(cs,
3293 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3294 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3295 radeon_emit(cs,
3296 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3297 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3298
3299 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3300 }
3301
3302 if (loc->sgpr_idx != -1) {
3303 assert(!loc->indirect);
3304 assert(loc->num_sgprs == grid_used);
3305
3306 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3307 loc->sgpr_idx * 4, grid_used);
3308 radeon_emit(cs, blocks[0]);
3309 if (grid_used > 1)
3310 radeon_emit(cs, blocks[1]);
3311 if (grid_used > 2)
3312 radeon_emit(cs, blocks[2]);
3313 }
3314
3315 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3316 PKT3_SHADER_TYPE_S(1));
3317 radeon_emit(cs, blocks[0]);
3318 radeon_emit(cs, blocks[1]);
3319 radeon_emit(cs, blocks[2]);
3320 radeon_emit(cs, dispatch_initiator);
3321 }
3322
3323 assert(cmd_buffer->cs->cdw <= cdw_max);
3324 }
3325
3326 static void
3327 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3328 const struct radv_dispatch_info *info)
3329 {
3330 radv_emit_compute_pipeline(cmd_buffer);
3331
3332 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3333 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3334 VK_SHADER_STAGE_COMPUTE_BIT);
3335
3336 si_emit_cache_flush(cmd_buffer);
3337
3338 radv_emit_dispatch_packets(cmd_buffer, info);
3339
3340 radv_cmd_buffer_after_draw(cmd_buffer);
3341 }
3342
3343 void radv_CmdDispatch(
3344 VkCommandBuffer commandBuffer,
3345 uint32_t x,
3346 uint32_t y,
3347 uint32_t z)
3348 {
3349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3350 struct radv_dispatch_info info = {};
3351
3352 info.blocks[0] = x;
3353 info.blocks[1] = y;
3354 info.blocks[2] = z;
3355
3356 radv_dispatch(cmd_buffer, &info);
3357 }
3358
3359 void radv_CmdDispatchIndirect(
3360 VkCommandBuffer commandBuffer,
3361 VkBuffer _buffer,
3362 VkDeviceSize offset)
3363 {
3364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3365 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3366 struct radv_dispatch_info info = {};
3367
3368 info.indirect = buffer;
3369 info.indirect_offset = offset;
3370
3371 radv_dispatch(cmd_buffer, &info);
3372 }
3373
3374 void radv_unaligned_dispatch(
3375 struct radv_cmd_buffer *cmd_buffer,
3376 uint32_t x,
3377 uint32_t y,
3378 uint32_t z)
3379 {
3380 struct radv_dispatch_info info = {};
3381
3382 info.blocks[0] = x;
3383 info.blocks[1] = y;
3384 info.blocks[2] = z;
3385 info.unaligned = 1;
3386
3387 radv_dispatch(cmd_buffer, &info);
3388 }
3389
3390 void radv_CmdEndRenderPass(
3391 VkCommandBuffer commandBuffer)
3392 {
3393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3394
3395 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3396
3397 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3398
3399 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3400 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3401 radv_handle_subpass_image_transition(cmd_buffer,
3402 (VkAttachmentReference){i, layout});
3403 }
3404
3405 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3406
3407 cmd_buffer->state.pass = NULL;
3408 cmd_buffer->state.subpass = NULL;
3409 cmd_buffer->state.attachments = NULL;
3410 cmd_buffer->state.framebuffer = NULL;
3411 }
3412
3413 /*
3414 * For HTILE we have the following interesting clear words:
3415 * 0x0000030f: Uncompressed.
3416 * 0xfffffff0: Clear depth to 1.0
3417 * 0x00000000: Clear depth to 0.0
3418 */
3419 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3420 struct radv_image *image,
3421 const VkImageSubresourceRange *range,
3422 uint32_t clear_word)
3423 {
3424 assert(range->baseMipLevel == 0);
3425 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3426 unsigned layer_count = radv_get_layerCount(image, range);
3427 uint64_t size = image->surface.htile_slice_size * layer_count;
3428 uint64_t offset = image->offset + image->htile_offset +
3429 image->surface.htile_slice_size * range->baseArrayLayer;
3430
3431 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3432 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3433
3434 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3435
3436 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3437 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3438 RADV_CMD_FLAG_INV_VMEM_L1 |
3439 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3440 }
3441
3442 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3443 struct radv_image *image,
3444 VkImageLayout src_layout,
3445 VkImageLayout dst_layout,
3446 unsigned src_queue_mask,
3447 unsigned dst_queue_mask,
3448 const VkImageSubresourceRange *range,
3449 VkImageAspectFlags pending_clears)
3450 {
3451 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3452 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3453 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3454 cmd_buffer->state.render_area.extent.width == image->info.width &&
3455 cmd_buffer->state.render_area.extent.height == image->info.height) {
3456 /* The clear will initialize htile. */
3457 return;
3458 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3459 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3460 /* TODO: merge with the clear if applicable */
3461 radv_initialize_htile(cmd_buffer, image, range, 0);
3462 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3463 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3464 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3465 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3466 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3467 VkImageSubresourceRange local_range = *range;
3468 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3469 local_range.baseMipLevel = 0;
3470 local_range.levelCount = 1;
3471
3472 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3473 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3474
3475 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3476
3477 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3478 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3479 }
3480 }
3481
3482 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3483 struct radv_image *image, uint32_t value)
3484 {
3485 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3486 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3487
3488 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3489 image->cmask.size, value);
3490
3491 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3492 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3493 RADV_CMD_FLAG_INV_VMEM_L1 |
3494 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3495 }
3496
3497 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3498 struct radv_image *image,
3499 VkImageLayout src_layout,
3500 VkImageLayout dst_layout,
3501 unsigned src_queue_mask,
3502 unsigned dst_queue_mask,
3503 const VkImageSubresourceRange *range)
3504 {
3505 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3506 if (image->fmask.size)
3507 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3508 else
3509 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3510 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3511 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3512 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3513 }
3514 }
3515
3516 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3517 struct radv_image *image, uint32_t value)
3518 {
3519
3520 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3521 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3522
3523 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3524 image->surface.dcc_size, value);
3525
3526 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3527 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3528 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3529 RADV_CMD_FLAG_INV_VMEM_L1 |
3530 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3531 }
3532
3533 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3534 struct radv_image *image,
3535 VkImageLayout src_layout,
3536 VkImageLayout dst_layout,
3537 unsigned src_queue_mask,
3538 unsigned dst_queue_mask,
3539 const VkImageSubresourceRange *range)
3540 {
3541 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3542 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3543 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3544 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3545 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3546 }
3547 }
3548
3549 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3550 struct radv_image *image,
3551 VkImageLayout src_layout,
3552 VkImageLayout dst_layout,
3553 uint32_t src_family,
3554 uint32_t dst_family,
3555 const VkImageSubresourceRange *range,
3556 VkImageAspectFlags pending_clears)
3557 {
3558 if (image->exclusive && src_family != dst_family) {
3559 /* This is an acquire or a release operation and there will be
3560 * a corresponding release/acquire. Do the transition in the
3561 * most flexible queue. */
3562
3563 assert(src_family == cmd_buffer->queue_family_index ||
3564 dst_family == cmd_buffer->queue_family_index);
3565
3566 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3567 return;
3568
3569 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3570 (src_family == RADV_QUEUE_GENERAL ||
3571 dst_family == RADV_QUEUE_GENERAL))
3572 return;
3573 }
3574
3575 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3576 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3577
3578 if (image->surface.htile_size)
3579 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3580 dst_layout, src_queue_mask,
3581 dst_queue_mask, range,
3582 pending_clears);
3583
3584 if (image->cmask.size || image->fmask.size)
3585 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3586 dst_layout, src_queue_mask,
3587 dst_queue_mask, range);
3588
3589 if (image->surface.dcc_size)
3590 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3591 dst_layout, src_queue_mask,
3592 dst_queue_mask, range);
3593 }
3594
3595 void radv_CmdPipelineBarrier(
3596 VkCommandBuffer commandBuffer,
3597 VkPipelineStageFlags srcStageMask,
3598 VkPipelineStageFlags destStageMask,
3599 VkBool32 byRegion,
3600 uint32_t memoryBarrierCount,
3601 const VkMemoryBarrier* pMemoryBarriers,
3602 uint32_t bufferMemoryBarrierCount,
3603 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3604 uint32_t imageMemoryBarrierCount,
3605 const VkImageMemoryBarrier* pImageMemoryBarriers)
3606 {
3607 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3608 enum radv_cmd_flush_bits src_flush_bits = 0;
3609 enum radv_cmd_flush_bits dst_flush_bits = 0;
3610
3611 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3612 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3613 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3614 NULL);
3615 }
3616
3617 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3618 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3619 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3620 NULL);
3621 }
3622
3623 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3624 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3625 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3626 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3627 image);
3628 }
3629
3630 radv_stage_flush(cmd_buffer, srcStageMask);
3631 cmd_buffer->state.flush_bits |= src_flush_bits;
3632
3633 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3634 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3635 radv_handle_image_transition(cmd_buffer, image,
3636 pImageMemoryBarriers[i].oldLayout,
3637 pImageMemoryBarriers[i].newLayout,
3638 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3639 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3640 &pImageMemoryBarriers[i].subresourceRange,
3641 0);
3642 }
3643
3644 cmd_buffer->state.flush_bits |= dst_flush_bits;
3645 }
3646
3647
3648 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3649 struct radv_event *event,
3650 VkPipelineStageFlags stageMask,
3651 unsigned value)
3652 {
3653 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3654 uint64_t va = radv_buffer_get_va(event->bo);
3655
3656 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3657
3658 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3659
3660 /* TODO: this is overkill. Probably should figure something out from
3661 * the stage mask. */
3662
3663 si_cs_emit_write_event_eop(cs,
3664 cmd_buffer->state.predicating,
3665 cmd_buffer->device->physical_device->rad_info.chip_class,
3666 false,
3667 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3668 1, va, 2, value);
3669
3670 assert(cmd_buffer->cs->cdw <= cdw_max);
3671 }
3672
3673 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3674 VkEvent _event,
3675 VkPipelineStageFlags stageMask)
3676 {
3677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3678 RADV_FROM_HANDLE(radv_event, event, _event);
3679
3680 write_event(cmd_buffer, event, stageMask, 1);
3681 }
3682
3683 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3684 VkEvent _event,
3685 VkPipelineStageFlags stageMask)
3686 {
3687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3688 RADV_FROM_HANDLE(radv_event, event, _event);
3689
3690 write_event(cmd_buffer, event, stageMask, 0);
3691 }
3692
3693 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3694 uint32_t eventCount,
3695 const VkEvent* pEvents,
3696 VkPipelineStageFlags srcStageMask,
3697 VkPipelineStageFlags dstStageMask,
3698 uint32_t memoryBarrierCount,
3699 const VkMemoryBarrier* pMemoryBarriers,
3700 uint32_t bufferMemoryBarrierCount,
3701 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3702 uint32_t imageMemoryBarrierCount,
3703 const VkImageMemoryBarrier* pImageMemoryBarriers)
3704 {
3705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3706 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3707
3708 for (unsigned i = 0; i < eventCount; ++i) {
3709 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3710 uint64_t va = radv_buffer_get_va(event->bo);
3711
3712 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3713
3714 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3715
3716 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3717 assert(cmd_buffer->cs->cdw <= cdw_max);
3718 }
3719
3720
3721 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3722 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3723
3724 radv_handle_image_transition(cmd_buffer, image,
3725 pImageMemoryBarriers[i].oldLayout,
3726 pImageMemoryBarriers[i].newLayout,
3727 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3728 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3729 &pImageMemoryBarriers[i].subresourceRange,
3730 0);
3731 }
3732
3733 /* TODO: figure out how to do memory barriers without waiting */
3734 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3735 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3736 RADV_CMD_FLAG_INV_VMEM_L1 |
3737 RADV_CMD_FLAG_INV_SMEM_L1;
3738 }