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radv/ac: add support for indirect access of descriptor sets.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524
525 export_count = MAX2(1, outinfo->param_exports);
526 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
527 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
528
529 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
530 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
531 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
532 V_02870C_SPI_SHADER_4COMP :
533 V_02870C_SPI_SHADER_NONE) |
534 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
535 V_02870C_SPI_SHADER_4COMP :
536 V_02870C_SPI_SHADER_NONE) |
537 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
538 V_02870C_SPI_SHADER_4COMP :
539 V_02870C_SPI_SHADER_NONE));
540
541
542 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
543 radeon_emit(cmd_buffer->cs, va >> 8);
544 radeon_emit(cmd_buffer->cs, va >> 40);
545 radeon_emit(cmd_buffer->cs, shader->rsrc1);
546 radeon_emit(cmd_buffer->cs, shader->rsrc2);
547
548 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
549 S_028818_VTX_W0_FMT(1) |
550 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
551 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
552 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
553
554
555 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
556 pipeline->graphics.pa_cl_vs_out_cntl);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
559 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
560 }
561
562 static void
563 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_shader_variant *shader,
565 struct ac_es_output_info *outinfo)
566 {
567 struct radeon_winsys *ws = cmd_buffer->device->ws;
568 uint64_t va = ws->buffer_get_va(shader->bo);
569
570 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
573 outinfo->esgs_itemsize / 4);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
575 radeon_emit(cmd_buffer->cs, va >> 8);
576 radeon_emit(cmd_buffer->cs, va >> 40);
577 radeon_emit(cmd_buffer->cs, shader->rsrc1);
578 radeon_emit(cmd_buffer->cs, shader->rsrc2);
579 }
580
581 static void
582 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_shader_variant *shader)
584 {
585 struct radeon_winsys *ws = cmd_buffer->device->ws;
586 uint64_t va = ws->buffer_get_va(shader->bo);
587 uint32_t rsrc2 = shader->rsrc2;
588
589 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
590
591 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
592 radeon_emit(cmd_buffer->cs, va >> 8);
593 radeon_emit(cmd_buffer->cs, va >> 40);
594
595 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
596 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
597 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
598 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
599
600 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
601 radeon_emit(cmd_buffer->cs, shader->rsrc1);
602 radeon_emit(cmd_buffer->cs, rsrc2);
603 }
604
605 static void
606 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_shader_variant *shader)
608 {
609 struct radeon_winsys *ws = cmd_buffer->device->ws;
610 uint64_t va = ws->buffer_get_va(shader->bo);
611
612 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
613
614 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
615 radeon_emit(cmd_buffer->cs, va >> 8);
616 radeon_emit(cmd_buffer->cs, va >> 40);
617 radeon_emit(cmd_buffer->cs, shader->rsrc1);
618 radeon_emit(cmd_buffer->cs, shader->rsrc2);
619 }
620
621 static void
622 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
623 struct radv_pipeline *pipeline)
624 {
625 struct radv_shader_variant *vs;
626
627 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
628
629 vs = pipeline->shaders[MESA_SHADER_VERTEX];
630
631 if (vs->info.vs.as_ls)
632 radv_emit_hw_ls(cmd_buffer, vs);
633 else if (vs->info.vs.as_es)
634 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
635 else
636 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
637
638 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
639 }
640
641
642 static void
643 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 if (!radv_pipeline_has_tess(pipeline))
647 return;
648
649 struct radv_shader_variant *tes, *tcs;
650
651 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
652 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
653
654 if (tes->info.tes.as_es)
655 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
656 else
657 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
658
659 radv_emit_hw_hs(cmd_buffer, tcs);
660
661 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
662 pipeline->graphics.tess.tf_param);
663
664 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
665 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
666 pipeline->graphics.tess.ls_hs_config);
667 else
668 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
669 pipeline->graphics.tess.ls_hs_config);
670
671 struct ac_userdata_info *loc;
672
673 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
674 if (loc->sgpr_idx != -1) {
675 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
676 assert(loc->num_sgprs == 4);
677 assert(!loc->indirect);
678 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
679 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
680 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
681 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
682 pipeline->graphics.tess.num_tcs_input_cp << 26);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
684 }
685
686 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
687 if (loc->sgpr_idx != -1) {
688 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
689 assert(loc->num_sgprs == 1);
690 assert(!loc->indirect);
691
692 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
693 pipeline->graphics.tess.offchip_layout);
694 }
695
696 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
697 if (loc->sgpr_idx != -1) {
698 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
699 assert(loc->num_sgprs == 1);
700 assert(!loc->indirect);
701
702 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
703 pipeline->graphics.tess.tcs_in_layout);
704 }
705 }
706
707 static void
708 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
709 struct radv_pipeline *pipeline)
710 {
711 struct radeon_winsys *ws = cmd_buffer->device->ws;
712 struct radv_shader_variant *gs;
713 uint64_t va;
714
715 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
716
717 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
718 if (!gs)
719 return;
720
721 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
722
723 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
724 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
725 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
726 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
727
728 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
731
732 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
733 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
734 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
735 radeon_emit(cmd_buffer->cs, 0);
736 radeon_emit(cmd_buffer->cs, 0);
737 radeon_emit(cmd_buffer->cs, 0);
738
739 uint32_t gs_num_invocations = gs->info.gs.invocations;
740 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
741 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
742 S_028B90_ENABLE(gs_num_invocations > 0));
743
744 va = ws->buffer_get_va(gs->bo);
745 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
746 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
747 radeon_emit(cmd_buffer->cs, va >> 8);
748 radeon_emit(cmd_buffer->cs, va >> 40);
749 radeon_emit(cmd_buffer->cs, gs->rsrc1);
750 radeon_emit(cmd_buffer->cs, gs->rsrc2);
751
752 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
753
754 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
755 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
756 if (loc->sgpr_idx != -1) {
757 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
758 uint32_t num_entries = 64;
759 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
760
761 if (is_vi)
762 num_entries *= stride;
763
764 stride = S_008F04_STRIDE(stride);
765 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
766 radeon_emit(cmd_buffer->cs, stride);
767 radeon_emit(cmd_buffer->cs, num_entries);
768 }
769 }
770
771 static void
772 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
773 struct radv_pipeline *pipeline)
774 {
775 struct radeon_winsys *ws = cmd_buffer->device->ws;
776 struct radv_shader_variant *ps;
777 uint64_t va;
778 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
779 struct radv_blend_state *blend = &pipeline->graphics.blend;
780 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
781
782 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
783
784 va = ws->buffer_get_va(ps->bo);
785 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
786
787 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
788 radeon_emit(cmd_buffer->cs, va >> 8);
789 radeon_emit(cmd_buffer->cs, va >> 40);
790 radeon_emit(cmd_buffer->cs, ps->rsrc1);
791 radeon_emit(cmd_buffer->cs, ps->rsrc2);
792
793 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
794 pipeline->graphics.db_shader_control);
795
796 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
797 ps->config.spi_ps_input_ena);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
800 ps->config.spi_ps_input_addr);
801
802 if (ps->info.fs.force_persample)
803 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
806 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
807
808 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
811 pipeline->graphics.shader_z_format);
812
813 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
814
815 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
816 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
817
818 if (pipeline->graphics.ps_input_cntl_num) {
819 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
820 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
821 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
822 }
823 }
824 }
825
826 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
827 struct radv_pipeline *pipeline)
828 {
829 uint32_t vtx_reuse_depth = 30;
830 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
831 return;
832
833 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
834 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
835 vtx_reuse_depth = 14;
836 }
837 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
838 vtx_reuse_depth);
839 }
840
841 static void
842 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
843 struct radv_pipeline *pipeline)
844 {
845 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
846 return;
847
848 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
849 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
850 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
851 radv_update_multisample_state(cmd_buffer, pipeline);
852 radv_emit_vertex_shader(cmd_buffer, pipeline);
853 radv_emit_tess_shaders(cmd_buffer, pipeline);
854 radv_emit_geometry_shader(cmd_buffer, pipeline);
855 radv_emit_fragment_shader(cmd_buffer, pipeline);
856 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
857
858 cmd_buffer->scratch_size_needed =
859 MAX2(cmd_buffer->scratch_size_needed,
860 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
861
862 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
863 S_0286E8_WAVES(pipeline->max_waves) |
864 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
865
866 if (!cmd_buffer->state.emitted_pipeline ||
867 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
868 pipeline->graphics.can_use_guardband)
869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
870 cmd_buffer->state.emitted_pipeline = pipeline;
871 }
872
873 static void
874 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
875 {
876 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
877 cmd_buffer->state.dynamic.viewport.viewports);
878 }
879
880 static void
881 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
882 {
883 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
884 si_write_scissors(cmd_buffer->cs, 0, count,
885 cmd_buffer->state.dynamic.scissor.scissors,
886 cmd_buffer->state.dynamic.viewport.viewports,
887 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
888 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
889 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
890 }
891
892 static void
893 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
894 int index,
895 struct radv_color_buffer_info *cb)
896 {
897 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
898 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
899 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
900 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
901 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
902 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
903 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
904 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
905 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
910
911 if (is_vi) { /* DCC BASE */
912 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
913 }
914 }
915
916 static void
917 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
918 struct radv_ds_buffer_info *ds,
919 struct radv_image *image,
920 VkImageLayout layout)
921 {
922 uint32_t db_z_info = ds->db_z_info;
923
924 if (!radv_layout_has_htile(image, layout))
925 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
926
927 if (!radv_layout_can_expclear(image, layout))
928 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
929
930 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
931 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
932
933 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
934 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
935 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
936 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
937 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
938 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
939 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
940 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
941 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
942 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
943
944 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
945 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
946 ds->pa_su_poly_offset_db_fmt_cntl);
947 }
948
949 /*
950 * To hw resolve multisample images both src and dst need to have the same
951 * micro tiling mode. However we don't always know in advance when creating
952 * the images. This function gets called if we have a resolve attachment,
953 * and tests if the attachment image has the same tiling mode, then it
954 * checks if the generated framebuffer data has the same tiling mode, and
955 * updates it if not.
956 */
957 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
958 struct radv_attachment_info *att,
959 uint32_t micro_tile_mode)
960 {
961 struct radv_image *image = att->attachment->image;
962 uint32_t tile_mode_index;
963 if (image->surface.nsamples <= 1)
964 return;
965
966 if (image->surface.micro_tile_mode != micro_tile_mode) {
967 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
968 }
969
970 if (att->cb.micro_tile_mode != micro_tile_mode) {
971 tile_mode_index = image->surface.tiling_index[0];
972
973 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
974 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
975 att->cb.micro_tile_mode = micro_tile_mode;
976 }
977 }
978
979 void
980 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
981 struct radv_image *image,
982 VkClearDepthStencilValue ds_clear_value,
983 VkImageAspectFlags aspects)
984 {
985 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
986 va += image->offset + image->clear_value_offset;
987 unsigned reg_offset = 0, reg_count = 0;
988
989 if (!image->surface.htile_size || !aspects)
990 return;
991
992 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
993 ++reg_count;
994 } else {
995 ++reg_offset;
996 va += 4;
997 }
998 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
999 ++reg_count;
1000
1001 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1002
1003 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1004 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1005 S_370_WR_CONFIRM(1) |
1006 S_370_ENGINE_SEL(V_370_PFP));
1007 radeon_emit(cmd_buffer->cs, va);
1008 radeon_emit(cmd_buffer->cs, va >> 32);
1009 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1010 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1011 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1012 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1013
1014 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1015 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1016 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1017 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1018 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1019 }
1020
1021 static void
1022 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1023 struct radv_image *image)
1024 {
1025 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1026 va += image->offset + image->clear_value_offset;
1027
1028 if (!image->surface.htile_size)
1029 return;
1030
1031 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1032
1033 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1034 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1035 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1036 COPY_DATA_COUNT_SEL);
1037 radeon_emit(cmd_buffer->cs, va);
1038 radeon_emit(cmd_buffer->cs, va >> 32);
1039 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1040 radeon_emit(cmd_buffer->cs, 0);
1041
1042 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1043 radeon_emit(cmd_buffer->cs, 0);
1044 }
1045
1046 void
1047 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1048 struct radv_image *image,
1049 int idx,
1050 uint32_t color_values[2])
1051 {
1052 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1053 va += image->offset + image->clear_value_offset;
1054
1055 if (!image->cmask.size && !image->surface.dcc_size)
1056 return;
1057
1058 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1059
1060 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1061 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1062 S_370_WR_CONFIRM(1) |
1063 S_370_ENGINE_SEL(V_370_PFP));
1064 radeon_emit(cmd_buffer->cs, va);
1065 radeon_emit(cmd_buffer->cs, va >> 32);
1066 radeon_emit(cmd_buffer->cs, color_values[0]);
1067 radeon_emit(cmd_buffer->cs, color_values[1]);
1068
1069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1070 radeon_emit(cmd_buffer->cs, color_values[0]);
1071 radeon_emit(cmd_buffer->cs, color_values[1]);
1072 }
1073
1074 static void
1075 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1076 struct radv_image *image,
1077 int idx)
1078 {
1079 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1080 va += image->offset + image->clear_value_offset;
1081
1082 if (!image->cmask.size && !image->surface.dcc_size)
1083 return;
1084
1085 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1086 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1087
1088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1089 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1090 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1091 COPY_DATA_COUNT_SEL);
1092 radeon_emit(cmd_buffer->cs, va);
1093 radeon_emit(cmd_buffer->cs, va >> 32);
1094 radeon_emit(cmd_buffer->cs, reg >> 2);
1095 radeon_emit(cmd_buffer->cs, 0);
1096
1097 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1098 radeon_emit(cmd_buffer->cs, 0);
1099 }
1100
1101 void
1102 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1103 {
1104 int i;
1105 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1106 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1107 int dst_resolve_micro_tile_mode = -1;
1108
1109 if (subpass->has_resolve) {
1110 uint32_t a = subpass->resolve_attachments[0].attachment;
1111 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1112 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1113 }
1114 for (i = 0; i < subpass->color_count; ++i) {
1115 int idx = subpass->color_attachments[i].attachment;
1116 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1117
1118 if (dst_resolve_micro_tile_mode != -1) {
1119 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1120 att, dst_resolve_micro_tile_mode);
1121 }
1122 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1123
1124 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1125 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1126
1127 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1128 }
1129
1130 for (i = subpass->color_count; i < 8; i++)
1131 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1132 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1133
1134 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1135 int idx = subpass->depth_stencil_attachment.attachment;
1136 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1137 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1138 struct radv_image *image = att->attachment->image;
1139 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1140
1141 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1142
1143 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1144 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1145 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1146 }
1147 radv_load_depth_clear_regs(cmd_buffer, image);
1148 } else {
1149 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1150 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1151 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1152 }
1153 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1154 S_028208_BR_X(framebuffer->width) |
1155 S_028208_BR_Y(framebuffer->height));
1156 }
1157
1158 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1159 {
1160 uint32_t db_count_control;
1161
1162 if(!cmd_buffer->state.active_occlusion_queries) {
1163 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1164 db_count_control = 0;
1165 } else {
1166 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1167 }
1168 } else {
1169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1170 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1171 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1172 S_028004_ZPASS_ENABLE(1) |
1173 S_028004_SLICE_EVEN_ENABLE(1) |
1174 S_028004_SLICE_ODD_ENABLE(1);
1175 } else {
1176 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1177 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1178 }
1179 }
1180
1181 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1182 }
1183
1184 static void
1185 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1188
1189 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1190 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1191 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1192 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1193 }
1194
1195 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1196 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1197 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1198 }
1199
1200 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1201 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1202 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1203 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1204 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1205 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1206 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1207 S_028430_STENCILOPVAL(1));
1208 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1209 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1210 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1211 S_028434_STENCILOPVAL_BF(1));
1212 }
1213
1214 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1215 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1217 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1218 }
1219
1220 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1221 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1222 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1223 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1224 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1225
1226 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1227 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1228 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1229 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1230 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1231 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1232 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1233 }
1234 }
1235
1236 cmd_buffer->state.dirty = 0;
1237 }
1238
1239 static void
1240 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1241 struct radv_pipeline *pipeline,
1242 int idx,
1243 uint64_t va,
1244 gl_shader_stage stage)
1245 {
1246 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1247 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1248
1249 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1250 return;
1251
1252 assert(!desc_set_loc->indirect);
1253 assert(desc_set_loc->num_sgprs == 2);
1254 radeon_set_sh_reg_seq(cmd_buffer->cs,
1255 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1256 radeon_emit(cmd_buffer->cs, va);
1257 radeon_emit(cmd_buffer->cs, va >> 32);
1258 }
1259
1260 static void
1261 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1262 struct radv_pipeline *pipeline,
1263 VkShaderStageFlags stages,
1264 struct radv_descriptor_set *set,
1265 unsigned idx)
1266 {
1267 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1268 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1269 idx, set->va,
1270 MESA_SHADER_FRAGMENT);
1271
1272 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1273 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1274 idx, set->va,
1275 MESA_SHADER_VERTEX);
1276
1277 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1278 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1279 idx, set->va,
1280 MESA_SHADER_GEOMETRY);
1281
1282 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1283 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1284 idx, set->va,
1285 MESA_SHADER_TESS_CTRL);
1286
1287 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1288 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1289 idx, set->va,
1290 MESA_SHADER_TESS_EVAL);
1291
1292 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1293 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1294 idx, set->va,
1295 MESA_SHADER_COMPUTE);
1296 }
1297
1298 static void
1299 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1300 {
1301 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1302 uint32_t *ptr = NULL;
1303 unsigned bo_offset;
1304
1305 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1306 &bo_offset,
1307 (void**) &ptr))
1308 return;
1309
1310 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1311 set->va += bo_offset;
1312
1313 memcpy(ptr, set->mapped_ptr, set->size);
1314 }
1315
1316 static void
1317 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1318 struct radv_pipeline *pipeline)
1319 {
1320 uint32_t size = MAX_SETS * 2 * 4;
1321 uint32_t offset;
1322 void *ptr;
1323
1324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1325 256, &offset, &ptr))
1326 return;
1327
1328 for (unsigned i = 0; i < MAX_SETS; i++) {
1329 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1330 uint64_t set_va = 0;
1331 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1332 if (set)
1333 set_va = set->va;
1334 uptr[0] = set_va & 0xffffffff;
1335 uptr[1] = set_va >> 32;
1336 }
1337
1338 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1339 va += offset;
1340
1341 if (pipeline->shaders[MESA_SHADER_VERTEX])
1342 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1343 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1344
1345 if (pipeline->shaders[MESA_SHADER_FRAGMENT])
1346 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1347 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1348
1349 if (radv_pipeline_has_gs(pipeline))
1350 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1351 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1352
1353 if (radv_pipeline_has_tess(pipeline))
1354 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1355 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1356
1357 if (radv_pipeline_has_tess(pipeline))
1358 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1359 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1360
1361 if (pipeline->shaders[MESA_SHADER_COMPUTE])
1362 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1363 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1364 }
1365
1366 static void
1367 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1368 struct radv_pipeline *pipeline,
1369 VkShaderStageFlags stages)
1370 {
1371 unsigned i;
1372
1373 if (!cmd_buffer->state.descriptors_dirty)
1374 return;
1375
1376 if (cmd_buffer->state.push_descriptors_dirty)
1377 radv_flush_push_descriptors(cmd_buffer);
1378
1379 if (pipeline->need_indirect_descriptor_sets) {
1380 radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
1381 }
1382
1383 for (i = 0; i < MAX_SETS; i++) {
1384 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1385 continue;
1386 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1387 if (!set)
1388 continue;
1389
1390 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1391 }
1392 cmd_buffer->state.descriptors_dirty = 0;
1393 cmd_buffer->state.push_descriptors_dirty = false;
1394 }
1395
1396 static void
1397 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1398 struct radv_pipeline *pipeline,
1399 VkShaderStageFlags stages)
1400 {
1401 struct radv_pipeline_layout *layout = pipeline->layout;
1402 unsigned offset;
1403 void *ptr;
1404 uint64_t va;
1405
1406 stages &= cmd_buffer->push_constant_stages;
1407 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1408 return;
1409
1410 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1411 16 * layout->dynamic_offset_count,
1412 256, &offset, &ptr))
1413 return;
1414
1415 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1416 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1417 16 * layout->dynamic_offset_count);
1418
1419 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1420 va += offset;
1421
1422 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1423 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1424 AC_UD_PUSH_CONSTANTS, va);
1425
1426 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1427 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1428 AC_UD_PUSH_CONSTANTS, va);
1429
1430 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1431 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1432 AC_UD_PUSH_CONSTANTS, va);
1433
1434 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1435 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1436 AC_UD_PUSH_CONSTANTS, va);
1437
1438 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1439 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1440 AC_UD_PUSH_CONSTANTS, va);
1441
1442 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1443 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1444 AC_UD_PUSH_CONSTANTS, va);
1445
1446 cmd_buffer->push_constant_stages &= ~stages;
1447 }
1448
1449 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1450 bool indexed_draw)
1451 {
1452 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1453
1454 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1455 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1456 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1457 primitive_reset_en);
1458 }
1459
1460 if (primitive_reset_en) {
1461 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1462
1463 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1464 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1465 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1466 primitive_reset_index);
1467 }
1468 }
1469 }
1470
1471 static void
1472 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1473 bool indexed_draw, bool instanced_draw,
1474 bool indirect_draw,
1475 uint32_t draw_vertex_count)
1476 {
1477 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1478 struct radv_device *device = cmd_buffer->device;
1479 uint32_t ia_multi_vgt_param;
1480
1481 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1482 cmd_buffer->cs, 4096);
1483
1484 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1485 cmd_buffer->state.pipeline->num_vertex_attribs &&
1486 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1487 unsigned vb_offset;
1488 void *vb_ptr;
1489 uint32_t i = 0;
1490 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1491 uint64_t va;
1492
1493 /* allocate some descriptor state for vertex buffers */
1494 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1495 &vb_offset, &vb_ptr);
1496
1497 for (i = 0; i < num_attribs; i++) {
1498 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1499 uint32_t offset;
1500 int vb = cmd_buffer->state.pipeline->va_binding[i];
1501 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1502 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1503
1504 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1505 va = device->ws->buffer_get_va(buffer->bo);
1506
1507 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1508 va += offset + buffer->offset;
1509 desc[0] = va;
1510 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1511 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1512 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1513 else
1514 desc[2] = buffer->size - offset;
1515 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1516 }
1517
1518 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1519 va += vb_offset;
1520
1521 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1522 AC_UD_VS_VERTEX_BUFFERS, va);
1523 }
1524
1525 cmd_buffer->state.vertex_descriptors_dirty = false;
1526 cmd_buffer->state.vb_dirty = 0;
1527 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1528 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1529
1530 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1531 radv_emit_framebuffer_state(cmd_buffer);
1532
1533 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1534 radv_emit_viewport(cmd_buffer);
1535
1536 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1537 radv_emit_scissor(cmd_buffer);
1538
1539 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1540 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1541 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1542 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1543 else
1544 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1545 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1546 }
1547
1548 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1549 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1550
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1552 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1553 } else {
1554 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1555 }
1556 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1557 }
1558
1559 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1560
1561 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1562
1563 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1564 VK_SHADER_STAGE_ALL_GRAPHICS);
1565 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1566 VK_SHADER_STAGE_ALL_GRAPHICS);
1567
1568 assert(cmd_buffer->cs->cdw <= cdw_max);
1569
1570 si_emit_cache_flush(cmd_buffer);
1571 }
1572
1573 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1574 VkPipelineStageFlags src_stage_mask)
1575 {
1576 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1577 VK_PIPELINE_STAGE_TRANSFER_BIT |
1578 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1579 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1580 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1581 }
1582
1583 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1584 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1585 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1586 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1587 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1588 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1589 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1590 VK_PIPELINE_STAGE_TRANSFER_BIT |
1591 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1592 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1593 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1594 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1595 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1596 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1597 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1598 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1599 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1600 }
1601 }
1602
1603 static enum radv_cmd_flush_bits
1604 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1605 VkAccessFlags src_flags)
1606 {
1607 enum radv_cmd_flush_bits flush_bits = 0;
1608 uint32_t b;
1609 for_each_bit(b, src_flags) {
1610 switch ((VkAccessFlagBits)(1 << b)) {
1611 case VK_ACCESS_SHADER_WRITE_BIT:
1612 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1613 break;
1614 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1615 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1616 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1617 break;
1618 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1619 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1620 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1621 break;
1622 case VK_ACCESS_TRANSFER_WRITE_BIT:
1623 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1624 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1625 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1627 RADV_CMD_FLAG_INV_GLOBAL_L2;
1628 break;
1629 default:
1630 break;
1631 }
1632 }
1633 return flush_bits;
1634 }
1635
1636 static enum radv_cmd_flush_bits
1637 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1638 VkAccessFlags dst_flags,
1639 struct radv_image *image)
1640 {
1641 enum radv_cmd_flush_bits flush_bits = 0;
1642 uint32_t b;
1643 for_each_bit(b, dst_flags) {
1644 switch ((VkAccessFlagBits)(1 << b)) {
1645 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1646 case VK_ACCESS_INDEX_READ_BIT:
1647 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1648 break;
1649 case VK_ACCESS_UNIFORM_READ_BIT:
1650 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1651 break;
1652 case VK_ACCESS_SHADER_READ_BIT:
1653 case VK_ACCESS_TRANSFER_READ_BIT:
1654 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1655 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1656 RADV_CMD_FLAG_INV_GLOBAL_L2;
1657 break;
1658 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1659 /* TODO: change to image && when the image gets passed
1660 * through from the subpass. */
1661 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1662 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1663 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1664 break;
1665 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1666 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1667 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1668 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1669 break;
1670 default:
1671 break;
1672 }
1673 }
1674 return flush_bits;
1675 }
1676
1677 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1678 {
1679 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1680 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1681 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1682 NULL);
1683 }
1684
1685 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1686 VkAttachmentReference att)
1687 {
1688 unsigned idx = att.attachment;
1689 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1690 VkImageSubresourceRange range;
1691 range.aspectMask = 0;
1692 range.baseMipLevel = view->base_mip;
1693 range.levelCount = 1;
1694 range.baseArrayLayer = view->base_layer;
1695 range.layerCount = cmd_buffer->state.framebuffer->layers;
1696
1697 radv_handle_image_transition(cmd_buffer,
1698 view->image,
1699 cmd_buffer->state.attachments[idx].current_layout,
1700 att.layout, 0, 0, &range,
1701 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1702
1703 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1704
1705
1706 }
1707
1708 void
1709 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1710 const struct radv_subpass *subpass, bool transitions)
1711 {
1712 if (transitions) {
1713 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1714
1715 for (unsigned i = 0; i < subpass->color_count; ++i) {
1716 radv_handle_subpass_image_transition(cmd_buffer,
1717 subpass->color_attachments[i]);
1718 }
1719
1720 for (unsigned i = 0; i < subpass->input_count; ++i) {
1721 radv_handle_subpass_image_transition(cmd_buffer,
1722 subpass->input_attachments[i]);
1723 }
1724
1725 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1726 radv_handle_subpass_image_transition(cmd_buffer,
1727 subpass->depth_stencil_attachment);
1728 }
1729 }
1730
1731 cmd_buffer->state.subpass = subpass;
1732
1733 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1734 }
1735
1736 static void
1737 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1738 struct radv_render_pass *pass,
1739 const VkRenderPassBeginInfo *info)
1740 {
1741 struct radv_cmd_state *state = &cmd_buffer->state;
1742
1743 if (pass->attachment_count == 0) {
1744 state->attachments = NULL;
1745 return;
1746 }
1747
1748 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1749 pass->attachment_count *
1750 sizeof(state->attachments[0]),
1751 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1752 if (state->attachments == NULL) {
1753 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1754 abort();
1755 }
1756
1757 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1758 struct radv_render_pass_attachment *att = &pass->attachments[i];
1759 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1760 VkImageAspectFlags clear_aspects = 0;
1761
1762 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1763 /* color attachment */
1764 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1765 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1766 }
1767 } else {
1768 /* depthstencil attachment */
1769 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1770 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1771 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1772 }
1773 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1774 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1775 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1776 }
1777 }
1778
1779 state->attachments[i].pending_clear_aspects = clear_aspects;
1780 if (clear_aspects && info) {
1781 assert(info->clearValueCount > i);
1782 state->attachments[i].clear_value = info->pClearValues[i];
1783 }
1784
1785 state->attachments[i].current_layout = att->initial_layout;
1786 }
1787 }
1788
1789 VkResult radv_AllocateCommandBuffers(
1790 VkDevice _device,
1791 const VkCommandBufferAllocateInfo *pAllocateInfo,
1792 VkCommandBuffer *pCommandBuffers)
1793 {
1794 RADV_FROM_HANDLE(radv_device, device, _device);
1795 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1796
1797 VkResult result = VK_SUCCESS;
1798 uint32_t i;
1799
1800 memset(pCommandBuffers, 0,
1801 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1802
1803 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1804
1805 if (!list_empty(&pool->free_cmd_buffers)) {
1806 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1807
1808 list_del(&cmd_buffer->pool_link);
1809 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1810
1811 radv_reset_cmd_buffer(cmd_buffer);
1812 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1813 cmd_buffer->level = pAllocateInfo->level;
1814
1815 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1816 result = VK_SUCCESS;
1817 } else {
1818 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1819 &pCommandBuffers[i]);
1820 }
1821 if (result != VK_SUCCESS)
1822 break;
1823 }
1824
1825 if (result != VK_SUCCESS)
1826 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1827 i, pCommandBuffers);
1828
1829 return result;
1830 }
1831
1832 void radv_FreeCommandBuffers(
1833 VkDevice device,
1834 VkCommandPool commandPool,
1835 uint32_t commandBufferCount,
1836 const VkCommandBuffer *pCommandBuffers)
1837 {
1838 for (uint32_t i = 0; i < commandBufferCount; i++) {
1839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1840
1841 if (cmd_buffer) {
1842 if (cmd_buffer->pool) {
1843 list_del(&cmd_buffer->pool_link);
1844 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1845 } else
1846 radv_cmd_buffer_destroy(cmd_buffer);
1847
1848 }
1849 }
1850 }
1851
1852 VkResult radv_ResetCommandBuffer(
1853 VkCommandBuffer commandBuffer,
1854 VkCommandBufferResetFlags flags)
1855 {
1856 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1857 radv_reset_cmd_buffer(cmd_buffer);
1858 return VK_SUCCESS;
1859 }
1860
1861 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1862 {
1863 struct radv_device *device = cmd_buffer->device;
1864 if (device->gfx_init) {
1865 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1866 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1867 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1868 radeon_emit(cmd_buffer->cs, va);
1869 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1870 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1871 } else
1872 si_init_config(cmd_buffer);
1873 }
1874
1875 VkResult radv_BeginCommandBuffer(
1876 VkCommandBuffer commandBuffer,
1877 const VkCommandBufferBeginInfo *pBeginInfo)
1878 {
1879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1880 radv_reset_cmd_buffer(cmd_buffer);
1881
1882 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1883 cmd_buffer->state.last_primitive_reset_en = -1;
1884
1885 /* setup initial configuration into command buffer */
1886 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1887 switch (cmd_buffer->queue_family_index) {
1888 case RADV_QUEUE_GENERAL:
1889 emit_gfx_buffer_state(cmd_buffer);
1890 radv_set_db_count_control(cmd_buffer);
1891 break;
1892 case RADV_QUEUE_COMPUTE:
1893 si_init_compute(cmd_buffer);
1894 break;
1895 case RADV_QUEUE_TRANSFER:
1896 default:
1897 break;
1898 }
1899 }
1900
1901 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1902 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1903 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1904
1905 struct radv_subpass *subpass =
1906 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1907
1908 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1909 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1910 }
1911
1912 radv_cmd_buffer_trace_emit(cmd_buffer);
1913 return VK_SUCCESS;
1914 }
1915
1916 void radv_CmdBindVertexBuffers(
1917 VkCommandBuffer commandBuffer,
1918 uint32_t firstBinding,
1919 uint32_t bindingCount,
1920 const VkBuffer* pBuffers,
1921 const VkDeviceSize* pOffsets)
1922 {
1923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1924 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1925
1926 /* We have to defer setting up vertex buffer since we need the buffer
1927 * stride from the pipeline. */
1928
1929 assert(firstBinding + bindingCount < MAX_VBS);
1930 for (uint32_t i = 0; i < bindingCount; i++) {
1931 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1932 vb[firstBinding + i].offset = pOffsets[i];
1933 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1934 }
1935 }
1936
1937 void radv_CmdBindIndexBuffer(
1938 VkCommandBuffer commandBuffer,
1939 VkBuffer buffer,
1940 VkDeviceSize offset,
1941 VkIndexType indexType)
1942 {
1943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1944
1945 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1946 cmd_buffer->state.index_offset = offset;
1947 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1948 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1949 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1950 }
1951
1952
1953 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1954 struct radv_descriptor_set *set,
1955 unsigned idx)
1956 {
1957 struct radeon_winsys *ws = cmd_buffer->device->ws;
1958
1959 cmd_buffer->state.descriptors[idx] = set;
1960 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1961 if (!set)
1962 return;
1963
1964 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1965 if (set->descriptors[j])
1966 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1967
1968 if(set->bo)
1969 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1970 }
1971
1972 void radv_CmdBindDescriptorSets(
1973 VkCommandBuffer commandBuffer,
1974 VkPipelineBindPoint pipelineBindPoint,
1975 VkPipelineLayout _layout,
1976 uint32_t firstSet,
1977 uint32_t descriptorSetCount,
1978 const VkDescriptorSet* pDescriptorSets,
1979 uint32_t dynamicOffsetCount,
1980 const uint32_t* pDynamicOffsets)
1981 {
1982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1983 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1984 unsigned dyn_idx = 0;
1985
1986 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1987 unsigned idx = i + firstSet;
1988 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1989 radv_bind_descriptor_set(cmd_buffer, set, idx);
1990
1991 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1992 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1993 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1994 assert(dyn_idx < dynamicOffsetCount);
1995
1996 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1997 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1998 dst[0] = va;
1999 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2000 dst[2] = range->size;
2001 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2002 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2003 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2004 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2005 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2006 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2007 cmd_buffer->push_constant_stages |=
2008 set->layout->dynamic_shader_stages;
2009 }
2010 }
2011 }
2012
2013 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2014 struct radv_descriptor_set *set,
2015 struct radv_descriptor_set_layout *layout)
2016 {
2017 set->size = layout->size;
2018 set->layout = layout;
2019
2020 if (cmd_buffer->push_descriptors.capacity < set->size) {
2021 size_t new_size = MAX2(set->size, 1024);
2022 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2023 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2024
2025 free(set->mapped_ptr);
2026 set->mapped_ptr = malloc(new_size);
2027
2028 if (!set->mapped_ptr) {
2029 cmd_buffer->push_descriptors.capacity = 0;
2030 cmd_buffer->record_fail = true;
2031 return false;
2032 }
2033
2034 cmd_buffer->push_descriptors.capacity = new_size;
2035 }
2036
2037 return true;
2038 }
2039
2040 void radv_meta_push_descriptor_set(
2041 struct radv_cmd_buffer* cmd_buffer,
2042 VkPipelineBindPoint pipelineBindPoint,
2043 VkPipelineLayout _layout,
2044 uint32_t set,
2045 uint32_t descriptorWriteCount,
2046 const VkWriteDescriptorSet* pDescriptorWrites)
2047 {
2048 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2049 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2050 unsigned bo_offset;
2051
2052 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2053
2054 push_set->size = layout->set[set].layout->size;
2055 push_set->layout = layout->set[set].layout;
2056
2057 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2058 &bo_offset,
2059 (void**) &push_set->mapped_ptr))
2060 return;
2061
2062 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2063 push_set->va += bo_offset;
2064
2065 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2066 radv_descriptor_set_to_handle(push_set),
2067 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2068
2069 cmd_buffer->state.descriptors[set] = push_set;
2070 cmd_buffer->state.descriptors_dirty |= (1 << set);
2071 }
2072
2073 void radv_CmdPushDescriptorSetKHR(
2074 VkCommandBuffer commandBuffer,
2075 VkPipelineBindPoint pipelineBindPoint,
2076 VkPipelineLayout _layout,
2077 uint32_t set,
2078 uint32_t descriptorWriteCount,
2079 const VkWriteDescriptorSet* pDescriptorWrites)
2080 {
2081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2082 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2083 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2084
2085 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2086
2087 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2088 return;
2089
2090 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2091 radv_descriptor_set_to_handle(push_set),
2092 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2093
2094 cmd_buffer->state.descriptors[set] = push_set;
2095 cmd_buffer->state.descriptors_dirty |= (1 << set);
2096 cmd_buffer->state.push_descriptors_dirty = true;
2097 }
2098
2099 void radv_CmdPushDescriptorSetWithTemplateKHR(
2100 VkCommandBuffer commandBuffer,
2101 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2102 VkPipelineLayout _layout,
2103 uint32_t set,
2104 const void* pData)
2105 {
2106 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2107 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2108 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2109
2110 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2111
2112 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2113 return;
2114
2115 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2116 descriptorUpdateTemplate, pData);
2117
2118 cmd_buffer->state.descriptors[set] = push_set;
2119 cmd_buffer->state.descriptors_dirty |= (1 << set);
2120 cmd_buffer->state.push_descriptors_dirty = true;
2121 }
2122
2123 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2124 VkPipelineLayout layout,
2125 VkShaderStageFlags stageFlags,
2126 uint32_t offset,
2127 uint32_t size,
2128 const void* pValues)
2129 {
2130 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2131 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2132 cmd_buffer->push_constant_stages |= stageFlags;
2133 }
2134
2135 VkResult radv_EndCommandBuffer(
2136 VkCommandBuffer commandBuffer)
2137 {
2138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2139
2140 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2141 si_emit_cache_flush(cmd_buffer);
2142
2143 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2144 cmd_buffer->record_fail)
2145 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2146 return VK_SUCCESS;
2147 }
2148
2149 static void
2150 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2151 {
2152 struct radeon_winsys *ws = cmd_buffer->device->ws;
2153 struct radv_shader_variant *compute_shader;
2154 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2155 uint64_t va;
2156
2157 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2158 return;
2159
2160 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2161
2162 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2163 va = ws->buffer_get_va(compute_shader->bo);
2164
2165 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2166
2167 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2168 cmd_buffer->cs, 16);
2169
2170 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2171 radeon_emit(cmd_buffer->cs, va >> 8);
2172 radeon_emit(cmd_buffer->cs, va >> 40);
2173
2174 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2175 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2176 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2177
2178
2179 cmd_buffer->compute_scratch_size_needed =
2180 MAX2(cmd_buffer->compute_scratch_size_needed,
2181 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2182
2183 /* change these once we have scratch support */
2184 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2185 S_00B860_WAVES(pipeline->max_waves) |
2186 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2187
2188 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2189 radeon_emit(cmd_buffer->cs,
2190 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2191 radeon_emit(cmd_buffer->cs,
2192 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2193 radeon_emit(cmd_buffer->cs,
2194 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2195
2196 assert(cmd_buffer->cs->cdw <= cdw_max);
2197 }
2198
2199
2200 void radv_CmdBindPipeline(
2201 VkCommandBuffer commandBuffer,
2202 VkPipelineBindPoint pipelineBindPoint,
2203 VkPipeline _pipeline)
2204 {
2205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2206 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2207
2208 for (unsigned i = 0; i < MAX_SETS; i++) {
2209 if (cmd_buffer->state.descriptors[i])
2210 cmd_buffer->state.descriptors_dirty |= (1 << i);
2211 }
2212
2213 switch (pipelineBindPoint) {
2214 case VK_PIPELINE_BIND_POINT_COMPUTE:
2215 cmd_buffer->state.compute_pipeline = pipeline;
2216 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2217 break;
2218 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2219 cmd_buffer->state.pipeline = pipeline;
2220 cmd_buffer->state.vertex_descriptors_dirty = true;
2221 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2222 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2223
2224 /* Apply the dynamic state from the pipeline */
2225 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2226 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2227 &pipeline->dynamic_state,
2228 pipeline->dynamic_state_mask);
2229
2230 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2231 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2232 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2233 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2234
2235 if (radv_pipeline_has_tess(pipeline))
2236 cmd_buffer->tess_rings_needed = true;
2237
2238 if (radv_pipeline_has_gs(pipeline)) {
2239 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2240 AC_UD_SCRATCH_RING_OFFSETS);
2241 if (cmd_buffer->ring_offsets_idx == -1)
2242 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2243 else if (loc->sgpr_idx != -1)
2244 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2245 }
2246 break;
2247 default:
2248 assert(!"invalid bind point");
2249 break;
2250 }
2251 }
2252
2253 void radv_CmdSetViewport(
2254 VkCommandBuffer commandBuffer,
2255 uint32_t firstViewport,
2256 uint32_t viewportCount,
2257 const VkViewport* pViewports)
2258 {
2259 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2260
2261 const uint32_t total_count = firstViewport + viewportCount;
2262 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2263 cmd_buffer->state.dynamic.viewport.count = total_count;
2264
2265 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2266 pViewports, viewportCount * sizeof(*pViewports));
2267
2268 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2269 }
2270
2271 void radv_CmdSetScissor(
2272 VkCommandBuffer commandBuffer,
2273 uint32_t firstScissor,
2274 uint32_t scissorCount,
2275 const VkRect2D* pScissors)
2276 {
2277 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2278
2279 const uint32_t total_count = firstScissor + scissorCount;
2280 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2281 cmd_buffer->state.dynamic.scissor.count = total_count;
2282
2283 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2284 pScissors, scissorCount * sizeof(*pScissors));
2285 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2286 }
2287
2288 void radv_CmdSetLineWidth(
2289 VkCommandBuffer commandBuffer,
2290 float lineWidth)
2291 {
2292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2293 cmd_buffer->state.dynamic.line_width = lineWidth;
2294 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2295 }
2296
2297 void radv_CmdSetDepthBias(
2298 VkCommandBuffer commandBuffer,
2299 float depthBiasConstantFactor,
2300 float depthBiasClamp,
2301 float depthBiasSlopeFactor)
2302 {
2303 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2304
2305 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2306 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2307 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2308
2309 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2310 }
2311
2312 void radv_CmdSetBlendConstants(
2313 VkCommandBuffer commandBuffer,
2314 const float blendConstants[4])
2315 {
2316 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2317
2318 memcpy(cmd_buffer->state.dynamic.blend_constants,
2319 blendConstants, sizeof(float) * 4);
2320
2321 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2322 }
2323
2324 void radv_CmdSetDepthBounds(
2325 VkCommandBuffer commandBuffer,
2326 float minDepthBounds,
2327 float maxDepthBounds)
2328 {
2329 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2330
2331 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2332 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2333
2334 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2335 }
2336
2337 void radv_CmdSetStencilCompareMask(
2338 VkCommandBuffer commandBuffer,
2339 VkStencilFaceFlags faceMask,
2340 uint32_t compareMask)
2341 {
2342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2343
2344 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2345 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2346 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2347 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2348
2349 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2350 }
2351
2352 void radv_CmdSetStencilWriteMask(
2353 VkCommandBuffer commandBuffer,
2354 VkStencilFaceFlags faceMask,
2355 uint32_t writeMask)
2356 {
2357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358
2359 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2360 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2361 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2362 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2363
2364 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2365 }
2366
2367 void radv_CmdSetStencilReference(
2368 VkCommandBuffer commandBuffer,
2369 VkStencilFaceFlags faceMask,
2370 uint32_t reference)
2371 {
2372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2373
2374 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2375 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2376 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2377 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2378
2379 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2380 }
2381
2382
2383 void radv_CmdExecuteCommands(
2384 VkCommandBuffer commandBuffer,
2385 uint32_t commandBufferCount,
2386 const VkCommandBuffer* pCmdBuffers)
2387 {
2388 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2389
2390 /* Emit pending flushes on primary prior to executing secondary */
2391 si_emit_cache_flush(primary);
2392
2393 for (uint32_t i = 0; i < commandBufferCount; i++) {
2394 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2395
2396 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2397 secondary->scratch_size_needed);
2398 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2399 secondary->compute_scratch_size_needed);
2400
2401 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2402 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2403 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2404 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2405 if (secondary->tess_rings_needed)
2406 primary->tess_rings_needed = true;
2407 if (secondary->sample_positions_needed)
2408 primary->sample_positions_needed = true;
2409
2410 if (secondary->ring_offsets_idx != -1) {
2411 if (primary->ring_offsets_idx == -1)
2412 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2413 else
2414 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2415 }
2416 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2417 }
2418
2419 /* if we execute secondary we need to re-emit out pipelines */
2420 if (commandBufferCount) {
2421 primary->state.emitted_pipeline = NULL;
2422 primary->state.emitted_compute_pipeline = NULL;
2423 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2424 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2425 primary->state.last_primitive_reset_en = -1;
2426 primary->state.last_primitive_reset_index = 0;
2427 }
2428 }
2429
2430 VkResult radv_CreateCommandPool(
2431 VkDevice _device,
2432 const VkCommandPoolCreateInfo* pCreateInfo,
2433 const VkAllocationCallbacks* pAllocator,
2434 VkCommandPool* pCmdPool)
2435 {
2436 RADV_FROM_HANDLE(radv_device, device, _device);
2437 struct radv_cmd_pool *pool;
2438
2439 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2440 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2441 if (pool == NULL)
2442 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2443
2444 if (pAllocator)
2445 pool->alloc = *pAllocator;
2446 else
2447 pool->alloc = device->alloc;
2448
2449 list_inithead(&pool->cmd_buffers);
2450 list_inithead(&pool->free_cmd_buffers);
2451
2452 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2453
2454 *pCmdPool = radv_cmd_pool_to_handle(pool);
2455
2456 return VK_SUCCESS;
2457
2458 }
2459
2460 void radv_DestroyCommandPool(
2461 VkDevice _device,
2462 VkCommandPool commandPool,
2463 const VkAllocationCallbacks* pAllocator)
2464 {
2465 RADV_FROM_HANDLE(radv_device, device, _device);
2466 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2467
2468 if (!pool)
2469 return;
2470
2471 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2472 &pool->cmd_buffers, pool_link) {
2473 radv_cmd_buffer_destroy(cmd_buffer);
2474 }
2475
2476 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2477 &pool->free_cmd_buffers, pool_link) {
2478 radv_cmd_buffer_destroy(cmd_buffer);
2479 }
2480
2481 vk_free2(&device->alloc, pAllocator, pool);
2482 }
2483
2484 VkResult radv_ResetCommandPool(
2485 VkDevice device,
2486 VkCommandPool commandPool,
2487 VkCommandPoolResetFlags flags)
2488 {
2489 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2490
2491 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2492 &pool->cmd_buffers, pool_link) {
2493 radv_reset_cmd_buffer(cmd_buffer);
2494 }
2495
2496 return VK_SUCCESS;
2497 }
2498
2499 void radv_TrimCommandPoolKHR(
2500 VkDevice device,
2501 VkCommandPool commandPool,
2502 VkCommandPoolTrimFlagsKHR flags)
2503 {
2504 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2505
2506 if (!pool)
2507 return;
2508
2509 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2510 &pool->free_cmd_buffers, pool_link) {
2511 radv_cmd_buffer_destroy(cmd_buffer);
2512 }
2513 }
2514
2515 void radv_CmdBeginRenderPass(
2516 VkCommandBuffer commandBuffer,
2517 const VkRenderPassBeginInfo* pRenderPassBegin,
2518 VkSubpassContents contents)
2519 {
2520 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2521 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2522 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2523
2524 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2525 cmd_buffer->cs, 2048);
2526
2527 cmd_buffer->state.framebuffer = framebuffer;
2528 cmd_buffer->state.pass = pass;
2529 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2530 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2531
2532 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2533 assert(cmd_buffer->cs->cdw <= cdw_max);
2534
2535 radv_cmd_buffer_clear_subpass(cmd_buffer);
2536 }
2537
2538 void radv_CmdNextSubpass(
2539 VkCommandBuffer commandBuffer,
2540 VkSubpassContents contents)
2541 {
2542 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2543
2544 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2545
2546 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2547 2048);
2548
2549 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2550 radv_cmd_buffer_clear_subpass(cmd_buffer);
2551 }
2552
2553 void radv_CmdDraw(
2554 VkCommandBuffer commandBuffer,
2555 uint32_t vertexCount,
2556 uint32_t instanceCount,
2557 uint32_t firstVertex,
2558 uint32_t firstInstance)
2559 {
2560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2561
2562 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2563
2564 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2565
2566 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2567 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2568 if (loc->sgpr_idx != -1) {
2569 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2570 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2571 int vs_num = 2;
2572 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2573 vs_num = 3;
2574
2575 assert (loc->num_sgprs == vs_num);
2576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2577 radeon_emit(cmd_buffer->cs, firstVertex);
2578 radeon_emit(cmd_buffer->cs, firstInstance);
2579 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2580 radeon_emit(cmd_buffer->cs, 0);
2581 }
2582 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2583 radeon_emit(cmd_buffer->cs, instanceCount);
2584
2585 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2586 radeon_emit(cmd_buffer->cs, vertexCount);
2587 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2588 S_0287F0_USE_OPAQUE(0));
2589
2590 assert(cmd_buffer->cs->cdw <= cdw_max);
2591
2592 radv_cmd_buffer_trace_emit(cmd_buffer);
2593 }
2594
2595 void radv_CmdDrawIndexed(
2596 VkCommandBuffer commandBuffer,
2597 uint32_t indexCount,
2598 uint32_t instanceCount,
2599 uint32_t firstIndex,
2600 int32_t vertexOffset,
2601 uint32_t firstInstance)
2602 {
2603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2604 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2605 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2606 uint64_t index_va;
2607
2608 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2609
2610 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2611
2612 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2613 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2614
2615 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2616 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2617 if (loc->sgpr_idx != -1) {
2618 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2619 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2620 int vs_num = 2;
2621 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2622 vs_num = 3;
2623
2624 assert (loc->num_sgprs == vs_num);
2625 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2626 radeon_emit(cmd_buffer->cs, vertexOffset);
2627 radeon_emit(cmd_buffer->cs, firstInstance);
2628 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2629 radeon_emit(cmd_buffer->cs, 0);
2630 }
2631 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2632 radeon_emit(cmd_buffer->cs, instanceCount);
2633
2634 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2635 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2636 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2637 radeon_emit(cmd_buffer->cs, index_max_size);
2638 radeon_emit(cmd_buffer->cs, index_va);
2639 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2640 radeon_emit(cmd_buffer->cs, indexCount);
2641 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2642
2643 assert(cmd_buffer->cs->cdw <= cdw_max);
2644 radv_cmd_buffer_trace_emit(cmd_buffer);
2645 }
2646
2647 static void
2648 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2649 VkBuffer _buffer,
2650 VkDeviceSize offset,
2651 VkBuffer _count_buffer,
2652 VkDeviceSize count_offset,
2653 uint32_t draw_count,
2654 uint32_t stride,
2655 bool indexed)
2656 {
2657 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2658 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2659 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2660 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2661 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2662 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2663 indirect_va += offset + buffer->offset;
2664 uint64_t count_va = 0;
2665
2666 if (count_buffer) {
2667 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2668 count_va += count_offset + count_buffer->offset;
2669 }
2670
2671 if (!draw_count)
2672 return;
2673
2674 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2675
2676 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2677 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2678 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2679 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2680 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2681 assert(loc->sgpr_idx != -1);
2682 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2683 radeon_emit(cs, 1);
2684 radeon_emit(cs, indirect_va);
2685 radeon_emit(cs, indirect_va >> 32);
2686
2687 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2688 PKT3_DRAW_INDIRECT_MULTI,
2689 8, false));
2690 radeon_emit(cs, 0);
2691 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2692 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2693 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2694 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2695 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2696 radeon_emit(cs, draw_count); /* count */
2697 radeon_emit(cs, count_va); /* count_addr */
2698 radeon_emit(cs, count_va >> 32);
2699 radeon_emit(cs, stride); /* stride */
2700 radeon_emit(cs, di_src_sel);
2701 radv_cmd_buffer_trace_emit(cmd_buffer);
2702 }
2703
2704 static void
2705 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2706 VkBuffer buffer,
2707 VkDeviceSize offset,
2708 VkBuffer countBuffer,
2709 VkDeviceSize countBufferOffset,
2710 uint32_t maxDrawCount,
2711 uint32_t stride)
2712 {
2713 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2714 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2715
2716 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2717 cmd_buffer->cs, 14);
2718
2719 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2720 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2721
2722 assert(cmd_buffer->cs->cdw <= cdw_max);
2723 }
2724
2725 static void
2726 radv_cmd_draw_indexed_indirect_count(
2727 VkCommandBuffer commandBuffer,
2728 VkBuffer buffer,
2729 VkDeviceSize offset,
2730 VkBuffer countBuffer,
2731 VkDeviceSize countBufferOffset,
2732 uint32_t maxDrawCount,
2733 uint32_t stride)
2734 {
2735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2736 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2737 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2738 uint64_t index_va;
2739 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2740
2741 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2742 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2743
2744 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2745
2746 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2747 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2748
2749 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2750 radeon_emit(cmd_buffer->cs, index_va);
2751 radeon_emit(cmd_buffer->cs, index_va >> 32);
2752
2753 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2754 radeon_emit(cmd_buffer->cs, index_max_size);
2755
2756 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2757 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2758
2759 assert(cmd_buffer->cs->cdw <= cdw_max);
2760 }
2761
2762 void radv_CmdDrawIndirect(
2763 VkCommandBuffer commandBuffer,
2764 VkBuffer buffer,
2765 VkDeviceSize offset,
2766 uint32_t drawCount,
2767 uint32_t stride)
2768 {
2769 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2770 VK_NULL_HANDLE, 0, drawCount, stride);
2771 }
2772
2773 void radv_CmdDrawIndexedIndirect(
2774 VkCommandBuffer commandBuffer,
2775 VkBuffer buffer,
2776 VkDeviceSize offset,
2777 uint32_t drawCount,
2778 uint32_t stride)
2779 {
2780 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2781 VK_NULL_HANDLE, 0, drawCount, stride);
2782 }
2783
2784 void radv_CmdDrawIndirectCountAMD(
2785 VkCommandBuffer commandBuffer,
2786 VkBuffer buffer,
2787 VkDeviceSize offset,
2788 VkBuffer countBuffer,
2789 VkDeviceSize countBufferOffset,
2790 uint32_t maxDrawCount,
2791 uint32_t stride)
2792 {
2793 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2794 countBuffer, countBufferOffset,
2795 maxDrawCount, stride);
2796 }
2797
2798 void radv_CmdDrawIndexedIndirectCountAMD(
2799 VkCommandBuffer commandBuffer,
2800 VkBuffer buffer,
2801 VkDeviceSize offset,
2802 VkBuffer countBuffer,
2803 VkDeviceSize countBufferOffset,
2804 uint32_t maxDrawCount,
2805 uint32_t stride)
2806 {
2807 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2808 countBuffer, countBufferOffset,
2809 maxDrawCount, stride);
2810 }
2811
2812 static void
2813 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2814 {
2815 radv_emit_compute_pipeline(cmd_buffer);
2816 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2817 VK_SHADER_STAGE_COMPUTE_BIT);
2818 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2819 VK_SHADER_STAGE_COMPUTE_BIT);
2820 si_emit_cache_flush(cmd_buffer);
2821 }
2822
2823 void radv_CmdDispatch(
2824 VkCommandBuffer commandBuffer,
2825 uint32_t x,
2826 uint32_t y,
2827 uint32_t z)
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2830
2831 radv_flush_compute_state(cmd_buffer);
2832
2833 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2834
2835 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2836 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2837 if (loc->sgpr_idx != -1) {
2838 assert(!loc->indirect);
2839 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2840 assert(loc->num_sgprs == grid_used);
2841 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2842 radeon_emit(cmd_buffer->cs, x);
2843 if (grid_used > 1)
2844 radeon_emit(cmd_buffer->cs, y);
2845 if (grid_used > 2)
2846 radeon_emit(cmd_buffer->cs, z);
2847 }
2848
2849 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2850 PKT3_SHADER_TYPE_S(1));
2851 radeon_emit(cmd_buffer->cs, x);
2852 radeon_emit(cmd_buffer->cs, y);
2853 radeon_emit(cmd_buffer->cs, z);
2854 radeon_emit(cmd_buffer->cs, 1);
2855
2856 assert(cmd_buffer->cs->cdw <= cdw_max);
2857 radv_cmd_buffer_trace_emit(cmd_buffer);
2858 }
2859
2860 void radv_CmdDispatchIndirect(
2861 VkCommandBuffer commandBuffer,
2862 VkBuffer _buffer,
2863 VkDeviceSize offset)
2864 {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2866 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2867 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2868 va += buffer->offset + offset;
2869
2870 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2871
2872 radv_flush_compute_state(cmd_buffer);
2873
2874 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2875 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2876 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2877 if (loc->sgpr_idx != -1) {
2878 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2879 for (unsigned i = 0; i < grid_used; ++i) {
2880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2881 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2882 COPY_DATA_DST_SEL(COPY_DATA_REG));
2883 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2884 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2885 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2886 radeon_emit(cmd_buffer->cs, 0);
2887 }
2888 }
2889
2890 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2891 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2892 PKT3_SHADER_TYPE_S(1));
2893 radeon_emit(cmd_buffer->cs, va);
2894 radeon_emit(cmd_buffer->cs, va >> 32);
2895 radeon_emit(cmd_buffer->cs, 1);
2896 } else {
2897 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2898 PKT3_SHADER_TYPE_S(1));
2899 radeon_emit(cmd_buffer->cs, 1);
2900 radeon_emit(cmd_buffer->cs, va);
2901 radeon_emit(cmd_buffer->cs, va >> 32);
2902
2903 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2904 PKT3_SHADER_TYPE_S(1));
2905 radeon_emit(cmd_buffer->cs, 0);
2906 radeon_emit(cmd_buffer->cs, 1);
2907 }
2908
2909 assert(cmd_buffer->cs->cdw <= cdw_max);
2910 radv_cmd_buffer_trace_emit(cmd_buffer);
2911 }
2912
2913 void radv_unaligned_dispatch(
2914 struct radv_cmd_buffer *cmd_buffer,
2915 uint32_t x,
2916 uint32_t y,
2917 uint32_t z)
2918 {
2919 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2920 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2921 uint32_t blocks[3], remainder[3];
2922
2923 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2924 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2925 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2926
2927 /* If aligned, these should be an entire block size, not 0 */
2928 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2929 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2930 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2931
2932 radv_flush_compute_state(cmd_buffer);
2933
2934 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2935
2936 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2937 radeon_emit(cmd_buffer->cs,
2938 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2939 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2940 radeon_emit(cmd_buffer->cs,
2941 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2942 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2943 radeon_emit(cmd_buffer->cs,
2944 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2945 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2946
2947 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2948 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2949 if (loc->sgpr_idx != -1) {
2950 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2951 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2952 radeon_emit(cmd_buffer->cs, blocks[0]);
2953 if (grid_used > 1)
2954 radeon_emit(cmd_buffer->cs, blocks[1]);
2955 if (grid_used > 2)
2956 radeon_emit(cmd_buffer->cs, blocks[2]);
2957 }
2958 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2959 PKT3_SHADER_TYPE_S(1));
2960 radeon_emit(cmd_buffer->cs, blocks[0]);
2961 radeon_emit(cmd_buffer->cs, blocks[1]);
2962 radeon_emit(cmd_buffer->cs, blocks[2]);
2963 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2964 S_00B800_PARTIAL_TG_EN(1));
2965
2966 assert(cmd_buffer->cs->cdw <= cdw_max);
2967 radv_cmd_buffer_trace_emit(cmd_buffer);
2968 }
2969
2970 void radv_CmdEndRenderPass(
2971 VkCommandBuffer commandBuffer)
2972 {
2973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2974
2975 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2976
2977 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2978
2979 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2980 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2981 radv_handle_subpass_image_transition(cmd_buffer,
2982 (VkAttachmentReference){i, layout});
2983 }
2984
2985 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2986
2987 cmd_buffer->state.pass = NULL;
2988 cmd_buffer->state.subpass = NULL;
2989 cmd_buffer->state.attachments = NULL;
2990 cmd_buffer->state.framebuffer = NULL;
2991 }
2992
2993
2994 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2995 struct radv_image *image,
2996 const VkImageSubresourceRange *range)
2997 {
2998 assert(range->baseMipLevel == 0);
2999 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3000 unsigned layer_count = radv_get_layerCount(image, range);
3001 uint64_t size = image->surface.htile_slice_size * layer_count;
3002 uint64_t offset = image->offset + image->htile_offset +
3003 image->surface.htile_slice_size * range->baseArrayLayer;
3004
3005 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3006 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3007
3008 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
3009
3010 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3011 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3012 RADV_CMD_FLAG_INV_VMEM_L1 |
3013 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3014 }
3015
3016 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3017 struct radv_image *image,
3018 VkImageLayout src_layout,
3019 VkImageLayout dst_layout,
3020 const VkImageSubresourceRange *range,
3021 VkImageAspectFlags pending_clears)
3022 {
3023 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3024 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3025 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3026 cmd_buffer->state.render_area.extent.width == image->extent.width &&
3027 cmd_buffer->state.render_area.extent.height == image->extent.height) {
3028 /* The clear will initialize htile. */
3029 return;
3030 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3031 radv_layout_has_htile(image, dst_layout)) {
3032 /* TODO: merge with the clear if applicable */
3033 radv_initialize_htile(cmd_buffer, image, range);
3034 } else if (!radv_layout_has_htile(image, src_layout) &&
3035 radv_layout_has_htile(image, dst_layout)) {
3036 radv_initialize_htile(cmd_buffer, image, range);
3037 } else if ((radv_layout_has_htile(image, src_layout) &&
3038 !radv_layout_has_htile(image, dst_layout)) ||
3039 (radv_layout_is_htile_compressed(image, src_layout) &&
3040 !radv_layout_is_htile_compressed(image, dst_layout))) {
3041 VkImageSubresourceRange local_range = *range;
3042 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3043 local_range.baseMipLevel = 0;
3044 local_range.levelCount = 1;
3045
3046 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3047 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3048
3049 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3050
3051 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3052 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3053 }
3054 }
3055
3056 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3057 struct radv_image *image, uint32_t value)
3058 {
3059 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3060 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3061
3062 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3063 image->cmask.size, value);
3064
3065 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3066 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3067 RADV_CMD_FLAG_INV_VMEM_L1 |
3068 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3069 }
3070
3071 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3072 struct radv_image *image,
3073 VkImageLayout src_layout,
3074 VkImageLayout dst_layout,
3075 unsigned src_queue_mask,
3076 unsigned dst_queue_mask,
3077 const VkImageSubresourceRange *range,
3078 VkImageAspectFlags pending_clears)
3079 {
3080 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3081 if (image->fmask.size)
3082 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3083 else
3084 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3085 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3086 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3087 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3088 }
3089 }
3090
3091 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3092 struct radv_image *image, uint32_t value)
3093 {
3094
3095 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3096 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3097
3098 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3099 image->surface.dcc_size, value);
3100
3101 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3102 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3103 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3104 RADV_CMD_FLAG_INV_VMEM_L1 |
3105 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3106 }
3107
3108 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3109 struct radv_image *image,
3110 VkImageLayout src_layout,
3111 VkImageLayout dst_layout,
3112 unsigned src_queue_mask,
3113 unsigned dst_queue_mask,
3114 const VkImageSubresourceRange *range,
3115 VkImageAspectFlags pending_clears)
3116 {
3117 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3118 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3119 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3120 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3121 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3122 }
3123 }
3124
3125 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3126 struct radv_image *image,
3127 VkImageLayout src_layout,
3128 VkImageLayout dst_layout,
3129 uint32_t src_family,
3130 uint32_t dst_family,
3131 const VkImageSubresourceRange *range,
3132 VkImageAspectFlags pending_clears)
3133 {
3134 if (image->exclusive && src_family != dst_family) {
3135 /* This is an acquire or a release operation and there will be
3136 * a corresponding release/acquire. Do the transition in the
3137 * most flexible queue. */
3138
3139 assert(src_family == cmd_buffer->queue_family_index ||
3140 dst_family == cmd_buffer->queue_family_index);
3141
3142 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3143 return;
3144
3145 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3146 (src_family == RADV_QUEUE_GENERAL ||
3147 dst_family == RADV_QUEUE_GENERAL))
3148 return;
3149 }
3150
3151 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3152 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3153
3154 if (image->surface.htile_size)
3155 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3156 dst_layout, range, pending_clears);
3157
3158 if (image->cmask.size)
3159 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3160 dst_layout, src_queue_mask,
3161 dst_queue_mask, range,
3162 pending_clears);
3163
3164 if (image->surface.dcc_size)
3165 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3166 dst_layout, src_queue_mask,
3167 dst_queue_mask, range,
3168 pending_clears);
3169 }
3170
3171 void radv_CmdPipelineBarrier(
3172 VkCommandBuffer commandBuffer,
3173 VkPipelineStageFlags srcStageMask,
3174 VkPipelineStageFlags destStageMask,
3175 VkBool32 byRegion,
3176 uint32_t memoryBarrierCount,
3177 const VkMemoryBarrier* pMemoryBarriers,
3178 uint32_t bufferMemoryBarrierCount,
3179 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3180 uint32_t imageMemoryBarrierCount,
3181 const VkImageMemoryBarrier* pImageMemoryBarriers)
3182 {
3183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3184 enum radv_cmd_flush_bits src_flush_bits = 0;
3185 enum radv_cmd_flush_bits dst_flush_bits = 0;
3186
3187 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3188 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3189 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3190 NULL);
3191 }
3192
3193 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3194 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3195 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3196 NULL);
3197 }
3198
3199 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3200 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3201 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3202 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3203 image);
3204 }
3205
3206 radv_stage_flush(cmd_buffer, srcStageMask);
3207 cmd_buffer->state.flush_bits |= src_flush_bits;
3208
3209 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3210 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3211 radv_handle_image_transition(cmd_buffer, image,
3212 pImageMemoryBarriers[i].oldLayout,
3213 pImageMemoryBarriers[i].newLayout,
3214 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3215 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3216 &pImageMemoryBarriers[i].subresourceRange,
3217 0);
3218 }
3219
3220 cmd_buffer->state.flush_bits |= dst_flush_bits;
3221 }
3222
3223
3224 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3225 struct radv_event *event,
3226 VkPipelineStageFlags stageMask,
3227 unsigned value)
3228 {
3229 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3230 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3231
3232 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3233
3234 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3235
3236 /* TODO: this is overkill. Probably should figure something out from
3237 * the stage mask. */
3238
3239 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3240 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3241 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3242 EVENT_INDEX(5));
3243 radeon_emit(cs, va);
3244 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3245 radeon_emit(cs, 2);
3246 radeon_emit(cs, 0);
3247 }
3248
3249 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3250 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3251 EVENT_INDEX(5));
3252 radeon_emit(cs, va);
3253 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3254 radeon_emit(cs, value);
3255 radeon_emit(cs, 0);
3256
3257 assert(cmd_buffer->cs->cdw <= cdw_max);
3258 }
3259
3260 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3261 VkEvent _event,
3262 VkPipelineStageFlags stageMask)
3263 {
3264 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3265 RADV_FROM_HANDLE(radv_event, event, _event);
3266
3267 write_event(cmd_buffer, event, stageMask, 1);
3268 }
3269
3270 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3271 VkEvent _event,
3272 VkPipelineStageFlags stageMask)
3273 {
3274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3275 RADV_FROM_HANDLE(radv_event, event, _event);
3276
3277 write_event(cmd_buffer, event, stageMask, 0);
3278 }
3279
3280 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3281 uint32_t eventCount,
3282 const VkEvent* pEvents,
3283 VkPipelineStageFlags srcStageMask,
3284 VkPipelineStageFlags dstStageMask,
3285 uint32_t memoryBarrierCount,
3286 const VkMemoryBarrier* pMemoryBarriers,
3287 uint32_t bufferMemoryBarrierCount,
3288 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3289 uint32_t imageMemoryBarrierCount,
3290 const VkImageMemoryBarrier* pImageMemoryBarriers)
3291 {
3292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3293 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3294
3295 for (unsigned i = 0; i < eventCount; ++i) {
3296 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3297 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3298
3299 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3300
3301 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3302
3303 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3304 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3305 radeon_emit(cs, va);
3306 radeon_emit(cs, va >> 32);
3307 radeon_emit(cs, 1); /* reference value */
3308 radeon_emit(cs, 0xffffffff); /* mask */
3309 radeon_emit(cs, 4); /* poll interval */
3310
3311 assert(cmd_buffer->cs->cdw <= cdw_max);
3312 }
3313
3314
3315 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3316 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3317
3318 radv_handle_image_transition(cmd_buffer, image,
3319 pImageMemoryBarriers[i].oldLayout,
3320 pImageMemoryBarriers[i].newLayout,
3321 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3322 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3323 &pImageMemoryBarriers[i].subresourceRange,
3324 0);
3325 }
3326
3327 /* TODO: figure out how to do memory barriers without waiting */
3328 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3329 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3330 RADV_CMD_FLAG_INV_VMEM_L1 |
3331 RADV_CMD_FLAG_INV_SMEM_L1;
3332 }