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radv: clean up radv_{set,load}_color_clear_regs() helpers
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_winsys_cs *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_winsys_cs *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_winsys_cs *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
564 return &shader->info.user_sgprs_locs.shader_data[idx];
565 }
566
567 static void
568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
569 struct radv_pipeline *pipeline,
570 gl_shader_stage stage,
571 int idx, uint64_t va)
572 {
573 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
574 uint32_t base_reg = pipeline->user_data_0[stage];
575 if (loc->sgpr_idx == -1)
576 return;
577
578 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
579 assert(!loc->indirect);
580
581 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
582 base_reg + loc->sgpr_idx * 4, va, false);
583 }
584
585 static void
586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_pipeline *pipeline,
588 struct radv_descriptor_state *descriptors_state,
589 gl_shader_stage stage)
590 {
591 struct radv_device *device = cmd_buffer->device;
592 struct radeon_winsys_cs *cs = cmd_buffer->cs;
593 uint32_t sh_base = pipeline->user_data_0[stage];
594 struct radv_userdata_locations *locs =
595 &pipeline->shaders[stage]->info.user_sgprs_locs;
596 unsigned mask;
597
598 mask = descriptors_state->dirty & descriptors_state->valid;
599
600 for (int i = 0; i < MAX_SETS; i++) {
601 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
602 if (loc->sgpr_idx != -1 && !loc->indirect)
603 continue;
604 mask &= ~(1 << i);
605 }
606
607 while (mask) {
608 int start, count;
609
610 u_bit_scan_consecutive_range(&mask, &start, &count);
611
612 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
613 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
614
615 radv_emit_shader_pointer_head(cs, sh_offset, count,
616 HAVE_32BIT_POINTERS);
617 for (int i = 0; i < count; i++) {
618 struct radv_descriptor_set *set =
619 descriptors_state->sets[start + i];
620
621 radv_emit_shader_pointer_body(device, cs, set->va,
622 HAVE_32BIT_POINTERS);
623 }
624 }
625 }
626
627 static void
628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 int num_samples = pipeline->graphics.ms.num_samples;
632 struct radv_multisample_state *ms = &pipeline->graphics.ms;
633 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
634
635 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
636 cmd_buffer->sample_positions_needed = true;
637
638 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
639 return;
640
641 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
642 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
643 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
646
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
648
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer->device->dfsm_allowed) {
651 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
652 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
653 }
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 uint64_t va;
661
662 if (!shader)
663 return;
664
665 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
668 }
669
670 static void
671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
672 struct radv_pipeline *pipeline,
673 bool vertex_stage_only)
674 {
675 struct radv_cmd_state *state = &cmd_buffer->state;
676 uint32_t mask = state->prefetch_L2_mask;
677
678 if (vertex_stage_only) {
679 /* Fast prefetch path for starting draws as soon as possible.
680 */
681 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
682 RADV_PREFETCH_VBO_DESCRIPTORS);
683 }
684
685 if (mask & RADV_PREFETCH_VS)
686 radv_emit_shader_prefetch(cmd_buffer,
687 pipeline->shaders[MESA_SHADER_VERTEX]);
688
689 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
690 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
691
692 if (mask & RADV_PREFETCH_TCS)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
695
696 if (mask & RADV_PREFETCH_TES)
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
699
700 if (mask & RADV_PREFETCH_GS) {
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_GEOMETRY]);
703 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
704 }
705
706 if (mask & RADV_PREFETCH_PS)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709
710 state->prefetch_L2_mask &= ~mask;
711 }
712
713 static void
714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
715 {
716 if (!cmd_buffer->device->physical_device->rbplus_allowed)
717 return;
718
719 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
720 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722
723 unsigned sx_ps_downconvert = 0;
724 unsigned sx_blend_opt_epsilon = 0;
725 unsigned sx_blend_opt_control = 0;
726
727 for (unsigned i = 0; i < subpass->color_count; ++i) {
728 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
729 continue;
730
731 int idx = subpass->color_attachments[i].attachment;
732 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
733
734 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
735 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
736 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
737 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
738
739 bool has_alpha, has_rgb;
740
741 /* Set if RGB and A are present. */
742 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
743
744 if (format == V_028C70_COLOR_8 ||
745 format == V_028C70_COLOR_16 ||
746 format == V_028C70_COLOR_32)
747 has_rgb = !has_alpha;
748 else
749 has_rgb = true;
750
751 /* Check the colormask and export format. */
752 if (!(colormask & 0x7))
753 has_rgb = false;
754 if (!(colormask & 0x8))
755 has_alpha = false;
756
757 if (spi_format == V_028714_SPI_SHADER_ZERO) {
758 has_rgb = false;
759 has_alpha = false;
760 }
761
762 /* Disable value checking for disabled channels. */
763 if (!has_rgb)
764 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
765 if (!has_alpha)
766 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
767
768 /* Enable down-conversion for 32bpp and smaller formats. */
769 switch (format) {
770 case V_028C70_COLOR_8:
771 case V_028C70_COLOR_8_8:
772 case V_028C70_COLOR_8_8_8_8:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
776 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
778 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
779 }
780 break;
781
782 case V_028C70_COLOR_5_6_5:
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
784 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
785 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
786 }
787 break;
788
789 case V_028C70_COLOR_1_5_5_5:
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
792 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
793 }
794 break;
795
796 case V_028C70_COLOR_4_4_4_4:
797 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
798 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
799 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
800 }
801 break;
802
803 case V_028C70_COLOR_32:
804 if (swap == V_028C70_SWAP_STD &&
805 spi_format == V_028714_SPI_SHADER_32_R)
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
807 else if (swap == V_028C70_SWAP_ALT_REV &&
808 spi_format == V_028714_SPI_SHADER_32_AR)
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
810 break;
811
812 case V_028C70_COLOR_16:
813 case V_028C70_COLOR_16_16:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
818 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
819 if (swap == V_028C70_SWAP_STD ||
820 swap == V_028C70_SWAP_STD_REV)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
822 else
823 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
824 }
825 break;
826
827 case V_028C70_COLOR_10_11_11:
828 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
830 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
831 }
832 break;
833
834 case V_028C70_COLOR_2_10_10_10:
835 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
837 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
838 }
839 break;
840 }
841 }
842
843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
844 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
845 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
846 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
847 }
848
849 static void
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
851 {
852 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
853
854 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
855 return;
856
857 radv_update_multisample_state(cmd_buffer, pipeline);
858
859 cmd_buffer->scratch_size_needed =
860 MAX2(cmd_buffer->scratch_size_needed,
861 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
862
863 if (!cmd_buffer->state.emitted_pipeline ||
864 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
865 pipeline->graphics.can_use_guardband)
866 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
867
868 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
869
870 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
871 if (!pipeline->shaders[i])
872 continue;
873
874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
875 pipeline->shaders[i]->bo, 8);
876 }
877
878 if (radv_pipeline_has_gs(pipeline))
879 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
880 pipeline->gs_copy_shader->bo, 8);
881
882 if (unlikely(cmd_buffer->device->trace_bo))
883 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
884
885 cmd_buffer->state.emitted_pipeline = pipeline;
886
887 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
888 }
889
890 static void
891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
892 {
893 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
894 cmd_buffer->state.dynamic.viewport.viewports);
895 }
896
897 static void
898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
899 {
900 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
901
902 si_write_scissors(cmd_buffer->cs, 0, count,
903 cmd_buffer->state.dynamic.scissor.scissors,
904 cmd_buffer->state.dynamic.viewport.viewports,
905 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
906 }
907
908 static void
909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
910 {
911 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
912 return;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
915 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
916 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
917 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
918 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
919 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
920 S_028214_BR_Y(rect.offset.y + rect.extent.height));
921 }
922 }
923
924 static void
925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
926 {
927 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
930 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
931 }
932
933 static void
934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
935 {
936 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
937
938 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
939 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
940 }
941
942 static void
943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs,
948 R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cmd_buffer->cs,
950 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
951 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
952 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer->cs,
955 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
956 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
957 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
958 S_028434_STENCILOPVAL_BF(1));
959 }
960
961 static void
962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
967 fui(d->depth_bounds.min));
968 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
969 fui(d->depth_bounds.max));
970 }
971
972 static void
973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
974 {
975 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
976 unsigned slope = fui(d->depth_bias.slope * 16.0f);
977 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
978
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
982 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
983 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
986 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
987 }
988
989 static void
990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
991 int index,
992 struct radv_attachment_info *att,
993 struct radv_image *image,
994 VkImageLayout layout)
995 {
996 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
997 struct radv_color_buffer_info *cb = &att->cb;
998 uint32_t cb_color_info = cb->cb_color_info;
999
1000 if (!radv_layout_dcc_compressed(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 cb_color_info &= C_028C70_DCC_ENABLE;
1005 }
1006
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013 radeon_emit(cmd_buffer->cs, cb_color_info);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041 if (is_vi) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043 }
1044 }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_ds_buffer_info *ds,
1050 struct radv_image *image, VkImageLayout layout,
1051 bool requires_cond_write)
1052 {
1053 uint32_t db_z_info = ds->db_z_info;
1054 uint32_t db_z_info_reg;
1055
1056 if (!radv_image_is_tc_compat_htile(image))
1057 return;
1058
1059 if (!radv_layout_has_htile(image, layout,
1060 radv_image_queue_family_mask(image,
1061 cmd_buffer->queue_family_index,
1062 cmd_buffer->queue_family_index))) {
1063 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064 }
1065
1066 db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069 db_z_info_reg = R_028038_DB_Z_INFO;
1070 } else {
1071 db_z_info_reg = R_028040_DB_Z_INFO;
1072 }
1073
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1076 */
1077 if (requires_cond_write) {
1078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080 const uint32_t write_space = 0 << 8; /* register */
1081 const uint32_t poll_space = 1 << 4; /* memory */
1082 const uint32_t function = 3 << 0; /* equal to the reference */
1083 const uint32_t options = write_space | poll_space | function;
1084 radeon_emit(cmd_buffer->cs, options);
1085
1086 /* poll address - location of the depth clear value */
1087 uint64_t va = radv_buffer_get_va(image->bo);
1088 va += image->offset + image->clear_value_offset;
1089
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1092 */
1093 if (vk_format_is_stencil(image->vk_format))
1094 va += 4;
1095
1096 radeon_emit(cmd_buffer->cs, va);
1097 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1100 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1103 radeon_emit(cmd_buffer->cs, db_z_info);
1104 } else {
1105 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106 }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 void
1175 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1176 struct radv_image *image,
1177 VkClearDepthStencilValue ds_clear_value,
1178 VkImageAspectFlags aspects)
1179 {
1180 uint64_t va = radv_buffer_get_va(image->bo);
1181 va += image->offset + image->clear_value_offset;
1182 unsigned reg_offset = 0, reg_count = 0;
1183
1184 assert(radv_image_has_htile(image));
1185
1186 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1187 ++reg_count;
1188 } else {
1189 ++reg_offset;
1190 va += 4;
1191 }
1192 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1193 ++reg_count;
1194
1195 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1196 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1197 S_370_WR_CONFIRM(1) |
1198 S_370_ENGINE_SEL(V_370_PFP));
1199 radeon_emit(cmd_buffer->cs, va);
1200 radeon_emit(cmd_buffer->cs, va >> 32);
1201 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1202 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1203 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1204 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1205
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1207 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1208 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1209 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1210 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1211
1212 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1213 * only needed when clearing Z to 0.0.
1214 */
1215 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1216 ds_clear_value.depth == 0.0) {
1217 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1218 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1219
1220 if (!framebuffer || !subpass)
1221 return;
1222
1223 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1224 return;
1225
1226 int idx = subpass->depth_stencil_attachment.attachment;
1227 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1228 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1229 struct radv_image *image = att->attachment->image;
1230
1231 /* Only needed if the image is currently bound as the depth
1232 * surface.
1233 */
1234 if (att->attachment->image != image)
1235 return;
1236
1237 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1238 layout, false);
1239 }
1240 }
1241
1242 static void
1243 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1244 struct radv_image *image)
1245 {
1246 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1247 uint64_t va = radv_buffer_get_va(image->bo);
1248 va += image->offset + image->clear_value_offset;
1249 unsigned reg_offset = 0, reg_count = 0;
1250
1251 if (!radv_image_has_htile(image))
1252 return;
1253
1254 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1255 ++reg_count;
1256 } else {
1257 ++reg_offset;
1258 va += 4;
1259 }
1260 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1261 ++reg_count;
1262
1263 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1264 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1265 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1266 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1267 radeon_emit(cmd_buffer->cs, va);
1268 radeon_emit(cmd_buffer->cs, va >> 32);
1269 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1270 radeon_emit(cmd_buffer->cs, 0);
1271
1272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1273 radeon_emit(cmd_buffer->cs, 0);
1274 }
1275
1276 /*
1277 * With DCC some colors don't require CMASK elimination before being
1278 * used as a texture. This sets a predicate value to determine if the
1279 * cmask eliminate is required.
1280 */
1281 void
1282 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1283 struct radv_image *image,
1284 bool value)
1285 {
1286 uint64_t pred_val = value;
1287 uint64_t va = radv_buffer_get_va(image->bo);
1288 va += image->offset + image->dcc_pred_offset;
1289
1290 assert(radv_image_has_dcc(image));
1291
1292 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1293 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1294 S_370_WR_CONFIRM(1) |
1295 S_370_ENGINE_SEL(V_370_PFP));
1296 radeon_emit(cmd_buffer->cs, va);
1297 radeon_emit(cmd_buffer->cs, va >> 32);
1298 radeon_emit(cmd_buffer->cs, pred_val);
1299 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1300 }
1301
1302 /**
1303 * Update the fast clear color values if the image is bound as a color buffer.
1304 */
1305 static void
1306 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1307 struct radv_image *image,
1308 int cb_idx,
1309 uint32_t color_values[2])
1310 {
1311 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1312 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1313 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1314 struct radv_attachment_info *att;
1315 uint32_t att_idx;
1316
1317 if (!framebuffer || !subpass)
1318 return;
1319
1320 att_idx = subpass->color_attachments[cb_idx].attachment;
1321 if (att_idx == VK_ATTACHMENT_UNUSED)
1322 return;
1323
1324 att = &framebuffer->attachments[att_idx];
1325 if (att->attachment->image != image)
1326 return;
1327
1328 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1329 radeon_emit(cs, color_values[0]);
1330 radeon_emit(cs, color_values[1]);
1331 }
1332
1333 /**
1334 * Set the clear color values to the image's metadata.
1335 */
1336 void
1337 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1338 struct radv_image *image,
1339 int cb_idx,
1340 uint32_t color_values[2])
1341 {
1342 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1343 uint64_t va = radv_buffer_get_va(image->bo);
1344
1345 va += image->offset + image->clear_value_offset;
1346
1347 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1348
1349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1351 S_370_WR_CONFIRM(1) |
1352 S_370_ENGINE_SEL(V_370_PFP));
1353 radeon_emit(cs, va);
1354 radeon_emit(cs, va >> 32);
1355 radeon_emit(cs, color_values[0]);
1356 radeon_emit(cs, color_values[1]);
1357
1358 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1359 color_values);
1360 }
1361
1362 /**
1363 * Load the clear color values from the image's metadata.
1364 */
1365 static void
1366 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1367 struct radv_image *image,
1368 int cb_idx)
1369 {
1370 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1371 uint64_t va = radv_buffer_get_va(image->bo);
1372
1373 va += image->offset + image->clear_value_offset;
1374
1375 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1376 return;
1377
1378 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1379
1380 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1381 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1382 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1383 COPY_DATA_COUNT_SEL);
1384 radeon_emit(cs, va);
1385 radeon_emit(cs, va >> 32);
1386 radeon_emit(cs, reg >> 2);
1387 radeon_emit(cs, 0);
1388
1389 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1390 radeon_emit(cs, 0);
1391 }
1392
1393 static void
1394 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1395 {
1396 int i;
1397 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1398 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1399
1400 /* this may happen for inherited secondary recording */
1401 if (!framebuffer)
1402 return;
1403
1404 for (i = 0; i < 8; ++i) {
1405 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1406 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1407 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1408 continue;
1409 }
1410
1411 int idx = subpass->color_attachments[i].attachment;
1412 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1413 struct radv_image *image = att->attachment->image;
1414 VkImageLayout layout = subpass->color_attachments[i].layout;
1415
1416 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1417
1418 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1419 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1420
1421 radv_load_color_clear_metadata(cmd_buffer, image, i);
1422 }
1423
1424 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1425 int idx = subpass->depth_stencil_attachment.attachment;
1426 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1427 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1428 struct radv_image *image = att->attachment->image;
1429 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1430 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1431 cmd_buffer->queue_family_index,
1432 cmd_buffer->queue_family_index);
1433 /* We currently don't support writing decompressed HTILE */
1434 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1435 radv_layout_is_htile_compressed(image, layout, queue_mask));
1436
1437 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1438
1439 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1440 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1441 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1442 }
1443 radv_load_depth_clear_regs(cmd_buffer, image);
1444 } else {
1445 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1446 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1447 else
1448 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1449
1450 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1451 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1452 }
1453 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1454 S_028208_BR_X(framebuffer->width) |
1455 S_028208_BR_Y(framebuffer->height));
1456
1457 if (cmd_buffer->device->dfsm_allowed) {
1458 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1459 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1460 }
1461
1462 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1463 }
1464
1465 static void
1466 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1467 {
1468 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1469 struct radv_cmd_state *state = &cmd_buffer->state;
1470
1471 if (state->index_type != state->last_index_type) {
1472 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1473 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1474 2, state->index_type);
1475 } else {
1476 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1477 radeon_emit(cs, state->index_type);
1478 }
1479
1480 state->last_index_type = state->index_type;
1481 }
1482
1483 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1484 radeon_emit(cs, state->index_va);
1485 radeon_emit(cs, state->index_va >> 32);
1486
1487 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1488 radeon_emit(cs, state->max_index_count);
1489
1490 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1491 }
1492
1493 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1494 {
1495 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1496 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1497 uint32_t pa_sc_mode_cntl_1 =
1498 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1499 uint32_t db_count_control;
1500
1501 if(!cmd_buffer->state.active_occlusion_queries) {
1502 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1503 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1504 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1505 has_perfect_queries) {
1506 /* Re-enable out-of-order rasterization if the
1507 * bound pipeline supports it and if it's has
1508 * been disabled before starting any perfect
1509 * occlusion queries.
1510 */
1511 radeon_set_context_reg(cmd_buffer->cs,
1512 R_028A4C_PA_SC_MODE_CNTL_1,
1513 pa_sc_mode_cntl_1);
1514 }
1515 db_count_control = 0;
1516 } else {
1517 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1518 }
1519 } else {
1520 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1521 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1522
1523 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1524 db_count_control =
1525 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1526 S_028004_SAMPLE_RATE(sample_rate) |
1527 S_028004_ZPASS_ENABLE(1) |
1528 S_028004_SLICE_EVEN_ENABLE(1) |
1529 S_028004_SLICE_ODD_ENABLE(1);
1530
1531 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1532 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1533 has_perfect_queries) {
1534 /* If the bound pipeline has enabled
1535 * out-of-order rasterization, we should
1536 * disable it before starting any perfect
1537 * occlusion queries.
1538 */
1539 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1540
1541 radeon_set_context_reg(cmd_buffer->cs,
1542 R_028A4C_PA_SC_MODE_CNTL_1,
1543 pa_sc_mode_cntl_1);
1544 }
1545 } else {
1546 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1547 S_028004_SAMPLE_RATE(sample_rate);
1548 }
1549 }
1550
1551 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1552 }
1553
1554 static void
1555 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1556 {
1557 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1558
1559 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1560 radv_emit_viewport(cmd_buffer);
1561
1562 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1563 !cmd_buffer->device->physical_device->has_scissor_bug)
1564 radv_emit_scissor(cmd_buffer);
1565
1566 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1567 radv_emit_line_width(cmd_buffer);
1568
1569 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1570 radv_emit_blend_constants(cmd_buffer);
1571
1572 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1573 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1574 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1575 radv_emit_stencil(cmd_buffer);
1576
1577 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1578 radv_emit_depth_bounds(cmd_buffer);
1579
1580 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1581 radv_emit_depth_bias(cmd_buffer);
1582
1583 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1584 radv_emit_discard_rectangle(cmd_buffer);
1585
1586 cmd_buffer->state.dirty &= ~states;
1587 }
1588
1589 static void
1590 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1591 VkPipelineBindPoint bind_point)
1592 {
1593 struct radv_descriptor_state *descriptors_state =
1594 radv_get_descriptors_state(cmd_buffer, bind_point);
1595 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1596 unsigned bo_offset;
1597
1598 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1599 set->mapped_ptr,
1600 &bo_offset))
1601 return;
1602
1603 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1604 set->va += bo_offset;
1605 }
1606
1607 static void
1608 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1609 VkPipelineBindPoint bind_point)
1610 {
1611 struct radv_descriptor_state *descriptors_state =
1612 radv_get_descriptors_state(cmd_buffer, bind_point);
1613 uint32_t size = MAX_SETS * 2 * 4;
1614 uint32_t offset;
1615 void *ptr;
1616
1617 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1618 256, &offset, &ptr))
1619 return;
1620
1621 for (unsigned i = 0; i < MAX_SETS; i++) {
1622 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1623 uint64_t set_va = 0;
1624 struct radv_descriptor_set *set = descriptors_state->sets[i];
1625 if (descriptors_state->valid & (1u << i))
1626 set_va = set->va;
1627 uptr[0] = set_va & 0xffffffff;
1628 uptr[1] = set_va >> 32;
1629 }
1630
1631 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1632 va += offset;
1633
1634 if (cmd_buffer->state.pipeline) {
1635 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1636 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1637 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1638
1639 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1640 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1641 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1642
1643 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1644 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1645 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1646
1647 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1648 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1649 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1650
1651 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1652 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1653 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1654 }
1655
1656 if (cmd_buffer->state.compute_pipeline)
1657 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1658 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1659 }
1660
1661 static void
1662 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1663 VkShaderStageFlags stages)
1664 {
1665 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1666 VK_PIPELINE_BIND_POINT_COMPUTE :
1667 VK_PIPELINE_BIND_POINT_GRAPHICS;
1668 struct radv_descriptor_state *descriptors_state =
1669 radv_get_descriptors_state(cmd_buffer, bind_point);
1670
1671 if (!descriptors_state->dirty)
1672 return;
1673
1674 if (descriptors_state->push_dirty)
1675 radv_flush_push_descriptors(cmd_buffer, bind_point);
1676
1677 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1678 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1679 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1680 }
1681
1682 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1683 cmd_buffer->cs,
1684 MAX_SETS * MESA_SHADER_STAGES * 4);
1685
1686 if (cmd_buffer->state.pipeline) {
1687 radv_foreach_stage(stage, stages) {
1688 if (!cmd_buffer->state.pipeline->shaders[stage])
1689 continue;
1690
1691 radv_emit_descriptor_pointers(cmd_buffer,
1692 cmd_buffer->state.pipeline,
1693 descriptors_state, stage);
1694 }
1695 }
1696
1697 if (cmd_buffer->state.compute_pipeline &&
1698 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1699 radv_emit_descriptor_pointers(cmd_buffer,
1700 cmd_buffer->state.compute_pipeline,
1701 descriptors_state,
1702 MESA_SHADER_COMPUTE);
1703 }
1704
1705 descriptors_state->dirty = 0;
1706 descriptors_state->push_dirty = false;
1707
1708 if (unlikely(cmd_buffer->device->trace_bo))
1709 radv_save_descriptors(cmd_buffer, bind_point);
1710
1711 assert(cmd_buffer->cs->cdw <= cdw_max);
1712 }
1713
1714 static void
1715 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1716 VkShaderStageFlags stages)
1717 {
1718 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1719 ? cmd_buffer->state.compute_pipeline
1720 : cmd_buffer->state.pipeline;
1721 struct radv_pipeline_layout *layout = pipeline->layout;
1722 struct radv_shader_variant *shader, *prev_shader;
1723 unsigned offset;
1724 void *ptr;
1725 uint64_t va;
1726
1727 stages &= cmd_buffer->push_constant_stages;
1728 if (!stages ||
1729 (!layout->push_constant_size && !layout->dynamic_offset_count))
1730 return;
1731
1732 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1733 16 * layout->dynamic_offset_count,
1734 256, &offset, &ptr))
1735 return;
1736
1737 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1738 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1739 16 * layout->dynamic_offset_count);
1740
1741 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1742 va += offset;
1743
1744 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1745 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1746
1747 prev_shader = NULL;
1748 radv_foreach_stage(stage, stages) {
1749 shader = radv_get_shader(pipeline, stage);
1750
1751 /* Avoid redundantly emitting the address for merged stages. */
1752 if (shader && shader != prev_shader) {
1753 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1754 AC_UD_PUSH_CONSTANTS, va);
1755
1756 prev_shader = shader;
1757 }
1758 }
1759
1760 cmd_buffer->push_constant_stages &= ~stages;
1761 assert(cmd_buffer->cs->cdw <= cdw_max);
1762 }
1763
1764 static void
1765 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1766 bool pipeline_is_dirty)
1767 {
1768 if ((pipeline_is_dirty ||
1769 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1770 cmd_buffer->state.pipeline->vertex_elements.count &&
1771 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1772 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1773 unsigned vb_offset;
1774 void *vb_ptr;
1775 uint32_t i = 0;
1776 uint32_t count = velems->count;
1777 uint64_t va;
1778
1779 /* allocate some descriptor state for vertex buffers */
1780 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1781 &vb_offset, &vb_ptr))
1782 return;
1783
1784 for (i = 0; i < count; i++) {
1785 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1786 uint32_t offset;
1787 int vb = velems->binding[i];
1788 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1789 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1790
1791 va = radv_buffer_get_va(buffer->bo);
1792
1793 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1794 va += offset + buffer->offset;
1795 desc[0] = va;
1796 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1797 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1798 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1799 else
1800 desc[2] = buffer->size - offset;
1801 desc[3] = velems->rsrc_word3[i];
1802 }
1803
1804 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1805 va += vb_offset;
1806
1807 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1808 AC_UD_VS_VERTEX_BUFFERS, va);
1809
1810 cmd_buffer->state.vb_va = va;
1811 cmd_buffer->state.vb_size = count * 16;
1812 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1813 }
1814 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1815 }
1816
1817 static void
1818 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1819 {
1820 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1821 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1822 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1823 }
1824
1825 static void
1826 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1827 bool instanced_draw, bool indirect_draw,
1828 uint32_t draw_vertex_count)
1829 {
1830 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1831 struct radv_cmd_state *state = &cmd_buffer->state;
1832 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1833 uint32_t ia_multi_vgt_param;
1834 int32_t primitive_reset_en;
1835
1836 /* Draw state. */
1837 ia_multi_vgt_param =
1838 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1839 indirect_draw, draw_vertex_count);
1840
1841 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1842 if (info->chip_class >= GFX9) {
1843 radeon_set_uconfig_reg_idx(cs,
1844 R_030960_IA_MULTI_VGT_PARAM,
1845 4, ia_multi_vgt_param);
1846 } else if (info->chip_class >= CIK) {
1847 radeon_set_context_reg_idx(cs,
1848 R_028AA8_IA_MULTI_VGT_PARAM,
1849 1, ia_multi_vgt_param);
1850 } else {
1851 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1852 ia_multi_vgt_param);
1853 }
1854 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1855 }
1856
1857 /* Primitive restart. */
1858 primitive_reset_en =
1859 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1860
1861 if (primitive_reset_en != state->last_primitive_reset_en) {
1862 state->last_primitive_reset_en = primitive_reset_en;
1863 if (info->chip_class >= GFX9) {
1864 radeon_set_uconfig_reg(cs,
1865 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1866 primitive_reset_en);
1867 } else {
1868 radeon_set_context_reg(cs,
1869 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1870 primitive_reset_en);
1871 }
1872 }
1873
1874 if (primitive_reset_en) {
1875 uint32_t primitive_reset_index =
1876 state->index_type ? 0xffffffffu : 0xffffu;
1877
1878 if (primitive_reset_index != state->last_primitive_reset_index) {
1879 radeon_set_context_reg(cs,
1880 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1881 primitive_reset_index);
1882 state->last_primitive_reset_index = primitive_reset_index;
1883 }
1884 }
1885 }
1886
1887 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1888 VkPipelineStageFlags src_stage_mask)
1889 {
1890 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1891 VK_PIPELINE_STAGE_TRANSFER_BIT |
1892 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1893 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1894 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1895 }
1896
1897 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1898 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1899 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1900 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1901 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1902 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1903 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1904 VK_PIPELINE_STAGE_TRANSFER_BIT |
1905 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1906 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1907 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1908 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1909 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1910 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1911 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1912 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1913 }
1914 }
1915
1916 static enum radv_cmd_flush_bits
1917 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1918 VkAccessFlags src_flags)
1919 {
1920 enum radv_cmd_flush_bits flush_bits = 0;
1921 uint32_t b;
1922 for_each_bit(b, src_flags) {
1923 switch ((VkAccessFlagBits)(1 << b)) {
1924 case VK_ACCESS_SHADER_WRITE_BIT:
1925 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1926 break;
1927 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1928 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1929 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1930 break;
1931 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1932 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1933 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1934 break;
1935 case VK_ACCESS_TRANSFER_WRITE_BIT:
1936 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1937 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1938 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1939 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1940 RADV_CMD_FLAG_INV_GLOBAL_L2;
1941 break;
1942 default:
1943 break;
1944 }
1945 }
1946 return flush_bits;
1947 }
1948
1949 static enum radv_cmd_flush_bits
1950 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1951 VkAccessFlags dst_flags,
1952 struct radv_image *image)
1953 {
1954 enum radv_cmd_flush_bits flush_bits = 0;
1955 uint32_t b;
1956 for_each_bit(b, dst_flags) {
1957 switch ((VkAccessFlagBits)(1 << b)) {
1958 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1959 case VK_ACCESS_INDEX_READ_BIT:
1960 break;
1961 case VK_ACCESS_UNIFORM_READ_BIT:
1962 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1963 break;
1964 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1965 case VK_ACCESS_SHADER_READ_BIT:
1966 case VK_ACCESS_TRANSFER_READ_BIT:
1967 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1968 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1969 RADV_CMD_FLAG_INV_GLOBAL_L2;
1970 break;
1971 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1972 /* TODO: change to image && when the image gets passed
1973 * through from the subpass. */
1974 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1975 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1976 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1977 break;
1978 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1979 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1980 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1981 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1982 break;
1983 default:
1984 break;
1985 }
1986 }
1987 return flush_bits;
1988 }
1989
1990 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1991 {
1992 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1993 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1994 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1995 NULL);
1996 }
1997
1998 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1999 VkAttachmentReference att)
2000 {
2001 unsigned idx = att.attachment;
2002 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2003 VkImageSubresourceRange range;
2004 range.aspectMask = 0;
2005 range.baseMipLevel = view->base_mip;
2006 range.levelCount = 1;
2007 range.baseArrayLayer = view->base_layer;
2008 range.layerCount = cmd_buffer->state.framebuffer->layers;
2009
2010 radv_handle_image_transition(cmd_buffer,
2011 view->image,
2012 cmd_buffer->state.attachments[idx].current_layout,
2013 att.layout, 0, 0, &range,
2014 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2015
2016 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2017
2018
2019 }
2020
2021 void
2022 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2023 const struct radv_subpass *subpass, bool transitions)
2024 {
2025 if (transitions) {
2026 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2027
2028 for (unsigned i = 0; i < subpass->color_count; ++i) {
2029 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2030 radv_handle_subpass_image_transition(cmd_buffer,
2031 subpass->color_attachments[i]);
2032 }
2033
2034 for (unsigned i = 0; i < subpass->input_count; ++i) {
2035 radv_handle_subpass_image_transition(cmd_buffer,
2036 subpass->input_attachments[i]);
2037 }
2038
2039 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2040 radv_handle_subpass_image_transition(cmd_buffer,
2041 subpass->depth_stencil_attachment);
2042 }
2043 }
2044
2045 cmd_buffer->state.subpass = subpass;
2046
2047 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2048 }
2049
2050 static VkResult
2051 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2052 struct radv_render_pass *pass,
2053 const VkRenderPassBeginInfo *info)
2054 {
2055 struct radv_cmd_state *state = &cmd_buffer->state;
2056
2057 if (pass->attachment_count == 0) {
2058 state->attachments = NULL;
2059 return VK_SUCCESS;
2060 }
2061
2062 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2063 pass->attachment_count *
2064 sizeof(state->attachments[0]),
2065 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2066 if (state->attachments == NULL) {
2067 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2068 return cmd_buffer->record_result;
2069 }
2070
2071 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2072 struct radv_render_pass_attachment *att = &pass->attachments[i];
2073 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2074 VkImageAspectFlags clear_aspects = 0;
2075
2076 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2077 /* color attachment */
2078 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2079 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2080 }
2081 } else {
2082 /* depthstencil attachment */
2083 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2084 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2085 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2086 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2087 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2088 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2089 }
2090 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2091 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2092 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2093 }
2094 }
2095
2096 state->attachments[i].pending_clear_aspects = clear_aspects;
2097 state->attachments[i].cleared_views = 0;
2098 if (clear_aspects && info) {
2099 assert(info->clearValueCount > i);
2100 state->attachments[i].clear_value = info->pClearValues[i];
2101 }
2102
2103 state->attachments[i].current_layout = att->initial_layout;
2104 }
2105
2106 return VK_SUCCESS;
2107 }
2108
2109 VkResult radv_AllocateCommandBuffers(
2110 VkDevice _device,
2111 const VkCommandBufferAllocateInfo *pAllocateInfo,
2112 VkCommandBuffer *pCommandBuffers)
2113 {
2114 RADV_FROM_HANDLE(radv_device, device, _device);
2115 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2116
2117 VkResult result = VK_SUCCESS;
2118 uint32_t i;
2119
2120 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2121
2122 if (!list_empty(&pool->free_cmd_buffers)) {
2123 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2124
2125 list_del(&cmd_buffer->pool_link);
2126 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2127
2128 result = radv_reset_cmd_buffer(cmd_buffer);
2129 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2130 cmd_buffer->level = pAllocateInfo->level;
2131
2132 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2133 } else {
2134 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2135 &pCommandBuffers[i]);
2136 }
2137 if (result != VK_SUCCESS)
2138 break;
2139 }
2140
2141 if (result != VK_SUCCESS) {
2142 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2143 i, pCommandBuffers);
2144
2145 /* From the Vulkan 1.0.66 spec:
2146 *
2147 * "vkAllocateCommandBuffers can be used to create multiple
2148 * command buffers. If the creation of any of those command
2149 * buffers fails, the implementation must destroy all
2150 * successfully created command buffer objects from this
2151 * command, set all entries of the pCommandBuffers array to
2152 * NULL and return the error."
2153 */
2154 memset(pCommandBuffers, 0,
2155 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2156 }
2157
2158 return result;
2159 }
2160
2161 void radv_FreeCommandBuffers(
2162 VkDevice device,
2163 VkCommandPool commandPool,
2164 uint32_t commandBufferCount,
2165 const VkCommandBuffer *pCommandBuffers)
2166 {
2167 for (uint32_t i = 0; i < commandBufferCount; i++) {
2168 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2169
2170 if (cmd_buffer) {
2171 if (cmd_buffer->pool) {
2172 list_del(&cmd_buffer->pool_link);
2173 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2174 } else
2175 radv_cmd_buffer_destroy(cmd_buffer);
2176
2177 }
2178 }
2179 }
2180
2181 VkResult radv_ResetCommandBuffer(
2182 VkCommandBuffer commandBuffer,
2183 VkCommandBufferResetFlags flags)
2184 {
2185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2186 return radv_reset_cmd_buffer(cmd_buffer);
2187 }
2188
2189 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2190 {
2191 struct radv_device *device = cmd_buffer->device;
2192 if (device->gfx_init) {
2193 uint64_t va = radv_buffer_get_va(device->gfx_init);
2194 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2195 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2196 radeon_emit(cmd_buffer->cs, va);
2197 radeon_emit(cmd_buffer->cs, va >> 32);
2198 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2199 } else
2200 si_init_config(cmd_buffer);
2201 }
2202
2203 VkResult radv_BeginCommandBuffer(
2204 VkCommandBuffer commandBuffer,
2205 const VkCommandBufferBeginInfo *pBeginInfo)
2206 {
2207 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2208 VkResult result = VK_SUCCESS;
2209
2210 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2211 /* If the command buffer has already been resetted with
2212 * vkResetCommandBuffer, no need to do it again.
2213 */
2214 result = radv_reset_cmd_buffer(cmd_buffer);
2215 if (result != VK_SUCCESS)
2216 return result;
2217 }
2218
2219 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2220 cmd_buffer->state.last_primitive_reset_en = -1;
2221 cmd_buffer->state.last_index_type = -1;
2222 cmd_buffer->state.last_num_instances = -1;
2223 cmd_buffer->state.last_vertex_offset = -1;
2224 cmd_buffer->state.last_first_instance = -1;
2225 cmd_buffer->usage_flags = pBeginInfo->flags;
2226
2227 /* setup initial configuration into command buffer */
2228 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2229 switch (cmd_buffer->queue_family_index) {
2230 case RADV_QUEUE_GENERAL:
2231 emit_gfx_buffer_state(cmd_buffer);
2232 break;
2233 case RADV_QUEUE_COMPUTE:
2234 si_init_compute(cmd_buffer);
2235 break;
2236 case RADV_QUEUE_TRANSFER:
2237 default:
2238 break;
2239 }
2240 }
2241
2242 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2243 assert(pBeginInfo->pInheritanceInfo);
2244 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2245 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2246
2247 struct radv_subpass *subpass =
2248 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2249
2250 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2251 if (result != VK_SUCCESS)
2252 return result;
2253
2254 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2255 }
2256
2257 if (unlikely(cmd_buffer->device->trace_bo))
2258 radv_cmd_buffer_trace_emit(cmd_buffer);
2259
2260 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2261
2262 return result;
2263 }
2264
2265 void radv_CmdBindVertexBuffers(
2266 VkCommandBuffer commandBuffer,
2267 uint32_t firstBinding,
2268 uint32_t bindingCount,
2269 const VkBuffer* pBuffers,
2270 const VkDeviceSize* pOffsets)
2271 {
2272 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2273 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2274 bool changed = false;
2275
2276 /* We have to defer setting up vertex buffer since we need the buffer
2277 * stride from the pipeline. */
2278
2279 assert(firstBinding + bindingCount <= MAX_VBS);
2280 for (uint32_t i = 0; i < bindingCount; i++) {
2281 uint32_t idx = firstBinding + i;
2282
2283 if (!changed &&
2284 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2285 vb[idx].offset != pOffsets[i])) {
2286 changed = true;
2287 }
2288
2289 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2290 vb[idx].offset = pOffsets[i];
2291
2292 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2293 vb[idx].buffer->bo, 8);
2294 }
2295
2296 if (!changed) {
2297 /* No state changes. */
2298 return;
2299 }
2300
2301 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2302 }
2303
2304 void radv_CmdBindIndexBuffer(
2305 VkCommandBuffer commandBuffer,
2306 VkBuffer buffer,
2307 VkDeviceSize offset,
2308 VkIndexType indexType)
2309 {
2310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2311 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2312
2313 if (cmd_buffer->state.index_buffer == index_buffer &&
2314 cmd_buffer->state.index_offset == offset &&
2315 cmd_buffer->state.index_type == indexType) {
2316 /* No state changes. */
2317 return;
2318 }
2319
2320 cmd_buffer->state.index_buffer = index_buffer;
2321 cmd_buffer->state.index_offset = offset;
2322 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2323 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2324 cmd_buffer->state.index_va += index_buffer->offset + offset;
2325
2326 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2327 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2329 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2330 }
2331
2332
2333 static void
2334 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2335 VkPipelineBindPoint bind_point,
2336 struct radv_descriptor_set *set, unsigned idx)
2337 {
2338 struct radeon_winsys *ws = cmd_buffer->device->ws;
2339
2340 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2341 if (!set)
2342 return;
2343
2344 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2345
2346 if (!cmd_buffer->device->use_global_bo_list) {
2347 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2348 if (set->descriptors[j])
2349 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2350 }
2351
2352 if(set->bo)
2353 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2354 }
2355
2356 void radv_CmdBindDescriptorSets(
2357 VkCommandBuffer commandBuffer,
2358 VkPipelineBindPoint pipelineBindPoint,
2359 VkPipelineLayout _layout,
2360 uint32_t firstSet,
2361 uint32_t descriptorSetCount,
2362 const VkDescriptorSet* pDescriptorSets,
2363 uint32_t dynamicOffsetCount,
2364 const uint32_t* pDynamicOffsets)
2365 {
2366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2367 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2368 unsigned dyn_idx = 0;
2369
2370 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2371
2372 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2373 unsigned idx = i + firstSet;
2374 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2375 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2376
2377 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2378 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2379 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2380 assert(dyn_idx < dynamicOffsetCount);
2381
2382 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2383 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2384 dst[0] = va;
2385 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2386 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2387 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2388 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2389 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2390 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2391 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2392 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2393 cmd_buffer->push_constant_stages |=
2394 set->layout->dynamic_shader_stages;
2395 }
2396 }
2397 }
2398
2399 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2400 struct radv_descriptor_set *set,
2401 struct radv_descriptor_set_layout *layout,
2402 VkPipelineBindPoint bind_point)
2403 {
2404 struct radv_descriptor_state *descriptors_state =
2405 radv_get_descriptors_state(cmd_buffer, bind_point);
2406 set->size = layout->size;
2407 set->layout = layout;
2408
2409 if (descriptors_state->push_set.capacity < set->size) {
2410 size_t new_size = MAX2(set->size, 1024);
2411 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2412 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2413
2414 free(set->mapped_ptr);
2415 set->mapped_ptr = malloc(new_size);
2416
2417 if (!set->mapped_ptr) {
2418 descriptors_state->push_set.capacity = 0;
2419 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2420 return false;
2421 }
2422
2423 descriptors_state->push_set.capacity = new_size;
2424 }
2425
2426 return true;
2427 }
2428
2429 void radv_meta_push_descriptor_set(
2430 struct radv_cmd_buffer* cmd_buffer,
2431 VkPipelineBindPoint pipelineBindPoint,
2432 VkPipelineLayout _layout,
2433 uint32_t set,
2434 uint32_t descriptorWriteCount,
2435 const VkWriteDescriptorSet* pDescriptorWrites)
2436 {
2437 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2438 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2439 unsigned bo_offset;
2440
2441 assert(set == 0);
2442 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2443
2444 push_set->size = layout->set[set].layout->size;
2445 push_set->layout = layout->set[set].layout;
2446
2447 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2448 &bo_offset,
2449 (void**) &push_set->mapped_ptr))
2450 return;
2451
2452 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2453 push_set->va += bo_offset;
2454
2455 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2456 radv_descriptor_set_to_handle(push_set),
2457 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2458
2459 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2460 }
2461
2462 void radv_CmdPushDescriptorSetKHR(
2463 VkCommandBuffer commandBuffer,
2464 VkPipelineBindPoint pipelineBindPoint,
2465 VkPipelineLayout _layout,
2466 uint32_t set,
2467 uint32_t descriptorWriteCount,
2468 const VkWriteDescriptorSet* pDescriptorWrites)
2469 {
2470 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2471 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2472 struct radv_descriptor_state *descriptors_state =
2473 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2474 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2475
2476 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2477
2478 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2479 layout->set[set].layout,
2480 pipelineBindPoint))
2481 return;
2482
2483 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2484 radv_descriptor_set_to_handle(push_set),
2485 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2486
2487 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2488 descriptors_state->push_dirty = true;
2489 }
2490
2491 void radv_CmdPushDescriptorSetWithTemplateKHR(
2492 VkCommandBuffer commandBuffer,
2493 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2494 VkPipelineLayout _layout,
2495 uint32_t set,
2496 const void* pData)
2497 {
2498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2499 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2500 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2501 struct radv_descriptor_state *descriptors_state =
2502 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2503 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2504
2505 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2506
2507 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2508 layout->set[set].layout,
2509 templ->bind_point))
2510 return;
2511
2512 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2513 descriptorUpdateTemplate, pData);
2514
2515 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2516 descriptors_state->push_dirty = true;
2517 }
2518
2519 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2520 VkPipelineLayout layout,
2521 VkShaderStageFlags stageFlags,
2522 uint32_t offset,
2523 uint32_t size,
2524 const void* pValues)
2525 {
2526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2527 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2528 cmd_buffer->push_constant_stages |= stageFlags;
2529 }
2530
2531 VkResult radv_EndCommandBuffer(
2532 VkCommandBuffer commandBuffer)
2533 {
2534 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2535
2536 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2537 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2538 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2539 si_emit_cache_flush(cmd_buffer);
2540 }
2541
2542 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2543
2544 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2545 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2546
2547 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2548
2549 return cmd_buffer->record_result;
2550 }
2551
2552 static void
2553 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2554 {
2555 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2556
2557 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2558 return;
2559
2560 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2561
2562 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2563 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2564
2565 cmd_buffer->compute_scratch_size_needed =
2566 MAX2(cmd_buffer->compute_scratch_size_needed,
2567 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2568
2569 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2570 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2571
2572 if (unlikely(cmd_buffer->device->trace_bo))
2573 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2574 }
2575
2576 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2577 VkPipelineBindPoint bind_point)
2578 {
2579 struct radv_descriptor_state *descriptors_state =
2580 radv_get_descriptors_state(cmd_buffer, bind_point);
2581
2582 descriptors_state->dirty |= descriptors_state->valid;
2583 }
2584
2585 void radv_CmdBindPipeline(
2586 VkCommandBuffer commandBuffer,
2587 VkPipelineBindPoint pipelineBindPoint,
2588 VkPipeline _pipeline)
2589 {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2591 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2592
2593 switch (pipelineBindPoint) {
2594 case VK_PIPELINE_BIND_POINT_COMPUTE:
2595 if (cmd_buffer->state.compute_pipeline == pipeline)
2596 return;
2597 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2598
2599 cmd_buffer->state.compute_pipeline = pipeline;
2600 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2601 break;
2602 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2603 if (cmd_buffer->state.pipeline == pipeline)
2604 return;
2605 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2606
2607 cmd_buffer->state.pipeline = pipeline;
2608 if (!pipeline)
2609 break;
2610
2611 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2612 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2613
2614 /* the new vertex shader might not have the same user regs */
2615 cmd_buffer->state.last_first_instance = -1;
2616 cmd_buffer->state.last_vertex_offset = -1;
2617
2618 /* Prefetch all pipeline shaders at first draw time. */
2619 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2620
2621 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2622
2623 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2624 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2625 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2626 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2627
2628 if (radv_pipeline_has_tess(pipeline))
2629 cmd_buffer->tess_rings_needed = true;
2630
2631 if (radv_pipeline_has_gs(pipeline)) {
2632 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2633 AC_UD_SCRATCH_RING_OFFSETS);
2634 if (cmd_buffer->ring_offsets_idx == -1)
2635 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2636 else if (loc->sgpr_idx != -1)
2637 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2638 }
2639 break;
2640 default:
2641 assert(!"invalid bind point");
2642 break;
2643 }
2644 }
2645
2646 void radv_CmdSetViewport(
2647 VkCommandBuffer commandBuffer,
2648 uint32_t firstViewport,
2649 uint32_t viewportCount,
2650 const VkViewport* pViewports)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653 struct radv_cmd_state *state = &cmd_buffer->state;
2654 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2655
2656 assert(firstViewport < MAX_VIEWPORTS);
2657 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2658
2659 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2660 viewportCount * sizeof(*pViewports));
2661
2662 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2663 }
2664
2665 void radv_CmdSetScissor(
2666 VkCommandBuffer commandBuffer,
2667 uint32_t firstScissor,
2668 uint32_t scissorCount,
2669 const VkRect2D* pScissors)
2670 {
2671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2672 struct radv_cmd_state *state = &cmd_buffer->state;
2673 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2674
2675 assert(firstScissor < MAX_SCISSORS);
2676 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2677
2678 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2679 scissorCount * sizeof(*pScissors));
2680
2681 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2682 }
2683
2684 void radv_CmdSetLineWidth(
2685 VkCommandBuffer commandBuffer,
2686 float lineWidth)
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2689 cmd_buffer->state.dynamic.line_width = lineWidth;
2690 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2691 }
2692
2693 void radv_CmdSetDepthBias(
2694 VkCommandBuffer commandBuffer,
2695 float depthBiasConstantFactor,
2696 float depthBiasClamp,
2697 float depthBiasSlopeFactor)
2698 {
2699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2700
2701 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2702 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2703 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2704
2705 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2706 }
2707
2708 void radv_CmdSetBlendConstants(
2709 VkCommandBuffer commandBuffer,
2710 const float blendConstants[4])
2711 {
2712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2713
2714 memcpy(cmd_buffer->state.dynamic.blend_constants,
2715 blendConstants, sizeof(float) * 4);
2716
2717 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2718 }
2719
2720 void radv_CmdSetDepthBounds(
2721 VkCommandBuffer commandBuffer,
2722 float minDepthBounds,
2723 float maxDepthBounds)
2724 {
2725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2726
2727 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2728 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2729
2730 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2731 }
2732
2733 void radv_CmdSetStencilCompareMask(
2734 VkCommandBuffer commandBuffer,
2735 VkStencilFaceFlags faceMask,
2736 uint32_t compareMask)
2737 {
2738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2739
2740 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2741 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2742 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2743 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2744
2745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2746 }
2747
2748 void radv_CmdSetStencilWriteMask(
2749 VkCommandBuffer commandBuffer,
2750 VkStencilFaceFlags faceMask,
2751 uint32_t writeMask)
2752 {
2753 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2754
2755 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2756 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2757 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2758 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2759
2760 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2761 }
2762
2763 void radv_CmdSetStencilReference(
2764 VkCommandBuffer commandBuffer,
2765 VkStencilFaceFlags faceMask,
2766 uint32_t reference)
2767 {
2768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2769
2770 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2771 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2772 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2773 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2774
2775 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2776 }
2777
2778 void radv_CmdSetDiscardRectangleEXT(
2779 VkCommandBuffer commandBuffer,
2780 uint32_t firstDiscardRectangle,
2781 uint32_t discardRectangleCount,
2782 const VkRect2D* pDiscardRectangles)
2783 {
2784 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2785 struct radv_cmd_state *state = &cmd_buffer->state;
2786 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2787
2788 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2789 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2790
2791 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2792 pDiscardRectangles, discardRectangleCount);
2793
2794 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2795 }
2796
2797 void radv_CmdExecuteCommands(
2798 VkCommandBuffer commandBuffer,
2799 uint32_t commandBufferCount,
2800 const VkCommandBuffer* pCmdBuffers)
2801 {
2802 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2803
2804 assert(commandBufferCount > 0);
2805
2806 /* Emit pending flushes on primary prior to executing secondary */
2807 si_emit_cache_flush(primary);
2808
2809 for (uint32_t i = 0; i < commandBufferCount; i++) {
2810 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2811
2812 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2813 secondary->scratch_size_needed);
2814 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2815 secondary->compute_scratch_size_needed);
2816
2817 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2818 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2819 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2820 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2821 if (secondary->tess_rings_needed)
2822 primary->tess_rings_needed = true;
2823 if (secondary->sample_positions_needed)
2824 primary->sample_positions_needed = true;
2825
2826 if (secondary->ring_offsets_idx != -1) {
2827 if (primary->ring_offsets_idx == -1)
2828 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2829 else
2830 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2831 }
2832 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2833
2834
2835 /* When the secondary command buffer is compute only we don't
2836 * need to re-emit the current graphics pipeline.
2837 */
2838 if (secondary->state.emitted_pipeline) {
2839 primary->state.emitted_pipeline =
2840 secondary->state.emitted_pipeline;
2841 }
2842
2843 /* When the secondary command buffer is graphics only we don't
2844 * need to re-emit the current compute pipeline.
2845 */
2846 if (secondary->state.emitted_compute_pipeline) {
2847 primary->state.emitted_compute_pipeline =
2848 secondary->state.emitted_compute_pipeline;
2849 }
2850
2851 /* Only re-emit the draw packets when needed. */
2852 if (secondary->state.last_primitive_reset_en != -1) {
2853 primary->state.last_primitive_reset_en =
2854 secondary->state.last_primitive_reset_en;
2855 }
2856
2857 if (secondary->state.last_primitive_reset_index) {
2858 primary->state.last_primitive_reset_index =
2859 secondary->state.last_primitive_reset_index;
2860 }
2861
2862 if (secondary->state.last_ia_multi_vgt_param) {
2863 primary->state.last_ia_multi_vgt_param =
2864 secondary->state.last_ia_multi_vgt_param;
2865 }
2866
2867 primary->state.last_first_instance = secondary->state.last_first_instance;
2868 primary->state.last_num_instances = secondary->state.last_num_instances;
2869 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2870
2871 if (secondary->state.last_index_type != -1) {
2872 primary->state.last_index_type =
2873 secondary->state.last_index_type;
2874 }
2875 }
2876
2877 /* After executing commands from secondary buffers we have to dirty
2878 * some states.
2879 */
2880 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2881 RADV_CMD_DIRTY_INDEX_BUFFER |
2882 RADV_CMD_DIRTY_DYNAMIC_ALL;
2883 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2884 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2885 }
2886
2887 VkResult radv_CreateCommandPool(
2888 VkDevice _device,
2889 const VkCommandPoolCreateInfo* pCreateInfo,
2890 const VkAllocationCallbacks* pAllocator,
2891 VkCommandPool* pCmdPool)
2892 {
2893 RADV_FROM_HANDLE(radv_device, device, _device);
2894 struct radv_cmd_pool *pool;
2895
2896 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2897 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2898 if (pool == NULL)
2899 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2900
2901 if (pAllocator)
2902 pool->alloc = *pAllocator;
2903 else
2904 pool->alloc = device->alloc;
2905
2906 list_inithead(&pool->cmd_buffers);
2907 list_inithead(&pool->free_cmd_buffers);
2908
2909 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2910
2911 *pCmdPool = radv_cmd_pool_to_handle(pool);
2912
2913 return VK_SUCCESS;
2914
2915 }
2916
2917 void radv_DestroyCommandPool(
2918 VkDevice _device,
2919 VkCommandPool commandPool,
2920 const VkAllocationCallbacks* pAllocator)
2921 {
2922 RADV_FROM_HANDLE(radv_device, device, _device);
2923 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2924
2925 if (!pool)
2926 return;
2927
2928 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2929 &pool->cmd_buffers, pool_link) {
2930 radv_cmd_buffer_destroy(cmd_buffer);
2931 }
2932
2933 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2934 &pool->free_cmd_buffers, pool_link) {
2935 radv_cmd_buffer_destroy(cmd_buffer);
2936 }
2937
2938 vk_free2(&device->alloc, pAllocator, pool);
2939 }
2940
2941 VkResult radv_ResetCommandPool(
2942 VkDevice device,
2943 VkCommandPool commandPool,
2944 VkCommandPoolResetFlags flags)
2945 {
2946 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2947 VkResult result;
2948
2949 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2950 &pool->cmd_buffers, pool_link) {
2951 result = radv_reset_cmd_buffer(cmd_buffer);
2952 if (result != VK_SUCCESS)
2953 return result;
2954 }
2955
2956 return VK_SUCCESS;
2957 }
2958
2959 void radv_TrimCommandPool(
2960 VkDevice device,
2961 VkCommandPool commandPool,
2962 VkCommandPoolTrimFlagsKHR flags)
2963 {
2964 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2965
2966 if (!pool)
2967 return;
2968
2969 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2970 &pool->free_cmd_buffers, pool_link) {
2971 radv_cmd_buffer_destroy(cmd_buffer);
2972 }
2973 }
2974
2975 void radv_CmdBeginRenderPass(
2976 VkCommandBuffer commandBuffer,
2977 const VkRenderPassBeginInfo* pRenderPassBegin,
2978 VkSubpassContents contents)
2979 {
2980 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2981 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2982 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2983
2984 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2985 cmd_buffer->cs, 2048);
2986 MAYBE_UNUSED VkResult result;
2987
2988 cmd_buffer->state.framebuffer = framebuffer;
2989 cmd_buffer->state.pass = pass;
2990 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2991
2992 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2993 if (result != VK_SUCCESS)
2994 return;
2995
2996 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2997 assert(cmd_buffer->cs->cdw <= cdw_max);
2998
2999 radv_cmd_buffer_clear_subpass(cmd_buffer);
3000 }
3001
3002 void radv_CmdNextSubpass(
3003 VkCommandBuffer commandBuffer,
3004 VkSubpassContents contents)
3005 {
3006 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3007
3008 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3009
3010 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3011 2048);
3012
3013 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3014 radv_cmd_buffer_clear_subpass(cmd_buffer);
3015 }
3016
3017 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3018 {
3019 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3020 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3021 if (!pipeline->shaders[stage])
3022 continue;
3023 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3024 if (loc->sgpr_idx == -1)
3025 continue;
3026 uint32_t base_reg = pipeline->user_data_0[stage];
3027 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3028
3029 }
3030 if (pipeline->gs_copy_shader) {
3031 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3032 if (loc->sgpr_idx != -1) {
3033 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3034 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3035 }
3036 }
3037 }
3038
3039 static void
3040 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3041 uint32_t vertex_count)
3042 {
3043 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3044 radeon_emit(cmd_buffer->cs, vertex_count);
3045 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3046 S_0287F0_USE_OPAQUE(0));
3047 }
3048
3049 static void
3050 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3051 uint64_t index_va,
3052 uint32_t index_count)
3053 {
3054 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3055 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3056 radeon_emit(cmd_buffer->cs, index_va);
3057 radeon_emit(cmd_buffer->cs, index_va >> 32);
3058 radeon_emit(cmd_buffer->cs, index_count);
3059 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3060 }
3061
3062 static void
3063 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3064 bool indexed,
3065 uint32_t draw_count,
3066 uint64_t count_va,
3067 uint32_t stride)
3068 {
3069 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3070 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3071 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3072 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3073 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3074 assert(base_reg);
3075
3076 /* just reset draw state for vertex data */
3077 cmd_buffer->state.last_first_instance = -1;
3078 cmd_buffer->state.last_num_instances = -1;
3079 cmd_buffer->state.last_vertex_offset = -1;
3080
3081 if (draw_count == 1 && !count_va && !draw_id_enable) {
3082 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3083 PKT3_DRAW_INDIRECT, 3, false));
3084 radeon_emit(cs, 0);
3085 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3086 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3087 radeon_emit(cs, di_src_sel);
3088 } else {
3089 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3090 PKT3_DRAW_INDIRECT_MULTI,
3091 8, false));
3092 radeon_emit(cs, 0);
3093 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3094 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3095 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3096 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3097 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3098 radeon_emit(cs, draw_count); /* count */
3099 radeon_emit(cs, count_va); /* count_addr */
3100 radeon_emit(cs, count_va >> 32);
3101 radeon_emit(cs, stride); /* stride */
3102 radeon_emit(cs, di_src_sel);
3103 }
3104 }
3105
3106 struct radv_draw_info {
3107 /**
3108 * Number of vertices.
3109 */
3110 uint32_t count;
3111
3112 /**
3113 * Index of the first vertex.
3114 */
3115 int32_t vertex_offset;
3116
3117 /**
3118 * First instance id.
3119 */
3120 uint32_t first_instance;
3121
3122 /**
3123 * Number of instances.
3124 */
3125 uint32_t instance_count;
3126
3127 /**
3128 * First index (indexed draws only).
3129 */
3130 uint32_t first_index;
3131
3132 /**
3133 * Whether it's an indexed draw.
3134 */
3135 bool indexed;
3136
3137 /**
3138 * Indirect draw parameters resource.
3139 */
3140 struct radv_buffer *indirect;
3141 uint64_t indirect_offset;
3142 uint32_t stride;
3143
3144 /**
3145 * Draw count parameters resource.
3146 */
3147 struct radv_buffer *count_buffer;
3148 uint64_t count_buffer_offset;
3149 };
3150
3151 static void
3152 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3153 const struct radv_draw_info *info)
3154 {
3155 struct radv_cmd_state *state = &cmd_buffer->state;
3156 struct radeon_winsys *ws = cmd_buffer->device->ws;
3157 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3158
3159 if (info->indirect) {
3160 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3161 uint64_t count_va = 0;
3162
3163 va += info->indirect->offset + info->indirect_offset;
3164
3165 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3166
3167 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3168 radeon_emit(cs, 1);
3169 radeon_emit(cs, va);
3170 radeon_emit(cs, va >> 32);
3171
3172 if (info->count_buffer) {
3173 count_va = radv_buffer_get_va(info->count_buffer->bo);
3174 count_va += info->count_buffer->offset +
3175 info->count_buffer_offset;
3176
3177 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3178 }
3179
3180 if (!state->subpass->view_mask) {
3181 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3182 info->indexed,
3183 info->count,
3184 count_va,
3185 info->stride);
3186 } else {
3187 unsigned i;
3188 for_each_bit(i, state->subpass->view_mask) {
3189 radv_emit_view_index(cmd_buffer, i);
3190
3191 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3192 info->indexed,
3193 info->count,
3194 count_va,
3195 info->stride);
3196 }
3197 }
3198 } else {
3199 assert(state->pipeline->graphics.vtx_base_sgpr);
3200
3201 if (info->vertex_offset != state->last_vertex_offset ||
3202 info->first_instance != state->last_first_instance) {
3203 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3204 state->pipeline->graphics.vtx_emit_num);
3205
3206 radeon_emit(cs, info->vertex_offset);
3207 radeon_emit(cs, info->first_instance);
3208 if (state->pipeline->graphics.vtx_emit_num == 3)
3209 radeon_emit(cs, 0);
3210 state->last_first_instance = info->first_instance;
3211 state->last_vertex_offset = info->vertex_offset;
3212 }
3213
3214 if (state->last_num_instances != info->instance_count) {
3215 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3216 radeon_emit(cs, info->instance_count);
3217 state->last_num_instances = info->instance_count;
3218 }
3219
3220 if (info->indexed) {
3221 int index_size = state->index_type ? 4 : 2;
3222 uint64_t index_va;
3223
3224 index_va = state->index_va;
3225 index_va += info->first_index * index_size;
3226
3227 if (!state->subpass->view_mask) {
3228 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3229 index_va,
3230 info->count);
3231 } else {
3232 unsigned i;
3233 for_each_bit(i, state->subpass->view_mask) {
3234 radv_emit_view_index(cmd_buffer, i);
3235
3236 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3237 index_va,
3238 info->count);
3239 }
3240 }
3241 } else {
3242 if (!state->subpass->view_mask) {
3243 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3244 } else {
3245 unsigned i;
3246 for_each_bit(i, state->subpass->view_mask) {
3247 radv_emit_view_index(cmd_buffer, i);
3248
3249 radv_cs_emit_draw_packet(cmd_buffer,
3250 info->count);
3251 }
3252 }
3253 }
3254 }
3255 }
3256
3257 /*
3258 * Vega and raven have a bug which triggers if there are multiple context
3259 * register contexts active at the same time with different scissor values.
3260 *
3261 * There are two possible workarounds:
3262 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3263 * there is only ever 1 active set of scissor values at the same time.
3264 *
3265 * 2) Whenever the hardware switches contexts we have to set the scissor
3266 * registers again even if it is a noop. That way the new context gets
3267 * the correct scissor values.
3268 *
3269 * This implements option 2. radv_need_late_scissor_emission needs to
3270 * return true on affected HW if radv_emit_all_graphics_states sets
3271 * any context registers.
3272 */
3273 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3274 bool indexed_draw)
3275 {
3276 struct radv_cmd_state *state = &cmd_buffer->state;
3277
3278 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3279 return false;
3280
3281 /* Assume all state changes except these two can imply context rolls. */
3282 if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3283 RADV_CMD_DIRTY_VERTEX_BUFFER |
3284 RADV_CMD_DIRTY_PIPELINE))
3285 return true;
3286
3287 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3288 return true;
3289
3290 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3291 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3292 return true;
3293
3294 return false;
3295 }
3296
3297 static void
3298 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3299 const struct radv_draw_info *info)
3300 {
3301 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3302
3303 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3304 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3305 radv_emit_rbplus_state(cmd_buffer);
3306
3307 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3308 radv_emit_graphics_pipeline(cmd_buffer);
3309
3310 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3311 radv_emit_framebuffer_state(cmd_buffer);
3312
3313 if (info->indexed) {
3314 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3315 radv_emit_index_buffer(cmd_buffer);
3316 } else {
3317 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3318 * so the state must be re-emitted before the next indexed
3319 * draw.
3320 */
3321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3322 cmd_buffer->state.last_index_type = -1;
3323 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3324 }
3325 }
3326
3327 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3328
3329 radv_emit_draw_registers(cmd_buffer, info->indexed,
3330 info->instance_count > 1, info->indirect,
3331 info->indirect ? 0 : info->count);
3332
3333 if (late_scissor_emission)
3334 radv_emit_scissor(cmd_buffer);
3335 }
3336
3337 static void
3338 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3339 const struct radv_draw_info *info)
3340 {
3341 bool has_prefetch =
3342 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3343 bool pipeline_is_dirty =
3344 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3345 cmd_buffer->state.pipeline &&
3346 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3347
3348 MAYBE_UNUSED unsigned cdw_max =
3349 radeon_check_space(cmd_buffer->device->ws,
3350 cmd_buffer->cs, 4096);
3351
3352 /* Use optimal packet order based on whether we need to sync the
3353 * pipeline.
3354 */
3355 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3356 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3357 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3358 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3359 /* If we have to wait for idle, set all states first, so that
3360 * all SET packets are processed in parallel with previous draw
3361 * calls. Then upload descriptors, set shader pointers, and
3362 * draw, and prefetch at the end. This ensures that the time
3363 * the CUs are idle is very short. (there are only SET_SH
3364 * packets between the wait and the draw)
3365 */
3366 radv_emit_all_graphics_states(cmd_buffer, info);
3367 si_emit_cache_flush(cmd_buffer);
3368 /* <-- CUs are idle here --> */
3369
3370 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3371
3372 radv_emit_draw_packets(cmd_buffer, info);
3373 /* <-- CUs are busy here --> */
3374
3375 /* Start prefetches after the draw has been started. Both will
3376 * run in parallel, but starting the draw first is more
3377 * important.
3378 */
3379 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3380 radv_emit_prefetch_L2(cmd_buffer,
3381 cmd_buffer->state.pipeline, false);
3382 }
3383 } else {
3384 /* If we don't wait for idle, start prefetches first, then set
3385 * states, and draw at the end.
3386 */
3387 si_emit_cache_flush(cmd_buffer);
3388
3389 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3390 /* Only prefetch the vertex shader and VBO descriptors
3391 * in order to start the draw as soon as possible.
3392 */
3393 radv_emit_prefetch_L2(cmd_buffer,
3394 cmd_buffer->state.pipeline, true);
3395 }
3396
3397 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3398
3399 radv_emit_all_graphics_states(cmd_buffer, info);
3400 radv_emit_draw_packets(cmd_buffer, info);
3401
3402 /* Prefetch the remaining shaders after the draw has been
3403 * started.
3404 */
3405 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3406 radv_emit_prefetch_L2(cmd_buffer,
3407 cmd_buffer->state.pipeline, false);
3408 }
3409 }
3410
3411 assert(cmd_buffer->cs->cdw <= cdw_max);
3412 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3413 }
3414
3415 void radv_CmdDraw(
3416 VkCommandBuffer commandBuffer,
3417 uint32_t vertexCount,
3418 uint32_t instanceCount,
3419 uint32_t firstVertex,
3420 uint32_t firstInstance)
3421 {
3422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3423 struct radv_draw_info info = {};
3424
3425 info.count = vertexCount;
3426 info.instance_count = instanceCount;
3427 info.first_instance = firstInstance;
3428 info.vertex_offset = firstVertex;
3429
3430 radv_draw(cmd_buffer, &info);
3431 }
3432
3433 void radv_CmdDrawIndexed(
3434 VkCommandBuffer commandBuffer,
3435 uint32_t indexCount,
3436 uint32_t instanceCount,
3437 uint32_t firstIndex,
3438 int32_t vertexOffset,
3439 uint32_t firstInstance)
3440 {
3441 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3442 struct radv_draw_info info = {};
3443
3444 info.indexed = true;
3445 info.count = indexCount;
3446 info.instance_count = instanceCount;
3447 info.first_index = firstIndex;
3448 info.vertex_offset = vertexOffset;
3449 info.first_instance = firstInstance;
3450
3451 radv_draw(cmd_buffer, &info);
3452 }
3453
3454 void radv_CmdDrawIndirect(
3455 VkCommandBuffer commandBuffer,
3456 VkBuffer _buffer,
3457 VkDeviceSize offset,
3458 uint32_t drawCount,
3459 uint32_t stride)
3460 {
3461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3462 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3463 struct radv_draw_info info = {};
3464
3465 info.count = drawCount;
3466 info.indirect = buffer;
3467 info.indirect_offset = offset;
3468 info.stride = stride;
3469
3470 radv_draw(cmd_buffer, &info);
3471 }
3472
3473 void radv_CmdDrawIndexedIndirect(
3474 VkCommandBuffer commandBuffer,
3475 VkBuffer _buffer,
3476 VkDeviceSize offset,
3477 uint32_t drawCount,
3478 uint32_t stride)
3479 {
3480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3481 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3482 struct radv_draw_info info = {};
3483
3484 info.indexed = true;
3485 info.count = drawCount;
3486 info.indirect = buffer;
3487 info.indirect_offset = offset;
3488 info.stride = stride;
3489
3490 radv_draw(cmd_buffer, &info);
3491 }
3492
3493 void radv_CmdDrawIndirectCountAMD(
3494 VkCommandBuffer commandBuffer,
3495 VkBuffer _buffer,
3496 VkDeviceSize offset,
3497 VkBuffer _countBuffer,
3498 VkDeviceSize countBufferOffset,
3499 uint32_t maxDrawCount,
3500 uint32_t stride)
3501 {
3502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3503 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3504 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3505 struct radv_draw_info info = {};
3506
3507 info.count = maxDrawCount;
3508 info.indirect = buffer;
3509 info.indirect_offset = offset;
3510 info.count_buffer = count_buffer;
3511 info.count_buffer_offset = countBufferOffset;
3512 info.stride = stride;
3513
3514 radv_draw(cmd_buffer, &info);
3515 }
3516
3517 void radv_CmdDrawIndexedIndirectCountAMD(
3518 VkCommandBuffer commandBuffer,
3519 VkBuffer _buffer,
3520 VkDeviceSize offset,
3521 VkBuffer _countBuffer,
3522 VkDeviceSize countBufferOffset,
3523 uint32_t maxDrawCount,
3524 uint32_t stride)
3525 {
3526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3528 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3529 struct radv_draw_info info = {};
3530
3531 info.indexed = true;
3532 info.count = maxDrawCount;
3533 info.indirect = buffer;
3534 info.indirect_offset = offset;
3535 info.count_buffer = count_buffer;
3536 info.count_buffer_offset = countBufferOffset;
3537 info.stride = stride;
3538
3539 radv_draw(cmd_buffer, &info);
3540 }
3541
3542 void radv_CmdDrawIndirectCountKHR(
3543 VkCommandBuffer commandBuffer,
3544 VkBuffer _buffer,
3545 VkDeviceSize offset,
3546 VkBuffer _countBuffer,
3547 VkDeviceSize countBufferOffset,
3548 uint32_t maxDrawCount,
3549 uint32_t stride)
3550 {
3551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3552 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3553 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3554 struct radv_draw_info info = {};
3555
3556 info.count = maxDrawCount;
3557 info.indirect = buffer;
3558 info.indirect_offset = offset;
3559 info.count_buffer = count_buffer;
3560 info.count_buffer_offset = countBufferOffset;
3561 info.stride = stride;
3562
3563 radv_draw(cmd_buffer, &info);
3564 }
3565
3566 void radv_CmdDrawIndexedIndirectCountKHR(
3567 VkCommandBuffer commandBuffer,
3568 VkBuffer _buffer,
3569 VkDeviceSize offset,
3570 VkBuffer _countBuffer,
3571 VkDeviceSize countBufferOffset,
3572 uint32_t maxDrawCount,
3573 uint32_t stride)
3574 {
3575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3576 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3577 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3578 struct radv_draw_info info = {};
3579
3580 info.indexed = true;
3581 info.count = maxDrawCount;
3582 info.indirect = buffer;
3583 info.indirect_offset = offset;
3584 info.count_buffer = count_buffer;
3585 info.count_buffer_offset = countBufferOffset;
3586 info.stride = stride;
3587
3588 radv_draw(cmd_buffer, &info);
3589 }
3590
3591 struct radv_dispatch_info {
3592 /**
3593 * Determine the layout of the grid (in block units) to be used.
3594 */
3595 uint32_t blocks[3];
3596
3597 /**
3598 * A starting offset for the grid. If unaligned is set, the offset
3599 * must still be aligned.
3600 */
3601 uint32_t offsets[3];
3602 /**
3603 * Whether it's an unaligned compute dispatch.
3604 */
3605 bool unaligned;
3606
3607 /**
3608 * Indirect compute parameters resource.
3609 */
3610 struct radv_buffer *indirect;
3611 uint64_t indirect_offset;
3612 };
3613
3614 static void
3615 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3616 const struct radv_dispatch_info *info)
3617 {
3618 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3619 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3620 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3621 struct radeon_winsys *ws = cmd_buffer->device->ws;
3622 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3623 struct radv_userdata_info *loc;
3624
3625 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3626 AC_UD_CS_GRID_SIZE);
3627
3628 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3629
3630 if (info->indirect) {
3631 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3632
3633 va += info->indirect->offset + info->indirect_offset;
3634
3635 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3636
3637 if (loc->sgpr_idx != -1) {
3638 for (unsigned i = 0; i < 3; ++i) {
3639 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3640 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3641 COPY_DATA_DST_SEL(COPY_DATA_REG));
3642 radeon_emit(cs, (va + 4 * i));
3643 radeon_emit(cs, (va + 4 * i) >> 32);
3644 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3645 + loc->sgpr_idx * 4) >> 2) + i);
3646 radeon_emit(cs, 0);
3647 }
3648 }
3649
3650 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3651 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3652 PKT3_SHADER_TYPE_S(1));
3653 radeon_emit(cs, va);
3654 radeon_emit(cs, va >> 32);
3655 radeon_emit(cs, dispatch_initiator);
3656 } else {
3657 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3658 PKT3_SHADER_TYPE_S(1));
3659 radeon_emit(cs, 1);
3660 radeon_emit(cs, va);
3661 radeon_emit(cs, va >> 32);
3662
3663 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3664 PKT3_SHADER_TYPE_S(1));
3665 radeon_emit(cs, 0);
3666 radeon_emit(cs, dispatch_initiator);
3667 }
3668 } else {
3669 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3670 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3671
3672 if (info->unaligned) {
3673 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3674 unsigned remainder[3];
3675
3676 /* If aligned, these should be an entire block size,
3677 * not 0.
3678 */
3679 remainder[0] = blocks[0] + cs_block_size[0] -
3680 align_u32_npot(blocks[0], cs_block_size[0]);
3681 remainder[1] = blocks[1] + cs_block_size[1] -
3682 align_u32_npot(blocks[1], cs_block_size[1]);
3683 remainder[2] = blocks[2] + cs_block_size[2] -
3684 align_u32_npot(blocks[2], cs_block_size[2]);
3685
3686 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3687 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3688 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3689
3690 for(unsigned i = 0; i < 3; ++i) {
3691 assert(offsets[i] % cs_block_size[i] == 0);
3692 offsets[i] /= cs_block_size[i];
3693 }
3694
3695 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3696 radeon_emit(cs,
3697 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3698 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3699 radeon_emit(cs,
3700 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3701 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3702 radeon_emit(cs,
3703 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3704 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3705
3706 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3707 }
3708
3709 if (loc->sgpr_idx != -1) {
3710 assert(!loc->indirect);
3711 assert(loc->num_sgprs == 3);
3712
3713 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3714 loc->sgpr_idx * 4, 3);
3715 radeon_emit(cs, blocks[0]);
3716 radeon_emit(cs, blocks[1]);
3717 radeon_emit(cs, blocks[2]);
3718 }
3719
3720 if (offsets[0] || offsets[1] || offsets[2]) {
3721 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3722 radeon_emit(cs, offsets[0]);
3723 radeon_emit(cs, offsets[1]);
3724 radeon_emit(cs, offsets[2]);
3725
3726 /* The blocks in the packet are not counts but end values. */
3727 for (unsigned i = 0; i < 3; ++i)
3728 blocks[i] += offsets[i];
3729 } else {
3730 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3731 }
3732
3733 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3734 PKT3_SHADER_TYPE_S(1));
3735 radeon_emit(cs, blocks[0]);
3736 radeon_emit(cs, blocks[1]);
3737 radeon_emit(cs, blocks[2]);
3738 radeon_emit(cs, dispatch_initiator);
3739 }
3740
3741 assert(cmd_buffer->cs->cdw <= cdw_max);
3742 }
3743
3744 static void
3745 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3746 {
3747 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3748 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3749 }
3750
3751 static void
3752 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3753 const struct radv_dispatch_info *info)
3754 {
3755 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3756 bool has_prefetch =
3757 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3758 bool pipeline_is_dirty = pipeline &&
3759 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3760
3761 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3762 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3763 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3764 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3765 /* If we have to wait for idle, set all states first, so that
3766 * all SET packets are processed in parallel with previous draw
3767 * calls. Then upload descriptors, set shader pointers, and
3768 * dispatch, and prefetch at the end. This ensures that the
3769 * time the CUs are idle is very short. (there are only SET_SH
3770 * packets between the wait and the draw)
3771 */
3772 radv_emit_compute_pipeline(cmd_buffer);
3773 si_emit_cache_flush(cmd_buffer);
3774 /* <-- CUs are idle here --> */
3775
3776 radv_upload_compute_shader_descriptors(cmd_buffer);
3777
3778 radv_emit_dispatch_packets(cmd_buffer, info);
3779 /* <-- CUs are busy here --> */
3780
3781 /* Start prefetches after the dispatch has been started. Both
3782 * will run in parallel, but starting the dispatch first is
3783 * more important.
3784 */
3785 if (has_prefetch && pipeline_is_dirty) {
3786 radv_emit_shader_prefetch(cmd_buffer,
3787 pipeline->shaders[MESA_SHADER_COMPUTE]);
3788 }
3789 } else {
3790 /* If we don't wait for idle, start prefetches first, then set
3791 * states, and dispatch at the end.
3792 */
3793 si_emit_cache_flush(cmd_buffer);
3794
3795 if (has_prefetch && pipeline_is_dirty) {
3796 radv_emit_shader_prefetch(cmd_buffer,
3797 pipeline->shaders[MESA_SHADER_COMPUTE]);
3798 }
3799
3800 radv_upload_compute_shader_descriptors(cmd_buffer);
3801
3802 radv_emit_compute_pipeline(cmd_buffer);
3803 radv_emit_dispatch_packets(cmd_buffer, info);
3804 }
3805
3806 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3807 }
3808
3809 void radv_CmdDispatchBase(
3810 VkCommandBuffer commandBuffer,
3811 uint32_t base_x,
3812 uint32_t base_y,
3813 uint32_t base_z,
3814 uint32_t x,
3815 uint32_t y,
3816 uint32_t z)
3817 {
3818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3819 struct radv_dispatch_info info = {};
3820
3821 info.blocks[0] = x;
3822 info.blocks[1] = y;
3823 info.blocks[2] = z;
3824
3825 info.offsets[0] = base_x;
3826 info.offsets[1] = base_y;
3827 info.offsets[2] = base_z;
3828 radv_dispatch(cmd_buffer, &info);
3829 }
3830
3831 void radv_CmdDispatch(
3832 VkCommandBuffer commandBuffer,
3833 uint32_t x,
3834 uint32_t y,
3835 uint32_t z)
3836 {
3837 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3838 }
3839
3840 void radv_CmdDispatchIndirect(
3841 VkCommandBuffer commandBuffer,
3842 VkBuffer _buffer,
3843 VkDeviceSize offset)
3844 {
3845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3846 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3847 struct radv_dispatch_info info = {};
3848
3849 info.indirect = buffer;
3850 info.indirect_offset = offset;
3851
3852 radv_dispatch(cmd_buffer, &info);
3853 }
3854
3855 void radv_unaligned_dispatch(
3856 struct radv_cmd_buffer *cmd_buffer,
3857 uint32_t x,
3858 uint32_t y,
3859 uint32_t z)
3860 {
3861 struct radv_dispatch_info info = {};
3862
3863 info.blocks[0] = x;
3864 info.blocks[1] = y;
3865 info.blocks[2] = z;
3866 info.unaligned = 1;
3867
3868 radv_dispatch(cmd_buffer, &info);
3869 }
3870
3871 void radv_CmdEndRenderPass(
3872 VkCommandBuffer commandBuffer)
3873 {
3874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3875
3876 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3877
3878 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3879
3880 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3881 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3882 radv_handle_subpass_image_transition(cmd_buffer,
3883 (VkAttachmentReference){i, layout});
3884 }
3885
3886 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3887
3888 cmd_buffer->state.pass = NULL;
3889 cmd_buffer->state.subpass = NULL;
3890 cmd_buffer->state.attachments = NULL;
3891 cmd_buffer->state.framebuffer = NULL;
3892 }
3893
3894 /*
3895 * For HTILE we have the following interesting clear words:
3896 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3897 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3898 * 0xfffffff0: Clear depth to 1.0
3899 * 0x00000000: Clear depth to 0.0
3900 */
3901 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3902 struct radv_image *image,
3903 const VkImageSubresourceRange *range,
3904 uint32_t clear_word)
3905 {
3906 assert(range->baseMipLevel == 0);
3907 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3908 unsigned layer_count = radv_get_layerCount(image, range);
3909 uint64_t size = image->surface.htile_slice_size * layer_count;
3910 uint64_t offset = image->offset + image->htile_offset +
3911 image->surface.htile_slice_size * range->baseArrayLayer;
3912 struct radv_cmd_state *state = &cmd_buffer->state;
3913
3914 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3915 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3916
3917 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3918 size, clear_word);
3919
3920 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3921
3922 /* Initialize the depth clear registers and update the ZRANGE_PRECISION
3923 * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
3924 * default). This is only needed whean clearing Z to 0.0f.
3925 */
3926 if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
3927 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3928 VkClearDepthStencilValue value = {};
3929
3930 if (vk_format_is_stencil(image->vk_format))
3931 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3932
3933 radv_set_depth_clear_regs(cmd_buffer, image, value, aspects);
3934 }
3935 }
3936
3937 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3938 struct radv_image *image,
3939 VkImageLayout src_layout,
3940 VkImageLayout dst_layout,
3941 unsigned src_queue_mask,
3942 unsigned dst_queue_mask,
3943 const VkImageSubresourceRange *range,
3944 VkImageAspectFlags pending_clears)
3945 {
3946 if (!radv_image_has_htile(image))
3947 return;
3948
3949 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3950 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3951 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3952 cmd_buffer->state.render_area.extent.width == image->info.width &&
3953 cmd_buffer->state.render_area.extent.height == image->info.height) {
3954 /* The clear will initialize htile. */
3955 return;
3956 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3957 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3958 /* TODO: merge with the clear if applicable */
3959 radv_initialize_htile(cmd_buffer, image, range, 0);
3960 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3961 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3962 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3963 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3964 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3965 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3966 VkImageSubresourceRange local_range = *range;
3967 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3968 local_range.baseMipLevel = 0;
3969 local_range.levelCount = 1;
3970
3971 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3972 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3973
3974 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3975
3976 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3977 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3978 }
3979 }
3980
3981 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3982 struct radv_image *image, uint32_t value)
3983 {
3984 struct radv_cmd_state *state = &cmd_buffer->state;
3985
3986 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3987 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3988
3989 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3990
3991 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3992 }
3993
3994 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3995 struct radv_image *image, uint32_t value)
3996 {
3997 struct radv_cmd_state *state = &cmd_buffer->state;
3998
3999 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4000 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4001
4002 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4003
4004 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4005 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4006 }
4007
4008 /**
4009 * Initialize DCC/FMASK/CMASK metadata for a color image.
4010 */
4011 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4012 struct radv_image *image,
4013 VkImageLayout src_layout,
4014 VkImageLayout dst_layout,
4015 unsigned src_queue_mask,
4016 unsigned dst_queue_mask)
4017 {
4018 if (radv_image_has_cmask(image)) {
4019 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4020
4021 /* TODO: clarify this. */
4022 if (radv_image_has_fmask(image)) {
4023 value = 0xccccccccu;
4024 }
4025
4026 radv_initialise_cmask(cmd_buffer, image, value);
4027 }
4028
4029 if (radv_image_has_dcc(image)) {
4030 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4031
4032 if (radv_layout_dcc_compressed(image, dst_layout,
4033 dst_queue_mask)) {
4034 value = 0x20202020u;
4035 }
4036
4037 radv_initialize_dcc(cmd_buffer, image, value);
4038 }
4039 }
4040
4041 /**
4042 * Handle color image transitions for DCC/FMASK/CMASK.
4043 */
4044 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4045 struct radv_image *image,
4046 VkImageLayout src_layout,
4047 VkImageLayout dst_layout,
4048 unsigned src_queue_mask,
4049 unsigned dst_queue_mask,
4050 const VkImageSubresourceRange *range)
4051 {
4052 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4053 radv_init_color_image_metadata(cmd_buffer, image,
4054 src_layout, dst_layout,
4055 src_queue_mask, dst_queue_mask);
4056 return;
4057 }
4058
4059 if (radv_image_has_dcc(image)) {
4060 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4061 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4062 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4063 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4064 radv_decompress_dcc(cmd_buffer, image, range);
4065 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4066 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4067 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4068 }
4069 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4070 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4071 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4072 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4073 }
4074 }
4075 }
4076
4077 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4078 struct radv_image *image,
4079 VkImageLayout src_layout,
4080 VkImageLayout dst_layout,
4081 uint32_t src_family,
4082 uint32_t dst_family,
4083 const VkImageSubresourceRange *range,
4084 VkImageAspectFlags pending_clears)
4085 {
4086 if (image->exclusive && src_family != dst_family) {
4087 /* This is an acquire or a release operation and there will be
4088 * a corresponding release/acquire. Do the transition in the
4089 * most flexible queue. */
4090
4091 assert(src_family == cmd_buffer->queue_family_index ||
4092 dst_family == cmd_buffer->queue_family_index);
4093
4094 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4095 return;
4096
4097 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4098 (src_family == RADV_QUEUE_GENERAL ||
4099 dst_family == RADV_QUEUE_GENERAL))
4100 return;
4101 }
4102
4103 unsigned src_queue_mask =
4104 radv_image_queue_family_mask(image, src_family,
4105 cmd_buffer->queue_family_index);
4106 unsigned dst_queue_mask =
4107 radv_image_queue_family_mask(image, dst_family,
4108 cmd_buffer->queue_family_index);
4109
4110 if (vk_format_is_depth(image->vk_format)) {
4111 radv_handle_depth_image_transition(cmd_buffer, image,
4112 src_layout, dst_layout,
4113 src_queue_mask, dst_queue_mask,
4114 range, pending_clears);
4115 } else {
4116 radv_handle_color_image_transition(cmd_buffer, image,
4117 src_layout, dst_layout,
4118 src_queue_mask, dst_queue_mask,
4119 range);
4120 }
4121 }
4122
4123 void radv_CmdPipelineBarrier(
4124 VkCommandBuffer commandBuffer,
4125 VkPipelineStageFlags srcStageMask,
4126 VkPipelineStageFlags destStageMask,
4127 VkBool32 byRegion,
4128 uint32_t memoryBarrierCount,
4129 const VkMemoryBarrier* pMemoryBarriers,
4130 uint32_t bufferMemoryBarrierCount,
4131 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4132 uint32_t imageMemoryBarrierCount,
4133 const VkImageMemoryBarrier* pImageMemoryBarriers)
4134 {
4135 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4136 enum radv_cmd_flush_bits src_flush_bits = 0;
4137 enum radv_cmd_flush_bits dst_flush_bits = 0;
4138
4139 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4140 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4141 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4142 NULL);
4143 }
4144
4145 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4146 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4147 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4148 NULL);
4149 }
4150
4151 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4152 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4153 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4154 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4155 image);
4156 }
4157
4158 radv_stage_flush(cmd_buffer, srcStageMask);
4159 cmd_buffer->state.flush_bits |= src_flush_bits;
4160
4161 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4162 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4163 radv_handle_image_transition(cmd_buffer, image,
4164 pImageMemoryBarriers[i].oldLayout,
4165 pImageMemoryBarriers[i].newLayout,
4166 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4167 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4168 &pImageMemoryBarriers[i].subresourceRange,
4169 0);
4170 }
4171
4172 cmd_buffer->state.flush_bits |= dst_flush_bits;
4173 }
4174
4175
4176 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4177 struct radv_event *event,
4178 VkPipelineStageFlags stageMask,
4179 unsigned value)
4180 {
4181 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4182 uint64_t va = radv_buffer_get_va(event->bo);
4183
4184 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4185
4186 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4187
4188 /* TODO: this is overkill. Probably should figure something out from
4189 * the stage mask. */
4190
4191 si_cs_emit_write_event_eop(cs,
4192 cmd_buffer->state.predicating,
4193 cmd_buffer->device->physical_device->rad_info.chip_class,
4194 radv_cmd_buffer_uses_mec(cmd_buffer),
4195 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4196 1, va, 2, value);
4197
4198 assert(cmd_buffer->cs->cdw <= cdw_max);
4199 }
4200
4201 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4202 VkEvent _event,
4203 VkPipelineStageFlags stageMask)
4204 {
4205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4206 RADV_FROM_HANDLE(radv_event, event, _event);
4207
4208 write_event(cmd_buffer, event, stageMask, 1);
4209 }
4210
4211 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4212 VkEvent _event,
4213 VkPipelineStageFlags stageMask)
4214 {
4215 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4216 RADV_FROM_HANDLE(radv_event, event, _event);
4217
4218 write_event(cmd_buffer, event, stageMask, 0);
4219 }
4220
4221 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4222 uint32_t eventCount,
4223 const VkEvent* pEvents,
4224 VkPipelineStageFlags srcStageMask,
4225 VkPipelineStageFlags dstStageMask,
4226 uint32_t memoryBarrierCount,
4227 const VkMemoryBarrier* pMemoryBarriers,
4228 uint32_t bufferMemoryBarrierCount,
4229 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4230 uint32_t imageMemoryBarrierCount,
4231 const VkImageMemoryBarrier* pImageMemoryBarriers)
4232 {
4233 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4234 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4235
4236 for (unsigned i = 0; i < eventCount; ++i) {
4237 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4238 uint64_t va = radv_buffer_get_va(event->bo);
4239
4240 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4241
4242 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4243
4244 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4245 assert(cmd_buffer->cs->cdw <= cdw_max);
4246 }
4247
4248
4249 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4250 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4251
4252 radv_handle_image_transition(cmd_buffer, image,
4253 pImageMemoryBarriers[i].oldLayout,
4254 pImageMemoryBarriers[i].newLayout,
4255 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4256 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4257 &pImageMemoryBarriers[i].subresourceRange,
4258 0);
4259 }
4260
4261 /* TODO: figure out how to do memory barriers without waiting */
4262 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4263 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4264 RADV_CMD_FLAG_INV_VMEM_L1 |
4265 RADV_CMD_FLAG_INV_SMEM_L1;
4266 }
4267
4268
4269 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4270 uint32_t deviceMask)
4271 {
4272 /* No-op */
4273 }